ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #13898 from RyoheiHagimoto/add_can_to_grmango 

Adding CAN function to GR-MANGO
pull/13995/head
Martin Kojtal 2020-12-07 11:03:27 +00:00 committed by GitHub
parent 660b964bb2 edbcb78bb4
commit 0fa43ca750
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
98 changed files with 8035 additions and 344 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PeripheralPins.c
View File

@ -210,3 +210,16 @@ const PinMap PinMap_PWM[] = {
{NC, NC, 0}
};
/************CAN***************/
const PinMap PinMap_CAN_RD[] = {
{P1_1, CAN_0, 4},
{P2_0, CAN_1, 4},
{NC, NC, 0}
};
const PinMap PinMap_CAN_TD[] = {
{P1_3, CAN_0, 4},
{P2_2, CAN_1, 4},
{NC, NC, 0}
};

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/adc_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/bsc_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ceu_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

8
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/cpg_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/
@ -172,8 +172,6 @@
#define CPG_SYSCR3_RRAMWE3_SHIFT (3u)
#define CPG_STBCR3_MSTP30 (0x01u)
#define CPG_STBCR3_MSTP30_SHIFT (0u)
#define CPG_STBCR3_MSTP31 (0x02u)
#define CPG_STBCR3_MSTP31_SHIFT (1u)
#define CPG_STBCR3_MSTP32 (0x04u)
#define CPG_STBCR3_MSTP32_SHIFT (2u)
#define CPG_STBCR3_MSTP33 (0x08u)

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/csi2link_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/dmac_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/drpk_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/drw_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/edmac_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/eptpc_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/etherc_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/gpio_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/gpt_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/hyper_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

14
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/imr2_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/
@ -84,15 +84,15 @@
#define IMR2_IMR_INM_SHIFT (2u)
#define IMR2_DLPR_DLP (0xFFFFFFFFu)
#define IMR2_DLPR_DLP_SHIFT (0u)
#define IMR2_DLSAR_DLSA (0xFFFFFFC0u)
#define IMR2_DLSAR_DLSA (0xFFFFFFF8u)
#define IMR2_DLSAR_DLSA_SHIFT (3u)
#define IMR2_DSAR_DSA (0xFFFFFC00u)
#define IMR2_DSAR_DSA (0xFFFFFFE0u)
#define IMR2_DSAR_DSA_SHIFT (5u)
#define IMR2_DSTR_DST (0x00003FFFu)
#define IMR2_DSTR_DST_SHIFT (0u)
#define IMR2_DSAR2_DSA2 (0xFFFFFC00u)
#define IMR2_DSAR2_DSA2 (0xFFFFFFE0u)
#define IMR2_DSAR2_DSA2_SHIFT (5u)
#define IMR2_DLSAR2_DLSA2 (0xFFFFFFC0u)
#define IMR2_DLSAR2_DLSA2 (0xFFFFFFF8u)
#define IMR2_DLSAR2_DLSA2_SHIFT (3u)
#define IMR2_TRIMR_TME (0x00000001u)
#define IMR2_TRIMR_TME_SHIFT (0u)

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/intc_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/irda_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/jcu_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/lvds_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

10
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/mtu_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/
@ -298,8 +298,8 @@
#define MTU_NFCRC_NFCEN_SHIFT (2u)
#define MTU_NFCRC_NFDEN (0x08u)
#define MTU_NFCRC_NFDEN_SHIFT (3u)
#define MTU_NFCRC_NFCSC (0x30u)
#define MTU_NFCRC_NFCSC_SHIFT (4u)
#define MTU_NFCRC_NFCS (0x30u)
#define MTU_NFCRC_NFCS_SHIFT (4u)
#define MTU_TCR_TPSC (0x07u)
#define MTU_TCR_TPSC_SHIFT (0u)
#define MTU_TCR_CKEG (0x18u)

8
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/nandc_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/
@ -160,7 +160,7 @@
#define NANDC_DATA_REG_DATA_REG_SHIFT (0u)
#define NANDC_DATA_REG_SIZE_DATA_REG_SIZE (0x00000003u)
#define NANDC_DATA_REG_SIZE_DATA_REG_SIZE_SHIFT (0u)
#define NANDC_DEV0_PTR_PTR_ADDR (0x00000FF0u)
#define NANDC_DEV0_PTR_PTR_ADDR (0x00000FFCu)
#define NANDC_DEV0_PTR_PTR_ADDR_SHIFT (2u)
#define NANDC_DMA_ADDR_L_DMA_ADDR_L (0xFFFFFFFFu)
#define NANDC_DMA_ADDR_L_DMA_ADDR_L_SHIFT (0u)

10
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/octa_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/
@ -108,10 +108,6 @@
#define OCTA_DRCSTR_DVRDHI0_SHIFT (11u)
#define OCTA_DRCSTR_DVRDLO0 (0x0000C000u)
#define OCTA_DRCSTR_DVRDLO0_SHIFT (14u)
#define OCTA_DRCSTR_CTRW1 (0x007F0000u)
#define OCTA_DRCSTR_CTRW1_SHIFT (16u)
#define OCTA_DRCSTR_CTR1 (0x00800000u)
#define OCTA_DRCSTR_CTR1_SHIFT (23u)
#define OCTA_DRCSTR_DVRDCMD1 (0x07000000u)
#define OCTA_DRCSTR_DVRDCMD1_SHIFT (24u)
#define OCTA_DRCSTR_DVRDHI1 (0x38000000u)

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ostm_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/pl310_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/pmg_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/poe3_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/poeg_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/prr_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ptpedmac_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rcan_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

22
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rcanfd_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/
@ -1822,14 +1822,6 @@
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE0_SHIFT (8u)
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE1 (0x00000200u)
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE1_SHIFT (9u)
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE2 (0x00000400u)
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE2_SHIFT (10u)
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE3 (0x00000800u)
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE3_SHIFT (11u)
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE4 (0x00001000u)
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE4_SHIFT (12u)
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE5 (0x00002000u)
#define RCANFD_RSCFD0CFDCDTCT_CFDMAE5_SHIFT (13u)
#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS0 (0x00000001u)
#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS0_SHIFT (0u)
#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS1 (0x00000002u)
@ -1850,14 +1842,6 @@
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS0_SHIFT (8u)
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS1 (0x00000200u)
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS1_SHIFT (9u)
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS2 (0x00000400u)
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS2_SHIFT (10u)
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS3 (0x00000800u)
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS3_SHIFT (11u)
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS4 (0x00001000u)
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS4_SHIFT (12u)
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS5 (0x00002000u)
#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS5_SHIFT (13u)
#define RCANFD_RSCFD0CFDGRMCFG_RCMC (0x00000001u)
#define RCANFD_RSCFD0CFDGRMCFG_RCMC_SHIFT (0u)
#define RCANFD_RSCFD0CFDC0DCFG_DBRP (0x000000FFu)

12
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/riic_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/
@ -178,19 +178,19 @@
#define RIIC_ICSR2_TDRE_SHIFT (7u)
#define RIIC_ICSAR0_SVA0 (0x00000001u)
#define RIIC_ICSAR0_SVA0_SHIFT (0u)
#define RIIC_ICSAR0_SVA (0x000003FCu)
#define RIIC_ICSAR0_SVA (0x000003FEu)
#define RIIC_ICSAR0_SVA_SHIFT (1u)
#define RIIC_ICSAR0_FS0 (0x00008000u)
#define RIIC_ICSAR0_FS0_SHIFT (15u)
#define RIIC_ICSAR1_SVA0 (0x00000001u)
#define RIIC_ICSAR1_SVA0_SHIFT (0u)
#define RIIC_ICSAR1_SVA (0x000003FCu)
#define RIIC_ICSAR1_SVA (0x000003FEu)
#define RIIC_ICSAR1_SVA_SHIFT (1u)
#define RIIC_ICSAR1_FS1 (0x00008000u)
#define RIIC_ICSAR1_FS1_SHIFT (15u)
#define RIIC_ICSAR2_SVA0 (0x00000001u)
#define RIIC_ICSAR2_SVA0_SHIFT (0u)
#define RIIC_ICSAR2_SVA (0x000003FCu)
#define RIIC_ICSAR2_SVA (0x000003FEu)
#define RIIC_ICSAR2_SVA_SHIFT (1u)
#define RIIC_ICSAR2_FS2 (0x00008000u)
#define RIIC_ICSAR2_FS2_SHIFT (15u)

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rspi_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

24
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rtc_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/
@ -172,27 +172,27 @@
#define RTC_RADJ_PMADJ_SHIFT (6u)
#define RTC_BCNT0_BCNT (0xFFu)
#define RTC_BCNT0_BCNT_SHIFT (0u)
#define RTC_BCNT1_BCNT (0x00u)
#define RTC_BCNT1_BCNT (0xFFu)
#define RTC_BCNT1_BCNT_SHIFT (0u)
#define RTC_BCNT2_BCNT (0x00u)
#define RTC_BCNT2_BCNT (0xFFu)
#define RTC_BCNT2_BCNT_SHIFT (0u)
#define RTC_BCNT3_BCNT (0x00u)
#define RTC_BCNT3_BCNT (0xFFu)
#define RTC_BCNT3_BCNT_SHIFT (0u)
#define RTC_BCNT0AR_BCNTAR (0xFFu)
#define RTC_BCNT0AR_BCNTAR_SHIFT (0u)
#define RTC_BCNT1AR_BCNTAR (0x00u)
#define RTC_BCNT1AR_BCNTAR (0xFFu)
#define RTC_BCNT1AR_BCNTAR_SHIFT (0u)
#define RTC_BCNT2AR_BCNTAR (0x00u)
#define RTC_BCNT2AR_BCNTAR (0xFFu)
#define RTC_BCNT2AR_BCNTAR_SHIFT (0u)
#define RTC_BCNT3AR_BCNTAR (0x00u)
#define RTC_BCNT3AR_BCNTAR (0xFFu)
#define RTC_BCNT3AR_BCNTAR_SHIFT (0u)
#define RTC_BCNT0AER_ENB (0xFFu)
#define RTC_BCNT0AER_ENB_SHIFT (0u)
#define RTC_BCNT1AER_ENB (0x00u)
#define RTC_BCNT1AER_ENB (0xFFu)
#define RTC_BCNT1AER_ENB_SHIFT (0u)
#define RTC_BCNT2AER_ENB (0x0000u)
#define RTC_BCNT2AER_ENB (0x00FFu)
#define RTC_BCNT2AER_ENB_SHIFT (0u)
#define RTC_BCNT3AER_ENB (0x00u)
#define RTC_BCNT3AER_ENB (0xFFu)
#define RTC_BCNT3AER_ENB_SHIFT (0u)
#endif

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/scifa_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/scim_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

32
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/sdmmc_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/
@ -48,7 +48,7 @@
#define SDMMC_SCC_DTCNTL_TAPEN (0x00000001u)
#define SDMMC_SCC_DTCNTL_TAPEN_SHIFT (0u)
#define SDMMC_SCC_DTCNTL_TAPNUM (0x00000000u)
#define SDMMC_SCC_DTCNTL_TAPNUM (0x00FF0000u)
#define SDMMC_SCC_DTCNTL_TAPNUM_SHIFT (16u)
#define SDMMC_SCC_TAPSET_TAPSET (0x000000FFu)
#define SDMMC_SCC_TAPSET_TAPSET_SHIFT (0u)
@ -74,7 +74,7 @@
#define SDMMC_SCC_SMPCMP_CMPNGD_SHIFT (0u)
#define SDMMC_SCC_SMPCMP_CMPNGU (0x01FF0000u)
#define SDMMC_SCC_SMPCMP_CMPNGU_SHIFT (16u)
#define SDMMC_SD_CMD_CF (0x0000000000000000u)
#define SDMMC_SD_CMD_CF (0x000000000000003Fu)
#define SDMMC_SD_CMD_CF_SHIFT (0u)
#define SDMMC_SD_CMD_C0 (0x0000000000000040u)
#define SDMMC_SD_CMD_C0_SHIFT (6u)
@ -96,9 +96,9 @@
#define SDMMC_SD_CMD_MD6_SHIFT (14u)
#define SDMMC_SD_CMD_MD7 (0x0000000000008000u)
#define SDMMC_SD_CMD_MD7_SHIFT (15u)
#define SDMMC_SD_ARG_CF (0x00000000FFFFFF00u)
#define SDMMC_SD_ARG_CF (0x00000000FFFFFFFFu)
#define SDMMC_SD_ARG_CF_SHIFT (0u)
#define SDMMC_SD_ARG1_CF (0x0000000000000000u)
#define SDMMC_SD_ARG1_CF (0x000000000000FFFFu)
#define SDMMC_SD_ARG1_CF_SHIFT (0u)
#define SDMMC_SD_STOP_STP (0x0000000000000001u)
#define SDMMC_SD_STOP_STP_SHIFT (0u)
@ -110,21 +110,21 @@
#define SDMMC_SD_STOP_HPIMODE_SHIFT (17u)
#define SDMMC_SD_SECCNT_CNT (0x00000000FFFFFFFFu)
#define SDMMC_SD_SECCNT_CNT_SHIFT (0u)
#define SDMMC_SD_RSP10_R (0xFFFFFFFFFFFFFF00u)
#define SDMMC_SD_RSP10_R (0xFFFFFFFFFFFFFFFFu)
#define SDMMC_SD_RSP10_R_SHIFT (0u)
#define SDMMC_SD_RSP1_R (0x0000000000000000u)
#define SDMMC_SD_RSP1_R (0x000000000000FFFFu)
#define SDMMC_SD_RSP1_R_SHIFT (0u)
#define SDMMC_SD_RSP32_R (0x0000000000000000u)
#define SDMMC_SD_RSP32_R (0x00000000FFFFFFFFu)
#define SDMMC_SD_RSP32_R_SHIFT (0u)
#define SDMMC_SD_RSP3_R (0x0000000000000000u)
#define SDMMC_SD_RSP3_R (0x000000000000FFFFu)
#define SDMMC_SD_RSP3_R_SHIFT (0u)
#define SDMMC_SD_RSP54_R (0x0000000000000000u)
#define SDMMC_SD_RSP54_R (0x00FFFFFFFFFFFFFFu)
#define SDMMC_SD_RSP54_R_SHIFT (0u)
#define SDMMC_SD_RSP5_R (0x0000000000000000u)
#define SDMMC_SD_RSP5_R (0x000000000000FFFFu)
#define SDMMC_SD_RSP5_R_SHIFT (0u)
#define SDMMC_SD_RSP76_R (0x0000000000000000u)
#define SDMMC_SD_RSP76_R (0x0000000000FFFFFFu)
#define SDMMC_SD_RSP76_R_SHIFT (0u)
#define SDMMC_SD_RSP7_R (0x0000000000000000u)
#define SDMMC_SD_RSP7_R (0x00000000000000FFu)
#define SDMMC_SD_RSP7_R_SHIFT (0u)
#define SDMMC_SD_INFO1_INFO0 (0x0000000000000001u)
#define SDMMC_SD_INFO1_INFO0_SHIFT (0u)
@ -356,7 +356,7 @@
#define SDMMC_DM_CM_INFO2_MASK_DTRANERR0_MASK_SHIFT (16u)
#define SDMMC_DM_CM_INFO2_MASK_DTRANERR1_MASK (0x0000000000020000u)
#define SDMMC_DM_CM_INFO2_MASK_DTRANERR1_MASK_SHIFT (17u)
#define SDMMC_DM_DTRAN_ADDR_DADDR (0x00000000FFFFFFC0u)
#define SDMMC_DM_DTRAN_ADDR_DADDR (0x00000000FFFFFFF8u)
#define SDMMC_DM_DTRAN_ADDR_DADDR_SHIFT (3u)
#endif

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/spdif_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/spibsc_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/sprite_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ssif_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/usb_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/vdc6_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/vin_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/wdt_iobitmask.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO bitmask header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/adc_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/bsc_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ceu_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

8
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/cpg_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/
@ -226,7 +226,7 @@ struct st_cpg {
unsigned char BYTE;
struct {
unsigned char MSTP30: 1;
unsigned char MSTP31: 1;
unsigned char : 1;
unsigned char MSTP32: 1;
unsigned char MSTP33: 1;
unsigned char MSTP34: 1;

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/csi2link_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/dmac_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/drpk_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/drw_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/edmac_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/eptpc_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/etherc_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/gpio_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/gpt_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/hyper_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/imr_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/intc_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/irda_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/jcu_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/lvds_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

8
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/mtu_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/
@ -453,7 +453,7 @@ struct st_mtu0 {
unsigned char NFBEN: 1;
unsigned char NFCEN: 1;
unsigned char NFDEN: 1;
unsigned char NFCSC: 2;
unsigned char NFCS: 2;
unsigned char : 2;
} BIT;
} NFCRC;

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/nandc_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

9
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/octa_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/
@ -130,8 +130,7 @@ struct st_octa {
unsigned long DVRDCMD0: 3;
unsigned long DVRDHI0: 3;
unsigned long DVRDLO0: 2;
unsigned long CTRW1: 7;
unsigned long CTR1: 1;
unsigned long : 8;
unsigned long DVRDCMD1: 3;
unsigned long DVRDHI1: 3;
unsigned long DVRDLO1: 2;

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ostm_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/pl_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/pmg_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/poe_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/poeg_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/prr_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ptpedmac_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rcan_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

18
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rcanfd_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/
@ -2910,11 +2910,7 @@ struct st_rcanfd {
unsigned char RFDMAE7: 1;
unsigned char CFDMAE0: 1;
unsigned char CFDMAE1: 1;
unsigned char CFDMAE2: 1;
unsigned char CFDMAE3: 1;
unsigned char CFDMAE4: 1;
unsigned char CFDMAE5: 1;
unsigned char : 2;
unsigned char : 6;
unsigned char : 8;
unsigned char : 8;
} BIT;
@ -2942,11 +2938,7 @@ struct st_rcanfd {
unsigned char RFDMASTS7: 1;
unsigned char CFDMASTS0: 1;
unsigned char CFDMASTS1: 1;
unsigned char CFDMASTS2: 1;
unsigned char CFDMASTS3: 1;
unsigned char CFDMASTS4: 1;
unsigned char CFDMASTS5: 1;
unsigned char : 2;
unsigned char : 6;
unsigned char : 8;
unsigned char : 8;
} BIT;

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/riic_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rspi_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rtc_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/scifa_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/scim_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/sdmmc_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/spdif_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/spibsc_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/sprite_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ssif_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/usb_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/vdc_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/vin_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

6
targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/wdt_iodefine.h
View File

@ -18,9 +18,9 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/* Copyright (c) 2018-2020 Renesas Electronics Corporation.
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,7 +36,7 @@
* limitations under the License.
*/
/*******************************************************************************
* Rev: 2.00
* Rev: 3.01
* Description : IO define header
*******************************************************************************/

927
targets/TARGET_RENESAS/TARGET_RZ_A2XX/can_api.c Normal file
View File

@ -0,0 +1,927 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2020 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if DEVICE_CAN
#include "mbed_assert.h"
#include "can_api.h"
#include "RZ_A2_Init.h"
#include "cmsis.h"
#include "PeripheralPins.h"
#include "iodefine.h"
#include "r_typedefs.h"
#include "mbed_drv_cfg.h"
#include "rza_io_regrw.h"
#include "iobitmask.h"
#include "r_can_rz_config.h"
#include "r_can_rz_if.h"
/* RZA IO */
#define REG_32W RZA_IO_RegWrite_32
#define REG_NONSHIFT IOREG_NONSHIFT_ACCESS
#define REG_NONMASK IOREG_NONMASK_ACCESS
/* Channel */
#define CHANNEL_MAX MAX_CHANNELS
#define CAN_TX_RX 2
#define CAN_IRQ_TYPE_MAX 8
/* RX rule */
#define RXRULE_J_MAX 16
#define RXRULE_CH0_MAX CAN0_RX_RULE_NUM
#define RXRULE_CH1_MAX CAN1_RX_RULE_NUM
/* TR_FIFO */
#define TX_TRFIFO_INDEX(ch) (ch * TRFIFO_NUM_PER_CH)
#define RX_TRFIFO_INDEX(ch) (ch * TRFIFO_NUM_PER_CH) + 1
/* Normal bit rate */
#define NSS_MAX 1
#define NTSEG1_MAX 128
#define NTSEG2_MAX 32
#define N_TOTAL_TQMAX (NSS_MAX + NTSEG1_MAX + NTSEG2_MAX)
#define N_TOTAL_TQMIN 8
#define N_SAMPLE_POINT 0.666666667
#define N_SJW 3
#define N_BITRATE_DEFAULT 100000
#define N_BITRATE_MAX 1000000
/* Data bit rate */
#define DSS_MAX 1
#define DTSEG1_MAX 16
#define DTSEG2_MAX 8
#define D_TOTAL_TQMAX (DSS_MAX + DTSEG1_MAX + DTSEG2_MAX)
#define D_TOTAL_TQMIN 8
#define D_SAMPLE_POINT 0.666666667
#define D_SJW 3
#define D_CH0_BITRATE 2000000
#define D_CH1_BITRATE 2000000
/*
* RCANFD Register
*/
/* CmCTR */
#define CTR_BEIE RCANFD_RSCFD0CFDC0CTR_BEIE
#define CTR_EWIE RCANFD_RSCFD0CFDC0CTR_EWIE
#define CTR_EPIE RCANFD_RSCFD0CFDC0CTR_EPIE
#define CTR_BOEIE RCANFD_RSCFD0CFDC0CTR_BOEIE
#define CTR_BORIE RCANFD_RSCFD0CFDC0CTR_BORIE
#define CTR_OLIE RCANFD_RSCFD0CFDC0CTR_OLIE
#define CTR_BLIE RCANFD_RSCFD0CFDC0CTR_BLIE
#define CTR_ALIE RCANFD_RSCFD0CFDC0CTR_ALIE
#define CTR_TAIE RCANFD_RSCFD0CFDC0CTR_TAIE
#define CTR_IEALL (CTR_BEIE | CTR_EWIE | CTR_EPIE | CTR_BOEIE | CTR_BORIE | \
CTR_OLIE | CTR_BLIE | CTR_ALIE | CTR_TAIE)
#define CTR_EOCOIE RCANFD_RSCFD0CFDC0CTR_EOCOIE
#define CTR_SOCOIE RCANFD_RSCFD0CFDC0CTR_SOCOIE
#define CTR_TDCVFIE RCANFD_RSCFD0CFDC0CTR_TDCVFIE
#define CTR_BOM RCANFD_RSCFD0CFDC0CTR_BOM
#define CTR_ERRD RCANFD_RSCFD0CFDC0CTR_ERRD
#define CTR_CTME RCANFD_RSCFD0CFDC0CTR_CTME
#define CTR_CTMS RCANFD_RSCFD0CFDC0CTR_CTMS
#define CTR_CRCT RCANFD_RSCFD0CFDC0CTR_CRCT
#define CTR_ROM RCANFD_RSCFD0CFDC0CTR_ROM
#define CTR_CTME_SHIFT RCANFD_RSCFD0CFDC0CTR_CTME_SHIFT
#define CTR_CTMS_SHIFT RCANFD_RSCFD0CFDC0CTR_CTMS_SHIFT
#define MASK_CTR_INIT (CTR_ERRD | CTR_BOM | CTR_TDCVFIE | CTR_SOCOIE | CTR_EOCOIE | CTR_IEALL)
/* CmERFL */
#define ERFL_BEF RCANFD_RSCFD0CFDC0ERFL_BEF
#define ERFL_EWF RCANFD_RSCFD0CFDC0ERFL_EWF
#define ERFL_EPF RCANFD_RSCFD0CFDC0ERFL_EPF
#define ERFL_BOEF RCANFD_RSCFD0CFDC0ERFL_BOEF
#define ERFL_BORF RCANFD_RSCFD0CFDC0ERFL_BORF
#define ERFL_OVLF RCANFD_RSCFD0CFDC0ERFL_OVLF
#define ERFL_BLF RCANFD_RSCFD0CFDC0ERFL_BLF
#define ERFL_ALF RCANFD_RSCFD0CFDC0ERFL_ALF
#define ERFL_SERR RCANFD_RSCFD0CFDC0ERFL_SERR
#define ERFL_FERR RCANFD_RSCFD0CFDC0ERFL_FERR
#define ERFL_AERR RCANFD_RSCFD0CFDC0ERFL_AERR
#define ERFL_CERR RCANFD_RSCFD0CFDC0ERFL_CERR
#define ERFL_B1ERR RCANFD_RSCFD0CFDC0ERFL_B1ERR
#define ERFL_B0ERR RCANFD_RSCFD0CFDC0ERFL_B0ERR
#define ERFL_ADERR RCANFD_RSCFD0CFDC0ERFL_ADERR
#define ERFL_ALLERR (ERFL_SERR | ERFL_FERR | ERFL_AERR | ERFL_CERR | ERFL_B1ERR | ERFL_B0ERR | ERFL_ADERR)
/* CmFDCFG */
#define FDCFG_EOCCFG RCANFD_RSCFD0CFDC0FDCFG_EOCCFG
#define FDCFG_ESIC RCANFD_RSCFD0CFDC0FDCFG_ESIC
#define FDCFG_GWEN RCANFD_RSCFD0CFDC0FDCFG_GWEN
#define FDCFG_GWFDF RCANFD_RSCFD0CFDC0FDCFG_GWFDF
#define FDCFG_GWBRS RCANFD_RSCFD0CFDC0FDCFG_GWBRS
#define FDCFG_TMME RCANFD_RSCFD0CFDC0FDCFG_TMME
#define FDCFG_FDOE RCANFD_RSCFD0CFDC0FDCFG_FDOE
#define FDCFG_REFE RCANFD_RSCFD0CFDC0FDCFG_REFE
#define MASK_FDCFG_INIT (FDCFG_REFE | FDCFG_FDOE | FDCFG_TMME | FDCFG_GWBRS | FDCFG_GWFDF| \
FDCFG_GWEN | FDCFG_ESIC | FDCFG_EOCCFG)
/* GCTR */
#define GCTR_DEIE RCANFD_RSCFD0CFDGCTR_DEIE
#define GCTR_MEIE RCANFD_RSCFD0CFDGCTR_MEIE
#define GCTR_THLEIE RCANFD_RSCFD0CFDGCTR_THLEIE
#define GCTR_CMPOFIE RCANFD_RSCFD0CFDGCTR_CMPOFIE
#define MASK_GCTR_INIT (GCTR_DEIE | GCTR_MEIE | GCTR_THLEIE | GCTR_CMPOFIE)
/* CFCCk */
#define CFCC_CFTXIE RCANFD_RSCFD0CFDCFCC0_CFTXIE
#define CFCC_CFRXIE RCANFD_RSCFD0CFDCFCC0_CFRXIE
#define CFCC_CFE RCANFD_RSCFD0CFDCFCC0_CFE
#define MASK_CFCC_INIT ~(CFCC_CFTXIE | CFCC_CFRXIE | CFCC_CFE)
/* CFSTSk */
#define CFSTS_CFRXIF RCANFD_RSCFD0CFDCFSTS0_CFRXIF
#define CFSTS_CFTXIF RCANFD_RSCFD0CFDCFSTS0_CFTXIF
/* RFCCx*/
#define RFCC_RFIE RCANFD_RSCFD0CFDRFCC0_RFIE
#define RFCC_RFE RCANFD_RSCFD0CFDRFCC0_RFE
#define MASK_RFCC_INIT ~(RFCC_RFIE | RFCC_RFE)
/* TXQCCm */
#define TXQCC_TXQDC RCANFD_RSCFD0CFDTXQCC0_TXQDC
#define TXQCC_TXQIE RCANFD_RSCFD0CFDTXQCC0_TXQIE
#define TXQCC_TXQIM RCANFD_RSCFD0CFDTXQCC0_TXQIM
/* THLCCm */
#define THLCC_THLIE RCANFD_RSCFD0CFDTHLCC0_THLIE
#define THLCC_THLIM RCANFD_RSCFD0CFDTHLCC0_THLIM
#define THLCC_THLDTE RCANFD_RSCFD0CFDTHLCC0_THLDTE
/* GTSTCFG */
#define GTSTCFG_C0ICBCE RCANFD_RSCFD0CFDGTSTCFG_C0ICBCE
#define GTSTCFG_C1ICBCE RCANFD_RSCFD0CFDGTSTCFG_C1ICBCE
#define GTSTCFG_C0ICBCE_SHIFT RCANFD_RSCFD0CFDGTSTCFG_C0ICBCE_SHIFT
#define GTSTCFG_C1ICBCE_SHIFT RCANFD_RSCFD0CFDGTSTCFG_C1ICBCE_SHIFT
/* GTSTCTR */
#define GTSTCTR_ICBCTME RCANFD_RSCFD0CFDGTSTCTR_ICBCTME
#define GTSTCTR_ICBCTME_SHIFT RCANFD_RSCFD0CFDGTSTCTR_ICBCTME_SHIFT
/* RX buffer size */
#define RX_FIFO_MULTIPLE 8
#define RX_BUFFER_MAX (4 * ((19 * RX_FIFO_MULTIPLE) + 1)) / 4
static void can_rec_irq(uint32_t ch);
static void can_trx_irq(uint32_t ch);
static void can_err_irq(uint32_t ch);
static void can0_rec_irq(void);
static void can0_trx_irq(void);
static void can0_err_irq(void);
static void can1_rec_irq(void);
static void can1_trx_irq(void);
static void can1_err_irq(void);
static void set_normal_bitrate(uint32_t ch, int f);
static void reset_register(uint32_t ch);
static void reset_buffer(uint32_t ch);
static void get_rxrule_index(uint32_t ch, int32_t handle, uint8_t *page, uint8_t *j);
static void reconfigure_channel(uint32_t ch);
static void set_test_mode(uint32_t ch, uint32_t mode, uint32_t enable);
typedef enum {
CAN_TX = 0,
CAN_RX
} can_operation;
typedef enum {
TEST_DISABLE = 0,
TEST_ENABLE
} ctr_ctme;
typedef struct {
IRQn_Type id; /* Interrupt identifier */
IRQHandler handler; /* Interrupt handler */
} can_irq_int_t;
static const can_irq_int_t irq_tbl[CHANNEL_MAX][CAN_IRQ_TYPE_MAX] = {
{ /* ch0 */
{ CFRXI0_IRQn, can0_rec_irq }, /* RxIrq : IRQ_RX */
{ CTXI0_IRQn, can0_trx_irq }, /* TxIrq : IRQ_TX */
{ CERI0_IRQn, can0_err_irq }, /* EwIrq : IRQ_ERROR */
{ CERI0_IRQn, can0_err_irq }, /* DoIrq : IRQ_OVERRUN */
{ CERI0_IRQn, can0_err_irq }, /* WuIrq : IRQ_WAKEUP */
{ CERI0_IRQn, can0_err_irq }, /* EpIrq : IRQ_PASSIVE */
{ CERI0_IRQn, can0_err_irq }, /* AlIrq : IRQ_ARB */
{ CERI0_IRQn, can0_err_irq } /* BeIrq : IRQ_BUS */
},
{ /* ch1 */
{ CFRXI1_IRQn, can1_rec_irq }, /* RxIrq : IRQ_RX */
{ CTXI1_IRQn, can1_trx_irq }, /* TxIrq : IRQ_TX */
{ CERI1_IRQn, can1_err_irq }, /* EwIrq : IRQ_ERROR */
{ CERI1_IRQn, can1_err_irq }, /* DoIrq : IRQ_OVERRUN */
{ CERI1_IRQn, can1_err_irq }, /* WuIrq : IRQ_WAKEUP */
{ CERI1_IRQn, can1_err_irq }, /* EpIrq : IRQ_PASSIVE */
{ CERI1_IRQn, can1_err_irq }, /* EpIrq : IRQ_PASSIVE */
{ CERI1_IRQn, can1_err_irq } /* BeIrq : IRQ_BUS */
},
};
static const uint32_t irq_enable_flag_tbl[CAN_IRQ_TYPE_MAX] = {
CFCC_CFRXIE, /* RxIrq : IRQ_RX */
CFCC_CFTXIE, /* TxIrq : IRQ_TX */
CTR_EWIE, /* EwIrq : IRQ_ERROR */
CTR_OLIE, /* DoIrq : IRQ_OVERRUN */
0, /* WuIrq : IRQ_WAKEUP */
CTR_EPIE, /* EpIrq : IRQ_PASSIVE */
CTR_ALIE, /* AlIrq : IRQ_ARB */
CTR_BEIE, /* BeIrq : IRQ_BUS */
};
/* Channel bit rate configuration */
static __IO uint32_t *g_regtbl_ncfg[CHANNEL_MAX] = {
&RCANFD.RSCFD0CFDC0NCFG.LONG,
&RCANFD.RSCFD0CFDC1NCFG.LONG
};
/* Channel data bit rate configuration */
static __IO uint32_t *g_regtbl_dcfg[CHANNEL_MAX] = {
&RCANFD.RSCFD0CFDC0DCFG.LONG,
&RCANFD.RSCFD0CFDC1DCFG.LONG
};
/* Channel CANFD configuration */
static __IO uint32_t *g_regtbl_fdcfg[CHANNEL_MAX] = {
&RCANFD.RSCFD0CFDC0FDCFG.LONG,
&RCANFD.RSCFD0CFDC1FDCFG.LONG
};
static uint32_t g_fdcfg_init[CHANNEL_MAX] = {
CAN_C0FDCFG,
CAN_C1FDCFG
};
/* Channel control */
static __IO uint32_t *g_regtbl_ctr[CHANNEL_MAX] = {
&RCANFD.RSCFD0CFDC0CTR.LONG,
&RCANFD.RSCFD0CFDC1CTR.LONG
};
static uint32_t g_ctr_init[CHANNEL_MAX] = {
CAN_C0CTR,
CAN_C1CTR
};
/* Channel status */
static __IO uint32_t *g_regtbl_sts[CHANNEL_MAX] = {
&RCANFD.RSCFD0CFDC0STS.LONG,
&RCANFD.RSCFD0CFDC1STS.LONG
};
/* Channel error flag */
static __IO uint32_t *g_regtbl_erfl[CHANNEL_MAX] = {
&RCANFD.RSCFD0CFDC0ERFL.LONG,
&RCANFD.RSCFD0CFDC1ERFL.LONG
};
/* TRFIFO Configuration */
static __IO uint32_t *g_regtbl_cfcc[CHANNEL_MAX][CAN_TX_RX] = {
{ &RCANFD.RSCFD0CFDCFCC0.LONG, &RCANFD.RSCFD0CFDCFCC1.LONG }, // CAN0(TX TR_FIFO0, RX TR_FIFO1)
{ &RCANFD.RSCFD0CFDCFCC3.LONG, &RCANFD.RSCFD0CFDCFCC4.LONG } // CAN1(TX TR_FIFO3, RX TR_FIFO4)
};
static uint32_t g_cfcc_init[CHANNEL_MAX][CAN_TX_RX] = {
{ CAN_CFCC0, CAN_CFCC1 }, // CAN0(TX TR_FIFO0, RX TR_FIFO1)
{ CAN_CFCC3, CAN_CFCC4 } // CAN1(TX TR_FIFO3, RX TR_FIFO4)
};
/* TRFIFO Status */
static __IO uint32_t *g_regtbl_cfsts[CHANNEL_MAX][CAN_TX_RX] = {
{ &RCANFD.RSCFD0CFDCFSTS0.LONG, &RCANFD.RSCFD0CFDCFSTS1.LONG }, // CAN0(TX TR_FIFO0, RX TR_FIFO1)
{ &RCANFD.RSCFD0CFDCFSTS3.LONG, &RCANFD.RSCFD0CFDCFSTS4.LONG } // CAN1(TX TR_FIFO3, RX TR_FIFO4)
};
/* RXFIFO Configuration */
static __IO uint32_t *g_regtbl_rfcc[CHANNEL_MAX] = {
&RCANFD.RSCFD0CFDRFCC0.LONG, // CAN0(RX_FIFO0)
&RCANFD.RSCFD0CFDRFCC4.LONG // CAN1(RX_FIFO4)
};
static uint32_t g_rfcc_init[CHANNEL_MAX] = {
CAN_RFCC0, // CAN0(RX_FIFO0)
CAN_RFCC4 // CAN1(RX_FIFO4)
};
/* TXQCC */
static __IO uint32_t *g_regtbl_txqcc[CHANNEL_MAX] = {
&RCANFD.RSCFD0CFDTXQCC0.LONG,
&RCANFD.RSCFD0CFDTXQCC1.LONG
};
static uint32_t g_init_txqcc[CHANNEL_MAX] = {
CAN_TXQCC0,
CAN_TXQCC1
};
/* THLCC */
static __IO uint32_t *g_regtbl_thlcc[CHANNEL_MAX] = {
&RCANFD.RSCFD0CFDTHLCC0.LONG,
&RCANFD.RSCFD0CFDTHLCC1.LONG
};
static uint32_t g_init_thlcc[CHANNEL_MAX] = {
CAN_THLCC0,
CAN_THLCC1
};
/* RX rule register : ID */
static __IO uint32_t *g_regtbl_gaflid[RXRULE_J_MAX] = {
&RCANFD.RSCFD0CFDGAFLID0.LONG,
&RCANFD.RSCFD0CFDGAFLID1.LONG,
&RCANFD.RSCFD0CFDGAFLID2.LONG,
&RCANFD.RSCFD0CFDGAFLID3.LONG,
&RCANFD.RSCFD0CFDGAFLID4.LONG,
&RCANFD.RSCFD0CFDGAFLID5.LONG,
&RCANFD.RSCFD0CFDGAFLID6.LONG,
&RCANFD.RSCFD0CFDGAFLID7.LONG,
&RCANFD.RSCFD0CFDGAFLID8.LONG,
&RCANFD.RSCFD0CFDGAFLID9.LONG,
&RCANFD.RSCFD0CFDGAFLID10.LONG,
&RCANFD.RSCFD0CFDGAFLID11.LONG,
&RCANFD.RSCFD0CFDGAFLID12.LONG,
&RCANFD.RSCFD0CFDGAFLID13.LONG,
&RCANFD.RSCFD0CFDGAFLID14.LONG,
&RCANFD.RSCFD0CFDGAFLID15.LONG
};
/* RX rule register : Mask */
static __IO uint32_t *g_regtbl_gaflm[RXRULE_J_MAX] = {
&RCANFD.RSCFD0CFDGAFLM0.LONG,
&RCANFD.RSCFD0CFDGAFLM1.LONG,
&RCANFD.RSCFD0CFDGAFLM2.LONG,
&RCANFD.RSCFD0CFDGAFLM3.LONG,
&RCANFD.RSCFD0CFDGAFLM4.LONG,
&RCANFD.RSCFD0CFDGAFLM5.LONG,
&RCANFD.RSCFD0CFDGAFLM6.LONG,
&RCANFD.RSCFD0CFDGAFLM7.LONG,
&RCANFD.RSCFD0CFDGAFLM8.LONG,
&RCANFD.RSCFD0CFDGAFLM9.LONG,
&RCANFD.RSCFD0CFDGAFLM10.LONG,
&RCANFD.RSCFD0CFDGAFLM11.LONG,
&RCANFD.RSCFD0CFDGAFLM12.LONG,
&RCANFD.RSCFD0CFDGAFLM13.LONG,
&RCANFD.RSCFD0CFDGAFLM14.LONG,
&RCANFD.RSCFD0CFDGAFLM15.LONG
};
/* RX rule register : pointer1 */
static __IO uint32_t *g_regtbl_gaflp1[RXRULE_J_MAX] = {
&RCANFD.RSCFD0CFDGAFLP1_0.LONG,
&RCANFD.RSCFD0CFDGAFLP1_1.LONG,
&RCANFD.RSCFD0CFDGAFLP1_2.LONG,
&RCANFD.RSCFD0CFDGAFLP1_3.LONG,
&RCANFD.RSCFD0CFDGAFLP1_4.LONG,
&RCANFD.RSCFD0CFDGAFLP1_5.LONG,
&RCANFD.RSCFD0CFDGAFLP1_6.LONG,
&RCANFD.RSCFD0CFDGAFLP1_7.LONG,
&RCANFD.RSCFD0CFDGAFLP1_8.LONG,
&RCANFD.RSCFD0CFDGAFLP1_9.LONG,
&RCANFD.RSCFD0CFDGAFLP1_10.LONG,
&RCANFD.RSCFD0CFDGAFLP1_11.LONG,
&RCANFD.RSCFD0CFDGAFLP1_12.LONG,
&RCANFD.RSCFD0CFDGAFLP1_13.LONG,
&RCANFD.RSCFD0CFDGAFLP1_14.LONG,
&RCANFD.RSCFD0CFDGAFLP1_15.LONG
};
/* DLC to data length */
static const uint8_t dlc_to_length[16] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64
};
volatile int g_normal_bitrate[CHANNEL_MAX];
volatile int g_data_bitrate[CHANNEL_MAX] = {D_CH0_BITRATE, D_CH1_BITRATE};
uint32_t rx_buf[RX_BUFFER_MAX];
static can_irq_handler irq_handler[CHANNEL_MAX] = {NULL};
static uint32_t can_irq_id[CHANNEL_MAX] = {0};
void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
{
irq_handler[obj->ch] = handler;
can_irq_id[obj->ch] = id;
}
void can_irq_free(can_t *obj)
{
can_irq_id[obj->ch] = 0;
*g_regtbl_cfcc[obj->ch][CAN_RX] &= ~CFCC_CFRXIE;
*g_regtbl_cfcc[obj->ch][CAN_TX] &= ~CFCC_CFTXIE;
*g_regtbl_ctr[obj->ch] &= ~(CTR_EWIE | CTR_OLIE | CTR_EPIE | CTR_ALIE | CTR_BEIE);
if (CH_0 == obj->ch) {
GIC_DisableIRQ(CFRXI0_IRQn);
GIC_DisableIRQ(CTXI0_IRQn);
GIC_DisableIRQ(CERI0_IRQn);
} else {
GIC_DisableIRQ(CFRXI1_IRQn);
GIC_DisableIRQ(CTXI1_IRQn);
GIC_DisableIRQ(CERI1_IRQn);
}
}
void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
{
switch (type) {
case IRQ_RX:
if (enable) {
*g_regtbl_cfcc[obj->ch][CAN_RX] |= CFCC_CFRXIE;
} else {
*g_regtbl_cfcc[obj->ch][CAN_RX] &= ~CFCC_CFRXIE;
}
break;
case IRQ_TX:
if (enable) {
*g_regtbl_cfcc[obj->ch][CAN_TX] |= CFCC_CFTXIE;
} else {
*g_regtbl_cfcc[obj->ch][CAN_TX] &= ~CFCC_CFTXIE;
}
break;
case IRQ_ERROR:
case IRQ_OVERRUN:
case IRQ_PASSIVE:
case IRQ_ARB:
case IRQ_BUS:
if (enable) {
*g_regtbl_ctr[obj->ch] |= irq_enable_flag_tbl[type];
} else {
*g_regtbl_ctr[obj->ch] &= ~irq_enable_flag_tbl[type];
}
break;
case IRQ_WAKEUP:
/* not supported */
/* fall through */
default:
return;
}
if (enable) {
InterruptHandlerRegister(irq_tbl[obj->ch][type].id, irq_tbl[obj->ch][type].handler);
GIC_SetPriority(irq_tbl[obj->ch][type].id, 20);
GIC_EnableIRQ(irq_tbl[obj->ch][type].id);
GIC_SetConfiguration(irq_tbl[obj->ch][type].id, 1);
} else {
GIC_DisableIRQ(irq_tbl[obj->ch][type].id);
}
}
static void can_rec_irq(uint32_t ch)
{
*g_regtbl_cfsts[ch][CAN_RX] &= ~CFSTS_CFRXIF;
irq_handler[ch](can_irq_id[ch], IRQ_RX);
}
static void can_trx_irq(uint32_t ch)
{
*g_regtbl_cfsts[ch][CAN_TX] &= ~CFSTS_CFTXIF;
irq_handler[ch](can_irq_id[ch], IRQ_TX);
}
static void can_err_irq(uint32_t ch)
{
/* error warning */
if (*g_regtbl_erfl[ch] & ERFL_EWF) {
*g_regtbl_erfl[ch] &= ~ERFL_EWF;
irq_handler[ch](can_irq_id[ch], IRQ_ERROR);
}
/* over load */
if (*g_regtbl_erfl[ch] & ERFL_OVLF) {
*g_regtbl_erfl[ch] &= ~ERFL_OVLF;
irq_handler[ch](can_irq_id[ch], IRQ_OVERRUN);
}
/* error passive */
if (*g_regtbl_erfl[ch] & ERFL_EPF) {
*g_regtbl_erfl[ch] &= ~ERFL_EPF;
irq_handler[ch](can_irq_id[ch], IRQ_PASSIVE);
}
/* arbitration lost */
if (*g_regtbl_erfl[ch] & ERFL_ALF) {
*g_regtbl_erfl[ch] &= ~ERFL_ALF;
irq_handler[ch](can_irq_id[ch], IRQ_ARB);
}
/* bus error */
if (*g_regtbl_erfl[ch] & ERFL_ALLERR) {
*g_regtbl_erfl[ch] &= ~ERFL_ALLERR;
*g_regtbl_erfl[ch] &= ~ERFL_BEF;
irq_handler[ch](can_irq_id[ch], IRQ_BUS);
}
}
static void can0_rec_irq(void)
{
can_rec_irq(CAN_0);
}
static void can0_trx_irq(void)
{
can_trx_irq(CAN_0);
}
static void can0_err_irq(void)
{
can_err_irq(CAN_0);
}
static void can1_rec_irq(void)
{
can_rec_irq(CAN_1);
}
static void can1_trx_irq(void)
{
can_trx_irq(CAN_1);
}
static void can1_err_irq(void)
{
can_err_irq(CAN_1);
}
static void set_normal_bitrate(uint32_t ch, int f)
{
uint32_t clkc;
uint16_t tq_total;
uint16_t brp;
uint8_t tseg1 = 0;
uint8_t tseg2 = 0;
uint8_t sjw = 0;
/* clkc */
if (false == RZ_A2_IsClockMode0()) {
clkc = CM1_RENESAS_RZ_A2_P1_CLK / 2;
} else {
clkc = CM0_RENESAS_RZ_A2_P1_CLK / 2;
}
/* calculate NTSEG1 bit and NTSEG2 bit */
for (brp = 1; brp < 1024; brp++) {
tq_total = clkc / (f * brp);
if ((N_TOTAL_TQMIN <= tq_total) && (tq_total <= N_TOTAL_TQMAX)) {
tseg1 = tq_total * N_SAMPLE_POINT - NSS_MAX;
tseg2 = tq_total - (NSS_MAX + tseg1);
if ((NTSEG1_MAX >= tseg1) && (NTSEG2_MAX >= tseg2)) {
break;
}
}
}
/* calculate NSJW */
sjw = (tseg2 > N_SJW) ? N_SJW : tseg2;
/* set RSCAN0CmCFG register */
*g_regtbl_ncfg[ch] = ((tseg2 - 1) << 24) | ((tseg1 - 1) << 16) | ((sjw - 1) << 11) | (brp - 1);
}
static void set_data_bitrate(uint32_t ch, int f)
{
uint32_t clkc;
uint16_t tq_total;
uint16_t dbrp;
uint8_t dtseg1 = 0;
uint8_t dtseg2 = 0;
uint8_t dsjw = 0;
/* clkc */
if (false == RZ_A2_IsClockMode0()) {
clkc = CM1_RENESAS_RZ_A2_P1_CLK / 2;
} else {
clkc = CM0_RENESAS_RZ_A2_P1_CLK / 2;
}
/* calculate DTSEG1 bit and DTSEG2 bit */
for (dbrp = 1; dbrp < 256; dbrp++) {
tq_total = clkc / (f * dbrp);
if ((D_TOTAL_TQMIN <= tq_total) && (tq_total <= D_TOTAL_TQMAX)) {
dtseg1 = tq_total * D_SAMPLE_POINT - DSS_MAX;
dtseg2 = tq_total - (DSS_MAX + dtseg1);
if ((DTSEG1_MAX >= dtseg1) && (DTSEG2_MAX >= dtseg2)) {
break;
}
}
}
/* calculate DSJW */
dsjw = (dtseg2 >= D_SJW) ? D_SJW : dtseg2;
/* set RSCAN0CmDCFG register */
*g_regtbl_dcfg[ch] = ((dsjw - 1) << 24) | ((dtseg2 - 1) << 20) | ((dtseg1 - 1) << 16) | (dbrp - 1);
}
static void reset_register(uint32_t ch)
{
/* Global function setting */
REG_32W(&RCANFD.RSCFD0CFDGCFG.LONG, CAN_GCFG, REG_NONSHIFT, REG_NONMASK);
REG_32W(&RCANFD.RSCFD0CFDGFDCFG.LONG, CAN_GFDCFG, REG_NONSHIFT, REG_NONMASK);
/* Communication speed setting */
set_normal_bitrate(ch, g_normal_bitrate[ch]);
set_data_bitrate(ch, g_data_bitrate[ch]);
/* Rx rule setting */
Wrap_Can_SetRxRule();
/* Buffer setting */
reset_buffer(ch);
/* Global Error Interrupt setting */
REG_32W(&RCANFD.RSCFD0CFDGCTR.LONG, CAN_GCTR, REG_NONSHIFT, MASK_GCTR_INIT);
/* CANFD setting */
REG_32W(g_regtbl_ctr[ch], g_ctr_init[ch], REG_NONSHIFT, MASK_CTR_INIT);
REG_32W(g_regtbl_fdcfg[ch], g_fdcfg_init[ch], REG_NONSHIFT, MASK_FDCFG_INIT);
/* Global Test mode switch (reset->test) */
R_CAN_Control(UNUSED, GLOBAL_TEST);
/* Channel halt mode switch (reset->halt) */
R_CAN_Control(ch, CHANNEL_HALT);
/* Channel Restricted Operation Mode setting */
REG_32W(g_regtbl_ctr[ch], g_ctr_init[ch], REG_NONSHIFT, CTR_ROM);
}
static void reset_buffer(uint32_t ch)
{
/* TR FIFO */
REG_32W(g_regtbl_cfcc[ch][CAN_TX], g_cfcc_init[ch][CAN_TX], REG_NONSHIFT, MASK_CFCC_INIT);
REG_32W(g_regtbl_cfcc[ch][CAN_RX], g_cfcc_init[ch][CAN_RX], REG_NONSHIFT, MASK_CFCC_INIT);
/* RX FIFO */
REG_32W(g_regtbl_rfcc[ch], g_rfcc_init[ch], REG_NONSHIFT, MASK_RFCC_INIT);
/* RX buffer */
REG_32W(&RCANFD.RSCFD0CFDRMNB.LONG, CAN_RMNB, REG_NONSHIFT, REG_NONMASK);
/* TX buffer */
REG_32W(&RCANFD.RSCFD0CFDTMIEC0.LONG, CAN_TMIEC0, REG_NONSHIFT, REG_NONMASK);
/* TX queue */
REG_32W(g_regtbl_txqcc[ch], g_init_txqcc[ch], REG_NONSHIFT, (TXQCC_TXQDC | TXQCC_TXQIE | TXQCC_TXQIM));
/* TX history */
REG_32W(g_regtbl_thlcc[ch], g_init_thlcc[ch], REG_NONSHIFT, (THLCC_THLIE | THLCC_THLIM | THLCC_THLDTE));
}
static void get_rxrule_index(uint32_t ch, int32_t handle, uint8_t *page, uint8_t *j)
{
*page = (handle + (ch * CAN0_RX_RULE_NUM)) / RXRULE_J_MAX;
*j = (handle + (ch * CAN0_RX_RULE_NUM)) % RXRULE_J_MAX;
}
static void reconfigure_channel(uint32_t ch)
{
R_CAN_Control(UNUSED, GLOBAL_OPERATION);
R_CAN_Control(ch, CHANNEL_COM);
REG_32W(g_regtbl_cfcc[ch][CAN_TX], CFCC_CFE, REG_NONSHIFT, CFCC_CFE);
REG_32W(g_regtbl_cfcc[ch][CAN_RX], CFCC_CFE, REG_NONSHIFT, CFCC_CFE);
}
static void set_test_mode(uint32_t ch, uint32_t mode, uint32_t enable)
{
R_CAN_Control(ch, CHANNEL_HALT);
REG_32W(g_regtbl_ctr[ch], mode, CTR_CTMS_SHIFT, CTR_CTMS);
REG_32W(g_regtbl_ctr[ch], enable, CTR_CTME_SHIFT, CTR_CTME);
}
void can_init(can_t *obj, PinName rd, PinName td)
{
/* set default frequency */
can_init_freq(obj, rd, td, N_BITRATE_DEFAULT);
}
void can_init_freq(can_t *obj, PinName rd, PinName td, int hz)
{
/* determine the CAN to use */
uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD);
uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD);
obj->ch = pinmap_merge(can_tx, can_rx);
MBED_ASSERT((int)obj->ch != NC);
/* initialize */
CPG.STBCR3.BYTE &= ~CPG_STBCR3_MSTP32;
R_CAN_PortSet(obj->ch, ENABLE_COMMON);
R_CAN_PortSet(obj->ch, ENABLE_CHANNEL);
Wrap_Can_WaitRamInitOver();
R_CAN_Control(UNUSED, GLOBAL_RESET);
RCANFD.RSCFD0CFDGRMCFG.LONG |= RCANFD_RSCFD0CFDGRMCFG_RCMC;
R_CAN_Control(obj->ch, CHANNEL_RESET);
g_normal_bitrate[obj->ch] = hz;
reset_register(obj->ch);
reconfigure_channel(obj->ch);
/* pin out the can pins */
pinmap_pinout(rd, PinMap_CAN_RD);
pinmap_pinout(td, PinMap_CAN_TD);
}
void can_free(can_t *obj)
{
/* disable CANFD clock */
CPG.STBCR3.BYTE |= CPG_STBCR3_MSTP32;
}
int can_frequency(can_t *obj, int f)
{
int retval = 0;
/* less than normal bitrate */
if (f <= N_BITRATE_MAX) {
/* set normal bit rate */
R_CAN_Control(obj->ch, CHANNEL_RESET);
g_normal_bitrate[obj->ch] = f;
set_normal_bitrate(obj->ch, g_normal_bitrate[obj->ch]);
reconfigure_channel(obj->ch);
retval = 1;
}
return retval;
}
int can_write(can_t *obj, CAN_Message msg, int cc)
{
can_frame_t frame;
/* CAN frame */
frame.ID = msg.id; // Message ID
frame.THDSE = 0;
frame.RTR = msg.type; // 0:CANData, 1:CANRemote
frame.IDE = msg.format; // 0:Standard ID, 1:Extend ID
frame.LBL = 0;
frame.DLC = msg.len; // Data length
frame.FDSTS = 1;
frame.BRS = 1;
frame.ESI = 0;
if (R_CAN_OK != R_CAN_TxSet(TX_TRFIFO, TX_TRFIFO_INDEX(obj->ch), &frame, (uint32_t *)&msg.data[0])) {
return 0;
}
if (R_CAN_OK != R_CAN_Tx(TX_TRFIFO, TX_TRFIFO_INDEX(obj->ch), ENABLE)) {
return 0;
}
return 1;
}
int can_read(can_t *obj, CAN_Message *msg, int handle)
{
uint32_t page_index = 0;
uint8_t received_msg_num = 0;
uint8_t msg_cnt;
if (R_CAN_OK != R_CAN_RxPoll(RX_TRFIFO, RX_TRFIFO_INDEX(obj->ch))) {
return 0;
}
if (R_CAN_OK != R_CAN_RxRead(RX_TRFIFO, RX_TRFIFO_INDEX(obj->ch), (uint32_t *)&rx_buf[0])) {
return 0;
}
/* number of received message */
received_msg_num = rx_buf[0];
for (msg_cnt = 0; msg_cnt < received_msg_num; msg_cnt++) {
page_index = msg_cnt * 19;
/* IDE 0:Standard ID, 1:Extend ID */
msg->format = (CANFormat)(rx_buf[page_index + 1] >> 31);
/* RTR/RRS : Data or Remote */
msg->type = (CANType)((rx_buf[page_index + 1] >> 30) & 0x1);
/* ID : Standard ID(b10-b0), Extend ID(b28-b0) */
msg->id = (rx_buf[page_index + 1] & 0x1FFFFFFF);
/* data Length */
msg->len = dlc_to_length[(uint8_t)(rx_buf[page_index + 2] >> 28)];
/* received data */
msg->data[0] = (uint8_t)(rx_buf[page_index + 4] & 0x000000FF);
msg->data[1] = (uint8_t)(rx_buf[page_index + 4] >> 8) & 0x000000FF;
msg->data[2] = (uint8_t)(rx_buf[page_index + 4] >> 16) & 0x000000FF;
msg->data[3] = (uint8_t)(rx_buf[page_index + 4] >> 24) & 0x000000FF;
msg->data[4] = (uint8_t)(rx_buf[page_index + 5] & 0x000000FF);
msg->data[5] = (uint8_t)(rx_buf[page_index + 5] >> 8) & 0x000000FF;
msg->data[6] = (uint8_t)(rx_buf[page_index + 5] >> 16) & 0x000000FF;
msg->data[7] = (uint8_t)(rx_buf[page_index + 5] >> 24) & 0x000000FF;
}
return 1; /* message arrived */
}
int can_mode(can_t *obj, CanMode mode)
{
int retval = 1;
switch (mode) {
case MODE_RESET:
/* set to reset mode */
R_CAN_Control(UNUSED, GLOBAL_RESET);
R_CAN_Control(obj->ch, CHANNEL_RESET);
break;
case MODE_NORMAL:
/* disable test mode */
set_test_mode(obj->ch, STD_TEST, TEST_DISABLE);
reconfigure_channel(obj->ch);
break;
case MODE_SILENT:
/* enable listen only mode */
set_test_mode(obj->ch, TEST_LISTEN_ONLY, TEST_ENABLE);
reconfigure_channel(obj->ch);
break;
case MODE_TEST_LOCAL:
/* enable self test mode 0 */
set_test_mode(obj->ch, EXT_LOOPBACK, TEST_ENABLE);
reconfigure_channel(obj->ch);
break;
case MODE_TEST_GLOBAL:
/* enable Inter-Channel Communication Test */
R_CAN_Control(UNUSED, GLOBAL_TEST);
REG_32W(&RCANFD.RSCFD0CFDGTSTCFG.LONG, TEST_ENABLE, GTSTCFG_C0ICBCE_SHIFT, GTSTCFG_C0ICBCE);
REG_32W(&RCANFD.RSCFD0CFDGTSTCFG.LONG, TEST_ENABLE, GTSTCFG_C1ICBCE_SHIFT, GTSTCFG_C1ICBCE);
REG_32W(&RCANFD.RSCFD0CFDGTSTCTR.LONG, TEST_ENABLE, GTSTCTR_ICBCTME_SHIFT, GTSTCTR_ICBCTME);
/* enable standard test */
set_test_mode(CH_0, STD_TEST, TEST_ENABLE);
set_test_mode(CH_1, STD_TEST, TEST_ENABLE);
reconfigure_channel(CH_0);
reconfigure_channel(CH_1);
break;
case MODE_TEST_SILENT:
/* enable self test mode 1 */
set_test_mode(obj->ch, INT_LOOPBACK, TEST_ENABLE);
reconfigure_channel(obj->ch);
break;
default:
retval = 0;
break;
}
return retval;
}
int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
{
uint8_t page_index;
uint8_t j_index;
if ((CH_0 == obj->ch) && (handle >= CAN0_RX_RULE_NUM)) {
return 0;
}
if ((CH_1 == obj->ch) && (handle >= CAN1_RX_RULE_NUM)) {
return 0;
}
/* set to reset mode */
R_CAN_Control(UNUSED, GLOBAL_RESET);
R_CAN_Control(obj->ch, CHANNEL_RESET);
/* write enable (RSCFD0CFDGAFLECTR.AFLDAE) */
RCANFD.RSCFD0CFDGAFLECTR.LONG |= RCANFD_RSCFD0CFDGAFLECTR_AFLDAE;
/* set page number */
get_rxrule_index(obj->ch, handle, &page_index, &j_index);
REG_32W(&RCANFD.RSCFD0CFDGAFLECTR.LONG, page_index, REG_NONSHIFT, 0x0000001F);
/* set CAN format */
REG_32W(g_regtbl_gaflid[j_index], format, 31, 0x80000000);
if (CANExtended == format) {
REG_32W(g_regtbl_gaflid[j_index], (id & 0x1FFFFFFF), REG_NONSHIFT, 0x1FFFFFFF);
} else {
REG_32W(g_regtbl_gaflid[j_index], (id & 0x000007FF), REG_NONSHIFT, 0x000007FF);
}
/* set masks(IDE, RTR, ID) */
if (CANAny == format) {
/* no masks */
REG_32W(g_regtbl_gaflm[j_index], 0, REG_NONSHIFT, REG_NONMASK);
} else {
/* IDE and ID */
REG_32W(g_regtbl_gaflm[j_index], (0x80000000 | mask), REG_NONSHIFT, REG_NONMASK);
}
/* set GAFLFDP1_j.GAFLFDP */
if (CH_0 == obj->ch) {
REG_32W(g_regtbl_gaflp1[j_index], 0x00000200, REG_NONSHIFT, REG_NONMASK); // CH0:use TRFIFO1
} else {
REG_32W(g_regtbl_gaflp1[j_index], 0x00001000, REG_NONSHIFT, REG_NONMASK); // CH1:use TRFIFO4
}
/* write disable (RSCFD0CFDGAFLECTR.AFLDAE) */
RCANFD.RSCFD0CFDGAFLECTR.LONG &= ~RCANFD_RSCFD0CFDGAFLECTR_AFLDAE;
reconfigure_channel(obj->ch);
return 1;
}
void can_reset(can_t *obj)
{
R_CAN_Control(UNUSED, GLOBAL_RESET);
R_CAN_Control(obj->ch, CHANNEL_RESET);
reset_register(obj->ch);
reconfigure_channel(obj->ch);
}
unsigned char can_rderror(can_t *obj)
{
return (unsigned char)(*g_regtbl_sts[obj->ch] >> RCANFD_RSCFD0CFDC0STS_REC_SHIFT);
}
unsigned char can_tderror(can_t *obj)
{
return (unsigned char)(*g_regtbl_sts[obj->ch] >> RCANFD_RSCFD0CFDC0STS_TEC_SHIFT);
}
void can_monitor(can_t *obj, int silent)
{
if (silent) {
set_test_mode(obj->ch, TEST_LISTEN_ONLY, TEST_ENABLE);
} else {
set_test_mode(obj->ch, STD_TEST, TEST_DISABLE);
}
reconfigure_channel(obj->ch);
}
const PinMap *can_rd_pinmap()
{
return PinMap_CAN_TD;
}
const PinMap *can_td_pinmap()
{
return PinMap_CAN_RD;
}
#endif // DEVICE_CAN

3698
targets/TARGET_RENESAS/TARGET_RZ_A2XX/r_can/inc/r_can_rz_config.h Normal file
View File

File diff suppressed because it is too large Load Diff

310
targets/TARGET_RENESAS/TARGET_RZ_A2XX/r_can/inc/r_can_rz_if.h Normal file
View File

@ -0,0 +1,310 @@
/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
* this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2019-2020 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/* Copyright (c) 2019-2020 Renesas Electronics Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/***********************************************************************************************************************
* File Name : r_can_rz_if.h
* Description : The RZ CAN API.
************************************************************************************************************************
* History : DD.MM.YYYY Version Description
* : 20.09.2019 1.00 First Release
***********************************************************************************************************************/
#ifndef CAN_INTERFACE_HEADER_FILE
#define CAN_INTERFACE_HEADER_FILE
/***********************************************************************************************************************
Includes <System Includes>, "Project Includes"
***********************************************************************************************************************/
#include <stdint.h>
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
#define NOT_USED_PRV_(p) ((void)(p))
#define BIT_SET (1)
#define BIT_CLEAR (0)
#define ENABLE (0)
#define DISABLE (1)
#define BIT00_MASK (0x00000001)
#define BIT01_MASK (0x00000002)
#define BIT02_MASK (0x00000004)
#define BIT03_MASK (0x00000008)
#define BIT04_MASK (0x00000010)
#define BIT05_MASK (0x00000020)
#define BIT06_MASK (0x00000040)
#define BIT07_MASK (0x00000080)
#define BIT08_MASK (0x00000100)
#define BIT09_MASK (0x00000200)
#define BIT10_MASK (0x00000400)
#define BIT11_MASK (0x00000800)
#define BIT12_MASK (0x00001000)
#define BIT13_MASK (0x00002000)
#define BIT14_MASK (0x00004000)
#define BIT15_MASK (0x00008000)
#define BIT16_MASK (0x00010000)
#define BIT17_MASK (0x00020000)
#define BIT18_MASK (0x00040000)
#define BIT19_MASK (0x00080000)
#define BIT20_MASK (0x00100000)
#define BIT21_MASK (0x00200000)
#define BIT22_MASK (0x00400000)
#define BIT23_MASK (0x00800000)
#define BIT24_MASK (0x01000000)
#define BIT25_MASK (0x02000000)
#define BIT26_MASK (0x04000000)
#define BIT27_MASK (0x08000000)
#define BIT28_MASK (0x10000000)
#define BIT29_MASK (0x20000000)
#define BIT30_MASK (0x40000000)
#define BIT31_MASK (0x80000000)
#define PROGRESS_OR_NOREQUEST (0)
#define ABORT_COMPLETE (1)
#define ONE_SHOT_TRANSMIT (0x05)
#define CAN_FIFO_PTR_INC (0xFF)
#define CAN_QUEUE_PTR_INC (0xFF)
#define RX_HEAD_SIZE (4 * 3) /* ID_REG, PTR_REG, FDSTS_REG (4byte * 3register) */
#define RX_DATA_MAX_SIZE (64)
#define RX_MSG_MAX_SIZE (RX_HEAD_SIZE+RX_DATA_MAX_SIZE)
/*** Write data for register ************************/
#define THLSTS_THLELT_CLR (0x00001F0B)
#define THLSTS_THLIF_CLR (0x00001F07)
#define CFSTS_CFMLT_CLR (0x0000FF1B)
#define CFSTS_CFRXIF_CLR (0x0000FF17)
#define CFSTS_CFTXIF_CLR (0x0000FF0F)
#define TXQSTS_TXQIF_CLR (0x00000003)
#define RFSTS_RFMLT_CLR (0x0000FF0B)
#define RFSTS_RFIF_CLR (0x0000FF07)
#define GERFL_CMPOF_DEF_CLR (0x00000006)
#define ERFL_ALF2BEF_CLR (0x7FFF7F00)
#define FDSTS_SOCO2TDCVF_CLR (0xFFFF007F)
#define TMSTS_TMTRF_CLR (0x19)
/*** Mask bit for register W/R **********************/
/* used in R_CAN_Create func */
#define FDCFG_MASK_FOR_CREATE (0x3F000407)
#define CFCC_MASK_FOR_CREATE (0xFFFFFFFE)
#define RFCC_MASK_FOR_CREATE (0xFFFFFFFE)
#define GCTR_MASK_FOR_CREATE (0x00000F00)
#define CTR_MASK01_FOR_CREATE (0x00EFFF00)
#define CTR_MASK02_FOR_CREATE (0x80000000)
#define TXQCC_MASK_FOR_CREATE (0x00003F00)
#define THLCC_MASK_FOR_CREATE (0x00000700)
/* used in R_CAN_SetBitrate func */
#define CFDCFG_MASK_FOR_BITRATE (0x00EF0300)
/* Test mode */
#define STD_TEST (0)
#define TEST_LISTEN_ONLY (1)
#define EXT_LOOPBACK (2)
#define INT_LOOPBACK (3)
#define VAL_CLEAR (0)
#define CAN_PORT (0x04) /* CAN PORT Function */
#define RAM_TEST_PROTECT_RELEASE_CODE_1 (0x00007575)
#define RAM_TEST_PROTECT_RELEASE_CODE_2 (0x00008A8A)
#define RAM_INIT_DATA (0x00000000)
/*** CAN Hard resources *****************************/
#define MAX_CHANNELS (2) /* Number of mounted channels */
#define CH_0 (0) /* CAN CH0 */
#define CH_1 (1) /* CAN CH1 */
#define UNUSED (0)
#define TRFIFO_NUM_PER_CH (3) /* Number of Transmit/Receive FIFO Buffers per channel */
#define TRFIFO_MAX (MAX_CHANNELS * TRFIFO_NUM_PER_CH)
#define RXFIFO_MAX (8)
#define TXBUF_PER_CH (16) /* Number of Transmit Buffers per channel */
#define TXBUF_MAX (MAX_CHANNELS * TXBUF_PER_CH)
#define CH_0_TXBUF_TOP (0)
#define CH_0_TXBUF_END (15)
#define CH_1_TXBUF_TOP (16)
#define CH_1_TXBUF_END (31)
#define RXBUF_MAX (32)
/*** CAN mode setting values ******************************/
/* RSCFDnCFDGCTR: Global Control Register */
#define CFDGCTR_GMDC_TEST (0x00000002) /* bit1-0=2: Global test mode */
#define CFDGCTR_GMDC_RESET (0x00000001) /* bit1-0=1: Global reset mode */
#define CFDGCTR_GMDC_OP (0x00000000) /* bit1-0=0: Global operating mode */
/* RSCFDnCFDCmSTS：Channel m Status Register */
#define CFDCmCTR_CSLPSTS (0x00000004) /* bit2=1 : Channel stop mode */
#define CFDCmCTR_CHLTSTS (0x00000002) /* bit1-0=2: Channel halt mode */
#define CFDCmCTR_CHRST (0x00000001) /* bit1-0=1: Channel reset mode */
#define CFDCmCTR_CHOP (0x00000000) /* bit1-0=0: Channel communication mode */
/*** CAN API arguments values *****************************/
#define GLOBAL_STOP (0)
#define GLOBAL_RESET (1)
#define GLOBAL_OPERATION (2)
#define GLOBAL_TEST (3)
#define CHANNEL_STOP (4)
#define CHANNEL_RESET (5)
#define CHANNEL_HALT (6)
#define CHANNEL_COM (7)
/*** CAN API ACTION TYPES ***/
#define ENABLE_COMMON (0)
#define DISABLE_COMMON (1)
#define ENABLE_CHANNEL (2)
#define DISABLE_CHANNEL (3)
#define CANPORT_TEST_LISTEN_ONLY (4)
#define CANPORT_TEST_0_EXT_LOOPBACK (5)
#define CANPORT_TEST_1_INT_LOOPBACK (6)
#define CANPORT_RETURN_TO_NORMAL (7)
/* Tx mode */
#define TX_TRFIFO (0)
#define TX_TXBUF (1)
#define TX_QUEUE (2)
/* Rx mode */
#define RX_TRFIFO (0)
#define RX_RXFIFO (1)
#define RX_RXBUF (2)
/*** CAN API return values *****************************/
#define R_CAN_OK (0)
#define R_CAN_NOT_OK (1)
#define R_CAN_ERR (2)
#define R_CAN_BAD_CH_NR (3)
#define R_CAN_SW_BAD_IDX (4)
#define R_CAN_BAD_ACTION_TYPE (5)
#define R_CAN_SW_RAM_ERR (6)
#define R_CAN_MODULE_STOP_ERR (7)
#define R_CAN_BAD_MODE_TYPE (8)
#define R_CAN_BAD_ONESHOT_TYPE (9)
#define R_CAN_BUF_EMPTY (10)
#define R_CAN_BUF_OVERFLOW (11)
#define R_CAN_MSGLOST (12)
#define R_CAN_REG_ISR_ERR (13)
#define R_CAN_NO_SENTDATA (14)
#define R_CAN_GLB_STOP_ERR (15)
#define R_CAN_GLB_RST_ERR (16)
#define R_CAN_GLB_TEST_ERR (17)
#define R_CAN_GLB_OP_ERR (18)
#define R_CAN_CH_STOP_ERR (19)
#define R_CAN_CH_RST_ERR (20)
#define R_CAN_CH_HALT_ERR (21)
#define R_CAN_CH_COM_ERR (22)
#define R_CAN_STATUS_ERROR_ACTIVE (23)
#define R_CAN_STATUS_ERROR_PASSIVE (24)
#define R_CAN_STATUS_BUSOFF (25)
#define R_CAN_CRC_ERR (26)
#define R_CAN_ICC_TMO (27)
/******************************************************************************
Typedef definitions
******************************************************************************/
typedef struct {
uint32_t ID : 29; /* ID Data */
uint32_t THDSE : 1; /* Transmit History Data Store Enable */
uint32_t RTR : 1; /* RTR 0:Data 1:Remote */
uint32_t IDE : 1; /* IDE 0:Standard 1:Extend */
uint32_t LBL : 12; /* Label Data */
uint32_t DLC : 4; /* DLC Data */
uint32_t FDSTS: 1; /* FD Status 0:CLASSICAL_CAN, 1:CANFD */
uint32_t BRS: 1; /* BRS bit */
uint32_t ESI: 1; /* ESI bit */
} can_frame_t;
typedef struct {
void (*p_Addr)(void); /* Interrupt callback function pointer */
uint8_t prior; /* Interrupt priority */
} isr_attr_t;
typedef struct {
isr_attr_t rxfifo; /* Receive FIFO interrupt */
isr_attr_t glb_err; /* Global error interrupt */
isr_attr_t tx[MAX_CHANNELS]; /* CANm transmit/receive FIFO transmit complete interrupt */
isr_attr_t trfifo_rx[MAX_CHANNELS]; /* CANm transmit/receive FIFO receive complete interrupt */
isr_attr_t ch_err[MAX_CHANNELS]; /* CANm error interrupt */
} can_isr_t;
/**************************************************************************************************
Exported global variables
***************************************************************************************************/
/**************************************************************************************************
Exported global functions (to be accessed by other files)
***************************************************************************************************/
/*****************************************************************
R Z C A N A P I
******************************************************************/
/* INITIALIZATION */
uint8_t R_CAN_Create(const can_isr_t *cb_func);
uint8_t R_CAN_PortSet(const uint8_t ch_nr, const uint8_t action_type);
uint8_t R_CAN_Control(const uint8_t ch_nr, const uint8_t action_type);
void R_CAN_SetBitrate(const uint8_t ch_nr);
uint8_t R_CAN_Gateway(const uint8_t idx_nr);
/* TRANSMIT */
uint8_t R_CAN_TxSet(const uint8_t tx_mode, const uint8_t idx_nr, const can_frame_t *p_frame, const uint32_t *p_buf);
uint8_t R_CAN_Tx(const uint8_t tx_mode, const uint8_t idx_nr, const uint8_t one_shot_en);
uint8_t R_CAN_TxCheck(const uint8_t tx_mode, const uint8_t idx_nr);
uint8_t R_CAN_TxStopMsg(const uint8_t tx_mode, const uint8_t idx_nr);
uint8_t R_CAN_TxHis(const uint8_t ch_nr, uint32_t *p_buf);
/* RECEIVE */
uint8_t R_CAN_RxSet(const uint8_t rx_mode, const uint8_t idx_nr);
uint8_t R_CAN_RxPoll(const uint8_t rx_mode, const uint8_t idx_nr);
uint8_t R_CAN_RxRead(const uint8_t rx_mode, const uint8_t idx_nr, uint32_t *p_buf);
/* ERRORS */
uint8_t R_CAN_CheckErr(const uint8_t ch_nr);
/* DIAGNOSIS */
uint8_t R_CAN_RamTest(const uint32_t wr_dt);
uint8_t R_CAN_CrcTest(const uint8_t tx_mode, const uint8_t tx_idx_nr, const can_frame_t *p_frame, const uint32_t *p_tx_buf,
const uint8_t rx_mode, const uint8_t rx_idx_nr, uint32_t *p_rx_buf);
/* API WRAPPER */
void Wrap_Can_WaitRamInitOver(void);
void Wrap_Can_SetRxRule(void);
#endif /* CAN_INTERFACE_HEADER_FILE */

2773
targets/TARGET_RENESAS/TARGET_RZ_A2XX/r_can/src/r_can_rz.c Normal file
View File

File diff suppressed because it is too large Load Diff

1
targets/targets.json
View File

@ -4699,6 +4699,7 @@
"USTICKER",
"RTC",
"ANALOGIN",
"CAN",
"ETHERNET",
"I2C",
"I2CSLAVE",