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Merge pull request #2273 from svastm/fix_i2c_clock_l4 

[STM32L4XX] Fix i2c clock config
pull/2347/merge
Sam Grove 2016-08-04 12:26:21 -05:00 committed by GitHub
parent ff34c5b54b 0e63f4183c
commit 0edef2da82
5 changed files with 74 additions and 82 deletions
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41
hal/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/system_stm32l4xx.c
View File

@ -26,43 +26,20 @@
*
* This file configures the system clock as follows:
*=============================================================================
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
* | (external 8 MHz clock) | (internal 16 MHz)
* | 2- PLL_HSE_XTAL | or PLL_MSI
* | (external 8 MHz xtal) | (internal 4 MHz)
*-----------------------------------------------------------------------------
* System Clock source | MSI
* SYSCLK(MHz) | 48 | 80
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 4000000
* AHBCLK (MHz) | 48 | 80
*-----------------------------------------------------------------------------
* HCLK(Hz) | 4000000
* APB1CLK (MHz) | 48 | 80
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
* APB2CLK (MHz) | 48 | 80
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* PLLSAI1_P | NA
*-----------------------------------------------------------------------------
* PLLSAI1_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI1_R | NA
*-----------------------------------------------------------------------------
* PLLSAI2_P | NA
*-----------------------------------------------------------------------------
* PLLSAI2_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI2_R | NA
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
* USB capable (48 MHz precise clock) | YES | NO
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************

4
hal/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/system_stm32l4xx.c
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@ -45,7 +45,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -205,7 +205,7 @@ void SystemInit(void)
RCC->CR &= (uint32_t)0xEAF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00000800;
RCC->PLLCFGR = 0x00001000;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/system_stm32l4xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l4xx.h
* @author MCD Application Team
* @version V1.0.0
* @date 26-June-2015
* @version V1.1.1
* @date 29-April-2016
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

41
hal/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/system_stm32l4xx.c
View File

@ -26,43 +26,20 @@
*
* This file configures the system clock as follows:
*=============================================================================
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
* | (external 8 MHz clock) | (internal 16 MHz)
* | 2- PLL_HSE_XTAL | or PLL_MSI
* | (external 8 MHz xtal) | (internal 4 MHz)
*-----------------------------------------------------------------------------
* System Clock source | MSI
* SYSCLK(MHz) | 48 | 80
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 4000000
* AHBCLK (MHz) | 48 | 80
*-----------------------------------------------------------------------------
* HCLK(Hz) | 4000000
* APB1CLK (MHz) | 48 | 80
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
* APB2CLK (MHz) | 48 | 80
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* PLLSAI1_P | NA
*-----------------------------------------------------------------------------
* PLLSAI1_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI1_R | NA
*-----------------------------------------------------------------------------
* PLLSAI2_P | NA
*-----------------------------------------------------------------------------
* PLLSAI2_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI2_R | NA
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
* USB capable (48 MHz precise clock) | YES | NO
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************

64
hal/targets/hal/TARGET_STM/TARGET_STM32L4/i2c_api.c
View File

@ -116,21 +116,59 @@ void i2c_frequency(i2c_t *obj, int hz)
// wait before init
timeout = LONG_TIMEOUT;
while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
// Update the SystemCoreClock variable.
SystemCoreClockUpdate();
// Common settings: I2C clock = 32 MHz, Analog filter = ON, Digital filter coefficient = 0
switch (hz) {
case 100000:
I2cHandle.Init.Timing = 0x20602938; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
break;
case 400000:
I2cHandle.Init.Timing = 0x00B0122A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
break;
case 1000000:
I2cHandle.Init.Timing = 0x0030040E; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
break;
default:
break;
if (SystemCoreClock == 80000000) {
// Common settings: I2C clock = 80 MHz, Analog filter = ON, Digital filter coefficient = 0
switch (hz) {
case 100000:
I2cHandle.Init.Timing = 0x30C14E6B; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
break;
case 400000:
I2cHandle.Init.Timing = 0x10D1143A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
break;
case 1000000:
I2cHandle.Init.Timing = 0x00810E27; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
break;
default:
break;
}
} else if (SystemCoreClock == 48000000) {
// Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0
switch (hz) {
case 100000:
I2cHandle.Init.Timing = 0x20A03E55; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
break;
case 400000:
I2cHandle.Init.Timing = 0x10800C21; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
break;
case 1000000:
I2cHandle.Init.Timing = 0x00500816; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
break;
default:
break;
}
}
// Enable the Fast Mode Plus capability
if (hz == 1000000) {
if (obj->i2c == I2C_1) {
__HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C1);
}
#if defined(I2C2_BASE)
if (obj->i2c == I2C_2) {
__HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C2);
}
#endif
#if defined(I2C3_BASE)
if (obj->i2c == I2C_3) {
__HAL_SYSCFG_FASTMODEPLUS_ENABLE(HAL_SYSCFG_FASTMODEPLUS_I2C3);
}
#endif
}
// I2C configuration
I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;