diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_conf.h
new file mode 100644
index 0000000000..1025fb65db
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_conf.h
@@ -0,0 +1,292 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CONF_H
+#define __STM32L0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LCD_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)50) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal Multiple Speed oscillator (MSI) default value.
+ * This value is the default MSI range value after Reset.
+ */
+#if !defined (MSI_VALUE)
+ #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)500) /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)3) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define PREREAD_ENABLE 1
+#define BUFFER_CACHE_DISABLE 0
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32l0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32l0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32l0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32l0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32l0xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32l0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32l0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32l0xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32l0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32l0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32l0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32l0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32l0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32l0xx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32l0xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32l0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32l0xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32l0xx_hal_rtc.h"
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32l0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32l0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32l0xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32l0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32l0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32l0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32l0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32l0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32l0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32l0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cortex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cortex.c
new file mode 100644
index 0000000000..fc5c0aa1dd
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cortex.c
@@ -0,0 +1,333 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_cortex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief CORTEX HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using CORTEX HAL driver ***
+ ===========================================================
+ [..]
+ This section provide functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex-M0+ exceptions are managed by CMSIS functions.
+ (#) Enable and Configure the priority of the selected IRQ Channels.
+ The priority can be 0..3.
+
+ -@- Lower priority values gives higher priority.
+ -@- Priority Order:
+ (#@) Lowest priority.
+ (#@) Lowest hardware priority (IRQn position).
+
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
+
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+
+ [..]
+ *** How to configure Systick using CORTEX HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for time base
+
+ (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value (0x03).
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+ inside the stm32l0xx_hal_cortex.h file.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX
+ * @brief CORTEX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CORTEX_Private_Functions
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+ Systick functionalities
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn: External interrupt number .
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
+ * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 3.
+ * A lower priority value indicates a higher priority
+ * @param SubPriority: The subpriority level for the IRQ channel.
+ * with stm32l0xx devices, this parameter is a dummy value and it is ignored, because
+ * no subpriority supported in Cortex M0+ based products.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+ NVIC_SetPriority(IRQn,PreemptPriority);
+}
+
+/**
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param IRQn External interrupt number .
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number .
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiates a system reset request to reset the MCU.
+ * @param None
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+
+
+
+/**
+ * @brief Sets Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of @ref IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+ * and returns the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number .
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number .
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+ {
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ }
+}
+
+/**
+ * @brief This function handles SYSTICK interrupt request.
+ * @param None
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void)
+{
+ HAL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @param None
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cortex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cortex.h
new file mode 100644
index 0000000000..9dad2c67a6
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cortex.h
@@ -0,0 +1,132 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_cortex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CORTEX_H
+#define __STM32L0xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants
+ * @{
+ */
+
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
+
+/** @defgroup CORTEX_SysTick_clock_source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/** @brief Configures the SysTick clock source.
+ * @param __CLKSRC__: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
+ do { \
+ if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
+ { \
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
+ } \
+ else \
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
+ } while(0)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions *******************************/
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+
+/* Peripheral Control functions *************************************************/
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc.c
new file mode 100644
index 0000000000..ee749ea0cd
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc.c
@@ -0,0 +1,558 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_crc.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief CRC HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the CRC peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (+) Enable CRC AHB clock using __CRC_CLK_ENABLE();
+ (+) Initialize CRC calculator
+ - specify generating polynomial (IP default or non-default one)
+ - specify initialization value (IP default or non-default one)
+ - specify input data format
+ - specify input or output data inversion mode if any
+ (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+ input data buffer starting with the previously computed CRC as
+ initialization value
+ (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+ input data buffer starting with the defined initialization value
+ (default or non-default) to initiate CRC calculation
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRC
+ * @brief CRC HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/** @defgroup CRC_Private_Functions
+ * @{
+ */
+
+/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization/de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRC according to the specified parameters
+ in the CRC_InitTypeDef and create the associated handle
+ (+) DeInitialize the CRC peripheral
+ (+) Initialize the CRC MSP
+ (+) DeInitialize CRC MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRC according to the specified
+ * parameters in the CRC_InitTypeDef and creates the associated handle.
+ * @param hcrc: CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CRC_INSTANCE(hcrc->Instance));
+
+ if(hcrc->State == HAL_CRC_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_CRC_MspInit(hcrc);
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* check whether or not non-default generating polynomial has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
+ if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+ {
+ /* initialize IP with default generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
+ }
+ else
+ {
+ /* initialize CRC IP with generating polynomial defined by user */
+ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* check whether or not non-default CRC initial value has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
+ if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+ {
+ WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
+ }
+ else
+ {
+ WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
+ }
+
+
+ /* set input data inversion mode */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
+
+ /* set output data inversion mode */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
+
+ /* makes sure the input data format (bytes, halfwords or words stream)
+ * is properly specified by user */
+ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CRC peripheral.
+ * @param hcrc: CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CRC_INSTANCE(hcrc->Instance));
+
+ /* Check the CRC peripheral state */
+ if(hcrc->State == HAL_CRC_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CRC_MspDeInit(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRC MSP.
+ * @param hcrc: CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CRC MSP.
+ * @param hcrc: CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspDeInit can be implemented in the user file
+ */
+}
+
+
+
+/**
+ * @brief Set the Reverse Input data mode.
+ * @param hcrc: CRC handle
+ * @param InputReverseMode: Input Data inversion mode
+ * This parameter can be one of the following values:
+ * @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
+ * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
+ * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
+ * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set input data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Reverse Output data mode.
+ * @param hcrc: CRC handle
+ * @param OutputReverseMode: Output Data inversion mode
+ * This parameter can be one of the following values:
+ * @arg CRC_OUTPUTDATA_INVERSION_DISABLED: no CRC inversion (default value)
+ * @arg CRC_OUTPUTDATA_INVERSION_ENABLED: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set output data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Group2 Peripheral Control functions
+ * @brief management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ using combination of the previous CRC value and the new one.
+
+ or
+
+ (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ independently of the previous CRC value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with the previously computed CRC as initialization value.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0; /* CRC input data buffer index */
+ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Process locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter Data to the CRC calculator */
+ for(index = 0; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ break;
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with hcrc->Instance->INIT as initialization value.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0; /* CRC input data buffer index */
+ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Process locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+ * written in hcrc->Instance->DR) */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter 32-bit input data to the CRC calculator */
+ for(index = 0; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ /* Specific 8-bit input data handling */
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ /* Specific 16-bit input data handling */
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ break;
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+
+
+/**
+ * @brief Enter 8-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0; /* input data buffer index */
+
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+ * handling by the IP */
+ for(i = 0; i < (BufferLength/4); i++)
+ {
+ hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));
+ }
+ /* last bytes specific handling */
+ if ((BufferLength%4) != 0)
+ {
+ if (BufferLength%4 == 1)
+ {
+ *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
+ }
+ if (BufferLength%4 == 2)
+ {
+ *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));
+ }
+ if (BufferLength%4 == 3)
+ {
+ *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1]));
+ *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
+ }
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+
+
+/**
+ * @brief Enter 16-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0; /* input data buffer index */
+
+ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+ * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
+ * a correct type handling by the IP */
+ for(i = 0; i < (BufferLength/2); i++)
+ {
+ hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));
+ }
+ if ((BufferLength%2) != 0)
+ {
+ *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the CRC state.
+ * @param hcrc: CRC handle
+ * @retval HAL state
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+ return hcrc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc.h
new file mode 100644
index 0000000000..f6000eb55a
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc.h
@@ -0,0 +1,343 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_crc.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CRC_H
+#define __STM32L0xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief CRC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CRC_STATE_RESET = 0x00, /*!< CRC Reset State */
+ HAL_CRC_STATE_READY = 0x01, /*!< CRC Initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02, /*!< CRC process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC Timeout State */
+ HAL_CRC_STATE_ERROR = 0x04 /*!< CRC Error State */
+}HAL_CRC_StateTypeDef;
+
+/**
+ * @brief CRC Init Structure definition
+ */
+typedef struct
+{
+ uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
+ If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
+ X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
+ In that case, there is no need to set GeneratingPolynomial field.
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
+
+ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
+ If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+ 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
+ If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */
+
+ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
+ respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
+ e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
+ No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */
+
+ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Size_Definitions and indicates CRC length.
+ Value can be either one of
+ CRC_POLYLENGTH_32B (32-bit CRC)
+ CRC_POLYLENGTH_16B (16-bit CRC)
+ CRC_POLYLENGTH_8B (8-bit CRC)
+ CRC_POLYLENGTH_7B (7-bit CRC) */
+
+ uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
+ is set to DEFAULT_INIT_VALUE_ENABLE */
+
+ uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref Input_Data_Inversion and specifies input data inversion mode.
+ Can be either one of the following values
+ CRC_INPUTDATA_INVERSION_NONE no input data inversion
+ CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
+ CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
+ CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+
+ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+ Can be either
+ CRC_OUTPUTDATA_INVERSION_DISABLED no CRC inversion, or
+ CRC_OUTPUTDATA_INVERSION_ENABLED CRC 0x11223344 is converted into 0x22CC4488 */
+}CRC_InitTypeDef;
+
+
+/**
+ * @brief CRC Handle Structure definition
+ */
+typedef struct
+{
+ CRC_TypeDef *Instance; /*!< Register base address */
+
+ CRC_InitTypeDef Init; /*!< CRC configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRC Locking object */
+
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+
+ uint32_t InputDataFormat; /*!< This parameter is a value of @ref Input_Buffer_Format and specifies input data format.
+ Can be either
+ CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
+ CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
+ CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data)
+ Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
+ must occur if InputBufferFormat is not one of the three values listed above */
+}CRC_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
+ * @{
+ */
+#define DEFAULT_CRC32_POLY 0x04C11DB7
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
+ * @{
+ */
+#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
+ * @{
+ */
+#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
+#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
+ * @{
+ */
+#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
+#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)
+#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
+ * @{
+ */
+#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
+#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
+#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
+#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
+#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
+ ((LENGTH) == CRC_POLYLENGTH_16B) || \
+ ((LENGTH) == CRC_POLYLENGTH_8B) || \
+ ((LENGTH) == CRC_POLYLENGTH_7B))
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+ * @{
+ */
+#define HAL_CRC_LENGTH_32B 32
+#define HAL_CRC_LENGTH_16B 16
+#define HAL_CRC_LENGTH_8B 8
+#define HAL_CRC_LENGTH_7B 7
+
+/**
+ * @}
+ */
+
+/** @defgroup Input_Data_Inversion Input Data Inversion Modes
+ * @{
+ */
+#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
+#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
+#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
+#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+/**
+ * @}
+ */
+
+/** @defgroup Output_Data_Inversion Output Data Inversion Modes
+ * @{
+ */
+#define CRC_OUTPUTDATA_INVERSION_DISABLED ((uint32_t)0x00000000)
+#define CRC_OUTPUTDATA_INVERSION_ENABLED ((uint32_t)CRC_CR_REV_OUT)
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLED) || \
+ ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup Input_Buffer_Format Input Buffer Format
+ * @{
+ */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
+ * the CRC APIs to provide a correct result */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
+#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
+#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
+#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Macro
+ * @{
+ */
+
+/** @brief Reset CRC handle state
+ * @param __HANDLE__: CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+ * @brief Check that instance is correctly set to CRC
+ * @param __PERIPH__: CRC handle instance
+ * @retval None.
+ */
+#define IS_CRC_INSTANCE(__PERIPH__) ((__PERIPH__) == CRC)
+
+/**
+ * @brief Reset CRC Data Register.
+ * @param __HANDLE__: CRC handle
+ * @retval None.
+ */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+ * @brief Set CRC INIT non-default value
+ * @param __HANDLE__ : CRC handle
+ * @param __INIT__ : 32-bit initial value
+ * @retval None.
+ */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
+
+
+/**
+ * @brief Set CRC output reversal
+ * @param __HANDLE__ : CRC handle
+ * @retval None.
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+
+
+/**
+ * @brief Unset CRC output reversal
+ * @param __HANDLE__ : CRC handle
+ * @retval None.
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+
+
+/**
+ * @}
+ */
+
+
+/* Include CRC HAL Extension module */
+#include "stm32l0xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRC_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+
+/* Peripheral State and Error functions ***************************************/
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc_ex.c
new file mode 100644
index 0000000000..c1d2876606
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc_ex.c
@@ -0,0 +1,210 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_crc_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief Extended CRC HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the CRC peripheral:
+ * + Initialization/de-initialization functions
+ *
+ @verbatim
+================================================================================
+ ##### #####
+================================================================================
+
+ [..] < This section can contain:
+ (#) Description of the product specific implementation; all features
+ that is specific to this IP: separate clock for RTC/LCD/IWDG/ADC,
+ power domain (backup domain for the RTC)...
+ (#) IP main features, only when needed and not mandatory for all IPs,
+ ex. for xWDG, GPIO, COMP...
+ >
+
+ [..] < You can add as much sections as needed.>
+
+ [..] < You can add as much sections as needed.>
+
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (+) Enable CRC AHB clock using __CRC_CLK_ENABLE();
+ (+) Initialize CRC calculator
+ - specify generating polynomial (IP default or non-default one)
+ - specify initialization value (IP default or non-default one)
+ - specify input data format
+ - specify input or output data inversion mode if any
+ (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+ input data buffer starting with the previously computed CRC as
+ initialization value
+ (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+ input data buffer starting with the defined initialization value
+ (default or non-default) to initiate CRC calculation
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRCEx
+ * @brief CRC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRCEx_Private_Functions
+ * @{
+ */
+
+/** @defgroup CRCEx_Group1 Extended Initialization/de-initialization functions
+ * @brief Extended Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization/de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRC according to the specified parameters
+ in the CRC_InitTypeDef and create the associated handle
+ (+) DeInitialize the CRC peripheral
+ (+) Initialize the CRC MSP
+ (+) DeInitialize CRC MSP
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initializes the CRC polynomial if different from default one.
+ * @param hcrc: CRC handle
+ * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)
+ * This parameter is written in normal representation, e.g.
+ * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
+ * @param PolyLength: CRC polynomial length
+ * This parameter can be one of the following values:
+ * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
+ * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
+ * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
+ * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
+{
+ uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
+
+ /* Check the parameters */
+ assert_param(IS_CRC_POL_LENGTH(PolyLength));
+
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0))
+ {
+ }
+
+ switch (PolyLength)
+ {
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ break;
+ }
+
+ /* set generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, Pol);
+
+ /* set generating polynomial size */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc_ex.h
new file mode 100644
index 0000000000..9a1df59a98
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_crc_ex.h
@@ -0,0 +1,105 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_crc_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CRC_EX_H
+#define __STM32L0xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup CRCEx_Extended_Exported_Macro
+ * @{
+ */
+
+
+/**
+ * @brief Set CRC non-default polynomial
+ * @param __HANDLE__ : CRC handle
+ * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
+ * @retval None.
+ */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+
+/* Peripheral Control functions ***********************************************/
+/* Peripheral State and Error functions ***************************************/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CRC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cryp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cryp.c
new file mode 100644
index 0000000000..1af697c46b
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cryp.c
@@ -0,0 +1,2090 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_cryp.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief CRYP HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Cryptography (CRYP) peripheral:
+ * + Initialization and de-initialization functions
+ * + Processing functions by algorithm using polling mode
+ * + Processing functions by algorithm using interrupt mode
+ * + Processing functions by algorithm using DMA mode
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The CRYP HAL driver can be used as follows:
+
+ (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
+ (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
+ (##) In case of using interrupts (e.g. HAL_AES_ECB_Encrypt_IT())
+ (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
+ (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
+ (+) Enable the DMA1 interface clock using
+ (++) __DMA1_CLK_ENABLE()
+ (+) Configure and enable two DMA Channels one for managing data transfer from
+ memory to peripheral (input channel) and another channel for managing data
+ transfer from peripheral to memory (output channel)
+ (+) Associate the initilalized DMA handle to the CRYP DMA handle
+ using __HAL_LINKDMA()
+ (+) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the two DMA Streams. The output stream should have higher
+ priority than the input stream.
+ (++) HAL_NVIC_SetPriority()
+ (++) HAL_NVIC_EnableIRQ()
+
+ (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
+ (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
+ (##) The encryption/decryption key.
+ (##) The initialization vector (counter). It is not used ECB mode.
+
+ (#)Three processing (encryption/decryption) functions are available:
+ (##) Polling mode: encryption and decryption APIs are blocking functions
+ i.e. they process the data and wait till the processing is finished
+ e.g. HAL_CRYP_AESCBC_Encrypt()
+ (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+ i.e. they process the data under interrupt
+ e.g. HAL_CRYP_AESCBC_Encrypt_IT()
+ (##) DMA mode: encryption and decryption APIs are not blocking functions
+ i.e. the data transfer is ensured by DMA
+ e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
+
+ (#)When the processing function is called at first time after HAL_CRYP_Init()
+ the CRYP peripheral is initialized and processes the buffer in input.
+ At second call, the processing function performs an append of the already
+ processed buffer.
+ When a new data block is to be processed, call HAL_CRYP_Init() then the
+ processing function.
+
+ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRYP
+ * @brief CRYP HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CRYP_ALGO_CHAIN_MASK (AES_CR_MODE | AES_CR_CHMOD)
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key);
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRYP_Private_Functions
+ * @{
+ */
+
+/** @defgroup CRYP_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRYP according to the specified parameters
+ in the CRYP_InitTypeDef and creates the associated handle
+ (+) DeInitialize the CRYP peripheral
+ (+) Initialize the CRYP MSP
+ (+) DeInitialize CRYP MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRYP according to the specified
+ * parameters in the CRYP_InitTypeDef and creates the associated handle.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check the parameters */
+ assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_CRYP_MspInit(hcryp);
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the data type*/
+ AES->CR = hcryp->Init.DataType;
+
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0;
+ hcryp->CrypOutCount = 0;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = HAL_CRYP_PHASE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the CRYP peripheral.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = HAL_CRYP_PHASE_READY;
+
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0;
+ hcryp->CrypOutCount = 0;
+
+ /* Disable the CRYP Peripheral Clock */
+ __HAL_CRYP_DISABLE();
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_CRYP_MspDeInit(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP MSP.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes CRYP MSP.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Group2 AES processing functions
+ * @brief processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### AES processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Encrypt plaintext using AES algorithm in different chaining modes
+ (+) Decrypt cyphertext using AES algorithm in different chaining modes
+ [..] Three processing functions are available:
+ (+) Polling mode
+ (+) Interrupt mode
+ (+) DMA mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode
+ * then encrypt pPlainData. The cypher data are available in pCypherData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode
+ * then decrypted pCypherData. The cypher data are available in pPlainData
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES CTR decryption mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Write Plain Data and Get Cypher Data */
+ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(AES_IT_CC);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Get the last input data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+ else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF))
+ {
+ /* Clear CCF Flag */
+ AES->CR |= AES_CR_CCFC;
+
+ /* Get the last Output data adress */
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+
+ /* Read the Output block from the Data Output Register */
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ hcryp->pCrypOutBuffPtr += 16;
+ hcryp->CrypOutCount -= 16;
+
+ /* Check if all input text is encrypted */
+ if(hcryp->CrypOutCount == 0)
+ {
+ /* Disable Computation Complete Interrupt */
+ __HAL_CRYP_DISABLE_IT(AES_IT_CC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call computation complete callback */
+ HAL_CRYP_ComputationCpltCallback(hcryp);
+ }
+ else /* Process the rest of input text */
+ {
+ /* Get the last Intput data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES CBC mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(AES_IT_CC);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Get the last input data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+ else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF))
+ {
+ /* Clear CCF Flag */
+ AES->CR |= AES_CR_CCFC;
+
+ /* Get the last Output data adress */
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+
+ /* Read the Output block from the Data Output Register */
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ hcryp->pCrypOutBuffPtr += 16;
+ hcryp->CrypOutCount -= 16;
+
+ /* Check if all input text is encrypted */
+ if(hcryp->CrypOutCount == 0)
+ {
+ /* Disable Computation Complete Interrupt */
+ __HAL_CRYP_DISABLE_IT(AES_IT_CC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call computation complete callback */
+ HAL_CRYP_ComputationCpltCallback(hcryp);
+ }
+ else /* Process the rest of input text */
+ {
+ /* Get the last Intput data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pPlainData;
+ hcryp->pCrypOutBuffPtr = pCypherData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES CTR mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(AES_IT_CC);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Get the last input data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+ else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF))
+ {
+ /* Clear CCF Flag */
+ AES->CR |= AES_CR_CCFC;
+
+ /* Get the last Output data adress */
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+
+ /* Read the Output block from the Data Output Register */
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ hcryp->pCrypOutBuffPtr += 16;
+ hcryp->CrypOutCount -= 16;
+
+ /* Check if all input text is encrypted */
+ if(hcryp->CrypOutCount == 0)
+ {
+ /* Disable Computation Complete Interrupt */
+ __HAL_CRYP_DISABLE_IT(AES_IT_CC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call computation complete callback */
+ HAL_CRYP_ComputationCpltCallback(hcryp);
+ }
+ else /* Process the rest of input text */
+ {
+ /* Get the last Intput data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(AES_IT_CC);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Get the last input data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+ else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF))
+ {
+ /* Clear CCF Flag */
+ AES->CR |= AES_CR_CCFC;
+
+ /* Get the last Output data adress */
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+
+ /* Read the Output block from the Output register */
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+
+ hcryp->pCrypOutBuffPtr += 16;
+ hcryp->CrypOutCount -= 16;
+
+ /* Check if all input text is decrypted */
+ if(hcryp->CrypOutCount == 0)
+ {
+ /* Disable Computation Complete Interrupt */
+ __HAL_CRYP_DISABLE_IT(AES_IT_CC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call computation complete callback */
+ HAL_CRYP_ComputationCpltCallback(hcryp);
+ }
+ else /* Process the rest of input text */
+ {
+ /* Get the last Intput data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(AES_IT_CC);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Get the last input data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+ else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF))
+ {
+ /* Clear CCF Flag */
+ AES->CR |= AES_CR_CCFC;
+
+ /* Get the last Output data adress */
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+
+ /* Read the Output block from the Output Register */
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+
+ hcryp->pCrypOutBuffPtr += 16;
+ hcryp->CrypOutCount -= 16;
+
+ /* Check if all input text is decrypted */
+ if(hcryp->CrypOutCount == 0)
+ {
+ /* Disable Computation Complete Interrupt */
+ __HAL_CRYP_DISABLE_IT(AES_IT_CC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call computation complete callback */
+ HAL_CRYP_ComputationCpltCallback(hcryp);
+ }
+ else /* Process the rest of input text */
+ {
+ /* Get the last Intput data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ /* Get the buffer addresses and sizes */
+ hcryp->CrypInCount = Size;
+ hcryp->pCrypInBuffPtr = pCypherData;
+ hcryp->pCrypOutBuffPtr = pPlainData;
+ hcryp->CrypOutCount = Size;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES CTR decryption mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(AES_IT_CC);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+
+ /* Get the last input data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+ else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF))
+ {
+ /* Clear CCF Flag */
+ AES->CR |= AES_CR_CCFC;
+
+ /* Get the last Output data adress */
+ outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+
+ /* Read the Output block from the Output Register */
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+
+ hcryp->pCrypOutBuffPtr += 16;
+ hcryp->CrypOutCount -= 16;
+
+ /* Check if all input text is decrypted */
+ if(hcryp->CrypOutCount == 0)
+ {
+ /* Disable Computation Complete Interrupt */
+ __HAL_CRYP_DISABLE_IT(AES_IT_CC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call computation complete callback */
+ HAL_CRYP_ComputationCpltCallback(hcryp);
+ }
+ else /* Process the rest of input text */
+ {
+ /* Get the last Intput data adress */
+ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ hcryp->pCrypInBuffPtr += 16;
+ hcryp->CrypInCount -= 16;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16.
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pPlainData;
+ outputaddr = (uint32_t)pCypherData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Set the CRYP peripheral in AES ECB mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Reset the CHMOD & MODE bits & */
+ AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK);
+
+ /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param pCypherData: Pointer to the cyphertext buffer
+ * @param Size: Length of the plaintext buffer, must be a multiple of 16
+ * @param pPlainData: Pointer to the plaintext buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+ uint32_t inputaddr;
+ uint32_t outputaddr;
+
+ if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcryp);
+
+ inputaddr = (uint32_t)pCypherData;
+ outputaddr = (uint32_t)pPlainData;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
+
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ {
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.pKey);
+
+ /* Set the CRYP peripheral in AES CTR mode */
+ __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
+
+ /* Set the Initialization Vector */
+ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+
+ /* Set the phase */
+ hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ }
+
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CRYP_Group3 DMA callback functions
+ * @brief DMA callback functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### DMA callback functions #####
+ ==============================================================================
+ [..] This section provides DMA callback functions:
+ (+) DMA Input data transfer complete
+ (+) DMA Output data transfer complete
+ (+) DMA error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Input Computation completed callbacks.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_ComputationCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CRYP error callbacks.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input transfer completed callbacks.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_InCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Output transfer completed callbacks.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_OutCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Group4 CRYP IRQ handler
+ * @brief CRYP IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### CRYP IRQ handler management #####
+ ==============================================================================
+[..] This section provides CRYP IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles CRYP interrupt request.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval None
+ */
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
+{
+ switch(AES->CR & CRYP_CR_ALGOMODE_DIRECTION)
+ {
+ case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
+ HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT:
+ HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
+ HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT:
+ HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
+ HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL);
+ break;
+
+ case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
+ HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Group5 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the CRYP state.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval HAL state
+ */
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+{
+ return hcryp->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief DMA CRYP Input Data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable the DMA transfer for input request */
+ AES->CR &= (uint32_t)(~AES_CR_DMAINEN);
+
+ /* Call input data transfer complete callback */
+ HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP Output Data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Disable the DMA transfer for output request by resetting the DOEN bit
+ in the DMACR register */
+ AES->CR &= (uint32_t)(~AES_CR_DMAOUTEN);
+
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE();
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Call output data transfer complete callback */
+ HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+ * @brief DMA CRYP communication error callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ hcryp->State= HAL_CRYP_STATE_READY;
+ HAL_CRYP_ErrorCallback(hcryp);
+}
+
+/**
+ * @brief Writes the Key in Key registers.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Key: Pointer to Key buffer
+ * @param KeySize: Size of Key
+ * @retval None
+ */
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key)
+{
+ uint32_t keyaddr = (uint32_t)Key;
+
+ AES->KEYR3 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ AES->KEYR2 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ AES->KEYR1 = __REV(*(uint32_t*)(keyaddr));
+ keyaddr+=4;
+ AES->KEYR0 = __REV(*(uint32_t*)(keyaddr));
+}
+
+/**
+ * @brief Writes the InitVector/InitCounter in IV registers.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param InitVector: Pointer to InitVector/InitCounter buffer
+ * @param IVSize: Size of the InitVector/InitCounter
+ * @retval None
+ */
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
+{
+ uint32_t ivaddr = (uint32_t)InitVector;
+
+ AES->IVR3 = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ AES->IVR2 = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ AES->IVR1 = __REV(*(uint32_t*)(ivaddr));
+ ivaddr+=4;
+ AES->IVR0 = __REV(*(uint32_t*)(ivaddr));
+}
+
+/**
+ * @brief Process Data: Writes Input data in polling mode and read the output data
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Input: Pointer to the Input buffer
+ * @param Ilength: Length of the Input buffer, must be a multiple of 16.
+ * @param Output: Pointer to the returned buffer
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ uint32_t i = 0;
+ uint32_t inputaddr = (uint32_t)Input;
+ uint32_t outputaddr = (uint32_t)Output;
+
+ for(i=0; (i < Ilength); i+=16)
+ {
+ /* Write the Input block in the Data Input register */
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+ AES->DINR = *(uint32_t*)(inputaddr);
+ inputaddr+=4;
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(AES->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Change state */
+ hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Clear CCF Flag */
+ AES->CR |= AES_CR_CCFC;
+
+ /* Read the Output block from the Data Output Register */
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ *(uint32_t*)(outputaddr) = AES->DOUTR;
+ outputaddr+=4;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the DMA configuration and start the DMA transfer
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr: address of the Input buffer
+ * @param Size: Size of the Input buffer, must be a multiple of 16.
+ * @param outputaddr: address of the Output buffer
+ * @retval None
+ */
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+ /* Set the DMA error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+
+ /* Enable the DMA In DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&AES->DINR, Size/4);
+
+ /* Enable the DMA Out DMA Stream */
+ HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&AES->DOUTR, outputaddr, Size/4);
+
+ /* Enable In and Out DMA requests */
+ AES->CR |= (AES_CR_DMAINEN | AES_CR_DMAOUTEN);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE();
+}
+
+
+
+
+
+
+/**
+ * @}
+ */
+#endif /* STM32L051xx && STM32L052xx && STM32L053xx*/
+#endif /* HAL_CRYP_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cryp.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cryp.h
new file mode 100644
index 0000000000..c6819dd612
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_cryp.h
@@ -0,0 +1,306 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_cryp.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief Header file of CRYP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CRYP_H
+#define __STM32L0xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRYP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief CRYP Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref CRYP_Data_Type */
+
+ uint8_t* pKey; /*!< The key used for encryption/decryption */
+
+ uint8_t* pInitVect; /*!< The initialization vector used also as initialization
+ counter in CTR mode */
+
+}CRYP_InitTypeDef;
+
+/**
+ * @brief HAL CRYP State structures definition
+ */
+typedef enum
+{
+ HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
+ HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
+ HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
+ HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
+ HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
+
+}HAL_CRYP_STATETypeDef;
+
+/**
+ * @brief HAL CRYP phase structures definition
+ */
+typedef enum
+{
+ HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
+ HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */
+}HAL_PhaseTypeDef;
+
+/**
+ * @brief CRYP handle Structure definition
+ */
+typedef struct
+{
+ CRYP_InitTypeDef Init; /*!< CRYP required parameters */
+
+ uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ __IO uint16_t CrypInCount; /*!< Counter of inputed data */
+
+ __IO uint16_t CrypOutCount; /*!< Counter of outputed data */
+
+ HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
+
+ HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
+
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
+
+}CRYP_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CRYP_Data_Type
+ * @{
+ */
+#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)
+#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0
+#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1
+#define CRYP_DATATYPE_1B AES_CR_DATATYPE
+
+#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
+ ((DATATYPE) == CRYP_DATATYPE_16B) || \
+ ((DATATYPE) == CRYP_DATATYPE_8B) || \
+ ((DATATYPE) == CRYP_DATATYPE_1B))
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_AlgoModeDirection
+ * @{
+ */
+#define CRYP_CR_ALGOMODE_DIRECTION (uint32_t)(AES_CR_MODE|AES_CR_CHMOD)
+
+#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT (AES_CR_MODE)
+#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT (AES_CR_CHMOD_0)
+#define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE))
+#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT (AES_CR_CHMOD_1)
+#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)(AES_CR_CHMOD_1 | AES_CR_MODE_1))
+/**
+ * @}
+ */
+
+/** @defgroup AES_Interrupts
+ * @{
+ */
+#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */
+#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */
+
+#define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup AES_Flags
+ * @{
+ */
+#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */
+#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */
+#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */
+
+#define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF) || \
+ ((FLAG) == AES_FLAG_RDERR) || \
+ ((FLAG) == AES_FLAG_WRERR))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset CRYP handle state
+ * @param __HANDLE__: specifies the CRYP Handle.
+ * @retval None
+ */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+
+/**
+ * @brief Enable/Disable the CRYP peripheral.
+ * @param None
+ * @retval None
+ */
+#define __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN)
+#define __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN)
+
+/**
+ * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,...
+ * @param MODE: The algorithm mode.
+ * @retval None
+ */
+#define __HAL_CRYP_SET_MODE(MODE) (AES->CR |= (uint32_t)(MODE))
+
+
+/** @brief Check whether the specified CRYP flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg AES_FLAG_CCF : Computation Complete Flag
+ * @arg AES_FLAG_RDERR : Read Error Flag
+ * @arg AES_FLAG_WRERR : Write Error Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Enable the CRYP interrupt.
+ * @param __INTERRUPT__: CRYP Interrupt.
+ * @retval None
+ */
+#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the CRYP interrupt.
+ * @param __INTERRUPT__: CRYP interrupt.
+ * @retval None
+ */
+#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions *********************************/
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+
+/* AES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* Processing functions ********************************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+/* Peripheral State functions **************************************************/
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+
+/* MSP functions *************************************************************/
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+
+/* CallBack functions ********************************************************/
+void HAL_CRYP_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+
+#endif /* STM32L051xx && STM32L052xx && STM32L053xx*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CRYP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac.c
new file mode 100644
index 0000000000..fa8164a428
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac.c
@@ -0,0 +1,770 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_dac.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief DAC HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Digital to Analog Converter (DAC) peripheral:
+ * + DAC channels configuration: trigger, output buffer, data format
+ * + DMA management
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### DAC Peripheral features #####
+ ==============================================================================
+ [..]
+ *** DAC Channels ***
+ ====================
+ [..]
+ The device integrates 1 12-bit Digital Analog Converters:
+ (#) DAC channel1 with DAC_OUT1 (PA4) as output
+
+ *** DAC Triggers ***
+ ====================
+ [..]
+ Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+ and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
+ [..]
+ Digital to Analog conversion can be triggered by:
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+ The used pin (GPIOx_Pin9) must be configured in input mode.
+
+ (#) Timers TRGO: TIM2, TIM6 and TIM21
+ (DAC_Trigger_T2_TRGO, DAC_Trigger_T6_TRGO...)
+
+ (#) Software using DAC_Trigger_Software
+
+ *** DAC Buffer mode feature ***
+ ===============================
+ [..]
+ Each DAC channel integrates an output buffer that can be used to
+ reduce the output impedance, and to drive external loads directly
+ without having to add an external operational amplifier.
+ To enable, the output buffer use
+ sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+ [..]
+ (@) Refer to the device datasheet for more details about output
+ impedance value with and without output buffer.
+
+ *** DAC wave generation feature ***
+ ===================================
+ [..]
+ Both DAC channels can be used to generate
+ (#) Noise wave using HAL_DAC_NoiseWaveGenerate()
+ (#) Triangle wave using HAL_DAC_TriangleWaveGenerate()
+
+ *** DAC data format ***
+ =======================
+ [..]
+ The DAC data format can be:
+ (#) 8-bit right alignment using DAC_ALIGN_8B_R
+ (#) 12-bit left alignment using DAC_ALIGN_12B_L
+ (#) 12-bit right alignment using DAC_ALIGN_12B_R
+
+ *** DAC data value to voltage correspondence ***
+ ================================================
+ [..]
+ The analog output voltage on each DAC channel pin is determined
+ by the following equation:
+ DAC_OUTx = VREF+ * DOR / 4095
+ with DOR is the Data Output Register
+ VEF+ is the input voltage reference (refer to the device datasheet)
+ e.g. To set DAC_OUT1 to 0.7V, use
+ Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+ *** DMA requests ***
+ =====================
+ [..]
+ A DMA1 request can be generated when an external trigger (but not
+ a software trigger) occurs if DMA1 requests are enabled using
+ HAL_DAC_Start_DMA()
+ [..]
+ DMA1 requests are mapped as following:
+ (#) DAC channel1 : mapped on DMA1 Request9 channel2 which must be
+ already configured
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) DAC APB clock must be enabled to get write access to DAC
+ registers using HAL_DAC_Init()
+ (+) Configure DAC_OUTx (DAC_OUT1: PA4) in analog mode.
+ (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+ (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#if !defined (STM32L051xx) && !defined (STM32L061xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+ * @{
+ */
+
+/** @defgroup DAC_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DAC.
+ (+) De-initialize the DAC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified parameters
+ * in the DAC_InitStruct.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ if(hdac->State == HAL_DAC_STATE_RESET)
+ {
+ /* Init the low level hardware */
+ HAL_DAC_MspInit(hdac);
+ }
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_DAC_MspDeInit(hdac);
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the DAC MSP.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the DAC MSP.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Group2 I/O operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripharal */
+ __HAL_DAC_ENABLE(hdac, channel);
+
+ /* Check if software trigger enabled */
+ if(((hdac->Instance->CR & DAC_CR_TEN1) == DAC_CR_TEN1) && ((hdac->Instance->CR & DAC_CR_TSEL1) == DAC_CR_TSEL1))
+ {
+ /* Enable the selected DAC software conversion */
+ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
+ }
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(channel));
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables DAC and starts conversion of channel using DMA.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @param pData: The destination peripheral Buffer address.
+ * @param Length: The length of data to be transferred from memory to DAC peripheral
+ * @param alignment: Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t* pData, uint32_t Length, uint32_t alignment)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(channel));
+ assert_param(IS_DAC_ALIGN(alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ hdac->Instance->CR |= DAC_CR_DMAEN1;
+
+ /* Case of use of channel 1 */
+ switch(alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the DMA Channel */
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+
+ /* Enable the Peripharal */
+ __HAL_DAC_ENABLE(hdac, channel);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel using DMA.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(channel));
+
+ /* Disable the selected DAC channel DMA request */
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << channel);
+
+ /* Disable the Peripharal */
+ __HAL_DAC_DISABLE(hdac, channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(channel));
+
+ /* Returns the DAC channel data output register value */
+ return hdac->Instance->DOR1;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels.
+ (+) Set the specified data holding register value for DAC channel.
+ (+) Set the specified data holding register value for Dual DAC channels.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig: DAC configuration structure.
+ * @param channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t channel)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Get the DAC CR value */
+ tmpreg1 = DAC->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << channel);
+ /* Configure for the selected DAC channel: buffer output, trigger */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value */
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << channel;
+ /* Write to DAC CR */
+ DAC->CR = tmpreg1;
+ /* Disable wave generation */
+ DAC->CR &= ~(DAC_CR_WAVE1 << channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param alignment: Specifies the data alignment for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param data: Data to be loaded in the selected data holding register.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(channel));
+ assert_param(IS_DAC_ALIGN(alignment));
+ assert_param(IS_DAC_DATA(data));
+
+ tmp = (uint32_t)DAC_BASE;
+
+ tmp += __HAL_DHR12R1_ALIGNEMENT(alignment);
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Group4 DAC Peripheral State functions
+ * @brief DAC Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### DAC Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DAC state.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the DAC state
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL state
+ */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
+{
+ /* Return DAC state */
+ return hdac->State;
+}
+
+/**
+ * @brief Handles DAC interrupt request
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+ /* Check Overrun flag */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to chanel1 DMA underrun error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+ /* Disable the selected DAC channel1 DMA request */
+ hdac->Instance->CR &= ~DAC_CR_DMAEN1;
+
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
+}
+
+/**
+ * @brief Return the DAC error code
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval DAC Error Code
+ */
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+{
+ return hdac->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel1
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel1.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ErrorCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief DMA underrun DAC callback for channel1.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DAC_ConvCpltCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Conversion complete callback */
+ HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DAC_ErrorCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32L051xx && STM32L061xx*/
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac.h
new file mode 100644
index 0000000000..98e160146d
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac.h
@@ -0,0 +1,283 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_dac.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief Header file of DAC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_DAC_H
+#define __STM32L0xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined (STM32L051xx) && !defined (STM32L061xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
+ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
+
+}HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
+ */
+typedef struct
+{
+ DAC_TypeDef *Instance; /*!< Register base address */
+
+ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
+
+ HAL_LockTypeDef Lock; /*!< DAC locking object */
+
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
+
+ __IO uint32_t ErrorCode; /*!< DAC Error code */
+
+}DAC_HandleTypeDef;
+
+/**
+ * @brief DAC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+
+}DAC_ChannelConfTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL DAC Error Code
+ * @{
+ */
+#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
+#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_trigger_selection
+ * @{
+ */
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T21_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM21 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T21_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer
+ * @{
+ */
+#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
+
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
+
+#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignement
+ * @{
+ */
+#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
+#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
+#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+/**
+ * @}
+ */
+
+
+/** @defgroup DAC_data
+ * @{
+ */
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition
+ * @{
+ */
+#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+
+#define IS_DAC_FLAG(FLAG) ((FLAG) == DAC_FLAG_DMAUDR1)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition
+ * @{
+ */
+#define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
+
+#define IS_DAC_IT(IT) ((IT) == DAC_IT_DMAUDR1)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DAC handle state
+ * @param __HANDLE__: specifies the DAC Handle.
+ * @retval None
+ */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/* Enable the DAC peripheral */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/* Disable the DAC peripheral */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+
+
+/* Set DHR12R1 alignment */
+#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
+
+/* Enable the DAC interrupt */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/* Disable the DAC interrupt */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/* Get the selected DAC's flag status */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/* Clear the DAC's flag */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) |= (__FLAG__))
+
+/* Include DAC HAL Extension module */
+#include "stm32l0xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t* pData, uint32_t Length, uint32_t alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t channel);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t channel);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data);
+
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+#endif /* STM32L051xx && STM32L061xx*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*__STM32L0xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac_ex.c
new file mode 100644
index 0000000000..8e1efdbaf5
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac_ex.c
@@ -0,0 +1,202 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_dac_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief DAC HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Digital to Analog Converter (DAC) peripheral:
+ * + DAC wave generation
+ *
+ @verbatim
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DACEx
+ * @brief DAC driver modules
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#if !defined (STM32L051xx) && !defined (STM32L061xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Functions
+ * @{
+ */
+
+
+/** @defgroup DACEx_Group Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Triangle wave generation.
+ (+) Configure Noise wave generation.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the selected DAC channel wave triangle generation.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @param Amplitude: Select max triangle amplitude.
+ * This parameter can be one of the following values:
+ * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+ * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+ * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+ * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+ * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+ * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+ * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+ * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+ * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+ * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ hdac->Instance->CR |= (DAC_WAVEGENERATION_TRIANGLE | Amplitude) << channel;
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave noise generation.
+ * @param channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
+ * This parameter can be one of the following values:
+ * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ hdac->Instance->CR |= (DAC_WAVEGENERATION_NOISE | Amplitude) << channel;
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32L051xx && STM32L061xx*/
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac_ex.h
new file mode 100644
index 0000000000..b32b6b30b7
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dac_ex.h
@@ -0,0 +1,160 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_dac_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief Header file of DAC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_DAC_EX_H
+#define __STM32L0xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined (STM32L051xx) && !defined (STM32L061xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DACEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DACEx_wave_generation
+ * @{
+ */
+#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000)
+#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
+ ((WAVE) == DAC_WAVEGENERATION_NOISE) || \
+ ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude
+ * @{
+ */
+#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Peripheral Control methods *************************************************/
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude);
+
+#endif /* STM32L051xx && STM32L061xx*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*__STM32L0xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_def.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_def.h
new file mode 100644
index 0000000000..cd797a0767
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_def.h
@@ -0,0 +1,180 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_def.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_DEF
+#define __STM32L0xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00,
+ HAL_ERROR = 0x01,
+ HAL_BUSY = 0x02,
+ HAL_TIMEOUT = 0x03
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00,
+ HAL_LOCKED = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#ifndef NULL
+ #define NULL (void *) 0
+#endif
+
+#define HAL_MAX_DELAY 0xFFFFFFFF
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \
+ } while(0)
+
+#if (USE_RTOS == 1)
+
+#else
+ #define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0)
+
+ #define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ )
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__GNUC__) /* GNU Compiler */
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif /* __ALIGN_BEGIN */
+#else
+ #ifndef __ALIGN_END
+ #define __ALIGN_END
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #if defined (__CC_ARM) /* ARM Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #elif defined (__ICCARM__) /* IAR Compiler */
+ #define __ALIGN_BEGIN
+ #elif defined (__TASKING__) /* TASKING Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #endif /* __CC_ARM */
+ #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief __RAM_FUNC definition
+ */
+#if defined ( __CC_ARM )
+/* ARM Compiler
+ ------------
+ RAM functions are defined using the toolchain options.
+ Functions that are executed in RAM should reside in a separate source module.
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'
+ area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+ dialog.
+*/
+#define __RAM_FUNC HAL_StatusTypeDef
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
+
+#elif defined ( __GNUC__ )
+/* GNU Compiler
+ ------------
+ RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32L0xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dma.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dma.c
new file mode 100644
index 0000000000..960f4f4a84
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dma.c
@@ -0,0 +1,762 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_dma.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief DMA HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral State functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Channel
+ (except for internal SRAM / FLASH memories: no initialization is
+ necessary).
+
+ (#) For a given Channel, program the required configuration through the following parameters:
+ Channel request, Transfer Direction, Source and Destination data formats,
+ Circular, Normal or peripheral flow control mode, Channel Priority level,
+ Source and Destination Increment mode using HAL_DMA_Init() function.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred. In this
+ case the DMA interrupt is configured
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of DMA handle structure).
+
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ detection.
+
+ (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Private_Functions
+ * @{
+ */
+
+/** @defgroup DMA_Group1 Initialization/de-initialization functions
+ * @brief Initialization/de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DMA
+ (+) De-Initialize the DMA
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and create the associated handle.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tmp = 0;
+
+ /* Check the DMA peripheral state */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(hdma->Instance));
+ assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Get the CR register value */
+ tmp = hdma->Instance->CCR;
+
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
+ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
+ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
+ DMA_CCR_DIR));
+
+ /* Prepare the DMA Channel configuration */
+ tmp |= hdma->Init.Direction |
+ hdma->Init.PeriphInc | hdma->Init.MemInc |
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ hdma->Init.Mode | hdma->Init.Priority;
+
+ /* Write to DMA Channel CR register */
+ hdma->Instance->CCR = tmp;
+
+ /* Write to DMA channel selection register */
+ if (hdma->Instance == DMA1_Channel1)
+ {
+ /*Reset request selection for DMA1 Channel1*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
+
+ /* Configure request selection for DMA1 Channel1 */
+ DMA1_CSELR->CSELR |= hdma->Init.Request;
+ }
+ else if (hdma->Instance == DMA1_Channel2)
+ {
+ /*Reset request selection for DMA1 Channel2*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
+
+ /* Configure request selection for DMA1 Channel2 */
+ DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4);
+ }
+ else if (hdma->Instance == DMA1_Channel3)
+ {
+ /*Reset request selection for DMA1 Channel3*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
+
+ /* Configure request selection for DMA1 Channel3 */
+ DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8);
+ }
+ else if (hdma->Instance == DMA1_Channel4)
+ {
+ /*Reset request selection for DMA1 Channel4*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
+
+ /* Configure request selection for DMA1 Channel4 */
+ DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12);
+ }
+ else if (hdma->Instance == DMA1_Channel5)
+ {
+ /*Reset request selection for DMA1 Channel5*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
+
+ /* Configure request selection for DMA1 Channel5 */
+ DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16);
+ }
+ else if (hdma->Instance == DMA1_Channel6)
+ {
+ /*Reset request selection for DMA1 Channel6*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
+
+ /* Configure request selection for DMA1 Channel6 */
+ DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20);
+ }
+ else if (hdma->Instance == DMA1_Channel7)
+ {
+ /*Reset request selection for DMA1 Channel7*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
+
+ /* Configure request selection for DMA1 Channel7 */
+ DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24);
+ }
+
+ /* Initialize the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the DMA peripheral
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+ /* Check the DMA peripheral state */
+ if(hdma->State == HAL_DMA_STATE_BUSY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the selected DMA Channelx */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Reset DMA Channel control register */
+ hdma->Instance->CCR = 0;
+
+ /* Reset DMA Channel Number of Data to Transfer register */
+ hdma->Instance->CNDTR = 0;
+
+ /* Reset DMA Channel peripheral address register */
+ hdma->Instance->CPAR = 0;
+
+ /* Reset DMA Channel memory address register */
+ hdma->Instance->CMAR = 0;
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Reset DMA channel selection register */
+ if (hdma->Instance == DMA1_Channel1)
+ {
+ /*Reset DMA request*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
+ }
+ else if (hdma->Instance == DMA1_Channel2)
+ {
+ /*Reset DMA request*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
+ }
+ else if (hdma->Instance == DMA1_Channel3)
+ {
+ /*Reset DMA request*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
+ }
+ else if (hdma->Instance == DMA1_Channel4)
+ {
+ /*Reset DMA request*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
+ }
+ else if (hdma->Instance == DMA1_Channel5)
+ {
+ /*Reset DMA request*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
+ }
+ else if (hdma->Instance == DMA1_Channel6)
+ {
+ /*Reset DMA request*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
+ }
+ else if (hdma->Instance == DMA1_Channel7)
+ {
+ /*Reset DMA request*/
+ DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
+ }
+
+ /* Initialise the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Group2 I/O operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start DMA transfer with interrupt
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the DMA Transfer with interrupt enabled.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
+
+ /* Enable the Half transfer complete interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+
+ /* Enable the transfer Error interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Aborts the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tickstart = 0;
+
+ /* Disable the channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Check if the DMA Channel is effectively disabled */
+ while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
+ {
+ /* Check for the Timeout */
+ if((int32_t) (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param CompleteLevel: Specifies the DMA level complete.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart = 0;
+
+ /* Get the level transfer complete flag */
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Transfer Complete flag */
+ temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+ }
+ else
+ {
+ /* Half Transfer Complete flag */
+ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+ {
+ if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
+ {
+ /* Clear the transfer error flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+ /* Change the DMA state */
+ hdma->State= HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((int32_t) (HAL_GetTick() - tickstart ) > Timeout)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers are complete) */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+ }
+ else
+ {
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers are complete) */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @brief Handles DMA interrupt request.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ /* Transfer Error Interrupt management ***************************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+ {
+ /* Disable the transfer error interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
+
+ /* Clear the transfer error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ }
+
+ /* Half Transfer Complete Interrupt management ******************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+ {
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable the half transfer interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ }
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ }
+
+ /* Transfer Complete Interrupt management ***********************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+ {
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable the transfer complete interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
+ }
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the DMA state.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA error code
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+ return hdma->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Group4 Extanded feature functions
+ * @brief Extanded feature functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extanded feature functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Configure the source, destination address and data length
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Sets the DMA Transfer parameter.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Configure DMA Channel data length */
+ hdma->Instance->CNDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CPAR = DstAddress;
+
+ /* Configure DMA Channel source address */
+ hdma->Instance->CMAR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Channel source address */
+ hdma->Instance->CPAR = SrcAddress;
+
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CMAR = DstAddress;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dma.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dma.h
new file mode 100644
index 0000000000..0549a8ae9a
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_dma.h
@@ -0,0 +1,542 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_dma.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_DMA_H
+#define __STM32L0xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Request; /*!< Specifies the request selected for the specified channel.
+ This parameter can be a value of @ref DMA_request */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref Priority_level */
+} DMA_InitTypeDef;
+
+/**
+ * @brief DMA Configuration enumeration values definition
+ */
+typedef enum
+{
+ DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
+ DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
+
+} DMA_ControlTypeDef;
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
+ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
+ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+ HAL_DMA_STATE_READY_HALF = 0x05, /*!< DMA Half process success */
+}HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
+
+}HAL_DMA_LevelCompleteTypeDef;
+
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Channel_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
+} DMA_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
+#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+/**
+ * @}
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+ ((PERIPH) == DMA1_Channel2) || \
+ ((PERIPH) == DMA1_Channel3) || \
+ ((PERIPH) == DMA1_Channel4) || \
+ ((PERIPH) == DMA1_Channel5) || \
+ ((PERIPH) == DMA1_Channel6) || \
+ ((PERIPH) == DMA1_Channel7))
+
+#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_request
+ * @{
+ */
+#define DMA_REQUEST_0 ((uint32_t)0x00000000)
+#define DMA_REQUEST_1 ((uint32_t)0x00000001)
+#define DMA_REQUEST_2 ((uint32_t)0x00000002)
+#define DMA_REQUEST_3 ((uint32_t)0x00000003)
+#define DMA_REQUEST_4 ((uint32_t)0x00000004)
+#define DMA_REQUEST_5 ((uint32_t)0x00000005)
+#define DMA_REQUEST_6 ((uint32_t)0x00000006)
+#define DMA_REQUEST_7 ((uint32_t)0x00000007)
+#define DMA_REQUEST_8 ((uint32_t)0x00000008)
+#define DMA_REQUEST_9 ((uint32_t)0x00000009)
+#define DMA_REQUEST_11 ((uint32_t)0x0000000B)
+
+#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
+ ((REQUEST) == DMA_REQUEST_1) || \
+ ((REQUEST) == DMA_REQUEST_2) || \
+ ((REQUEST) == DMA_REQUEST_3) || \
+ ((REQUEST) == DMA_REQUEST_4) || \
+ ((REQUEST) == DMA_REQUEST_5) || \
+ ((REQUEST) == DMA_REQUEST_6) || \
+ ((REQUEST) == DMA_REQUEST_7) || \
+ ((REQUEST) == DMA_REQUEST_8) || \
+ ((REQUEST) == DMA_REQUEST_9) || \
+ ((REQUEST) == DMA_REQUEST_11))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_buffer_size
+ * @{
+ */
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_Memory_data_size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode
+ * @{
+ */
+#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level
+ * @{
+ */
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_interrupt_enable_definitions
+ * @{
+ */
+
+#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions
+ * @{
+ */
+
+#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Enable the specified DMA Channel.
+ * @param __HANDLE__: DMA handle
+ * @retval None.
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
+
+/**
+ * @brief Disable the specified DMA Channel.
+ * @param __HANDLE__: DMA handle
+ * @retval None.
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
+
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ DMA_FLAG_TC7)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ DMA_FLAG_HT7)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ DMA_FLAG_TE7)
+
+/**
+ * @brief Returns the current DMA Channel Global interrupt flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
+ DMA_ISR_GIF7)
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag
+ * @arg DMA_FLAG_TEIFx: Transfer error flag
+ * @arg DMA_ISR_GIFx: Global interrupt flag
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag
+ * @arg DMA_FLAG_TEIFx: Transfer error flag
+ * @arg DMA_ISR_GIFx: Global interrupt flag
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__))
+
+/**
+ * @brief Enables the specified DMA Channel interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified DMA Channel interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval The state of DMA_IT (SET or RESET).
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash.c
new file mode 100644
index 0000000000..aa587d1093
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash.c
@@ -0,0 +1,710 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_flash.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + FLASH Interface configuration
+ * + FLASH Memory Programming
+ * + DATA EEPROM Programming
+ * + Option Bytes Programming
+ * + Interrupts and flags management
+ *
+ * @verbatim
+
+ ==============================================================================
+ ##### FLASH peripheral features #####
+ ==============================================================================
+
+ [..] The Flash memory interface manages CPU accesses to the Flash memory.
+ It implements the erase and program Flash memory operations
+ and the read and write protection mechanisms.
+
+ [..] The FLASH main features are:
+ (+) Flash memory read operations
+ (+) Flash memory program/erase operations
+ (+) Read / write protections
+ (+) Option Bytes programming
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions and macros to configure and program the FLASH
+ memory of all STM32L0xx devices.
+
+ (#) FLASH Memory IO Programming functions:
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+ HAL_FLASH_Lock() functions
+ (++) Program functions: byte, half word and word
+ (++) There Two modes of programming :
+ (+++) Polling mode using HAL_FLASH_Program() function
+ (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+ (#) Interrupts and flags management functions :
+ (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+ (++) Wait for last FLASH operation according to its status
+ (++) Get error flag status by calling HAL_GetErrorCode()
+
+ [..]
+ In addition to these functions, this driver includes a set of macros allowing
+ to handle the following operations:
+ (+) Set the latency
+ (+) Enable/Disable the prefetch buffer
+ (+) Enable/Disable the preread buffer
+ (+) Enable/Disable the Flash power-down
+ (+) Enable/Disable the FLASH interrupts
+ (+) Monitor the FLASH flags status
+
+ ===============================================================================
+ ##### Programming operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FLASH
+ program operations.
+
+ [..] The FLASH Memory Programming functions, includes the following functions:
+ (+) HAL_FLASH_Unlock(void);
+ (+) HAL_FLASH_Lock(void);
+ (+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
+ (+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
+
+ [..] Any operation of erase or program should follow these steps:
+ (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
+ program memory access.
+ (#) Call the desired function to erase page or program data.
+ (#) Call the HAL_FLASH_Lock() to disable the flash program memory access
+ (recommended to protect the FLASH memory against possible unwanted operation).
+
+ ==============================================================================
+ ##### Option Bytes Programming functions #####
+ ==============================================================================
+
+ [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
+ (+) HAL_FLASH_OB_Unlock(void);
+ (+) HAL_FLASH_OB_Lock(void);
+ (+) HAL_FLASH_OB_Launch(void);
+ (+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+ (+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+ [..] Any operation of erase or program should follow these steps:
+ (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control
+ register access.
+ (#) Call the following functions to program the desired option bytes.
+ (++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+ (#) Once all needed option bytes to be programmed are correctly written, call the
+ HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
+ (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended
+ to protect the option Bytes against possible unwanted operations).
+
+ [..] Proprietary code Read Out Protection (PcROP):
+ (#) The PcROP sector is selected by using the same option bytes as the Write
+ protection (nWRPi bits). As a result, these 2 options are exclusive each other.
+ (#) In order to activate the PcROP (change the function of the nWRPi option bits),
+ the SPRMOD option bit must be activated.
+ (#) The active value of nWRPi bits is inverted when PCROP mode is active, this
+ means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user page "i"
+ is read/write protected.
+ (#) To activate PCROP mode for Flash page(s), you need to follow the sequence below:
+ (++) For page(s) within the first 64KB of the Flash, use this function
+ HAL_FLASHEx_AdvOBProgram with PCROPState = PCROPSTATE_ENABLE.
+
+
+ * @endverbatim
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)0xFFFF0)
+
+/* FLASH Mask */
+#define WRP01_MASK ((uint32_t)0x0000FFFF)
+#define PAGESIZE ((uint32_t)0x00000080)
+
+/* Private macro -------------------------------------------------------------*/
+/*Variables used for Erase sectors under interruption*/
+FLASH_ProcessTypeDef pFlash;
+
+/* Private function prototypes -----------------------------------------------*/
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+static void FLASH_SetErrorCode(void);
+static HAL_StatusTypeDef DATA_EEPROM_Unlock(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FLASH_Private_Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Group1 Programming operation functions
+ * @brief Programming operation functions
+ *
+@verbatim
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Program word at a specified address
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_TYPEPROGRAM(TypeProgram));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ if(TypeProgram == TYPEPROGRAM_WORD)
+ {
+ /*Program word (32-bit) at a specified address.*/
+ FLASH_Program_Word(Address, (uint32_t) Data);
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+ /* Reset PROG bit */
+ FLASH->PECR &= ~FLASH_PECR_PROG;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Program word at a specified address with interrupt enabled.
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_TYPEPROGRAM(TypeProgram));
+
+ /* Enable End of FLASH Operation interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+
+ /* Enable Error source interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+
+ /* Clear pending flags (if any) */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR |\
+ FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR| FLASH_FLAG_OPTVERR |\
+ FLASH_FLAG_RDERR | FLASH_FLAG_NOTZEROERR);
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+ pFlash.Address = Address;
+
+ if(TypeProgram == TYPEPROGRAM_WORD)
+ {
+ /*Program word (32-bit) at a specified address.*/
+ FLASH_Program_Word(Address, (uint32_t) Data);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief This function handles FLASH interrupt request.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void)
+{
+ uint32_t temp;
+
+ /* If the program operation is completed, disable the PROG Bit */
+ FLASH->PECR &= (~FLASH_PECR_PROG);
+
+ /* If the erase operation is completed, disable the ERASE Bit */
+ FLASH->PECR &= (~FLASH_PECR_ERASE);
+
+ /* Check FLASH End of Operation flag */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /*Nb of sector to erased can be decreased*/
+ pFlash.NbPagesToErase--;
+
+ /* Check if there are still sectors to erase*/
+ if(pFlash.NbPagesToErase != 0)
+ {
+ temp = pFlash.Page;
+ /*Indicate user which sector has been erased*/
+ HAL_FLASH_EndOfOperationCallback(temp);
+
+ /* Clear pending flags (if any) */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR |\
+ FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR| FLASH_FLAG_OPTVERR |\
+ FLASH_FLAG_RDERR | FLASH_FLAG_NOTZEROERR);
+
+ /*Increment sector number*/
+ temp = pFlash.Page + PAGESIZE;
+ pFlash.Page = pFlash.Page + PAGESIZE;
+ FLASH_Erase_Page(temp);
+ }
+ else
+ {
+ /*No more sectors to Erase, user callback can be called.*/
+ /*Reset Sector and stop Erase sectors procedure*/
+ pFlash.Page = temp = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(temp);
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+ }
+ else
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM)
+ {
+ /*Program ended. Return the selected address*/
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+
+ }
+ /* Check FLASH operation error flags */
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR |\
+ FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR| FLASH_FLAG_OPTVERR |\
+ FLASH_FLAG_RDERR | FLASH_FLAG_NOTZEROERR)))
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /*return the faulty sector*/
+ temp = pFlash.Page;
+ pFlash.Page = 0xFFFFFFFF;
+ }
+ else
+ {
+ /*retrun the faulty address*/
+ temp = pFlash.Address;
+ }
+
+ /*Save the Error code*/
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(temp);
+ /* Clear FLASH error pending bits */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR |\
+ FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR| FLASH_FLAG_OPTVERR |\
+ FLASH_FLAG_RDERR | FLASH_FLAG_NOTZEROERR);
+
+ /*Stop the procedure ongoing*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+ {
+ /* Disable End of FLASH Operation interrupt */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
+
+ /* Disable Error source interrupt */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+
+}
+
+/**
+ * @brief FLASH end of operation interrupt callback
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * - Pages Erase: Sector which has been erased
+ * (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FLASH operation error interrupt callback
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * - Pagess Erase: Sector number which returned an error
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Group2 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Unlock the FLASH control register access
+ * @param None
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET)
+ {
+ /* Unlocking the data memory and FLASH_PECR register access */
+ DATA_EEPROM_Unlock();
+
+ /* Unlocking the program memory access */
+ FLASH->PRGKEYR = FLASH_PRGKEY1;
+ FLASH->PRGKEYR = FLASH_PRGKEY2;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Locks the FLASH control register access
+ * @param None
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ /* Set the PRGLOCK Bit to lock the program memory access */
+ FLASH->PECR |= FLASH_PECR_PRGLOCK;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Unlock the FLASH Option Control Registers access.
+ * @param None
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+ if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET)
+ {
+ /* Unlocking the data memory and FLASH_PECR register access */
+ DATA_EEPROM_Unlock();
+
+ /* Unlocking the option bytes block access */
+ FLASH->OPTKEYR = FLASH_OPTKEY1;
+ FLASH->OPTKEYR = FLASH_OPTKEY2;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Lock the FLASH Option Control Registers access.
+ * @param None
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+ /* Set the OPTLOCK Bit to lock the option bytes block access */
+ FLASH->PECR |= FLASH_PECR_OPTLOCK;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @param None
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+ /* Set the OBL_Launch bit to lauch the option byte loading */
+ FLASH->PECR |= FLASH_PECR_OBL_LAUNCH;
+
+ /* Wait for last operation to be completed */
+ return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+}
+
+/**
+ * @brief Unlocks the data memory and FLASH_PECR register access.
+ * @param None
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+static HAL_StatusTypeDef DATA_EEPROM_Unlock(void)
+{
+ if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)
+ {
+ /* Unlocking the Data memory and FLASH_PECR register access*/
+ FLASH->PEKEYR = FLASH_PEKEY1;
+ FLASH->PEKEYR = FLASH_PEKEY2;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Group3 Peripheral State and Errors functions
+ * @brief Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the specific FLASH error flag.
+ * @param None
+ * @retval FLASH_ErrorCode: The returned value can be:
+ * @arg FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+ * @arg FLASH_ERROR_ENDHV: FLASH Programming Sequence error flag
+ * @arg FLASH_ERROR_SIZE: FLASH Programming Parallelism error flag
+ * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+ * @arg FLASH_ERROR_WRP: FLASH Write protected error flag
+ * @arg FLASH_ERROR_OPTV: FLASH Option valid error flag
+ * @arg FLASH_ERROR_NOTZERO: FLASH write operation is done in a not-erased region
+ */
+FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
+{
+ return pFlash.ErrorCode;
+}
+
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout: maximum flash operationtimeout
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+
+ tickstart = HAL_GetTick();
+
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((HAL_GetTick() - tickstart ) > Timeout)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_OPTVERR |\
+ FLASH_FLAG_RDERR | FLASH_FLAG_NOTZEROERR)))
+ {
+ /*Save the error code*/
+ FLASH_SetErrorCode();
+ return HAL_ERROR;
+ }
+
+ /* If there is an error flag set */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the specific FLASH error flag.
+ * @param None
+ * @retval None
+ */
+static void FLASH_SetErrorCode(void)
+{
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ENDHV))
+ {
+ pFlash.ErrorCode = FLASH_ERROR_ENDHV;
+ }
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+ {
+ pFlash.ErrorCode = FLASH_ERROR_WRP;
+ }
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
+ {
+ pFlash.ErrorCode = FLASH_ERROR_PGA;
+ }
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
+ {
+ pFlash.ErrorCode = FLASH_ERROR_SIZE;
+ }
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
+ {
+ pFlash.ErrorCode = FLASH_ERROR_OPTV;
+ }
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
+ {
+ pFlash.ErrorCode = FLASH_ERROR_RD;
+ }
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR))
+ {
+ pFlash.ErrorCode = FLASH_ERROR_NOTZERO;
+ }
+}
+
+/**
+ * @brief Erases a specified page in program memory.
+ * @note To correctly run this function, the HAL_FLASH_Unlock() function
+ * must be called before.
+ * Call the HAL_FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param Page_Address: The page address in program memory to be erased.
+ * @note A Page is erased in the Program memory only if the address to load
+ * is the start address of a page (multiple of 256 bytes).
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+void FLASH_Erase_Page(uint32_t Page_Address)
+{
+ /* Set the ERASE bit */
+ FLASH->PECR |= FLASH_PECR_ERASE;
+
+ /* Set PROG bit */
+ FLASH->PECR |= FLASH_PECR_PROG;
+
+ /* Write 00000000h to the first word of the program page to erase */
+ *(__IO uint32_t *)Page_Address = 0x00000000;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @brief Program word (32-bit) at a specified address.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Set PROG bit */
+ FLASH->PECR |= FLASH_PECR_PROG;
+
+ *(__IO uint32_t*)Address = Data;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+*/
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash.h
new file mode 100644
index 0000000000..fecec662fb
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash.h
@@ -0,0 +1,503 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_flash.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief This file contains all the functions prototypes for the FLASH
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0XX_HAL_FLASH_H
+#define __STM32L0XX_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief FLASH Error structure definition
+ */
+typedef enum
+{
+ FLASH_ERROR_RD = 0x01,
+ FLASH_ERROR_ENDHV = 0x02,
+ FLASH_ERROR_SIZE = 0x04,
+ FLASH_ERROR_PGA = 0x08,
+ FLASH_ERROR_WRP = 0x10,
+ FLASH_ERROR_OPTV = 0x20,
+ FLASH_ERROR_NOTZERO = 0x40
+}FLASH_ErrorTypeDef;
+
+/**
+ * @brief FLASH Procedure structure definition
+ */
+typedef enum
+{
+ FLASH_PROC_NONE = 0,
+ FLASH_PROC_PAGEERASE,
+ FLASH_PROC_PROGRAM
+} FLASH_ProcedureTypeDef;
+
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< TypeErase: Mass erase or sector Erase.
+ This parameter can be a value of @ref FLASH_Type_Erase */
+
+ uint32_t Page; /*!< Sector: Initial FLASH sector to erase when Mass erase is disabled
+ This parameter must be a value of @ref FLASH_Sectors */
+
+ uint32_t NbPages; /*!< NbSectors: Number of sectors to be erased.
+ This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Option Bytes PROGRAM structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+ This parameter can be a value of @ref FLASH_Option_Type */
+
+ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+ This parameter can be a value of @ref FLASH_WRP_State */
+
+ uint32_t WRPSector; /*!< WRPSector: specifies the sector(s) to be write protected
+ The value of this parameter depend on device used within the same series */
+
+ uint32_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+ This parameter can be a value of @ref FLASH_Option_Bytes_Read_Protection */
+
+ uint32_t BORLevel; /*!< BORLevel: Set the BOR Level.
+ This parameter can be a value of @ref Option_Bytes_BOR_Level */
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ This parameter can be a combination of @ref FLASH_Option_Bytes_IWatchdog, @ref FLASH_Option_Bytes_nRST_STOP and @ref FLASH_Option_Bytes_nRST_STDBY*/
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct
+{
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/
+
+ __IO uint32_t NbPagesToErase; /*Internal variable to save the remaining sectors to erase in IT context*/
+
+ __IO uint32_t Page; /*Internal variable to define the current sector which is erasing*/
+
+ __IO uint32_t Address; /*Internal variable to save address selected for program*/
+
+ HAL_LockTypeDef Lock; /* FLASH locking object */
+
+ __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */
+
+}FLASH_ProcessTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Type_Erase FLASH Type Erase
+ * @{
+ */
+#define TYPEERASE_PAGEERASE ((uint32_t)0x00) /*!= 0x08080000) && ((ADDRESS) <= 0x080807FF)) /* 2K */
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF)) /* 64K */
+#define IS_NBPAGES(PAGES) (((PAGES) >= 1) && ((PAGES) <= 512)) /* 512 pages from page0 to page 511 */
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_Write_Protection
+ * @{
+ */
+#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */
+#define OB_WRP_Pages32to63 ((uint32_t)0x00000002) /* Write protection of Sector1 */
+#define OB_WRP_Pages64to95 ((uint32_t)0x00000004) /* Write protection of Sector2 */
+#define OB_WRP_Pages96to127 ((uint32_t)0x00000008) /* Write protection of Sector3 */
+#define OB_WRP_Pages128to159 ((uint32_t)0x00000010) /* Write protection of Sector4 */
+#define OB_WRP_Pages160to191 ((uint32_t)0x00000020) /* Write protection of Sector5 */
+#define OB_WRP_Pages192to223 ((uint32_t)0x00000040) /* Write protection of Sector6 */
+#define OB_WRP_Pages224to255 ((uint32_t)0x00000080) /* Write protection of Sector7 */
+#define OB_WRP_Pages256to287 ((uint32_t)0x00000100) /* Write protection of Sector8 */
+#define OB_WRP_Pages288to319 ((uint32_t)0x00000200) /* Write protection of Sector9 */
+#define OB_WRP_Pages320to351 ((uint32_t)0x00000400) /* Write protection of Sector10 */
+#define OB_WRP_Pages352to383 ((uint32_t)0x00000800) /* Write protection of Sector11 */
+#define OB_WRP_Pages384to415 ((uint32_t)0x00001000) /* Write protection of Sector12 */
+#define OB_WRP_Pages416to447 ((uint32_t)0x00002000) /* Write protection of Sector13 */
+#define OB_WRP_Pages448to479 ((uint32_t)0x00004000) /* Write protection of Sector14 */
+#define OB_WRP_Pages480to511 ((uint32_t)0x00008000) /* Write protection of Sector15 */
+
+#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_Read_Protection
+ * @{
+ */
+
+/**
+ * @brief FLASH_Option_Bytes_Read_Protection
+ */
+#define OB_RDP_Level_0 ((uint8_t)0xAA)
+#define OB_RDP_Level_1 ((uint8_t)0xBB)
+/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
+ it's no more possible to go back to level 1 or 0 */
+
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+ ((LEVEL) == OB_RDP_Level_1))/*||\
+ ((LEVEL) == OB_RDP_Level_2))*/
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_IWatchdog
+ * @{
+ */
+#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STOP
+ * @{
+ */
+#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_BOR_Level
+ * @{
+ */
+
+#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
+ power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
+#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
+#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
+#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
+#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
+#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
+
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \
+ ((LEVEL) == OB_BOR_LEVEL1) || \
+ ((LEVEL) == OB_BOR_LEVEL2) || \
+ ((LEVEL) == OB_BOR_LEVEL3) || \
+ ((LEVEL) == OB_BOR_LEVEL4) || \
+ ((LEVEL) == OB_BOR_LEVEL5))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flags
+ * @{
+ */
+
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
+#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */
+#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
+#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
+#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */
+#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protected error flag */
+#define FLASH_FLAG_NOTZEROERR FLASH_SR_NOTZEROERR /*!< FLASH Read protected error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFED0FF) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+ ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \
+ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \
+ ((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \
+ ((FLAG) == FLASH_FLAG_RDERR) || ((FLAG) == FLASH_FLAG_NOTZEROERR))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Keys
+ * @{
+ */
+
+#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */
+#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1
+ to unlock the RUN_PD bit in FLASH_ACR */
+
+#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */
+#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2
+ to unlock the write access to the FLASH_PECR register and
+ data EEPROM */
+
+#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */
+#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2
+ to unlock the program memory */
+
+#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */
+#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+ unlock the write access to the option byte block */
+/**
+ * @}
+ */
+
+/** @defgroup CMSIS_Legacy
+ * @{
+ */
+#if defined ( __ICCARM__ )
+#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_Interrupt FLASH Interrupt
+ * @brief macros to handle FLASH interrupts
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @param __INTERRUPT__: specifies the FLASH interrupt sources to be enabled or
+ * disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: FLASH end of programming Interrupt
+ * @arg FLASH_IT_ERR: FLASH Error Interrupt
+ * @retval None
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->PECR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->PECR &= ~(uint32_t)(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @param __FLAG__: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode
+ * @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+ * @arg FLASH_FLAG_SIZERR: FLASH size error flag
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+ * @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag
+ * @arg FLASH_FLAG_RDERR: FLASH Read protected error flag
+ * @arg FLASH_FLAG_NOTZEROERR: Not Zero area error flag
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the FLASH's pending flags.
+ * @param __FLAG__: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+ * @arg FLASH_FLAG_SIZERR: FLASH size error flag
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+ * @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag
+ * @arg FLASH_FLAG_RDERR: FLASH Read protected error flag
+ * @arg FLASH_FLAG_NOTZEROERR: Not Zero area error flag
+ * @retval None
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extension module */
+#include "stm32l0xx_hal_flash_ex.h"
+#include "stm32l0xx_hal_flash_ramfunc.h"
+
+/* Exported functions ------------------------------------------------------- */
+
+/**
+ * @brief FLASH memory functions that can be executed from FLASH.
+ */
+/* Program operation functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
+
+/* FLASH IRQ handler function */
+void HAL_FLASH_IRQHandler(void);
+
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+
+/* Peripheral State functions ************************************************/
+FLASH_ErrorTypeDef HAL_FLASH_GetError(void);
+
+/* Non-User functions ********************************************************/
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+void FLASH_Erase_Page(uint32_t Page_Address);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0XX_HAL_FLASH_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash_ex.c
new file mode 100644
index 0000000000..fe1aa4e764
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash_ex.c
@@ -0,0 +1,1177 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_flash_ex.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + FLASH Interface configuration
+ * + FLASH Memory Programming
+ * + DATA EEPROM Programming
+ * + Option Bytes Programming
+ * + Interrupts and flags management
+ *
+ * @verbatim
+ ==============================================================================
+ ##### Flash peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other products, the FLASH interface for STM32L0xx
+ devices contains the following additional features
+ (+) DATA_EEPROM memory management
+ (+) BOOT option bit configuration
+ (+) PCROP protection for all sectors
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the FLASH memory
+ of all STM32L0xx. It includes:
+ (+) Full DATA_EEPROM erase and program management
+ (+) Boot activation
+ (+) PCROP protection configuration and control for all pages
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+/** @addtogroup STM32L0XX_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FLASHEx HAL FLASH Driver
+ * @brief FLASH HAL Extension module driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)0x50000
+#define WRP01_MASK ((uint32_t)0x0000FFFF)
+#define PAGESIZE ((uint32_t)0x00000080)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/*Variables used for Erase sectors under interruption*/
+extern FLASH_ProcessTypeDef pFlash;
+
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t OB_WRP, FunctionalState NewState);
+static HAL_StatusTypeDef FLASH_OB_PCROPSelectionConfig(uint16_t OB_PcROP);
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint16_t OB_BOOT);
+static HAL_StatusTypeDef DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
+static HAL_StatusTypeDef DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
+static HAL_StatusTypeDef DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
+static HAL_StatusTypeDef DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
+static HAL_StatusTypeDef DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
+static HAL_StatusTypeDef DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);
+static uint8_t FLASH_OB_GetUser(void);
+static uint32_t FLASH_OB_GetWRP(void);
+static FlagStatus FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetBOR(void);
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup Extended_FLASHEx_Private_Functions Extended FLASH Private functions
+ * @{
+ */
+
+/** @defgroup HAL_FLASHEx_Group1 Peripheral extended features functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Features functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the FLASH data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program option bytes
+ * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_OBEX(pAdvOBInit->OptionType));
+
+ /*Program PCROP option byte*/
+ if ((pAdvOBInit->OptionType&OBEX_PCROP) == OBEX_PCROP)
+ {
+ /* Check the parameters */
+ assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
+ if (pAdvOBInit->PCROPState == PCROPSTATE_ENABLE)
+ {
+ /*Enable of Write protection on the selected Sector*/
+ status = FLASH_OB_PCROPConfig(pAdvOBInit->Pages, ENABLE);
+ status = FLASH_OB_PCROPSelectionConfig(OB_PCROP_SELECTED);
+ }
+ else
+ {
+ /*Disable of Write protection on the selected Sector*/
+ status = FLASH_OB_PCROPConfig(pAdvOBInit->Pages, DISABLE);
+ status = FLASH_OB_PCROPSelectionConfig(OB_PCROP_DESELECTED);
+ }
+ }
+ /*Program BOOT config option byte*/
+ if ((pAdvOBInit->OptionType&OBEX_BOOTCONFIG) == OBEX_BOOTCONFIG)
+ {
+ status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Get the OBEX byte configuration
+ * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
+{
+ pAdvOBInit->OptionType = OBEX_PCROP| OBEX_BOOTCONFIG;
+ /*Get PCROP state */
+ pAdvOBInit->PCROPState = (FLASH->OBR & 0x00000100) >> 8;
+ /*Get PCROP protected Pages */
+ pAdvOBInit->Pages = FLASH->WRPR;
+ /*Get Boot config OB*/
+ pAdvOBInit->BootConfig = (FLASH->OBR & 0x80000000) >> 24;
+}
+
+/** @defgroup HAL_FLASHEx_Group2 DATA EEPROM Programming functions
+ * @brief DATA EEPROM Programming functions
+ *
+@verbatim
+ ===============================================================================
+ ##### DATA EEPROM Programming functions #####
+ ===============================================================================
+
+ [..] The DATA_EEPROM Programming_Functions, includes the following functions:
+ (+) HAL_DATA_EEPROMEx_Unlock(void);
+ (+) HAL_DATA_EEPROMEx_Lock(void);
+ (+) HAL_DATA_EEPROMEx_Erase(uint32_t Address)
+ (+) HAL_DATA_EEPROMEx_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
+
+ [..] Any operation of erase or program should follow these steps:
+ (#) Call the HAL_DATA_EEPROMEx_Unlock() function to enable the data EEPROM access
+ and Flash program erase control register access.
+ (#) Call the desired function to erase or program data.
+ (#) Call the HAL_DATA_EEPROMEx_Lock() to disable the data EEPROM access
+ and Flash program erase control register access(recommended
+ to protect the DATA_EEPROM against possible unwanted operation).
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Unlocks the data memory and FLASH_PECR register access.
+ * @param None
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_DATA_EEPROMEx_Unlock(void)
+{
+ if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)
+ {
+ /* Unlocking the Data memory and FLASH_PECR register access*/
+ FLASH->PEKEYR = FLASH_PEKEY1;
+ FLASH->PEKEYR = FLASH_PEKEY2;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Locks the Data memory and FLASH_PECR register access.
+ * @param None
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_DATA_EEPROMEx_Lock(void)
+{
+ /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */
+ FLASH->PECR |= FLASH_PECR_PELOCK;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Erase a word in data memory.
+ * @param Address: specifies the address to be erased.
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function
+ * must be called before.
+ * Call the DATA_EEPROM_Lock() to the data EEPROM access
+ * and Flash program erase control register access(recommended to protect
+ * the DATA_EEPROM against possible unwanted operation).
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+HAL_StatusTypeDef HAL_DATA_EEPROMEx_Erase(uint32_t Address)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ /* Write "00000000h" to valid address in the data memory" */
+ *(__IO uint32_t *) Address = 0x00000000;
+ }
+
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Program word at a specified address
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+
+HAL_StatusTypeDef HAL_DATA_EEPROMEx_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_TYPEPROGRAM(TypeProgram));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ if(TypeProgram == TYPEPROGRAM_FASTBYTE)
+ {
+ /*Program word (8-bit) at a specified address.*/
+ DATA_EEPROM_FastProgramByte(Address, (uint8_t) Data);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+
+ if(TypeProgram == TYPEPROGRAM_FASTHALFWORD)
+ {
+ /*Program word (16-bit) at a specified address.*/
+ DATA_EEPROM_FastProgramHalfWord(Address, (uint16_t) Data);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+ if(TypeProgram == TYPEPROGRAM_FASTWORD)
+ {
+ /*Program word (32-bit) at a specified address.*/
+ DATA_EEPROM_FastProgramWord(Address, (uint32_t) Data);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+ if(TypeProgram == TYPEPROGRAM_WORD)
+ {
+ /*Program word (32-bit) at a specified address.*/
+ DATA_EEPROM_ProgramWord(Address, (uint32_t) Data);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+
+ if(TypeProgram == TYPEPROGRAM_HALFWORD)
+ {
+ /*Program word (16-bit) at a specified address.*/
+ DATA_EEPROM_ProgramHalfWord(Address, (uint16_t) Data);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+
+ if(TypeProgram == TYPEPROGRAM_BYTE)
+ {
+ /*Program word (8-bit) at a specified address.*/
+ DATA_EEPROM_ProgramByte(Address, (uint8_t) Data);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Erase the specified FLASH memory Pages
+ * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @param[out] PageError: pointer to variable that
+ * contains the configuration information on faulty sector in case of error
+ * (0xFFFFFFFF means that all the sectors have been correctly erased)
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t index = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if (status == HAL_OK)
+ {
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFF;
+
+ /* Check the parameters */
+ assert_param(IS_NBPAGES(pEraseInit->NbPages + pEraseInit->Page));
+
+ /* Erase by sector by sector to be done*/
+ for(index = pEraseInit->Page; index < ((pEraseInit->NbPages*PAGESIZE)+ pEraseInit->Page); index+=PAGESIZE)
+ {
+ FLASH_Erase_Page(index);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ /* If the erase operation is completed, disable the ERASE Bit */
+ FLASH->PECR &= (~FLASH_PECR_PROG);
+ FLASH->PECR &= (~FLASH_PECR_ERASE);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty sector*/
+ *PageError = index;
+ break;
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Perform a page erase of the specified FLASH memory pages with interrupt enabled
+ * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Enable End of FLASH Operation interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+
+ /* Enable Error source interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+
+ /* Clear pending flags (if any) */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR |\
+ FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR| FLASH_FLAG_OPTVERR |\
+ FLASH_FLAG_RDERR | FLASH_FLAG_NOTZEROERR);
+
+ if (pEraseInit->TypeErase == TYPEERASE_PAGEERASE)
+ {
+ /* Erase by sector to be done*/
+
+ /* Check the parameters */
+ assert_param(IS_NBPAGES(pEraseInit->NbPages + pEraseInit->Page));
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
+ pFlash.NbPagesToErase = pEraseInit->NbPages;
+ pFlash.Page = pEraseInit->Page;
+
+ /*Erase 1st page and wait for IT*/
+ FLASH_Erase_Page(pEraseInit->Page);
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Program option bytes
+ * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+ /*Write protection configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+ {
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));
+ if (pOBInit->WRPState == WRPSTATE_ENABLE)
+ {
+ /*Enable of Write protection on the selected Sector*/
+ status = FLASH_OB_WRPConfig(pOBInit->WRPSector, ENABLE);
+ }
+ else
+ {
+ /*Disable of Write protection on the selected Sector*/
+ status = FLASH_OB_WRPConfig(pOBInit->WRPSector, DISABLE);
+ }
+ }
+
+ /* Read protection configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+ {
+ status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
+ }
+
+ /* USER configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+ {
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW,
+ pOBInit->USERConfig&OB_STOP_NoRST,
+ pOBInit->USERConfig&OB_STDBY_NoRST);
+ }
+
+ /* BOR Level configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+ {
+ status = FLASH_OB_BORConfig(pOBInit->BORLevel);
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Get the Option byte configuration
+ * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
+
+ /*Get WRP*/
+ pOBInit->WRPSector = FLASH_OB_GetWRP();
+
+ /*Get RDP Level*/
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+ /*Get USER*/
+ pOBInit->USERConfig = FLASH_OB_GetUser();
+
+ /*Get BOR Level*/
+ pOBInit->BORLevel = FLASH_OB_GetBOR();
+}
+
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @param None
+ * @retval The FLASH User Option Bytes.
+ */
+static uint8_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return (uint8_t)(FLASH->OBR >> 20);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes value.
+ * @param None
+ * @retval The FLASH Write Protection Option Bytes value.
+ */
+static uint32_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+ * @brief Checks whether the FLASH Read out Protection Status is set or not.
+ * @param None
+ * @retval FLASH ReadOut Protection Status(SET or RESET).
+ */
+static FlagStatus FLASH_OB_GetRDP(void)
+{
+ FlagStatus readstatus = RESET;
+
+ if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0)
+ {
+ readstatus = SET;
+ }
+ else
+ {
+ readstatus = RESET;
+ }
+ return readstatus;
+}
+
+/**
+ * @brief Returns the FLASH BOR level.
+ * @param None
+ * @retval The FLASH User Option Bytes.
+ */
+static uint8_t FLASH_OB_GetBOR(void)
+{
+ /* Return the BOR level */
+ return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16);
+}
+
+/**
+ * @brief Write protects the desired pages of the first 64KB of the Flash.
+ * @param OB_WRP: specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg value between OB_WRP_Pages0to31 and OB_WRP_Pages480to511
+ * @arg OB_WRP_AllPages
+ * @param NewState: new state of the specified FLASH Pages Wtite protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval HAL_StatusTypeDef
+ */
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t WRP01_Data = 0;
+ uint32_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(OB_WRP));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ if (NewState != DISABLE)
+ {
+ WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01));
+ tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data);
+ OB->WRP01 = tmp1;
+ }
+ else
+ {
+ WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01));
+ tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data);
+ OB->WRP01 = tmp1;
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE));
+ }
+
+ /* Return the write protection operation Status */
+ return status;
+}
+/**
+ * @brief Enables or disables the read out protection.
+ * @note To correctly run this function, the FLASH_OB_Unlock() function
+ * must be called before.
+ * @param FLASH_ReadProtection_Level: specifies the read protection level.
+ * This parameter can be:
+ * @arg OB_RDP_Level_0: No protection
+ * @arg OB_RDP_Level_1: Read protection of the memory
+ * @arg OB_RDP_Level_2: Chip protection
+ *
+ * !!!Warning!!! When enabling OB_RDP_Level_2 it's no more possible to go back to level 1 or 0
+ *
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint8_t tmp1 = 0;
+ uint32_t tmp2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP(OB_RDP));
+ status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE));
+
+ /* calculate the option byte to write */
+ tmp1 = (uint8_t)(~(OB_RDP ));
+ tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)OB_RDP));
+
+ if(status == HAL_OK)
+ {
+ /* program read protection level */
+ OB->RDP = tmp2;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ /* Return the Read protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @param OB_IWDG: Selects the WDG mode.
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW: Software WDG selected
+ * @arg OB_IWDG_HW: Hardware WDG selected
+ * @param OB_STOP: Reset event when entering STOP mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP
+ * @arg OB_STOP_RST: Reset generated when entering in STOP
+ * @param OB_STDBY: Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmp = 0, tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+ /* Get the User Option byte register */
+ tmp1 = (FLASH->OBR & 0x800F0000) >> 16;
+
+ /* Calculate the user option byte to write */
+ tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16);
+ tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ /* Write the User Option Byte */
+ OB->USER = tmp;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH brownout reset threshold level Option Byte.
+ * @param OB_BOR: Selects the brownout reset threshold level.
+ * This parameter can be one of the following values:
+ * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD
+ * power supply reaches the PDR(Power Down Reset) threshold (1.5V)
+ * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply
+ * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply
+ * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply
+ * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply
+ * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmp = 0, tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OB_BOR_LEVEL(OB_BOR));
+
+ /* Get the User Option byte register */
+ tmp1 = (FLASH->OBR & 0x000F0000) >> 16;
+
+ /* Calculate the option byte to write */
+ tmp = (uint32_t)~(OB_BOR | tmp1)<<16;
+ tmp |= (OB_BOR | tmp1);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ /* Write the BOR Option Byte */
+ OB->USER = tmp;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @}
+ */
+/**
+ * @brief Enables or disables the read/write protection (PCROP) of the desired
+ * sectors, for the first 64KB of the Flash.
+ * @param OB_WRP: specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg value between OB_WRP_Pages0to31 and OB_WRP_Pages480to511
+ * @arg OB_WRP_AllPages
+ * @param NewState: new state of the specified FLASH Pages Write protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t OB_WRP, FunctionalState NewState)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t WRP01_Data = 0;
+ uint32_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(OB_WRP));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ if (NewState != DISABLE)
+ {
+ WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01));
+
+ tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data);
+ OB->WRP01 = tmp1;
+ }
+
+ else
+ {
+ WRP01_Data = (uint16_t)((OB_WRP & WRP01_MASK) | OB->WRP01);
+
+ tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data);
+ OB->WRP01 = tmp1;
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Select the Protection Mode (SPRMOD).
+ * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible
+ * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+ * @param OB_PcROP: Select the Protection Mode of WPR bits.
+ * This parameter can be:
+ * @arg OB_PCROP_SELECTED: nWRP control the read&write protection (PcROP) of respective user sectors.
+ * @arg OB_PCROP_DESELECTED: nWRP control the write protection of respective user sectors.
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef FLASH_OB_PCROPSelectionConfig(uint16_t OB_PcROP)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint16_t tmp1 = 0;
+ uint32_t tmp2 = 0;
+ uint8_t optiontmp = 0;
+ uint16_t optiontmp2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ /* Mask RDP Byte */
+ optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE));
+
+ /* Update Option Byte */
+ optiontmp2 = (uint16_t)(OB_PcROP | optiontmp);
+
+
+ /* calculate the option byte to write */
+ tmp1 = (uint16_t)(~(optiontmp2 ));
+ tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2));
+
+ if(status == HAL_OK)
+ {
+ /* program PCRop */
+ OB->RDP = tmp2;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE));
+
+ /* Return the Read protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Sets or resets the BOOT1 option bit.
+ * @param OB_BOOT1: Set or Reset the BOOT1 option bit.
+ * This parameter can be one of the following values:
+ * @arg OB_BOOT1_RESET: BOOT1 option bit reset
+ * @arg OB_BOOT1_SET: BOOT1 option bit set
+ * @retval None
+ */
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint16_t OB_BOOT)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmp = 0, tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OB_BOOT1(OB_BOOT));
+
+ /* Get the User Option byte register */
+ tmp1 = (FLASH->OBR & 0x007F0000) >> 16;
+
+ /* Calculate the option byte to write */
+ tmp = (uint32_t)~(OB_BOOT | tmp1)<<16;
+ tmp |= (OB_BOOT | tmp1);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ /* Write the BOOT Option Byte */
+ OB->USER = tmp;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Write a Byte at a specified address in data memory.
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function
+ * must be called before.
+ * Call the DATA_EEPROM_Lock() to the data EEPROM access
+ * and Flash program erase control register access(recommended to protect
+ * the DATA_EEPROM against possible unwanted operation).
+ * @param Address: specifies the address to be written.
+ * @param Data: specifies the data to be written.
+ * @note This function assumes that data word is already erased.
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ /* Clear the FTDW bit */
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
+
+ /* If the previous operation is completed, proceed to write the new Data */
+ *(__IO uint8_t *)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+ /* Return the Write Status */
+ return status;
+}
+
+/**
+ * @brief Writes a half word at a specified address in data memory.
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function
+ * must be called before.
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * and Flash program erase control register access(recommended to protect
+ * the DATA_EEPROM against possible unwanted operation).
+ * @param Address: specifies the address to be written.
+ * @param Data: specifies the data to be written.
+ * @note This function assumes that the is data word is already erased.
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ /* Clear the FTDW bit */
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
+
+ /* If the previous operation is completed, proceed to write the new data */
+ *(__IO uint16_t *)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+ /* Return the Write Status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address in data memory.
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function
+ * must be called before.
+ * Call the DATA_EEPROM_Lock() to the data EEPROM access
+ * and Flash program erase control register access(recommended to protect
+ * the DATA_EEPROM against possible unwanted operation).
+ * @param Address: specifies the address to be written.
+ * @param Data: specifies the data to be written.
+ * @note This function assumes that the is data word is already erased.
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ /* Clear the FTDW bit */
+ FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
+
+ /* If the previous operation is completed, proceed to program the new data */
+ *(__IO uint32_t *)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+ /* Return the Write Status */
+ return status;
+}
+
+/**
+ * @brief Write a Byte at a specified address in data memory without erase.
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function
+ * must be called before.
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * and Flash program erase control register access(recommended to protect
+ * the DATA_EEPROM against possible unwanted operation).
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before
+ * this function to configure the Fixed Time Programming.
+ * @param Address: specifies the address to be written.
+ * @param Data: specifies the data to be written.
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ /* Set the FTDW bit */
+ FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW;
+
+ *(__IO uint8_t *)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+ /* Return the Write Status */
+ return status;
+}
+
+/**
+ * @brief Writes a half word at a specified address in data memory without erase.
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function
+ * must be called before.
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * and Flash program erase control register access(recommended to protect
+ * the DATA_EEPROM against possible unwanted operation).
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before
+ * this function to configure the Fixed Time Programming
+ * @param Address: specifies the address to be written.
+ * @param Data: specifies the data to be written.
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ /* Set the FTDW bit */
+ FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW;
+
+ *(__IO uint16_t *)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+ /* Return the Write Status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address in data memory without erase.
+ * @note To correctly run this function, the DATA_EEPROM_Unlock() function
+ * must be called before.
+ * Call the DATA_EEPROM_Lock() to he data EEPROM access
+ * and Flash program erase control register access(recommended to protect
+ * the DATA_EEPROM against possible unwanted operation).
+ * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before
+ * this function to configure the Fixed Time Programming.
+ * @param Address: specifies the address to be written.
+ * @param Data: specifies the data to be written.
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+static HAL_StatusTypeDef DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+
+ if(status == HAL_OK)
+ {
+ /* Set the FTDW bit */
+ FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW;
+
+ *(__IO uint32_t *)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ }
+ /* Return the Write Status */
+ return status;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash_ex.h
new file mode 100644
index 0000000000..072c385a92
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L053R8/stm32l0xx_hal_flash_ex.h
@@ -0,0 +1,289 @@
+/**
+ ******************************************************************************
+ * @file stm32l0xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 22-April-2014
+ * @brief Header file of FLASH HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_FLASH_EX_H
+#define __STM32L0xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief FLASH Advanced Option Bytes Program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
+ This parameter can be a value of @ref FLASHEx_OptionEx_Type */
+
+ uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_PCROP_State */
+
+ uint16_t Pages; /*!< Sectors: specifies the sector(s) set for PCROP
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+ uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
+ This parameter can be a value of @ref FLASHEx_Dual_Boot */
+} FLASH_AdvOBProgramInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
+ * @{
+ */
+#define PCROPSTATE_DISABLE ((uint32_t)0x00) /*!ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
+
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval none
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval none
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
+
+/**
+ * @brief Enable the FLASH Buffer cache.
+ * @retval none
+ */
+#define __HAL_FLASH_BUFFER_CACHE_ENABLE() (FLASH->ACR &= (~FLASH_ACR_DISAB_BUF))
+
+/**
+ * @brief Disable the FLASH Buffer cache.
+ * @retval none
+ */
+#define __HAL_FLASH_BUFFER_CACHE_DISABLE() (FLASH->ACR |= FLASH_ACR_DISAB_BUF)
+
+/**
+ * @brief Enable the FLASH preread buffer
+ * @retval none
+ */
+#define __HAL_FLASH_PREREAD_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRE_READ)
+
+/**
+ * @brief Disable the FLASH preread buffer
+ * @retval none
+ */
+#define __HAL_FLASH_PREREAD_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRE_READ))
+
+/**
+ * @brief Enable the FLASH power down during Sleep mode
+ * @retval none
+ */
+#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+ * @brief Disable the FLASH power down during Sleep mode
+ * @retval none
+ */
+#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+ * @brief Macro to enable or disable the Flash Run power down mode.
+ * @note Writing this bit to 0 this bit, automatically the keys are
+ * loss and a new unlock sequence is necessary to re-write it to 1.
+ */
+
+#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
+ FLASH->PDKEYR = FLASH_PDKEY2; \
+ SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
+ } while (0)
+
+#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
+ FLASH->PDKEYR = FLASH_PDKEY2; \
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
+ } while (0)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* I/O operation functions *****************************************************/
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_DATA_EEPROMEx_Unlock(void);
+HAL_StatusTypeDef HAL_DATA_EEPROMEx_Lock(void);
+
+HAL_StatusTypeDef HAL_DATA_EEPROMEx_Erase(uint32_t Address);
+HAL_StatusTypeDef HAL_DATA_EEPROMEx_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
+
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/