From 2c533d4693b2f6cd5c3265ee5837013000e225c2 Mon Sep 17 00:00:00 2001 From: Adrien Chardon Date: Mon, 3 Jul 2017 11:54:39 +0200 Subject: [PATCH 1/9] Initial support for PSoC 6. --- .../TARGET_PSoC6_CY8C/PeripheralNames.h | 90 + .../TARGET_PSoC6_CY8C/PeripheralPins.h | 84 + .../TARGET_PSoC6_CY8C/PinNamesTypes.h | 67 + .../TARGET_PSoC6_CY8C/PortNames.h | 61 + .../TARGET_PSoC6_CY8C_CM0p/PeripheralPins.c | 131 + .../TARGET_PSoC6_CY8C_CM0p/PinNames.h | 251 ++ .../TARGET_PSoC6_CY8C_CM0p/device.h | 39 + .../TOOLCHAIN_GCC_ARM/cy8c6x7_cm0plus.ld | 328 ++ .../device/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S | 101 + .../startup_psoc6ble_cm0plus.S | 423 +++ .../TARGET_PSoC6_CY8C_CM0p/device/cmsis.h | 38 + .../device/cy8c637bzi_bld74.h | 1030 ++++++ .../device/cy_device_headers.h | 85 + .../device/gpio_psoc6ble_116_bga_ble.h | 1611 ++++++++++ .../device/psoc6ble_config.h | 2289 ++++++++++++++ .../device/system_psoc6ble_cm0plus.c | 667 ++++ .../device/system_psoc6ble_cm0plus.h | 185 ++ .../device/cy_crypto_config.h | 92 + .../TARGET_PSoC6_CY8C/device/cyapicallbacks.h | 28 + .../device/cydisabledsheets.h | 5 + .../TARGET_PSoC6_CY8C/device/cyfitter.h | 6 + .../TARGET_PSoC6_CY8C/device/cyfitter_cfg.c | 271 ++ .../TARGET_PSoC6_CY8C/device/cyfitter_cfg.h | 29 + .../TARGET_PSoC6_CY8C/device/cyfitter_gpio.h | 6 + .../TARGET_PSoC6_CY8C/device/cymetadata.c | 48 + .../device/driver_periph/crypto/cy_crypto.c | 1809 +++++++++++ .../device/driver_periph/crypto/cy_crypto.h | 450 +++ .../driver_periph/crypto/cy_crypto_common.h | 504 +++ .../driver_periph/crypto/cy_crypto_core_aes.c | 405 +++ .../driver_periph/crypto/cy_crypto_core_aes.h | 77 + .../crypto/cy_crypto_core_cmac.c | 272 ++ .../crypto/cy_crypto_core_cmac.h | 72 + .../driver_periph/crypto/cy_crypto_core_crc.c | 117 + .../driver_periph/crypto/cy_crypto_core_crc.h | 41 + .../driver_periph/crypto/cy_crypto_core_des.c | 208 ++ .../driver_periph/crypto/cy_crypto_core_des.h | 48 + .../crypto/cy_crypto_core_hmac.c | 244 ++ .../crypto/cy_crypto_core_hmac.h | 37 + .../crypto/cy_crypto_core_instructions.h | 180 ++ .../crypto/cy_crypto_core_prng.c | 99 + .../crypto/cy_crypto_core_prng.h | 39 + .../driver_periph/crypto/cy_crypto_core_rsa.c | 993 ++++++ .../driver_periph/crypto/cy_crypto_core_rsa.h | 62 + .../driver_periph/crypto/cy_crypto_core_sha.c | 442 +++ .../driver_periph/crypto/cy_crypto_core_sha.h | 115 + .../driver_periph/crypto/cy_crypto_core_str.c | 194 ++ .../driver_periph/crypto/cy_crypto_core_str.h | 43 + .../crypto/cy_crypto_core_trng.c | 93 + .../crypto/cy_crypto_core_trng.h | 37 + .../crypto/cy_crypto_core_trng_config.h | 239 ++ .../crypto/cy_crypto_core_util.c | 485 +++ .../crypto/cy_crypto_core_util.h | 132 + .../driver_periph/crypto/cy_crypto_core_vu.c | 66 + .../driver_periph/crypto/cy_crypto_core_vu.h | 136 + .../crypto/cy_crypto_core_vu_hw.h | 380 +++ .../driver_periph/crypto/cy_crypto_server.c | 409 +++ .../driver_periph/crypto/cy_crypto_server.h | 51 + .../device/driver_periph/flash/cy_flash.c | 470 +++ .../device/driver_periph/flash/cy_flash.h | 283 ++ .../device/driver_periph/gpio/cy_gpio.c | 137 + .../device/driver_periph/gpio/cy_gpio.h | 1719 ++++++++++ .../device/driver_periph/ipc/cy_ipc_drv.c | 464 +++ .../device/driver_periph/ipc/cy_ipc_drv.h | 288 ++ .../device/driver_periph/ipc/cy_ipc_lock.c | 268 ++ .../device/driver_periph/ipc/cy_ipc_lock.h | 84 + .../device/driver_periph/ipc/cy_ipc_pipe.c | 345 ++ .../device/driver_periph/ipc/cy_ipc_pipe.h | 191 ++ .../device/driver_periph/profile/cy_profile.c | 374 +++ .../device/driver_periph/profile/cy_profile.h | 540 ++++ .../device/driver_periph/prot/cy_prot.c | 1587 ++++++++++ .../device/driver_periph/prot/cy_prot.h | 558 ++++ .../device/driver_periph/scb/cy_scb_common.c | 412 +++ .../device/driver_periph/scb/cy_scb_common.h | 1617 ++++++++++ .../device/driver_periph/scb/cy_scb_ezi2c.c | 1058 +++++++ .../device/driver_periph/scb/cy_scb_ezi2c.h | 424 +++ .../device/driver_periph/scb/cy_scb_i2c.c | 2791 +++++++++++++++++ .../device/driver_periph/scb/cy_scb_i2c.h | 1112 +++++++ .../device/driver_periph/scb/cy_scb_spi.c | 766 +++++ .../device/driver_periph/scb/cy_scb_spi.h | 1233 ++++++++ .../device/driver_periph/scb/cy_scb_uart.c | 1181 +++++++ .../device/driver_periph/scb/cy_scb_uart.h | 1282 ++++++++ .../device/driver_periph/sysclk/cy_sysclk.c | 1285 ++++++++ .../device/driver_periph/sysclk/cy_sysclk.h | 2165 +++++++++++++ .../device/driver_periph/sysint/cy_sysint.c | 369 +++ .../device/driver_periph/sysint/cy_sysint.h | 343 ++ .../device/driver_periph/syslib/cy_syslib.c | 654 ++++ .../device/driver_periph/syslib/cy_syslib.h | 800 +++++ .../device/driver_periph/syspm/cy_syspm.c | 1879 +++++++++++ .../device/driver_periph/syspm/cy_syspm.h | 820 +++++ .../device/driver_periph/systick/cy_systick.c | 335 ++ .../device/driver_periph/systick/cy_systick.h | 170 + .../device/driver_periph/tcpwm/cy_tcpwm.h | 591 ++++ .../driver_periph/tcpwm/cy_tcpwm_counter.c | 137 + .../driver_periph/tcpwm/cy_tcpwm_counter.h | 484 +++ .../device/driver_periph/tcpwm/cy_tcpwm_pwm.c | 153 + .../device/driver_periph/tcpwm/cy_tcpwm_pwm.h | 576 ++++ .../driver_periph/tcpwm/cy_tcpwm_quaddec.c | 116 + .../driver_periph/tcpwm/cy_tcpwm_quaddec.h | 281 ++ .../device/driver_periph/trigmux/cy_trigmux.c | 112 + .../device/driver_periph/trigmux/cy_trigmux.h | 199 ++ .../device/driver_periph/wdt/cy_wdt.c | 303 ++ .../device/driver_periph/wdt/cy_wdt.h | 261 ++ .../TARGET_PSoC6_CY8C/device/ip/cyip_backup.h | 221 ++ .../TARGET_PSoC6_CY8C/device/ip/cyip_ble.h | 2219 +++++++++++++ .../TARGET_PSoC6_CY8C/device/ip/cyip_cpuss.h | 346 ++ .../TARGET_PSoC6_CY8C/device/ip/cyip_crypto.h | 375 +++ .../TARGET_PSoC6_CY8C/device/ip/cyip_csd.h | 473 +++ .../TARGET_PSoC6_CY8C/device/ip/cyip_ctbm.h | 287 ++ .../TARGET_PSoC6_CY8C/device/ip/cyip_ctdac.h | 110 + .../TARGET_PSoC6_CY8C/device/ip/cyip_dw.h | 230 ++ .../TARGET_PSoC6_CY8C/device/ip/cyip_efuse.h | 318 ++ .../TARGET_PSoC6_CY8C/device/ip/cyip_fault.h | 113 + .../TARGET_PSoC6_CY8C/device/ip/cyip_flashc.h | 518 +++ .../TARGET_PSoC6_CY8C/device/ip/cyip_gpio.h | 468 +++ .../device/ip/cyip_headers.h | 31 + .../TARGET_PSoC6_CY8C/device/ip/cyip_hsiom.h | 88 + .../TARGET_PSoC6_CY8C/device/ip/cyip_i2s.h | 280 ++ .../TARGET_PSoC6_CY8C/device/ip/cyip_ipc.h | 123 + .../TARGET_PSoC6_CY8C/device/ip/cyip_lcd.h | 92 + .../TARGET_PSoC6_CY8C/device/ip/cyip_lpcomp.h | 171 + .../TARGET_PSoC6_CY8C/device/ip/cyip_pass.h | 130 + .../TARGET_PSoC6_CY8C/device/ip/cyip_pdm.h | 169 + .../TARGET_PSoC6_CY8C/device/ip/cyip_peri.h | 482 +++ .../device/ip/cyip_profile.h | 105 + .../TARGET_PSoC6_CY8C/device/ip/cyip_prot.h | 374 +++ .../TARGET_PSoC6_CY8C/device/ip/cyip_sar.h | 627 ++++ .../TARGET_PSoC6_CY8C/device/ip/cyip_scb.h | 755 +++++ .../TARGET_PSoC6_CY8C/device/ip/cyip_sflash.h | 186 ++ .../device/ip/cyip_smartio.h | 109 + .../TARGET_PSoC6_CY8C/device/ip/cyip_smif.h | 404 +++ .../TARGET_PSoC6_CY8C/device/ip/cyip_srss.h | 655 ++++ .../TARGET_PSoC6_CY8C/device/ip/cyip_tcpwm.h | 191 ++ .../TARGET_PSoC6_CY8C/device/ip/cyip_udb.h | 2052 ++++++++++++ .../device/middleware/ble/cy_ble_clk.c | 491 +++ .../device/middleware/ble/cy_ble_clk.h | 220 ++ .../TARGET_PSoC6_CY8C/device/project.h | 99 + .../TARGET_PSoC6_CY8C/gpio_api.c | 153 + .../TARGET_PSoC6_CY8C/objects.h | 120 + .../TARGET_PSoC6_CY8C/serial_api.c | 219 ++ .../TARGET_PSoC6_CY8C/us_ticker.c | 129 + targets/TARGET_Cypress/mbed_rtx.h | 32 + 141 files changed, 61826 insertions(+) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralNames.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralPins.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PinNamesTypes.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PortNames.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PeripheralPins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PinNames.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/cy8c6x7_cm0plus.ld create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/startup_psoc6ble_cm0plus.S create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cmsis.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cy8c637bzi_bld74.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cy_device_headers.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/gpio_psoc6ble_116_bga_ble.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/psoc6ble_config.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/system_psoc6ble_cm0plus.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/system_psoc6ble_cm0plus.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cy_crypto_config.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyapicallbacks.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cydisabledsheets.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_cfg.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_cfg.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_gpio.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cymetadata.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_common.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_aes.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_aes.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_cmac.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_cmac.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_crc.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_crc.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_des.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_des.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_hmac.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_hmac.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_instructions.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_prng.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_prng.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_rsa.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_rsa.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_sha.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_sha.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_str.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_str.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng_config.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_util.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_util.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu_hw.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_server.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_server.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_drv.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_drv.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_lock.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_lock.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_pipe.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_pipe.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/profile/cy_profile.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/profile/cy_profile.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/prot/cy_prot.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/prot/cy_prot.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_common.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_common.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_ezi2c.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_ezi2c.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_i2c.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_i2c.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_spi.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_spi.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_uart.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_uart.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysclk/cy_sysclk.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysclk/cy_sysclk.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysint/cy_sysint.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysint/cy_sysint.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syslib/cy_syslib.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syslib/cy_syslib.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syspm/cy_syspm.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syspm/cy_syspm.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/systick/cy_systick.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/systick/cy_systick.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_counter.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_counter.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_pwm.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_pwm.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_quaddec.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_quaddec.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/trigmux/cy_trigmux.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/trigmux/cy_trigmux.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/wdt/cy_wdt.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/wdt/cy_wdt.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_backup.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ble.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_cpuss.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_crypto.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_csd.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ctbm.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ctdac.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_dw.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_efuse.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_fault.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_flashc.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_gpio.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_headers.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_hsiom.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_i2s.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ipc.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_lcd.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_lpcomp.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_pass.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_pdm.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_peri.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_profile.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_prot.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_sar.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_scb.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_sflash.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_smartio.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_smif.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_srss.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_tcpwm.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_udb.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/middleware/ble/cy_ble_clk.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/middleware/ble/cy_ble_clk.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/project.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/gpio_api.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/objects.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/serial_api.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6_CY8C/us_ticker.c create mode 100644 targets/TARGET_Cypress/mbed_rtx.h diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralNames.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralNames.h new file mode 100644 index 0000000000..7ab3dc1d8c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralNames.h @@ -0,0 +1,90 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) XXX + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// typedef enum { +// ADC_1 = (int)ADC1_BASE, +// ADC_2 = (int)ADC2_BASE, +// ADC_3 = (int)ADC3_BASE, +// } ADCName; + +// typedef enum { +// DAC_1 = (int)DAC_BASE, +// } DACName; + +// typedef enum { +// UART_1 = (int)USART1_BASE, +// UART_2 = (int)USART2_BASE, +// UART_3 = (int)USART3_BASE, +// } UARTName; + +#define STDIO_UART_TX CY_UART_TX +#define STDIO_UART_RX CY_UART_RX + +// typedef enum { +// SPI_1 = (int)SPI1_BASE, +// SPI_2 = (int)SPI2_BASE, +// SPI_3 = (int)SPI3_BASE, +// } SPIName; + +// typedef enum { +// I2C_0 = (int)I2C0_BASE, +// I2C_1 = (int)I2C1_BASE, +// } I2CName; + +// typedef enum { +// PWM_0 = (int)PWM_CH0_BASE, +// PWM_1 = (int)PWM_CH1_BASE, +// PWM_2 = (int)PWM_CH2_BASE, +// PWM_3 = (int)PWM_CH3_BASE, +// PWM_4 = (int)PWM_CH4_BASE, +// PWM_5 = (int)PWM_CH5_BASE, +// PWM_6 = (int)PWM_CH6_BASE, +// PWM_7 = (int)PWM_CH7_BASE, +// } PWMName; + +// typedef enum { +// CAN_1 = (int)CAN1_BASE, +// } CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralPins.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralPins.h new file mode 100644 index 0000000000..a24ce8e001 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralPins.h @@ -0,0 +1,84 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) XXX + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +// //*** ADC *** +// #ifdef DEVICE_ANALOGIN +// extern const PinMap PinMap_ADC[]; +// #endif + +// //*** DAC *** +// #ifdef DEVICE_ANALOGOUT +// extern const PinMap PinMap_DAC[]; +// #endif + +// //*** I2C *** +// #if DEVICE_I2C +// extern const PinMap PinMap_I2C_SDA[]; +// extern const PinMap PinMap_I2C_SCL[]; +// #endif + +// //*** PWM *** +// #if DEVICE_PWMOUT +// extern const PinMap PinMap_PWM[]; +// #endif + +// //*** SERIAL *** +// #ifdef DEVICE_SERIAL +// extern const PinMap PinMap_UART_TX[]; +// extern const PinMap PinMap_UART_RX[]; +// #endif + +// //*** I2C *** +// #ifdef DEVICE_I2C +// extern const PinMap PinMap_I2C_SDA[]; +// extern const PinMap PinMap_I2C_SCL[]; +// #endif + +// //*** SPI *** +// #ifdef DEVICE_SPI +// extern const PinMap PinMap_SPI_MOSI[]; +// extern const PinMap PinMap_SPI_MISO[]; +// extern const PinMap PinMap_SPI_SCLK[]; +// extern const PinMap PinMap_SPI_SSEL[]; +// #endif + +// //*** CAN *** +// #ifdef DEVICE_CAN +// extern const PinMap PinMap_CAN_RD[]; +// extern const PinMap PinMap_CAN_TD[]; +// #endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PinNamesTypes.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PinNamesTypes.h new file mode 100644 index 0000000000..bda1000b2f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PinNamesTypes.h @@ -0,0 +1,67 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMESTYPES_H +#define MBED_PINNAMESTYPES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// PinName[15-0] = Port[15-8] + Pin[7-0] +#define CYPRESS_PIN(pinname) ((pinname) & 0xFF) +#define CYPRESS_PORT(pinname) (((pinname) >> 8) & 0xFF) + +typedef enum { + PIN_INPUT = 0, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrainPullUp = 3, + OpenDrainNoPull = 4, + OpenDrainPullDown = 5, + PushPullNoPull = PullNone, + PushPullPullUp = PullUp, + PushPullPullDown = PullDown, + OpenDrain = OpenDrainPullUp, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PortNames.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PortNames.h new file mode 100644 index 0000000000..3f2e76232b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PortNames.h @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) XXX + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// Port[7-0] +typedef enum { + Port0 = 0x0, + Port1 = 0x1, + Port2 = 0x2, + Port3 = 0x3, + Port4 = 0x4, + Port5 = 0x5, + Port6 = 0x6, + Port7 = 0x7, + Port8 = 0x8, + Port9 = 0x9, + Port10 = 0xA, + Port11 = 0xB, + Port12 = 0xC, + Port13 = 0xD, + Port14 = 0xE, + Port15 = 0xF +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PeripheralPins.c new file mode 100644 index 0000000000..451cf138c9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PeripheralPins.c @@ -0,0 +1,131 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) XXX + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralNames.h" +#include "PeripheralPins.h" +#include "pinmap.h" + +// //*** ADC *** +// const PinMap PinMap_ADC[] = { +// {PC_15, ADC_0, STM_PIN_DATA_EXT(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0 +// {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1 +// {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2 +// {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3 +// {PC_11, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN4 +// {PC_10, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN5 +// {PC_9 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN6 +// {PC_8 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN7 +// {NC, NC, 0} +// }; + +// //*** DAC *** +// const PinMap PinMap_DAC[] = { +// {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1 +// {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2 (Warning: LED1 is also on this pin) +// {NC, NC, 0} +// }; + +// //*** SERIAL *** +// const PinMap PinMap_UART_TX[] = { +// {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {PC_10, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {NC, NC, 0} +// }; +// const PinMap PinMap_UART_RX[] = { +// {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {PC_11, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {NC, NC, 0} +// }; + +// //*** I2C *** +// const PinMap PinMap_I2C_SDA[] = { +// {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PA_6, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC, NC, 0} +// }; +// const PinMap PinMap_I2C_SCL[] = { +// {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_8, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_4, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PA_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC, NC, 0} +// }; + +// //*** SPI *** +// const PinMap PinMap_SPI_SCLK[] = { +// {PA_6 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PB_1 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC , NC , 0} +// }; +// const PinMap PinMap_SPI_MOSI[] = { +// {PA_8 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PB_3 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_15, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC , NC , 0} +// }; +// const PinMap PinMap_SPI_MISO[] = { +// {PA_7 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PB_2 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_14, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC , NC , 0} +// }; +// const PinMap PinMap_SPI_SSEL[] = { +// {PA_5 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PB_0 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC , NC , 0} +// }; + +// //*** PWM *** +// const PinMap PinMap_PWM[] = { +// {PA_0 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_1 , PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, +// {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, +// {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, +// {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, +// {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, +// {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_10, PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC , NC , WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)} +// }; diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PinNames.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PinNames.h new file mode 100644 index 0000000000..23ab89eee5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PinNames.h @@ -0,0 +1,251 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) XXX + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" +#include "PortNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define CY_UART_RX P5_0 +#define CY_UART_TX P5_1 + +// PinName[15-0] = Port[15-8] + Pin[7-0] +typedef enum { + P0_0 = (Port0 << 8) + 0x00, + P0_1 = (Port0 << 8) + 0x01, + P0_2 = (Port0 << 8) + 0x02, + P0_3 = (Port0 << 8) + 0x03, + P0_4 = (Port0 << 8) + 0x04, + P0_5 = (Port0 << 8) + 0x05, + P0_6 = (Port0 << 8) + 0x06, + P0_7 = (Port0 << 8) + 0x07, + + P1_0 = (Port1 << 8) + 0x00, + P1_1 = (Port1 << 8) + 0x01, + P1_2 = (Port1 << 8) + 0x02, + P1_3 = (Port1 << 8) + 0x03, + P1_4 = (Port1 << 8) + 0x04, + P1_5 = (Port1 << 8) + 0x05, + P1_6 = (Port1 << 8) + 0x06, + P1_7 = (Port1 << 8) + 0x07, + + P2_0 = (Port2 << 8) + 0x00, + P2_1 = (Port2 << 8) + 0x01, + P2_2 = (Port2 << 8) + 0x02, + P2_3 = (Port2 << 8) + 0x03, + P2_4 = (Port2 << 8) + 0x04, + P2_5 = (Port2 << 8) + 0x05, + P2_6 = (Port2 << 8) + 0x06, + P2_7 = (Port2 << 8) + 0x07, + + P3_0 = (Port3 << 8) + 0x00, + P3_1 = (Port3 << 8) + 0x01, + P3_2 = (Port3 << 8) + 0x02, + P3_3 = (Port3 << 8) + 0x03, + P3_4 = (Port3 << 8) + 0x04, + P3_5 = (Port3 << 8) + 0x05, + P3_6 = (Port3 << 8) + 0x06, + P3_7 = (Port3 << 8) + 0x07, + + P4_0 = (Port4 << 8) + 0x00, + P4_1 = (Port4 << 8) + 0x01, + P4_2 = (Port4 << 8) + 0x02, + P4_3 = (Port4 << 8) + 0x03, + P4_4 = (Port4 << 8) + 0x04, + P4_5 = (Port4 << 8) + 0x05, + P4_6 = (Port4 << 8) + 0x06, + P4_7 = (Port4 << 8) + 0x07, + + P5_0 = (Port5 << 8) + 0x00, + P5_1 = (Port5 << 8) + 0x01, + P5_2 = (Port5 << 8) + 0x02, + P5_3 = (Port5 << 8) + 0x03, + P5_4 = (Port5 << 8) + 0x04, + P5_5 = (Port5 << 8) + 0x05, + P5_6 = (Port5 << 8) + 0x06, + P5_7 = (Port5 << 8) + 0x07, + + P6_0 = (Port6 << 8) + 0x00, + P6_1 = (Port6 << 8) + 0x01, + P6_2 = (Port6 << 8) + 0x02, + P6_3 = (Port6 << 8) + 0x03, + P6_4 = (Port6 << 8) + 0x04, + P6_5 = (Port6 << 8) + 0x05, + P6_6 = (Port6 << 8) + 0x06, + P6_7 = (Port6 << 8) + 0x07, + + P7_0 = (Port7 << 8) + 0x00, + P7_1 = (Port7 << 8) + 0x01, + P7_2 = (Port7 << 8) + 0x02, + P7_3 = (Port7 << 8) + 0x03, + P7_4 = (Port7 << 8) + 0x04, + P7_5 = (Port7 << 8) + 0x05, + P7_6 = (Port7 << 8) + 0x06, + P7_7 = (Port7 << 8) + 0x07, + + P8_0 = (Port8 << 8) + 0x00, + P8_1 = (Port8 << 8) + 0x01, + P8_2 = (Port8 << 8) + 0x02, + P8_3 = (Port8 << 8) + 0x03, + P8_4 = (Port8 << 8) + 0x04, + P8_5 = (Port8 << 8) + 0x05, + P8_6 = (Port8 << 8) + 0x06, + P8_7 = (Port8 << 8) + 0x07, + + P9_0 = (Port9 << 8) + 0x00, + P9_1 = (Port9 << 8) + 0x01, + P9_2 = (Port9 << 8) + 0x02, + P9_3 = (Port9 << 8) + 0x03, + P9_4 = (Port9 << 8) + 0x04, + P9_5 = (Port9 << 8) + 0x05, + P9_6 = (Port9 << 8) + 0x06, + P9_7 = (Port9 << 8) + 0x07, + + P10_0 = (Port10 << 8) + 0x00, + P10_1 = (Port10 << 8) + 0x01, + P10_2 = (Port10 << 8) + 0x02, + P10_3 = (Port10 << 8) + 0x03, + P10_4 = (Port10 << 8) + 0x04, + P10_5 = (Port10 << 8) + 0x05, + P10_6 = (Port10 << 8) + 0x06, + P10_7 = (Port10 << 8) + 0x07, + + P11_0 = (Port11 << 8) + 0x00, + P11_1 = (Port11 << 8) + 0x01, + P11_2 = (Port11 << 8) + 0x02, + P11_3 = (Port11 << 8) + 0x03, + P11_4 = (Port11 << 8) + 0x04, + P11_5 = (Port11 << 8) + 0x05, + P11_6 = (Port11 << 8) + 0x06, + P11_7 = (Port11 << 8) + 0x07, + + P12_0 = (Port12 << 8) + 0x00, + P12_1 = (Port12 << 8) + 0x01, + P12_2 = (Port12 << 8) + 0x02, + P12_3 = (Port12 << 8) + 0x03, + P12_4 = (Port12 << 8) + 0x04, + P12_5 = (Port12 << 8) + 0x05, + P12_6 = (Port12 << 8) + 0x06, + P12_7 = (Port12 << 8) + 0x07, + + P13_0 = (Port13 << 8) + 0x00, + P13_1 = (Port13 << 8) + 0x01, + P13_2 = (Port13 << 8) + 0x02, + P13_3 = (Port13 << 8) + 0x03, + P13_4 = (Port13 << 8) + 0x04, + P13_5 = (Port13 << 8) + 0x05, + P13_6 = (Port13 << 8) + 0x06, + P13_7 = (Port13 << 8) + 0x07, + + P14_0 = (Port14 << 8) + 0x00, + P14_1 = (Port14 << 8) + 0x01, + P14_2 = (Port14 << 8) + 0x02, + P14_3 = (Port14 << 8) + 0x03, + P14_4 = (Port14 << 8) + 0x04, + P14_5 = (Port14 << 8) + 0x05, + P14_6 = (Port14 << 8) + 0x06, + P14_7 = (Port14 << 8) + 0x07, + + P15_0 = (Port15 << 8) + 0x00, + P15_1 = (Port15 << 8) + 0x01, + P15_2 = (Port15 << 8) + 0x02, + P15_3 = (Port15 << 8) + 0x03, + P15_4 = (Port15 << 8) + 0x04, + P15_5 = (Port15 << 8) + 0x05, + P15_6 = (Port15 << 8) + 0x06, + P15_7 = (Port15 << 8) + 0x07, + + // Arduino connector namings + A0 = P10_0, + A1 = P10_1, + A2 = P10_2, + A3 = P10_3, + A4 = P10_4, + A5 = P10_5, + + D0 = P5_0, + D1 = P5_1, + D2 = P5_2, + D3 = P5_3, + D4 = P5_4, + D5 = P5_5, + D6 = P5_6, + D7 = P0_2, + D8 = P13_0, + D9 = P13_1, + D10 = P12_3, + D11 = P12_0, + D12 = P12_1, + D13 = P12_2, + + // Generic signals namings + + LED_RED = P0_3, + LED_GREEN = P1_1, + LED_BLUE = P11_1, + + SWITCH2 = P0_4, + + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_RED, + + USER_BUTTON = SWITCH2, + BUTTON1 = USER_BUTTON, + + // Standardized interfaces names + SERIAL_TX = CY_UART_TX, + SERIAL_RX = CY_UART_RX, + USBTX = CY_UART_TX, + USBRX = CY_UART_RX, + // I2C_SCL = PB_8, + // I2C_SDA = PB_9, + // SPI_MOSI = PA_7, + // SPI_MISO = PA_6, + // SPI_SCK = PA_5, + // SPI_CS = PB_6, + // PWM_OUT = PB_3, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device.h new file mode 100644 index 0000000000..fa47e5377a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device.h @@ -0,0 +1,39 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) XXX + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" +#include "project.h" + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/cy8c6x7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/cy8c6x7_cm0plus.ld new file mode 100644 index 0000000000..c181e96892 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/cy8c6x7_cm0plus.ld @@ -0,0 +1,328 @@ +/***************************************************************************//** +* \file cy8c6x7_cm0plus.ld +* \version 1.0 +* +* \brief Linker file for the GNU C compiler. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) +EXTERN(vectors) +EXTERN(ram_vectors) +EXTERN(cychipprotect) +EXTERN(cymeta) + +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Working Flash */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* XIP */ +__cy_memory_2_start = 0x18000000; +__cy_memory_2_length = 0x08000000; +__cy_memory_2_row_size = 0x200; + + +/* Linker script to configure memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 + wrom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x08000000 + ram_cm0p (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +} + + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + /* Cortex-M0+ ROM vector table */ + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > rom + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > rom + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6ble_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > rom + + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6ble_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > rom + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram_cm0p + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram_cm0p + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram_cm0p + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram_cm0p + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram_cm0p + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram_cm0p + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram_cm0p) + LENGTH(ram_cm0p); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* The section is used for BLE bonding data storage. */ + ble_bond_data 0x14000000 : + { + __ble_bond_data_start = . ; + KEEP(*(.ble_bond_data)) + __ble_bond_data_end = . ; + } > wrom + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .xip 0x18000000 : + { + . = ALIGN(4); + __xip_data_start = . ; + KEEP(*(.xip)) + __xip_data_end = . ; + } > xip + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE + .cychipprotect 0x90600000 : { KEEP(*(.cychipprotect)) } :NONE +} + + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S new file mode 100644 index 0000000000..131fc910da --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S @@ -0,0 +1,101 @@ +/***************************************************************************//** +* \file cy_syslib_core_armcc.s +* \version 1.0 +* +* \brief Assembly routines for GNU as. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +.syntax unified +.text +.thumb + + +/******************************************************************************* +* Function Name: Cy_SysLib_DelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* \param uint32_t cycles: The number of cycles to delay. +* +*******************************************************************************/ +/* void Cy_SysLib_DelayCycles(uint32_t cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global Cy_SysLib_DelayCycles +.func Cy_SysLib_DelayCycles, Cy_SysLib_DelayCycles +.type Cy_SysLib_DelayCycles, %function +.thumb_func +Cy_SysLib_DelayCycles: /* cycles bytes */ + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ Cy_DelayCycles_done /* 2 2 Skip if 0 */ +Cy_DelayCycles_loop: +/* For CM0+ branch instruction takes 2 CPU cycles */ + ADDS r0, r0, #1 /* 1 2 Increment counter */ + SUBS r0, r0, #2 /* 1 2 Decrement counter by 2 */ + BNE Cy_DelayCycles_loop /* 2 2 2 CPU cycles (if branch is taken)*/ + NOP /* 1 2 Loop alignment padding */ +Cy_DelayCycles_done: + NOP /* 1 2 Loop alignment padding */ + BX lr /* 3 2 */ +.endfunc + + +/******************************************************************************* +* Function Name: Cy_SysLib_EnterCriticalSection +****************************************************************************//** +* +* Cy_SysLib_EnterCriticalSection disables interrupts and returns a value +* indicating whether interrupts were previously enabled. +* +* Note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ +* enable bit with interrupts still enabled. +* +* \return Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8_t Cy_SysLib_EnterCriticalSection(void) */ +.global Cy_SysLib_EnterCriticalSection +.func Cy_SysLib_EnterCriticalSection, Cy_SysLib_EnterCriticalSection +.type Cy_SysLib_EnterCriticalSection, %function +.thumb_func +Cy_SysLib_EnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + CPSID I /* Disable interrupts */ + BX lr +.endfunc + + +/******************************************************************************* +* Function Name: Cy_SysLib_ExitCriticalSection +****************************************************************************//** +* +* Re-enables interrupts if they were enabled before +* Cy_SysLib_EnterCriticalSection() was called. The argument should be the value +* returned from \ref Cy_SysLib_EnterCriticalSection(). +* +* \param uint8_t savedIntrStatus: +* Saved interrupt status returned by the \ref Cy_SysLib_EnterCriticalSection(). +* +*******************************************************************************/ +/* void Cy_SysLib_ExitCriticalSection(uint8_t savedIntrStatus) */ +.global Cy_SysLib_ExitCriticalSection +.func Cy_SysLib_ExitCriticalSection, Cy_SysLib_ExitCriticalSection +.type Cy_SysLib_ExitCriticalSection, %function +.thumb_func +Cy_SysLib_ExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr +.endfunc + +.end + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/startup_psoc6ble_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/startup_psoc6ble_cm0plus.S new file mode 100644 index 0000000000..7cb88f5e8f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/startup_psoc6ble_cm0plus.S @@ -0,0 +1,423 @@ +/**************************************************************************//** + * @file startup_psoc6ble_cm0plus.s + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The Cortex-M4 VTOR register */ + #define CY_CORTEX_M4_VTOR_ADDR 0x402102C0 + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Power Mode Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* DeepSleep GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* DeepSleep GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* DeepSleep GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* DeepSleep GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* DeepSleep GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* DeepSleep GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* DeepSleep GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* DeepSleep GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* DeepSleep GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* DeepSleep GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* DeepSleep GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* DeepSleep GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* DeepSleep GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* DeepSleep GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* DeepSleep GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* DeepSleep GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* DeepSleep GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* DeepSleep Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* DeepSleep Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* DeepSleep Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* DeepSleep Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* DeepSleep Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* DeepSleep Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* DeepSleep CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* DeepSleep Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* DeepSleep CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* DeepSleep CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* DeepSleep CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* DeepSleep CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* DeepSleep CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* DeepSleep CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* DeepSleep CPUSS Inter Process Communication Interrupt #6 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function +Cy_OnResetUser: + + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Saves and disables the interrupts */ + .global Cy_SaveIRQ + .func Cy_SaveIRQ, Cy_SaveIRQ + .type Cy_SaveIRQ, %function +Cy_SaveIRQ: + mrs r0, PRIMASK + cpsid i + bx lr + .size Cy_SaveIRQ, . - Cy_SaveIRQ + .endfunc + + /* Restores the interrupts */ + .global Cy_RestoreIRQ + .func Cy_RestoreIRQ, Cy_RestoreIRQ + .type Cy_RestoreIRQ, %function +Cy_RestoreIRQ: + msr PRIMASK, r0 + bx lr + .size Cy_RestoreIRQ, . - Cy_RestoreIRQ + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + + + .type Fault_Handler, %function +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler + def_irq_handler ioss_interrupts_gpio_1_IRQHandler + def_irq_handler ioss_interrupts_gpio_2_IRQHandler + def_irq_handler ioss_interrupts_gpio_3_IRQHandler + def_irq_handler ioss_interrupts_gpio_4_IRQHandler + def_irq_handler ioss_interrupts_gpio_5_IRQHandler + def_irq_handler ioss_interrupts_gpio_6_IRQHandler + def_irq_handler ioss_interrupts_gpio_7_IRQHandler + def_irq_handler ioss_interrupts_gpio_8_IRQHandler + def_irq_handler ioss_interrupts_gpio_9_IRQHandler + def_irq_handler ioss_interrupts_gpio_10_IRQHandler + def_irq_handler ioss_interrupts_gpio_11_IRQHandler + def_irq_handler ioss_interrupts_gpio_12_IRQHandler + def_irq_handler ioss_interrupts_gpio_13_IRQHandler + def_irq_handler ioss_interrupts_gpio_14_IRQHandler + def_irq_handler ioss_interrupt_gpio_IRQHandler + def_irq_handler ioss_interrupt_vdd_IRQHandler + def_irq_handler lpcomp_interrupt_IRQHandler + def_irq_handler scb_8_interrupt_IRQHandler + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler + def_irq_handler srss_interrupt_backup_IRQHandler + def_irq_handler srss_interrupt_IRQHandler + def_irq_handler pass_interrupt_ctbs_IRQHandler + def_irq_handler bless_interrupt_IRQHandler + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cmsis.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cmsis.h new file mode 100644 index 0000000000..5de272b134 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) XXX + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "cy8c637bzi_bld74.h" // IRQn - could include "include/cy_device_headers.h" +#include "core_cm0plus.h" // NVIC + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cy8c637bzi_bld74.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cy8c637bzi_bld74.h new file mode 100644 index 0000000000..8a451ed880 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cy8c637bzi_bld74.h @@ -0,0 +1,1030 @@ +/***************************************************************************//** +* \file cy8c637bzi_bld74.h +* +* \brief +* CY8C637BZI-BLD74 device header +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CY8C637BZI_BLD74_H_ +#define _CY8C637BZI_BLD74_H_ + +/** +* \addtogroup group_device CY8C637BZI-BLD74 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) +/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +#else +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +#endif +/* ====================================== cy8c637bzi_bld74 Specific Interrupt Numbers ====================================== */ + ioss_interrupts_gpio0_IRQn = 0, /*!< 0 GPIO Port Interrupt #0 */ + ioss_interrupts_gpio1_IRQn = 1, /*!< 1 GPIO Port Interrupt #1 */ + ioss_interrupts_gpio2_IRQn = 2, /*!< 2 GPIO Port Interrupt #2 */ + ioss_interrupts_gpio3_IRQn = 3, /*!< 3 GPIO Port Interrupt #3 */ + ioss_interrupts_gpio4_IRQn = 4, /*!< 4 GPIO Port Interrupt #4 */ + ioss_interrupts_gpio5_IRQn = 5, /*!< 5 GPIO Port Interrupt #5 */ + ioss_interrupts_gpio6_IRQn = 6, /*!< 6 GPIO Port Interrupt #6 */ + ioss_interrupts_gpio7_IRQn = 7, /*!< 7 GPIO Port Interrupt #7 */ + ioss_interrupts_gpio8_IRQn = 8, /*!< 8 GPIO Port Interrupt #8 */ + ioss_interrupts_gpio9_IRQn = 9, /*!< 9 GPIO Port Interrupt #9 */ + ioss_interrupts_gpio10_IRQn = 10, /*!< 10 GPIO Port Interrupt #10 */ + ioss_interrupts_gpio11_IRQn = 11, /*!< 11 GPIO Port Interrupt #11 */ + ioss_interrupts_gpio12_IRQn = 12, /*!< 12 GPIO Port Interrupt #12 */ + ioss_interrupts_gpio13_IRQn = 13, /*!< 13 GPIO Port Interrupt #13 */ + ioss_interrupts_gpio14_IRQn = 14, /*!< 14 GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 Low Power Comparator Interrupt */ + scb8_interrupt_IRQn = 18, /*!< 18 Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt0_IRQn = 19, /*!< 19 Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt1_IRQn = 20, /*!< 20 Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 Bluetooth Radio interrupt */ + cpuss_interrupts_ipc0_IRQn = 25, /*!< 25 CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc1_IRQn = 26, /*!< 26 CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc2_IRQn = 27, /*!< 27 CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc3_IRQn = 28, /*!< 28 CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc4_IRQn = 29, /*!< 29 CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc5_IRQn = 30, /*!< 30 CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc6_IRQn = 31, /*!< 31 CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc7_IRQn = 32, /*!< 32 CPUSS Inter Process Communication Interrupt #7 */ + scb0_interrupt_IRQn = 33, /*!< 33 Serial Communication Block #0 */ + scb1_interrupt_IRQn = 34, /*!< 34 Serial Communication Block #1 */ + scb2_interrupt_IRQn = 35, /*!< 35 Serial Communication Block #2 */ + scb3_interrupt_IRQn = 36, /*!< 36 Serial Communication Block #3 */ + scb4_interrupt_IRQn = 37, /*!< 37 Serial Communication Block #4 */ + scb5_interrupt_IRQn = 38, /*!< 38 Serial Communication Block #5 */ + scb6_interrupt_IRQn = 39, /*!< 39 Serial Communication Block #6 */ + scb7_interrupt_IRQn = 40, /*!< 40 Serial Communication Block #7 */ + csd_interrupt_IRQn = 41, /*!< 41 CSD (Capsense) interrupt */ + cpuss_interrupts_dw00_IRQn = 42, /*!< 42 CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw01_IRQn = 43, /*!< 43 CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw02_IRQn = 44, /*!< 44 CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw03_IRQn = 45, /*!< 45 CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw04_IRQn = 46, /*!< 46 CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw05_IRQn = 47, /*!< 47 CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw06_IRQn = 48, /*!< 48 CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw07_IRQn = 49, /*!< 49 CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw08_IRQn = 50, /*!< 50 CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw09_IRQn = 51, /*!< 51 CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw010_IRQn = 52, /*!< 52 CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw011_IRQn = 53, /*!< 53 CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw012_IRQn = 54, /*!< 54 CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw013_IRQn = 55, /*!< 55 CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw014_IRQn = 56, /*!< 56 CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw015_IRQn = 57, /*!< 57 CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw10_IRQn = 58, /*!< 58 CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw11_IRQn = 59, /*!< 59 CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw12_IRQn = 60, /*!< 60 CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw13_IRQn = 61, /*!< 61 CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw14_IRQn = 62, /*!< 62 CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw15_IRQn = 63, /*!< 63 CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw16_IRQn = 64, /*!< 64 CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw17_IRQn = 65, /*!< 65 CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw18_IRQn = 66, /*!< 66 CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw19_IRQn = 67, /*!< 67 CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw110_IRQn = 68, /*!< 68 CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw111_IRQn = 69, /*!< 69 CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw112_IRQn = 70, /*!< 70 CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw113_IRQn = 71, /*!< 71 CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw114_IRQn = 72, /*!< 72 CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw115_IRQn = 73, /*!< 73 CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault0_IRQn = 74, /*!< 74 CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault1_IRQn = 75, /*!< 75 CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 76, /*!< 76 CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 77, /*!< 77 FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti0_IRQn = 78, /*!< 78 CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti1_IRQn = 79, /*!< 79 CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti0_IRQn = 80, /*!< 80 CM4 CTI #0 */ + cpuss_interrupts_cm4_cti1_IRQn = 81, /*!< 81 CM4 CTI #1 */ + tcpwm0_interrupts0_IRQn = 82, /*!< 82 TCPWM #0, Counter #0 */ + tcpwm0_interrupts1_IRQn = 83, /*!< 83 TCPWM #0, Counter #1 */ + tcpwm0_interrupts2_IRQn = 84, /*!< 84 TCPWM #0, Counter #2 */ + tcpwm0_interrupts3_IRQn = 85, /*!< 85 TCPWM #0, Counter #3 */ + tcpwm0_interrupts4_IRQn = 86, /*!< 86 TCPWM #0, Counter #4 */ + tcpwm0_interrupts5_IRQn = 87, /*!< 87 TCPWM #0, Counter #5 */ + tcpwm0_interrupts6_IRQn = 88, /*!< 88 TCPWM #0, Counter #6 */ + tcpwm0_interrupts7_IRQn = 89, /*!< 89 TCPWM #0, Counter #7 */ + tcpwm1_interrupts0_IRQn = 90, /*!< 90 TCPWM #1, Counter #0 */ + tcpwm1_interrupts1_IRQn = 91, /*!< 91 TCPWM #1, Counter #1 */ + tcpwm1_interrupts2_IRQn = 92, /*!< 92 TCPWM #1, Counter #2 */ + tcpwm1_interrupts3_IRQn = 93, /*!< 93 TCPWM #1, Counter #3 */ + tcpwm1_interrupts4_IRQn = 94, /*!< 94 TCPWM #1, Counter #4 */ + tcpwm1_interrupts5_IRQn = 95, /*!< 95 TCPWM #1, Counter #5 */ + tcpwm1_interrupts6_IRQn = 96, /*!< 96 TCPWM #1, Counter #6 */ + tcpwm1_interrupts7_IRQn = 97, /*!< 97 TCPWM #1, Counter #7 */ + tcpwm1_interrupts8_IRQn = 98, /*!< 98 TCPWM #1, Counter #8 */ + tcpwm1_interrupts9_IRQn = 99, /*!< 99 TCPWM #1, Counter #9 */ + tcpwm1_interrupts10_IRQn = 100, /*!< 100 TCPWM #1, Counter #10 */ + tcpwm1_interrupts11_IRQn = 101, /*!< 101 TCPWM #1, Counter #11 */ + tcpwm1_interrupts12_IRQn = 102, /*!< 102 TCPWM #1, Counter #12 */ + tcpwm1_interrupts13_IRQn = 103, /*!< 103 TCPWM #1, Counter #13 */ + tcpwm1_interrupts14_IRQn = 104, /*!< 104 TCPWM #1, Counter #14 */ + tcpwm1_interrupts15_IRQn = 105, /*!< 105 TCPWM #1, Counter #15 */ + tcpwm1_interrupts16_IRQn = 106, /*!< 106 TCPWM #1, Counter #16 */ + tcpwm1_interrupts17_IRQn = 107, /*!< 107 TCPWM #1, Counter #17 */ + tcpwm1_interrupts18_IRQn = 108, /*!< 108 TCPWM #1, Counter #18 */ + tcpwm1_interrupts19_IRQn = 109, /*!< 109 TCPWM #1, Counter #19 */ + tcpwm1_interrupts20_IRQn = 110, /*!< 110 TCPWM #1, Counter #20 */ + tcpwm1_interrupts21_IRQn = 111, /*!< 111 TCPWM #1, Counter #21 */ + tcpwm1_interrupts22_IRQn = 112, /*!< 112 TCPWM #1, Counter #22 */ + tcpwm1_interrupts23_IRQn = 113, /*!< 113 TCPWM #1, Counter #23 */ + udb_interrupts0_IRQn = 114, /*!< 114 UDB Interrupt #0 */ + udb_interrupts1_IRQn = 115, /*!< 115 UDB Interrupt #1 */ + udb_interrupts2_IRQn = 116, /*!< 116 UDB Interrupt #2 */ + udb_interrupts3_IRQn = 117, /*!< 117 UDB Interrupt #3 */ + udb_interrupts4_IRQn = 118, /*!< 118 UDB Interrupt #4 */ + udb_interrupts5_IRQn = 119, /*!< 119 UDB Interrupt #5 */ + udb_interrupts6_IRQn = 120, /*!< 120 UDB Interrupt #6 */ + udb_interrupts7_IRQn = 121, /*!< 121 UDB Interrupt #7 */ + udb_interrupts8_IRQn = 122, /*!< 122 UDB Interrupt #8 */ + udb_interrupts9_IRQn = 123, /*!< 123 UDB Interrupt #9 */ + udb_interrupts10_IRQn = 124, /*!< 124 UDB Interrupt #10 */ + udb_interrupts11_IRQn = 125, /*!< 125 UDB Interrupt #11 */ + udb_interrupts12_IRQn = 126, /*!< 126 UDB Interrupt #12 */ + udb_interrupts13_IRQn = 127, /*!< 127 UDB Interrupt #13 */ + udb_interrupts14_IRQn = 128, /*!< 128 UDB Interrupt #14 */ + udb_interrupts15_IRQn = 129, /*!< 129 UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 130, /*!< 130 SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 131, /*!< 131 I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 132, /*!< 132 PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 133, /*!< 133 Energy Profiler interrupt */ + smif_interrupt_IRQn = 134, /*!< 134 Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 135, /*!< 135 USB Interrupt */ + usb_interrupt_med_IRQn = 136, /*!< 136 USB Interrupt */ + usb_interrupt_lo_IRQn = 137, /*!< 137 USB Interrupt */ + pass_interrupt_dacs_IRQn = 138 /*!< 138 Consolidated interrrupt for all DACs */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + +/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_psoc6ble_cm0plus.h" /*!< PSoC 6 BLE System */ + +#else + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_psoc6ble_cm4.h" /*!< PSoC 6 BLE System */ + +#endif + +#include "psoc6ble_config.h" +#include "gpio_psoc6ble_116_bga_ble.h" + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00020000UL +#define CY_SRAM0_BASE 0x08000000UL +#define CY_SRAM0_SIZE 0x00048000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_WFLASH_BASE 0x14000000UL +#define CY_WFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL + +#define CY_SILICON_ID 0xE2011100UL + +/* Device power profile */ +typedef enum +{ + CY_POWER_MODE_ULP = 0, + CY_POWER_MODE_LP = 1, + CY_POWER_MODE_ANY = 2, +} cy_en_power_mode_t; + +#define CY_POWER_MODE CY_POWER_MODE_ANY + +#define CY_HF_CLK_MAX_FREQ 150000000UL + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +/* Include IP definitions */ +#include "cyip_sflash.h" +#include "cyip_peri.h" +#include "cyip_crypto.h" +#include "cyip_cpuss.h" +#include "cyip_fault.h" +#include "cyip_ipc.h" +#include "cyip_prot.h" +#include "cyip_flashc.h" +#include "cyip_srss.h" +#include "cyip_backup.h" +#include "cyip_dw.h" +#include "cyip_efuse.h" +#include "cyip_profile.h" +#include "cyip_hsiom.h" +#include "cyip_gpio.h" +#include "cyip_smartio.h" +#include "cyip_udb.h" +#include "cyip_lpcomp.h" +#include "cyip_csd.h" +#include "cyip_tcpwm.h" +#include "cyip_lcd.h" +#include "cyip_ble.h" +#include "cyip_smif.h" +#include "cyip_scb.h" +#include "cyip_ctbm.h" +#include "cyip_ctdac.h" +#include "cyip_sar.h" +#include "cyip_pass.h" +#include "cyip_i2s.h" +#include "cyip_pdm.h" + +/* =========================================================================================================================== */ +/* ================ SFLASH ================ */ +/* =========================================================================================================================== */ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/* =========================================================================================================================== */ +/* ================ PERI ================ */ +/* =========================================================================================================================== */ + +#define PERI_BASE 0x40010000UL +#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL +#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL +#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL +#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL +#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL +#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL +#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL +#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL +#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL +#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL +#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL +#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL +#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL +#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL +#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL +#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL +#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL +#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL +#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL +#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL +#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL +#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL +#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL +#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL +#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL +#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL +#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL +#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL +#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL +#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL +#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL +#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL +#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL +#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL +#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL +#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL +#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL +#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL +#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL +#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL +#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL +#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL +#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL +#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL +#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL +#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL +#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL +#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL +#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL +#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL +#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL +#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL +#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL +#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL +#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL +#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL +#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL +#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL +#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL +#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL +#define PERI_GR_PPU_SL_PASS6A_BASE 0x41000040UL +#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL +#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL +#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ +#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ +#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ +#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ +#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ +#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ +#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ +#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ +#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ +#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ +#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ +#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ +#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ +#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ +#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ +#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ +#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ +#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ +#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ +#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ +#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ +#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ +#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ +#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ +#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ +#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ +#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ +#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ +#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ +#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ +#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ +#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ +#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ +#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ +#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ +#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ +#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ +#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ +#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ +#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ +#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ +#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ +#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ +#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ +#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ +#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ +#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ +#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ +#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ +#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ +#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ +#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ +#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ +#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ +#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ +#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ +#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ +#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ +#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ +#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ +#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ +#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ +#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ +#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ +#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ +#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ +#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ +#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ +#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ +#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ +#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ +#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ +#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ +#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ +#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ +#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ +#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ +#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ +#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ +#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ +#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ +#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ +#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ +#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ +#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ +#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ +#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ +#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ +#define PERI_GR_PPU_SL_PASS6A ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS6A_BASE) /* 0x41000040 */ +#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ +#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ +#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ + +/* =========================================================================================================================== */ +/* ================ CRYPTO ================ */ +/* =========================================================================================================================== */ + +#define CRYPTO_BASE 0x40110000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */ + +/* =========================================================================================================================== */ +/* ================ CPUSS ================ */ +/* =========================================================================================================================== */ + +#define CPUSS_BASE 0x40210000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ + +/* =========================================================================================================================== */ +/* ================ FAULT ================ */ +/* =========================================================================================================================== */ + +#define FAULT_BASE 0x40220000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ + +/* =========================================================================================================================== */ +/* ================ IPC ================ */ +/* =========================================================================================================================== */ + +#define IPC_BASE 0x40230000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ + +/* =========================================================================================================================== */ +/* ================ PROT ================ */ +/* =========================================================================================================================== */ + +#define PROT_BASE 0x40240000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ + +/* =========================================================================================================================== */ +/* ================ FLASHC ================ */ +/* =========================================================================================================================== */ + +#define FLASHC_BASE 0x40250000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ + +/* =========================================================================================================================== */ +/* ================ SRSS ================ */ +/* =========================================================================================================================== */ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ +#define CLK_CSV0 ((CLK_CSV_Type*) &SRSS->CLK_CSV[0]) /* 0x40260400 */ + +/* =========================================================================================================================== */ +/* ================ BACKUP ================ */ +/* =========================================================================================================================== */ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/* =========================================================================================================================== */ +/* ================ DW ================ */ +/* =========================================================================================================================== */ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40281000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ +#define DW0_DESCR_STRUCT ((DW_DESCR_STRUCT_Type*) &DW0->DESCR_STRUCT) /* 0x40280C00 */ +#define DW1_DESCR_STRUCT ((DW_DESCR_STRUCT_Type*) &DW1->DESCR_STRUCT) /* 0x40281C00 */ + +/* =========================================================================================================================== */ +/* ================ EFUSE ================ */ +/* =========================================================================================================================== */ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/* =========================================================================================================================== */ +/* ================ PROFILE ================ */ +/* =========================================================================================================================== */ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/* =========================================================================================================================== */ +/* ================ HSIOM ================ */ +/* =========================================================================================================================== */ + +#define HSIOM_BASE 0x40310000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +#define GPIO_BASE 0x40320000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ + +/* =========================================================================================================================== */ +/* ================ SMARTIO ================ */ +/* =========================================================================================================================== */ + +#define SMARTIO_BASE 0x40330000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ + +/* =========================================================================================================================== */ +/* ================ UDB ================ */ +/* =========================================================================================================================== */ + +#define UDB_BASE 0x40340000UL +#define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ +#define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ +#define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ +#define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ +#define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ +#define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */ +#define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */ +#define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */ +#define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */ +#define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */ +#define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */ +#define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */ +#define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */ +#define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */ +#define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */ +#define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */ +#define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */ +#define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ +#define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ +#define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ +#define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ +#define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ +#define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ +#define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */ +#define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */ +#define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */ +#define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */ +#define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */ +#define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */ +#define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */ +#define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */ +#define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */ +#define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */ +#define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */ +#define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */ +#define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */ +#define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */ +#define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */ +#define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */ +#define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */ +#define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */ +#define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */ +#define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */ +#define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */ +#define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */ +#define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */ + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/* =========================================================================================================================== */ +/* ================ CSD ================ */ +/* =========================================================================================================================== */ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/* =========================================================================================================================== */ +/* ================ TCPWM ================ */ +/* =========================================================================================================================== */ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/* =========================================================================================================================== */ +/* ================ LCD ================ */ +/* =========================================================================================================================== */ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/* =========================================================================================================================== */ +/* ================ BLE ================ */ +/* =========================================================================================================================== */ + +#define BLE_BASE 0x403C0000UL +#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ +#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ +#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ + +/* =========================================================================================================================== */ +/* ================ SMIF ================ */ +/* =========================================================================================================================== */ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/* =========================================================================================================================== */ +/* ================ SCB ================ */ +/* =========================================================================================================================== */ + +#define SCB0_BASE 0x40610000UL +#define SCB1_BASE 0x40620000UL +#define SCB2_BASE 0x40630000UL +#define SCB3_BASE 0x40640000UL +#define SCB4_BASE 0x40650000UL +#define SCB5_BASE 0x40660000UL +#define SCB6_BASE 0x40670000UL +#define SCB7_BASE 0x40680000UL +#define SCB8_BASE 0x40690000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ + +/* =========================================================================================================================== */ +/* ================ CTBM ================ */ +/* =========================================================================================================================== */ + +#define CTBM0_BASE 0x41100000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ + +/* =========================================================================================================================== */ +/* ================ CTDAC ================ */ +/* =========================================================================================================================== */ + +#define CTDAC0_BASE 0x41140000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +#define SAR_BASE 0x411D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ + +/* =========================================================================================================================== */ +/* ================ PASS ================ */ +/* =========================================================================================================================== */ + +#define PASS_BASE 0x411F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ + +#define I2S_BASE 0x42A10000UL +#define I2S ((I2S_Type*) I2S_BASE) /* 0x42A10000 */ + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + +#define PDM_BASE 0x42A20000UL +#define PDM ((PDM_Type*) PDM_BASE) /* 0x42A20000 */ + +/** \} CY8C637BZI-BLD74 */ + +#endif /* _CY8C637BZI_BLD74_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cy_device_headers.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cy_device_headers.h new file mode 100644 index 0000000000..815517a8ca --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cy_device_headers.h @@ -0,0 +1,85 @@ +/***************************************************************************//** +* \file cy_device_headers.h +* +* \brief +* Common header file to be included by the drivers. +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CY_DEVICE_HEADERS_H_ +#define _CY_DEVICE_HEADERS_H_ + +#if defined (CY8C622PSVP) + #include "cy8c622psvp.h" +#elif defined (CY8C622PSVP_DUAL) + #include "cy8c622psvp_dual.h" +#elif defined (CY8C616FMI_BL603) + #include "cy8c616fmi_bl603.h" +#elif defined (CY8C616FMI_BL673) + #include "cy8c616fmi_bl673.h" +#elif defined (CY8C616LQI_BL601) + #include "cy8c616lqi_bl601.h" +#elif defined (CY8C616LQI_BL671) + #include "cy8c616lqi_bl671.h" +#elif defined (CY8C617FMI_BL603) + #include "cy8c617fmi_bl603.h" +#elif defined (CY8C617FMI_BLD73) + #include "cy8c617fmi_bld73.h" +#elif defined (CY8C626FMI_BL603) + #include "cy8c626fmi_bl603.h" +#elif defined (CY8C626BZI_BL604) + #include "cy8c626bzi_bl604.h" +#elif defined (CY8C626BZI_BL674) + #include "cy8c626bzi_bl674.h" +#elif defined (CY8C627BZI_BL604) + #include "cy8c627bzi_bl604.h" +#elif defined (CY8C627FMI_BLD73) + #include "cy8c627fmi_bld73.h" +#elif defined (CY8C627BZI_BLD74) + #include "cy8c627bzi_bld74.h" +#elif defined (CY8C636BZI_BL604) + #include "cy8c636bzi_bl604.h" +#elif defined (CY8C636BZI_BL674) + #include "cy8c636bzi_bl674.h" +#elif defined (CY8C636FMI_BL603) + #include "cy8c636fmi_bl603.h" +#elif defined (CY8C636FMI_BL673) + #include "cy8c636fmi_bl673.h" +#elif defined (CY8C636LQI_BL601) + #include "cy8c636lqi_bl601.h" +#elif defined (CY8C636LQI_BL671) + #include "cy8c636lqi_bl671.h" +#elif defined (CY8C637BZI_BLD04) + #include "cy8c637bzi_bld04.h" +#elif defined (CY8C637BZI_BLD74) + #include "cy8c637bzi_bld74.h" +#elif defined (CY8C637FMI_BLD03) + #include "cy8c637fmi_bld03.h" +#elif defined (CY8C637FMI_BLD73) + #include "cy8c637fmi_bld73.h" +#elif defined (CY8C637LQI_BLD01) + #include "cy8c637lqi_bld01.h" +#elif defined (CY8C637LQI_BLD71) + #include "cy8c637lqi_bld71.h" +#elif defined (CY8C68237FM_BLE) + #include "cy8c68237fm_ble.h" +#elif defined (CY8C68237BZ_BLE) + #include "cy8c68237bz_ble.h" +#else + #error Undefined part number +#endif + +#endif /* _CY_DEVICE_HEADERS_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/gpio_psoc6ble_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/gpio_psoc6ble_116_bga_ble.h new file mode 100644 index 0000000000..46d8b6031b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/gpio_psoc6ble_116_bga_ble.h @@ -0,0 +1,1611 @@ +/***************************************************************************//** +* \file gpio_psoc6ble_116_bga_ble.h +* +* \brief +* PSoC 6 BLE device GPIO header for 116-BGA-BLE package +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _GPIO_PSOC6BLE_116_BGA_BLE_H_ +#define _GPIO_PSOC6BLE_116_BGA_BLE_H_ + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_CSHIELDPADS_PORT 7u +#define CSD_CSHIELDPADS_PIN 7u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP0_PORT 5u +#define LPCOMP_INP_COMP0_PIN 6u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_AREF_EXT_VREF_PORT 9u +#define PASS_AREF_EXT_VREF_PIN 7u +#define PASS_CTB_OA0_OUT_10X_PORT 9u +#define PASS_CTB_OA0_OUT_10X_PIN 2u +#define PASS_CTB_OA1_OUT_10X_PORT 9u +#define PASS_CTB_OA1_OUT_10X_PIN 3u +#define PASS_CTB_PADS0_PORT 9u +#define PASS_CTB_PADS0_PIN 0u +#define PASS_CTB_PADS1_PORT 9u +#define PASS_CTB_PADS1_PIN 1u +#define PASS_CTB_PADS2_PORT 9u +#define PASS_CTB_PADS2_PIN 2u +#define PASS_CTB_PADS3_PORT 9u +#define PASS_CTB_PADS3_PIN 3u +#define PASS_CTB_PADS4_PORT 9u +#define PASS_CTB_PADS4_PIN 4u +#define PASS_CTB_PADS5_PORT 9u +#define PASS_CTB_PADS5_PIN 5u +#define PASS_CTB_PADS6_PORT 9u +#define PASS_CTB_PADS6_PIN 6u +#define PASS_CTB_PADS7_PORT 9u +#define PASS_CTB_PADS7_PIN 7u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define PASS_SARMUX_PADS2_PORT 10u +#define PASS_SARMUX_PADS2_PIN 2u +#define PASS_SARMUX_PADS3_PORT 10u +#define PASS_SARMUX_PADS3_PIN 3u +#define PASS_SARMUX_PADS4_PORT 10u +#define PASS_SARMUX_PADS4_PIN 4u +#define PASS_SARMUX_PADS5_PORT 10u +#define PASS_SARMUX_PADS5_PIN 5u +#define PASS_SARMUX_PADS6_PORT 10u +#define PASS_SARMUX_PADS6_PIN 6u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_ECO_IN_PORT 12u +#define SRSS_ECO_IN_PIN 6u +#define SRSS_ECO_OUT_PORT 12u +#define SRSS_ECO_OUT_PIN 7u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ + + /* P0.0 */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ + P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_0_AMUXA = 4, /* Analog mux bus A */ + P0_0_AMUXB = 5, /* Analog mux bus B */ + P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ + P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_1_AMUXA = 4, /* Analog mux bus A */ + P0_1_AMUXB = 5, /* Analog mux bus B */ + P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P0.2 */ + P0_2_GPIO = 0, /* GPIO controls 'out' */ + P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_2_AMUXA = 4, /* Analog mux bus A */ + P0_2_AMUXB = 5, /* Analog mux bus B */ + P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ + P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ + P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ + P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ + P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ + P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ + P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ + P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ + P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ + + /* P0.3 */ + P0_3_GPIO = 0, /* GPIO controls 'out' */ + P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_3_AMUXA = 4, /* Analog mux bus A */ + P0_3_AMUXB = 5, /* Analog mux bus B */ + P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ + P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ + P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ + P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ + P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ + P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ + P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ + P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ + P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ + + /* P0.4 */ + P0_4_GPIO = 0, /* GPIO controls 'out' */ + P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_4_AMUXA = 4, /* Analog mux bus A */ + P0_4_AMUXB = 5, /* Analog mux bus B */ + P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ + P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ + P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ + P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ + P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ + P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ + P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ + P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ + P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ + + /* P0.5 */ + P0_5_GPIO = 0, /* GPIO controls 'out' */ + P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_5_AMUXA = 4, /* Analog mux bus A */ + P0_5_AMUXB = 5, /* Analog mux bus B */ + P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ + P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ + P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ + P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ + P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ + P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ + P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ + P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ + P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ + P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ + + /* P1.0 */ + P1_0_GPIO = 0, /* GPIO controls 'out' */ + P1_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_0_AMUXA = 4, /* Analog mux bus A */ + P1_0_AMUXB = 5, /* Analog mux bus B */ + P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ + P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ + P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ + P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ + P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ + P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ + P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */ + P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */ + P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */ + P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ + + /* P1.1 */ + P1_1_GPIO = 0, /* GPIO controls 'out' */ + P1_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_1_AMUXA = 4, /* Analog mux bus A */ + P1_1_AMUXB = 5, /* Analog mux bus B */ + P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ + P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ + P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ + P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ + P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ + P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ + P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */ + P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */ + P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */ + P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ + + /* P1.2 */ + P1_2_GPIO = 0, /* GPIO controls 'out' */ + P1_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_2_AMUXA = 4, /* Analog mux bus A */ + P1_2_AMUXB = 5, /* Analog mux bus B */ + P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_2_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:4 */ + P1_2_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:1 */ + P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ + P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ + P1_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ + P1_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ + P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */ + P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */ + + /* P1.3 */ + P1_3_GPIO = 0, /* GPIO controls 'out' */ + P1_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_3_AMUXA = 4, /* Analog mux bus A */ + P1_3_AMUXB = 5, /* Analog mux bus B */ + P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_3_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:4 */ + P1_3_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ + P1_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ + P1_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ + P1_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ + P1_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ + P1_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:0 */ + P1_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:0 */ + + /* P1.4 */ + P1_4_GPIO = 0, /* GPIO controls 'out' */ + P1_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_4_AMUXA = 4, /* Analog mux bus A */ + P1_4_AMUXB = 5, /* Analog mux bus B */ + P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */ + P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */ + P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ + P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ + P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ + P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ + P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */ + + /* P1.5 */ + P1_5_GPIO = 0, /* GPIO controls 'out' */ + P1_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_5_AMUXA = 4, /* Analog mux bus A */ + P1_5_AMUXB = 5, /* Analog mux bus B */ + P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */ + P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ + P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ + P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ + P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ + P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ + P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ + + /* P5.0 */ + P5_0_GPIO = 0, /* GPIO controls 'out' */ + P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_0_AMUXA = 4, /* Analog mux bus A */ + P5_0_AMUXB = 5, /* Analog mux bus B */ + P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ + P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ + P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ + P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ + P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ + P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ + P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ + P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ + P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ + P5_0_AUDIOSS_CLK_I2S_IF = 22, /* Digital Active - audioss.clk_i2s_if */ + P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ + + /* P5.1 */ + P5_1_GPIO = 0, /* GPIO controls 'out' */ + P5_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_1_AMUXA = 4, /* Analog mux bus A */ + P5_1_AMUXB = 5, /* Analog mux bus B */ + P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ + P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ + P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ + P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ + P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ + P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ + P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ + P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ + P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ + P5_1_AUDIOSS_TX_SCK = 22, /* Digital Active - audioss.tx_sck */ + P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ + + /* P5.2 */ + P5_2_GPIO = 0, /* GPIO controls 'out' */ + P5_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_2_AMUXA = 4, /* Analog mux bus A */ + P5_2_AMUXB = 5, /* Analog mux bus B */ + P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ + P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ + P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ + P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ + P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ + P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ + P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ + P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ + P5_2_AUDIOSS_TX_WS = 22, /* Digital Active - audioss.tx_ws */ + + /* P5.3 */ + P5_3_GPIO = 0, /* GPIO controls 'out' */ + P5_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_3_AMUXA = 4, /* Analog mux bus A */ + P5_3_AMUXB = 5, /* Analog mux bus B */ + P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */ + P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ + P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ + P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ + P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ + P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ + P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ + P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ + P5_3_AUDIOSS_TX_SDO = 22, /* Digital Active - audioss.tx_sdo */ + + /* P5.4 */ + P5_4_GPIO = 0, /* GPIO controls 'out' */ + P5_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_4_AMUXA = 4, /* Analog mux bus A */ + P5_4_AMUXB = 5, /* Analog mux bus B */ + P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ + P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ + P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ + P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ + P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ + P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ + P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ + P5_4_AUDIOSS_RX_SCK = 22, /* Digital Active - audioss.rx_sck */ + + /* P5.5 */ + P5_5_GPIO = 0, /* GPIO controls 'out' */ + P5_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_5_AMUXA = 4, /* Analog mux bus A */ + P5_5_AMUXB = 5, /* Analog mux bus B */ + P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */ + P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ + P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ + P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ + P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ + P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ + P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ + P5_5_AUDIOSS_RX_WS = 22, /* Digital Active - audioss.rx_ws */ + + /* P5.6 */ + P5_6_GPIO = 0, /* GPIO controls 'out' */ + P5_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_6_AMUXA = 4, /* Analog mux bus A */ + P5_6_AMUXB = 5, /* Analog mux bus B */ + P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ + P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ + P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ + P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ + P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ + P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ + P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ + P5_6_AUDIOSS_RX_SDI = 22, /* Digital Active - audioss.rx_sdi */ + + /* P6.0 */ + P6_0_GPIO = 0, /* GPIO controls 'out' */ + P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_0_AMUXA = 4, /* Analog mux bus A */ + P6_0_AMUXB = 5, /* Analog mux bus B */ + P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ + P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ + P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ + P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ + P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ + P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ + P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ + P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ + P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ + P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ + P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ + P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ + + /* P6.1 */ + P6_1_GPIO = 0, /* GPIO controls 'out' */ + P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_1_AMUXA = 4, /* Analog mux bus A */ + P6_1_AMUXB = 5, /* Analog mux bus B */ + P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ + P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ + P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ + P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ + P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ + P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ + P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ + P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ + P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ + P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ + P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ + P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ + + /* P6.2 */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ + P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_2_AMUXA = 4, /* Analog mux bus A */ + P6_2_AMUXB = 5, /* Analog mux bus B */ + P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ + P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ + P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ + + /* P6.3 */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ + P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_3_AMUXA = 4, /* Analog mux bus A */ + P6_3_AMUXB = 5, /* Analog mux bus B */ + P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ + P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ + P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ + + /* P6.4 */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ + P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_4_AMUXA = 4, /* Analog mux bus A */ + P6_4_AMUXB = 5, /* Analog mux bus B */ + P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ + P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ + P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ + P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ + P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ + P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_5_AMUXA = 4, /* Analog mux bus A */ + P6_5_AMUXB = 5, /* Analog mux bus B */ + P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ + P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ + P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ + P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ + P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ + P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ + P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_6_AMUXA = 4, /* Analog mux bus A */ + P6_6_AMUXB = 5, /* Analog mux bus B */ + P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ + P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ + P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ + P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ + P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_7_AMUXA = 4, /* Analog mux bus A */ + P6_7_AMUXB = 5, /* Analog mux bus B */ + P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ + P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ + P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ + P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ + P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ + P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ + P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ + + /* P7.4 */ + P7_4_GPIO = 0, /* GPIO controls 'out' */ + P7_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_4_AMUXA = 4, /* Analog mux bus A */ + P7_4_AMUXB = 5, /* Analog mux bus B */ + P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ + P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */ + P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ + P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ + P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ + P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ + P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ + P7_4_BLESS_EXT_LNA_RX_CTL_OUT = 26, /* Digital Active - bless.ext_lna_rx_ctl_out */ + P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ + + /* P7.5 */ + P7_5_GPIO = 0, /* GPIO controls 'out' */ + P7_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_5_AMUXA = 4, /* Analog mux bus A */ + P7_5_AMUXB = 5, /* Analog mux bus B */ + P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */ + P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ + P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ + P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ + P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ + P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ + P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ + P7_5_BLESS_EXT_PA_TX_CTL_OUT = 26, /* Digital Active - bless.ext_pa_tx_ctl_out */ + P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ + + /* P7.6 */ + P7_6_GPIO = 0, /* GPIO controls 'out' */ + P7_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_6_AMUXA = 4, /* Analog mux bus A */ + P7_6_AMUXB = 5, /* Analog mux bus B */ + P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ + P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */ + P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ + P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ + P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ + P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ + P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ + P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT = 26, /* Digital Active - bless.ext_pa_lna_chip_en_out */ + P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ + + /* P7.7 */ + P7_7_GPIO = 0, /* GPIO controls 'out' */ + P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_7_AMUXA = 4, /* Analog mux bus A */ + P7_7_AMUXB = 5, /* Analog mux bus B */ + P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ + P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ + P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ + P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ + P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ + P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ + P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ + P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ + P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ + + /* P8.0 */ + P8_0_GPIO = 0, /* GPIO controls 'out' */ + P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_0_AMUXA = 4, /* Analog mux bus A */ + P8_0_AMUXB = 5, /* Analog mux bus B */ + P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ + P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ + P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ + P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ + P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ + + /* P8.1 */ + P8_1_GPIO = 0, /* GPIO controls 'out' */ + P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_1_AMUXA = 4, /* Analog mux bus A */ + P8_1_AMUXB = 5, /* Analog mux bus B */ + P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ + P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ + P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ + P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ + P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ + + /* P8.2 */ + P8_2_GPIO = 0, /* GPIO controls 'out' */ + P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_2_AMUXA = 4, /* Analog mux bus A */ + P8_2_AMUXB = 5, /* Analog mux bus B */ + P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ + P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ + P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ + P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ + P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ + P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ + P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ + P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ + P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ + + /* P8.3 */ + P8_3_GPIO = 0, /* GPIO controls 'out' */ + P8_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_3_AMUXA = 4, /* Analog mux bus A */ + P8_3_AMUXB = 5, /* Analog mux bus B */ + P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ + P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ + P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ + P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ + P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ + P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ + P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ + P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ + P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ + + /* P8.4 */ + P8_4_GPIO = 0, /* GPIO controls 'out' */ + P8_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_4_AMUXA = 4, /* Analog mux bus A */ + P8_4_AMUXB = 5, /* Analog mux bus B */ + P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ + P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */ + P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ + P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ + P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ + P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ + P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ + + /* P8.5 */ + P8_5_GPIO = 0, /* GPIO controls 'out' */ + P8_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_5_AMUXA = 4, /* Analog mux bus A */ + P8_5_AMUXB = 5, /* Analog mux bus B */ + P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ + P8_5_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ + P8_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ + P8_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ + P8_5_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ + P8_5_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ + P8_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */ + + /* P8.6 */ + P8_6_GPIO = 0, /* GPIO controls 'out' */ + P8_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_6_AMUXA = 4, /* Analog mux bus A */ + P8_6_AMUXB = 5, /* Analog mux bus B */ + P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ + P8_6_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:0 */ + P8_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ + P8_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ + P8_6_LCD_COM60 = 12, /* Digital Deep Sleep - lcd.com[60]:0 */ + P8_6_LCD_SEG60 = 13, /* Digital Deep Sleep - lcd.seg[60]:0 */ + P8_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:0 */ + + /* P8.7 */ + P8_7_GPIO = 0, /* GPIO controls 'out' */ + P8_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_7_AMUXA = 4, /* Analog mux bus A */ + P8_7_AMUXB = 5, /* Analog mux bus B */ + P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ + P8_7_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ + P8_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ + P8_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ + P8_7_LCD_COM61 = 12, /* Digital Deep Sleep - lcd.com[61]:0 */ + P8_7_LCD_SEG61 = 13, /* Digital Deep Sleep - lcd.seg[61]:0 */ + P8_7_SCB3_SPI_SELECT2 = 20, /* Digital Active - scb[3].spi_select2:0 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ + P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ + P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ + P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ + P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ + P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ + P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ + P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ + P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ + P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ + P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ + P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ + P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P9.4 */ + P9_4_GPIO = 0, /* GPIO controls 'out' */ + P9_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_4_AMUXA = 4, /* Analog mux bus A */ + P9_4_AMUXB = 5, /* Analog mux bus B */ + P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */ + P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ + P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */ + P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */ + P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */ + P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */ + P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ + + /* P9.5 */ + P9_5_GPIO = 0, /* GPIO controls 'out' */ + P9_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_5_AMUXA = 4, /* Analog mux bus A */ + P9_5_AMUXB = 5, /* Analog mux bus B */ + P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_5_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:5 */ + P9_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */ + P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:67 */ + P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:67 */ + P9_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:1 */ + P9_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:1 */ + P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */ + + /* P9.6 */ + P9_6_GPIO = 0, /* GPIO controls 'out' */ + P9_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_6_AMUXA = 4, /* Analog mux bus A */ + P9_6_AMUXB = 5, /* Analog mux bus B */ + P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_6_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ + P9_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */ + P9_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:68 */ + P9_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:68 */ + P9_6_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:1 */ + P9_6_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:1 */ + P9_6_SCB2_SPI_SELECT3 = 20, /* Digital Active - scb[2].spi_select3:0 */ + + /* P9.7 */ + P9_7_GPIO = 0, /* GPIO controls 'out' */ + P9_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_7_AMUXA = 4, /* Analog mux bus A */ + P9_7_AMUXB = 5, /* Analog mux bus B */ + P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ + P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ + P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */ + P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */ + P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */ + P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ + P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ + P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ + P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ + P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ + P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ + P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + + /* P10.2 */ + P10_2_GPIO = 0, /* GPIO controls 'out' */ + P10_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_2_AMUXA = 4, /* Analog mux bus A */ + P10_2_AMUXB = 5, /* Analog mux bus B */ + P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ + P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ + P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ + P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ + P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ + P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ + P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ + P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ + P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ + + /* P10.3 */ + P10_3_GPIO = 0, /* GPIO controls 'out' */ + P10_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_3_AMUXA = 4, /* Analog mux bus A */ + P10_3_AMUXB = 5, /* Analog mux bus B */ + P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ + P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ + P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ + P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ + P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ + P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ + P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ + P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ + P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ + + /* P10.4 */ + P10_4_GPIO = 0, /* GPIO controls 'out' */ + P10_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_4_AMUXA = 4, /* Analog mux bus A */ + P10_4_AMUXB = 5, /* Analog mux bus B */ + P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ + P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ + P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ + P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ + P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ + P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ + P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ + P10_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk */ + + /* P10.5 */ + P10_5_GPIO = 0, /* GPIO controls 'out' */ + P10_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_5_AMUXA = 4, /* Analog mux bus A */ + P10_5_AMUXB = 5, /* Analog mux bus B */ + P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ + P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ + P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ + P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ + P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ + P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ + P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ + P10_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data */ + + /* P10.6 */ + P10_6_GPIO = 0, /* GPIO controls 'out' */ + P10_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_6_AMUXA = 4, /* Analog mux bus A */ + P10_6_AMUXB = 5, /* Analog mux bus B */ + P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ + P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ + P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */ + P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */ + P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */ + P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */ + P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ + + /* P11.0 */ + P11_0_GPIO = 0, /* GPIO controls 'out' */ + P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_0_AMUXA = 4, /* Analog mux bus A */ + P11_0_AMUXB = 5, /* Analog mux bus B */ + P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ + P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ + P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ + P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ + P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ + P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ + P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ + P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ + P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ + P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ + + /* P11.1 */ + P11_1_GPIO = 0, /* GPIO controls 'out' */ + P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_1_AMUXA = 4, /* Analog mux bus A */ + P11_1_AMUXB = 5, /* Analog mux bus B */ + P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ + P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ + P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ + P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ + P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ + P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ + P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ + P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ + P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ + P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ + P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_2_AMUXA = 4, /* Analog mux bus A */ + P11_2_AMUXB = 5, /* Analog mux bus B */ + P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ + P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ + P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ + P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_3_AMUXA = 4, /* Analog mux bus A */ + P11_3_AMUXB = 5, /* Analog mux bus B */ + P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ + P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ + P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ + P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_4_AMUXA = 4, /* Analog mux bus A */ + P11_4_AMUXB = 5, /* Analog mux bus B */ + P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ + P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ + P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ + P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_5_AMUXA = 4, /* Analog mux bus A */ + P11_5_AMUXB = 5, /* Analog mux bus B */ + P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ + P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ + P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ + P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_6_AMUXA = 4, /* Analog mux bus A */ + P11_6_AMUXB = 5, /* Analog mux bus B */ + P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ + P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ + P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ + P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_7_AMUXA = 4, /* Analog mux bus A */ + P11_7_AMUXB = 5, /* Analog mux bus B */ + P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ + + /* P12.0 */ + P12_0_GPIO = 0, /* GPIO controls 'out' */ + P12_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_0_AMUXA = 4, /* Analog mux bus A */ + P12_0_AMUXB = 5, /* Analog mux bus B */ + P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */ + P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ + P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */ + P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */ + P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */ + P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */ + P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ + P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ + P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ + P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ + P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ + + /* P12.1 */ + P12_1_GPIO = 0, /* GPIO controls 'out' */ + P12_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_1_AMUXA = 4, /* Analog mux bus A */ + P12_1_AMUXB = 5, /* Analog mux bus B */ + P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */ + P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ + P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */ + P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */ + P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */ + P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */ + P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ + P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ + P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ + P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ + P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ + + /* P12.2 */ + P12_2_GPIO = 0, /* GPIO controls 'out' */ + P12_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_2_AMUXA = 4, /* Analog mux bus A */ + P12_2_AMUXB = 5, /* Analog mux bus B */ + P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */ + P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ + P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */ + P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */ + P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */ + P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */ + P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ + P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ + P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ + + /* P12.3 */ + P12_3_GPIO = 0, /* GPIO controls 'out' */ + P12_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_3_AMUXA = 4, /* Analog mux bus A */ + P12_3_AMUXB = 5, /* Analog mux bus B */ + P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */ + P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ + P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */ + P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */ + P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */ + P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */ + P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ + P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ + P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ + + /* P12.4 */ + P12_4_GPIO = 0, /* GPIO controls 'out' */ + P12_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_4_AMUXA = 4, /* Analog mux bus A */ + P12_4_AMUXB = 5, /* Analog mux bus B */ + P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */ + P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ + P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */ + P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */ + P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */ + P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */ + P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ + P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ + + /* P12.5 */ + P12_5_GPIO = 0, /* GPIO controls 'out' */ + P12_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_5_AMUXA = 4, /* Analog mux bus A */ + P12_5_AMUXB = 5, /* Analog mux bus B */ + P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */ + P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ + P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */ + P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */ + P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */ + P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */ + P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ + + /* P12.6 */ + P12_6_GPIO = 0, /* GPIO controls 'out' */ + P12_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_6_AMUXA = 4, /* Analog mux bus A */ + P12_6_AMUXB = 5, /* Analog mux bus B */ + P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ + P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ + P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ + P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ + P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ + P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ + P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ + + /* P12.7 */ + P12_7_GPIO = 0, /* GPIO controls 'out' */ + P12_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_7_AMUXA = 4, /* Analog mux bus A */ + P12_7_AMUXB = 5, /* Analog mux bus B */ + P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ + P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ + P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ + P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ + P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ + P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ + + /* P13.0 */ + P13_0_GPIO = 0, /* GPIO controls 'out' */ + P13_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_0_AMUXA = 4, /* Analog mux bus A */ + P13_0_AMUXB = 5, /* Analog mux bus B */ + P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ + P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */ + P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */ + P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */ + P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */ + P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */ + P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ + P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ + P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */ + P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */ + + /* P13.1 */ + P13_1_GPIO = 0, /* GPIO controls 'out' */ + P13_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_1_AMUXA = 4, /* Analog mux bus A */ + P13_1_AMUXB = 5, /* Analog mux bus B */ + P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ + P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ + P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */ + P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */ + P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */ + P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */ + P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ + P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ + P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ + P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */ + + /* P13.6 */ + P13_6_GPIO = 0, /* GPIO controls 'out' */ + P13_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_6_AMUXA = 4, /* Analog mux bus A */ + P13_6_AMUXB = 5, /* Analog mux bus B */ + P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ + P13_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:1 */ + P13_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:99 */ + P13_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:99 */ + P13_6_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:1 */ + P13_6_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:1 */ + P13_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:1 */ + + /* P13.7 */ + P13_7_GPIO = 0, /* GPIO controls 'out' */ + P13_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_7_AMUXA = 4, /* Analog mux bus A */ + P13_7_AMUXB = 5, /* Analog mux bus B */ + P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ + P13_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ + P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ + P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ + P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ + P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC6BLE_116_BGA_BLE_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/psoc6ble_config.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/psoc6ble_config.h new file mode 100644 index 0000000000..347d5fb7d4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/psoc6ble_config.h @@ -0,0 +1,2289 @@ +/***************************************************************************//** +* \file psoc6ble_config.h +* +* \brief +* PSoC 6 BLE device configuration header +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _PSOC6BLE_CONFIG_H_ +#define _PSOC6BLE_CONFIG_H_ + +/* Clock Connections */ +typedef enum +{ + PCLK_SCB0_CLOCK = 0, /* scb[0].clock */ + PCLK_SCB1_CLOCK = 1, /* scb[1].clock */ + PCLK_SCB2_CLOCK = 2, /* scb[2].clock */ + PCLK_SCB3_CLOCK = 3, /* scb[3].clock */ + PCLK_SCB4_CLOCK = 4, /* scb[4].clock */ + PCLK_SCB5_CLOCK = 5, /* scb[5].clock */ + PCLK_SCB6_CLOCK = 6, /* scb[6].clock */ + PCLK_SCB7_CLOCK = 7, /* scb[7].clock */ + PCLK_SCB8_CLOCK = 8, /* scb[8].clock */ + PCLK_UDB_CLOCKS0 = 9, /* udb.clocks[0] */ + PCLK_UDB_CLOCKS1 = 10, /* udb.clocks[1] */ + PCLK_UDB_CLOCKS2 = 11, /* udb.clocks[2] */ + PCLK_UDB_CLOCKS3 = 12, /* udb.clocks[3] */ + PCLK_UDB_CLOCKS4 = 13, /* udb.clocks[4] */ + PCLK_UDB_CLOCKS5 = 14, /* udb.clocks[5] */ + PCLK_UDB_CLOCKS6 = 15, /* udb.clocks[6] */ + PCLK_UDB_CLOCKS7 = 16, /* udb.clocks[7] */ + PCLK_SMARTIO8_CLOCK = 17, /* smartio[8].clock */ + PCLK_SMARTIO9_CLOCK = 18, /* smartio[9].clock */ + PCLK_TCPWM0_CLOCKS0 = 19, /* tcpwm[0].clocks[0] */ + PCLK_TCPWM0_CLOCKS1 = 20, /* tcpwm[0].clocks[1] */ + PCLK_TCPWM0_CLOCKS2 = 21, /* tcpwm[0].clocks[2] */ + PCLK_TCPWM0_CLOCKS3 = 22, /* tcpwm[0].clocks[3] */ + PCLK_TCPWM0_CLOCKS4 = 23, /* tcpwm[0].clocks[4] */ + PCLK_TCPWM0_CLOCKS5 = 24, /* tcpwm[0].clocks[5] */ + PCLK_TCPWM0_CLOCKS6 = 25, /* tcpwm[0].clocks[6] */ + PCLK_TCPWM0_CLOCKS7 = 26, /* tcpwm[0].clocks[7] */ + PCLK_TCPWM1_CLOCKS0 = 27, /* tcpwm[1].clocks[0] */ + PCLK_TCPWM1_CLOCKS1 = 28, /* tcpwm[1].clocks[1] */ + PCLK_TCPWM1_CLOCKS2 = 29, /* tcpwm[1].clocks[2] */ + PCLK_TCPWM1_CLOCKS3 = 30, /* tcpwm[1].clocks[3] */ + PCLK_TCPWM1_CLOCKS4 = 31, /* tcpwm[1].clocks[4] */ + PCLK_TCPWM1_CLOCKS5 = 32, /* tcpwm[1].clocks[5] */ + PCLK_TCPWM1_CLOCKS6 = 33, /* tcpwm[1].clocks[6] */ + PCLK_TCPWM1_CLOCKS7 = 34, /* tcpwm[1].clocks[7] */ + PCLK_TCPWM1_CLOCKS8 = 35, /* tcpwm[1].clocks[8] */ + PCLK_TCPWM1_CLOCKS9 = 36, /* tcpwm[1].clocks[9] */ + PCLK_TCPWM1_CLOCKS10 = 37, /* tcpwm[1].clocks[10] */ + PCLK_TCPWM1_CLOCKS11 = 38, /* tcpwm[1].clocks[11] */ + PCLK_TCPWM1_CLOCKS12 = 39, /* tcpwm[1].clocks[12] */ + PCLK_TCPWM1_CLOCKS13 = 40, /* tcpwm[1].clocks[13] */ + PCLK_TCPWM1_CLOCKS14 = 41, /* tcpwm[1].clocks[14] */ + PCLK_TCPWM1_CLOCKS15 = 42, /* tcpwm[1].clocks[15] */ + PCLK_TCPWM1_CLOCKS16 = 43, /* tcpwm[1].clocks[16] */ + PCLK_TCPWM1_CLOCKS17 = 44, /* tcpwm[1].clocks[17] */ + PCLK_TCPWM1_CLOCKS18 = 45, /* tcpwm[1].clocks[18] */ + PCLK_TCPWM1_CLOCKS19 = 46, /* tcpwm[1].clocks[19] */ + PCLK_TCPWM1_CLOCKS20 = 47, /* tcpwm[1].clocks[20] */ + PCLK_TCPWM1_CLOCKS21 = 48, /* tcpwm[1].clocks[21] */ + PCLK_TCPWM1_CLOCKS22 = 49, /* tcpwm[1].clocks[22] */ + PCLK_TCPWM1_CLOCKS23 = 50, /* tcpwm[1].clocks[23] */ + PCLK_CSD_CLOCK = 51, /* csd.clock */ + PCLK_LCD_CLOCK = 52, /* lcd.clock */ + PCLK_PROFILE_CLOCK_PROFILE = 53, /* profile.clock_profile */ + PCLK_CPUSS_CLOCK_TRACE_IN = 54, /* cpuss.clock_trace_in */ + PCLK_PASS_CLOCK_CTDAC = 55, /* pass.clock_ctdac */ + PCLK_PASS_CLOCK_PUMP_PERI = 56, /* pass.clock_pump_peri */ + PCLK_PASS_CLOCK_SAR = 57, /* pass.clock_sar */ + PCLK_USB_CLOCK_DEV_BRS = 58 /* usb.clock_dev_brs */ +} en_clk_dst_t; + +/* Trigger Group Inputs */ +/* Trigger Input Group 0 - DMA Request Assignments */ +typedef enum +{ + TRIG0_IN_TR_GROUP10_OUTPUT0 = 0x0000u, /* tr_group[10].output[0] */ + TRIG0_IN_TR_GROUP10_OUTPUT1 = 0x0001u, /* tr_group[10].output[1] */ + TRIG0_IN_TR_GROUP10_OUTPUT2 = 0x0002u, /* tr_group[10].output[2] */ + TRIG0_IN_TR_GROUP10_OUTPUT3 = 0x0003u, /* tr_group[10].output[3] */ + TRIG0_IN_TR_GROUP10_OUTPUT4 = 0x0004u, /* tr_group[10].output[4] */ + TRIG0_IN_TR_GROUP10_OUTPUT5 = 0x0005u, /* tr_group[10].output[5] */ + TRIG0_IN_TR_GROUP10_OUTPUT6 = 0x0006u, /* tr_group[10].output[6] */ + TRIG0_IN_TR_GROUP10_OUTPUT7 = 0x0007u, /* tr_group[10].output[7] */ + TRIG0_IN_TR_GROUP11_OUTPUT0 = 0x0008u, /* tr_group[11].output[0] */ + TRIG0_IN_TR_GROUP11_OUTPUT1 = 0x0009u, /* tr_group[11].output[1] */ + TRIG0_IN_TR_GROUP11_OUTPUT2 = 0x000Au, /* tr_group[11].output[2] */ + TRIG0_IN_TR_GROUP11_OUTPUT3 = 0x000Bu, /* tr_group[11].output[3] */ + TRIG0_IN_TR_GROUP11_OUTPUT4 = 0x000Cu, /* tr_group[11].output[4] */ + TRIG0_IN_TR_GROUP11_OUTPUT5 = 0x000Du, /* tr_group[11].output[5] */ + TRIG0_IN_TR_GROUP11_OUTPUT6 = 0x000Eu, /* tr_group[11].output[6] */ + TRIG0_IN_TR_GROUP11_OUTPUT7 = 0x000Fu, /* tr_group[11].output[7] */ + TRIG0_IN_TR_GROUP11_OUTPUT8 = 0x0010u, /* tr_group[11].output[8] */ + TRIG0_IN_TR_GROUP11_OUTPUT9 = 0x0011u, /* tr_group[11].output[9] */ + TRIG0_IN_TR_GROUP11_OUTPUT10 = 0x0012u, /* tr_group[11].output[10] */ + TRIG0_IN_TR_GROUP11_OUTPUT11 = 0x0013u, /* tr_group[11].output[11] */ + TRIG0_IN_TR_GROUP11_OUTPUT12 = 0x0014u, /* tr_group[11].output[12] */ + TRIG0_IN_TR_GROUP11_OUTPUT13 = 0x0015u, /* tr_group[11].output[13] */ + TRIG0_IN_TR_GROUP11_OUTPUT14 = 0x0016u, /* tr_group[11].output[14] */ + TRIG0_IN_TR_GROUP11_OUTPUT15 = 0x0017u, /* tr_group[11].output[15] */ + TRIG0_IN_TR_GROUP12_OUTPUT8 = 0x0018u, /* tr_group[12].output[8] */ + TRIG0_IN_TR_GROUP12_OUTPUT9 = 0x0019u, /* tr_group[12].output[9] */ + TRIG0_IN_TR_GROUP13_OUTPUT0 = 0x001Au, /* tr_group[13].output[0] */ + TRIG0_IN_TR_GROUP13_OUTPUT1 = 0x001Bu, /* tr_group[13].output[1] */ + TRIG0_IN_TR_GROUP13_OUTPUT2 = 0x001Cu, /* tr_group[13].output[2] */ + TRIG0_IN_TR_GROUP13_OUTPUT3 = 0x001Du, /* tr_group[13].output[3] */ + TRIG0_IN_TR_GROUP13_OUTPUT4 = 0x001Eu, /* tr_group[13].output[4] */ + TRIG0_IN_TR_GROUP13_OUTPUT5 = 0x001Fu, /* tr_group[13].output[5] */ + TRIG0_IN_TR_GROUP13_OUTPUT6 = 0x0020u, /* tr_group[13].output[6] */ + TRIG0_IN_TR_GROUP13_OUTPUT7 = 0x0021u, /* tr_group[13].output[7] */ + TRIG0_IN_TR_GROUP13_OUTPUT8 = 0x0022u, /* tr_group[13].output[8] */ + TRIG0_IN_TR_GROUP13_OUTPUT9 = 0x0023u, /* tr_group[13].output[9] */ + TRIG0_IN_TR_GROUP13_OUTPUT10 = 0x0024u, /* tr_group[13].output[10] */ + TRIG0_IN_TR_GROUP13_OUTPUT11 = 0x0025u, /* tr_group[13].output[11] */ + TRIG0_IN_TR_GROUP13_OUTPUT12 = 0x0026u, /* tr_group[13].output[12] */ + TRIG0_IN_TR_GROUP13_OUTPUT13 = 0x0027u, /* tr_group[13].output[13] */ + TRIG0_IN_TR_GROUP13_OUTPUT14 = 0x0028u, /* tr_group[13].output[14] */ + TRIG0_IN_TR_GROUP13_OUTPUT15 = 0x0029u, /* tr_group[13].output[15] */ + TRIG0_IN_TR_GROUP14_OUTPUT0 = 0x002Au, /* tr_group[14].output[0] */ + TRIG0_IN_TR_GROUP14_OUTPUT1 = 0x002Bu, /* tr_group[14].output[1] */ + TRIG0_IN_TR_GROUP14_OUTPUT2 = 0x002Cu, /* tr_group[14].output[2] */ + TRIG0_IN_TR_GROUP14_OUTPUT3 = 0x002Du, /* tr_group[14].output[3] */ + TRIG0_IN_TR_GROUP14_OUTPUT4 = 0x002Eu, /* tr_group[14].output[4] */ + TRIG0_IN_TR_GROUP14_OUTPUT5 = 0x002Fu, /* tr_group[14].output[5] */ + TRIG0_IN_TR_GROUP14_OUTPUT6 = 0x0030u, /* tr_group[14].output[6] */ + TRIG0_IN_TR_GROUP14_OUTPUT7 = 0x0031u /* tr_group[14].output[7] */ +} en_trig_input_grp0_t; + +/* Trigger Input Group 1 - DMA Request Assignments */ +typedef enum +{ + TRIG1_IN_TR_GROUP10_OUTPUT0 = 0x0100u, /* tr_group[10].output[0] */ + TRIG1_IN_TR_GROUP10_OUTPUT1 = 0x0101u, /* tr_group[10].output[1] */ + TRIG1_IN_TR_GROUP10_OUTPUT2 = 0x0102u, /* tr_group[10].output[2] */ + TRIG1_IN_TR_GROUP10_OUTPUT3 = 0x0103u, /* tr_group[10].output[3] */ + TRIG1_IN_TR_GROUP10_OUTPUT4 = 0x0104u, /* tr_group[10].output[4] */ + TRIG1_IN_TR_GROUP10_OUTPUT5 = 0x0105u, /* tr_group[10].output[5] */ + TRIG1_IN_TR_GROUP10_OUTPUT6 = 0x0106u, /* tr_group[10].output[6] */ + TRIG1_IN_TR_GROUP10_OUTPUT7 = 0x0107u, /* tr_group[10].output[7] */ + TRIG1_IN_TR_GROUP11_OUTPUT0 = 0x0108u, /* tr_group[11].output[0] */ + TRIG1_IN_TR_GROUP11_OUTPUT1 = 0x0109u, /* tr_group[11].output[1] */ + TRIG1_IN_TR_GROUP11_OUTPUT2 = 0x010Au, /* tr_group[11].output[2] */ + TRIG1_IN_TR_GROUP11_OUTPUT3 = 0x010Bu, /* tr_group[11].output[3] */ + TRIG1_IN_TR_GROUP11_OUTPUT4 = 0x010Cu, /* tr_group[11].output[4] */ + TRIG1_IN_TR_GROUP11_OUTPUT5 = 0x010Du, /* tr_group[11].output[5] */ + TRIG1_IN_TR_GROUP11_OUTPUT6 = 0x010Eu, /* tr_group[11].output[6] */ + TRIG1_IN_TR_GROUP11_OUTPUT7 = 0x010Fu, /* tr_group[11].output[7] */ + TRIG1_IN_TR_GROUP11_OUTPUT8 = 0x0110u, /* tr_group[11].output[8] */ + TRIG1_IN_TR_GROUP11_OUTPUT9 = 0x0111u, /* tr_group[11].output[9] */ + TRIG1_IN_TR_GROUP11_OUTPUT10 = 0x0112u, /* tr_group[11].output[10] */ + TRIG1_IN_TR_GROUP11_OUTPUT11 = 0x0113u, /* tr_group[11].output[11] */ + TRIG1_IN_TR_GROUP11_OUTPUT12 = 0x0114u, /* tr_group[11].output[12] */ + TRIG1_IN_TR_GROUP11_OUTPUT13 = 0x0115u, /* tr_group[11].output[13] */ + TRIG1_IN_TR_GROUP11_OUTPUT14 = 0x0116u, /* tr_group[11].output[14] */ + TRIG1_IN_TR_GROUP11_OUTPUT15 = 0x0117u, /* tr_group[11].output[15] */ + TRIG1_IN_TR_GROUP12_OUTPUT8 = 0x0118u, /* tr_group[12].output[8] */ + TRIG1_IN_TR_GROUP12_OUTPUT9 = 0x0119u, /* tr_group[12].output[9] */ + TRIG1_IN_TR_GROUP13_OUTPUT0 = 0x011Au, /* tr_group[13].output[0] */ + TRIG1_IN_TR_GROUP13_OUTPUT1 = 0x011Bu, /* tr_group[13].output[1] */ + TRIG1_IN_TR_GROUP13_OUTPUT2 = 0x011Cu, /* tr_group[13].output[2] */ + TRIG1_IN_TR_GROUP13_OUTPUT3 = 0x011Du, /* tr_group[13].output[3] */ + TRIG1_IN_TR_GROUP13_OUTPUT4 = 0x011Eu, /* tr_group[13].output[4] */ + TRIG1_IN_TR_GROUP13_OUTPUT5 = 0x011Fu, /* tr_group[13].output[5] */ + TRIG1_IN_TR_GROUP13_OUTPUT6 = 0x0120u, /* tr_group[13].output[6] */ + TRIG1_IN_TR_GROUP13_OUTPUT7 = 0x0121u, /* tr_group[13].output[7] */ + TRIG1_IN_TR_GROUP13_OUTPUT8 = 0x0122u, /* tr_group[13].output[8] */ + TRIG1_IN_TR_GROUP13_OUTPUT9 = 0x0123u, /* tr_group[13].output[9] */ + TRIG1_IN_TR_GROUP13_OUTPUT10 = 0x0124u, /* tr_group[13].output[10] */ + TRIG1_IN_TR_GROUP13_OUTPUT11 = 0x0125u, /* tr_group[13].output[11] */ + TRIG1_IN_TR_GROUP13_OUTPUT12 = 0x0126u, /* tr_group[13].output[12] */ + TRIG1_IN_TR_GROUP13_OUTPUT13 = 0x0127u, /* tr_group[13].output[13] */ + TRIG1_IN_TR_GROUP13_OUTPUT14 = 0x0128u, /* tr_group[13].output[14] */ + TRIG1_IN_TR_GROUP13_OUTPUT15 = 0x0129u, /* tr_group[13].output[15] */ + TRIG1_IN_TR_GROUP14_OUTPUT0 = 0x012Au, /* tr_group[14].output[0] */ + TRIG1_IN_TR_GROUP14_OUTPUT1 = 0x012Bu, /* tr_group[14].output[1] */ + TRIG1_IN_TR_GROUP14_OUTPUT2 = 0x012Cu, /* tr_group[14].output[2] */ + TRIG1_IN_TR_GROUP14_OUTPUT3 = 0x012Du, /* tr_group[14].output[3] */ + TRIG1_IN_TR_GROUP14_OUTPUT4 = 0x012Eu, /* tr_group[14].output[4] */ + TRIG1_IN_TR_GROUP14_OUTPUT5 = 0x012Fu, /* tr_group[14].output[5] */ + TRIG1_IN_TR_GROUP14_OUTPUT6 = 0x0130u, /* tr_group[14].output[6] */ + TRIG1_IN_TR_GROUP14_OUTPUT7 = 0x0131u /* tr_group[14].output[7] */ +} en_trig_input_grp1_t; + +/* Trigger Input Group 2 - TCPWM trigger inputs */ +typedef enum +{ + TRIG2_IN_TR_GROUP10_OUTPUT0 = 0x0200u, /* tr_group[10].output[0] */ + TRIG2_IN_TR_GROUP10_OUTPUT1 = 0x0201u, /* tr_group[10].output[1] */ + TRIG2_IN_TR_GROUP10_OUTPUT2 = 0x0202u, /* tr_group[10].output[2] */ + TRIG2_IN_TR_GROUP10_OUTPUT3 = 0x0203u, /* tr_group[10].output[3] */ + TRIG2_IN_TR_GROUP10_OUTPUT4 = 0x0204u, /* tr_group[10].output[4] */ + TRIG2_IN_TR_GROUP10_OUTPUT5 = 0x0205u, /* tr_group[10].output[5] */ + TRIG2_IN_TR_GROUP10_OUTPUT6 = 0x0206u, /* tr_group[10].output[6] */ + TRIG2_IN_TR_GROUP10_OUTPUT7 = 0x0207u, /* tr_group[10].output[7] */ + TRIG2_IN_TR_GROUP11_OUTPUT0 = 0x0208u, /* tr_group[11].output[0] */ + TRIG2_IN_TR_GROUP11_OUTPUT1 = 0x0209u, /* tr_group[11].output[1] */ + TRIG2_IN_TR_GROUP11_OUTPUT2 = 0x020Au, /* tr_group[11].output[2] */ + TRIG2_IN_TR_GROUP11_OUTPUT3 = 0x020Bu, /* tr_group[11].output[3] */ + TRIG2_IN_TR_GROUP11_OUTPUT4 = 0x020Cu, /* tr_group[11].output[4] */ + TRIG2_IN_TR_GROUP11_OUTPUT5 = 0x020Du, /* tr_group[11].output[5] */ + TRIG2_IN_TR_GROUP11_OUTPUT6 = 0x020Eu, /* tr_group[11].output[6] */ + TRIG2_IN_TR_GROUP11_OUTPUT7 = 0x020Fu, /* tr_group[11].output[7] */ + TRIG2_IN_TR_GROUP11_OUTPUT8 = 0x0210u, /* tr_group[11].output[8] */ + TRIG2_IN_TR_GROUP11_OUTPUT9 = 0x0211u, /* tr_group[11].output[9] */ + TRIG2_IN_TR_GROUP11_OUTPUT10 = 0x0212u, /* tr_group[11].output[10] */ + TRIG2_IN_TR_GROUP11_OUTPUT11 = 0x0213u, /* tr_group[11].output[11] */ + TRIG2_IN_TR_GROUP11_OUTPUT12 = 0x0214u, /* tr_group[11].output[12] */ + TRIG2_IN_TR_GROUP11_OUTPUT13 = 0x0215u, /* tr_group[11].output[13] */ + TRIG2_IN_TR_GROUP11_OUTPUT14 = 0x0216u, /* tr_group[11].output[14] */ + TRIG2_IN_TR_GROUP11_OUTPUT15 = 0x0217u, /* tr_group[11].output[15] */ + TRIG2_IN_TR_GROUP12_OUTPUT0 = 0x0218u, /* tr_group[12].output[0] */ + TRIG2_IN_TR_GROUP12_OUTPUT1 = 0x0219u, /* tr_group[12].output[1] */ + TRIG2_IN_TR_GROUP12_OUTPUT2 = 0x021Au, /* tr_group[12].output[2] */ + TRIG2_IN_TR_GROUP12_OUTPUT3 = 0x021Bu, /* tr_group[12].output[3] */ + TRIG2_IN_TR_GROUP12_OUTPUT4 = 0x021Cu, /* tr_group[12].output[4] */ + TRIG2_IN_TR_GROUP12_OUTPUT5 = 0x021Du, /* tr_group[12].output[5] */ + TRIG2_IN_TR_GROUP12_OUTPUT6 = 0x021Eu, /* tr_group[12].output[6] */ + TRIG2_IN_TR_GROUP12_OUTPUT7 = 0x021Fu, /* tr_group[12].output[7] */ + TRIG2_IN_TR_GROUP13_OUTPUT16 = 0x0220u, /* tr_group[13].output[16] */ + TRIG2_IN_TR_GROUP13_OUTPUT17 = 0x0221u, /* tr_group[13].output[17] */ + TRIG2_IN_TR_GROUP14_OUTPUT8 = 0x0222u, /* tr_group[14].output[8] */ + TRIG2_IN_TR_GROUP14_OUTPUT9 = 0x0223u, /* tr_group[14].output[9] */ + TRIG2_IN_TR_GROUP14_OUTPUT10 = 0x0224u, /* tr_group[14].output[10] */ + TRIG2_IN_TR_GROUP14_OUTPUT11 = 0x0225u, /* tr_group[14].output[11] */ + TRIG2_IN_TR_GROUP14_OUTPUT12 = 0x0226u, /* tr_group[14].output[12] */ + TRIG2_IN_TR_GROUP14_OUTPUT13 = 0x0227u, /* tr_group[14].output[13] */ + TRIG2_IN_TR_GROUP14_OUTPUT14 = 0x0228u, /* tr_group[14].output[14] */ + TRIG2_IN_TR_GROUP14_OUTPUT15 = 0x0229u /* tr_group[14].output[15] */ +} en_trig_input_grp2_t; + +/* Trigger Input Group 3 - TCPWM trigger inputs */ +typedef enum +{ + TRIG3_IN_TR_GROUP10_OUTPUT0 = 0x0300u, /* tr_group[10].output[0] */ + TRIG3_IN_TR_GROUP10_OUTPUT1 = 0x0301u, /* tr_group[10].output[1] */ + TRIG3_IN_TR_GROUP10_OUTPUT2 = 0x0302u, /* tr_group[10].output[2] */ + TRIG3_IN_TR_GROUP10_OUTPUT3 = 0x0303u, /* tr_group[10].output[3] */ + TRIG3_IN_TR_GROUP10_OUTPUT4 = 0x0304u, /* tr_group[10].output[4] */ + TRIG3_IN_TR_GROUP10_OUTPUT5 = 0x0305u, /* tr_group[10].output[5] */ + TRIG3_IN_TR_GROUP10_OUTPUT6 = 0x0306u, /* tr_group[10].output[6] */ + TRIG3_IN_TR_GROUP10_OUTPUT7 = 0x0307u, /* tr_group[10].output[7] */ + TRIG3_IN_TR_GROUP11_OUTPUT0 = 0x0308u, /* tr_group[11].output[0] */ + TRIG3_IN_TR_GROUP11_OUTPUT1 = 0x0309u, /* tr_group[11].output[1] */ + TRIG3_IN_TR_GROUP11_OUTPUT2 = 0x030Au, /* tr_group[11].output[2] */ + TRIG3_IN_TR_GROUP11_OUTPUT3 = 0x030Bu, /* tr_group[11].output[3] */ + TRIG3_IN_TR_GROUP11_OUTPUT4 = 0x030Cu, /* tr_group[11].output[4] */ + TRIG3_IN_TR_GROUP11_OUTPUT5 = 0x030Du, /* tr_group[11].output[5] */ + TRIG3_IN_TR_GROUP11_OUTPUT6 = 0x030Eu, /* tr_group[11].output[6] */ + TRIG3_IN_TR_GROUP11_OUTPUT7 = 0x030Fu, /* tr_group[11].output[7] */ + TRIG3_IN_TR_GROUP11_OUTPUT8 = 0x0310u, /* tr_group[11].output[8] */ + TRIG3_IN_TR_GROUP11_OUTPUT9 = 0x0311u, /* tr_group[11].output[9] */ + TRIG3_IN_TR_GROUP11_OUTPUT10 = 0x0312u, /* tr_group[11].output[10] */ + TRIG3_IN_TR_GROUP11_OUTPUT11 = 0x0313u, /* tr_group[11].output[11] */ + TRIG3_IN_TR_GROUP11_OUTPUT12 = 0x0314u, /* tr_group[11].output[12] */ + TRIG3_IN_TR_GROUP11_OUTPUT13 = 0x0315u, /* tr_group[11].output[13] */ + TRIG3_IN_TR_GROUP11_OUTPUT14 = 0x0316u, /* tr_group[11].output[14] */ + TRIG3_IN_TR_GROUP11_OUTPUT15 = 0x0317u, /* tr_group[11].output[15] */ + TRIG3_IN_TR_GROUP12_OUTPUT0 = 0x0318u, /* tr_group[12].output[0] */ + TRIG3_IN_TR_GROUP12_OUTPUT1 = 0x0319u, /* tr_group[12].output[1] */ + TRIG3_IN_TR_GROUP12_OUTPUT2 = 0x031Au, /* tr_group[12].output[2] */ + TRIG3_IN_TR_GROUP12_OUTPUT3 = 0x031Bu, /* tr_group[12].output[3] */ + TRIG3_IN_TR_GROUP12_OUTPUT4 = 0x031Cu, /* tr_group[12].output[4] */ + TRIG3_IN_TR_GROUP12_OUTPUT5 = 0x031Du, /* tr_group[12].output[5] */ + TRIG3_IN_TR_GROUP12_OUTPUT6 = 0x031Eu, /* tr_group[12].output[6] */ + TRIG3_IN_TR_GROUP12_OUTPUT7 = 0x031Fu, /* tr_group[12].output[7] */ + TRIG3_IN_TR_GROUP13_OUTPUT16 = 0x0320u, /* tr_group[13].output[16] */ + TRIG3_IN_TR_GROUP13_OUTPUT17 = 0x0321u, /* tr_group[13].output[17] */ + TRIG3_IN_TR_GROUP14_OUTPUT8 = 0x0322u, /* tr_group[14].output[8] */ + TRIG3_IN_TR_GROUP14_OUTPUT9 = 0x0323u, /* tr_group[14].output[9] */ + TRIG3_IN_TR_GROUP14_OUTPUT10 = 0x0324u, /* tr_group[14].output[10] */ + TRIG3_IN_TR_GROUP14_OUTPUT11 = 0x0325u, /* tr_group[14].output[11] */ + TRIG3_IN_TR_GROUP14_OUTPUT12 = 0x0326u, /* tr_group[14].output[12] */ + TRIG3_IN_TR_GROUP14_OUTPUT13 = 0x0327u, /* tr_group[14].output[13] */ + TRIG3_IN_TR_GROUP14_OUTPUT14 = 0x0328u, /* tr_group[14].output[14] */ + TRIG3_IN_TR_GROUP14_OUTPUT15 = 0x0329u /* tr_group[14].output[15] */ +} en_trig_input_grp3_t; + +/* Trigger Input Group 4 - PROFILE trigger multiplexer */ +typedef enum +{ + TRIG4_IN_TR_GROUP10_OUTPUT0 = 0x0400u, /* tr_group[10].output[0] */ + TRIG4_IN_TR_GROUP10_OUTPUT1 = 0x0401u, /* tr_group[10].output[1] */ + TRIG4_IN_TR_GROUP10_OUTPUT2 = 0x0402u, /* tr_group[10].output[2] */ + TRIG4_IN_TR_GROUP10_OUTPUT3 = 0x0403u, /* tr_group[10].output[3] */ + TRIG4_IN_TR_GROUP10_OUTPUT4 = 0x0404u, /* tr_group[10].output[4] */ + TRIG4_IN_TR_GROUP10_OUTPUT5 = 0x0405u, /* tr_group[10].output[5] */ + TRIG4_IN_TR_GROUP10_OUTPUT6 = 0x0406u, /* tr_group[10].output[6] */ + TRIG4_IN_TR_GROUP10_OUTPUT7 = 0x0407u, /* tr_group[10].output[7] */ + TRIG4_IN_TR_GROUP11_OUTPUT0 = 0x0408u, /* tr_group[11].output[0] */ + TRIG4_IN_TR_GROUP11_OUTPUT1 = 0x0409u, /* tr_group[11].output[1] */ + TRIG4_IN_TR_GROUP11_OUTPUT2 = 0x040Au, /* tr_group[11].output[2] */ + TRIG4_IN_TR_GROUP11_OUTPUT3 = 0x040Bu, /* tr_group[11].output[3] */ + TRIG4_IN_TR_GROUP11_OUTPUT4 = 0x040Cu, /* tr_group[11].output[4] */ + TRIG4_IN_TR_GROUP11_OUTPUT5 = 0x040Du, /* tr_group[11].output[5] */ + TRIG4_IN_TR_GROUP11_OUTPUT6 = 0x040Eu, /* tr_group[11].output[6] */ + TRIG4_IN_TR_GROUP11_OUTPUT7 = 0x040Fu, /* tr_group[11].output[7] */ + TRIG4_IN_TR_GROUP11_OUTPUT8 = 0x0410u, /* tr_group[11].output[8] */ + TRIG4_IN_TR_GROUP11_OUTPUT9 = 0x0411u, /* tr_group[11].output[9] */ + TRIG4_IN_TR_GROUP11_OUTPUT10 = 0x0412u, /* tr_group[11].output[10] */ + TRIG4_IN_TR_GROUP11_OUTPUT11 = 0x0413u, /* tr_group[11].output[11] */ + TRIG4_IN_TR_GROUP11_OUTPUT12 = 0x0414u, /* tr_group[11].output[12] */ + TRIG4_IN_TR_GROUP11_OUTPUT13 = 0x0415u, /* tr_group[11].output[13] */ + TRIG4_IN_TR_GROUP11_OUTPUT14 = 0x0416u, /* tr_group[11].output[14] */ + TRIG4_IN_TR_GROUP11_OUTPUT15 = 0x0417u, /* tr_group[11].output[15] */ + TRIG4_IN_TR_GROUP12_OUTPUT0 = 0x0418u, /* tr_group[12].output[0] */ + TRIG4_IN_TR_GROUP12_OUTPUT1 = 0x0419u, /* tr_group[12].output[1] */ + TRIG4_IN_TR_GROUP12_OUTPUT2 = 0x041Au, /* tr_group[12].output[2] */ + TRIG4_IN_TR_GROUP12_OUTPUT3 = 0x041Bu, /* tr_group[12].output[3] */ + TRIG4_IN_TR_GROUP12_OUTPUT4 = 0x041Cu, /* tr_group[12].output[4] */ + TRIG4_IN_TR_GROUP12_OUTPUT5 = 0x041Du, /* tr_group[12].output[5] */ + TRIG4_IN_TR_GROUP12_OUTPUT6 = 0x041Eu, /* tr_group[12].output[6] */ + TRIG4_IN_TR_GROUP12_OUTPUT7 = 0x041Fu, /* tr_group[12].output[7] */ + TRIG4_IN_TR_GROUP13_OUTPUT16 = 0x0420u, /* tr_group[13].output[16] */ + TRIG4_IN_TR_GROUP13_OUTPUT17 = 0x0421u, /* tr_group[13].output[17] */ + TRIG4_IN_TR_GROUP14_OUTPUT8 = 0x0422u, /* tr_group[14].output[8] */ + TRIG4_IN_TR_GROUP14_OUTPUT9 = 0x0423u, /* tr_group[14].output[9] */ + TRIG4_IN_TR_GROUP14_OUTPUT10 = 0x0424u, /* tr_group[14].output[10] */ + TRIG4_IN_TR_GROUP14_OUTPUT11 = 0x0425u, /* tr_group[14].output[11] */ + TRIG4_IN_TR_GROUP14_OUTPUT12 = 0x0426u, /* tr_group[14].output[12] */ + TRIG4_IN_TR_GROUP14_OUTPUT13 = 0x0427u, /* tr_group[14].output[13] */ + TRIG4_IN_TR_GROUP14_OUTPUT14 = 0x0428u, /* tr_group[14].output[14] */ + TRIG4_IN_TR_GROUP14_OUTPUT15 = 0x0429u /* tr_group[14].output[15] */ +} en_trig_input_grp4_t; + +/* Trigger Input Group 5 - CPUSS.CTI trigger multiplexer */ +typedef enum +{ + TRIG5_IN_TR_GROUP10_OUTPUT0 = 0x0500u, /* tr_group[10].output[0] */ + TRIG5_IN_TR_GROUP10_OUTPUT1 = 0x0501u, /* tr_group[10].output[1] */ + TRIG5_IN_TR_GROUP10_OUTPUT2 = 0x0502u, /* tr_group[10].output[2] */ + TRIG5_IN_TR_GROUP10_OUTPUT3 = 0x0503u, /* tr_group[10].output[3] */ + TRIG5_IN_TR_GROUP10_OUTPUT4 = 0x0504u, /* tr_group[10].output[4] */ + TRIG5_IN_TR_GROUP10_OUTPUT5 = 0x0505u, /* tr_group[10].output[5] */ + TRIG5_IN_TR_GROUP10_OUTPUT6 = 0x0506u, /* tr_group[10].output[6] */ + TRIG5_IN_TR_GROUP10_OUTPUT7 = 0x0507u, /* tr_group[10].output[7] */ + TRIG5_IN_TR_GROUP11_OUTPUT0 = 0x0508u, /* tr_group[11].output[0] */ + TRIG5_IN_TR_GROUP11_OUTPUT1 = 0x0509u, /* tr_group[11].output[1] */ + TRIG5_IN_TR_GROUP11_OUTPUT2 = 0x050Au, /* tr_group[11].output[2] */ + TRIG5_IN_TR_GROUP11_OUTPUT3 = 0x050Bu, /* tr_group[11].output[3] */ + TRIG5_IN_TR_GROUP11_OUTPUT4 = 0x050Cu, /* tr_group[11].output[4] */ + TRIG5_IN_TR_GROUP11_OUTPUT5 = 0x050Du, /* tr_group[11].output[5] */ + TRIG5_IN_TR_GROUP11_OUTPUT6 = 0x050Eu, /* tr_group[11].output[6] */ + TRIG5_IN_TR_GROUP11_OUTPUT7 = 0x050Fu, /* tr_group[11].output[7] */ + TRIG5_IN_TR_GROUP11_OUTPUT8 = 0x0510u, /* tr_group[11].output[8] */ + TRIG5_IN_TR_GROUP11_OUTPUT9 = 0x0511u, /* tr_group[11].output[9] */ + TRIG5_IN_TR_GROUP11_OUTPUT10 = 0x0512u, /* tr_group[11].output[10] */ + TRIG5_IN_TR_GROUP11_OUTPUT11 = 0x0513u, /* tr_group[11].output[11] */ + TRIG5_IN_TR_GROUP11_OUTPUT12 = 0x0514u, /* tr_group[11].output[12] */ + TRIG5_IN_TR_GROUP11_OUTPUT13 = 0x0515u, /* tr_group[11].output[13] */ + TRIG5_IN_TR_GROUP11_OUTPUT14 = 0x0516u, /* tr_group[11].output[14] */ + TRIG5_IN_TR_GROUP11_OUTPUT15 = 0x0517u, /* tr_group[11].output[15] */ + TRIG5_IN_TR_GROUP12_OUTPUT0 = 0x0518u, /* tr_group[12].output[0] */ + TRIG5_IN_TR_GROUP12_OUTPUT1 = 0x0519u, /* tr_group[12].output[1] */ + TRIG5_IN_TR_GROUP12_OUTPUT2 = 0x051Au, /* tr_group[12].output[2] */ + TRIG5_IN_TR_GROUP12_OUTPUT3 = 0x051Bu, /* tr_group[12].output[3] */ + TRIG5_IN_TR_GROUP12_OUTPUT4 = 0x051Cu, /* tr_group[12].output[4] */ + TRIG5_IN_TR_GROUP12_OUTPUT5 = 0x051Du, /* tr_group[12].output[5] */ + TRIG5_IN_TR_GROUP12_OUTPUT6 = 0x051Eu, /* tr_group[12].output[6] */ + TRIG5_IN_TR_GROUP12_OUTPUT7 = 0x051Fu, /* tr_group[12].output[7] */ + TRIG5_IN_TR_GROUP13_OUTPUT16 = 0x0520u, /* tr_group[13].output[16] */ + TRIG5_IN_TR_GROUP13_OUTPUT17 = 0x0521u, /* tr_group[13].output[17] */ + TRIG5_IN_TR_GROUP14_OUTPUT8 = 0x0522u, /* tr_group[14].output[8] */ + TRIG5_IN_TR_GROUP14_OUTPUT9 = 0x0523u, /* tr_group[14].output[9] */ + TRIG5_IN_TR_GROUP14_OUTPUT10 = 0x0524u, /* tr_group[14].output[10] */ + TRIG5_IN_TR_GROUP14_OUTPUT11 = 0x0525u, /* tr_group[14].output[11] */ + TRIG5_IN_TR_GROUP14_OUTPUT12 = 0x0526u, /* tr_group[14].output[12] */ + TRIG5_IN_TR_GROUP14_OUTPUT13 = 0x0527u, /* tr_group[14].output[13] */ + TRIG5_IN_TR_GROUP14_OUTPUT14 = 0x0528u, /* tr_group[14].output[14] */ + TRIG5_IN_TR_GROUP14_OUTPUT15 = 0x0529u /* tr_group[14].output[15] */ +} en_trig_input_grp5_t; + +/* Trigger Input Group 6 - PASS trigger multiplexer */ +typedef enum +{ + TRIG6_IN_TR_GROUP10_OUTPUT0 = 0x0600u, /* tr_group[10].output[0] */ + TRIG6_IN_TR_GROUP10_OUTPUT1 = 0x0601u, /* tr_group[10].output[1] */ + TRIG6_IN_TR_GROUP10_OUTPUT2 = 0x0602u, /* tr_group[10].output[2] */ + TRIG6_IN_TR_GROUP10_OUTPUT3 = 0x0603u, /* tr_group[10].output[3] */ + TRIG6_IN_TR_GROUP10_OUTPUT4 = 0x0604u, /* tr_group[10].output[4] */ + TRIG6_IN_TR_GROUP10_OUTPUT5 = 0x0605u, /* tr_group[10].output[5] */ + TRIG6_IN_TR_GROUP10_OUTPUT6 = 0x0606u, /* tr_group[10].output[6] */ + TRIG6_IN_TR_GROUP10_OUTPUT7 = 0x0607u, /* tr_group[10].output[7] */ + TRIG6_IN_TR_GROUP11_OUTPUT0 = 0x0608u, /* tr_group[11].output[0] */ + TRIG6_IN_TR_GROUP11_OUTPUT1 = 0x0609u, /* tr_group[11].output[1] */ + TRIG6_IN_TR_GROUP11_OUTPUT2 = 0x060Au, /* tr_group[11].output[2] */ + TRIG6_IN_TR_GROUP11_OUTPUT3 = 0x060Bu, /* tr_group[11].output[3] */ + TRIG6_IN_TR_GROUP11_OUTPUT4 = 0x060Cu, /* tr_group[11].output[4] */ + TRIG6_IN_TR_GROUP11_OUTPUT5 = 0x060Du, /* tr_group[11].output[5] */ + TRIG6_IN_TR_GROUP11_OUTPUT6 = 0x060Eu, /* tr_group[11].output[6] */ + TRIG6_IN_TR_GROUP11_OUTPUT7 = 0x060Fu, /* tr_group[11].output[7] */ + TRIG6_IN_TR_GROUP11_OUTPUT8 = 0x0610u, /* tr_group[11].output[8] */ + TRIG6_IN_TR_GROUP11_OUTPUT9 = 0x0611u, /* tr_group[11].output[9] */ + TRIG6_IN_TR_GROUP11_OUTPUT10 = 0x0612u, /* tr_group[11].output[10] */ + TRIG6_IN_TR_GROUP11_OUTPUT11 = 0x0613u, /* tr_group[11].output[11] */ + TRIG6_IN_TR_GROUP11_OUTPUT12 = 0x0614u, /* tr_group[11].output[12] */ + TRIG6_IN_TR_GROUP11_OUTPUT13 = 0x0615u, /* tr_group[11].output[13] */ + TRIG6_IN_TR_GROUP11_OUTPUT14 = 0x0616u, /* tr_group[11].output[14] */ + TRIG6_IN_TR_GROUP11_OUTPUT15 = 0x0617u, /* tr_group[11].output[15] */ + TRIG6_IN_TR_GROUP12_OUTPUT0 = 0x0618u, /* tr_group[12].output[0] */ + TRIG6_IN_TR_GROUP12_OUTPUT1 = 0x0619u, /* tr_group[12].output[1] */ + TRIG6_IN_TR_GROUP12_OUTPUT2 = 0x061Au, /* tr_group[12].output[2] */ + TRIG6_IN_TR_GROUP12_OUTPUT3 = 0x061Bu, /* tr_group[12].output[3] */ + TRIG6_IN_TR_GROUP12_OUTPUT4 = 0x061Cu, /* tr_group[12].output[4] */ + TRIG6_IN_TR_GROUP12_OUTPUT5 = 0x061Du, /* tr_group[12].output[5] */ + TRIG6_IN_TR_GROUP12_OUTPUT6 = 0x061Eu, /* tr_group[12].output[6] */ + TRIG6_IN_TR_GROUP12_OUTPUT7 = 0x061Fu, /* tr_group[12].output[7] */ + TRIG6_IN_TR_GROUP13_OUTPUT16 = 0x0620u, /* tr_group[13].output[16] */ + TRIG6_IN_TR_GROUP13_OUTPUT17 = 0x0621u, /* tr_group[13].output[17] */ + TRIG6_IN_TR_GROUP14_OUTPUT8 = 0x0622u, /* tr_group[14].output[8] */ + TRIG6_IN_TR_GROUP14_OUTPUT9 = 0x0623u, /* tr_group[14].output[9] */ + TRIG6_IN_TR_GROUP14_OUTPUT10 = 0x0624u, /* tr_group[14].output[10] */ + TRIG6_IN_TR_GROUP14_OUTPUT11 = 0x0625u, /* tr_group[14].output[11] */ + TRIG6_IN_TR_GROUP14_OUTPUT12 = 0x0626u, /* tr_group[14].output[12] */ + TRIG6_IN_TR_GROUP14_OUTPUT13 = 0x0627u, /* tr_group[14].output[13] */ + TRIG6_IN_TR_GROUP14_OUTPUT14 = 0x0628u, /* tr_group[14].output[14] */ + TRIG6_IN_TR_GROUP14_OUTPUT15 = 0x0629u /* tr_group[14].output[15] */ +} en_trig_input_grp6_t; + +/* Trigger Input Group 7 - UDB general purpose trigger multiplexer */ +typedef enum +{ + TRIG7_IN_TR_GROUP10_OUTPUT0 = 0x0700u, /* tr_group[10].output[0] */ + TRIG7_IN_TR_GROUP10_OUTPUT1 = 0x0701u, /* tr_group[10].output[1] */ + TRIG7_IN_TR_GROUP10_OUTPUT2 = 0x0702u, /* tr_group[10].output[2] */ + TRIG7_IN_TR_GROUP10_OUTPUT3 = 0x0703u, /* tr_group[10].output[3] */ + TRIG7_IN_TR_GROUP10_OUTPUT4 = 0x0704u, /* tr_group[10].output[4] */ + TRIG7_IN_TR_GROUP10_OUTPUT5 = 0x0705u, /* tr_group[10].output[5] */ + TRIG7_IN_TR_GROUP10_OUTPUT6 = 0x0706u, /* tr_group[10].output[6] */ + TRIG7_IN_TR_GROUP10_OUTPUT7 = 0x0707u, /* tr_group[10].output[7] */ + TRIG7_IN_TR_GROUP11_OUTPUT0 = 0x0708u, /* tr_group[11].output[0] */ + TRIG7_IN_TR_GROUP11_OUTPUT1 = 0x0709u, /* tr_group[11].output[1] */ + TRIG7_IN_TR_GROUP11_OUTPUT2 = 0x070Au, /* tr_group[11].output[2] */ + TRIG7_IN_TR_GROUP11_OUTPUT3 = 0x070Bu, /* tr_group[11].output[3] */ + TRIG7_IN_TR_GROUP11_OUTPUT4 = 0x070Cu, /* tr_group[11].output[4] */ + TRIG7_IN_TR_GROUP11_OUTPUT5 = 0x070Du, /* tr_group[11].output[5] */ + TRIG7_IN_TR_GROUP11_OUTPUT6 = 0x070Eu, /* tr_group[11].output[6] */ + TRIG7_IN_TR_GROUP11_OUTPUT7 = 0x070Fu, /* tr_group[11].output[7] */ + TRIG7_IN_TR_GROUP11_OUTPUT8 = 0x0710u, /* tr_group[11].output[8] */ + TRIG7_IN_TR_GROUP11_OUTPUT9 = 0x0711u, /* tr_group[11].output[9] */ + TRIG7_IN_TR_GROUP11_OUTPUT10 = 0x0712u, /* tr_group[11].output[10] */ + TRIG7_IN_TR_GROUP11_OUTPUT11 = 0x0713u, /* tr_group[11].output[11] */ + TRIG7_IN_TR_GROUP11_OUTPUT12 = 0x0714u, /* tr_group[11].output[12] */ + TRIG7_IN_TR_GROUP11_OUTPUT13 = 0x0715u, /* tr_group[11].output[13] */ + TRIG7_IN_TR_GROUP11_OUTPUT14 = 0x0716u, /* tr_group[11].output[14] */ + TRIG7_IN_TR_GROUP11_OUTPUT15 = 0x0717u, /* tr_group[11].output[15] */ + TRIG7_IN_TR_GROUP12_OUTPUT0 = 0x0718u, /* tr_group[12].output[0] */ + TRIG7_IN_TR_GROUP12_OUTPUT1 = 0x0719u, /* tr_group[12].output[1] */ + TRIG7_IN_TR_GROUP12_OUTPUT2 = 0x071Au, /* tr_group[12].output[2] */ + TRIG7_IN_TR_GROUP12_OUTPUT3 = 0x071Bu, /* tr_group[12].output[3] */ + TRIG7_IN_TR_GROUP12_OUTPUT4 = 0x071Cu, /* tr_group[12].output[4] */ + TRIG7_IN_TR_GROUP12_OUTPUT5 = 0x071Du, /* tr_group[12].output[5] */ + TRIG7_IN_TR_GROUP12_OUTPUT6 = 0x071Eu, /* tr_group[12].output[6] */ + TRIG7_IN_TR_GROUP12_OUTPUT7 = 0x071Fu, /* tr_group[12].output[7] */ + TRIG7_IN_TR_GROUP13_OUTPUT16 = 0x0720u, /* tr_group[13].output[16] */ + TRIG7_IN_TR_GROUP13_OUTPUT17 = 0x0721u, /* tr_group[13].output[17] */ + TRIG7_IN_TR_GROUP14_OUTPUT8 = 0x0722u, /* tr_group[14].output[8] */ + TRIG7_IN_TR_GROUP14_OUTPUT9 = 0x0723u, /* tr_group[14].output[9] */ + TRIG7_IN_TR_GROUP14_OUTPUT10 = 0x0724u, /* tr_group[14].output[10] */ + TRIG7_IN_TR_GROUP14_OUTPUT11 = 0x0725u, /* tr_group[14].output[11] */ + TRIG7_IN_TR_GROUP14_OUTPUT12 = 0x0726u, /* tr_group[14].output[12] */ + TRIG7_IN_TR_GROUP14_OUTPUT13 = 0x0727u, /* tr_group[14].output[13] */ + TRIG7_IN_TR_GROUP14_OUTPUT14 = 0x0728u, /* tr_group[14].output[14] */ + TRIG7_IN_TR_GROUP14_OUTPUT15 = 0x0729u /* tr_group[14].output[15] */ +} en_trig_input_grp7_t; + +/* Trigger Input Group 8 - Trigger multiplexer to pins */ +typedef enum +{ + TRIG8_IN_TR_GROUP10_OUTPUT0 = 0x0800u, /* tr_group[10].output[0] */ + TRIG8_IN_TR_GROUP10_OUTPUT1 = 0x0801u, /* tr_group[10].output[1] */ + TRIG8_IN_TR_GROUP10_OUTPUT2 = 0x0802u, /* tr_group[10].output[2] */ + TRIG8_IN_TR_GROUP10_OUTPUT3 = 0x0803u, /* tr_group[10].output[3] */ + TRIG8_IN_TR_GROUP10_OUTPUT4 = 0x0804u, /* tr_group[10].output[4] */ + TRIG8_IN_TR_GROUP10_OUTPUT5 = 0x0805u, /* tr_group[10].output[5] */ + TRIG8_IN_TR_GROUP10_OUTPUT6 = 0x0806u, /* tr_group[10].output[6] */ + TRIG8_IN_TR_GROUP10_OUTPUT7 = 0x0807u, /* tr_group[10].output[7] */ + TRIG8_IN_TR_GROUP11_OUTPUT0 = 0x0808u, /* tr_group[11].output[0] */ + TRIG8_IN_TR_GROUP11_OUTPUT1 = 0x0809u, /* tr_group[11].output[1] */ + TRIG8_IN_TR_GROUP11_OUTPUT2 = 0x080Au, /* tr_group[11].output[2] */ + TRIG8_IN_TR_GROUP11_OUTPUT3 = 0x080Bu, /* tr_group[11].output[3] */ + TRIG8_IN_TR_GROUP11_OUTPUT4 = 0x080Cu, /* tr_group[11].output[4] */ + TRIG8_IN_TR_GROUP11_OUTPUT5 = 0x080Du, /* tr_group[11].output[5] */ + TRIG8_IN_TR_GROUP11_OUTPUT6 = 0x080Eu, /* tr_group[11].output[6] */ + TRIG8_IN_TR_GROUP11_OUTPUT7 = 0x080Fu, /* tr_group[11].output[7] */ + TRIG8_IN_TR_GROUP11_OUTPUT8 = 0x0810u, /* tr_group[11].output[8] */ + TRIG8_IN_TR_GROUP11_OUTPUT9 = 0x0811u, /* tr_group[11].output[9] */ + TRIG8_IN_TR_GROUP11_OUTPUT10 = 0x0812u, /* tr_group[11].output[10] */ + TRIG8_IN_TR_GROUP11_OUTPUT11 = 0x0813u, /* tr_group[11].output[11] */ + TRIG8_IN_TR_GROUP11_OUTPUT12 = 0x0814u, /* tr_group[11].output[12] */ + TRIG8_IN_TR_GROUP11_OUTPUT13 = 0x0815u, /* tr_group[11].output[13] */ + TRIG8_IN_TR_GROUP11_OUTPUT14 = 0x0816u, /* tr_group[11].output[14] */ + TRIG8_IN_TR_GROUP11_OUTPUT15 = 0x0817u, /* tr_group[11].output[15] */ + TRIG8_IN_TR_GROUP12_OUTPUT0 = 0x0818u, /* tr_group[12].output[0] */ + TRIG8_IN_TR_GROUP12_OUTPUT1 = 0x0819u, /* tr_group[12].output[1] */ + TRIG8_IN_TR_GROUP12_OUTPUT2 = 0x081Au, /* tr_group[12].output[2] */ + TRIG8_IN_TR_GROUP12_OUTPUT3 = 0x081Bu, /* tr_group[12].output[3] */ + TRIG8_IN_TR_GROUP12_OUTPUT4 = 0x081Cu, /* tr_group[12].output[4] */ + TRIG8_IN_TR_GROUP12_OUTPUT5 = 0x081Du, /* tr_group[12].output[5] */ + TRIG8_IN_TR_GROUP12_OUTPUT6 = 0x081Eu, /* tr_group[12].output[6] */ + TRIG8_IN_TR_GROUP12_OUTPUT7 = 0x081Fu, /* tr_group[12].output[7] */ + TRIG8_IN_TR_GROUP13_OUTPUT16 = 0x0820u, /* tr_group[13].output[16] */ + TRIG8_IN_TR_GROUP13_OUTPUT17 = 0x0821u, /* tr_group[13].output[17] */ + TRIG8_IN_TR_GROUP14_OUTPUT8 = 0x0822u, /* tr_group[14].output[8] */ + TRIG8_IN_TR_GROUP14_OUTPUT9 = 0x0823u, /* tr_group[14].output[9] */ + TRIG8_IN_TR_GROUP14_OUTPUT10 = 0x0824u, /* tr_group[14].output[10] */ + TRIG8_IN_TR_GROUP14_OUTPUT11 = 0x0825u, /* tr_group[14].output[11] */ + TRIG8_IN_TR_GROUP14_OUTPUT12 = 0x0826u, /* tr_group[14].output[12] */ + TRIG8_IN_TR_GROUP14_OUTPUT13 = 0x0827u, /* tr_group[14].output[13] */ + TRIG8_IN_TR_GROUP14_OUTPUT14 = 0x0828u, /* tr_group[14].output[14] */ + TRIG8_IN_TR_GROUP14_OUTPUT15 = 0x0829u /* tr_group[14].output[15] */ +} en_trig_input_grp8_t; + +/* Trigger Input Group 9 - Feedback mux to USB DMA interface */ +typedef enum +{ + TRIG9_IN_CPUSS_DW0_TR_OUT0 = 0x0900u, /* cpuss.dw0_tr_out[0] */ + TRIG9_IN_CPUSS_DW0_TR_OUT1 = 0x0901u, /* cpuss.dw0_tr_out[1] */ + TRIG9_IN_CPUSS_DW0_TR_OUT2 = 0x0902u, /* cpuss.dw0_tr_out[2] */ + TRIG9_IN_CPUSS_DW0_TR_OUT3 = 0x0903u, /* cpuss.dw0_tr_out[3] */ + TRIG9_IN_CPUSS_DW0_TR_OUT4 = 0x0904u, /* cpuss.dw0_tr_out[4] */ + TRIG9_IN_CPUSS_DW0_TR_OUT5 = 0x0905u, /* cpuss.dw0_tr_out[5] */ + TRIG9_IN_CPUSS_DW0_TR_OUT6 = 0x0906u, /* cpuss.dw0_tr_out[6] */ + TRIG9_IN_CPUSS_DW0_TR_OUT7 = 0x0907u, /* cpuss.dw0_tr_out[7] */ + TRIG9_IN_CPUSS_DW0_TR_OUT8 = 0x0908u, /* cpuss.dw0_tr_out[8] */ + TRIG9_IN_CPUSS_DW0_TR_OUT9 = 0x0909u, /* cpuss.dw0_tr_out[9] */ + TRIG9_IN_CPUSS_DW0_TR_OUT10 = 0x090Au, /* cpuss.dw0_tr_out[10] */ + TRIG9_IN_CPUSS_DW0_TR_OUT11 = 0x090Bu, /* cpuss.dw0_tr_out[11] */ + TRIG9_IN_CPUSS_DW0_TR_OUT12 = 0x090Cu, /* cpuss.dw0_tr_out[12] */ + TRIG9_IN_CPUSS_DW0_TR_OUT13 = 0x090Du, /* cpuss.dw0_tr_out[13] */ + TRIG9_IN_CPUSS_DW0_TR_OUT14 = 0x090Eu, /* cpuss.dw0_tr_out[14] */ + TRIG9_IN_CPUSS_DW0_TR_OUT15 = 0x090Fu, /* cpuss.dw0_tr_out[15] */ + TRIG9_IN_CPUSS_DW1_TR_OUT0 = 0x0910u, /* cpuss.dw1_tr_out[0] */ + TRIG9_IN_CPUSS_DW1_TR_OUT1 = 0x0911u, /* cpuss.dw1_tr_out[1] */ + TRIG9_IN_CPUSS_DW1_TR_OUT2 = 0x0912u, /* cpuss.dw1_tr_out[2] */ + TRIG9_IN_CPUSS_DW1_TR_OUT3 = 0x0913u, /* cpuss.dw1_tr_out[3] */ + TRIG9_IN_CPUSS_DW1_TR_OUT4 = 0x0914u, /* cpuss.dw1_tr_out[4] */ + TRIG9_IN_CPUSS_DW1_TR_OUT5 = 0x0915u, /* cpuss.dw1_tr_out[5] */ + TRIG9_IN_CPUSS_DW1_TR_OUT6 = 0x0916u, /* cpuss.dw1_tr_out[6] */ + TRIG9_IN_CPUSS_DW1_TR_OUT7 = 0x0917u, /* cpuss.dw1_tr_out[7] */ + TRIG9_IN_CPUSS_DW1_TR_OUT8 = 0x0918u, /* cpuss.dw1_tr_out[8] */ + TRIG9_IN_CPUSS_DW1_TR_OUT9 = 0x0919u, /* cpuss.dw1_tr_out[9] */ + TRIG9_IN_CPUSS_DW1_TR_OUT10 = 0x091Au, /* cpuss.dw1_tr_out[10] */ + TRIG9_IN_CPUSS_DW1_TR_OUT11 = 0x091Bu, /* cpuss.dw1_tr_out[11] */ + TRIG9_IN_CPUSS_DW1_TR_OUT12 = 0x091Cu, /* cpuss.dw1_tr_out[12] */ + TRIG9_IN_CPUSS_DW1_TR_OUT13 = 0x091Du, /* cpuss.dw1_tr_out[13] */ + TRIG9_IN_CPUSS_DW1_TR_OUT14 = 0x091Eu, /* cpuss.dw1_tr_out[14] */ + TRIG9_IN_CPUSS_DW1_TR_OUT15 = 0x091Fu /* cpuss.dw1_tr_out[15] */ +} en_trig_input_grp9_t; + +/* Trigger Input Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */ +typedef enum +{ + TRIG10_IN_CPUSS_DW0_TR_OUT0 = 0x0A00u, /* cpuss.dw0_tr_out[0] */ + TRIG10_IN_CPUSS_DW0_TR_OUT1 = 0x0A01u, /* cpuss.dw0_tr_out[1] */ + TRIG10_IN_CPUSS_DW0_TR_OUT2 = 0x0A02u, /* cpuss.dw0_tr_out[2] */ + TRIG10_IN_CPUSS_DW0_TR_OUT3 = 0x0A03u, /* cpuss.dw0_tr_out[3] */ + TRIG10_IN_CPUSS_DW0_TR_OUT4 = 0x0A04u, /* cpuss.dw0_tr_out[4] */ + TRIG10_IN_CPUSS_DW0_TR_OUT5 = 0x0A05u, /* cpuss.dw0_tr_out[5] */ + TRIG10_IN_CPUSS_DW0_TR_OUT6 = 0x0A06u, /* cpuss.dw0_tr_out[6] */ + TRIG10_IN_CPUSS_DW0_TR_OUT7 = 0x0A07u, /* cpuss.dw0_tr_out[7] */ + TRIG10_IN_CPUSS_DW0_TR_OUT8 = 0x0A08u, /* cpuss.dw0_tr_out[8] */ + TRIG10_IN_CPUSS_DW0_TR_OUT9 = 0x0A09u, /* cpuss.dw0_tr_out[9] */ + TRIG10_IN_CPUSS_DW0_TR_OUT10 = 0x0A0Au, /* cpuss.dw0_tr_out[10] */ + TRIG10_IN_CPUSS_DW0_TR_OUT11 = 0x0A0Bu, /* cpuss.dw0_tr_out[11] */ + TRIG10_IN_CPUSS_DW0_TR_OUT12 = 0x0A0Cu, /* cpuss.dw0_tr_out[12] */ + TRIG10_IN_CPUSS_DW0_TR_OUT13 = 0x0A0Du, /* cpuss.dw0_tr_out[13] */ + TRIG10_IN_CPUSS_DW0_TR_OUT14 = 0x0A0Eu, /* cpuss.dw0_tr_out[14] */ + TRIG10_IN_CPUSS_DW0_TR_OUT15 = 0x0A0Fu, /* cpuss.dw0_tr_out[15] */ + TRIG10_IN_CPUSS_DW1_TR_OUT0 = 0x0A10u, /* cpuss.dw1_tr_out[0] */ + TRIG10_IN_CPUSS_DW1_TR_OUT1 = 0x0A11u, /* cpuss.dw1_tr_out[1] */ + TRIG10_IN_CPUSS_DW1_TR_OUT2 = 0x0A12u, /* cpuss.dw1_tr_out[2] */ + TRIG10_IN_CPUSS_DW1_TR_OUT3 = 0x0A13u, /* cpuss.dw1_tr_out[3] */ + TRIG10_IN_CPUSS_DW1_TR_OUT4 = 0x0A14u, /* cpuss.dw1_tr_out[4] */ + TRIG10_IN_CPUSS_DW1_TR_OUT5 = 0x0A15u, /* cpuss.dw1_tr_out[5] */ + TRIG10_IN_CPUSS_DW1_TR_OUT6 = 0x0A16u, /* cpuss.dw1_tr_out[6] */ + TRIG10_IN_CPUSS_DW1_TR_OUT7 = 0x0A17u, /* cpuss.dw1_tr_out[7] */ + TRIG10_IN_CPUSS_DW1_TR_OUT8 = 0x0A18u, /* cpuss.dw1_tr_out[8] */ + TRIG10_IN_CPUSS_DW1_TR_OUT9 = 0x0A19u, /* cpuss.dw1_tr_out[9] */ + TRIG10_IN_CPUSS_DW1_TR_OUT10 = 0x0A1Au, /* cpuss.dw1_tr_out[10] */ + TRIG10_IN_CPUSS_DW1_TR_OUT11 = 0x0A1Bu, /* cpuss.dw1_tr_out[11] */ + TRIG10_IN_CPUSS_DW1_TR_OUT12 = 0x0A1Cu, /* cpuss.dw1_tr_out[12] */ + TRIG10_IN_CPUSS_DW1_TR_OUT13 = 0x0A1Du, /* cpuss.dw1_tr_out[13] */ + TRIG10_IN_CPUSS_DW1_TR_OUT14 = 0x0A1Eu, /* cpuss.dw1_tr_out[14] */ + TRIG10_IN_CPUSS_DW1_TR_OUT15 = 0x0A1Fu /* cpuss.dw1_tr_out[15] */ +} en_trig_input_grp10_t; + +/* Trigger Input Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */ +typedef enum +{ + TRIG11_IN_TCPWM0_TR_OVERFLOW0 = 0x0B00u, /* tcpwm[0].tr_overflow[0] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW1 = 0x0B01u, /* tcpwm[0].tr_overflow[1] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW2 = 0x0B02u, /* tcpwm[0].tr_overflow[2] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW3 = 0x0B03u, /* tcpwm[0].tr_overflow[3] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW4 = 0x0B04u, /* tcpwm[0].tr_overflow[4] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW5 = 0x0B05u, /* tcpwm[0].tr_overflow[5] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW6 = 0x0B06u, /* tcpwm[0].tr_overflow[6] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW7 = 0x0B07u, /* tcpwm[0].tr_overflow[7] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH0 = 0x0B08u, /* tcpwm[0].tr_compare_match[0] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH1 = 0x0B09u, /* tcpwm[0].tr_compare_match[1] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH2 = 0x0B0Au, /* tcpwm[0].tr_compare_match[2] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH3 = 0x0B0Bu, /* tcpwm[0].tr_compare_match[3] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH4 = 0x0B0Cu, /* tcpwm[0].tr_compare_match[4] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH5 = 0x0B0Du, /* tcpwm[0].tr_compare_match[5] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH6 = 0x0B0Eu, /* tcpwm[0].tr_compare_match[6] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH7 = 0x0B0Fu, /* tcpwm[0].tr_compare_match[7] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW0 = 0x0B10u, /* tcpwm[0].tr_underflow[0] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW1 = 0x0B11u, /* tcpwm[0].tr_underflow[1] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW2 = 0x0B12u, /* tcpwm[0].tr_underflow[2] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW3 = 0x0B13u, /* tcpwm[0].tr_underflow[3] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW4 = 0x0B14u, /* tcpwm[0].tr_underflow[4] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW5 = 0x0B15u, /* tcpwm[0].tr_underflow[5] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW6 = 0x0B16u, /* tcpwm[0].tr_underflow[6] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW7 = 0x0B17u, /* tcpwm[0].tr_underflow[7] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW0 = 0x0B18u, /* tcpwm[1].tr_overflow[0] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW1 = 0x0B19u, /* tcpwm[1].tr_overflow[1] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW2 = 0x0B1Au, /* tcpwm[1].tr_overflow[2] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW3 = 0x0B1Bu, /* tcpwm[1].tr_overflow[3] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW4 = 0x0B1Cu, /* tcpwm[1].tr_overflow[4] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW5 = 0x0B1Du, /* tcpwm[1].tr_overflow[5] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW6 = 0x0B1Eu, /* tcpwm[1].tr_overflow[6] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW7 = 0x0B1Fu, /* tcpwm[1].tr_overflow[7] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW8 = 0x0B20u, /* tcpwm[1].tr_overflow[8] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW9 = 0x0B21u, /* tcpwm[1].tr_overflow[9] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW10 = 0x0B22u, /* tcpwm[1].tr_overflow[10] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW11 = 0x0B23u, /* tcpwm[1].tr_overflow[11] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW12 = 0x0B24u, /* tcpwm[1].tr_overflow[12] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW13 = 0x0B25u, /* tcpwm[1].tr_overflow[13] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW14 = 0x0B26u, /* tcpwm[1].tr_overflow[14] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW15 = 0x0B27u, /* tcpwm[1].tr_overflow[15] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW16 = 0x0B28u, /* tcpwm[1].tr_overflow[16] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW17 = 0x0B29u, /* tcpwm[1].tr_overflow[17] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW18 = 0x0B2Au, /* tcpwm[1].tr_overflow[18] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW19 = 0x0B2Bu, /* tcpwm[1].tr_overflow[19] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW20 = 0x0B2Cu, /* tcpwm[1].tr_overflow[20] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW21 = 0x0B2Du, /* tcpwm[1].tr_overflow[21] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW22 = 0x0B2Eu, /* tcpwm[1].tr_overflow[22] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW23 = 0x0B2Fu, /* tcpwm[1].tr_overflow[23] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH0 = 0x0B30u, /* tcpwm[1].tr_compare_match[0] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH1 = 0x0B31u, /* tcpwm[1].tr_compare_match[1] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH2 = 0x0B32u, /* tcpwm[1].tr_compare_match[2] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH3 = 0x0B33u, /* tcpwm[1].tr_compare_match[3] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH4 = 0x0B34u, /* tcpwm[1].tr_compare_match[4] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH5 = 0x0B35u, /* tcpwm[1].tr_compare_match[5] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH6 = 0x0B36u, /* tcpwm[1].tr_compare_match[6] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH7 = 0x0B37u, /* tcpwm[1].tr_compare_match[7] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH8 = 0x0B38u, /* tcpwm[1].tr_compare_match[8] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH9 = 0x0B39u, /* tcpwm[1].tr_compare_match[9] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH10 = 0x0B3Au, /* tcpwm[1].tr_compare_match[10] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH11 = 0x0B3Bu, /* tcpwm[1].tr_compare_match[11] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH12 = 0x0B3Cu, /* tcpwm[1].tr_compare_match[12] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH13 = 0x0B3Du, /* tcpwm[1].tr_compare_match[13] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH14 = 0x0B3Eu, /* tcpwm[1].tr_compare_match[14] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH15 = 0x0B3Fu, /* tcpwm[1].tr_compare_match[15] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH16 = 0x0B40u, /* tcpwm[1].tr_compare_match[16] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH17 = 0x0B41u, /* tcpwm[1].tr_compare_match[17] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH18 = 0x0B42u, /* tcpwm[1].tr_compare_match[18] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH19 = 0x0B43u, /* tcpwm[1].tr_compare_match[19] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH20 = 0x0B44u, /* tcpwm[1].tr_compare_match[20] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH21 = 0x0B45u, /* tcpwm[1].tr_compare_match[21] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH22 = 0x0B46u, /* tcpwm[1].tr_compare_match[22] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH23 = 0x0B47u, /* tcpwm[1].tr_compare_match[23] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW0 = 0x0B48u, /* tcpwm[1].tr_underflow[0] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW1 = 0x0B49u, /* tcpwm[1].tr_underflow[1] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW2 = 0x0B4Au, /* tcpwm[1].tr_underflow[2] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW3 = 0x0B4Bu, /* tcpwm[1].tr_underflow[3] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW4 = 0x0B4Cu, /* tcpwm[1].tr_underflow[4] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW5 = 0x0B4Du, /* tcpwm[1].tr_underflow[5] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW6 = 0x0B4Eu, /* tcpwm[1].tr_underflow[6] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW7 = 0x0B4Fu, /* tcpwm[1].tr_underflow[7] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW8 = 0x0B50u, /* tcpwm[1].tr_underflow[8] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW9 = 0x0B51u, /* tcpwm[1].tr_underflow[9] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW10 = 0x0B52u, /* tcpwm[1].tr_underflow[10] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW11 = 0x0B53u, /* tcpwm[1].tr_underflow[11] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW12 = 0x0B54u, /* tcpwm[1].tr_underflow[12] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW13 = 0x0B55u, /* tcpwm[1].tr_underflow[13] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW14 = 0x0B56u, /* tcpwm[1].tr_underflow[14] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW15 = 0x0B57u, /* tcpwm[1].tr_underflow[15] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW16 = 0x0B58u, /* tcpwm[1].tr_underflow[16] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW17 = 0x0B59u, /* tcpwm[1].tr_underflow[17] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW18 = 0x0B5Au, /* tcpwm[1].tr_underflow[18] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW19 = 0x0B5Bu, /* tcpwm[1].tr_underflow[19] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW20 = 0x0B5Cu, /* tcpwm[1].tr_underflow[20] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW21 = 0x0B5Du, /* tcpwm[1].tr_underflow[21] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW22 = 0x0B5Eu, /* tcpwm[1].tr_underflow[22] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW23 = 0x0B5Fu /* tcpwm[1].tr_underflow[23] */ +} en_trig_input_grp11_t; + +/* Trigger Input Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */ +typedef enum +{ + TRIG12_IN_PERI_TR_IO_INPUT0 = 0x0C00u, /* peri.tr_io_input[0] */ + TRIG12_IN_PERI_TR_IO_INPUT1 = 0x0C01u, /* peri.tr_io_input[1] */ + TRIG12_IN_PERI_TR_IO_INPUT2 = 0x0C02u, /* peri.tr_io_input[2] */ + TRIG12_IN_PERI_TR_IO_INPUT3 = 0x0C03u, /* peri.tr_io_input[3] */ + TRIG12_IN_PERI_TR_IO_INPUT4 = 0x0C04u, /* peri.tr_io_input[4] */ + TRIG12_IN_PERI_TR_IO_INPUT5 = 0x0C05u, /* peri.tr_io_input[5] */ + TRIG12_IN_PERI_TR_IO_INPUT6 = 0x0C06u, /* peri.tr_io_input[6] */ + TRIG12_IN_PERI_TR_IO_INPUT7 = 0x0C07u, /* peri.tr_io_input[7] */ + TRIG12_IN_PERI_TR_IO_INPUT8 = 0x0C08u, /* peri.tr_io_input[8] */ + TRIG12_IN_PERI_TR_IO_INPUT9 = 0x0C09u, /* peri.tr_io_input[9] */ + TRIG12_IN_PERI_TR_IO_INPUT10 = 0x0C0Au, /* peri.tr_io_input[10] */ + TRIG12_IN_PERI_TR_IO_INPUT11 = 0x0C0Bu, /* peri.tr_io_input[11] */ + TRIG12_IN_PERI_TR_IO_INPUT12 = 0x0C0Cu, /* peri.tr_io_input[12] */ + TRIG12_IN_PERI_TR_IO_INPUT13 = 0x0C0Du, /* peri.tr_io_input[13] */ + TRIG12_IN_PERI_TR_IO_INPUT14 = 0x0C0Eu, /* peri.tr_io_input[14] */ + TRIG12_IN_PERI_TR_IO_INPUT15 = 0x0C0Fu, /* peri.tr_io_input[15] */ + TRIG12_IN_PERI_TR_IO_INPUT16 = 0x0C10u, /* peri.tr_io_input[16] */ + TRIG12_IN_PERI_TR_IO_INPUT17 = 0x0C11u, /* peri.tr_io_input[17] */ + TRIG12_IN_PERI_TR_IO_INPUT18 = 0x0C12u, /* peri.tr_io_input[18] */ + TRIG12_IN_PERI_TR_IO_INPUT19 = 0x0C13u, /* peri.tr_io_input[19] */ + TRIG12_IN_PERI_TR_IO_INPUT20 = 0x0C14u, /* peri.tr_io_input[20] */ + TRIG12_IN_PERI_TR_IO_INPUT21 = 0x0C15u, /* peri.tr_io_input[21] */ + TRIG12_IN_PERI_TR_IO_INPUT22 = 0x0C16u, /* peri.tr_io_input[22] */ + TRIG12_IN_PERI_TR_IO_INPUT23 = 0x0C17u, /* peri.tr_io_input[23] */ + TRIG12_IN_PERI_TR_IO_INPUT24 = 0x0C18u, /* peri.tr_io_input[24] */ + TRIG12_IN_PERI_TR_IO_INPUT25 = 0x0C19u, /* peri.tr_io_input[25] */ + TRIG12_IN_PERI_TR_IO_INPUT26 = 0x0C1Au, /* peri.tr_io_input[26] */ + TRIG12_IN_PERI_TR_IO_INPUT27 = 0x0C1Bu /* peri.tr_io_input[27] */ +} en_trig_input_grp12_t; + +/* Trigger Input Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */ +typedef enum +{ + TRIG13_IN_SCB0_TR_TX_REQ = 0x0D00u, /* scb[0].tr_tx_req */ + TRIG13_IN_SCB0_TR_RX_REQ = 0x0D01u, /* scb[0].tr_rx_req */ + TRIG13_IN_SCB1_TR_TX_REQ = 0x0D02u, /* scb[1].tr_tx_req */ + TRIG13_IN_SCB1_TR_RX_REQ = 0x0D03u, /* scb[1].tr_rx_req */ + TRIG13_IN_SCB2_TR_TX_REQ = 0x0D04u, /* scb[2].tr_tx_req */ + TRIG13_IN_SCB2_TR_RX_REQ = 0x0D05u, /* scb[2].tr_rx_req */ + TRIG13_IN_SCB3_TR_TX_REQ = 0x0D06u, /* scb[3].tr_tx_req */ + TRIG13_IN_SCB3_TR_RX_REQ = 0x0D07u, /* scb[3].tr_rx_req */ + TRIG13_IN_SCB4_TR_TX_REQ = 0x0D08u, /* scb[4].tr_tx_req */ + TRIG13_IN_SCB4_TR_RX_REQ = 0x0D09u, /* scb[4].tr_rx_req */ + TRIG13_IN_SCB5_TR_TX_REQ = 0x0D0Au, /* scb[5].tr_tx_req */ + TRIG13_IN_SCB5_TR_RX_REQ = 0x0D0Bu, /* scb[5].tr_rx_req */ + TRIG13_IN_SCB6_TR_TX_REQ = 0x0D0Cu, /* scb[6].tr_tx_req */ + TRIG13_IN_SCB6_TR_RX_REQ = 0x0D0Du, /* scb[6].tr_rx_req */ + TRIG13_IN_SCB7_TR_TX_REQ = 0x0D0Eu, /* scb[7].tr_tx_req */ + TRIG13_IN_SCB7_TR_RX_REQ = 0x0D0Fu, /* scb[7].tr_rx_req */ + TRIG13_IN_SCB8_TR_TX_REQ = 0x0D10u, /* scb[8].tr_tx_req */ + TRIG13_IN_SCB8_TR_RX_REQ = 0x0D11u, /* scb[8].tr_rx_req */ + TRIG13_IN_AUDIOSS_TR_PDM_RX_REQ = 0x0D12u, /* audioss.tr_pdm_rx_req */ + TRIG13_IN_AUDIOSS_TR_I2S_TX_REQ = 0x0D13u, /* audioss.tr_i2s_tx_req */ + TRIG13_IN_AUDIOSS_TR_I2S_RX_REQ = 0x0D14u, /* audioss.tr_i2s_rx_req */ + TRIG13_IN_SMIF_TR_TX_REQ = 0x0D15u, /* smif.tr_tx_req */ + TRIG13_IN_SMIF_TR_RX_REQ = 0x0D16u, /* smif.tr_rx_req */ + TRIG13_IN_USB_DMA_REQ0 = 0x0D17u, /* usb.dma_req[0] */ + TRIG13_IN_USB_DMA_REQ1 = 0x0D18u, /* usb.dma_req[1] */ + TRIG13_IN_USB_DMA_REQ2 = 0x0D19u, /* usb.dma_req[2] */ + TRIG13_IN_USB_DMA_REQ3 = 0x0D1Au, /* usb.dma_req[3] */ + TRIG13_IN_USB_DMA_REQ4 = 0x0D1Bu, /* usb.dma_req[4] */ + TRIG13_IN_USB_DMA_REQ5 = 0x0D1Cu, /* usb.dma_req[5] */ + TRIG13_IN_USB_DMA_REQ6 = 0x0D1Du, /* usb.dma_req[6] */ + TRIG13_IN_USB_DMA_REQ7 = 0x0D1Eu /* usb.dma_req[7] */ +} en_trig_input_grp13_t; + +/* Trigger Input Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */ +typedef enum +{ + TRIG14_IN_UDB_TR_UDB0 = 0x0E00u, /* udb.tr_udb[0] */ + TRIG14_IN_UDB_TR_UDB1 = 0x0E01u, /* udb.tr_udb[1] */ + TRIG14_IN_UDB_TR_UDB2 = 0x0E02u, /* udb.tr_udb[2] */ + TRIG14_IN_UDB_TR_UDB3 = 0x0E03u, /* udb.tr_udb[3] */ + TRIG14_IN_UDB_TR_UDB4 = 0x0E04u, /* udb.tr_udb[4] */ + TRIG14_IN_UDB_TR_UDB5 = 0x0E05u, /* udb.tr_udb[5] */ + TRIG14_IN_UDB_TR_UDB6 = 0x0E06u, /* udb.tr_udb[6] */ + TRIG14_IN_UDB_TR_UDB7 = 0x0E07u, /* udb.tr_udb[7] */ + TRIG14_IN_UDB_TR_UDB8 = 0x0E08u, /* udb.tr_udb[8] */ + TRIG14_IN_UDB_TR_UDB9 = 0x0E09u, /* udb.tr_udb[9] */ + TRIG14_IN_UDB_TR_UDB10 = 0x0E0Au, /* udb.tr_udb[10] */ + TRIG14_IN_UDB_TR_UDB11 = 0x0E0Bu, /* udb.tr_udb[11] */ + TRIG14_IN_UDB_TR_UDB12 = 0x0E0Cu, /* udb.tr_udb[12] */ + TRIG14_IN_UDB_TR_UDB13 = 0x0E0Du, /* udb.tr_udb[13] */ + TRIG14_IN_UDB_TR_UDB14 = 0x0E0Eu, /* udb.tr_udb[14] */ + TRIG14_IN_UDB_TR_UDB15 = 0x0E0Fu, /* udb.tr_udb[15] */ + TRIG14_IN_UDB_DSI_OUT_TR0 = 0x0E10u, /* udb.dsi_out_tr[0] */ + TRIG14_IN_UDB_DSI_OUT_TR1 = 0x0E11u, /* udb.dsi_out_tr[1] */ + TRIG14_IN_CPUSS_CTI_TR_OUT0 = 0x0E12u, /* cpuss.cti_tr_out[0] */ + TRIG14_IN_CPUSS_CTI_TR_OUT1 = 0x0E13u, /* cpuss.cti_tr_out[1] */ + TRIG14_IN_PASS_TR_SAR_OUT = 0x0E14u, /* pass.tr_sar_out */ + TRIG14_IN_PASS_TR_CTDAC_EMPTY = 0x0E15u, /* pass.tr_ctdac_empty */ + TRIG14_IN_PASS_DSI_CTB_CMP0 = 0x0E16u, /* pass.dsi_ctb_cmp0 */ + TRIG14_IN_PASS_DSI_CTB_CMP1 = 0x0E17u, /* pass.dsi_ctb_cmp1 */ + TRIG14_IN_LPCOMP_DSI_COMP0 = 0x0E18u, /* lpcomp.dsi_comp0 */ + TRIG14_IN_LPCOMP_DSI_COMP1 = 0x0E19u, /* lpcomp.dsi_comp1 */ + TRIG14_IN_SCB0_TR_I2C_SCL_FILTERED = 0x0E1Au, /* scb[0].tr_i2c_scl_filtered */ + TRIG14_IN_SCB1_TR_I2C_SCL_FILTERED = 0x0E1Bu, /* scb[1].tr_i2c_scl_filtered */ + TRIG14_IN_SCB2_TR_I2C_SCL_FILTERED = 0x0E1Cu, /* scb[2].tr_i2c_scl_filtered */ + TRIG14_IN_SCB3_TR_I2C_SCL_FILTERED = 0x0E1Du, /* scb[3].tr_i2c_scl_filtered */ + TRIG14_IN_SCB4_TR_I2C_SCL_FILTERED = 0x0E1Eu, /* scb[4].tr_i2c_scl_filtered */ + TRIG14_IN_SCB5_TR_I2C_SCL_FILTERED = 0x0E1Fu, /* scb[5].tr_i2c_scl_filtered */ + TRIG14_IN_SCB6_TR_I2C_SCL_FILTERED = 0x0E20u, /* scb[6].tr_i2c_scl_filtered */ + TRIG14_IN_SCB7_TR_I2C_SCL_FILTERED = 0x0E21u, /* scb[7].tr_i2c_scl_filtered */ + TRIG14_IN_SCB8_TR_I2C_SCL_FILTERED = 0x0E22u, /* scb[8].tr_i2c_scl_filtered */ + TRIG14_IN_CPUSS_TR_FAULT0 = 0x0E23u, /* cpuss.tr_fault[0] */ + TRIG14_IN_CPUSS_TR_FAULT1 = 0x0E24u /* cpuss.tr_fault[1] */ +} en_trig_input_grp14_t; + +/* Trigger Group Outputs */ +/* Trigger Output Group 0 - DMA Request Assignments */ +typedef enum +{ + TRIG0_OUT_CPUSS_DW0_TR_IN0 = 0x1000u, /* cpuss.dw0_tr_in[0] */ + TRIG0_OUT_CPUSS_DW0_TR_IN1 = 0x1001u, /* cpuss.dw0_tr_in[1] */ + TRIG0_OUT_CPUSS_DW0_TR_IN2 = 0x1002u, /* cpuss.dw0_tr_in[2] */ + TRIG0_OUT_CPUSS_DW0_TR_IN3 = 0x1003u, /* cpuss.dw0_tr_in[3] */ + TRIG0_OUT_CPUSS_DW0_TR_IN4 = 0x1004u, /* cpuss.dw0_tr_in[4] */ + TRIG0_OUT_CPUSS_DW0_TR_IN5 = 0x1005u, /* cpuss.dw0_tr_in[5] */ + TRIG0_OUT_CPUSS_DW0_TR_IN6 = 0x1006u, /* cpuss.dw0_tr_in[6] */ + TRIG0_OUT_CPUSS_DW0_TR_IN7 = 0x1007u, /* cpuss.dw0_tr_in[7] */ + TRIG0_OUT_CPUSS_DW0_TR_IN8 = 0x1008u, /* cpuss.dw0_tr_in[8] */ + TRIG0_OUT_CPUSS_DW0_TR_IN9 = 0x1009u, /* cpuss.dw0_tr_in[9] */ + TRIG0_OUT_CPUSS_DW0_TR_IN10 = 0x100Au, /* cpuss.dw0_tr_in[10] */ + TRIG0_OUT_CPUSS_DW0_TR_IN11 = 0x100Bu, /* cpuss.dw0_tr_in[11] */ + TRIG0_OUT_CPUSS_DW0_TR_IN12 = 0x100Cu, /* cpuss.dw0_tr_in[12] */ + TRIG0_OUT_CPUSS_DW0_TR_IN13 = 0x100Du, /* cpuss.dw0_tr_in[13] */ + TRIG0_OUT_CPUSS_DW0_TR_IN14 = 0x100Eu, /* cpuss.dw0_tr_in[14] */ + TRIG0_OUT_CPUSS_DW0_TR_IN15 = 0x100Fu /* cpuss.dw0_tr_in[15] */ +} en_trig_output_grp0_t; + +/* Trigger Output Group 1 - DMA Request Assignments */ +typedef enum +{ + TRIG1_OUT_CPUSS_DW1_TR_IN0 = 0x1100u, /* cpuss.dw1_tr_in[0] */ + TRIG1_OUT_CPUSS_DW1_TR_IN1 = 0x1101u, /* cpuss.dw1_tr_in[1] */ + TRIG1_OUT_CPUSS_DW1_TR_IN2 = 0x1102u, /* cpuss.dw1_tr_in[2] */ + TRIG1_OUT_CPUSS_DW1_TR_IN3 = 0x1103u, /* cpuss.dw1_tr_in[3] */ + TRIG1_OUT_CPUSS_DW1_TR_IN4 = 0x1104u, /* cpuss.dw1_tr_in[4] */ + TRIG1_OUT_CPUSS_DW1_TR_IN5 = 0x1105u, /* cpuss.dw1_tr_in[5] */ + TRIG1_OUT_CPUSS_DW1_TR_IN6 = 0x1106u, /* cpuss.dw1_tr_in[6] */ + TRIG1_OUT_CPUSS_DW1_TR_IN7 = 0x1107u, /* cpuss.dw1_tr_in[7] */ + TRIG1_OUT_CPUSS_DW1_TR_IN8 = 0x1108u, /* cpuss.dw1_tr_in[8] */ + TRIG1_OUT_CPUSS_DW1_TR_IN9 = 0x1109u, /* cpuss.dw1_tr_in[9] */ + TRIG1_OUT_CPUSS_DW1_TR_IN10 = 0x110Au, /* cpuss.dw1_tr_in[10] */ + TRIG1_OUT_CPUSS_DW1_TR_IN11 = 0x110Bu, /* cpuss.dw1_tr_in[11] */ + TRIG1_OUT_CPUSS_DW1_TR_IN12 = 0x110Cu, /* cpuss.dw1_tr_in[12] */ + TRIG1_OUT_CPUSS_DW1_TR_IN13 = 0x110Du, /* cpuss.dw1_tr_in[13] */ + TRIG1_OUT_CPUSS_DW1_TR_IN14 = 0x110Eu, /* cpuss.dw1_tr_in[14] */ + TRIG1_OUT_CPUSS_DW1_TR_IN15 = 0x110Fu /* cpuss.dw1_tr_in[15] */ +} en_trig_output_grp1_t; + +/* Trigger Output Group 2 - TCPWM trigger inputs */ +typedef enum +{ + TRIG2_OUT_TCPWM0_TR_IN0 = 0x1200u, /* tcpwm[0].tr_in[0] */ + TRIG2_OUT_TCPWM0_TR_IN1 = 0x1201u, /* tcpwm[0].tr_in[1] */ + TRIG2_OUT_TCPWM0_TR_IN2 = 0x1202u, /* tcpwm[0].tr_in[2] */ + TRIG2_OUT_TCPWM0_TR_IN3 = 0x1203u, /* tcpwm[0].tr_in[3] */ + TRIG2_OUT_TCPWM0_TR_IN4 = 0x1204u, /* tcpwm[0].tr_in[4] */ + TRIG2_OUT_TCPWM0_TR_IN5 = 0x1205u, /* tcpwm[0].tr_in[5] */ + TRIG2_OUT_TCPWM0_TR_IN6 = 0x1206u, /* tcpwm[0].tr_in[6] */ + TRIG2_OUT_TCPWM0_TR_IN7 = 0x1207u, /* tcpwm[0].tr_in[7] */ + TRIG2_OUT_TCPWM0_TR_IN8 = 0x1208u, /* tcpwm[0].tr_in[8] */ + TRIG2_OUT_TCPWM0_TR_IN9 = 0x1209u, /* tcpwm[0].tr_in[9] */ + TRIG2_OUT_TCPWM0_TR_IN10 = 0x120Au, /* tcpwm[0].tr_in[10] */ + TRIG2_OUT_TCPWM0_TR_IN11 = 0x120Bu, /* tcpwm[0].tr_in[11] */ + TRIG2_OUT_TCPWM0_TR_IN12 = 0x120Cu, /* tcpwm[0].tr_in[12] */ + TRIG2_OUT_TCPWM0_TR_IN13 = 0x120Du /* tcpwm[0].tr_in[13] */ +} en_trig_output_grp2_t; + +/* Trigger Output Group 3 - TCPWM trigger inputs */ +typedef enum +{ + TRIG3_OUT_TCPWM1_TR_IN0 = 0x1300u, /* tcpwm[1].tr_in[0] */ + TRIG3_OUT_TCPWM1_TR_IN1 = 0x1301u, /* tcpwm[1].tr_in[1] */ + TRIG3_OUT_TCPWM1_TR_IN2 = 0x1302u, /* tcpwm[1].tr_in[2] */ + TRIG3_OUT_TCPWM1_TR_IN3 = 0x1303u, /* tcpwm[1].tr_in[3] */ + TRIG3_OUT_TCPWM1_TR_IN4 = 0x1304u, /* tcpwm[1].tr_in[4] */ + TRIG3_OUT_TCPWM1_TR_IN5 = 0x1305u, /* tcpwm[1].tr_in[5] */ + TRIG3_OUT_TCPWM1_TR_IN6 = 0x1306u, /* tcpwm[1].tr_in[6] */ + TRIG3_OUT_TCPWM1_TR_IN7 = 0x1307u, /* tcpwm[1].tr_in[7] */ + TRIG3_OUT_TCPWM1_TR_IN8 = 0x1308u, /* tcpwm[1].tr_in[8] */ + TRIG3_OUT_TCPWM1_TR_IN9 = 0x1309u, /* tcpwm[1].tr_in[9] */ + TRIG3_OUT_TCPWM1_TR_IN10 = 0x130Au, /* tcpwm[1].tr_in[10] */ + TRIG3_OUT_TCPWM1_TR_IN11 = 0x130Bu, /* tcpwm[1].tr_in[11] */ + TRIG3_OUT_TCPWM1_TR_IN12 = 0x130Cu, /* tcpwm[1].tr_in[12] */ + TRIG3_OUT_TCPWM1_TR_IN13 = 0x130Du /* tcpwm[1].tr_in[13] */ +} en_trig_output_grp3_t; + +/* Trigger Output Group 4 - PROFILE trigger multiplexer */ +typedef enum +{ + TRIG4_OUT_PROFILE_TR_START = 0x1400u, /* profile.tr_start */ + TRIG4_OUT_PROFILE_TR_STOP = 0x1401u /* profile.tr_stop */ +} en_trig_output_grp4_t; + +/* Trigger Output Group 5 - CPUSS.CTI trigger multiplexer */ +typedef enum +{ + TRIG5_OUT_CPUSS_CTI_TR_IN0 = 0x1500u, /* cpuss.cti_tr_in[0] */ + TRIG5_OUT_CPUSS_CTI_TR_IN1 = 0x1501u /* cpuss.cti_tr_in[1] */ +} en_trig_output_grp5_t; + +/* Trigger Output Group 6 - PASS trigger multiplexer */ +typedef enum +{ + TRIG6_OUT_PASS_TR_SAR_IN = 0x1600u /* pass.tr_sar_in */ +} en_trig_output_grp6_t; + +/* Trigger Output Group 7 - UDB general purpose trigger multiplexer */ +typedef enum +{ + TRIG7_OUT_UDB_TR_IN0 = 0x1700u, /* udb.tr_in[0] */ + TRIG7_OUT_UDB_TR_IN1 = 0x1701u /* udb.tr_in[1] */ +} en_trig_output_grp7_t; + +/* Trigger Output Group 8 - Trigger multiplexer to pins */ +typedef enum +{ + TRIG8_OUT_PERI_TR_IO_OUTPUT0 = 0x1800u, /* peri.tr_io_output[0] */ + TRIG8_OUT_PERI_TR_IO_OUTPUT1 = 0x1801u /* peri.tr_io_output[1] */ +} en_trig_output_grp8_t; + +/* Trigger Output Group 9 - Feedback mux to USB DMA interface */ +typedef enum +{ + TRIG9_OUT_USB_DMA_BURSTEND0 = 0x1900u, /* usb.dma_burstend[0] */ + TRIG9_OUT_USB_DMA_BURSTEND1 = 0x1901u, /* usb.dma_burstend[1] */ + TRIG9_OUT_USB_DMA_BURSTEND2 = 0x1902u, /* usb.dma_burstend[2] */ + TRIG9_OUT_USB_DMA_BURSTEND3 = 0x1903u, /* usb.dma_burstend[3] */ + TRIG9_OUT_USB_DMA_BURSTEND4 = 0x1904u, /* usb.dma_burstend[4] */ + TRIG9_OUT_USB_DMA_BURSTEND5 = 0x1905u, /* usb.dma_burstend[5] */ + TRIG9_OUT_USB_DMA_BURSTEND6 = 0x1906u, /* usb.dma_burstend[6] */ + TRIG9_OUT_USB_DMA_BURSTEND7 = 0x1907u /* usb.dma_burstend[7] */ +} en_trig_output_grp9_t; + +/* Trigger Output Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */ +typedef enum +{ + TRIG10_OUT_UDB_TR_DW_ACK0 = 0x1A00u, /* udb.tr_dw_ack[0] */ + TRIG10_OUT_TR_GROUP0_INPUT0 = 0x1A00u, /* tr_group[0].input[0] */ + TRIG10_OUT_TR_GROUP1_INPUT0 = 0x1A00u, /* tr_group[1].input[0] */ + TRIG10_OUT_TR_GROUP2_INPUT0 = 0x1A00u, /* tr_group[2].input[0] */ + TRIG10_OUT_TR_GROUP3_INPUT0 = 0x1A00u, /* tr_group[3].input[0] */ + TRIG10_OUT_TR_GROUP4_INPUT0 = 0x1A00u, /* tr_group[4].input[0] */ + TRIG10_OUT_TR_GROUP5_INPUT0 = 0x1A00u, /* tr_group[5].input[0] */ + TRIG10_OUT_TR_GROUP6_INPUT0 = 0x1A00u, /* tr_group[6].input[0] */ + TRIG10_OUT_TR_GROUP7_INPUT0 = 0x1A00u, /* tr_group[7].input[0] */ + TRIG10_OUT_TR_GROUP8_INPUT0 = 0x1A00u, /* tr_group[8].input[0] */ + TRIG10_OUT_UDB_TR_DW_ACK1 = 0x1A01u, /* udb.tr_dw_ack[1] */ + TRIG10_OUT_TR_GROUP0_INPUT1 = 0x1A01u, /* tr_group[0].input[1] */ + TRIG10_OUT_TR_GROUP1_INPUT1 = 0x1A01u, /* tr_group[1].input[1] */ + TRIG10_OUT_TR_GROUP2_INPUT1 = 0x1A01u, /* tr_group[2].input[1] */ + TRIG10_OUT_TR_GROUP3_INPUT1 = 0x1A01u, /* tr_group[3].input[1] */ + TRIG10_OUT_TR_GROUP4_INPUT1 = 0x1A01u, /* tr_group[4].input[1] */ + TRIG10_OUT_TR_GROUP5_INPUT1 = 0x1A01u, /* tr_group[5].input[1] */ + TRIG10_OUT_TR_GROUP6_INPUT1 = 0x1A01u, /* tr_group[6].input[1] */ + TRIG10_OUT_TR_GROUP7_INPUT1 = 0x1A01u, /* tr_group[7].input[1] */ + TRIG10_OUT_TR_GROUP8_INPUT1 = 0x1A01u, /* tr_group[8].input[1] */ + TRIG10_OUT_UDB_TR_DW_ACK2 = 0x1A02u, /* udb.tr_dw_ack[2] */ + TRIG10_OUT_TR_GROUP0_INPUT2 = 0x1A02u, /* tr_group[0].input[2] */ + TRIG10_OUT_TR_GROUP1_INPUT2 = 0x1A02u, /* tr_group[1].input[2] */ + TRIG10_OUT_TR_GROUP2_INPUT2 = 0x1A02u, /* tr_group[2].input[2] */ + TRIG10_OUT_TR_GROUP3_INPUT2 = 0x1A02u, /* tr_group[3].input[2] */ + TRIG10_OUT_TR_GROUP4_INPUT2 = 0x1A02u, /* tr_group[4].input[2] */ + TRIG10_OUT_TR_GROUP5_INPUT2 = 0x1A02u, /* tr_group[5].input[2] */ + TRIG10_OUT_TR_GROUP6_INPUT2 = 0x1A02u, /* tr_group[6].input[2] */ + TRIG10_OUT_TR_GROUP7_INPUT2 = 0x1A02u, /* tr_group[7].input[2] */ + TRIG10_OUT_TR_GROUP8_INPUT2 = 0x1A02u, /* tr_group[8].input[2] */ + TRIG10_OUT_UDB_TR_DW_ACK3 = 0x1A03u, /* udb.tr_dw_ack[3] */ + TRIG10_OUT_TR_GROUP0_INPUT3 = 0x1A03u, /* tr_group[0].input[3] */ + TRIG10_OUT_TR_GROUP1_INPUT3 = 0x1A03u, /* tr_group[1].input[3] */ + TRIG10_OUT_TR_GROUP2_INPUT3 = 0x1A03u, /* tr_group[2].input[3] */ + TRIG10_OUT_TR_GROUP3_INPUT3 = 0x1A03u, /* tr_group[3].input[3] */ + TRIG10_OUT_TR_GROUP4_INPUT3 = 0x1A03u, /* tr_group[4].input[3] */ + TRIG10_OUT_TR_GROUP5_INPUT3 = 0x1A03u, /* tr_group[5].input[3] */ + TRIG10_OUT_TR_GROUP6_INPUT3 = 0x1A03u, /* tr_group[6].input[3] */ + TRIG10_OUT_TR_GROUP7_INPUT3 = 0x1A03u, /* tr_group[7].input[3] */ + TRIG10_OUT_TR_GROUP8_INPUT3 = 0x1A03u, /* tr_group[8].input[3] */ + TRIG10_OUT_UDB_TR_DW_ACK4 = 0x1A04u, /* udb.tr_dw_ack[4] */ + TRIG10_OUT_TR_GROUP0_INPUT4 = 0x1A04u, /* tr_group[0].input[4] */ + TRIG10_OUT_TR_GROUP1_INPUT4 = 0x1A04u, /* tr_group[1].input[4] */ + TRIG10_OUT_TR_GROUP2_INPUT4 = 0x1A04u, /* tr_group[2].input[4] */ + TRIG10_OUT_TR_GROUP3_INPUT4 = 0x1A04u, /* tr_group[3].input[4] */ + TRIG10_OUT_TR_GROUP4_INPUT4 = 0x1A04u, /* tr_group[4].input[4] */ + TRIG10_OUT_TR_GROUP5_INPUT4 = 0x1A04u, /* tr_group[5].input[4] */ + TRIG10_OUT_TR_GROUP6_INPUT4 = 0x1A04u, /* tr_group[6].input[4] */ + TRIG10_OUT_TR_GROUP7_INPUT4 = 0x1A04u, /* tr_group[7].input[4] */ + TRIG10_OUT_TR_GROUP8_INPUT4 = 0x1A04u, /* tr_group[8].input[4] */ + TRIG10_OUT_UDB_TR_DW_ACK5 = 0x1A05u, /* udb.tr_dw_ack[5] */ + TRIG10_OUT_TR_GROUP0_INPUT5 = 0x1A05u, /* tr_group[0].input[5] */ + TRIG10_OUT_TR_GROUP1_INPUT5 = 0x1A05u, /* tr_group[1].input[5] */ + TRIG10_OUT_TR_GROUP2_INPUT5 = 0x1A05u, /* tr_group[2].input[5] */ + TRIG10_OUT_TR_GROUP3_INPUT5 = 0x1A05u, /* tr_group[3].input[5] */ + TRIG10_OUT_TR_GROUP4_INPUT5 = 0x1A05u, /* tr_group[4].input[5] */ + TRIG10_OUT_TR_GROUP5_INPUT5 = 0x1A05u, /* tr_group[5].input[5] */ + TRIG10_OUT_TR_GROUP6_INPUT5 = 0x1A05u, /* tr_group[6].input[5] */ + TRIG10_OUT_TR_GROUP7_INPUT5 = 0x1A05u, /* tr_group[7].input[5] */ + TRIG10_OUT_TR_GROUP8_INPUT5 = 0x1A05u, /* tr_group[8].input[5] */ + TRIG10_OUT_UDB_TR_DW_ACK6 = 0x1A06u, /* udb.tr_dw_ack[6] */ + TRIG10_OUT_TR_GROUP0_INPUT6 = 0x1A06u, /* tr_group[0].input[6] */ + TRIG10_OUT_TR_GROUP1_INPUT6 = 0x1A06u, /* tr_group[1].input[6] */ + TRIG10_OUT_TR_GROUP2_INPUT6 = 0x1A06u, /* tr_group[2].input[6] */ + TRIG10_OUT_TR_GROUP3_INPUT6 = 0x1A06u, /* tr_group[3].input[6] */ + TRIG10_OUT_TR_GROUP4_INPUT6 = 0x1A06u, /* tr_group[4].input[6] */ + TRIG10_OUT_TR_GROUP5_INPUT6 = 0x1A06u, /* tr_group[5].input[6] */ + TRIG10_OUT_TR_GROUP6_INPUT6 = 0x1A06u, /* tr_group[6].input[6] */ + TRIG10_OUT_TR_GROUP7_INPUT6 = 0x1A06u, /* tr_group[7].input[6] */ + TRIG10_OUT_TR_GROUP8_INPUT6 = 0x1A06u, /* tr_group[8].input[6] */ + TRIG10_OUT_UDB_TR_DW_ACK7 = 0x1A07u, /* udb.tr_dw_ack[7] */ + TRIG10_OUT_TR_GROUP0_INPUT7 = 0x1A07u, /* tr_group[0].input[7] */ + TRIG10_OUT_TR_GROUP1_INPUT7 = 0x1A07u, /* tr_group[1].input[7] */ + TRIG10_OUT_TR_GROUP2_INPUT7 = 0x1A07u, /* tr_group[2].input[7] */ + TRIG10_OUT_TR_GROUP3_INPUT7 = 0x1A07u, /* tr_group[3].input[7] */ + TRIG10_OUT_TR_GROUP4_INPUT7 = 0x1A07u, /* tr_group[4].input[7] */ + TRIG10_OUT_TR_GROUP5_INPUT7 = 0x1A07u, /* tr_group[5].input[7] */ + TRIG10_OUT_TR_GROUP6_INPUT7 = 0x1A07u, /* tr_group[6].input[7] */ + TRIG10_OUT_TR_GROUP7_INPUT7 = 0x1A07u, /* tr_group[7].input[7] */ + TRIG10_OUT_TR_GROUP8_INPUT7 = 0x1A07u /* tr_group[8].input[7] */ +} en_trig_output_grp10_t; + +/* Trigger Output Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */ +typedef enum +{ + TRIG11_OUT_TR_GROUP0_INPUT8 = 0x1B00u, /* tr_group[0].input[8] */ + TRIG11_OUT_TR_GROUP1_INPUT8 = 0x1B00u, /* tr_group[1].input[8] */ + TRIG11_OUT_TR_GROUP2_INPUT8 = 0x1B00u, /* tr_group[2].input[8] */ + TRIG11_OUT_TR_GROUP3_INPUT8 = 0x1B00u, /* tr_group[3].input[8] */ + TRIG11_OUT_TR_GROUP4_INPUT8 = 0x1B00u, /* tr_group[4].input[8] */ + TRIG11_OUT_TR_GROUP5_INPUT8 = 0x1B00u, /* tr_group[5].input[8] */ + TRIG11_OUT_TR_GROUP6_INPUT8 = 0x1B00u, /* tr_group[6].input[8] */ + TRIG11_OUT_TR_GROUP7_INPUT8 = 0x1B00u, /* tr_group[7].input[8] */ + TRIG11_OUT_TR_GROUP8_INPUT8 = 0x1B00u, /* tr_group[8].input[8] */ + TRIG11_OUT_TR_GROUP0_INPUT9 = 0x1B01u, /* tr_group[0].input[9] */ + TRIG11_OUT_TR_GROUP1_INPUT9 = 0x1B01u, /* tr_group[1].input[9] */ + TRIG11_OUT_TR_GROUP2_INPUT9 = 0x1B01u, /* tr_group[2].input[9] */ + TRIG11_OUT_TR_GROUP3_INPUT9 = 0x1B01u, /* tr_group[3].input[9] */ + TRIG11_OUT_TR_GROUP4_INPUT9 = 0x1B01u, /* tr_group[4].input[9] */ + TRIG11_OUT_TR_GROUP5_INPUT9 = 0x1B01u, /* tr_group[5].input[9] */ + TRIG11_OUT_TR_GROUP6_INPUT9 = 0x1B01u, /* tr_group[6].input[9] */ + TRIG11_OUT_TR_GROUP7_INPUT9 = 0x1B01u, /* tr_group[7].input[9] */ + TRIG11_OUT_TR_GROUP8_INPUT9 = 0x1B01u, /* tr_group[8].input[9] */ + TRIG11_OUT_TR_GROUP0_INPUT10 = 0x1B02u, /* tr_group[0].input[10] */ + TRIG11_OUT_TR_GROUP1_INPUT10 = 0x1B02u, /* tr_group[1].input[10] */ + TRIG11_OUT_TR_GROUP2_INPUT10 = 0x1B02u, /* tr_group[2].input[10] */ + TRIG11_OUT_TR_GROUP3_INPUT10 = 0x1B02u, /* tr_group[3].input[10] */ + TRIG11_OUT_TR_GROUP4_INPUT10 = 0x1B02u, /* tr_group[4].input[10] */ + TRIG11_OUT_TR_GROUP5_INPUT10 = 0x1B02u, /* tr_group[5].input[10] */ + TRIG11_OUT_TR_GROUP6_INPUT10 = 0x1B02u, /* tr_group[6].input[10] */ + TRIG11_OUT_TR_GROUP7_INPUT10 = 0x1B02u, /* tr_group[7].input[10] */ + TRIG11_OUT_TR_GROUP8_INPUT10 = 0x1B02u, /* tr_group[8].input[10] */ + TRIG11_OUT_TR_GROUP0_INPUT11 = 0x1B03u, /* tr_group[0].input[11] */ + TRIG11_OUT_TR_GROUP1_INPUT11 = 0x1B03u, /* tr_group[1].input[11] */ + TRIG11_OUT_TR_GROUP2_INPUT11 = 0x1B03u, /* tr_group[2].input[11] */ + TRIG11_OUT_TR_GROUP3_INPUT11 = 0x1B03u, /* tr_group[3].input[11] */ + TRIG11_OUT_TR_GROUP4_INPUT11 = 0x1B03u, /* tr_group[4].input[11] */ + TRIG11_OUT_TR_GROUP5_INPUT11 = 0x1B03u, /* tr_group[5].input[11] */ + TRIG11_OUT_TR_GROUP6_INPUT11 = 0x1B03u, /* tr_group[6].input[11] */ + TRIG11_OUT_TR_GROUP7_INPUT11 = 0x1B03u, /* tr_group[7].input[11] */ + TRIG11_OUT_TR_GROUP8_INPUT11 = 0x1B03u, /* tr_group[8].input[11] */ + TRIG11_OUT_TR_GROUP0_INPUT12 = 0x1B04u, /* tr_group[0].input[12] */ + TRIG11_OUT_TR_GROUP1_INPUT12 = 0x1B04u, /* tr_group[1].input[12] */ + TRIG11_OUT_TR_GROUP2_INPUT12 = 0x1B04u, /* tr_group[2].input[12] */ + TRIG11_OUT_TR_GROUP3_INPUT12 = 0x1B04u, /* tr_group[3].input[12] */ + TRIG11_OUT_TR_GROUP4_INPUT12 = 0x1B04u, /* tr_group[4].input[12] */ + TRIG11_OUT_TR_GROUP5_INPUT12 = 0x1B04u, /* tr_group[5].input[12] */ + TRIG11_OUT_TR_GROUP6_INPUT12 = 0x1B04u, /* tr_group[6].input[12] */ + TRIG11_OUT_TR_GROUP7_INPUT12 = 0x1B04u, /* tr_group[7].input[12] */ + TRIG11_OUT_TR_GROUP8_INPUT12 = 0x1B04u, /* tr_group[8].input[12] */ + TRIG11_OUT_TR_GROUP0_INPUT13 = 0x1B05u, /* tr_group[0].input[13] */ + TRIG11_OUT_TR_GROUP1_INPUT13 = 0x1B05u, /* tr_group[1].input[13] */ + TRIG11_OUT_TR_GROUP2_INPUT13 = 0x1B05u, /* tr_group[2].input[13] */ + TRIG11_OUT_TR_GROUP3_INPUT13 = 0x1B05u, /* tr_group[3].input[13] */ + TRIG11_OUT_TR_GROUP4_INPUT13 = 0x1B05u, /* tr_group[4].input[13] */ + TRIG11_OUT_TR_GROUP5_INPUT13 = 0x1B05u, /* tr_group[5].input[13] */ + TRIG11_OUT_TR_GROUP6_INPUT13 = 0x1B05u, /* tr_group[6].input[13] */ + TRIG11_OUT_TR_GROUP7_INPUT13 = 0x1B05u, /* tr_group[7].input[13] */ + TRIG11_OUT_TR_GROUP8_INPUT13 = 0x1B05u, /* tr_group[8].input[13] */ + TRIG11_OUT_TR_GROUP0_INPUT14 = 0x1B06u, /* tr_group[0].input[14] */ + TRIG11_OUT_TR_GROUP1_INPUT14 = 0x1B06u, /* tr_group[1].input[14] */ + TRIG11_OUT_TR_GROUP2_INPUT14 = 0x1B06u, /* tr_group[2].input[14] */ + TRIG11_OUT_TR_GROUP3_INPUT14 = 0x1B06u, /* tr_group[3].input[14] */ + TRIG11_OUT_TR_GROUP4_INPUT14 = 0x1B06u, /* tr_group[4].input[14] */ + TRIG11_OUT_TR_GROUP5_INPUT14 = 0x1B06u, /* tr_group[5].input[14] */ + TRIG11_OUT_TR_GROUP6_INPUT14 = 0x1B06u, /* tr_group[6].input[14] */ + TRIG11_OUT_TR_GROUP7_INPUT14 = 0x1B06u, /* tr_group[7].input[14] */ + TRIG11_OUT_TR_GROUP8_INPUT14 = 0x1B06u, /* tr_group[8].input[14] */ + TRIG11_OUT_TR_GROUP0_INPUT15 = 0x1B07u, /* tr_group[0].input[15] */ + TRIG11_OUT_TR_GROUP1_INPUT15 = 0x1B07u, /* tr_group[1].input[15] */ + TRIG11_OUT_TR_GROUP2_INPUT15 = 0x1B07u, /* tr_group[2].input[15] */ + TRIG11_OUT_TR_GROUP3_INPUT15 = 0x1B07u, /* tr_group[3].input[15] */ + TRIG11_OUT_TR_GROUP4_INPUT15 = 0x1B07u, /* tr_group[4].input[15] */ + TRIG11_OUT_TR_GROUP5_INPUT15 = 0x1B07u, /* tr_group[5].input[15] */ + TRIG11_OUT_TR_GROUP6_INPUT15 = 0x1B07u, /* tr_group[6].input[15] */ + TRIG11_OUT_TR_GROUP7_INPUT15 = 0x1B07u, /* tr_group[7].input[15] */ + TRIG11_OUT_TR_GROUP8_INPUT15 = 0x1B07u, /* tr_group[8].input[15] */ + TRIG11_OUT_TR_GROUP0_INPUT16 = 0x1B08u, /* tr_group[0].input[16] */ + TRIG11_OUT_TR_GROUP1_INPUT16 = 0x1B08u, /* tr_group[1].input[16] */ + TRIG11_OUT_TR_GROUP2_INPUT16 = 0x1B08u, /* tr_group[2].input[16] */ + TRIG11_OUT_TR_GROUP3_INPUT16 = 0x1B08u, /* tr_group[3].input[16] */ + TRIG11_OUT_TR_GROUP4_INPUT16 = 0x1B08u, /* tr_group[4].input[16] */ + TRIG11_OUT_TR_GROUP5_INPUT16 = 0x1B08u, /* tr_group[5].input[16] */ + TRIG11_OUT_TR_GROUP6_INPUT16 = 0x1B08u, /* tr_group[6].input[16] */ + TRIG11_OUT_TR_GROUP7_INPUT16 = 0x1B08u, /* tr_group[7].input[16] */ + TRIG11_OUT_TR_GROUP8_INPUT16 = 0x1B08u, /* tr_group[8].input[16] */ + TRIG11_OUT_TR_GROUP0_INPUT17 = 0x1B09u, /* tr_group[0].input[17] */ + TRIG11_OUT_TR_GROUP1_INPUT17 = 0x1B09u, /* tr_group[1].input[17] */ + TRIG11_OUT_TR_GROUP2_INPUT17 = 0x1B09u, /* tr_group[2].input[17] */ + TRIG11_OUT_TR_GROUP3_INPUT17 = 0x1B09u, /* tr_group[3].input[17] */ + TRIG11_OUT_TR_GROUP4_INPUT17 = 0x1B09u, /* tr_group[4].input[17] */ + TRIG11_OUT_TR_GROUP5_INPUT17 = 0x1B09u, /* tr_group[5].input[17] */ + TRIG11_OUT_TR_GROUP6_INPUT17 = 0x1B09u, /* tr_group[6].input[17] */ + TRIG11_OUT_TR_GROUP7_INPUT17 = 0x1B09u, /* tr_group[7].input[17] */ + TRIG11_OUT_TR_GROUP8_INPUT17 = 0x1B09u, /* tr_group[8].input[17] */ + TRIG11_OUT_TR_GROUP0_INPUT18 = 0x1B0Au, /* tr_group[0].input[18] */ + TRIG11_OUT_TR_GROUP1_INPUT18 = 0x1B0Au, /* tr_group[1].input[18] */ + TRIG11_OUT_TR_GROUP2_INPUT18 = 0x1B0Au, /* tr_group[2].input[18] */ + TRIG11_OUT_TR_GROUP3_INPUT18 = 0x1B0Au, /* tr_group[3].input[18] */ + TRIG11_OUT_TR_GROUP4_INPUT18 = 0x1B0Au, /* tr_group[4].input[18] */ + TRIG11_OUT_TR_GROUP5_INPUT18 = 0x1B0Au, /* tr_group[5].input[18] */ + TRIG11_OUT_TR_GROUP6_INPUT18 = 0x1B0Au, /* tr_group[6].input[18] */ + TRIG11_OUT_TR_GROUP7_INPUT18 = 0x1B0Au, /* tr_group[7].input[18] */ + TRIG11_OUT_TR_GROUP8_INPUT18 = 0x1B0Au, /* tr_group[8].input[18] */ + TRIG11_OUT_TR_GROUP0_INPUT19 = 0x1B0Bu, /* tr_group[0].input[19] */ + TRIG11_OUT_TR_GROUP1_INPUT19 = 0x1B0Bu, /* tr_group[1].input[19] */ + TRIG11_OUT_TR_GROUP2_INPUT19 = 0x1B0Bu, /* tr_group[2].input[19] */ + TRIG11_OUT_TR_GROUP3_INPUT19 = 0x1B0Bu, /* tr_group[3].input[19] */ + TRIG11_OUT_TR_GROUP4_INPUT19 = 0x1B0Bu, /* tr_group[4].input[19] */ + TRIG11_OUT_TR_GROUP5_INPUT19 = 0x1B0Bu, /* tr_group[5].input[19] */ + TRIG11_OUT_TR_GROUP6_INPUT19 = 0x1B0Bu, /* tr_group[6].input[19] */ + TRIG11_OUT_TR_GROUP7_INPUT19 = 0x1B0Bu, /* tr_group[7].input[19] */ + TRIG11_OUT_TR_GROUP8_INPUT19 = 0x1B0Bu, /* tr_group[8].input[19] */ + TRIG11_OUT_TR_GROUP0_INPUT20 = 0x1B0Cu, /* tr_group[0].input[20] */ + TRIG11_OUT_TR_GROUP1_INPUT20 = 0x1B0Cu, /* tr_group[1].input[20] */ + TRIG11_OUT_TR_GROUP2_INPUT20 = 0x1B0Cu, /* tr_group[2].input[20] */ + TRIG11_OUT_TR_GROUP3_INPUT20 = 0x1B0Cu, /* tr_group[3].input[20] */ + TRIG11_OUT_TR_GROUP4_INPUT20 = 0x1B0Cu, /* tr_group[4].input[20] */ + TRIG11_OUT_TR_GROUP5_INPUT20 = 0x1B0Cu, /* tr_group[5].input[20] */ + TRIG11_OUT_TR_GROUP6_INPUT20 = 0x1B0Cu, /* tr_group[6].input[20] */ + TRIG11_OUT_TR_GROUP7_INPUT20 = 0x1B0Cu, /* tr_group[7].input[20] */ + TRIG11_OUT_TR_GROUP8_INPUT20 = 0x1B0Cu, /* tr_group[8].input[20] */ + TRIG11_OUT_TR_GROUP0_INPUT21 = 0x1B0Du, /* tr_group[0].input[21] */ + TRIG11_OUT_TR_GROUP1_INPUT21 = 0x1B0Du, /* tr_group[1].input[21] */ + TRIG11_OUT_TR_GROUP2_INPUT21 = 0x1B0Du, /* tr_group[2].input[21] */ + TRIG11_OUT_TR_GROUP3_INPUT21 = 0x1B0Du, /* tr_group[3].input[21] */ + TRIG11_OUT_TR_GROUP4_INPUT21 = 0x1B0Du, /* tr_group[4].input[21] */ + TRIG11_OUT_TR_GROUP5_INPUT21 = 0x1B0Du, /* tr_group[5].input[21] */ + TRIG11_OUT_TR_GROUP6_INPUT21 = 0x1B0Du, /* tr_group[6].input[21] */ + TRIG11_OUT_TR_GROUP7_INPUT21 = 0x1B0Du, /* tr_group[7].input[21] */ + TRIG11_OUT_TR_GROUP8_INPUT21 = 0x1B0Du, /* tr_group[8].input[21] */ + TRIG11_OUT_TR_GROUP0_INPUT22 = 0x1B0Eu, /* tr_group[0].input[22] */ + TRIG11_OUT_TR_GROUP1_INPUT22 = 0x1B0Eu, /* tr_group[1].input[22] */ + TRIG11_OUT_TR_GROUP2_INPUT22 = 0x1B0Eu, /* tr_group[2].input[22] */ + TRIG11_OUT_TR_GROUP3_INPUT22 = 0x1B0Eu, /* tr_group[3].input[22] */ + TRIG11_OUT_TR_GROUP4_INPUT22 = 0x1B0Eu, /* tr_group[4].input[22] */ + TRIG11_OUT_TR_GROUP5_INPUT22 = 0x1B0Eu, /* tr_group[5].input[22] */ + TRIG11_OUT_TR_GROUP6_INPUT22 = 0x1B0Eu, /* tr_group[6].input[22] */ + TRIG11_OUT_TR_GROUP7_INPUT22 = 0x1B0Eu, /* tr_group[7].input[22] */ + TRIG11_OUT_TR_GROUP8_INPUT22 = 0x1B0Eu, /* tr_group[8].input[22] */ + TRIG11_OUT_TR_GROUP0_INPUT23 = 0x1B0Fu, /* tr_group[0].input[23] */ + TRIG11_OUT_TR_GROUP1_INPUT23 = 0x1B0Fu, /* tr_group[1].input[23] */ + TRIG11_OUT_TR_GROUP2_INPUT23 = 0x1B0Fu, /* tr_group[2].input[23] */ + TRIG11_OUT_TR_GROUP3_INPUT23 = 0x1B0Fu, /* tr_group[3].input[23] */ + TRIG11_OUT_TR_GROUP4_INPUT23 = 0x1B0Fu, /* tr_group[4].input[23] */ + TRIG11_OUT_TR_GROUP5_INPUT23 = 0x1B0Fu, /* tr_group[5].input[23] */ + TRIG11_OUT_TR_GROUP6_INPUT23 = 0x1B0Fu, /* tr_group[6].input[23] */ + TRIG11_OUT_TR_GROUP7_INPUT23 = 0x1B0Fu, /* tr_group[7].input[23] */ + TRIG11_OUT_TR_GROUP8_INPUT23 = 0x1B0Fu /* tr_group[8].input[23] */ +} en_trig_output_grp11_t; + +/* Trigger Output Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */ +typedef enum +{ + TRIG12_OUT_TR_GROUP2_INPUT24 = 0x1C00u, /* tr_group[2].input[24] */ + TRIG12_OUT_TR_GROUP3_INPUT24 = 0x1C00u, /* tr_group[3].input[24] */ + TRIG12_OUT_TR_GROUP4_INPUT24 = 0x1C00u, /* tr_group[4].input[24] */ + TRIG12_OUT_TR_GROUP5_INPUT24 = 0x1C00u, /* tr_group[5].input[24] */ + TRIG12_OUT_TR_GROUP6_INPUT24 = 0x1C00u, /* tr_group[6].input[24] */ + TRIG12_OUT_TR_GROUP7_INPUT24 = 0x1C00u, /* tr_group[7].input[24] */ + TRIG12_OUT_TR_GROUP8_INPUT24 = 0x1C00u, /* tr_group[8].input[24] */ + TRIG12_OUT_TR_GROUP2_INPUT25 = 0x1C01u, /* tr_group[2].input[25] */ + TRIG12_OUT_TR_GROUP3_INPUT25 = 0x1C01u, /* tr_group[3].input[25] */ + TRIG12_OUT_TR_GROUP4_INPUT25 = 0x1C01u, /* tr_group[4].input[25] */ + TRIG12_OUT_TR_GROUP5_INPUT25 = 0x1C01u, /* tr_group[5].input[25] */ + TRIG12_OUT_TR_GROUP6_INPUT25 = 0x1C01u, /* tr_group[6].input[25] */ + TRIG12_OUT_TR_GROUP7_INPUT25 = 0x1C01u, /* tr_group[7].input[25] */ + TRIG12_OUT_TR_GROUP8_INPUT25 = 0x1C01u, /* tr_group[8].input[25] */ + TRIG12_OUT_TR_GROUP2_INPUT26 = 0x1C02u, /* tr_group[2].input[26] */ + TRIG12_OUT_TR_GROUP3_INPUT26 = 0x1C02u, /* tr_group[3].input[26] */ + TRIG12_OUT_TR_GROUP4_INPUT26 = 0x1C02u, /* tr_group[4].input[26] */ + TRIG12_OUT_TR_GROUP5_INPUT26 = 0x1C02u, /* tr_group[5].input[26] */ + TRIG12_OUT_TR_GROUP6_INPUT26 = 0x1C02u, /* tr_group[6].input[26] */ + TRIG12_OUT_TR_GROUP7_INPUT26 = 0x1C02u, /* tr_group[7].input[26] */ + TRIG12_OUT_TR_GROUP8_INPUT26 = 0x1C02u, /* tr_group[8].input[26] */ + TRIG12_OUT_TR_GROUP2_INPUT27 = 0x1C03u, /* tr_group[2].input[27] */ + TRIG12_OUT_TR_GROUP3_INPUT27 = 0x1C03u, /* tr_group[3].input[27] */ + TRIG12_OUT_TR_GROUP4_INPUT27 = 0x1C03u, /* tr_group[4].input[27] */ + TRIG12_OUT_TR_GROUP5_INPUT27 = 0x1C03u, /* tr_group[5].input[27] */ + TRIG12_OUT_TR_GROUP6_INPUT27 = 0x1C03u, /* tr_group[6].input[27] */ + TRIG12_OUT_TR_GROUP7_INPUT27 = 0x1C03u, /* tr_group[7].input[27] */ + TRIG12_OUT_TR_GROUP8_INPUT27 = 0x1C03u, /* tr_group[8].input[27] */ + TRIG12_OUT_TR_GROUP2_INPUT28 = 0x1C04u, /* tr_group[2].input[28] */ + TRIG12_OUT_TR_GROUP3_INPUT28 = 0x1C04u, /* tr_group[3].input[28] */ + TRIG12_OUT_TR_GROUP4_INPUT28 = 0x1C04u, /* tr_group[4].input[28] */ + TRIG12_OUT_TR_GROUP5_INPUT28 = 0x1C04u, /* tr_group[5].input[28] */ + TRIG12_OUT_TR_GROUP6_INPUT28 = 0x1C04u, /* tr_group[6].input[28] */ + TRIG12_OUT_TR_GROUP7_INPUT28 = 0x1C04u, /* tr_group[7].input[28] */ + TRIG12_OUT_TR_GROUP8_INPUT28 = 0x1C04u, /* tr_group[8].input[28] */ + TRIG12_OUT_TR_GROUP2_INPUT29 = 0x1C05u, /* tr_group[2].input[29] */ + TRIG12_OUT_TR_GROUP3_INPUT29 = 0x1C05u, /* tr_group[3].input[29] */ + TRIG12_OUT_TR_GROUP4_INPUT29 = 0x1C05u, /* tr_group[4].input[29] */ + TRIG12_OUT_TR_GROUP5_INPUT29 = 0x1C05u, /* tr_group[5].input[29] */ + TRIG12_OUT_TR_GROUP6_INPUT29 = 0x1C05u, /* tr_group[6].input[29] */ + TRIG12_OUT_TR_GROUP7_INPUT29 = 0x1C05u, /* tr_group[7].input[29] */ + TRIG12_OUT_TR_GROUP8_INPUT29 = 0x1C05u, /* tr_group[8].input[29] */ + TRIG12_OUT_TR_GROUP2_INPUT30 = 0x1C06u, /* tr_group[2].input[30] */ + TRIG12_OUT_TR_GROUP3_INPUT30 = 0x1C06u, /* tr_group[3].input[30] */ + TRIG12_OUT_TR_GROUP4_INPUT30 = 0x1C06u, /* tr_group[4].input[30] */ + TRIG12_OUT_TR_GROUP5_INPUT30 = 0x1C06u, /* tr_group[5].input[30] */ + TRIG12_OUT_TR_GROUP6_INPUT30 = 0x1C06u, /* tr_group[6].input[30] */ + TRIG12_OUT_TR_GROUP7_INPUT30 = 0x1C06u, /* tr_group[7].input[30] */ + TRIG12_OUT_TR_GROUP8_INPUT30 = 0x1C06u, /* tr_group[8].input[30] */ + TRIG12_OUT_TR_GROUP2_INPUT31 = 0x1C07u, /* tr_group[2].input[31] */ + TRIG12_OUT_TR_GROUP3_INPUT31 = 0x1C07u, /* tr_group[3].input[31] */ + TRIG12_OUT_TR_GROUP4_INPUT31 = 0x1C07u, /* tr_group[4].input[31] */ + TRIG12_OUT_TR_GROUP5_INPUT31 = 0x1C07u, /* tr_group[5].input[31] */ + TRIG12_OUT_TR_GROUP6_INPUT31 = 0x1C07u, /* tr_group[6].input[31] */ + TRIG12_OUT_TR_GROUP7_INPUT31 = 0x1C07u, /* tr_group[7].input[31] */ + TRIG12_OUT_TR_GROUP8_INPUT31 = 0x1C07u, /* tr_group[8].input[31] */ + TRIG12_OUT_TR_GROUP0_INPUT24 = 0x1C08u, /* tr_group[0].input[24] */ + TRIG12_OUT_TR_GROUP1_INPUT24 = 0x1C08u, /* tr_group[1].input[24] */ + TRIG12_OUT_TR_GROUP0_INPUT25 = 0x1C09u, /* tr_group[0].input[25] */ + TRIG12_OUT_TR_GROUP1_INPUT25 = 0x1C09u /* tr_group[1].input[25] */ +} en_trig_output_grp12_t; + +/* Trigger Output Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */ +typedef enum +{ + TRIG13_OUT_TR_GROUP0_INPUT26 = 0x1D00u, /* tr_group[0].input[26] */ + TRIG13_OUT_TR_GROUP1_INPUT26 = 0x1D00u, /* tr_group[1].input[26] */ + TRIG13_OUT_TR_GROUP0_INPUT27 = 0x1D01u, /* tr_group[0].input[27] */ + TRIG13_OUT_TR_GROUP1_INPUT27 = 0x1D01u, /* tr_group[1].input[27] */ + TRIG13_OUT_TR_GROUP0_INPUT28 = 0x1D02u, /* tr_group[0].input[28] */ + TRIG13_OUT_TR_GROUP1_INPUT28 = 0x1D02u, /* tr_group[1].input[28] */ + TRIG13_OUT_TR_GROUP0_INPUT29 = 0x1D03u, /* tr_group[0].input[29] */ + TRIG13_OUT_TR_GROUP1_INPUT29 = 0x1D03u, /* tr_group[1].input[29] */ + TRIG13_OUT_TR_GROUP0_INPUT30 = 0x1D04u, /* tr_group[0].input[30] */ + TRIG13_OUT_TR_GROUP1_INPUT30 = 0x1D04u, /* tr_group[1].input[30] */ + TRIG13_OUT_TR_GROUP0_INPUT31 = 0x1D05u, /* tr_group[0].input[31] */ + TRIG13_OUT_TR_GROUP1_INPUT31 = 0x1D05u, /* tr_group[1].input[31] */ + TRIG13_OUT_TR_GROUP0_INPUT32 = 0x1D06u, /* tr_group[0].input[32] */ + TRIG13_OUT_TR_GROUP1_INPUT32 = 0x1D06u, /* tr_group[1].input[32] */ + TRIG13_OUT_TR_GROUP0_INPUT33 = 0x1D07u, /* tr_group[0].input[33] */ + TRIG13_OUT_TR_GROUP1_INPUT33 = 0x1D07u, /* tr_group[1].input[33] */ + TRIG13_OUT_TR_GROUP0_INPUT34 = 0x1D08u, /* tr_group[0].input[34] */ + TRIG13_OUT_TR_GROUP1_INPUT34 = 0x1D08u, /* tr_group[1].input[34] */ + TRIG13_OUT_TR_GROUP0_INPUT35 = 0x1D09u, /* tr_group[0].input[35] */ + TRIG13_OUT_TR_GROUP1_INPUT35 = 0x1D09u, /* tr_group[1].input[35] */ + TRIG13_OUT_TR_GROUP0_INPUT36 = 0x1D0Au, /* tr_group[0].input[36] */ + TRIG13_OUT_TR_GROUP1_INPUT36 = 0x1D0Au, /* tr_group[1].input[36] */ + TRIG13_OUT_TR_GROUP0_INPUT37 = 0x1D0Bu, /* tr_group[0].input[37] */ + TRIG13_OUT_TR_GROUP1_INPUT37 = 0x1D0Bu, /* tr_group[1].input[37] */ + TRIG13_OUT_TR_GROUP0_INPUT38 = 0x1D0Cu, /* tr_group[0].input[38] */ + TRIG13_OUT_TR_GROUP1_INPUT38 = 0x1D0Cu, /* tr_group[1].input[38] */ + TRIG13_OUT_TR_GROUP0_INPUT39 = 0x1D0Du, /* tr_group[0].input[39] */ + TRIG13_OUT_TR_GROUP1_INPUT39 = 0x1D0Du, /* tr_group[1].input[39] */ + TRIG13_OUT_TR_GROUP0_INPUT40 = 0x1D0Eu, /* tr_group[0].input[40] */ + TRIG13_OUT_TR_GROUP1_INPUT40 = 0x1D0Eu, /* tr_group[1].input[40] */ + TRIG13_OUT_TR_GROUP0_INPUT41 = 0x1D0Fu, /* tr_group[0].input[41] */ + TRIG13_OUT_TR_GROUP1_INPUT41 = 0x1D0Fu, /* tr_group[1].input[41] */ + TRIG13_OUT_TR_GROUP2_INPUT32 = 0x1D10u, /* tr_group[2].input[32] */ + TRIG13_OUT_TR_GROUP3_INPUT32 = 0x1D10u, /* tr_group[3].input[32] */ + TRIG13_OUT_TR_GROUP4_INPUT32 = 0x1D10u, /* tr_group[4].input[32] */ + TRIG13_OUT_TR_GROUP5_INPUT32 = 0x1D10u, /* tr_group[5].input[32] */ + TRIG13_OUT_TR_GROUP6_INPUT32 = 0x1D10u, /* tr_group[6].input[32] */ + TRIG13_OUT_TR_GROUP7_INPUT32 = 0x1D10u, /* tr_group[7].input[32] */ + TRIG13_OUT_TR_GROUP8_INPUT32 = 0x1D10u, /* tr_group[8].input[32] */ + TRIG13_OUT_TR_GROUP2_INPUT33 = 0x1D11u, /* tr_group[2].input[33] */ + TRIG13_OUT_TR_GROUP3_INPUT33 = 0x1D11u, /* tr_group[3].input[33] */ + TRIG13_OUT_TR_GROUP4_INPUT33 = 0x1D11u, /* tr_group[4].input[33] */ + TRIG13_OUT_TR_GROUP5_INPUT33 = 0x1D11u, /* tr_group[5].input[33] */ + TRIG13_OUT_TR_GROUP6_INPUT33 = 0x1D11u, /* tr_group[6].input[33] */ + TRIG13_OUT_TR_GROUP7_INPUT33 = 0x1D11u, /* tr_group[7].input[33] */ + TRIG13_OUT_TR_GROUP8_INPUT33 = 0x1D11u /* tr_group[8].input[33] */ +} en_trig_output_grp13_t; + +/* Trigger Output Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */ +typedef enum +{ + TRIG14_OUT_TR_GROUP0_INPUT42 = 0x1E00u, /* tr_group[0].input[42] */ + TRIG14_OUT_TR_GROUP1_INPUT42 = 0x1E00u, /* tr_group[1].input[42] */ + TRIG14_OUT_TR_GROUP0_INPUT43 = 0x1E01u, /* tr_group[0].input[43] */ + TRIG14_OUT_TR_GROUP1_INPUT43 = 0x1E01u, /* tr_group[1].input[43] */ + TRIG14_OUT_TR_GROUP0_INPUT44 = 0x1E02u, /* tr_group[0].input[44] */ + TRIG14_OUT_TR_GROUP1_INPUT44 = 0x1E02u, /* tr_group[1].input[44] */ + TRIG14_OUT_TR_GROUP0_INPUT45 = 0x1E03u, /* tr_group[0].input[45] */ + TRIG14_OUT_TR_GROUP1_INPUT45 = 0x1E03u, /* tr_group[1].input[45] */ + TRIG14_OUT_TR_GROUP0_INPUT46 = 0x1E04u, /* tr_group[0].input[46] */ + TRIG14_OUT_TR_GROUP1_INPUT46 = 0x1E04u, /* tr_group[1].input[46] */ + TRIG14_OUT_TR_GROUP0_INPUT47 = 0x1E05u, /* tr_group[0].input[47] */ + TRIG14_OUT_TR_GROUP1_INPUT47 = 0x1E05u, /* tr_group[1].input[47] */ + TRIG14_OUT_TR_GROUP0_INPUT48 = 0x1E06u, /* tr_group[0].input[48] */ + TRIG14_OUT_TR_GROUP1_INPUT48 = 0x1E06u, /* tr_group[1].input[48] */ + TRIG14_OUT_TR_GROUP0_INPUT49 = 0x1E07u, /* tr_group[0].input[49] */ + TRIG14_OUT_TR_GROUP1_INPUT49 = 0x1E07u, /* tr_group[1].input[49] */ + TRIG14_OUT_TR_GROUP2_INPUT34 = 0x1E08u, /* tr_group[2].input[34] */ + TRIG14_OUT_TR_GROUP3_INPUT34 = 0x1E08u, /* tr_group[3].input[34] */ + TRIG14_OUT_TR_GROUP4_INPUT34 = 0x1E08u, /* tr_group[4].input[34] */ + TRIG14_OUT_TR_GROUP5_INPUT34 = 0x1E08u, /* tr_group[5].input[34] */ + TRIG14_OUT_TR_GROUP6_INPUT34 = 0x1E08u, /* tr_group[6].input[34] */ + TRIG14_OUT_TR_GROUP7_INPUT34 = 0x1E08u, /* tr_group[7].input[34] */ + TRIG14_OUT_TR_GROUP8_INPUT34 = 0x1E08u, /* tr_group[8].input[34] */ + TRIG14_OUT_TR_GROUP2_INPUT35 = 0x1E09u, /* tr_group[2].input[35] */ + TRIG14_OUT_TR_GROUP3_INPUT35 = 0x1E09u, /* tr_group[3].input[35] */ + TRIG14_OUT_TR_GROUP4_INPUT35 = 0x1E09u, /* tr_group[4].input[35] */ + TRIG14_OUT_TR_GROUP5_INPUT35 = 0x1E09u, /* tr_group[5].input[35] */ + TRIG14_OUT_TR_GROUP6_INPUT35 = 0x1E09u, /* tr_group[6].input[35] */ + TRIG14_OUT_TR_GROUP7_INPUT35 = 0x1E09u, /* tr_group[7].input[35] */ + TRIG14_OUT_TR_GROUP8_INPUT35 = 0x1E09u, /* tr_group[8].input[35] */ + TRIG14_OUT_TR_GROUP2_INPUT36 = 0x1E0Au, /* tr_group[2].input[36] */ + TRIG14_OUT_TR_GROUP3_INPUT36 = 0x1E0Au, /* tr_group[3].input[36] */ + TRIG14_OUT_TR_GROUP4_INPUT36 = 0x1E0Au, /* tr_group[4].input[36] */ + TRIG14_OUT_TR_GROUP5_INPUT36 = 0x1E0Au, /* tr_group[5].input[36] */ + TRIG14_OUT_TR_GROUP6_INPUT36 = 0x1E0Au, /* tr_group[6].input[36] */ + TRIG14_OUT_TR_GROUP7_INPUT36 = 0x1E0Au, /* tr_group[7].input[36] */ + TRIG14_OUT_TR_GROUP8_INPUT36 = 0x1E0Au, /* tr_group[8].input[36] */ + TRIG14_OUT_TR_GROUP2_INPUT37 = 0x1E0Bu, /* tr_group[2].input[37] */ + TRIG14_OUT_TR_GROUP3_INPUT37 = 0x1E0Bu, /* tr_group[3].input[37] */ + TRIG14_OUT_TR_GROUP4_INPUT37 = 0x1E0Bu, /* tr_group[4].input[37] */ + TRIG14_OUT_TR_GROUP5_INPUT37 = 0x1E0Bu, /* tr_group[5].input[37] */ + TRIG14_OUT_TR_GROUP6_INPUT37 = 0x1E0Bu, /* tr_group[6].input[37] */ + TRIG14_OUT_TR_GROUP7_INPUT37 = 0x1E0Bu, /* tr_group[7].input[37] */ + TRIG14_OUT_TR_GROUP8_INPUT37 = 0x1E0Bu, /* tr_group[8].input[37] */ + TRIG14_OUT_TR_GROUP2_INPUT38 = 0x1E0Cu, /* tr_group[2].input[38] */ + TRIG14_OUT_TR_GROUP3_INPUT38 = 0x1E0Cu, /* tr_group[3].input[38] */ + TRIG14_OUT_TR_GROUP4_INPUT38 = 0x1E0Cu, /* tr_group[4].input[38] */ + TRIG14_OUT_TR_GROUP5_INPUT38 = 0x1E0Cu, /* tr_group[5].input[38] */ + TRIG14_OUT_TR_GROUP6_INPUT38 = 0x1E0Cu, /* tr_group[6].input[38] */ + TRIG14_OUT_TR_GROUP7_INPUT38 = 0x1E0Cu, /* tr_group[7].input[38] */ + TRIG14_OUT_TR_GROUP8_INPUT38 = 0x1E0Cu, /* tr_group[8].input[38] */ + TRIG14_OUT_TR_GROUP2_INPUT39 = 0x1E0Du, /* tr_group[2].input[39] */ + TRIG14_OUT_TR_GROUP3_INPUT39 = 0x1E0Du, /* tr_group[3].input[39] */ + TRIG14_OUT_TR_GROUP4_INPUT39 = 0x1E0Du, /* tr_group[4].input[39] */ + TRIG14_OUT_TR_GROUP5_INPUT39 = 0x1E0Du, /* tr_group[5].input[39] */ + TRIG14_OUT_TR_GROUP6_INPUT39 = 0x1E0Du, /* tr_group[6].input[39] */ + TRIG14_OUT_TR_GROUP7_INPUT39 = 0x1E0Du, /* tr_group[7].input[39] */ + TRIG14_OUT_TR_GROUP8_INPUT39 = 0x1E0Du, /* tr_group[8].input[39] */ + TRIG14_OUT_TR_GROUP2_INPUT40 = 0x1E0Eu, /* tr_group[2].input[40] */ + TRIG14_OUT_TR_GROUP3_INPUT40 = 0x1E0Eu, /* tr_group[3].input[40] */ + TRIG14_OUT_TR_GROUP4_INPUT40 = 0x1E0Eu, /* tr_group[4].input[40] */ + TRIG14_OUT_TR_GROUP5_INPUT40 = 0x1E0Eu, /* tr_group[5].input[40] */ + TRIG14_OUT_TR_GROUP6_INPUT40 = 0x1E0Eu, /* tr_group[6].input[40] */ + TRIG14_OUT_TR_GROUP7_INPUT40 = 0x1E0Eu, /* tr_group[7].input[40] */ + TRIG14_OUT_TR_GROUP8_INPUT40 = 0x1E0Eu, /* tr_group[8].input[40] */ + TRIG14_OUT_TR_GROUP2_INPUT41 = 0x1E0Fu, /* tr_group[2].input[41] */ + TRIG14_OUT_TR_GROUP3_INPUT41 = 0x1E0Fu, /* tr_group[3].input[41] */ + TRIG14_OUT_TR_GROUP4_INPUT41 = 0x1E0Fu, /* tr_group[4].input[41] */ + TRIG14_OUT_TR_GROUP5_INPUT41 = 0x1E0Fu, /* tr_group[5].input[41] */ + TRIG14_OUT_TR_GROUP6_INPUT41 = 0x1E0Fu, /* tr_group[6].input[41] */ + TRIG14_OUT_TR_GROUP7_INPUT41 = 0x1E0Fu, /* tr_group[7].input[41] */ + TRIG14_OUT_TR_GROUP8_INPUT41 = 0x1E0Fu /* tr_group[8].input[41] */ +} en_trig_output_grp14_t; + +/* Level or edge detection setting for a trigger mux */ +typedef enum +{ + /* The trigger is a simple level output */ + TRIGGER_TYPE_LEVEL = 0u, + /* The trigger is synchronized to the consumer blocks clock + and a two cycle pulse is generated on this clock */ + TRIGGER_TYPE_EDGE = 1u +} en_trig_type_t; + +/* Trigger Type Defines */ +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE +/* CSD Trigger Types */ +#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +/* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE +/* AUDIOSS Trigger Types */ +#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE +/* UDB Trigger Types */ +#define TRIGGER_TYPE_UDB_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_DW_ACK__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_DW_ACK__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_UDB__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_UDB__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_DSI_OUT_TR__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_DSI_OUT_TR__EDGE TRIGGER_TYPE_EDGE +/* PROFILE Trigger Types */ +#define TRIGGER_TYPE_PROFILE_TR_START TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PROFILE_TR_STOP TRIGGER_TYPE_EDGE +/* TR_GROUP Trigger Types */ +#define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE + +/* Monitor Signal Defines */ +typedef enum +{ + PROFILE_ONE = 0, + CPUSS_MONITOR_CM0 = 1, + CPUSS_MONITOR_CM4 = 2, + CPUSS_MONITOR_FLASH = 3, + CPUSS_MONITOR_DW0_AHB = 4, + CPUSS_MONITOR_DW1_AHB = 5, + CPUSS_MONITOR_CRYPTO = 6, + USB_MONITOR_AHB = 7, + SCB0_MONITOR_AHB = 8, + SCB1_MONITOR_AHB = 9, + SCB2_MONITOR_AHB = 10, + SCB3_MONITOR_AHB = 11, + SCB4_MONITOR_AHB = 12, + SCB5_MONITOR_AHB = 13, + SCB6_MONITOR_AHB = 14, + SCB7_MONITOR_AHB = 15, + SCB8_MONITOR_AHB = 16, + UDB_MONITOR_UDB0 = 17, + UDB_MONITOR_UDB1 = 18, + UDB_MONITOR_UDB2 = 19, + UDB_MONITOR_UDB3 = 20, + SMIF_MONITOR_SMIF_SPI_SELECT0 = 21, + SMIF_MONITOR_SMIF_SPI_SELECT1 = 22, + SMIF_MONITOR_SMIF_SPI_SELECT2 = 23, + SMIF_MONITOR_SMIF_SPI_SELECT3 = 24, + SMIF_MONITOR_SMIF_SPI_SELECT_ANY = 25, + BLESS_EXT_LNA_RX_CTL_OUT = 26, + BLESS_EXT_PA_TX_CTL_OUT = 27 +} en_ep_mon_sel_t; + +/* Total count of Energy Profiler monitor signal connections */ +#define EP_MONITOR_COUNT 28u + +/* Bus masters */ +typedef enum +{ + CPUSS_MS_ID_CM0 = 0, + CPUSS_MS_ID_CRYPTO = 1, + CPUSS_MS_ID_DW0 = 2, + CPUSS_MS_ID_DW1 = 3, + CPUSS_MS_ID_CM4 = 14, + CPUSS_MS_ID_TC = 15 +} en_prot_master_t; + +/* Parameter Defines */ +/* Number of regulator modules instantiated within SRSS */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* SIMO buck core regulator is present. Only compatible with ULP linear + regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 1u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 1u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 3u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 5u +/* Number of PWR_HIB_DATA registers */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 1u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 1u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 2u +/* Alternate high-frequency clock is present. This is used for logic + optimization. */ +#define SRSS_ALTHF_PRESENT 1u +/* Alternate low-frequency clock is present. This is used for logic + optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 8u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 8u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of GPIO ports in range 0..31 */ +#define IOSS_GPIO_GPIO_PORT_NR_0_31 15u +/* Number of GPIO ports in range 32..63 */ +#define IOSS_GPIO_GPIO_PORT_NR_32_63 0u +/* Number of GPIO ports in range 64..95 */ +#define IOSS_GPIO_GPIO_PORT_NR_64_95 0u +/* Number of GPIO ports in range 96..127 */ +#define IOSS_GPIO_GPIO_PORT_NR_96_127 0u +/* Number of ports in device */ +#define IOSS_GPIO_GPIO_PORT_NR 15u +/* Mask of SMARTIO instances presence */ +#define IOSS_SMARTIO_SMARTIO_MASK 768u +/* The number of protection contexts ([2, 16]). */ +#define PERI_PC_NR 8u +/* Master interface presence mask (4 bits) */ +#define PERI_MS_PRESENT 15u +/* Master interface PPU combinatorial (1) or registerd (0) */ +#define PERI_MS_PPU_COMBINATORIAL 1u +/* The number of programmable PPU structures for PERI (all peripherals) */ +#define PERI_MS_PPU_PROG_STRUCT_NR 16u +/* Number of programmable clocks (outputs) */ +#define PERI_CLOCK_NR 59u +/* Number of 8.0 dividers */ +#define PERI_DIV_8_NR 8u +/* Number of 16.0 dividers */ +#define PERI_DIV_16_NR 16u +/* Number of 16.5 (fractional) dividers */ +#define PERI_DIV_16_5_NR 4u +/* Number of 24.5 (fractional) dividers */ +#define PERI_DIV_24_5_NR 1u +/* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ +#define PERI_DIV_ADDR_WIDTH 4u +/* Trigger module present (0=No, 1=Yes) */ +#define PERI_TR 1u +/* Number of trigger groups */ +#define PERI_TR_GROUP_NR 15u +/* The number of protection contexts minus 1 ([1, 15]). */ +#define PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1 7u +/* The number of protection contexts minus 1 ([1, 15]). */ +#define PERI_PPU_PROG_STRUCT_PC_NR_MINUS1 7u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 288u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 9u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 32u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 256u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 16u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 128u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 1024u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 32u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Number of external slaves directly connected to slow AHB-Lite + infrastructure. Maximum nubmer of slave supported is 4. Width of this + parameter is 4-bits. 1-bit mask for each slave indicating present or not. + Example: 4'b0011 - slave 0 and slave 1 are present. Note: The SLOW_SLx_ADDR + and SLOW_SLx_MASK parameters (for the slaves present) should be derived from + the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite + infrastructure. Maximum nubmer of slave supported is 4. Width of this + parameter is 4-bits. 1-bit mask for each slave indicating present or not. + Example: 4'b0011 - slave 0 and slave 1 are present. Note: The FAST_SLx_ADDR + and FAST_SLx_MASK parameters (for the slaves present) should be derived from + the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 0u +/* Number of LF clock (which is connected to clk_lf input of CPUSS) cycles to + make 10ms time period. Example: =327 (or 24'000147) for 32.678 KHz LF clock + from SRSS. */ +#define CPUSS_LF_10MS_TICKS 16777215u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_IRQ_NR 139u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_DPSLP_IRQ_NR 33u +/* Number of DeepSleep wakeup interrupt inputs to CM0+ (product configuration) */ +#define CPUSS_CM0_DPSLP_IRQ_NR 8u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 + for trace level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 16u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 1u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 8u +/* Width of the TPIU interface in bits ([1,32]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 256u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 16u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 16u +/* AES cipher support (0 = no support, 1 = support */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support (0 = no support, 1 = support */ +#define CPUSS_CRYPTO_DES 1u +/* Pseudo random number generation support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA support included */ +#define CPUSS_CRYPTO_SHA 1u +/* SHA1 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA256 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA256 1u +/* SHA512 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA512 1u +/* Cyclic Redundancy Check support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_CRC 1u +/* Vector unit support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_VU 1u +/* True random number generation support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_TR 1u +/* String support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_STR 1u +/* AHB-Lite master interface support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_MASTER_IF 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, + 128, 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 + kB, 8 kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 8u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 8u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 7u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* Number of channels in each DataWire controller (must be the same for now) */ +#define CPUSS_DW_CH_NR 16u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* Number of profiling counters. Legal range [1, 32] */ +#define PROFILE_PRFL_CNT_NR 8u +/* Number of monitor event signals. Legal range [1, 128] */ +#define PROFILE_PRFL_MONITOR_NR 128u +/* Number of UDB Interrupts */ +#define UDB_NUMINT 16u +/* Number of triggers */ +#define UDB_NUMTR 16u +/* Number of UDB array rows (must be multiple of 2) */ +#define UDB_NUMROW 2u +/* Number of UDB array columns */ +#define UDB_NUMCOL 6u +/* DSI on bottom (1) or on bottom and top (2) of UDB array */ +#define UDB_DSISIDES 2u +/* Number of UDBs = NUMROW * NUMCOL */ +#define UDB_NUMUDB 12u +/* Number of UDB pairs = NUMUDB / 2 */ +#define UDB_NUMUDBPAIR 6u +/* Number of DSIs = NUMCOL * DSISIDES */ +#define UDB_NUMDSI 12u +/* Number of quad clocks */ +#define UDB_NUMQCLK 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB0_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB0_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB0_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB0_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB0_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB0_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB0_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB0_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB0_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB0_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB0_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB0_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB0_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB0_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB0_UART 1u +/* UART flow control support? ('0': no, '1': yes) */ +#define SCB0_UART_FLOW 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB0_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB0_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB0_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB0_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB0_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB0_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB0_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB1_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB1_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB1_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB1_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB1_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB1_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB1_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB1_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB1_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB1_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB1_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB1_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB1_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB1_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB1_UART 1u +/* UART flow control support? ('0': no, '1': yes) */ +#define SCB1_UART_FLOW 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB1_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB1_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB1_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB1_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB1_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB1_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB1_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB2_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB2_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB2_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB2_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB2_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB2_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB2_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB2_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB2_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB2_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB2_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB2_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB2_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB2_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB2_UART 1u +/* UART flow control support? ('0': no, '1': yes) */ +#define SCB2_UART_FLOW 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB2_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB2_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB2_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB2_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB2_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB2_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB2_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB3_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB3_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB3_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB3_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB3_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB3_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB3_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB3_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB3_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB3_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB3_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB3_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB3_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB3_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB3_UART 1u +/* UART flow control support? ('0': no, '1': yes) */ +#define SCB3_UART_FLOW 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB3_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB3_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB3_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB3_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB3_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB3_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB3_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB4_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB4_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB4_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB4_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB4_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB4_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB4_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB4_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB4_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB4_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB4_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB4_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB4_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB4_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB4_UART 1u +/* UART flow control support? ('0': no, '1': yes) */ +#define SCB4_UART_FLOW 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB4_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB4_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB4_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB4_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB4_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB4_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB4_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB5_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB5_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB5_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB5_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB5_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB5_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB5_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB5_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB5_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB5_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB5_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB5_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB5_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB5_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB5_UART 1u +/* UART flow control support? ('0': no, '1': yes) */ +#define SCB5_UART_FLOW 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB5_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB5_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB5_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB5_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB5_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB5_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB5_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB6_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB6_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB6_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB6_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB6_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB6_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB6_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB6_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB6_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB6_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB6_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB6_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB6_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB6_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB6_UART 1u +/* UART flow control support? ('0': no, '1': yes) */ +#define SCB6_UART_FLOW 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB6_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB6_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB6_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB6_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB6_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB6_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB6_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB7_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB7_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB7_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB7_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB7_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB7_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB7_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB7_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB7_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB7_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB7_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB7_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB7_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB7_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB7_UART 1u +/* UART flow control support? ('0': no, '1': yes) */ +#define SCB7_UART_FLOW 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB7_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB7_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB7_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB7_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB7_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB7_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB7_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB8_DEEPSLEEP 1u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB8_EC 1u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB8_I2C_M 0u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB8_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB8_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB8_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB8_I2C_EC 1u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB8_I2C_M_S 0u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB8_I2C_S_EC 1u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB8_SPI_M 0u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB8_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB8_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB8_SPI_EC 1u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB8_SPI_S_EC 1u +/* UART support? ('0': no, '1': yes) */ +#define SCB8_UART 0u +/* UART flow control support? ('0': no, '1': yes) */ +#define SCB8_UART_FLOW 0u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB8_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB8_CMD_RESP 1u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB8_EZ 1u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB8_EZ_CMD_RESP 1u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB8_I2C_S_EZ 1u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB8_SPI_S_EZ 1u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB8_I2C_FAST_PLUS 1u +/* Number of counters per IP (1..8) */ +#define TCPWM0_CNT_NR 8u +/* Counter width (in number of bits) */ +#define TCPWM0_CNT_CNT_WIDTH 32u +/* Number of counters per IP (1..8) */ +#define TCPWM1_CNT_NR 24u +/* Counter width (in number of bits) */ +#define TCPWM1_CNT_CNT_WIDTH 16u +/* Max number of LCD commons supported */ +#define LCD_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_PIN_NR 62u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 1u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 1u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 1u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 1u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u +#define PASS_CTBM_CTDAC_PRESENT 1u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]) */ +#define SMIF_MASTER_WIDTH 8u +/* Base address of the SMIF XIP memory region. This address must be a multiple + of the SMIF XIP memory capacity. This address must be a multiple of 64 KB. + This address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP + memory region should NOT overlap with other memory regions. */ +#define SMIF_SMIF_XIP_ADDR 402653184u +/* Capacity of the SMIF XIP memory region. The more significant bits of this + parameter must be '1' and the lesser significant bits of this paramter must + be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are + {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, + 0xffe0:0000, ..., 0xe000:0000}. */ +#define SMIF_SMIF_XIP_MASK 4160749568u +/* Cryptography (AES) support ('0' = no support, '1' = support) */ +#define SMIF_CRYPTO 1u +/* Number of external devices supported ([1,4]) */ +#define SMIF_DEVICE_NR 4u +/* External device write support. This is a 4-bit field. Each external device + has a dedicated bit. E.g., if bit 2 is '1', external device 2 has write + support. */ +#define SMIF_DEVICE_WR_EN 15u +/* AHB bus Master Width */ +#define BLE_BLESS_MASTER_WIDTH 8u +/* I2S capable? (0=No,1=Yes) */ +#define AUDIOSS_I2S 1u +/* PDM capable? (0=No,1=Yes) */ +#define AUDIOSS_PDM 1u + +#endif /* _PSOC6BLE_CONFIG_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/system_psoc6ble_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/system_psoc6ble_cm0plus.c new file mode 100644 index 0000000000..3b8ca3e4e3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/system_psoc6ble_cm0plus.c @@ -0,0 +1,667 @@ +/***************************************************************************//** +* \file system_psoc6ble_cm0plus.c +* \version 1.0 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include +#include "system_psoc6ble_cm0plus.h" +#include "cy_device_headers.h" + +#include "ipc/cy_ipc_drv.h" +#include "ipc/cy_ipc_pipe.h" +#include "ipc/cy_ipc_lock.h" +#include "sysint/cy_sysint.h" + +/******************************************************************************* +* Inter Process Communication (IPC) +*******************************************************************************/ +cy_stc_ipc_pipe_ep_t cy_ipc_pipe_sysEpArray[CPUSS_IPC_IPC_NR]; +uint32_t ipcLockArray[CY_IPC_LOCK_COUNT/CY_IPC_LOCKS_PER_WORD]; +cy_ipc_pipe_callback_ptr_t ipc_pipe_cyPipeCbArray[CY_IPC_CYPIPE_CLIENT_CNT]; + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_HFCLK0_FREQ_HZ_DEFAULT ( 8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT (4000000UL) + + +#define CY_IMO_FREQ_HZ ( 8000000UL) +#ifndef CY_EXT_FREQ_HZ + #define CY_EXT_FREQ_HZ (24000000UL) +#endif +#ifndef CY_ECO_FREQ_HZ + #define CY_ECO_FREQ_HZ (24000000UL) +#endif + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) + #ifndef CY_ALTHF_FREQ_HZ + #define CY_ALTHF_FREQ_HZ (32000000UL) + #endif + uint32_t cy_BleEcoClockFreqHz = CY_ALTHF_FREQ_HZ; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) */ + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#define CY_ROOT_PATH_SRC_ECO (2UL) +#define CY_ROOT_PATH_SRC_ALTHF (3UL) + +/** Holds the SlowClk system core clock, which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure +* the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case the application program is not using +* it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure +* the debugger. */ +uint32_t SystemCoreClock = CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_PERICLK_FREQ_HZ_DEFAULT; + + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT; +uint32_t cy_delayFreqKhz = (CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; +uint8_t cy_delayFreqMhz = (uint8_t)((CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * ((CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD); + + +/******************************************************************************* +* Table Of Content (TOC) +*******************************************************************************/ +typedef struct { + uint32_t securityImageAddr; /** Address of security image */ + uint32_t flashBootAddr; /** Address of Flash Boot stored in SFLASH */ + uint32_t flashBootSize; /** Size of Flash Boot (in bytes) */ + uint32_t objectOneAddr; /** Address of next object (0 if none) */ + uint32_t objectOneSize; /** Size of next object (0 if none) */ + uint32_t objectTwoAddr; /** Address of next object (0 if none) */ + uint32_t objectTwoSize; /** Size of next object (0 if none) */ + uint32_t objectThreeAddr; /** Address of next object (0 if none) */ + uint32_t objectThreeSize; /** Size of next object (0 if none) */ + uint32_t userAppAddr; /** Address of start of User Application */ + uint32_t userAppSize; /** Size of the User Application */ + uint32_t keyStorageAddr; /** Address of Key Storage Flash Blocks. */ + uint32_t keyStorageSize; /** Size of key storage area in bytes. */ + uint32_t smifConfigAddr; /** SMIF Configuration Table */ + uint32_t reserved[113u]; + uint32_t crc; /** 0x1FC CRC16-CCITT */ +} Cy_TOC_Type; + + +#define CY_TOC_BASE (0x100FFE00UL) +#define CY_TOC ((Cy_TOC_Type*) CY_TOC_BASE) + +#ifndef CY_TOC_FLASH_BOOT_ADDR + #define CY_TOC_FLASH_BOOT_ADDR (0x160020D8UL) +#endif + +#ifndef CY_TOC_FLASH_BOOT_SIZE + #define CY_TOC_FLASH_BOOT_SIZE (0x2000UL) +#endif + +#ifndef CY_TOC_SMIF_CONFIG_ADDR + #define CY_TOC_SMIF_CONFIG_ADDR (0xFFFFFFFFUL) +#endif + +#ifndef CY_TOC_USER_APP_ADDR + #define CY_TOC_USER_APP_ADDR (0x10000000UL) +#endif + +#ifndef CY_TOC_USER_APP_SIZE + #define CY_TOC_USER_APP_SIZE (0x80000UL) +#endif + +#ifdef CY_TOC_PRESENT + #if defined(__GNUC__) || defined(__ARMCC_VERSION) + __attribute__ ((__section__(".cy_toc"), used)) + #elif defined(__ICCARM__) + #pragma location=".cy_toc" + #endif + Cy_TOC_Type cyToc = { + .flashBootAddr = CY_TOC_FLASH_BOOT_ADDR, + .flashBootSize = CY_TOC_FLASH_BOOT_SIZE, + .smifConfigAddr = CY_TOC_SMIF_CONFIG_ADDR, + .userAppAddr = CY_TOC_USER_APP_ADDR, + .userAppSize = CY_TOC_USER_APP_SIZE + }; +#endif + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ +#define CY_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u) +#define CY_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u) + +/* CLK_FLL_CONFIG default values, from MXS40-IP-SRSS */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system. +* +*******************************************************************************/ +void SystemInit(void) +{ + /* Restores FLL to default state as it is not restored by ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + + /* Unlock and disable WDT */ + SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_WDT_LOCK_BIT0); + SRSS->WDT_CTL = (SRSS->WDT_CTL | CY_WDT_LOCK_BIT1); + SRSS->WDT_CTL &= (~ (uint32_t) SRSS_WDT_CTL_WDT_EN_Msk); + + + Cy_SystemInit(); + SystemCoreClockUpdate(); + Cy_SystemInitIpc(); + Cy_SMIF_StartupCallBack(); +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: Cy_SMIF_StartupCallBack +****************************************************************************//** +* +* The function is called during device startup. Once SMIF functionality is +* required, user should implement the function as described by the SMIF +* documentation. +* +******************************************************************************/ +__WEAK void Cy_SMIF_StartupCallBack(void) +{ + /* Empty weak function. The actual implementation to be in the user's + * strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Get Core Clock Frequency. +* +* Update \ref SystemCoreClock, \ref cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t slowClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_EXT_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_ECO_FREQ_HZ; + break; + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) */ + + default: + srcFreqHz = CY_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if (rootPath == 1UL) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Slow Clock Divider */ + slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + pathFreqHz = pathFreqHz / periClkDiv; + cy_PeriClkFreqHz = pathFreqHz; + pathFreqHz = pathFreqHz / slowClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitIpcCyPipeIsr +****************************************************************************//** +* +* This is the Interrupt Service Routine for the Cypress Pipe. +* +*******************************************************************************/ +void Cy_SystemInitIpcCyPipeIsr(void) +{ + Cy_IPC_PIPE_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_CYPIPE_ADDR]); +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitIpc +****************************************************************************//** +* +* Performs initial IPC configuration. +* +*******************************************************************************/ +void Cy_SystemInitIpc(void) +{ + cy_stc_sysint_t ipc_intr_cypipeConfig; + + Cy_IPC_PIPE_Config(cy_ipc_pipe_sysEpArray); + + #if (CY_CPU_CORTEX_M0P) + /* Initialize the lock subsystem. Should be called only on one CPU. */ + (void) Cy_IPC_LOCK_Init(CY_IPC_LOCK_COUNT, ipcLockArray); + #endif /* (CY_CPU_CORTEX_M0P) */ + + /* Initialize the pipe endpoints */ + Cy_IPC_PIPE_Init(CY_IPC_EP_CYPIPE_ADDR, ipc_pipe_cyPipeCbArray, CY_IPC_CYPIPE_CLIENT_CNT, CY_IPC_CYPIPE_CONFIG); + + /* Configure interrupts */ + ipc_intr_cypipeConfig.intrSrc = CY_IPC_INTR_CYPIPE_SRC; + ipc_intr_cypipeConfig.intrCm0p = CY_IPC_INTR_CYPIPE_CM0SRC; + ipc_intr_cypipeConfig.intrPriority = CY_IPC_INTR_CYPIPE_PRIO; + + Cy_SysInt_Init(&ipc_intr_cypipeConfig, &Cy_SystemInitIpcCyPipeIsr); + #if (CY_CPU_CORTEX_M0P) + NVIC_EnableIRQ((IRQn_Type)ipc_intr_cypipeConfig.intrCm0p); + #else + NVIC_EnableIRQ((IRQn_Type)ipc_intr_cypipeConfig.intrSrc); + #endif +} + + +/******************************************************************************* +* Function Name: Cy_SysGetCM4Status +****************************************************************************//** +* +* Gets the Cortex-M4 core mode. +* +* \return \ref group_startup_macro +* +*******************************************************************************/ +uint32_t Cy_SysGetCM4Status(void) +{ + uint32_t returnValue; + uint32_t regValue; + + regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_Msk; + switch(regValue) + { + case CPUSS_CM4_PWR_CTL_DISABLED: + returnValue = CY_SYS_CM4_STATUS_DISABLED; + break; + + case CPUSS_CM4_PWR_CTL_RETAINED: + returnValue = CY_SYS_CM4_STATUS_RETAINED; + break; + + case CPUSS_CM4_PWR_CTL_ENABLED: + returnValue = CY_SYS_CM4_STATUS_ENABLED; + break; + + case CPUSS_CM4_PWR_CTL_RESET_MODE: + returnValue = CY_SYS_CM4_STATUS_RESET; + break; + + default: + returnValue = CY_SYS_CM4_STATUS_UNKNOWN; + break; + } + + return (returnValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysEnableCM4 +****************************************************************************//** +* +* Enables the Cortex-M4 core. The CPU is enabled once if it was in the disabled +* or retained mode. If the CPU is enabled, the vector table base address is +* updated and software reset of the Cortex-M4 core is performed. +* +* \param vectorTableOffset The offset of the vector table base address from +* memory address 0x00000000. The offset should be multiple to 1024 bytes. +* +*******************************************************************************/ +void Cy_SysEnableCM4(uint32_t vectorTableOffset) +{ + uint32_t cm4Status; + uint32_t interruptState; + + interruptState = Cy_SaveIRQ(); + cm4Status = Cy_SysGetCM4Status(); + + switch(cm4Status) + { + case CY_SYS_CM4_STATUS_DISABLED: + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_POWER, 1UL); + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_ISOLATE, 1UL); + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); + break; + + case CY_SYS_CM4_STATUS_RETAINED: + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_POWER, 1UL); + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_RETAIN, 1UL); + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_ISOLATE, 1UL); + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); + break; + + case CY_SYS_CM4_STATUS_RESET: + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); + break; + + case CY_SYS_CM4_STATUS_ENABLED: + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + /* Move to Reset from Enabled state */ + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); + + /* Move to Enabled from Reset state */ + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); + break; + + default: + /* Do nothing if Cortex-M4 is already enabled. */ + break; + } + + Cy_RestoreIRQ(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysDisableCM4 +****************************************************************************//** +* +* Disables the Cortex-M4 core. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysDisableCM4(void) +{ + uint32_t cm4Status; + uint32_t interruptState; + + interruptState = Cy_SaveIRQ(); + cm4Status = Cy_SysGetCM4Status(); + + switch(cm4Status) + { + case CY_SYS_CM4_STATUS_ENABLED: + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_ISOLATE, 1UL); + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_POWER, 1UL); + break; + + case CY_SYS_CM4_STATUS_RETAINED: + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_RETAIN, 1UL); + break; + + default: + /* Do nothing if Cortex-M4 is already disabled. */ + break; + } + + Cy_RestoreIRQ(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysRetainCM4 +****************************************************************************//** +* +* Retains the Cortex-M4 core. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysRetainCM4(void) +{ + uint32_t cm4Status; + uint32_t interruptState; + + interruptState = Cy_SaveIRQ(); + cm4Status = Cy_SysGetCM4Status(); + + switch(cm4Status) + { + case CY_SYS_CM4_STATUS_ENABLED: + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_ISOLATE, 1UL); + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_RETAIN, 1UL); + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_POWER, 1UL); + break; + + case CY_SYS_CM4_STATUS_DISABLED: + /* Switch from the DISABLED to the RETAINED state is not valid. + * Do nothing in this case. */ + break; + + default: + /* Do nothing if Cortex-M4 is already in the RETAINED state. */ + break; + } + + Cy_RestoreIRQ(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysResetCM4 +****************************************************************************//** +* +* Resets the Cortex-M4 core. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysResetCM4(void) +{ + uint32_t cm4Status; + uint32_t interruptState; + + interruptState = Cy_SaveIRQ(); + cm4Status = Cy_SysGetCM4Status(); + + switch(cm4Status) + { + case CY_SYS_CM4_STATUS_ENABLED: + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); + break; + + case CY_SYS_CM4_STATUS_DISABLED: + CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_ISOLATE, 1UL); + CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_POWER, 1UL); + break; + + default: + /* Do nothing if Cortex-M4 is already in the RETAINED state. */ + break; + } + + Cy_RestoreIRQ(interruptState); +} + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/system_psoc6ble_cm0plus.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/system_psoc6ble_cm0plus.h new file mode 100644 index 0000000000..5e2c5054c5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/system_psoc6ble_cm0plus.h @@ -0,0 +1,185 @@ +/***************************************************************************//** +* \file system_psoc6ble_cm0plus.h +* \version 1.0 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6BLE_CM0PLUS_H_ +#define _SYSTEM_PSOC6BLE_CM0PLUS_H_ + +#define CY_CM0 ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + +#if (CY_CM0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** startup_m0p driver identifier */ +#define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0Eu) & 0x3FFFu) << 18u)) + + +/******************************************************************************* +* Inter Process Communication (IPC) +*******************************************************************************/ + +#define CY_IPC_CYPIPE_CLIENT_CNT (8u) /* Number of the defined clients */ + +#define CY_IPC_EP_MAX (CPUSS_IPC_IPC_NR) /* Number of IPC structures */ +#define CY_IPC_EP_CYPIPE_CM0_ADDR (0u) +#define CY_IPC_EP_CYPIPE_CM4_ADDR (1u) +#if (CY_CM0) + #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM0_ADDR +#else + #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM4_ADDR +#endif /* (CY_CM0) */ + + +#define CY_IPC_LOCK_COUNT (128u) /* Locks number. Must be a multiple of 32 */ + +/* IPC channels */ +#define CY_IPC_CHAN_SYSCALL_CM0 (0u) /* System calls for the CM0 processor */ +#define CY_IPC_CHAN_SYSCALL_CM4 (1u) /* System calls for the 1st non-CM0 processor */ +#if (CY_CM0) + #define CY_IPC_CHAN_SYSCALL CY_IPC_CHAN_SYSCALL_CM0 +#else + #define CY_IPC_CHAN_SYSCALL CY_IPC_CHAN_SYSCALL_CM4 +#endif /* (CY_CM0) */ +#define CY_IPC_CHAN_SYSCALL_DAP (2u) /* System call */ +#define CY_IPC_CHAN_CRYPTO (3u) /* Crypto functions */ +#define CY_IPC_CHAN_LOCK (4u) /* IPC Locks (System wide) */ +#define CY_IPC_CHAN_CYPIPE_CM0 (5u) /* Cypress Pipe, CM0 side */ +#define CY_IPC_CHAN_CYPIPE_CM4 (6u) /* Cypress Pipe, CM4 side */ + +/* IPC interrupts */ +#define CY_IPC_INTR_SYSCALL_CM0 (0u) +#define CY_IPC_INTR_SYSCALL_CM4 (1u) +#define CY_IPC_INTR_SYSCALL_DAP (2u) +#define CY_IPC_INTR_CRYPTO_M0 (3u) +#define CY_IPC_INTR_CRYPTO_M4 (4u) +#define CY_IPC_INTR_CYPIPE_CM0 (5u) +#define CY_IPC_INTR_CYPIPE_CM4 (6u) + +/* IPC CM0 Interrupts */ +#if (CY_CM0) + #define CY_IPC_INTR_CYPIPE_SRC cpuss_interrupts_ipc5_IRQn + #define CY_IPC_INTR_CYPIPE_CM0SRC NvicMux28 + #define CY_IPC_INTR_CYPIPE_PRIO (1u) +#else + #define CY_IPC_INTR_CYPIPE_SRC cpuss_interrupts_ipc6_IRQn + #define CY_IPC_INTR_CYPIPE_CM0SRC (240u) /* Default value of CM0_INT_CTLx register */ + #define CY_IPC_INTR_CYPIPE_PRIO (1u) +#endif + +/* The System pipe configuration defines the IPC channel number, interrupt number and the pipe interrupt mask */ +#define CY_IPC_CYPIPE_INTR_MASK (uint32_t)((0x0001ul << CY_IPC_CHAN_CYPIPE_CM0) | (0x0001ul << CY_IPC_CHAN_CYPIPE_CM4) ) + +#if (CY_CM0) + #define CY_IPC_CYPIPE_CONFIG (uint32_t)( (CY_IPC_CYPIPE_INTR_MASK << 16) | (CY_IPC_INTR_CYPIPE_CM0 << 8u) | CY_IPC_CHAN_CYPIPE_CM0) +#else + #define CY_IPC_CYPIPE_CONFIG (uint32_t)( (CY_IPC_CYPIPE_INTR_MASK << 16) | (CY_IPC_INTR_CYPIPE_CM4 << 8u) | CY_IPC_CHAN_CYPIPE_CM4) +#endif + + +/** +* \addtogroup group_startup_functions +* \{ +*/ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** \} group_startup_functions */ + + +/** +* \addtogroup group_startup_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_startup_functions */ + + +/** \cond */ +extern void Default_Handler (void); +extern uint32_t Cy_SaveIRQ(void); +extern void Cy_RestoreIRQ(uint32_t saved); + +extern void Cy_SMIF_StartupCallBack(void); +extern void Cy_SystemInit(void); +extern void Cy_SystemInitIpc(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; + +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; +/** \endcond */ + + +/** +* \addtogroup group_startup_macro +* \{ +*/ + +#ifndef CY_CORTEX_M4_APPL_ADDR + /** Start address of the Cortex-M4 application */ + #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) +#endif + +#define CY_SYS_CM4_STATUS_ENABLED (0u) /**< The Cortex-M4 core is enabled. */ +#define CY_SYS_CM4_STATUS_DISABLED (1u) /**< The Cortex-M4 core is disabled. */ +#define CY_SYS_CM4_STATUS_RETAINED (2u) /**< The Cortex-M4 core is retained. */ +#define CY_SYS_CM4_STATUS_UNKNOWN (3u) /**< The Cortex-M4 core is in the unknown state. Invalid state. */ +#define CY_SYS_CM4_STATUS_RESET (4u) /**< The Cortex-M4 core is in the Reset mode. */ +/** \} group_startup_macro */ + + +/** \cond */ + #define CPUSS_CM4_PWR_CTL_Msk (CPUSS_CM4_PWR_CTL_ISOLATE_Msk | \ + CPUSS_CM4_PWR_CTL_RETAIN_Msk | CPUSS_CM4_PWR_CTL_POWER_Msk | \ + CPUSS_CM4_PWR_CTL_RESET_Msk | CPUSS_CM4_PWR_CTL_CLOCK_Msk) + + #define CPUSS_CM4_PWR_CTL_DISABLED (CPUSS_CM4_PWR_CTL_RESET_Msk | CPUSS_CM4_PWR_CTL_ISOLATE_Msk) + #define CPUSS_CM4_PWR_CTL_RETAINED (CPUSS_CM4_PWR_CTL_RETAIN_Msk | CPUSS_CM4_PWR_CTL_ISOLATE_Msk) + #define CPUSS_CM4_PWR_CTL_ENABLED (CPUSS_CM4_PWR_CTL_CLOCK_Msk | CPUSS_CM4_PWR_CTL_POWER_Msk) + #define CPUSS_CM4_PWR_CTL_RESET_MODE (CPUSS_CM4_PWR_CTL_RESET_Msk | CPUSS_CM4_PWR_CTL_POWER_Msk) +/** \endcond */ + + +/** \addtogroup group_startup_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; + +/** \} group_startup_globals */ + +#ifdef __cplusplus +} +#endif + +#endif /* CY_CM0 */ +#endif /* _SYSTEM_PSOC6BLE_CM0PLUS_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cy_crypto_config.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cy_crypto_config.h new file mode 100644 index 0000000000..1de2332e52 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cy_crypto_config.h @@ -0,0 +1,92 @@ +/***************************************************************************//** +* \file cy_crypto_config.h +* \version 1.0 +* +* \brief +* This file provides user parameters for the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CONFIG_H) +#define CY_CRYPTO_CONFIG_H + + +/* Defines to configure interrupts used in Crypto driver */ + +/* Number of Crypto Notify interrupt inputs to CM0+ */ +#define CY_CRYPTO_CM0_NOTIFY_INTR_NR (26u) +/* Priority of Crypto Notify interrupt inputs to CM0+ */ +#define CY_CRYPTO_NOTIFY_INTR_PR (2u) + +/* Number of Crypto release interrupt inputs to CM0+ */ +#define CY_CRYPTO_CM0_RELEASE_INTR_NR (27u) +/* Priority of Crypto release interrupt inputs to CM0+ */ +#define CY_CRYPTO_RELEASE_INTR_PR (2u) + +/* Number of Crypto Error interrupt inputs to CM0+ */ +#define CY_CRYPTO_CM0_ERROR_INTR_NR (28u) +/* Priority of Crypto Error interrupt inputs to CM0+ */ +#define CY_CRYPTO_CM0_ERROR_INTR_PR (2u) + +/* Default Crypto driver configuration */ +#define CY_CRYPTO_DEFAULT_CONFIG \ + { \ + CY_CRYPTO_CM0_NOTIFY_INTR_NR, \ + CY_CRYPTO_NOTIFY_INTR_PR, \ + CY_CRYPTO_CM0_RELEASE_INTR_NR, \ + CY_CRYPTO_RELEASE_INTR_PR, \ + CY_CRYPTO_CM0_ERROR_INTR_NR, \ + CY_CRYPTO_CM0_ERROR_INTR_PR, \ + NULL, \ + NULL, \ + NULL \ + } + +/* Defines to Enable/Disable Crypto functionality */ + +/* AES CMAC support (0 = no support, 1 = support), + * to run CMAC, AES ECB mode should be enabled */ +#define CY_CRYPTO_USER_CMAC (1u) +/* AES ECB cipher support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_AES_ECB (1u) +/* AES CBC cipher support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_AES_CBC (1u) +/* AES CFB cipher support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_AES_CFB (1u) +/* AES CTR cipher support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_AES_CTR (1u) +/* PKCS1-v1_5 verification support (0 = no support, 1 = support), + * to run PKCS1-v1_ at least one of SHA modes should be enabled */ +#define CY_CRYPTO_USER_PKCS1_5 (1u) +/* HMAC support (0 = no support, 1 = support), + * to run HMAC at least one of SHA modes should be enabled */ +#define CY_CRYPTO_USER_HMAC (1u) +/* SHA1 hash support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_SHA1 (1u) +/* SHA 224 and 256 hash support, (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_SHA256 (1u) +/* SHA 384, 512, 512_224 and 512_256 hash support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_SHA512 (1u) +/* (Triple) DES cipher support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_DES (1u) +/* Pseudo random number generation support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_PR (1u) +/* Cyclic Redundancy Check support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_CRC (1u) +/* Vector unit support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_VU (1u) +/* True random number generation support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_TR (1u) +/* String support (0 = no support, 1 = support) */ +#define CY_CRYPTO_USER_STR (1u) + +#endif /* #if !defined(CY_CRYPTO_CONFIG_H) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyapicallbacks.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyapicallbacks.h new file mode 100644 index 0000000000..ff6c7a2d92 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyapicallbacks.h @@ -0,0 +1,28 @@ +/* ======================================== + * + * Copyright YOUR COMPANY, THE YEAR + * All Rights Reserved + * UNPUBLISHED, LICENSED SOFTWARE. + * + * CONFIDENTIAL AND PROPRIETARY INFORMATION + * WHICH IS THE PROPERTY OF your company. + * + * ======================================== +*/ +#ifndef CYAPICALLBACKS_H +#define CYAPICALLBACKS_H + + +#ifdef CPU_CORTEX_M0p + /*Define your Cortex-M0p macro callbacks here */ +#endif + +#ifdef CPU_CORTEX_M4 + /*Define your Cortex-M4 macro callbacks here */ +#endif + + /*For more information, refer to the Writing Code topic in the PSoC Creator Help.*/ + + +#endif /* CYAPICALLBACKS_H */ +/* [] */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cydisabledsheets.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cydisabledsheets.h new file mode 100644 index 0000000000..8178873980 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cydisabledsheets.h @@ -0,0 +1,5 @@ +#ifndef INCLUDED_CYDISABLEDSHEETS_H +#define INCLUDED_CYDISABLEDSHEETS_H + + +#endif /* INCLUDED_CYDISABLEDSHEETS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter.h new file mode 100644 index 0000000000..1a368ea3e4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter.h @@ -0,0 +1,6 @@ +#ifndef INCLUDED_CYFITTER_H +#define INCLUDED_CYFITTER_H + +#include "cy_device_headers.h" + +#endif /* INCLUDED_CYFITTER_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_cfg.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_cfg.c new file mode 100644 index 0000000000..5f575c3a3b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_cfg.c @@ -0,0 +1,271 @@ + +/******************************************************************************* +* File Name: cyfitter_cfg.c +* +* PSoC Creator 4.1 +* +* Description: +* This file contains device initialization code. +* Except for the user defined sections in CyClockStartupError(), this file should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include +#include "cyfitter.h" +#include "gpio/cy_gpio.h" +#include "syslib/cy_syslib.h" +#include "cyfitter_cfg.h" +#include "sysclk/cy_sysclk.h" +#include "systick/cy_systick.h" + +#define CY_NEED_CYCLOCKSTARTUPERROR 1 + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CYALIGNED __attribute__ ((aligned)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + #ifndef CY_CFG_SECTION + #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + #endif + + #if defined(__ARMCC_VERSION) + #define CY_CFG_MEMORY_BARRIER() __memory_changed() + #else + #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() + #endif + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CYALIGNED _Pragma("data_alignment=4") + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") + + #define CY_CFG_MEMORY_BARRIER() __DMB() + +#else + #error Unsupported toolchain +#endif + +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYDATA + #define CYDATA +#endif +#ifndef CYFAR + #define CYFAR +#endif +#ifndef CYXDATA + #define CYXDATA +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + + + + +/* Clock startup error codes */ +#define CYCLOCKSTART_NO_ERROR 0u +#define CYCLOCKSTART_XTAL_ERROR 1u +#define CYCLOCKSTART_32KHZ_ERROR 2u +#define CYCLOCKSTART_PLL_ERROR 3u +#define CYCLOCKSTART_FLL_ERROR 4u + + +#ifdef CY_NEED_CYCLOCKSTARTUPERROR +/******************************************************************************* +* Function Name: CyClockStartupError +******************************************************************************** +* Summary: +* If an error is encountered during clock configuration (crystal startup error, +* PLL lock error, etc.), the system will end up here. Unless reimplemented by +* the customer, this function will stop in an infinite loop. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode); +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode) +{ + /* To remove the compiler warning if errorCode not used. */ + errorCode = errorCode; + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + +#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK + CY_CFG_Clock_Startup_ErrorCallback(); +#else + while(1) {} +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ +} +#endif + +void ClockInit(void); +void ClockInit(void) +{ + uint32_t status; + + /* Enable all source clocks */ + Cy_SysClk_LfClkSetSource(CY_SYSCLK_LFCLK_IN_ILO); + + /* Configure CPU clock dividers */ + Cy_SysClk_FastClkSetDivider(0u); + Cy_SysClk_PeriClkSetDivider(1u); + Cy_SysClk_SlowClkSetDivider(0u); + + /* Configure LF & HF clocks */ + Cy_SysClk_HfClockSetSource(0u, CY_SYSCLK_HFCLK_IN_CLKPATH0); + Cy_SysClk_HfClockSetDivider(0u, CY_SYSCLK_HFCLK_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(0u); + + /* Configure Path Clocks */ + Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkPathSetSource(1, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkPathSetSource(2, CY_SYSCLK_CLKPATH_IN_IMO); + { + const cy_stc_fll_manual_config_t fllConfig = + { + .fllMult = 1825u, + .refDiv = 73u, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 20u, + .igain = 7u, + .pgain = 5u, + .settlingCount = 8u, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO + }; + status = Cy_SysClk_FllManualConfigure(&fllConfig); + if (CY_RET_SUCCESS != status) + { + CyClockStartupError(CYCLOCKSTART_FLL_ERROR); + } + } + status = Cy_SysClk_FllEnable(10000u); + if (CY_RET_SUCCESS != status) + { + CyClockStartupError(CYCLOCKSTART_FLL_ERROR); + } + + /* Configure miscellaneous clocks */ + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); + Cy_SysClk_ClkTimerSetDivider(0); + Cy_SysClk_ClkTimerEnable(); + Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH0); + Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_NO_DIV); + Cy_SysClk_ClkPumpEnable(); + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); + Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF); + Cy_SysClk_IloEnable(); + + /* Set memory wait states based on 100 MHz HFClk[0] */ + Cy_SysLib_SetWaitStates(false, 100); + + /* Configure peripheral clock dividers */ + /* + no Cy_SysClk_Periph* calls + + Each clock is configured in its respective API source file: + * 1M Hz clock (50M/50 Hz) for us_ticker + * oversample*bps Hz clock (50M/(oversample*bps) Hz clock) for serial_api + (depending on the bps) + */ +} + + +/* Analog API Functions */ + + +/******************************************************************************* +* Function Name: AnalogSetDefault +******************************************************************************** +* +* Summary: +* Sets up the analog portions of the chip to default values based on chip +* configuration options from the project. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void AnalogSetDefault(void); +static void AnalogSetDefault(void) +{ +} + +#define CY_AMUX_UNUSED CYREG_CPUSS_CM0_STATUS + + +/******************************************************************************* +* Function Name: Cy_SystemInit +******************************************************************************** +* Summary: +* This function is called by the start-up code for the selected device. It +* performs all of the necessary device configuration based on the design +* settings. This includes settings from the Design Wide Resources (DWR) such +* as Clocks and Pins as well as any component configuration that is necessary. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +void Cy_SystemInit(void) +{ + /* Set worst case memory wait states (150 MHz), ClockInit() will update */ + Cy_SysLib_SetWaitStates(false, 150); + + /* Clock */ + ClockInit(); + + /* Perform basic analog initialization to defaults */ + AnalogSetDefault(); + + __enable_irq(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_cfg.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_cfg.h new file mode 100644 index 0000000000..690718f687 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_cfg.h @@ -0,0 +1,29 @@ +/******************************************************************************* +* File Name: cyfitter_cfg.h +* +* PSoC Creator 4.1 +* +* Description: +* This file provides basic startup and mux configuration settings +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef CYFITTER_CFG_H +#define CYFITTER_CFG_H + + + +extern void Cy_SystemInit(void); + +/* Analog Set/Unset methods */ + + +#endif /* CYFITTER_CFG_H */ + +/*[]*/ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_gpio.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_gpio.h new file mode 100644 index 0000000000..4db0a07429 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cyfitter_gpio.h @@ -0,0 +1,6 @@ +#ifndef INCLUDED_CYFITTER_GPIO_H +#define INCLUDED_CYFITTER_GPIO_H + +#include "cy_device_headers.h" + +#endif /* INCLUDED_CYFITTER_GPIO_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cymetadata.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cymetadata.c new file mode 100644 index 0000000000..e7727ca9c0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/cymetadata.c @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: cymetadata.c +* +* PSoC Creator 4.1 +* +* Description: +* This file defines all extra memory spaces that need to be included. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#include "stdint.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_META_SECTION +#define CY_META_SECTION __attribute__ ((__section__(".cymeta"), used)) +#endif +CY_META_SECTION +#elif defined(__ICCARM__) +#pragma location=".cymeta" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_metadata[] = { + 0x00u, 0x05u, 0xE2u, 0x01u, 0x11u, 0x00u, 0x00u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_CHIP_PROT_SECTION +#define CY_CHIP_PROT_SECTION __attribute__ ((__section__(".cychipprotect"), used)) +#endif +CY_CHIP_PROT_SECTION +#elif defined(__ICCARM__) +#pragma location=".cychipprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_chipprotect[] = { + 0x01u +}; diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto.c new file mode 100644 index 0000000000..4b3bb62b44 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto.c @@ -0,0 +1,1809 @@ +/***************************************************************************//** +* \file cy_crypto.c +* \version 1.0 +* +* \brief +* Provides API implementation of the Cypress PDL Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto.h" +#include "crypto/cy_crypto_common.h" +#include "ipc/cy_ipc_drv.h" +#include "sysint/cy_sysint.h" +#include "syslib/cy_syslib.h" + + +#if (CPUSS_CRYPTO_PRESENT == 1) + + +#if defined(__cplusplus) +extern "C" { +#endif + +/* The function prototypes */ +void Cy_Crypto_Client_ReleaseIntrHndlr(void); +cy_en_crypto_status_t Cy_Crypto_Client_Send(cy_stc_crypto_context_t const *cryptoContext); + + +/* + * The global variable to store a pointer on the customer callback function. + * This variable is global because it is called from an interrupt. + */ +cy_crypto_callback_ptr_t cy_cryptoCompleteCallbackPtr = NULL; + +/******************************************************************************* +* Function Name: Cy_Crypto_Client_ReleaseIntrHndlr +****************************************************************************//** +* +* The interrupt handler for the Crypto IPC Release interrupt; happens +* when Crypto hardware completes operation. This function clears the specific +* interrupt source and calls the customer interrupt handler. +* +*******************************************************************************/ +void Cy_Crypto_Client_ReleaseIntrHndlr(void) +{ + uint32_t interruptMasked; + + interruptMasked = Cy_IPC_DRV_GetIntrStatusMasked(Cy_IPC_DRV_GetIntrBaseAddr(CY_CRYPTO_RELEASE_INTR)); + + /* Check that there is really the IPC Crypto Release interrupt */ + if((1uL << CY_IPC_CHAN_CRYPTO) == (interruptMasked & IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Msk)) + { + Cy_IPC_DRV_ClearIntr(Cy_IPC_DRV_GetIntrBaseAddr(CY_IPC_INTR_CRYPTO_M4), + (interruptMasked & IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Msk), CY_IPC_NO_NOTIFIFICATION); + + if (cy_cryptoCompleteCallbackPtr != NULL) + { + cy_cryptoCompleteCallbackPtr(); + } + } +} + +/******************************************************************************* +* Function Name: Cy_Crypto_IsServerStarted +****************************************************************************//** +* +* Checks if CryptoServer is started. +* +* \return +* True - CryptoServer is started. +* False - CryptoServer is not started. +* +*******************************************************************************/ +bool Cy_Crypto_IsServerStarted(void) +{ + /* Check if the Crypto server started (Crypto IPC Notify interrupt is started) */ + return ((1uL << (CY_IPC_CHAN_CRYPTO + IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Pos)) == + (Cy_IPC_DRV_GetIntrMask(Cy_IPC_DRV_GetIntrBaseAddr(CY_CRYPTO_NOTIFY_INTR)) & IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_IsServerReady +****************************************************************************//** +* +* Checks if CryptoServer is ready for operations. +* +* \return +* True - CryptoServer is ready. +* False - CryptoServer is not ready. +* +*******************************************************************************/ +bool Cy_Crypto_IsServerReady(void) +{ + return (CY_IPC_DRV_LOCKED != Cy_IPC_DRV_GetLockStatus(Cy_IPC_DRV_GetIpcBaseAddress(CY_IPC_CHAN_CRYPTO))); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Sync +****************************************************************************//** +* +* The synchronization function that waits or just checks (depending on the parameter) +* for the Crypto operation to complete. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param isBlocking +* Set whether Crypto_Sync is blocking or not: +* True - is blocking. +* False - is not blocking. +* +* \return +* True - Crypto HW is ready to new task. +* False - Crypto HW is busy. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Sync(cy_stc_crypto_context_t const *cryptoContext, bool isBlocking) +{ + cy_en_crypto_status_t status = CY_CRYPTO_NOT_INITIALIZED; + + if (CY_CRYPTO_INSTR_UNKNOWN != cryptoContext->instr) + { + status = CY_CRYPTO_SERVER_NOT_STARTED; + + /* Check if the Crypto server started (Crypto IPC Notify interrupt is started) */ + if (Cy_Crypto_IsServerStarted()) + { + + if (!isBlocking) + { + status = CY_CRYPTO_SERVER_BUSY; + + if (Cy_Crypto_IsServerReady()) + { + status = cryptoContext->resp; + } + } + else + { + while (!Cy_Crypto_IsServerReady()) + { + } + + status = cryptoContext->resp; + } + } + } + + return (status); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Client_Send +****************************************************************************//** +* +* Sends a pointer to the Crypto Server. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Client_Send(cy_stc_crypto_context_t const *cryptoContext) +{ + cy_en_crypto_status_t status = CY_CRYPTO_SERVER_NOT_STARTED; + + if (Cy_Crypto_IsServerStarted()) + { + status = CY_CRYPTO_SERVER_BUSY; + + if (Cy_Crypto_IsServerReady()) + { + status = CY_CRYPTO_SUCCESS; + + if (CY_IPC_DRV_SUCCESS != Cy_IPC_DRV_SendMsgPtr(Cy_IPC_DRV_GetIpcBaseAddress(CY_IPC_CHAN_CRYPTO), (1uL << CY_IPC_INTR_CRYPTO_M0), cryptoContext)) + { + status = CY_CRYPTO_COMM_FAIL; + } + } + } + + return (status); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_GetErrorStatus +****************************************************************************//** +* +* The function returns a cause of a Crypto hardware error. +* This function is independent of the Crypto previous state. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param hwErrorCause +* \ref cy_stc_crypto_hw_error_t. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_GetErrorStatus(const cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_hw_error_t *hwErrorCause) +{ + if(NULL != hwErrorCause) + { + hwErrorCause->errorStatus0 = cryptoContext->hwErrorStatus.errorStatus0; + hwErrorCause->errorStatus1 = cryptoContext->hwErrorStatus.errorStatus1; + } + + return (cryptoContext->resp); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Init +****************************************************************************//** +* +* Initializes the Crypto context buffer and +* interrupt for the Crypto callback. Must be called at first. +* +* To start working with Crypto methods after Crypto_Init(), +* call Crypto_Enable() to turn-on the Crypto Hardware. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param configStruct +* The pointer to the Crypto configuration structure. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Init(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_config_t const *configStruct) +{ + cy_stc_sysint_t intrCfg; + cy_en_crypto_status_t status = CY_CRYPTO_SERVER_NOT_STARTED; + + /* Release the Crypto IPC channel with the Release interrupt */ + (void)Cy_IPC_DRV_Release(Cy_IPC_DRV_GetIpcBaseAddress(CY_IPC_CHAN_CRYPTO), CY_IPC_NO_NOTIFIFICATION); + + cryptoContext->instr = CY_CRYPTO_INSTR_ENABLE; + + /* Check if the Crypto server started (Crypto IPC Notify interrupt is started) */ + if (Cy_Crypto_IsServerStarted()) + { + /* Set up a Release interrupt if the customer wants */ + if(NULL != configStruct->userCompleteCallback) + { + intrCfg.intrSrc = (IRQn_Type)(cpuss_interrupts_ipc0_IRQn + CY_CRYPTO_RELEASE_INTR); + intrCfg.intrCm0p = (IRQn_CM0P_Type)(configStruct->cm0ReleaseIntrNum); + intrCfg.intrPriority = configStruct->releaseIntrPrior; + Cy_SysInt_Init(&intrCfg, &Cy_Crypto_Client_ReleaseIntrHndlr); + + cy_cryptoCompleteCallbackPtr = configStruct->userCompleteCallback; + + /* Set up the IPC Release interrupt here */ + Cy_IPC_DRV_SetIntrMask(Cy_IPC_DRV_GetIntrBaseAddr(CY_CRYPTO_RELEASE_INTR), (1uL << CY_IPC_CHAN_CRYPTO), CY_IPC_NO_NOTIFIFICATION); + +#if (CY_CPU_CORTEX_M0P) + NVIC_EnableIRQ((IRQn_Type)intrCfg.intrCm0p); +#else + NVIC_EnableIRQ((IRQn_Type)intrCfg.intrSrc); +#endif + } + + status = CY_CRYPTO_SUCCESS; + } + + return(status); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_DeInit +****************************************************************************//** +* +* The function to de-initialize the Crypto driver. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param configStruct +* The pointer to the Crypto configuration structure. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_DeInit(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_config_t const *configStruct) +{ + uint32_t interruptMasked; + cy_en_crypto_status_t err = CY_CRYPTO_SUCCESS; + + cryptoContext->instr = CY_CRYPTO_INSTR_UNKNOWN; + + /* If the release interrupt was enable, disable it here */ + if(NULL != configStruct->userCompleteCallback) + { + /* Disable the Release interrupt from IPC */ +#if (CY_CPU_CORTEX_M0P) + NVIC_DisableIRQ((IRQn_Type)configStruct->cm0ReleaseIntrNum); +#else + NVIC_DisableIRQ((IRQn_Type)(cpuss_interrupts_ipc0_IRQn + CY_IPC_INTR_CRYPTO_M4)); +#endif + /* Reset up the IPC Release interrupt here */ + interruptMasked = Cy_IPC_DRV_GetIntrStatusMasked(Cy_IPC_DRV_GetIntrBaseAddr(CY_CRYPTO_RELEASE_INTR)); + + /* Check that there is really the IPC Crypto Release interrupt */ + if((1uL << CY_IPC_CHAN_CRYPTO) == (interruptMasked & IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk)) + { + Cy_IPC_DRV_ClearIntr(Cy_IPC_DRV_GetIntrBaseAddr(CY_IPC_INTR_CRYPTO_M4), (interruptMasked & IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk), CY_IPC_NO_NOTIFIFICATION); + } + } + + return (err); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Enable +****************************************************************************//** +* +* Enable the Crypo hardware. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Enable(cy_stc_crypto_context_t *cryptoContext) +{ + cy_en_crypto_status_t err; + + cryptoContext->instr = CY_CRYPTO_INSTR_ENABLE; + cryptoContext->xdata = NULL; + + err = Cy_Crypto_Client_Send(cryptoContext); + + /* Wait until initialization completes */ + if (CY_CRYPTO_SUCCESS == err) + { + err = Cy_Crypto_Sync(cryptoContext, CY_CRYPTO_SYNC_BLOCKING); + } + + return (err); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Disable +****************************************************************************//** +* +* Disables the Crypto hardware. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Disable(cy_stc_crypto_context_t *cryptoContext) +{ + cy_en_crypto_status_t err; + + cryptoContext->instr = CY_CRYPTO_INSTR_DISABLE; + cryptoContext->xdata = NULL; + + err = Cy_Crypto_Client_Send(cryptoContext); + + /* Wait until initialization completes */ + if (CY_CRYPTO_SUCCESS == err) + { + err = Cy_Crypto_Sync(cryptoContext, CY_CRYPTO_SYNC_BLOCKING); + } + + return (err); +} + +#if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) +/******************************************************************************* +* Function Name: Cy_Crypto_Prng_Init +****************************************************************************//** +* +* This function initializes parameters of the PRND. +* Resets the pseudo random sequence. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoPrngContext +* The pointer to the \ref cy_stc_crypto_context_prng_t structure which stores +* the Crypto function context. +* +* \param lfsr32InitState +* A non-zero seed value for the first LFSR. + +* \param lfsr31InitState +* A non-zero seed value for the second LFSR. + +* \param lfsr29InitState +* A non-zero seed value for the third LFSR +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Prng_Init(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_prng_t *cryptoPrngContext, + const uint32_t lfsr32InitState, + const uint32_t lfsr31InitState, + const uint32_t lfsr29InitState) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_PRNG_INIT; + cryptoContext->xdata = (void *)cryptoPrngContext; + + cryptoPrngContext->lfsr32InitState = lfsr32InitState; + cryptoPrngContext->lfsr31InitState = lfsr31InitState; + cryptoPrngContext->lfsr29InitState = lfsr29InitState; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Prng_Generate +****************************************************************************//** +* +* Generates the Pseudo Random Number. +* This function is dependent on Cy_Crypto_Prng_Init which should be called before. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoPrngContext +* The pointer to the \ref cy_stc_crypto_context_prng_t structure which stores +* the Crypto function context. +* +* \param max +* The maximum value of a random number. +* +* \param rndNumPtr +* The pointer to a generated pseudo random number. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Prng_Generate(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_prng_t *cryptoPrngContext, + uint32_t const max, + uint32_t *rndNumPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_PRNG; + cryptoContext->xdata = (void *)cryptoPrngContext; + + cryptoPrngContext->max = max; + cryptoPrngContext->prngNumPtr = rndNumPtr; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) */ + +#if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Init +****************************************************************************//** +* +* Initialize the AES operation by setting key and key length. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoAesContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure which stores all internal variables +* the Crypto driver requires. +* +* \param keyPtr +* The pointer to the encryption/decryption key. +* +* \param keyLength +* One of these: CRYPTO_AES_128, CRYPTO_AES_192 or CRYPTO_AES_256. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Init(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + uint32_t *keyPtr, + cy_en_crypto_aes_key_length_t keyLength) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_AES_INIT; + cryptoContext->xdata = cryptoAesContext; + + cryptoAesContext->aesState.keyPtr = keyPtr; + cryptoAesContext->aesState.keyLength = keyLength; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} + +#if (CY_CRYPTO_USER_AES_ECB == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Ecb_Run +****************************************************************************//** +* +* Performs AES operation on one Block. +* This function is dependent from Cy_Crypto_Aes_Init which should be called before. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoAesContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure which stores all internal variables +* the Crypto driver requires. +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT. +* +* \param srcBlockPtr +* The pointer to a source block. +* +* \param dstBlockPtr +* The pointer to a destination cipher block. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Ecb_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t *dstBlockPtr, + uint32_t *srcBlockPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_AES_ECB; + cryptoContext->xdata = cryptoAesContext; + + cryptoAesContext->dirMode = dirMode; + cryptoAesContext->dstPtr = dstBlockPtr; + cryptoAesContext->srcPtr = srcBlockPtr; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if (CY_CRYPTO_USER_AES_ECB == 1) */ + +#if (CY_CRYPTO_USER_AES_CBC == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Cbc_Run +****************************************************************************//** +* +* Performs AES operation on a plain text with Cipher Block Chaining (CBC). +* This function is dependent from Cy_Crypto_Aes_Init which should be called before. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoAesContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure which stores all internal variables +* the Crypto driver requires. +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT. +* +* \param srcSize +* The size of the source plain text. +* +* \param ivPtr +* The pointer to the initial vector. +* +* \param dstPtr +* The pointer to a destination cipher text. +* +* \param srcPtr +* The pointer to a source plain text. Must be 4-Byte aligned! +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Cbc_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t srcSize, + uint32_t *ivPtr, + uint32_t *dstPtr, + uint32_t *srcPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_AES_CBC; + cryptoContext->xdata = cryptoAesContext; + + cryptoAesContext->dirMode = dirMode; + cryptoAesContext->srcSize = srcSize; + cryptoAesContext->ivPtr = ivPtr; + cryptoAesContext->dstPtr = dstPtr; + cryptoAesContext->srcPtr = srcPtr; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if (CY_CRYPTO_USER_AES_CBC == 1) */ + +#if (CY_CRYPTO_USER_AES_CFB == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Cfb_Run +****************************************************************************//** +* +* Performs AES operation on a plain text with Cipher Feedback mode (CFB). +* This function is dependent from Cy_Crypto_Aes_Init +* which should be called before. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoAesContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure which stores all internal variables +* the Crypto driver requires. +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT. +* +* \param srcSize +* The size of the source plain text. +* +* \param ivPtr +* The pointer to the initial vector. +* +* \param dstPtr +* The pointer to a destination cipher text. +* +* \param srcPtr +* The pointer to a source plain text. Must be 4-Byte aligned! +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Cfb_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t srcSize, + uint32_t *ivPtr, + uint32_t *dstPtr, + uint32_t *srcPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_AES_CFB; + cryptoContext->xdata = cryptoAesContext; + + cryptoAesContext->dirMode = dirMode; + cryptoAesContext->srcSize = srcSize; + cryptoAesContext->ivPtr = ivPtr; + cryptoAesContext->dstPtr = dstPtr; + cryptoAesContext->srcPtr = srcPtr; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if (CY_CRYPTO_USER_AES_CFB == 1) */ + +#if (CY_CRYPTO_USER_AES_CTR == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Ctr_Run +****************************************************************************//** +* +* Performs AES operation on a plain text with Cipher Block Counter mode (CTR). +* NOTE: preparation of the unique nonceCounter for each block is +* the user's responsibility. This function is dependent from +* Cy_Crypto_Aes_Init which should be called before. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoAesContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure which stores all internal variables +* the Crypto driver requires. +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT. +* +* \param srcSize +* The size of a source plain text. +* +* \param srcOffset +* The size of an offset within the current block stream for resuming within the current cipher stream. +* +* \param nonceCounter +* The 128-bit nonce and counter. +* +* \param streamBlock +* The saved stream-block for resuming, is over-written by the function. +* +* \param dstPtr +* The pointer to a destination cipher text. +* +* \param srcPtr +* The pointer to a source plain text. Must be 4-Byte aligned! +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Ctr_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t srcSize, + uint32_t *srcOffset, + uint32_t nonceCounter[CY_CRYPTO_AES_BLOCK_SIZE / 8u], + uint32_t streamBlock[CY_CRYPTO_AES_BLOCK_SIZE / 8u], + uint32_t *dstPtr, + uint32_t *srcPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_AES_CTR; + cryptoContext->xdata = cryptoAesContext; + + cryptoAesContext->dirMode = dirMode; + cryptoAesContext->srcSize = srcSize; + cryptoAesContext->srcOffset = srcOffset; + cryptoAesContext->ivPtr = nonceCounter; + cryptoAesContext->streamBlock = streamBlock; + cryptoAesContext->dstPtr = dstPtr; + cryptoAesContext->srcPtr = srcPtr; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if (CY_CRYPTO_USER_AES_CTR == 1) */ + +#if (CY_CRYPTO_USER_CMAC == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Cmac_Run +****************************************************************************//** +* +* Performs the cipher-block chaining-message authentication-code. +* This function is independent of the previous Crypto state. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoAesContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure which stores all internal variables +* the Crypto driver requires. +* +* \param srcPtr +* The pointer to a source plain text. Must be 4-Byte aligned! +* +* \param srcSize +* The size of a source plain text. +* +* \param keyPtr +* The pointer to the encryption key. +* +* \param keyLength +* One of these: \ref cy_en_crypto_aes_key_length_t +* +* \param cmacPtr +* The pointer to the calculated CMAC. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Cmac_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + uint32_t *srcPtr, + uint32_t srcSize, + uint32_t *keyPtr, + cy_en_crypto_aes_key_length_t keyLength, + uint32_t *cmacPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_CMAC; + cryptoContext->xdata = cryptoAesContext; + + cryptoAesContext->srcSize = srcSize; + cryptoAesContext->dstPtr = cmacPtr; + cryptoAesContext->srcPtr = srcPtr; + cryptoAesContext->aesState.keyPtr = keyPtr; + cryptoAesContext->aesState.keyLength = keyLength; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if (CY_CRYPTO_USER_CMAC == 1) */ + +#endif /* #if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) */ + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) +/******************************************************************************* +* Function Name: Cy_Crypto_Sha_Run +****************************************************************************//** +* +* Performs the SHA Hash function. +* This function is independent of the previous Crypto state. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoShaContext +* the pointer to the \ref cy_stc_crypto_context_sha_t structure which stores all internal variables +* for Crypto driver. +* +* \param mode +* One of CRYPTO_SHA256, CRYPTO_SHA1, CRYPTO_SHA256_224, CRYPTO_SHA512, +* CRYPTO_SHA384, CRYPTO_SHA512_224, CRYPTO_SHA512_256. +* +* \param messagePtr +* The pointer to a message whose hash value is being computed. +* +* \param messageSize +* The size of a message. +* +* \param digestPtr +* The pointer to the hash digest . +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Sha_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_sha_t *cryptoShaContext, + uint32_t *messagePtr, + uint32_t messageSize, + uint32_t *digestPtr, + cy_en_crypto_sha_mode_t mode) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_SHA; + cryptoContext->xdata = cryptoShaContext; + + cryptoShaContext->messagePtr = messagePtr; + cryptoShaContext->messageSize = messageSize; + cryptoShaContext->dstPtr = digestPtr; + cryptoShaContext->mode = mode; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) */ + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) +/******************************************************************************* +* Function Name: Cy_Crypto_Hmac_Run +****************************************************************************//** +* +* Performs HMAC calculation. +* This function is independent of the previous Crypto state. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoShaContext +* the pointer to the \ref cy_stc_crypto_context_sha_t structure which stores all internal variables +* for Crypto driver. +* +* \param hmacPtr +* The pointer to the calculated HMAC . +* +* \param messagePtr +* The pointer to a message whose hash value is being computed. +* +* \param messageSize +* The size of a message. +* +* \param keyPtr +* The pointer to the key. +* +* \param keyLength +* The length of the key. +* +* \param mode +* One of these: CRYPTO_SHA256, CRYPTO_SHA1, CRYPTO_SHA256_224, CRYPTO_SHA512, +* CRYPTO_SHA384, CRYPTO_SHA512_224, CRYPTO_SHA512_256. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Hmac_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_sha_t *cryptoShaContext, + uint32_t *hmacPtr, + uint32_t *messagePtr, + uint32_t messageSize, + uint32_t *keyPtr, + uint32_t keyLength, + cy_en_crypto_sha_mode_t mode) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_HMAC; + cryptoContext->xdata = cryptoShaContext; + + cryptoShaContext->messagePtr = messagePtr; + cryptoShaContext->messageSize = messageSize; + cryptoShaContext->dstPtr = hmacPtr; + cryptoShaContext->mode = mode; + cryptoShaContext->keyPtr = keyPtr; + cryptoShaContext->keyLength = keyLength; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) */ + +#if ((CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) +/******************************************************************************* +* Function Name: Cy_Crypto_Str_MemCpy +****************************************************************************//** +* +* Function MemCpy that uses Crypto HW. +* Memory structures should not overlap! +* There is no alignment restriction. +* This function is independent of the previous Crypto state. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoMemContext +* the pointer to the \ref cy_stc_crypto_context_str_t structure which stores all internal variables +* for Crypto driver. +* +* \param dstPtr +* The pointer to the destination of MemCpy. +* +* \param srcPtr +* The pointer to the source of MemCpy. +* +* \param size +* The size in bytes of the copy operation. Maximum size is 65535 Bytes. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Str_MemCpy(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_str_t *cryptoMemContext, + void* dstPtr, + void const *srcPtr, + uint16_t size) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_MEM_CPY; + cryptoContext->xdata = cryptoMemContext; + + cryptoMemContext->dstPtr = dstPtr; + cryptoMemContext->srcPtr0 = srcPtr; + cryptoMemContext->dataSize = size; + + return(Cy_Crypto_Client_Send(cryptoContext)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Str_MemSet +****************************************************************************//** +* +* Function MemSet uses Crypto HW. +* There is no alignment restriction. +* This function is independent from the previous Crypto state. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoMemContext +* the pointer to the \ref cy_stc_crypto_context_str_t structure which stores all internal variables +* for Crypto driver. +* +* \param dstPtr +* The pointer to the destination of MemSet. +* +* \param data +* The value to be set. +* +* \param size +* The size in bytes of the set operation. Maximum size is 65535 Bytes. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Str_MemSet(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_str_t *cryptoMemContext, + void* dstPtr, + uint8_t data, + uint16_t size) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_MEM_SET; + cryptoContext->xdata = cryptoMemContext; + + cryptoMemContext->dstPtr = dstPtr; + cryptoMemContext->data = data; + cryptoMemContext->dataSize = size; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Str_MemCmp +****************************************************************************//** +* +* Function MemCmp uses Crypto HW. +* There is no alignment restriction. +* This function is independent from the previous Crypto state. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoMemContext +* the pointer to the \ref cy_stc_crypto_context_str_t structure which stores all internal variables +* for Crypto driver. +* +* \param src0Ptr +* The pointer to the first source of MemCmp. +* +* \param src1Ptr +* The pointer to the second source of MemCmp. +* +* \param size +* The size in bytes of the compare operation. Maximum size is 65535 Bytes. +* +* \param resultPtr +* The pointer to the result: 0 - if Source 1 = Source 2, 1 - if not. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Str_MemCmp(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_str_t *cryptoMemContext, + void const *src0Ptr, + void const *src1Ptr, + uint16_t size, + uint32_t *resultPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_MEM_CMP; + cryptoContext->xdata = cryptoMemContext; + + cryptoMemContext->srcPtr0 = src0Ptr; + cryptoMemContext->srcPtr1 = src1Ptr; + cryptoMemContext->dataSize = size; + cryptoMemContext->dstPtr = (void* )resultPtr; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} + +/******************************************************************************* +* Function Name: Crypto_Str_MemXor +****************************************************************************//** +* +* Function MemXor uses Crypto HW. +* Memory structures should not overlap! +* There is no alignment restriction. +* This function is independent from the previous Crypto state. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoMemContext +* the pointer to the \ref cy_stc_crypto_context_str_t structure which stores all internal variables +* for Crypto driver. +* +* \param src0Ptr +* The pointer to the first source of MemXor. + +* \param src1Ptr +* The pointer to the second source of MemXor. + +* \param dstPtr +* The pointer to the destination of MemXor. +* +* \param size +* The size in bytes of the compare operation. Maximum size is 65535 Bytes. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Str_MemXor(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_str_t *cryptoMemContext, + void const *src0Ptr, + void const *src1Ptr, + void* dstPtr, + uint16_t size) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_MEM_XOR; + cryptoContext->xdata = cryptoMemContext; + + cryptoMemContext->srcPtr0 = src0Ptr; + cryptoMemContext->srcPtr1 = src1Ptr; + cryptoMemContext->dstPtr = dstPtr; + cryptoMemContext->dataSize = size; + + return(Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if ((CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) */ + +#if ((CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) +/******************************************************************************* +* Function Name: Cy_Crypto_Crc_Init +****************************************************************************//** +* +* Performs CRC initialization. +* The peculiarity of CRC hardware block is that for some polynomials +* calculated CRC is MSB aligned, for another is LSB aligned. +* Here below is the table with knowing polynomials and their +* calculated CRCs from the string "123456789". +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
CRC modes and parameters
NameWidthPolyInitData RevData XORRem RevRem XORExpected CRCOutput of the CRC block
CRC-3 / ROHC30x30x71010x00x60x00000006
CRC-4 / ITU40x30x01010x00x70x00000007
CRC-5 / EPC50x90x90000x00x00x00000000
CRC-5 / ITU50x150x01010x00x70x00000007
CRC-5 / USB50x50x1F1010x1F0x190x00000019
CRC-6 / CDMA2000-A60x270x3F0000x00xD0xD0000000
CRC-6 / CDMA2000-B60x70x3F0000x00x3B0x3B000000
CRC-6 / DARC60x190x01010x00x260x00000026
CRC-6 / ITU60x30x01010x00x60x00000006
CRC-770x90x00000x00x750x75000000
CRC-7 / ROHC70x4F0x7F1010x00x530x00000053
CRC-880x70x00000x00xF40xF4000000
CRC-8 / CDMA200080x9B0xFF0000x00xDA0xDA000000
CRC-8 / DARC80x390x01010x00x150x00000015
CRC-8 / DVB-S280xD50x00000x00xBC0xBC000000
CRC-8 / EBU80x1D0xFF1010x00x970x00000097
CRC-8 / I-CODE80x1D0xFD0000x00x7E0x7E000000
CRC-8 / ITU80x70x00000x550xA10xA1000000
CRC-8 / MAXIM80x310x01010x00xA10x000000A1
CRC-8 / ROHC80x70xFF1010x00xD00x000000D0
CRC-8 / WCDMA80x9B0x01010x00x250x00000025
CRC-10100x2330x00000x00x1990x19900000
CRC-10 / CDMA2000100x3D90x3FF0000x00x2330x23300000
CRC-11110x3850x1A0000x00x5A30x5A300000
CRC-12 / 3GPP120x80F0x00010x00xDAF0x00000DAF
CRC-12 / CDMA2000120xF130xFFF0000x00xD4D0xD4D00000
CRC-12 / DECT120x80F0x00000x00xF5B0xF5B00000
CRC-13 / BBC130x1CF50x00000x00x4FA0x4FA00000
CRC-14 / DARC140x8050x01010x00x82D0x0000082D
CRC-15150x45990x00000x00x59E0x59E00000
CRC-15 / MPT1327150x68150x00000x10x25660x25660000
CRC-24240x0864CFB0x00B704CE0000x00x21CF020x21CF0200
CRC-24 / FLEXRAY-A240x05D6DCB0x00FEDCBA0000x00x7979BD0x7979BD00
CRC-24 / FLEXRAY-B240x05D6DCB0x00ABCDEF0000x00x1F23B80x1F23B800
CRC-31 / PHILIPS310x4C11DB70x7FFFFFFF0000x7FFFFFFF0xCE9E46C0xCE9E46C0
CRC-16 / ARC160x80050x00001010x00000xBB3D0x0000BB3D
CRC-16 / AUG-CCITT160x10210x1D0F0000x00000xE5CC0xE5CC0000
CRC-16 / BUYPASS160x80050x00000000x00000xFEE80xFEE80000
CRC-16 / CCITT-0160x10210xFFFF0000x00000x29B10x29B10000
CRC-16 / CDMA2000160xC8670xFFFF0000x00000x4C060x4C060000
CRC-16 / DDS-110160x80050x800D0000x00000x9ECF0x9ECF0000
CRC-16 / DECT-R160x05890x00000000x00010x007E0x007E0000
CRC-16 / DECT-X160x05890x00000000x00000x007F0x007F0000
CRC-16 / DNP160x3D650x00001010xFFFF0xEA820x0000EA82
CRC-16 / EN-13757160x3D650x00000000xFFFF0xC2B70xC2B70000
CRC-16 / GENIBUS160x10210xFFFF0000xFFFF0xD64E0xD64E0000
CRC-16 / MAXIM160x80050x00001010xFFFF0x44C20x000044C2
CRC-16 / MCRF4XX160x10210xFFFF1010x00000x6F910x00006F91
CRC-16 / RIELLO160x10210xB2AA1010x00000x63D00x000063D0
CRC-16 / T10-DIF160x8BB70x00000000x00000xD0DB0xD0DB0000
CRC-16 / TELEDISK160xA0970x00000000x00000x0FB30x0FB30000
CRC-16 / TMS37157160x10210x89EC1010x00000x26B10x000026B1
CRC-16 / USB160x80050xFFFF1010xFFFF0xB4C80x0000B4C8
CRC-A160x10210xC6C61010x00000xBF050x0000BF05
CRC-16 / KERMIT160x10210x00001010x00000x21890x00002189
CRC-16 / MODBUS160x80050xFFFF1010x00000x4B370x00004B37
CRC-16 / X-25160x10210xFFFF1010xFFFF0x906E0x0000906E
CRC-16 / XMODEM160x10210x00000000x00000x31C30x31C30000
CRC-32320x04C11DB70xFFFFFFFF1010xFFFFFFFF0xCBF439260xCBF43926
CRC-32 / BZIP2320x04C11DB70xFFFFFFFF0000xFFFFFFFF0xFC8919180xFC891918
CRC-32C320x1EDC6F410xFFFFFFFF1010xFFFFFFFF0xE30692830xE3069283
CRC-32D320xA833982B0xFFFFFFFF1010xFFFFFFFF0x873155760x87315576
CRC-32 / MPEG-2320x04C11DB70xFFFFFFFF0000x000000000x0376E6E70x0376E6E7
CRC-32 / POSIX320x04C11DB70x000000000000xFFFFFFFF0x765E76800x765E7680
CRC-32Q320x814141AB0x000000000000x000000000x3010BF7F0x3010BF7F
CRC-32 / JAMCRC320x04C11DB70xFFFFFFFF1010x000000000x340BC6D90x340BC6D9
CRC-32 / XFER320x000000AF0x000000000000x000000000xBD0BE3380xBD0BE338
+* +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoCrcContext +* The pointer to the \ref cy_stc_crypto_context_crc_t structure which stores +* the Crypto driver context. +* +* \param polynomial +* The polynomial (specified using 32 bits) used in the computing CRC. +* +* \param dataReverse +* The order in which data bytes are processed. 0 - MSB first, 1- LSB first. +* +* \param dataXor +* The byte mask for xoring data +* +* \param remReverse +* A reminder reverse: 0 means the remainder is not reversed. 1 means - reversed. +* +* \param remXor +* Specifies a mask with which the LFSR32 register is XORed to produce a remainder. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Crc_Init(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_crc_t *cryptoCrcContext, + uint32_t polynomial, + uint8_t dataReverse, + uint8_t dataXor, + uint8_t remReverse, + uint32_t remXor) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_CRC_INIT; + cryptoContext->xdata = cryptoCrcContext; + + cryptoCrcContext->dataReverse = dataReverse; + cryptoCrcContext->remReverse = remReverse; + cryptoCrcContext->dataXor = dataXor; + cryptoCrcContext->polynomial = polynomial; + cryptoCrcContext->remXor = remXor; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Crc_Run +****************************************************************************//** +* +* Performs CRC calculation on a message. +* This function is dependent from Cy_Crypto_Crc_Init which should be called before. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoCrcContext +* The pointer to the \ref cy_stc_crypto_context_crc_t structure which stores +* the Crypto driver context. +* +* \param dataPtr +* The pointer to the message whose CRC is being computed. +* +* \param dataSize +* The size of a message in bytes. +* +* \param crcPtr +* The pointer to a computed CRC value. +* +* \param lfsrInitState +* The initial state of the LFSR. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Crc_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_crc_t *cryptoCrcContext, + void* dataPtr, + uint16_t dataSize, + uint32_t *crcPtr, + uint32_t lfsrInitState) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_CRC; + cryptoContext->xdata = cryptoCrcContext; + + cryptoCrcContext->lfsrInitState = lfsrInitState; + cryptoCrcContext->srcDataPtr = dataPtr; + cryptoCrcContext->dataSize = dataSize; + cryptoCrcContext->crcPtr = crcPtr; + + return(Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if ((CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) */ + +#if ((CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) +/******************************************************************************* +* Function Name: Cy_Crypto_Trng_Generate +****************************************************************************//** +* +* Generates a True Random Number. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoTrngContext +* The pointer to the \ref cy_stc_crypto_context_trng_t structure which stores +* the Crypto driver context. +* +* \param GAROPol; +* The polynomial for the programmable Galois ring oscillator. +* +* \param FIROPol; +* The polynomial for the programmable Fibonacci ring oscillator. +* +* \param max +* The maximum length of a random number, in the range [0, 32] Bits. +* +* \param rndNumPtr +* the pointer to a generated true random number. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Trng_Generate(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_trng_t *cryptoTrngContext, + uint32_t GAROPol, + uint32_t FIROPol, + uint32_t max, + uint32_t *rndNumPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_TRNG; + cryptoContext->xdata = cryptoTrngContext; + + cryptoTrngContext->GAROPol = GAROPol; + cryptoTrngContext->GAROPol = FIROPol; + cryptoTrngContext->max = max; + cryptoTrngContext->trngNumPtr = rndNumPtr; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if ((CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) */ + +#if ((CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) +/******************************************************************************* +* Function Name: Cy_Crypto_Des_Run +****************************************************************************//** +* +* Performs DES operation on a Single Block. All addresses must be 4-Byte aligned. +* Ciphertext (dstBlockPtr) may overlap with plaintext (srcBlockPtr) +* This function is independent from the previous Crypto state. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoDesContext +* The pointer to the cy_stc_crypto_context_des_t structure which stores +* the Crypto driver context. +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT +* +* \param keyPtr +* The pointer to the encryption/decryption key. +* +* \param srcBlockPtr +* The pointer to a source block. Must be 4-Byte aligned! +* +* \param dstBlockPtr +* The pointer to a destination cipher block. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Des_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_des_t *cryptoDesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t *keyPtr, + uint32_t *dstBlockPtr, + uint32_t *srcBlockPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_DES; + cryptoContext->xdata = cryptoDesContext; + + cryptoDesContext->dirMode = dirMode; + cryptoDesContext->keyPtr = keyPtr; + cryptoDesContext->dstPtr = dstBlockPtr; + cryptoDesContext->srcPtr = srcBlockPtr; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Tdes_Run +****************************************************************************//** +* +* Performs TDES operation on a Single Block. All addresses must be 4-Byte aligned. +* Ciphertext (dstBlockPtr) may overlap with plaintext (srcBlockPtr) +* This function is independent from the previous Crypto state. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoDesContext +* The pointer to the cy_stc_crypto_context_des_t structure which stores +* the Crypto driver context. +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT. +* +* \param keyPtr +* The pointer to the encryption/decryption key. +* +* \param srcBlockPtr +* The pointer to a source block. Must be 4-Byte aligned! +* +* \param dstBlockPtr +* The pointer to a destination cipher block. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Tdes_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_des_t *cryptoDesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t *keyPtr, + uint32_t *dstBlockPtr, + uint32_t *srcBlockPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_3DES; + cryptoContext->xdata = cryptoDesContext; + + cryptoDesContext->dirMode = dirMode; + cryptoDesContext->keyPtr = keyPtr; + cryptoDesContext->dstPtr = dstBlockPtr; + cryptoDesContext->srcPtr = srcBlockPtr; + + return (Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if ((CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) */ + +#if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) +/******************************************************************************* +* Function Name: Cy_Crypto_Rsa_Proc +****************************************************************************//** +* +* Calculates (m^e mod modulo) where m is Message (Signature), e - public exponent +* using a public key in the next representation, it contains: +* modulo, +* public exponent, +* coefficient for Barrett reduction, +* binary inverse of the modulo, +* result of (2^moduloLength mod modulo) +* +* Not all fields in key must be given. Modulo and public exponent is mandatory; +* Barrett coefficient, inverse modulo and r-bar are optional. +* If they don't exists according pointers should be NULL. These coefficients +* could be calculated by \ref Cy_Crypto_Rsa_CalcCoefs. +* Their presence accelerates performance by 5 times. +* +* Returns the processed value and a success value. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoRsaContext +* The pointer to the \ref cy_stc_crypto_context_rsa_t structure which stores +* the RSA context. +* +* \param pubKeyPtr +* The pointer to the \ref cy_stc_crypto_rsa_pub_key_t structure which stores +* public key. +* +* \param messagePtr +* The pointer to the message to be processed. +* +* \param messageLength +* The length of the message to be processed. +* +* \param processedMessagePtr +* The pointer to processed message. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Rsa_Proc(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_rsa_t *cryptoRsaContext, + cy_stc_crypto_rsa_pub_key_t const *pubKeyPtr, + uint32_t const *messageePtr, + uint32_t messageLength, + uint32_t const *processedMessagePtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_RSA_PROC; + cryptoContext->xdata = cryptoRsaContext; + + cryptoRsaContext->keyPtr = (cy_stc_crypto_rsa_pub_key_t*)pubKeyPtr; + cryptoRsaContext->messagePtr = messageePtr; + cryptoRsaContext->messageLength = messageLength; + cryptoRsaContext->resultPtr = processedMessagePtr; + + return(Cy_Crypto_Client_Send(cryptoContext)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Rsa_CalcCoefs +****************************************************************************//** +* +* Calculates constant coefficients (which is dependent only on modulo +* and independent on message). With this pre-calculated coefficients calculations +* speed-up by 5 times. +* +* These coefficients are: +* coefficient for Barrett reduction, +* binary inverse of the modulo, +* result of (2^moduloLength mod modulo) +* +* Calculated coefficients will be placed by addresses provided in +* pubKeyPtr structure for according coefficients. +* Function overwrites previous values. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoRsaContext +* The pointer to the \ref cy_stc_crypto_context_rsa_t structure which stores +* the RSA context. +* +* \param pubKeyPtr +* The pointer to the \ref cy_stc_crypto_rsa_pub_key_t structure which stores +* public key. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Rsa_CalcCoefs(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_rsa_t *cryptoRsaContext, + cy_stc_crypto_rsa_pub_key_t const *pubKeyPtr) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_RSA_COEF; + cryptoContext->xdata = cryptoRsaContext; + + cryptoRsaContext->keyPtr = (cy_stc_crypto_rsa_pub_key_t*)pubKeyPtr; + + return(Cy_Crypto_Client_Send(cryptoContext)); +} +#endif /* #if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +#if (CY_CRYPTO_USER_PKCS1_5 == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Rsa_Verify +****************************************************************************//** +* +* RSA verification with checks for content, paddings and signature format. +* SHA digest of the message and decrypted message should be calculated before. +* Supports only PKCS1-v1_5 format, inside of this format supported padding +* using only SHA, cases with MD2 and MD5 are not supported. +* +* PKCS1-v1_5 described here, page 31: +* http://www.emc.com/collateral/white-papers/h11300-pkcs-1v2-2-rsa-cryptography-standard-wp.pdf +* +* Returns the verification result \ref cy_en_crypto_rsa_ver_result_t. +* +* \param cryptoContext +* The pointer to the \ref cy_stc_crypto_context_t structure which stores +* the Crypto driver common context. +* +* \param cryptoRsaVerContext +* The pointer to the \ref cy_stc_crypto_context_rsa_ver_t structure which stores +* the RSA context. +* +* \param verResult +* The pointer to the verification result \ref cy_en_crypto_rsa_ver_result_t. +* +* \param digestType +* SHA mode used for hash calculation \ref cy_en_crypto_sha_mode_t. +* +* \param digestPtr +* The pointer to the hash of message whose signature to be verified. +* +* \param decryptedSignaturePtr +* The pointer to decrypted signature to be verified. +* +* \param decryptedSignatureLength +* The length of the decrypted signature to be verified, in Bytes +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Rsa_Verify(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_rsa_ver_t *cryptoRsaVerContext, + cy_en_crypto_rsa_ver_result_t *verResult, + cy_en_crypto_sha_mode_t digestType, + uint32_t const *digestPtr, + uint32_t const *decryptedSignaturePtr, + uint32_t decryptedSignatureLength) +{ + cryptoContext->instr = CY_CRYPTO_INSTR_RSA_VER; + cryptoContext->xdata = cryptoRsaVerContext; + + cryptoRsaVerContext->verResult = verResult; + cryptoRsaVerContext->digestType = digestType; + cryptoRsaVerContext->hashPtr = digestPtr; + cryptoRsaVerContext->decryptedSignaturePtr = decryptedSignaturePtr; + cryptoRsaVerContext->decryptedSignatureLength = decryptedSignatureLength; + + return(Cy_Crypto_Client_Send(cryptoContext)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Rsa_InvertEndianness +****************************************************************************//** +* +* Inverts endianness in the memory range, like: +* inArr[0] <---> inArr[n] +* inArr[1] <---> inArr[n-1] +* inArr[2] <---> inArr[n-2] +* ........................ +* inArr[n/2] <---> inArr[n/2-1] +* +* Odd or even byteSize are acceptable. +* +* \param inArrPtr +* The pointer to the memory whose endianness to be inverted. +* +* \param byteSize +* The length of the memory range whose endianness to be inverted, in Bytes +* +*******************************************************************************/ +void Cy_Crypto_Rsa_InvertEndianness(void *inArrPtr, uint32_t byteSize) +{ + int32_t limit; + int32_t i; + int32_t j = 0; + uint8_t temp; + uint8_t *tempPtr = (uint8_t*)inArrPtr; + + if (byteSize > 1u) + { + limit = byteSize / 2u; + if (0u == (byteSize % 2u)) + { + limit -= 1u; + } + + for (i = byteSize - 1u, j = 0u; i > limit; i--, j++) + { + temp = tempPtr[j]; + tempPtr[j] = tempPtr[i]; + tempPtr[i] = temp; + } + } +} + +#endif /* #if (CY_CRYPTO_USER_PKCS1_5 == 1) */ + + +#if defined(__cplusplus) +} +#endif + + +#endif /* #if (CPUSS_CRYPTO_PRESENT == 1) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto.h new file mode 100644 index 0000000000..0430e77d98 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto.h @@ -0,0 +1,450 @@ +/***************************************************************************//** +* \file cy_crypto.h +* \version 1.0 +* +* \brief +* This file provides the public interface for the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +/** +* \defgroup group_crypto Cryptography (Crypto) +* \{ +* The Crypto driver provides an API to perform +* cryptographic operations on user-designated data. +* +* Crypto supports: DES, TDES, AES (128, 192, 256 bits), SHA, CMAC-AES, +* HMAC, PRNG, TRNG, CRC, the utility functions for string management, and +* the accelerator for arithmetic on very large numbers (up to 4096 bits). +* +* Definitions +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
TermDefinition
PlaintextAn unencrypted message
CiphertextAn encrypted message
Block cipherAn encryption function for fixed-size blocks of data. +* This function takes a fixed-size key and a block of plaintext data from +* the message and encrypts it to generate ciphertext. Block ciphers are +* reversible. The function performed on a block of encrypted data will decrypt it.
Block cipher modeA mode of encrypting a message using Block ciphers for messages of arbitrary length. +* The message is padded so that its length is an integer multiple of the block size. +* ECB (Electronic Code Book), CBC (Cipher Block Chaining), and CFB (Cipher Feedback) are all +* modes of using Block ciphers to create an encrypted message of arbitrary length.
Data Encryption Standard (DES)An obsolete Block cipher supported for legacy +* reasons. It uses a 56-bit key and a 64-bit message block size.
Triple DES (3DES or TDES)Uses the DES operation and three DES encryptions in sequence: encrypt +* with DES with one 56-bit key, decrypt with a second 56-bit key, and then encrypt again with either +* the first key or a third 56-bit key. The block size is 64-bits.
Advanced Encryption Standard (AES)This Block cipher replaces DES and 3DES. +* It is the current Block cipher standard. Keys can be 128, 192, or 256 bits +* in length and the message block size is 128 bits. This is the US government standard. +* AES is also used for message authentication.
Cipher-based Message Authentication Code (CMAC)This method uses a key along with the message +* to compute the MAC value using the AES Block Cipher algorithm.
Secure Hash Algorithm (SHA)This function takes a message of the arbitrary length +* and reduces it to a fixed-length residue or message digest after performing a series +* of mathematically defined operations that practically guarantee that any change in +* the message will change the hash value. It is used for message authentication by transmitting +* a message with a hash value appended to it and recalculating the message hash value using +* the same algorithm at the recipient's end. If the hashes differ, then the message is corrupted.
Message Authentication Code (MAC)MACs are used to verify that a received message has not been altered. +* This is done by first computing a MAC value at the sender's end and appending it to the transmitted message. +* When the message is received, the MAC is computed again and checked against the MAC value transmitted with +* the message. If they do not match, the message has been altered. Either a Hash algorithm (such as SHA) +* or a Block Cipher (such as AES) can be used to produce the MAC value. Keyed MAC schemes use a Secret Key +* along with the message, thus the Key value must be known to be able to compute the MAC value.
Hash Message Authentication Code (HMAC)This method uses a Key along with the message to compute +* the MAC value using a Hash algorithm.
Pseudo Random Number Generator (PRNG)Based on Linear Feedback Shift Registers that generate a sequence +* starting from a non-zero seed.
True Random Number Generator (TRNG)A block that generates a number that is statistically random and based +* on some physical random variation. The number cannot be duplicated by running the process again.
Symmetric Key CryptographyUses a common, known key to encrypt and decrypt messages (a shared secret between sender +* and receiver). An efficient method used for encrypting and decrypting messages once the authenticity +* of the other party has been established. DES (now obsolete), 3DES, and AES (currently used) +* are well known symmetric cryptography methods.
Asymmetric Key CryptographyAlso referred to as Public Key encryption. Someone who wishes to receive a message, publishes +* a very large public key (up to 4096 bits currently), which is one of two prime factors of a very large +* number. The other prime factor is the private key of the recipient and a secret. Someone wishing +* to send a message to the publisher of the public key encrypts the message with the public key. This message +* can now be decrypted only with the private key (the other prime factor held secret by the recipient). +* The message is now sent over any channel to the recipient who can decrypt it with the private, secret, key. +* The same process is used to send messages to the sender of the original message. The asymmetric cryptography +* relies on the mathematical impracticality (usually related to the processing power available at any given time) +* of factoring the keys. Common, computationally intensive, asymmetric algorithms are RSA and ECC. +* The public key is described by the pair (n, e) where n is a product of two randomly chosen primes p and q. +* The exponent e is a random integer 1 < e < Q where Q = (p-1) (q-1). The private key d is uniquely +* defined by the integer 1 < d < Q such that ed congruent to 1 (mod Q ).
+* +* \section group_crypto_configuration Configuration Considerations +* +* Crypto has one configuration structure: +* \ref cy_stc_crypto_config_t +* +* \section group_crypto_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* \section group_crypto_changelog Changelog +*
MISRA ruleRule Class (Required/ Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to the void to a pointer to the object type.The cast from the void to pointer and vice versa is used to transmit data via the IPC channel +* by exchanging the pointer. We exchange only one pointer, so there is no way to avoid this cast.
14.4RCast from a pointer to the void to a pointer to the object type.The cast from the void to pointer and vice versa is used to transmit data via the IPC channel +* by exchanging the pointer. We exchange only one pointer, so there is no way to avoid this cast.
16.7RThe object addressed by the pointer parameter '%s' is not modified +* and so the pointer can be of type 'pointer to const'.Data addressed by the pointer is modified by Crypto hardware, out of the compiler scope, so +* it can't be the pointer to const.
+* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \section group_crypto_memory_usage Memory Usage +* +* Flash and RAM memory usage for the Crypto driver is shown in the table below. +* The usage is measured for GCC 5.4.1 in a release build with "-Os" optimization +* for Cortex-M0+ and Cortex-M4 cores. +* +* +* +* +* +* +*
CoreFlash SizeRAM Size
CM0p 4294 5
CM4 692 4
+* +* \defgroup group_crypto_macro Macro +* \defgroup group_crypto_functions Functions +* \defgroup group_crypto_data_structures Data Structures +* \defgroup group_crypto_enums Enumerated Types +* +*/ + +#if !defined(CY_CRYPTO_H) +#define CY_CRYPTO_H + + +#include +#include +#include "cy_device_headers.h" +#include "crypto/cy_crypto_common.h" + +#if (CPUSS_CRYPTO_PRESENT == 1) + + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** +* \addtogroup group_crypto_functions +* \{ +*/ + +cy_en_crypto_status_t Cy_Crypto_Init(cy_stc_crypto_context_t *cryptoContext, cy_stc_crypto_config_t const *configStruct); + +cy_en_crypto_status_t Cy_Crypto_DeInit(cy_stc_crypto_context_t *cryptoContext, cy_stc_crypto_config_t const *configStruct); + +cy_en_crypto_status_t Cy_Crypto_Enable(cy_stc_crypto_context_t *cryptoContext); + +cy_en_crypto_status_t Cy_Crypto_Disable(cy_stc_crypto_context_t *cryptoContext); + +cy_en_crypto_status_t Cy_Crypto_Sync(cy_stc_crypto_context_t const *cryptoContext, bool isBlocking); + +cy_en_crypto_status_t Cy_Crypto_GetErrorStatus(const cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_hw_error_t *hwErrorCause); + +#if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) +cy_en_crypto_status_t Cy_Crypto_Prng_Init(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_prng_t *cryptoPrngContext, + const uint32_t lfsr32InitState, + const uint32_t lfsr31InitState, + const uint32_t lfsr29InitState); + +cy_en_crypto_status_t Cy_Crypto_Prng_Generate(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_prng_t *cryptoPrngContext, + uint32_t const max, + uint32_t *rndNumPtr); +#endif /* #if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) */ + +#if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) +cy_en_crypto_status_t Cy_Crypto_Aes_Init(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + uint32_t *keyPtr, + cy_en_crypto_aes_key_length_t keyLength); + +#if (CY_CRYPTO_USER_AES_ECB == 1) +cy_en_crypto_status_t Cy_Crypto_Aes_Ecb_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t *dstBlockPtr, + uint32_t *srcBlockPtr); +#endif /* #if (CY_CRYPTO_USER_AES_ECB == 1) */ + +#if (CY_CRYPTO_USER_AES_CBC == 1) +cy_en_crypto_status_t Cy_Crypto_Aes_Cbc_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t srcSize, + uint32_t *ivPtr, + uint32_t *dstPtr, + uint32_t *srcPtr); +#endif /* #if (CY_CRYPTO_USER_AES_CBC == 1) */ + +#if (CY_CRYPTO_USER_AES_CFB == 1) +cy_en_crypto_status_t Cy_Crypto_Aes_Cfb_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t srcSize, + uint32_t *ivPtr, + uint32_t *dstPtr, + uint32_t *srcPtr); +#endif /* #if (CY_CRYPTO_USER_AES_CFB == 1) */ + +#if (CY_CRYPTO_USER_AES_CTR == 1) +cy_en_crypto_status_t Cy_Crypto_Aes_Ctr_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t srcSize, + uint32_t *srcOffset, + uint32_t nonceCounter[CY_CRYPTO_AES_BLOCK_SIZE / 8u], + uint32_t streamBlock[CY_CRYPTO_AES_BLOCK_SIZE / 8u], + uint32_t *dstPtr, + uint32_t *srcPtr); +#endif /* #if (CY_CRYPTO_USER_AES_CTR == 1) */ + +#if (CY_CRYPTO_USER_CMAC == 1) +cy_en_crypto_status_t Cy_Crypto_Aes_Cmac_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_aes_t *cryptoAesContext, + uint32_t *srcPtr, + uint32_t srcSize, + uint32_t *keyPtr, + cy_en_crypto_aes_key_length_t keyLength, + uint32_t *cmacPtr); +#endif /* #if (CY_CRYPTO_USER_CMAC == 1) */ +#endif /* #if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) */ + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) +cy_en_crypto_status_t Cy_Crypto_Sha_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_sha_t *cryptoShaContext, + uint32_t *messagePtr, + uint32_t messageSize, + uint32_t *digestPtr, + cy_en_crypto_sha_mode_t mode); +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) */ + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) +cy_en_crypto_status_t Cy_Crypto_Hmac_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_sha_t *cryptoShaContext, + uint32_t *hmacPtr, + uint32_t *messagePtr, + uint32_t messageSize, + uint32_t *keyPtr, + uint32_t keyLength, + cy_en_crypto_sha_mode_t mode); +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) */ + +#if ((CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) +cy_en_crypto_status_t Cy_Crypto_Str_MemCpy(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_str_t *cryptoMemContext, + void *dstPtr, + void const *srcPtr, + uint16_t size); + +cy_en_crypto_status_t Cy_Crypto_Str_MemSet(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_str_t *cryptoMemContext, + void *dstPtr, + uint8_t data, + uint16_t size); + +cy_en_crypto_status_t Cy_Crypto_Str_MemCmp(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_str_t *cryptoMemContext, + void const *src0Ptr, + void const *src1Ptr, + uint16_t size, + uint32_t *resultPtr); + +cy_en_crypto_status_t Cy_Crypto_Str_MemXor(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_str_t *cryptoMemContext, + void const *src0Ptr, + void const *src1Ptr, + void *dstPtr, + uint16_t size); +#endif /* #if ((CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) */ + +#if ((CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) +cy_en_crypto_status_t Cy_Crypto_Crc_Init(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_crc_t *cryptoCrcContext, + uint32_t polynomial, + uint8_t dataReverse, + uint8_t dataXor, + uint8_t remReverse, + uint32_t remXor); + +cy_en_crypto_status_t Cy_Crypto_Crc_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_crc_t *cryptoCrcContext, + void *dataPtr, + uint16_t dataSize, + uint32_t *crcPtr, + uint32_t lfsrInitState); +#endif /* #if ((CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) */ + +#if ((CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) +cy_en_crypto_status_t Cy_Crypto_Trng_Generate(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_trng_t *cryptoTrngContext, + uint32_t GAROPol, + uint32_t FIROPol, + uint32_t max, + uint32_t *rndNumPtr); +#endif /* #if ((CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) */ + +#if ((CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) +cy_en_crypto_status_t Cy_Crypto_Des_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_des_t *cryptoDesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t *keyPtr, + uint32_t *dstBlockPtr, + uint32_t *srcBlockPtr); + +cy_en_crypto_status_t Cy_Crypto_Tdes_Run(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_des_t *cryptoDesContext, + cy_en_crypto_dir_mode_t dirMode, + uint32_t *keyPtr, + uint32_t *dstBlockPtr, + uint32_t *srcBlockPtr); +#endif /* #if ((CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) */ + +#if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) +cy_en_crypto_status_t Cy_Crypto_Rsa_Proc(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_rsa_t *cryptoRsaContext, + cy_stc_crypto_rsa_pub_key_t const *pubKeyPtr, + uint32_t const *messageePtr, + uint32_t messageLength, + uint32_t const *processedMessagePtr); + +cy_en_crypto_status_t Cy_Crypto_Rsa_CalcCoefs(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_rsa_t *cryptoRsaContext, + cy_stc_crypto_rsa_pub_key_t const *pubKeyPtr); +#endif /* #if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +#if (CY_CRYPTO_USER_PKCS1_5 == 1) +cy_en_crypto_status_t Cy_Crypto_Rsa_Verify(cy_stc_crypto_context_t *cryptoContext, + cy_stc_crypto_context_rsa_ver_t *cryptoRsaVerContext, + cy_en_crypto_rsa_ver_result_t *verResult, + cy_en_crypto_sha_mode_t digestType, + uint32_t const *digestPtr, + uint32_t const *decryptedSignaturePtr, + uint32_t decryptedSignatureLength); + +void Cy_Crypto_Rsa_InvertEndianness(void *inArrPtr, uint32_t byteSize); +#endif /* #if (CY_CRYPTO_USER_PKCS1_5 == 1) */ + + +/** \} group_crypto_functions */ + + +#if defined(__cplusplus) +} +#endif + +#endif /* #if (CPUSS_CRYPTO_PRESENT == 1) */ + +#endif /* (CY_CRYPTO_H) */ + +/** \} group_crypto */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_common.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_common.h new file mode 100644 index 0000000000..2934a27a92 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_common.h @@ -0,0 +1,504 @@ +/***************************************************************************//** +* \file cy_crypto_common.h +* \version 1.0 +* +* \brief +* This file provides common constants and parameters +* for the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_CRYPTO_COMMON_H) +#define CY_CRYPTO_COMMON_H + +#include +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" +#include "cy_crypto_config.h" + +#if (CPUSS_CRYPTO_PRESENT == 1) + +/** +* \addtogroup group_crypto_macro +* \{ +*/ + +/** Driver major version */ +#define CY_CRYPTO_DRV_VERSION_MAJOR (1) + +/** Driver minor version */ +#define CY_CRYPTO_DRV_VERSION_MINOR (0) + +/** Defines Crypto_Sync blocking execution type parameter */ +#define CY_CRYPTO_SYNC_BLOCKING (true) + +/** Defines Crypto_Sync non-blocking execution type parameter */ +#define CY_CRYPTO_SYNC_NON_BLOCKING (false) + +/** Defines the Crypto DES key size (in bytes) */ +#define CY_CRYPTO_DES_KEY_SIZE (8u) + +/** Defines the Crypto TDES key size (in bytes) */ +#define CY_CRYPTO_TDES_KEY_SIZE (24u) + +/** Defines the Crypto AES block size (in bytes) */ +#define CY_CRYPTO_AES_BLOCK_SIZE (16u) + +/** Defines the Crypto AES key maximum size (in bytes) */ +#define CY_CRYPTO_AES_128_KEY_SIZE (16u) + +/** Defines the Crypto AES key maximum size (in bytes) */ +#define CY_CRYPTO_AES_192_KEY_SIZE (24u) + +/** Defines the Crypto AES key maximum size (in bytes) */ +#define CY_CRYPTO_AES_256_KEY_SIZE (32u) + +/** Defines size of the AES block, in four byte words */ +#define CY_CRYPTO_AES_BLOCK_SIZE_U32 (4UL) + +/** Defines the Crypto notify interrupt number */ +#define CY_CRYPTO_NOTIFY_INTR CY_IPC_INTR_CRYPTO_M0 + +/* Overall AES enable */ +#define CY_CRYPTO_USER_AES_ENABLE (CY_CRYPTO_USER_AES_ECB | \ + CY_CRYPTO_USER_AES_CBC | \ + CY_CRYPTO_USER_AES_CFB | \ + CY_CRYPTO_USER_AES_CTR | \ + CY_CRYPTO_USER_CMAC) + +/* Overall SHA enable */ +#define CY_CRYPTO_USER_SHA_ENABLE (CY_CRYPTO_USER_SHA1 | \ + CY_CRYPTO_USER_SHA256 | \ + CY_CRYPTO_USER_SHA512 | \ + CY_CRYPTO_USER_HMAC) + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) + +/** Hash size for the SHA1 mode, in Bytes */ +#define CY_CRYPTO_SHA1_DIGEST_SIZE (20u) +/** Hash size for the SHA224 mode, in Bytes */ +#define CY_CRYPTO_SHA224_DIGEST_SIZE (28u) +/** Hash size for the SHA256 mode, in Bytes */ +#define CY_CRYPTO_SHA256_DIGEST_SIZE (32u) +/** Hash size for the SHA384 mode, in Bytes */ +#define CY_CRYPTO_SHA384_DIGEST_SIZE (48u) +/** Hash size for the SHA512 mode, in Bytes */ +#define CY_CRYPTO_SHA512_DIGEST_SIZE (64u) +/** Hash size for the SHA512_224 mode, in Bytes */ +#define CY_CRYPTO_SHA512_224_DIGEST_SIZE (28u) +/** Hash size for the SHA512_256 mode, in Bytes */ +#define CY_CRYPTO_SHA512_256_DIGEST_SIZE (32u) + +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) */ + + +#if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) + +/** Processed message size for the RSA 1024Bit mode, in Bytes */ +#define CY_CRYPTO_RSA1024_MESSAGE_SIZE (128) +/** Processed message size for the RSA 1536Bit mode, in Bytes */ +#define CY_CRYPTO_RSA1536_MESSAGE_SIZE (192) +/** Processed message size for the RSA 2048Bit mode, in Bytes */ +#define CY_CRYPTO_RSA2048_MESSAGE_SIZE (256) + +#endif /* #if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +/** Defines the Crypto release interrupt number */ +#define CY_CRYPTO_RELEASE_INTR CY_IPC_INTR_CRYPTO_M4 + +/** Crypto Driver PDL ID */ +#define CY_CRYPTO_ID CY_PDL_DRV_ID(0x0Cu) + +/** \} group_crypto_macro */ + +/** +* \addtogroup group_crypto_data_structures +* \{ +*/ + +/** The Crypto user callback function type called at the end of Crypto calculation. */ +typedef void (*cy_crypto_callback_ptr_t)(void); + +/** The Crypto configuration structure. */ +typedef struct +{ + uint8_t cm0NotifyIntrNum; /**< Specifies the notify interrupt number for the CM0 core */ + uint8_t notifyIntrPrior; /**< Specifies the notify interrupt priority */ + uint8_t cm0ReleaseIntrNum; /**< Specifies the release interrupt number for the CM0 core */ + uint8_t releaseIntrPrior; /**< Specifies the release interrupt priority */ + uint8_t cm0CryptoErrorIntrNum; /**< Specifies the interrupt number for the Crypto error handler */ + uint8_t cryptoErrorIntrPrior; /**< Specifies the interrupt priority for the Crypto error handler */ + cy_crypto_callback_ptr_t userCompleteCallback; /**< User callback, called after Crypto HW completes calculation */ + cy_israddress userGetDataHandler; /**< User IPC process data IRQ handler */ + cy_israddress userErrorHandler; /**< User error IRQ handler */ +} cy_stc_crypto_config_t; + +#if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) +/** The structure for storing the RSA public key. */ +typedef struct +{ + uint8_t *moduloPtr; /**< The pointer to the modulus for both public and private keys. */ + uint32_t moduloLength; /**< The modulus length, in bits, maximum supported size is 2048Bit */ + uint8_t *pubExpPtr; /**< The pointer to the RSA key public exponent */ + uint32_t pubExpLength; /**< The RSA key public exponent length, in bits, maximum supported size is 256Bit */ + uint8_t *barretCoefPtr; /**< The pointer to the Barrett coefficient of size (moduloLength + 1) */ + uint8_t *inverseModuloPtr; /**< The pointer to the binary inverse of the modulo of size moduloLength */ + uint8_t *rBarPtr; /**< The pointer to the (2^moduloLength mod modulo) of size moduloLength */ +} cy_stc_crypto_rsa_pub_key_t; + +typedef enum +{ + CY_CRYPTO_RSA_VERIFY_SUCCESS = 0x00u, /**< RSA verify SUCCESS */ + CY_CRYPTO_RSA_VERIFY_FAIL = 0x01u /**< RSA verify FAILED */ +} cy_en_crypto_rsa_ver_result_t; + +#endif /* #if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +/** Structure for storing a description of a Crypto hardware error */ +typedef struct +{ + uint32_t errorStatus0; /**< Captures error description information: + for INSTR_OPC_ERROR: - violating the instruction. + for INSTR_CC_ERROR : - violating the instruction condition code. + for BUS_ERROR : - violating the transfer address. */ + + uint32_t errorStatus1; /**< [31] - Specifies if ERROR_STATUS0 and ERROR_STATUS1 capture is valid error-information. + [26..24] - The error source: + "0": INSTR_OPC_ERROR - an instruction decoder error. + "1": INSTR_CC_ERROR - an instruction condition code-error. + "2": BUS_ERROR - a bus master interface AHB-Lite bus-error. + "3": TR_AP_DETECT_ERROR. + [23..0] - Captures error description information. + For BUS_ERROR: - violating the transfer, read the attribute (DATA23[0]). + - violating the transfer, the size attribute (DATA23[5:4]). + "0": an 8-bit transfer; "1": 16 bits transfer; "2": 32-bit transfer. */ +} cy_stc_crypto_hw_error_t; + +/** \} group_crypto_data_structures */ + + +/** +* \addtogroup group_crypto_enums +* \{ +*/ + + +/** The key length options for the AES method. */ +#if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) +typedef enum +{ + CY_CRYPTO_KEY_AES_128 = 0x00u, /**< The AES key size is 128 bits */ + CY_CRYPTO_KEY_AES_192 = 0x01u, /**< The AES key size is 192 bits */ + CY_CRYPTO_KEY_AES_256 = 0x02u /**< The AES key size is 256 bits */ +} cy_en_crypto_aes_key_length_t; +#endif /* #if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) */ + +/** Defines the direction of the Crypto methods*/ +typedef enum +{ + CY_CRYPTO_ENCRYPT = 0x00u, /**< The forward mode, plain text will be encrypted into cipher text */ + CY_CRYPTO_DECRYPT = 0x01u /**< The reverse mode, cipher text will be decrypted into plain text */ +} cy_en_crypto_dir_mode_t; + +/** Define modes of SHA method */ +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) +typedef enum +{ +#if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) + CY_CRYPTO_MODE_SHA1 = 0x00u, /**< Sets the SHA1 mode */ +#endif /* #if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) + CY_CRYPTO_MODE_SHA224 = 0x11u, /**< Sets the SHA224 mode */ + CY_CRYPTO_MODE_SHA256 = 0x01u, /**< Sets the SHA256 mode */ +#endif /* #if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) + CY_CRYPTO_MODE_SHA384 = 0x12u, /**< Sets the SHA384 mode */ + CY_CRYPTO_MODE_SHA512 = 0x02u, /**< Sets the SHA512 mode */ + CY_CRYPTO_MODE_SHA512_256 = 0x22u, /**< Sets the SHA512/256 mode */ + CY_CRYPTO_MODE_SHA512_224 = 0x32u /**< Sets the SHA512/224 mode */ +#endif /* #if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) */ +} cy_en_crypto_sha_mode_t; +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) */ + +/** Errors of the Crypto block */ +typedef enum +{ + /** Operation completed successfully. */ + CY_CRYPTO_SUCCESS = 0x00u, + + /** A hardware error occurred, detailed information is in stc_crypto_hw_error_t. */ + CY_CRYPTO_HW_ERROR = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x01u, + + /** The size of input data is not multiple of 16. */ + CY_CRYPTO_SIZE_NOT_X16 = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x02u, + + /** The key for the DES method is weak. */ + CY_CRYPTO_DES_WEAK_KEY = CY_CRYPTO_ID | CY_PDL_STATUS_WARNING | 0x03u, + + /** Communication between the client-server via IPC is broken. */ + CY_CRYPTO_COMM_FAIL = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x04u, + + /** The Crypto server is not started. */ + CY_CRYPTO_SERVER_NOT_STARTED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x06u, + + /** Communication between the client-server via IPC is broken. */ + CY_CRYPTO_SERVER_BUSY = CY_CRYPTO_ID | CY_PDL_STATUS_INFO | 0x07u, + + /** The Crypto driver is not initialized. */ + CY_CRYPTO_NOT_INITIALIZED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x08u, + + /** The Crypto hardware is not enabled. */ + CY_CRYPTO_HW_NOT_ENABLED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x09u, + + /** The Crypto hardware is not enabled. */ + CY_CRYPTO_NOT_SUPPORTED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x0Au + +} cy_en_crypto_status_t; + +/** \} group_crypto_enums */ + +/** Instruction to communicate between Client and Server */ +typedef enum +{ + CY_CRYPTO_INSTR_UNKNOWN = 0x00u, + CY_CRYPTO_INSTR_ENABLE = 0x01u, + CY_CRYPTO_INSTR_DISABLE = 0x02u, + +#if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) + CY_CRYPTO_INSTR_PRNG_INIT = 0x03u, + CY_CRYPTO_INSTR_PRNG = 0x04u, +#endif /* #if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) */ + +#if ((CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) + CY_CRYPTO_INSTR_TRNG_INIT = 0x05u, + CY_CRYPTO_INSTR_TRNG = 0x06u, +#endif /* #if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_TR == 1)) */ + +#if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) + CY_CRYPTO_INSTR_AES_INIT = 0x07u, + +#if (CY_CRYPTO_USER_AES_ECB == 1) + CY_CRYPTO_INSTR_AES_ECB = 0x08u, +#endif /* #if (CRYPTO_USER_AES_ECB == 1) */ + +#if (CY_CRYPTO_USER_AES_CBC == 1) + CY_CRYPTO_INSTR_AES_CBC = 0x09u, +#endif /* #if (CRYPTO_USER_AES_CBC == 1) */ + +#if (CY_CRYPTO_USER_AES_CFB == 1) + CY_CRYPTO_INSTR_AES_CFB = 0x0Au, +#endif /* #if (CRYPTO_USER_AES_CFB == 1) */ + +#if (CY_CRYPTO_USER_AES_CTR == 1) + CY_CRYPTO_INSTR_AES_CTR = 0x0Bu, +#endif /* #if (CRYPTO_USER_AES_CTR == 1) */ + +#if (CY_CRYPTO_USER_CMAC == 1) + CY_CRYPTO_INSTR_CMAC = 0x0Cu, +#endif /* #if (CY_CRYPTO_USER_CMAC == 1) */ +#endif /* #if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) */ + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) + CY_CRYPTO_INSTR_SHA = 0x0Du, +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) */ + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) + CY_CRYPTO_INSTR_HMAC = 0x0Eu, +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) */ + +#if ((CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) + CY_CRYPTO_INSTR_MEM_CPY = 0x0Fu, + CY_CRYPTO_INSTR_MEM_SET = 0x10u, + CY_CRYPTO_INSTR_MEM_CMP = 0x11u, + CY_CRYPTO_INSTR_MEM_XOR = 0x12u, +#endif /* #if ((CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) */ + +#if ((CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) + CY_CRYPTO_INSTR_CRC_INIT = 0x13u, + CY_CRYPTO_INSTR_CRC = 0x14u, +#endif /* #if ((CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) */ + +#if ((CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) + CY_CRYPTO_INSTR_DES = 0x15u, + CY_CRYPTO_INSTR_3DES = 0x16u, +#endif /* #if ((CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) */ + +#if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) + CY_CRYPTO_INSTR_RSA_PROC = 0x17u, + CY_CRYPTO_INSTR_RSA_COEF = 0x18u, +#endif /* #if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) + CY_CRYPTO_INSTR_RSA_VER = 0x19u +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) */ + +} cy_en_crypto_comm_instr_t; + + +/** +* \addtogroup group_crypto_data_structures +* \{ +*/ + +/** Structure for storing the AES state */ +#if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) +typedef struct +{ + uint32_t *keyPtr; /**< Pointer to AES key */ + uint32_t invKey[CY_CRYPTO_AES_256_KEY_SIZE / 4u]; /**< Storage for inversed key */ + cy_en_crypto_aes_key_length_t keyLength; /**< AES key length */ + uint32_t blockIdx; /**< AES processed block index (for CMAC, SHA operations) */ +} cy_stc_crypto_aes_state_t; +#endif /* #if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) */ + +/************************************************************* +* Structures used for communication between Client and Server +***************************************************************/ + +/** Structure for storing the global context */ +typedef struct +{ + cy_en_crypto_comm_instr_t instr; /**< Server instruction code */ + cy_en_crypto_status_t resp; /**< Response from executed crypto function */ + cy_stc_crypto_hw_error_t hwErrorStatus; /**< Hardware processing errors */ + void *xdata; /**< Pointer to the crypto function specific context data */ +} cy_stc_crypto_context_t; + + +#if ((CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) +/** Structure for storing the DES context */ +typedef struct +{ + cy_en_crypto_dir_mode_t dirMode; /**< Operation direction (Encrypt / Decrypt) */ + uint32_t *keyPtr; /**< Pointer to key data */ + uint32_t *dstPtr; /**< Pointer to data destination block */ + uint32_t *srcPtr; /**< Pointer to data source block */ +} cy_stc_crypto_context_des_t; +#endif /* #if ((CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) */ + +#if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) +/** Structure for storing the AES context */ +typedef struct +{ + cy_stc_crypto_aes_state_t aesState; /**< AES state data */ + cy_en_crypto_dir_mode_t dirMode; /**< Operation direction (Encrypt / Decrypt) */ + uint32_t srcSize; /**< Operation data size */ + uint32_t *srcOffset; /**< Size of the last non-complete block (for CTR mode only) */ + uint32_t *ivPtr; /**< Initialization vector, in the CTR mode is used as nonceCounter */ + uint32_t *streamBlock; /**< AES processed block pointer (for CTR mode only) */ + uint32_t *dstPtr; /**< Pointer to data destination block */ + uint32_t *srcPtr; /**< Pointer to data source block */ +} cy_stc_crypto_context_aes_t; +#endif /* #if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) */ + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) +/** Structure for storing the SHA context */ +typedef struct +{ + uint32_t *messagePtr; /**< Pointer to data source block */ + uint32_t messageSize; /**< Operation data size */ + uint32_t *dstPtr; /**< Pointer to data destination block */ + cy_en_crypto_sha_mode_t mode; /**< SHA mode */ + uint32_t *keyPtr; /**< Pointer to key data (for HMAC only) */ + uint32_t keyLength; /**< Key data length (for HMAC only) */ +} cy_stc_crypto_context_sha_t; +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) */ + +#if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) +/** Structure for storing the PRNG context */ +typedef struct +{ + uint32_t lfsr32InitState; /**< lfsr32 initialization data */ + uint32_t lfsr31InitState; /**< lfsr31 initialization data */ + uint32_t lfsr29InitState; /**< lfsr29 initialization data */ + uint32_t max; /**< Maximum of the generated value */ + uint32_t *prngNumPtr; /**< Pointer to generated value */ +} cy_stc_crypto_context_prng_t; +#endif /* #if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) */ + +#if ((CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) +/** Structure for storing the TRNG context */ +typedef struct +{ + uint32_t GAROPol; /**< The polynomial for the programmable Galois ring oscillator (TR_GARO_CTL). + The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). + The polynomial should be aligned so that more significant bits (bit 30 and down) + contain the polynomial and less significant bits (bit 0 and up) contain padding '0's. */ + + uint32_t FIROPol; /**< The polynomial for the programmable Fibonacci ring oscillator(TR_FIRO_CTL). + The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). + The polynomial should be aligned so that more significant bits (bit 30 and down) + contain the polynomial and less significant bits (bit 0 and up) contain padding '0's. */ + uint32_t max; /**< Maximum of the generated value */ + uint32_t *trngNumPtr; /**< Pointer to generated value */ +} cy_stc_crypto_context_trng_t; +#endif /* #if ((CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) */ + +#if ((CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) +/** Structure for storing the STR context */ +typedef struct +{ + void const *srcPtr0; /**< Pointer to 1-st string source */ + void const *srcPtr1; /**< Pointer to 2-nd string source */ + void *dstPtr; /**< Pointer to string destination */ + uint32_t dataSize; /**< Operation data size */ + uint32_t data; /**< Operation data value (for memory setting) */ +} cy_stc_crypto_context_str_t; +#endif /* #if ((CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) */ + +#if ((CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) +/** Structure for storing the CRC context */ +typedef struct +{ + void* srcDataPtr; /**< Pointer to data source block */ + uint32_t dataSize; /**< operation data size */ + uint32_t *crcPtr; /**< Pointer to CRC destination variable */ + uint32_t polynomial; /**< Polynomial for CRC calculate */ + uint32_t lfsrInitState; /**< CRC calculation initial value */ + uint32_t dataReverse; /**< Input data reverse flag */ + uint32_t dataXor; /**< Input data XOR flag */ + uint32_t remReverse; /**< Output data reverse flag */ + uint32_t remXor; /**< Output data XOR flag */ +} cy_stc_crypto_context_crc_t; +#endif /* #if ((CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) */ + +#if (CY_CRYPTO_USER_PKCS1_5 == 1) +/** Structure for storing the RSA verify context */ +typedef struct +{ + cy_en_crypto_rsa_ver_result_t *verResult; /**< Pointer to verification result /ref cy_en_crypto_rsa_ver_result_t */ + cy_en_crypto_sha_mode_t digestType; /**< SHA digess type, used with SHA calculation of the message */ + uint32_t const *hashPtr; /**< SHA digest of the message, calculated with digestType */ + uint32_t const *decryptedSignaturePtr; /**< Previously decrypted RSA signature */ + uint32_t decryptedSignatureLength; /**< Length of the decrypted RSA signature */ +} cy_stc_crypto_context_rsa_ver_t; +#endif /* #if (CY_CRYPTO_USER_PKCS1_5 == 1) */ + +#if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) +/** Structure for storing the RSA process context */ +typedef struct +{ + cy_stc_crypto_rsa_pub_key_t *keyPtr; /**< Pointer to key data */ + uint32_t const *messagePtr; /**< Pointer to data source block */ + uint32_t messageLength; /**< Operation data size */ + uint32_t const *resultPtr; /**< Pointer to data destination block */ +} cy_stc_crypto_context_rsa_t; +#endif /* #if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +/** \} group_crypto_data_structures */ + + +#endif /* (CPUSS_CRYPTO_PRESENT == 1) */ + +#endif /* #if !defined(CY_CRYPTO_COMMON_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_aes.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_aes.c new file mode 100644 index 0000000000..86d13fe225 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_aes.c @@ -0,0 +1,405 @@ +/***************************************************************************//** +* \file cy_crypto_core_aes.c +* \version 1.0 +* +* \brief +* This file provides the source code fro the API for the AES method +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_aes.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_str.h" +#include "syslib/cy_syslib.h" +#include + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Aes_InvKey +****************************************************************************//** +* +* Calculates an inverse block cipher key from the block cipher key. +* +* This function available for CM0+ core only. +* +* \param cryptoAesContext +* The pointer to the stc_crypto_context_t structure which stores all internal variables +* the Crypto driver requires. +* +*******************************************************************************/ +void Cy_Crypto_Core_Aes_InvKey(cy_stc_crypto_aes_state_t const *aesStatePtr) +{ + /* Issue the AES_KEY instruction to prepare the key for decrypt operation */ + Cy_Crypto_SetReg2Instr((uint32_t)aesStatePtr->keyPtr, (uint32_t)aesStatePtr->invKey); + + Cy_Crypto_Run2ParamInstr(CY_CRYPTO_AES_KEY_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC8_SHIFT); + + /* Wait until the AES instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_AES_BUSY, CRYPTO->STATUS)) + { + } +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Aes_Init +****************************************************************************//** +* +* Sets Aes mode and prepare inversed key. +* +* This function available for CM0+ core only. +* +* \param cryptoAesContext +* The pointer to the stc_crypto_context_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Aes_Init(cy_stc_crypto_context_aes_t const *cryptoAesContext) +{ + /* Set the key mode: 128, 192 or 256 Bit */ + CRYPTO->AES_CTL = (uint32_t)(_VAL2FLD(CRYPTO_AES_CTL_KEY_SIZE, + (uint32_t)(cryptoAesContext->aesState.keyLength))); + + Cy_Crypto_Core_Aes_InvKey(&(cryptoAesContext->aesState)); + + return (CY_CRYPTO_SUCCESS); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Aes_ProcessBlock +****************************************************************************//** +* +* Performs the AES block cipher. +* +* This function available for CM0+ core only. +* +* \param aesStatePtr +* The pointer to the aesStatePtr structure which stores the AES context. +* +* \param dirMode +* One of CRYPTO_ENCRYPT or CRYPTO_DECRYPT. +* +* \param dstBlockPtr +* The pointer to the cipher text. +* +* \param srcBlockPtr +* The pointer to the plain text. Must be 4-Byte aligned! +* +*******************************************************************************/ +void Cy_Crypto_Core_Aes_ProcessBlock(cy_stc_crypto_aes_state_t const *aesStatePtr, + cy_en_crypto_dir_mode_t dirMode, + uint32_t *dstBlockPtr, + uint32_t const *srcBlockPtr) +{ + Cy_Crypto_SetReg3Instr((CY_CRYPTO_DECRYPT == dirMode) ? (uint32_t)aesStatePtr->invKey : (uint32_t)aesStatePtr->keyPtr, + (uint32_t)srcBlockPtr, + (uint32_t)dstBlockPtr); + + Cy_Crypto_Run3ParamInstr((CY_CRYPTO_DECRYPT == dirMode) ? CY_CRYPTO_AES_BLOCK_INV_OPC : CY_CRYPTO_AES_BLOCK_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT, + CY_CRYPTO_RSRC12_SHIFT); + + /* Wait until the AES instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_AES_BUSY, CRYPTO->STATUS)) + { + } +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Aes_Xor +****************************************************************************//** +* +* Perform the XOR of two 16-Byte memory structures. +* All addresses must be 4-Byte aligned! +* +* This function available for CM0+ core only. +* +* \param src0BlockPtr +* The pointer to the first memory structure. Must be 4-Byte aligned! +* +* \param src1BlockPtr +* The pointer to the second memory structure. Must be 4-Byte aligned! +* +* \param dstBlockPtr +* The pointer to the memory structure with the XOR results. +* +*******************************************************************************/ +void Cy_Crypto_Core_Aes_Xor(uint32_t const *src0BlockPtr, + uint32_t const *src1BlockPtr, + uint32_t *dstBlockPtr) +{ + Cy_Crypto_SetReg3Instr((uint32_t)src0BlockPtr, + (uint32_t)src1BlockPtr, + (uint32_t)dstBlockPtr); + + /* Issue the AES_XOR instruction */ + Cy_Crypto_Run3ParamInstr(CY_CRYPTO_AES_XOR_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT, + CY_CRYPTO_RSRC8_SHIFT); + + /* Wait until the AES instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_AES_BUSY, CRYPTO->STATUS)) + { + } +} + +#if (CY_CRYPTO_USER_AES_ECB == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Aes_Ecb +****************************************************************************//** +* +* Performs AES operation on one Block. +* +* This function available for CM0+ core only. +* +* \param cryptoAesContext +* The pointer to the stc_crypto_context_t structure which stores +* Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ecb(cy_stc_crypto_context_aes_t *cryptoAesContext) +{ + cy_stc_crypto_aes_state_t aesStateTmp = cryptoAesContext->aesState; + cy_en_crypto_dir_mode_t dirModeTmp = (cy_en_crypto_dir_mode_t)(cryptoAesContext->dirMode); + + Cy_Crypto_Core_Aes_ProcessBlock(&aesStateTmp, + dirModeTmp, + cryptoAesContext->dstPtr, + cryptoAesContext->srcPtr); + + return (CY_CRYPTO_SUCCESS); +} +#endif /* #if (CY_CRYPTO_USER_AES_ECB == 1) */ + +#if (CY_CRYPTO_USER_AES_CBC == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Aes_Cbc +****************************************************************************//** +* +* Performs AES operation on a plain text with Cipher Block Chaining (CBC). +* +* This function available for CM0+ core only. +* +* \param cryptoAesContext +* The pointer to stc_crypto_context_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cbc(cy_stc_crypto_context_aes_t *cryptoAesContext) +{ + uint32_t size = (uint32_t)cryptoAesContext->srcSize; + uint32_t *dstPtrTmp = (uint32_t*)cryptoAesContext->dstPtr; + uint32_t *srcPtrTmp = (uint32_t*)cryptoAesContext->srcPtr; + cy_en_crypto_dir_mode_t dirModeTmp = cryptoAesContext->dirMode; + uint32_t *tempBuffPtr = (uint32_t*)CRYPTO->MEM_BUFF; + cy_en_crypto_status_t result; + + /* Check whether the data size is multiple of 16 */ + if (0uL != (uint32_t)(size & (CY_CRYPTO_AES_BLOCK_SIZE - 1u))) + { + result = CY_CRYPTO_SIZE_NOT_X16; + } + else + { + /* Copy the Initialization Vector to the local buffer because it changes during calculation */ + memcpy(tempBuffPtr, cryptoAesContext->ivPtr, CY_CRYPTO_AES_BLOCK_SIZE); + + if (CY_CRYPTO_DECRYPT == dirModeTmp) + { + while (size > 0uL) + { + Cy_Crypto_Core_Aes_ProcessBlock(&(cryptoAesContext->aesState), + dirModeTmp, + dstPtrTmp, + srcPtrTmp); + + Cy_Crypto_Core_Aes_Xor(tempBuffPtr, dstPtrTmp, dstPtrTmp); + + memcpy(tempBuffPtr, srcPtrTmp, CY_CRYPTO_AES_BLOCK_SIZE); + + srcPtrTmp += CY_CRYPTO_AES_BLOCK_SIZE_U32; + dstPtrTmp += CY_CRYPTO_AES_BLOCK_SIZE_U32; + size -= CY_CRYPTO_AES_BLOCK_SIZE; + } + } + else + { + while (size > 0uL) + { + Cy_Crypto_Core_Aes_Xor(srcPtrTmp, tempBuffPtr, tempBuffPtr); + + Cy_Crypto_Core_Aes_ProcessBlock(&(cryptoAesContext->aesState), + dirModeTmp, + dstPtrTmp, + tempBuffPtr); + + memcpy(tempBuffPtr, dstPtrTmp, CY_CRYPTO_AES_BLOCK_SIZE); + + srcPtrTmp += CY_CRYPTO_AES_BLOCK_SIZE_U32; + dstPtrTmp += CY_CRYPTO_AES_BLOCK_SIZE_U32; + size -= CY_CRYPTO_AES_BLOCK_SIZE; + } + } + + result = CY_CRYPTO_SUCCESS; + } + + return (result); +} +#endif /* #if (CY_CRYPTO_USER_AES_CBC == 1) */ + +#if (CY_CRYPTO_USER_AES_CFB == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Aes_Cfb +******************************************************************************** +* +* Performs AES operation on a plain text with the Cipher Feedback Block method (CFB). +* +* This function available for CM0+ core only. +* +* \param cryptoAesContext +* The pointer to the stc_crypto_context_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cfb(cy_stc_crypto_context_aes_t *cryptoAesContext) +{ + uint32_t size = (uint32_t)cryptoAesContext->srcSize; + uint32_t *tempIvPtr = (uint32_t*)CRYPTO->MEM_BUFF; + uint32_t *dstPtrTmp = (uint32_t*)cryptoAesContext->dstPtr; + uint32_t *srcPtrTmp = (uint32_t*)cryptoAesContext->srcPtr; + uint32_t *tempBuffPtr = (uint32_t*)dstPtrTmp; + cy_en_crypto_status_t result; + + /* Check whether the data size is multiple of 16 */ + if (0uL != (size & (CY_CRYPTO_AES_BLOCK_SIZE - 1u))) + { + result = CY_CRYPTO_SIZE_NOT_X16; + } + else + { + /* Copy the Initialization Vector to local buffer because it is changing during calculation */ + memcpy(tempIvPtr, cryptoAesContext->ivPtr, CY_CRYPTO_AES_BLOCK_SIZE); + + if (CY_CRYPTO_DECRYPT == cryptoAesContext->dirMode) + { + tempBuffPtr = srcPtrTmp; + } + + while (size > 0uL) + { + /* In this mode, (CFB) is always an encryption! */ + Cy_Crypto_Core_Aes_ProcessBlock(&(cryptoAesContext->aesState), + CY_CRYPTO_ENCRYPT, + dstPtrTmp, + tempIvPtr); + + Cy_Crypto_Core_Aes_Xor(srcPtrTmp, dstPtrTmp, dstPtrTmp); + + memcpy(tempIvPtr, tempBuffPtr, CY_CRYPTO_AES_BLOCK_SIZE); + + srcPtrTmp += CY_CRYPTO_AES_BLOCK_SIZE_U32; + dstPtrTmp += CY_CRYPTO_AES_BLOCK_SIZE_U32; + tempBuffPtr += CY_CRYPTO_AES_BLOCK_SIZE_U32; + size -= CY_CRYPTO_AES_BLOCK_SIZE; + } + + result = CY_CRYPTO_SUCCESS; + } + + return (result); +} +#endif /* #if (CY_CRYPTO_USER_AES_CFB == 1) */ + +#if (CY_CRYPTO_USER_AES_CTR == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Aes_Ctr +******************************************************************************** +* +* Performs AES operation on a plain text using the counter method (CTR). +* +* This function available for CM0+ core only. +* +* \param cryptoAesContext +* The pointer to the stc_crypto_context_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ctr(cy_stc_crypto_context_aes_t *cryptoAesContext) +{ + uint32_t *dstPtrTmp = (uint32_t*)cryptoAesContext->dstPtr; + uint32_t *srcPtrTmp = (uint32_t*)cryptoAesContext->srcPtr; + uint32_t size = (uint32_t)cryptoAesContext->srcSize; + uint32_t *streamBlockTmp = (uint32_t*)cryptoAesContext->streamBlock; + uint32_t *nonceCounter = (uint32_t*)cryptoAesContext->ivPtr; + uint32_t cnt; + uint32_t i; + uint64_t counter; + + cnt = (uint32_t)(size / CY_CRYPTO_AES_BLOCK_SIZE); + + for (i = 0uL; i < cnt; i++) + { + /* In this mode, (CTR) is always an encryption! */ + Cy_Crypto_Core_Aes_ProcessBlock(&(cryptoAesContext->aesState), + CY_CRYPTO_ENCRYPT, + streamBlockTmp, + nonceCounter); + + /* Increment the nonce counter, at least 64Bits (from 128) is the counter part */ + counter = *(uint64_t*)(nonceCounter + CY_CRYPTO_AES_CTR_CNT_POS); + counter = Cy_Crypto_InvertEndian8(counter); + counter++; + counter = Cy_Crypto_InvertEndian8(counter); + *(uint64_t*)(nonceCounter + CY_CRYPTO_AES_CTR_CNT_POS) = counter; + + Cy_Crypto_Core_Aes_Xor(srcPtrTmp, + streamBlockTmp, + dstPtrTmp); + + srcPtrTmp += CY_CRYPTO_AES_BLOCK_SIZE_U32; + dstPtrTmp += CY_CRYPTO_AES_BLOCK_SIZE_U32; + } + + /* Save the reminder of the last non-complete block */ + *cryptoAesContext->srcOffset = (uint32_t)(size % CY_CRYPTO_AES_BLOCK_SIZE); + + return (CY_CRYPTO_SUCCESS); +} +#endif /* #if (CY_CRYPTO_USER_AES_CTR == 1) */ + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_aes.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_aes.h new file mode 100644 index 0000000000..2514192aba --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_aes.h @@ -0,0 +1,77 @@ +/***************************************************************************//** +* \file cy_crypto_core_aes.h +* \version 1.0 +* +* \brief +* This file provides constant and parameters for the API for the AES method +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_CRYPTO_CORE_AES_H) +#define CY_CRYPTO_CORE_AES_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) + + +#define CY_CRYPTO_AES_CTR_CNT_POS (0x02u) + +void Cy_Crypto_Core_Aes_InvKey(cy_stc_crypto_aes_state_t const *aesStatePtr); + +void Cy_Crypto_Core_Aes_ProcessBlock(cy_stc_crypto_aes_state_t const *aesStatePtr, + cy_en_crypto_dir_mode_t dirMode, + uint32_t *dstBlockPtr, + uint32_t const *srcBlockPtr); + +void Cy_Crypto_Core_Aes_Xor(uint32_t const *src0BlockPtr, + uint32_t const *src1BlockPtr, + uint32_t *dstBlockPtr); + +cy_en_crypto_status_t Cy_Crypto_Core_Aes_Init(cy_stc_crypto_context_aes_t const *cryptoContextPtr); + +#if (CY_CRYPTO_USER_AES_ECB == 1) +cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ecb(cy_stc_crypto_context_aes_t *cryptoContextPtr); +#endif /* #if (CY_CRYPTO_USER_AES_ECB == 1) */ + +#if (CY_CRYPTO_USER_AES_CBC == 1) +cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cbc(cy_stc_crypto_context_aes_t *cryptoContextPtr); +#endif /* #if (CY_CRYPTO_USER_AES_CBC == 1) */ + +#if (CY_CRYPTO_USER_AES_CFB == 1) +cy_en_crypto_status_t Cy_Crypto_Core_Aes_Cfb(cy_stc_crypto_context_aes_t *cryptoContextPtr); +#endif /* #if (CY_CRYPTO_USER_AES_CFB == 1) */ + +#if (CY_CRYPTO_USER_AES_CTR == 1) +cy_en_crypto_status_t Cy_Crypto_Core_Aes_Ctr(cy_stc_crypto_context_aes_t *cryptoContextPtr); +#endif /* #if (CY_CRYPTO_USER_AES_CTE == 1) */ + +__STATIC_INLINE void Cy_Crypto_Core_Aes_WaitReady(void) +{ + /* Wait until the TRNG instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_AES_BUSY, CRYPTO->STATUS)) + { + } +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_AES_H) */ + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_cmac.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_cmac.c new file mode 100644 index 0000000000..9fae4cd10b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_cmac.c @@ -0,0 +1,272 @@ +/***************************************************************************//** +* \file cy_crypto_core_cmac.c +* \version 1.0 +* +* \brief +* This file provides the source code to the API for the CMAC method +* in the Crypto block driver. +* +* Implementation is done in accordance with: +* http://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38b.pdf +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_core_cmac.h" +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_aes.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_str.h" +#include "syslib/cy_syslib.h" +#include + + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_CMAC == 1)) + + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Cmac_CalcSubKey +****************************************************************************//** +* +* Calculates the sub-key for the CMAC algorithm +* according to the NIST publication 800-38B, page 7. +* +* This function available for CM0+ core only. +* +* \param srcDstPtr +* The pointer to the source data for sub-key calculation, see 800-38B. +* +*******************************************************************************/ +static void Cy_Crypto_Core_Cmac_CalcSubKey(uint8_t *srcDstPtr) +{ + int32_t i; + uint32_t c; + uint32_t msb = 0uL; + + for (i = 15; i >= 0; i--) + { + c = (uint32_t)srcDstPtr[i]; + c = (c << 1) | msb; + srcDstPtr[i] = (uint8_t) c; + msb = (c >> 8u) & 1uL; + } + + if (0uL != msb) + { + /* Just one byte is valuable, the rest are zeros */ + srcDstPtr[(uint8_t)(CY_CRYPTO_AES_BLOCK_SIZE - 1u)] ^= CY_CRYPTO_CMAC_RB; + } +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Cmac_Init +****************************************************************************//** +* +* The function for initialization of CMAC operation. +* +* This function available for CM0+ core only. +* +* \param cmacStatePtr +* The pointer to the structure which stores the CMAC context. +* +* \param tempPtr +* The pointer to the temporary memory needed for CMAC calculation, +* the max needed - 128 Bytes. +* +* \param blockPtr +* The pointer to the temporary storage for block, the max needed - 128 Bytes. +* +* \param kPtr +* The pointer to the sub-key. + +*******************************************************************************/ +void Cy_Crypto_Core_Cmac_Init(cy_stc_crypto_cmac_state_t* cmacStatePtr, + uint32_t* tempPtr, + uint32_t* blockPtr, + uint32_t* kPtr) +{ + cmacStatePtr->blockPtr = blockPtr; + cmacStatePtr->tempPtr = tempPtr; + cmacStatePtr->kPtr = kPtr; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Cmac_Start +****************************************************************************//** +* +* Starts CMAC calculation. +* +* This function available for CM0+ core only. +* +* \param aesStatePtr +* The pointer to the structure which stores the AES context. +* +* \param cmacStatePtr +* the pointer to the structure which stores the CMAC context. +* +*******************************************************************************/ +void Cy_Crypto_Core_Cmac_Start(cy_stc_crypto_aes_state_t *aesStatePtr, + cy_stc_crypto_cmac_state_t *cmacStatePtr) +{ + uint32_t *kPtrTmp = cmacStatePtr->kPtr; + uint32_t *tempPtrTmp = cmacStatePtr->tempPtr; + + /* Calculate the K1 sub-key */ + memset((void*)tempPtrTmp, 0u, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_Aes_ProcessBlock(aesStatePtr, CY_CRYPTO_ENCRYPT, kPtrTmp, tempPtrTmp); + + Cy_Crypto_Core_Cmac_CalcSubKey((uint8_t*)kPtrTmp); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Cmac_Update +****************************************************************************//** +* +* Calculates CMAC on a message. +* +* This function available for CM0+ core only. +* +* \param aesStatePtr +* The pointer to the structure which stores the AES context. +* +* \param cmacStatePtr +* The pointer to the structure which stores the CMAC context. +* +* \param messagePtr +* The pointer to the message whose CMAC is being computed. +* +* \param messageSize +* The size of the message whose CMAC is being computed. +* +*******************************************************************************/ +void Cy_Crypto_Core_Cmac_Update(cy_stc_crypto_aes_state_t *aesStatePtr, + cy_stc_crypto_cmac_state_t *cmacStatePtr, + uint32_t *messagePtr, + uint32_t messageSize) +{ + uint32_t *blockPtrTmp = cmacStatePtr->blockPtr; + uint32_t *tempPtrTmp = cmacStatePtr->tempPtr; + + /* Clear the argument for XOR for the first block */ + memset((void* )tempPtrTmp, 0x00u, CY_CRYPTO_AES_BLOCK_SIZE); + + /* Process all blocks except last */ + while (messageSize > CY_CRYPTO_AES_BLOCK_SIZE) + { + Cy_Crypto_Core_Aes_Xor(messagePtr, tempPtrTmp, blockPtrTmp); + Cy_Crypto_Core_Aes_ProcessBlock(aesStatePtr, CY_CRYPTO_ENCRYPT, tempPtrTmp, blockPtrTmp); + + /* Attention! 4 because the pointer is uint32_t */ + messagePtr += 4u; + messageSize -= 16u; + } + + /* The calculation size of the last block */ + aesStatePtr->blockIdx = messageSize; + + /* Copy the last block to the blockPtr */ + memcpy((void*)blockPtrTmp, (void*)messagePtr, (uint16_t)aesStatePtr->blockIdx); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Cmac_Finish +****************************************************************************//** +* +* Completes CMAC calculation. +* +* This function available for CM0+ core only. +* +* \param aesStatePtr +* the pointer to the structure which stores the AES context. +* +* \param cmacStatePtr +* The pointer to the structure which stores the CMAC context. +* +* \param cmacPtr +* The pointer to the computed CMAC value. +* +*******************************************************************************/ +void Cy_Crypto_Core_Cmac_Finish(cy_stc_crypto_aes_state_t *aesStatePtr, + cy_stc_crypto_cmac_state_t *cmacStatePtr, + uint32_t* cmacPtr) +{ + uint32_t *blockPtrTmp = cmacStatePtr->blockPtr; + uint32_t *tempPtrTmp = cmacStatePtr->tempPtr; + uint32_t *kPtrTmp = cmacStatePtr->kPtr; + uint32_t blockIdxTmp = aesStatePtr->blockIdx; + uint32_t copySize; + + if (blockIdxTmp < CY_CRYPTO_AES_BLOCK_SIZE) + { + /* Calculate the K2 sub-key */ + Cy_Crypto_Core_Cmac_CalcSubKey((uint8_t* )kPtrTmp); + + /* Appended '1' bit to the end of message, followed by '0' */ + *((uint8_t* )blockPtrTmp + blockIdxTmp) = 0x80u; + + /* Write zeros into the rest of the message */ + copySize = CY_CRYPTO_AES_BLOCK_SIZE - 1u - blockIdxTmp; + memset(((uint8_t* )blockPtrTmp + blockIdxTmp + 1), 0x00u, (uint16_t)copySize); + } + + Cy_Crypto_Core_Aes_Xor(blockPtrTmp, tempPtrTmp, blockPtrTmp); + Cy_Crypto_Core_Aes_Xor(blockPtrTmp, kPtrTmp, blockPtrTmp); + + Cy_Crypto_Core_Aes_ProcessBlock(aesStatePtr, CY_CRYPTO_ENCRYPT, cmacPtr, blockPtrTmp); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Cmac +****************************************************************************//** +* +* Performs CMAC(Cipher-based Message Authentication Code) operation +* on a message to produce message authentication code using AES. +* +* This function available for CM0+ core only. +* +* \param cryptoAesContext +* The pointer to the stc_crypto_context_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Cmac(cy_stc_crypto_context_aes_t *cryptoAesContext) +{ + uint32_t *resultPtr = (uint32_t*)cryptoAesContext->dstPtr; + uint32_t *messagePtr = (uint32_t*)cryptoAesContext->srcPtr; + uint32_t messageSize = (uint32_t)cryptoAesContext->srcSize; + + cy_stc_crypto_aes_state_t *aesStatePtr = &cryptoAesContext->aesState; + + uint32_t *blockPtr = (uint32_t*)CRYPTO->MEM_BUFF; + uint32_t *tempPtr = (uint32_t*)((uint8_t*)blockPtr + CY_CRYPTO_AES_BLOCK_SIZE); + uint32_t *kPtr = (uint32_t*)((uint8_t*)tempPtr + CY_CRYPTO_AES_BLOCK_SIZE); + + cy_stc_crypto_cmac_state_t *cmacStatePtr = (cy_stc_crypto_cmac_state_t* )((uint8_t*)kPtr + CY_CRYPTO_AES_BLOCK_SIZE); + + (void)Cy_Crypto_Core_Aes_Init(cryptoAesContext); + + Cy_Crypto_Core_Cmac_Init (cmacStatePtr, tempPtr, blockPtr, kPtr); + Cy_Crypto_Core_Cmac_Start (aesStatePtr, cmacStatePtr); + Cy_Crypto_Core_Cmac_Update(aesStatePtr, cmacStatePtr, messagePtr, messageSize); + Cy_Crypto_Core_Cmac_Finish(aesStatePtr, cmacStatePtr, resultPtr); + + return (CY_CRYPTO_SUCCESS); +} + + +#endif /* ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_CMAC == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_cmac.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_cmac.h new file mode 100644 index 0000000000..3a0c06ef2b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_cmac.h @@ -0,0 +1,72 @@ +/***************************************************************************//** +* \file cy_crypto_core_cmac.h +* \version 1.0 +* +* \brief +* This file provides constants and function prototypes +* for the API for the CMAC method in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CORE_CMAC_H) +#define CY_CRYPTO_CORE_CMAC_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_CMAC == 1)) + +/** \cond INTERNAL */ + +/* The bit string used to generate sub-keys */ +#define CY_CRYPTO_CMAC_RB (0x87u) + +/* The structure to store the AES-CMAC context */ +typedef struct +{ + uint32_t *blockPtr; + uint32_t *kPtr; + uint32_t *tempPtr; +} cy_stc_crypto_cmac_state_t; + + +/* The function prototypes */ +uint32_t Cy_Crypto_Core_Cmac_LeftShift(uint8_t *srcDstPtr); + +void Cy_Crypto_Core_Cmac_Init(cy_stc_crypto_cmac_state_t *cmacStatePtr, + uint32_t *tempPtr, + uint32_t *blockPtr, + uint32_t *kPtr); + +void Cy_Crypto_Core_Cmac_Start(cy_stc_crypto_aes_state_t *aesStatePtr, + cy_stc_crypto_cmac_state_t *cmacStatePtr); + +void Cy_Crypto_Core_Cmac_Update(cy_stc_crypto_aes_state_t *aesStatePtr, + cy_stc_crypto_cmac_state_t *cmacStatePtr, + uint32_t *messagePtr, + uint32_t messageSize); + +void Cy_Crypto_Core_Cmac_Finish(cy_stc_crypto_aes_state_t *aesStatePtr, + cy_stc_crypto_cmac_state_t *cmacStatePtr, + uint32_t* cmacPtr); + +cy_en_crypto_status_t Cy_Crypto_Core_Cmac(cy_stc_crypto_context_aes_t *cryptoAesContext); + +/** \endcond */ + + +#endif /* ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_CMAC == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_CMAC_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_crc.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_crc.c new file mode 100644 index 0000000000..acd6034f9d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_crc.c @@ -0,0 +1,117 @@ +/***************************************************************************//** +* \file cy_crypto_core_crc.c +* \version 1.0 +* +* \brief +* This file provides the source code for CRC API +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_crc.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "syslib/cy_syslib.h" + + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) + + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Crc_Init +****************************************************************************//** +* +* Initializes CRC calculation. +* +* This function available for CM0+ core only. +* +* \param cryptoCrcContext +* The pointer to the stc_crypto_context_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Crc_Init(cy_stc_crypto_context_crc_t *cryptoCrcContext) +{ + + /* Specifies the bit order in which a data Byte is processed + * (reversal is performed after XORing): + * '0': Most significant bit (bit 1) first. + * '1': Least significant bit (bit 0) first. */ + CRYPTO->CRC_CTL = (uint32_t)( (_VAL2FLD(CRYPTO_CRC_CTL_DATA_REVERSE, (uint32_t)(cryptoCrcContext->dataReverse))) | + (_VAL2FLD(CRYPTO_CRC_CTL_REM_REVERSE, (uint32_t)(cryptoCrcContext->remReverse))) ); + + /* Specifies a byte mask with which each data byte is XORed. + * The XOR is performed before data reversal. */ + CRYPTO->CRC_DATA_CTL = (uint32_t)(_VAL2FLD(CRYPTO_CRC_DATA_CTL_DATA_XOR, (uint32_t)cryptoCrcContext->dataXor)); + + /* CRC polynomial. The polynomial is represented WITHOUT the high order bit + * (this bit is always assumed '1'). */ + CRYPTO->CRC_POL_CTL = (uint32_t)(_VAL2FLD(CRYPTO_CRC_POL_CTL_POLYNOMIAL, (uint32_t)cryptoCrcContext->polynomial)); + + /*Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XORed to produce a remainder. + * The XOR is performed before remainder reversal. */ + CRYPTO->CRC_REM_CTL = (uint32_t)(_VAL2FLD(CRYPTO_CRC_REM_CTL_REM_XOR, (uint32_t)cryptoCrcContext->remXor)); + + return (CY_CRYPTO_SUCCESS); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_Crc +****************************************************************************//** +* +* Performs CRC calculation on a message. +* +* This function available for CM0+ core only. +* +* \param cryptoCrcContext +* The pointer to the stc_crypto_context_t structure which stores +* vCrypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Crc(cy_stc_crypto_context_crc_t *cryptoCrcContext) +{ + + /* A state of 32-bit Linear Feedback Shift Registers (LFSR) used to implement CRC. */ + CRYPTO->CRC_LFSR_CTL = (uint32_t)(_VAL2FLD(CRYPTO_CRC_LFSR_CTL_LFSR32, (uint32_t)cryptoCrcContext->lfsrInitState)); + + /* Fill the FIFO with the instruction parameters */ + Cy_Crypto_SetReg2Instr( (uint32_t)cryptoCrcContext->srcDataPtr, + (uint32_t)cryptoCrcContext->dataSize ); + + /* Issue the CRC instruction */ + Cy_Crypto_Run2ParamInstr(CY_CRYPTO_CRC_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT); + + /* Wait until STR instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_CRC_BUSY, CRYPTO->STATUS)) + { + } + + /* Copy the result from the CRC_REM_RESULT register */ + *cryptoCrcContext->crcPtr = (uint32_t)_FLD2VAL(CRYPTO_CRC_REM_RESULT_REM, CRYPTO->CRC_REM_RESULT); + + return (CY_CRYPTO_SUCCESS); +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_crc.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_crc.h new file mode 100644 index 0000000000..222e22a5d5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_crc.h @@ -0,0 +1,41 @@ +/***************************************************************************//** +* \file cy_crypto_core_crc.h +* \version 1.0 +* +* \brief +* This file provides the headers for CRC API +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CORE_CRC_H) +#define CY_CRYPTO_CORE_CRC_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) + + +cy_en_crypto_status_t Cy_Crypto_Core_Crc_Init (cy_stc_crypto_context_crc_t *cryptoCrcContext); + +cy_en_crypto_status_t Cy_Crypto_Core_Crc (cy_stc_crypto_context_crc_t *cryptoCrcContext); + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_CRC_H) */ + + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_des.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_des.c new file mode 100644 index 0000000000..4fd12ee002 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_des.c @@ -0,0 +1,208 @@ +/***************************************************************************//** +* \file cy_crypto_core_des.c +* \version 1.0 +* +* \brief +* This file provides the source code fro the API for the DES method +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_des.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_str.h" +#include "syslib/cy_syslib.h" +#include + + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) + + +uint8_t const cy_desCommands[2][2] = { + { CY_CRYPTO_DES_BLOCK_OPC, CY_CRYPTO_DES_BLOCK_INV_OPC }, /* DES mode */ + { CY_CRYPTO_TDES_BLOCK_OPC, CY_CRYPTO_TDES_BLOCK_INV_OPC } /* TDES mode */ +}; + +/* Table with DES weak keys */ +CY_ALIGN(4) uint8_t const cy_desWeakKeys[CY_CRYPTO_DES_WEAK_KEY_COUNT][CY_CRYPTO_DES_KEY_BYTE_LENGTH] = +{ + { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 }, + { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, + { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E }, + { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 }, + + { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E }, + { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 }, + { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 }, + { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 }, + { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE }, + { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 }, + { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 }, + { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E }, + { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE }, + { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E }, + { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE }, + { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 } +}; + + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Des_ProcessBlock +****************************************************************************//** +* +* Performs the DES or TDES block cipher. +* All addresses must be 4Byte aligned, +* srcBlock could overlap dstBlock. +* +* This function available for CM0+ core only. +* +* \param dirMode +* One of CRYPTO_ENCRYPT or CRYPTO_DECRYPT. +* +* \param keyPtr +* The pointer to the encryption/decryption key. +* +* \param dstBlockPtr +* The pointer to the cipher text. +* +* \param srcBlockPtr +* The pointer to the plain text. Must be 4-Byte aligned! +* +*******************************************************************************/ +void Cy_Crypto_Core_Des_ProcessBlock(cy_en_crypto_des_mode_t desMode, + cy_en_crypto_dir_mode_t dirMode, + uint32_t const *keyPtr, + uint32_t *dstBlockPtr, + uint32_t const *srcBlockPtr) +{ + Cy_Crypto_SetReg3Instr((uint32_t)keyPtr, + (uint32_t)srcBlockPtr, + (uint32_t)dstBlockPtr); + + /* Issue the DES_BLOCK instruction */ + Cy_Crypto_Run3ParamInstr(cy_desCommands[(uint8_t)desMode][(uint8_t)dirMode], + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT, + CY_CRYPTO_RSRC8_SHIFT); + + /* Wait until the AES instruction is complete */ + while (0uL != _FLD2VAL(CRYPTO_STATUS_DES_BUSY, CRYPTO->STATUS)) + { + } +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Des +****************************************************************************//** +* +* Performs DES operation on a Single Block. All addresses must be 4-Byte aligned. +* Ciphertext (dstBlockPtr) may overlap with plaintext (srcBlockPtr) +* This function is independent from the previous Crypto state. +* +* This function available for CM0+ core only. +* +* \param cryptoDesContext +* The pointer to the cy_stc_crypto_context_des_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Des(cy_stc_crypto_context_des_t *cryptoDesContext) +{ + uint32_t i; + cy_en_crypto_status_t status = CY_CRYPTO_SUCCESS; + + /* Check weak keys */ + for (i = 0; i < CY_CRYPTO_DES_WEAK_KEY_COUNT; i++) + { + if (memcmp(cryptoDesContext->keyPtr, (uint8_t*)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0) + { + status = CY_CRYPTO_DES_WEAK_KEY; + break; + } + } + + Cy_Crypto_Core_Des_ProcessBlock(CY_CRYPTO_DES_MODE_SINGLE, + cryptoDesContext->dirMode, + cryptoDesContext->keyPtr, + cryptoDesContext->dstPtr, + cryptoDesContext->srcPtr); + + return (status); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Tdes +****************************************************************************//** +* +* Performs TDES operation on a Single Block. All addresses must be 4-Byte aligned. +* Ciphertext (dstBlockPtr) may overlap with plaintext (srcBlockPtr) +* This function is independent from the previous Crypto state. +* +* This function available for CM0+ core only. +* +* \param cryptoDesContext +* The pointer to the cy_stc_crypto_context_des_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Tdes(cy_stc_crypto_context_des_t *cryptoDesContext) +{ + uint32_t i; + cy_en_crypto_status_t status = CY_CRYPTO_SUCCESS; + uint32_t *_keyPtr = cryptoDesContext->keyPtr; + + /* Check weak keys */ + for (i = 0; i < CY_CRYPTO_DES_WEAK_KEY_COUNT; i++) + { + if (memcmp(_keyPtr, (uint8_t*)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0) + { + status = CY_CRYPTO_DES_WEAK_KEY; + break; + } + + if (memcmp(&(_keyPtr[CY_CRYPTO_DES_KEY_BYTE_LENGTH]), + (uint8_t*)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0) + { + status = CY_CRYPTO_DES_WEAK_KEY; + break; + } + + if (memcmp(&(_keyPtr[2 * CY_CRYPTO_DES_KEY_BYTE_LENGTH]), + (uint8_t*)cy_desWeakKeys[i], CY_CRYPTO_DES_KEY_BYTE_LENGTH) == 0) + { + status = CY_CRYPTO_DES_WEAK_KEY; + break; + } + } + + Cy_Crypto_Core_Des_ProcessBlock(CY_CRYPTO_DES_MODE_TRIPLE, + cryptoDesContext->dirMode, + _keyPtr, + cryptoDesContext->dstPtr, + cryptoDesContext->srcPtr); + + return (status); +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_des.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_des.h new file mode 100644 index 0000000000..d5085031d9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_des.h @@ -0,0 +1,48 @@ +/***************************************************************************//** +* \file cy_crypto_core_des.h +* \version 1.0 +* +* \brief +* This file provides constant and parameters for the API for the DES method +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_CRYPTO_CORE_DES_H) +#define CY_CRYPTO_CORE_DES_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) + +#define CY_CRYPTO_DES_WEAK_KEY_COUNT (16) +#define CY_CRYPTO_DES_KEY_BYTE_LENGTH (8) + +typedef enum { + CY_CRYPTO_DES_MODE_SINGLE = 0, + CY_CRYPTO_DES_MODE_TRIPLE = 1 +} cy_en_crypto_des_mode_t; + +cy_en_crypto_status_t Cy_Crypto_Core_Des(cy_stc_crypto_context_des_t *cryptoDesContext); + +cy_en_crypto_status_t Cy_Crypto_Core_Tdes(cy_stc_crypto_context_des_t *cryptoDesContext); + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) */ +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_DES_H) */ + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_hmac.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_hmac.c new file mode 100644 index 0000000000..81b216792c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_hmac.c @@ -0,0 +1,244 @@ +/***************************************************************************//** +* \file cy_crypto_core_hmac.c +* \version 1.0 +* +* \brief +* This file provides the source code to the API for the HMAC method +* in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_hmac.h" +#include "crypto/cy_crypto_core_sha.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_str.h" +#include "syslib/cy_syslib.h" +#include + + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) + +#define CY_CRYPTO_HMAC_IPAD (0x36u) +#define CY_CRYPTO_HMAC_0PAD (0x5Cu) +#define CY_CRYPTO_HMAC_MAX_PAD_SIZE (128u) +#define CY_CRYPTO_HMAC_MAX_M0_KEY_SIZE (128u) + +typedef struct +{ + uint32_t *ipadPtr; + uint32_t *opadPtr; + uint32_t *m0KeyPtr; +} cy_stc_crypto_hmac_state_t; + + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Hmac_Init +****************************************************************************//** +* +* Initializes HMAC (Hash-based Message Authentication Code) calculation. +* Allocate two buffers (ipadPtr and opadPtr) for HMAC calculation. +* +* This function available for CM0+ core only. +* +* \param hmacStatePtr +* the pointer to the hmacStatePtr structure which stores internal variables +* for HMAC calculation. +* +* \param ipadPtr +* The memory buffer for HMAC calculation, the max used size = CRYPTO_HMAC_MAX_PAD_SIZE. +* +* \param opadPtr +* The memory buffer for HMAC calculation, the max used size = CRYPTO_HMAC_MAX_PAD_SIZE. +* +* * \param m0KeyPtr +* The memory buffer for HMAC calculation, the max used size = CRYPTO_HMAC_MAX_M0_KEY_SIZE. +* +*******************************************************************************/ +void Cy_Crypto_Core_Hmac_Init(cy_stc_crypto_hmac_state_t *hmacStatePtr, + uint32_t *ipadPtr, + uint32_t *opadPtr, + uint32_t *m0KeyPtr) +{ + hmacStatePtr->ipadPtr = ipadPtr; + hmacStatePtr->opadPtr = opadPtr; + hmacStatePtr->m0KeyPtr = m0KeyPtr; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Hmac_Calculate +****************************************************************************//** +* +* Starts HMAC (Hash-based Message Authentication Code) calculation. +* +* This function available for CM0+ core only. +* +* \param hmacStatePtr +* The pointer to the hmacStatePtr structure which stores internal variables +* for HMAC calculation. +* +* \param hashStatePtr +* The pointer to the hashStatePtr structure which stores internal variables +* of the SHA algorithm because it is used for HMAC calculation. +* +* \param keyPtr +* The pointer to the encryption key used in computing AES-CMAC. +* +* \param keyLength +* The size of the encryption key. +* +* \param messagePtr +* The pointer to the input message. +* +* \param messageSize +* The size of the input message. +* +* \param hmacPtr +* The pointer to the calculated HMAC. +* +*******************************************************************************/ +void Cy_Crypto_Core_Hmac_Calculate(cy_stc_crypto_hmac_state_t *hmacStatePtr, + cy_stc_crypto_sha_state_t *hashStatePtr, + uint32_t *keyPtr, + uint32_t keyLength, + uint32_t *messagePtr, + uint32_t messageSize, + uint32_t *hmacPtr) +{ + uint32_t i = 0uL; + uint8_t *ipadPtrTmp = (uint8_t*)hmacStatePtr->ipadPtr; + uint8_t *opadPtrTmp = (uint8_t*)hmacStatePtr->opadPtr; + uint8_t *m0KeyPtrTmp = (uint8_t*)hmacStatePtr->m0KeyPtr; + + + /* Steps 1-3 according to FIPS 198-1 */ + if (keyLength > hashStatePtr->blockSize) + { + /* The key is larger than the block size. Do a hash on the key. */ + Cy_Crypto_Core_Sha_Start (hashStatePtr); + Cy_Crypto_Core_Sha_Update (hashStatePtr, keyPtr, keyLength); + Cy_Crypto_Core_Sha_Finish (hashStatePtr, (uint32_t*)m0KeyPtrTmp, keyLength); + + /* Append zeros */ + memset((m0KeyPtrTmp + hashStatePtr->digestSize), 0x00u, + (hashStatePtr->blockSize - hashStatePtr->digestSize)); + } + else if (keyLength < hashStatePtr->blockSize) + { + /* If the key is shorter than the block, append zeros */ + memcpy(m0KeyPtrTmp, keyPtr, (uint16_t)keyLength); + memset((m0KeyPtrTmp + keyLength), 0x00u, (hashStatePtr->blockSize - keyLength)); + } + else + { + memcpy(m0KeyPtrTmp, keyPtr, keyLength); + } + + /* Steps 4 and 7 according to FIPS 198-1 */ + while (i < hashStatePtr->blockSize) + { + ipadPtrTmp[i] = CY_CRYPTO_HMAC_IPAD ^ m0KeyPtrTmp[i]; + opadPtrTmp[i] = CY_CRYPTO_HMAC_0PAD ^ m0KeyPtrTmp[i]; + i++; + } + + /* Step 6 according to FIPS 198-1 */ + Cy_Crypto_Core_Sha_Start (hashStatePtr); + Cy_Crypto_Core_Sha_ProcessBlock (hashStatePtr, (uint32_t*)ipadPtrTmp); + + /* Append a message */ + Cy_Crypto_Core_Sha_Update (hashStatePtr, messagePtr, messageSize); + Cy_Crypto_Core_Sha_Finish (hashStatePtr, (uint32_t*)ipadPtrTmp, (messageSize + hashStatePtr->blockSize)); + + /* Here is the ready part of HASH: Hash((Key^ipad)||text) */ + + /* Steps 8, 9 according to FIPS 198-1 */ + Cy_Crypto_Core_Sha_Start (hashStatePtr); + Cy_Crypto_Core_Sha_ProcessBlock (hashStatePtr, (uint32_t*)opadPtrTmp); + + /* Append HASH from Step 6 */ + Cy_Crypto_Core_Sha_Update (hashStatePtr, (uint32_t*)ipadPtrTmp, hashStatePtr->digestSize); + Cy_Crypto_Core_Sha_Finish (hashStatePtr, hmacPtr, (hashStatePtr->digestSize + hashStatePtr->blockSize)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Hmac_Free +****************************************************************************//** +* +* Clears the used memory buffers. +* +* This function available for CM0+ core only. +* +* \param hmacStatePtr +* The pointer to the HMAC context. +* +*******************************************************************************/ +void Cy_Crypto_Core_Hmac_Free(cy_stc_crypto_hmac_state_t *hmacStatePtr) +{ + /* Clear the memory buffer. */ + memset(hmacStatePtr->ipadPtr, 0x00u, CY_CRYPTO_HMAC_MAX_PAD_SIZE); + memset(hmacStatePtr->opadPtr, 0x00u, CY_CRYPTO_HMAC_MAX_PAD_SIZE); + memset(hmacStatePtr->m0KeyPtr, 0x00u, CY_CRYPTO_HMAC_MAX_M0_KEY_SIZE); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Hmac +****************************************************************************//** +* +* Performs HMAC calculation. +* +* This function available for CM0+ core only. +* +* \param cryptoShaContext +* The pointer to the stc_crypto_context_t structure which stores all internal variables +* for Crypto driver. +* +* \return +* A Crypto status \ref en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Hmac(cy_stc_crypto_context_sha_t *cryptoShaContext) +{ + uint32_t *messageTmpPtr = cryptoShaContext->messagePtr; + uint32_t messageSizeTmp = cryptoShaContext->messageSize; + uint32_t *hmacPtr = cryptoShaContext->dstPtr; + cy_en_crypto_sha_mode_t modeTmp = cryptoShaContext->mode; + uint32_t *keyTmpPtr = cryptoShaContext->keyPtr; + uint32_t keyLengthTmp = cryptoShaContext->keyLength; + + /* Allocating internal variables into the CRYPTO SRAM Buffer */ + uint32_t *blockPtr = (uint32_t*)CRYPTO->MEM_BUFF; + uint32_t *hashPtr = (uint32_t*)((uint8_t*)blockPtr + CY_CRYPTO_MAX_BLOCK_SIZE); + uint32_t *roundMemPtr = (uint32_t*)((uint8_t*)hashPtr + CY_CRYPTO_MAX_HASH_SIZE); + uint32_t *ipadPtr = (uint32_t*)((uint8_t*)roundMemPtr + CY_CRYPTO_MAX_ROUND_MEM_SIZE); + uint32_t *opadPtr = (uint32_t*)((uint8_t*)ipadPtr + CY_CRYPTO_HMAC_MAX_PAD_SIZE); + uint32_t *m0KeyPtr = (uint32_t*)((uint8_t*)opadPtr + CY_CRYPTO_HMAC_MAX_PAD_SIZE); + + cy_stc_crypto_hmac_state_t *hmacStatePtr = (cy_stc_crypto_hmac_state_t* )((uint8_t*)m0KeyPtr + CY_CRYPTO_MAX_BLOCK_SIZE); + cy_stc_crypto_sha_state_t *hashStatePtr = (cy_stc_crypto_sha_state_t* )((uint8_t*)hmacStatePtr + sizeof(cy_stc_crypto_hmac_state_t)); + + Cy_Crypto_Core_Sha_Init (hashStatePtr, (uint8_t*)blockPtr, hashPtr, roundMemPtr, modeTmp); + Cy_Crypto_Core_Hmac_Init (hmacStatePtr, ipadPtr, opadPtr, m0KeyPtr); + + Cy_Crypto_Core_Hmac_Calculate (hmacStatePtr, hashStatePtr, keyTmpPtr, keyLengthTmp, messageTmpPtr, messageSizeTmp, hmacPtr); + + Cy_Crypto_Core_Hmac_Free (hmacStatePtr); + Cy_Crypto_Core_Sha_Free (hashStatePtr); + + return (CY_CRYPTO_SUCCESS); +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_hmac.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_hmac.h new file mode 100644 index 0000000000..51f08e1b14 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_hmac.h @@ -0,0 +1,37 @@ +/***************************************************************************//** +* \file cy_crypto_cora_hmac.h +* \version 1.0 +* +* \brief +* This file provides constants and function prototypes +* for the API for the SHA method in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CORE_HMAC_H) +#define CY_CRYPTO_CORE_HMAC_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) + + +cy_en_crypto_status_t Cy_Crypto_Core_Hmac(cy_stc_crypto_context_sha_t *cryptoContext); + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_HMAC_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_instructions.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_instructions.h new file mode 100644 index 0000000000..2b91da82dc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_instructions.h @@ -0,0 +1,180 @@ +/***************************************************************************//** +* \file cy_crypto_core_instructions.h +* \version 1.0 +* +* \brief +* This file provides internal (not public) constant and parameters +* for the Crypto server. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CORE_INSTRUCTIONS_H) +#define CY_CRYPTO_CORE_INSTRUCTIONS_H + +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if (CPUSS_CRYPTO_PRESENT == 1) + + +/*************************************** +* Crypto IP opcodes +***************************************/ + +#define CY_CRYPTO_REGFILE_R0 (0x00uL) +#define CY_CRYPTO_REGFILE_R1 (0x01uL) +#define CY_CRYPTO_REGFILE_R2 (0x02uL) +#define CY_CRYPTO_REGFILE_R3 (0x03uL) +#define CY_CRYPTO_REGFILE_R4 (0x04uL) +#define CY_CRYPTO_REGFILE_R5 (0x05uL) +#define CY_CRYPTO_REGFILE_R6 (0x06uL) +#define CY_CRYPTO_REGFILE_R7 (0x07uL) +#define CY_CRYPTO_REGFILE_R8 (0x08uL) +#define CY_CRYPTO_REGFILE_R9 (0x09uL) +#define CY_CRYPTO_REGFILE_R10 (0x0AuL) +#define CY_CRYPTO_REGFILE_R11 (0x0BuL) +#define CY_CRYPTO_REGFILE_R12 (0x0CuL) +#define CY_CRYPTO_REGFILE_R13 (0x0DuL) +#define CY_CRYPTO_REGFILE_R14 (0x0EuL) +#define CY_CRYPTO_REGFILE_R15 (0x0FuL) + + +#define CY_CRYPTO_SET_REG1_OPC (0x40u) +#define CY_CRYPTO_SET_REG2_OPC (0x41u) +#define CY_CRYPTO_SET_REG3_OPC (0x42u) +#define CY_CRYPTO_SET_REG4_OPC (0x43u) + +#define CY_CRYPTO_RSRC0_SHIFT (0u) +#define CY_CRYPTO_RSRC4_SHIFT (4u) +#define CY_CRYPTO_RSRC8_SHIFT (8u) +#define CY_CRYPTO_RSRC12_SHIFT (12u) +#define CY_CRYPTO_RSRC20_SHIFT (20u) +#define CY_CRYPTO_OPCODE_POS (24u) +#define CY_CRYPTO_RSRC26_SHIFT (26u) +#define CY_CRYPTO_RSRC30_SHIFT (30u) + +#define CY_CRYPTO_AES_BLOCK_OPC (0x44u) +#define CY_CRYPTO_AES_BLOCK_INV_OPC (0x45u) +#define CY_CRYPTO_AES_KEY_OPC (0x46u) +#define CY_CRYPTO_AES_KEY_INV_OPC (0x47u) +#define CY_CRYPTO_AES_XOR_OPC (0x48u) + +#define CY_CRYPTO_SHA_OPC (0x4cu) + +#define CY_CRYPTO_STR_MEMCPY_OPC (0x50u) +#define CY_CRYPTO_STR_MEMSET_OPC (0x51u) +#define CY_CRYPTO_STR_MEMCMP_OPC (0x52u) +#define CY_CRYPTO_STR_MEMXOR_OPC (0x53u) + +#define CY_CRYPTO_CRC_OPC (0x58u) + +#define CY_CRYPTO_PRNG_OPC (0x5cu) + +#define CY_CRYPTO_TRNG_OPC (0x60u) + +#define CY_CRYPTO_DES_BLOCK_OPC (0x70u) +#define CY_CRYPTO_DES_BLOCK_INV_OPC (0x71u) + +#define CY_CRYPTO_TDES_BLOCK_OPC (0x72u) +#define CY_CRYPTO_TDES_BLOCK_INV_OPC (0x73u) + +#define CY_CRYPTO_SYNC_OPC (0x7fu) + +#define CY_CRYPTO_FIFODEPTH (0x08u) + +/* Vector Unit instructions */ +#define CY_CRYPTO_VU_ALLOC_MEM_OPC (0x12u) +#define CY_CRYPTO_VU_FREE_MEM_OPC (0x13u) + +/* Instructions with register operand only, category I */ +#define CY_CRYPTO_VU_SET_REG_OPC (0x80u) +#define CY_CRYPTO_VU_MOV_REG_OPC (0x02u) +#define CY_CRYPTO_VU_LD_REG_OPC (0x00u) +#define CY_CRYPTO_VU_ST_REG_OPC (0x01u) + +/* Instructions with register operand only, category III */ +#define CY_CRYPTO_VU_SWAP_REG_OPC (0x03u) + +/* Instructions with register operand only, category IV */ +#define CY_CRYPTO_VU_MOV_REG_TO_STATUS_OPC (0x04u) + +/* Instructions with register operand only, category V */ +#define CY_CRYPTO_VU_MOV_STATUS_TO_REG_OPC (0x05u) + +/* Instructions with register operand only, category VI */ +#define CY_CRYPTO_VU_PUSH_REG_OPC (0x10u) +#define CY_CRYPTO_VU_POP_REG_OPC (0x11u) + +/* Instructions with register operand only, category VII */ +#define CY_CRYPTO_VU_ADD_REG_OPC (0x06u) +#define CY_CRYPTO_VU_SUB_REG_OPC (0x07u) +#define CY_CRYPTO_VU_OR_REG_OPC (0x08u) +#define CY_CRYPTO_VU_AND_REG_OPC (0x09u) +#define CY_CRYPTO_VU_XOR_REG_OPC (0x0Au) +#define CY_CRYPTO_VU_NOR_REG_OPC (0x0Bu) +#define CY_CRYPTO_VU_NAND_REG_OPC (0x0Cu) +#define CY_CRYPTO_VU_MIN_REG_OPC (0x0Du) +#define CY_CRYPTO_VU_MAX_REG_OPC (0x0Eu) + +/* Instructions with mixed operands, category I */ +#define CY_CRYPTO_VU_LSL_OPC (0x20u) +#define CY_CRYPTO_VU_LSR_OPC (0x24u) + +/* Instructions with mixed operands, category II */ +#define CY_CRYPTO_VU_LSL1_OPC (0x21u) +#define CY_CRYPTO_VU_LSL1_WITH_CARRY_OPC (0x22u) +#define CY_CRYPTO_VU_LSR1_OPC (0x25u) +#define CY_CRYPTO_VU_LSR1_WITH_CARRY_OPC (0x26u) + +/* Instructions with mixed operands, category III */ +#define CY_CRYPTO_VU_SET_BIT_OPC (0x2Cu) +#define CY_CRYPTO_VU_CLR_BIT_OPC (0x2Du) +#define CY_CRYPTO_VU_INV_BIT_OPC (0x2Eu) + +/* Instructions with mixed operands, category IV */ +#define CY_CRYPTO_VU_GET_BIT_OPC (0x2Fu) + +/* Instructions with mixed operands, category V */ +#define CY_CRYPTO_VU_CLSAME_OPC (0x28u) +#define CY_CRYPTO_VU_CTSAME_OPC (0x29u) + +/* Instructions with memory buffer operands, category I */ +#define CY_CRYPTO_VU_SET_TO_ZERO_OPC (0x34u) +#define CY_CRYPTO_VU_SET_TO_ONE_OPC (0x35u) + +/* Instructions with memory buffer operands, category II */ +#define CY_CRYPTO_VU_MOV_OPC (0x30u) +#define CY_CRYPTO_VU_XSQUARE_OPC (0x31u) + +/* Instructions with memory buffer operands, category III */ +#define CY_CRYPTO_VU_CMP_SUB_OPC (0x3Du) +#define CY_CRYPTO_VU_CMP_DEFREE_OPC (0x3Eu) + +/* Instructions with memory buffer operands, category IV */ +#define CY_CRYPTO_VU_TST_OPC (0x3fu) +#define CY_CRYPTO_VU_XMUL_OPC (0x32u) +#define CY_CRYPTO_VU_UMUL_OPC (0x33u) +#define CY_CRYPTO_VU_ADD_OPC (0x36u) +#define CY_CRYPTO_VU_SUB_OPC (0x37u) +#define CY_CRYPTO_VU_OR_OPC (0x38u) +#define CY_CRYPTO_VU_AND_OPC (0x39u) +#define CY_CRYPTO_VU_XOR_OPC (0x3Au) +#define CY_CRYPTO_VU_NOR_OPC (0x3Bu) +#define CY_CRYPTO_VU_NAND_OPC (0x3Cu) + + +#endif /* #if (CPUSS_CRYPTO_PRESENT == 1) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_INSTRUCTIONS_H) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_prng.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_prng.c new file mode 100644 index 0000000000..69e2dc1cf1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_prng.c @@ -0,0 +1,99 @@ +/***************************************************************************//** +* \file cy_crypto_core_prng.c +* \version 1.0 +* +* \brief +* This file provides the source code to the API for the PRNG +* in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_prng.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "crypto/cy_crypto_core_util.h" +#include "syslib/cy_syslib.h" + + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) + + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Prng_Init +****************************************************************************//** +* +* Initializes the PRND parameters. +* Invoking this function causes a restart of the pseudo-random sequence. +* +* This function available for CM0+ core only. +* +* \param cryptoPrngContext +* The pointer to thestc_crypto_context_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Prng_Init(cy_stc_crypto_context_prng_t *cryptoPrngContext) +{ + CRYPTO->PR_LFSR_CTL0 = (uint32_t)(_VAL2FLD(CRYPTO_PR_LFSR_CTL0_LFSR32, + (uint32_t)cryptoPrngContext->lfsr32InitState)); + + CRYPTO->PR_LFSR_CTL1 = (uint32_t)(_VAL2FLD(CRYPTO_PR_LFSR_CTL1_LFSR31, + (uint32_t)cryptoPrngContext->lfsr31InitState)); + + CRYPTO->PR_LFSR_CTL2 = (uint32_t)(_VAL2FLD(CRYPTO_PR_LFSR_CTL2_LFSR29, + (uint32_t)cryptoPrngContext->lfsr29InitState)); + + return (CY_CRYPTO_SUCCESS); +} + +/******************************************************************************* +* Function Name: Crypto_Core_Prng +****************************************************************************//** +* +* Generates a Pseudo Random Number. +* +* This function available for CM0+ core only. +* +* \param cryptoPrngContext +* The pointer to the stc_crypto_context_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Prng(cy_stc_crypto_context_prng_t *cryptoPrngContext) +{ + CRYPTO->INSTR_FF_WR = (uint32_t)(CY_CRYPTO_SET_REG1_OPC << CY_CRYPTO_OPCODE_POS); + + CRYPTO->INSTR_FF_WR = (uint32_t)cryptoPrngContext->max; + + CRYPTO->INSTR_FF_WR = (uint32_t)((uint32_t)CY_CRYPTO_PRNG_OPC << CY_CRYPTO_OPCODE_POS); + + /* Wait until the PRNG instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_PR_BUSY, CRYPTO->STATUS)) + { + } + + *cryptoPrngContext->prngNumPtr = (uint32_t)_FLD2VAL(CRYPTO_PR_RESULT_DATA32, CRYPTO->PR_RESULT); + + return (CY_CRYPTO_SUCCESS); +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_prng.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_prng.h new file mode 100644 index 0000000000..44a211a5cd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_prng.h @@ -0,0 +1,39 @@ +/***************************************************************************//** +* \file cy_crypto_core_prng.h +* \version 1.0 +* +* \brief +* This file provides provides constant and parameters for the API of the PRNG +* in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CORE_PRNG_H) +#define CY_CRYPTO_CORE_PRNG_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) + + +cy_en_crypto_status_t Cy_Crypto_Core_Prng_Init (cy_stc_crypto_context_prng_t *cryptoPrngContext); +cy_en_crypto_status_t Cy_Crypto_Core_Prng (cy_stc_crypto_context_prng_t *cryptoPrngContext); + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_PRNG_H) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_rsa.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_rsa.c new file mode 100644 index 0000000000..e3681c4b52 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_rsa.c @@ -0,0 +1,993 @@ +/***************************************************************************//** +* \file cy_crypto_core_rsa.c +* \version 1.0 +* +* \brief +* This file provides the source code to the API to calculate +* a signature by the RSA method in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_rsa.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_vu_hw.h" +#include "crypto/cy_crypto_core_vu.h" +#include "crypto/cy_crypto_core_sha.h" +#include "syslib/cy_syslib.h" +#include + + +#if (CY_CPU_CORTEX_M0P) + +#define CY_CRYPTO_SHA1_PADDING_SIZE (15u) +#define CY_CRYPTO_SHA256_512_PADDING_SIZE (19u) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) + +/* Functions prototypes */ +void Cy_Crypto_Core_Rsa_MontCoeff(uint32_t modDerReg, uint32_t modReg, uint32_t size); +void Cy_Crypto_Core_Rsa_BarrettGetU(uint32_t barrettUReg, uint32_t modReg, uint32_t size); +void Cy_Crypto_Core_Rsa_BarretRed(uint32_t resultReg, uint32_t aReg, uint32_t barrettUReg, uint32_t modReg, uint32_t size); +void Cy_Crypto_Core_Rsa_MontTransform(uint32_t z, uint32_t a, uint32_t barrett_u, uint32_t mod, uint32_t size); +void Cy_Crypto_Core_Rsa_MontMul(uint32_t z, uint32_t a, uint32_t b, uint32_t mont_mod_der, uint32_t mod, uint32_t size); + +void Cy_Crypto_Core_Rsa_expModByMont(uint32_t y, + uint32_t x, + uint32_t e, + uint32_t n, + uint32_t barretCoef, + uint32_t inverseModulo, + uint32_t rBar, + uint32_t size); + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CY_CRYPTO_USER_PKCS1_5 == 1)) + +/* Encodings for hash functions */ + +#if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) +static const uint8_t Sha1EncStr[CY_CRYPTO_SHA1_PADDING_SIZE] = +{ + 0x14u, 0x04u, 0x00u, 0x05u, + 0x1Au, 0x02u, 0x03u, 0x0Eu, 0x2Bu, 0x05u, 0x06u, 0x09u, + 0x30u, 0x21u, 0x30u +}; +#endif /* #if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) +static const uint8_t Sha224EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = +{ + 0x1Cu, 0x04u, 0x00u, 0x05u, 0x04u, 0x02u, 0x04u, 0x03u, + 0x65u, 0x01u, 0x48u, 0x86u, 0x60u, 0x09u, 0x06u, 0x0du, + 0x30u, 0x2Du, 0x30u +}; + +static const uint8_t Sha256EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = +{ + 0x20u, 0x04u, 0x00u, 0x05u, 0x01u, 0x02u, 0x04u, 0x03u, + 0x65u, 0x01u, 0x48u, 0x86u, 0x60u, 0x09u, 0x06u, 0x0du, + 0x30u, 0x31u, 0x30u +}; +#endif /* #if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) +static const uint8_t Sha384EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = +{ + 0x30u, 0x04u, 0x00u, 0x05u, 0x02u, 0x02u, 0x04u, 0x03u, + 0x65u, 0x01u, 0x48u, 0x86u, 0x60u, 0x09u, 0x06u, 0x0du, + 0x30u, 0x41u, 0x30u +}; + +static const uint8_t Sha512EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = +{ + 0x40u, 0x04u, 0x00u, 0x05u, 0x03u, 0x02u, 0x04u, 0x03u, + 0x65u, 0x01u, 0x48u, 0x86u, 0x60u, 0x09u, 0x06u, 0x0du, + 0x30u, 0x51u, 0x30u +}; + +static const uint8_t Sha512_224EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = +{ + 0x1Cu, 0x04u, 0x00u, 0x05u, 0x05u, 0x02u, 0x04u, 0x03u, + 0x65u, 0x01u, 0x48u, 0x86u, 0x60u, 0x09u, 0x06u, 0x0du, + 0x30u, 0x2Du, 0x30u +}; + +static const uint8_t Sha512_256EncStr[CY_CRYPTO_SHA256_512_PADDING_SIZE] = +{ + 0x20u, 0x04u, 0x00u, 0x05u, 0x06u, 0x02u, 0x04u, 0x03u, + 0x65u, 0x01u, 0x48u, 0x86u, 0x60u, 0x09u, 0x06u, 0x0du, + 0x30u, 0x31u, 0x30u +}; +#endif /* #if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) */ + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_RsaVerify +****************************************************************************//** +* +* RSA verification with checks for content, paddings and signature format. +* SHA digest of the message and decrypted message should be calculated before. +* Supports only PKCS1-v1_5 format, inside of this format supported padding +* using only SHA, cases with MD2 and MD5 are not supported. +* PKCS1-v1_5 described here, page 31: +* http://www.emc.com/collateral/white-papers/h11300-pkcs-1v2-2-rsa-cryptography-standard-wp.pdf +* +* Returns the verification result \ref cy_en_crypto_rsa_ver_result_t. +* +* \param cryptoContextPtr +* Pointer to the RSA context +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_RsaVerify(cy_stc_crypto_context_rsa_ver_t *cryptoContextPtr) +{ + cy_en_crypto_status_t result = CY_CRYPTO_SUCCESS; + + cy_en_crypto_sha_mode_t _digestType = cryptoContextPtr->digestType; + uint8_t *_digestPtr = (uint8_t*)cryptoContextPtr->hashPtr; + uint8_t *_decryptedSignaturePtr = (uint8_t*)cryptoContextPtr->decryptedSignaturePtr; + uint32_t _decryptedSignatureLength = cryptoContextPtr->decryptedSignatureLength; + cy_en_crypto_rsa_ver_result_t *_verResult = cryptoContextPtr->verResult; + + uint8_t *psBeginPtr; + uint8_t *encodingArrPtr = NULL; + uint32_t encodingArrSize = 0; + uint32_t digestSize = 0; + uint32_t i; + int32_t psLength; + int32_t cmpRes = 0; + + + switch (_digestType) + { + +#if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) + case CY_CRYPTO_MODE_SHA1: + encodingArrPtr = (uint8_t*)Sha1EncStr; + encodingArrSize = sizeof(Sha1EncStr); + digestSize = CY_CRYPTO_SHA1_DIGEST_SIZE; + break; +#endif /* #if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) + case CY_CRYPTO_MODE_SHA224: + encodingArrPtr = (uint8_t*)Sha224EncStr; + encodingArrSize = sizeof(Sha224EncStr); + digestSize = CY_CRYPTO_SHA224_DIGEST_SIZE; + break; + + case CY_CRYPTO_MODE_SHA256: + encodingArrPtr = (uint8_t*)Sha256EncStr; + encodingArrSize = sizeof(Sha256EncStr); + digestSize = CY_CRYPTO_SHA256_DIGEST_SIZE; + break; +#endif /* #if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) + case CY_CRYPTO_MODE_SHA384: + encodingArrPtr = (uint8_t*)Sha384EncStr; + encodingArrSize = sizeof(Sha384EncStr); + digestSize = CY_CRYPTO_SHA384_DIGEST_SIZE; + break; + + case CY_CRYPTO_MODE_SHA512: + encodingArrPtr = (uint8_t*)Sha512EncStr; + encodingArrSize = sizeof(Sha512EncStr); + digestSize = CY_CRYPTO_SHA512_DIGEST_SIZE; + break; + + case CY_CRYPTO_MODE_SHA512_224: + encodingArrPtr = (uint8_t*)Sha512_224EncStr; + encodingArrSize = sizeof(Sha512_224EncStr); + digestSize = CY_CRYPTO_SHA512_224_DIGEST_SIZE; + break; + + case CY_CRYPTO_MODE_SHA512_256: + encodingArrPtr = (uint8_t*)Sha512_256EncStr; + encodingArrSize = sizeof(Sha512_256EncStr); + digestSize = CY_CRYPTO_SHA512_256_DIGEST_SIZE; + break; +#endif /* #if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) */ + + default: + break; + } + + /* Fail by default */ + *_verResult = CY_CRYPTO_RSA_VERIFY_FAIL; + + /* Check size of decrypted message */ + if (_decryptedSignatureLength < (encodingArrSize + digestSize + 11)) + { + cmpRes = 1; /* further checking is not needed */ + } + + psLength = _decryptedSignatureLength - digestSize - encodingArrSize - 3; + + /* Address of start of T string (0xFFs) in padding */ + psBeginPtr = _decryptedSignaturePtr + _decryptedSignatureLength - 3; + + /* Check whether the begin of message is 0x00, 0x01 and after PS string (before T string) is 0x00 byte.*/ + if ( (0 != cmpRes) || + (0x00 != *(psBeginPtr + 2)) || + (0x01 != *(psBeginPtr + 1)) || + (0x00 != *(_decryptedSignaturePtr + _decryptedSignatureLength - psLength - 3)) ) + { + cmpRes = 1; /* Further checking is not needed */ + } + + /* Check FFs */ + if (0 == cmpRes ) + { + for (i = psLength; i > 0; i--) + { + if (0xFF != *(psBeginPtr - i + 1)) + { + cmpRes = 1; /* Further checking is not needed */ + break; + } + } + } + + /* Check the padding (T string) */ + if (0 == cmpRes) + { + cmpRes = memcmp(encodingArrPtr, + (_decryptedSignaturePtr + digestSize), + encodingArrSize); + } + + /* Check the digest */ + if (0 == cmpRes) + { + _decryptedSignaturePtr = _decryptedSignaturePtr + digestSize - 1; + for (i = digestSize; i > 0; i--) + { + if( *_decryptedSignaturePtr != *_digestPtr ) + { + cmpRes = 1; /* Further checking is not needed */ + break; + } + _decryptedSignaturePtr--; + _digestPtr++; + } + } + + if (0 == cmpRes ) + { + *_verResult = CY_CRYPTO_RSA_VERIFY_SUCCESS; + } + + return (result); +} + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CY_CRYPTO_USER_PKCS1_5 == 1)) */ + + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Rsa_MontCoeff +****************************************************************************//** +* +* Calculation of Montgomery coefficients for Montgomery multiplication in GF(p). +* +* Reference: "Montgomery Multiplication", H. S. Warren, Jr., July 2012 +* Reference: http://www.hackersdelight.org/MontgomeryMultiplication.pdf +* +* GCD method is used, reference: +* https://en.wikipedia.org/wiki/Binary_GCD_algorithm +* +* Inputs: modulus n, k = number of bits in n; +* Outputs: R^-1 and n' which allows equation: R*R^-1 - n*n' = 1, +* where R = 1 << size. +* +* Leaf function. +* +* \param modDerReg +* Register index for Montgomery coefficient value. +* +* \param modReg +* Register index for modulo value. +* +* \param size +* Size of modulo, in Bits. +* +*******************************************************************************/ +void Cy_Crypto_Core_Rsa_MontCoeff(uint32_t modDerReg, uint32_t modReg, uint32_t size) +{ + uint32_t my_mod = 9; + uint32_t tmp = 10; + uint32_t a = 11; + uint32_t b = 12; + uint32_t u = 13; + uint32_t v = 14; + + uint16_t status; + uint16_t a_zero; + uint16_t u_even; + + CY_CRYPTO_VU_PUSH_REG (); + + CY_CRYPTO_VU_LD_REG (v, modDerReg); + CY_CRYPTO_VU_LD_REG (my_mod, modReg); + + CY_CRYPTO_VU_ALLOC_MEM (a, size); + CY_CRYPTO_VU_ALLOC_MEM (b, size); + CY_CRYPTO_VU_ALLOC_MEM (u, size); + + CY_CRYPTO_VU_SET_TO_ONE (u); + CY_CRYPTO_VU_SET_TO_ZERO (v); + + CY_CRYPTO_VU_SET_TO_ZERO (a); + CY_CRYPTO_VU_SET_REG (tmp, (size - 1), 1); + + CY_CRYPTO_VU_SET_BIT (a, tmp); + CY_CRYPTO_VU_MOV (b, my_mod); + + while(1) + { + Cy_Crypto_Core_WaitForReady(); + + CY_CRYPTO_VU_TST(a); + + status = Cy_Crypto_Core_Vu_StatusRead(); + a_zero = status & (1 << CY_CRYPTO_VU_STATUS_ZERO); + + if(a_zero != 0) + { + break; + } + + CY_CRYPTO_VU_LSR1(a, a); + + CY_CRYPTO_VU_TST(u); + status = Cy_Crypto_Core_Vu_StatusRead(); + u_even = status & (1 << CY_CRYPTO_VU_STATUS_EVEN); + + if(u_even != 0) + { + CY_CRYPTO_VU_LSR1(u, u); + CY_CRYPTO_VU_LSR1(v, v); + } + else + { + CY_CRYPTO_VU_ADD(u, u, b); + CY_CRYPTO_VU_LSR1_WITH_CARRY(u, u); + CY_CRYPTO_VU_LSR1(v, v); + CY_CRYPTO_VU_SET_BIT(v, tmp); + } + } + + CY_CRYPTO_VU_FREE_MEM((1 << a) | (1 << b) | (1 << u)); + + CY_CRYPTO_VU_POP_REG(); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Rsa_BarrettGetU +****************************************************************************//** +* +* Calculation of Barrett coefficient for Barrett reduction in GF(p). +* +* The function reduces the size of the Barrett coefficient by removing leading '0' bits. +* This improves the performance of the Barrett reduction (faster multiplication). +* (1 << bit_size) > mod > (1 << (bit_size-1)) +* +* barrett_u = (1 << (2 * size)) / mod NO!!! leading '1' Barrett bit. +* +* Leaf function. +* +* \param barrettUReg +* Register index for Barrett reduction value. +* +* \param modReg +* Register index for modulo value. +* +* \param +* Size modulo size in Bits. +* +*******************************************************************************/ +void Cy_Crypto_Core_Rsa_BarrettGetU(uint32_t barrettUReg, uint32_t modReg, uint32_t size) +{ + uint32_t dividend = 0; + uint32_t t = 1; + uint32_t temp = 2; + uint32_t sh = 3; + int32_t i; + + CY_CRYPTO_VU_ALLOC_MEM(dividend, size+1); + CY_CRYPTO_VU_ALLOC_MEM(t, size+1); + CY_CRYPTO_VU_ALLOC_MEM(temp, size+1); + + /* (1 << size) – there is probably a more efficient way to initialize this */ + CY_CRYPTO_VU_SET_REG (sh, size, 1); + CY_CRYPTO_VU_SET_TO_ZERO (dividend); + CY_CRYPTO_VU_SET_BIT (dividend, sh); + + CY_CRYPTO_VU_MOV (temp, dividend); + + CY_CRYPTO_VU_SET_TO_ZERO (barrettUReg); + + for (i = size; i >= 0; i--) + { + /* C = (a >= b) */ + CY_CRYPTO_VU_SUB (t, dividend, modReg); + CY_CRYPTO_VU_COND_SWAP_REG (CY_CRYPTO_VU_COND_CS, dividend, t); + CY_CRYPTO_VU_COND_XOR (CY_CRYPTO_VU_COND_CS, barrettUReg, barrettUReg, temp); + CY_CRYPTO_VU_LSL1 (dividend, dividend); + CY_CRYPTO_VU_LSR1 (temp, temp); + } + + CY_CRYPTO_VU_FREE_MEM((1 << dividend) | (1 << temp) | (1 << t)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Rsa_BarretRed +****************************************************************************//** +* +* Barrett reduction in GF(p). +* +* z = a_double mod modulo +* +* t[b-1:0] = z_double >> size +* t = t * barrett_u +* t = t + ((z_double >> size) << size) "for leading '1' Barrett bit" +* t = t >> size +* t = t * mod +* u = z_double - t +* u = IF (u >= mod) u = u - mod +* +* Leaf function. +* +* \param resultReg +* Register index for Barrett reduced value. +* +* \param aReg +* Register index for non reduced value. +* +* \param barrettUReg +* Register index for Barrett reduction value. +* +* \param modReg +* Register index for modulo value. +* +* \param size +* Bit size. +* +*******************************************************************************/ +void Cy_Crypto_Core_Rsa_BarretRed(uint32_t resultReg, uint32_t aReg, uint32_t barrettUReg, uint32_t modReg, uint32_t size) +{ + uint32_t sh = 0; + uint32_t t_double = 1; + uint32_t z_double = 2; + + CY_CRYPTO_VU_ALLOC_MEM (t_double, 2 * size); + CY_CRYPTO_VU_ALLOC_MEM (z_double, 2 * size); + + CY_CRYPTO_VU_SET_REG (sh, size, 1); + + + CY_CRYPTO_VU_LSR (t_double, aReg, sh); + + CY_CRYPTO_VU_UMUL (z_double, t_double, barrettUReg); + + CY_CRYPTO_VU_LSL (t_double, t_double, sh); + + CY_CRYPTO_VU_ADD (z_double, z_double, t_double); + + CY_CRYPTO_VU_LSR (z_double, z_double, sh); + + CY_CRYPTO_VU_UMUL (t_double, z_double, modReg); + + CY_CRYPTO_VU_SUB (z_double, aReg, t_double); + + /* C = (a >= b) */ + CY_CRYPTO_VU_CMP_SUB (z_double, modReg); + CY_CRYPTO_VU_COND_SUB (CY_CRYPTO_VU_COND_CS, z_double, z_double, modReg); + + CY_CRYPTO_VU_CMP_SUB (z_double, modReg); + CY_CRYPTO_VU_COND_SUB (CY_CRYPTO_VU_COND_CS, z_double, z_double, modReg); + + CY_CRYPTO_VU_MOV (resultReg, z_double); + + CY_CRYPTO_VU_FREE_MEM ((1 << z_double) | (1 << t_double)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Rsa_MontTransform +****************************************************************************//** +* +* \brief Conversion to Montgomery representation. +* +* z = (a << size) % mod +* +* \param z +* Register index for Montgomery representation value. +* +* \param a +* Register index for regular representation value. +* +* \param barrett_u +* Register index for Barrett reduction value. +* +* \param mod +* Register index for modulo value. +* +* \param size +* Bit size. +* +*******************************************************************************/ +void Cy_Crypto_Core_Rsa_MontTransform(uint32_t z, uint32_t a, uint32_t barrett_u, uint32_t mod, uint32_t size) +{ + uint32_t sh = 0; + uint32_t t1_plus2 = 1; + uint32_t t2_plus2 = 0; + uint32_t t_double = 2; + uint32_t a_double = 3; + + CY_CRYPTO_VU_ALLOC_MEM (t_double, 2 * size); + CY_CRYPTO_VU_ALLOC_MEM (a_double, 2 * size); + + CY_CRYPTO_VU_SET_REG (sh, size, 1); + + CY_CRYPTO_VU_UMUL (t_double, a, barrett_u); + CY_CRYPTO_VU_LSR (a_double, t_double, sh); + + CY_CRYPTO_VU_UMUL (t_double, a_double, mod); + + CY_CRYPTO_VU_LSL (a_double, a, sh); + + CY_CRYPTO_VU_ALLOC_MEM (t2_plus2, size + 2); + + CY_CRYPTO_VU_SUB (t2_plus2, a_double, t_double); + + CY_CRYPTO_VU_FREE_MEM ((1 << a_double) | (1 << t_double)); + CY_CRYPTO_VU_ALLOC_MEM (t1_plus2, size + 2); + + /* Check CARRY = (a >= b) */ + CY_CRYPTO_VU_SUB (t1_plus2, t2_plus2, mod); + CY_CRYPTO_VU_COND_SWAP_REG (CY_CRYPTO_VU_COND_CC, t1_plus2, t2_plus2); + + /* Check CARRY = (a >= b) */ + CY_CRYPTO_VU_SUB (t2_plus2, t1_plus2, mod); + CY_CRYPTO_VU_COND_MOV (CY_CRYPTO_VU_COND_CC, z, t1_plus2); + CY_CRYPTO_VU_COND_MOV (CY_CRYPTO_VU_COND_CS, z, t2_plus2); + + CY_CRYPTO_VU_FREE_MEM ((1 << t2_plus2) | (1 << t1_plus2)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Rsa_MontMul +****************************************************************************//** +* +* Montgomery multiplication in GF(p). +* +* z = a * b * r % mod +* +* t = mont_a * mont_b +* u = t * mont_mod_der "only lower 32 bits are needed" +* u = u * mod +* u = u + t +* u = u >> size +* u = IF (u >= mod) u = u - mod +* +* Leaf function. +* +* \param z +* Register index for product value. +* +* \param a +* Register index for multiplicand value. +* +* \param b +* Register index for multiplier value. +* +* \param mont_mod_der +* Register index for Montgomery coefficient value. +* +* \param mod +* Register index for modulo value. +* +* \param size +* Bit size. +* +*******************************************************************************/ +void Cy_Crypto_Core_Rsa_MontMul(uint32_t z, uint32_t a, uint32_t b, uint32_t mont_mod_der, uint32_t mod, uint32_t size) +{ + uint32_t sh = 0; + uint32_t t = 1; + uint32_t u_double = 2; + uint32_t t_double = 3; + + uint32_t status = 4; + + CY_CRYPTO_VU_ALLOC_MEM (t, size + 1); + CY_CRYPTO_VU_ALLOC_MEM (u_double, 2 * size); + CY_CRYPTO_VU_ALLOC_MEM (t_double, 2 * size); + + CY_CRYPTO_VU_SET_REG (sh, size, 1); + + CY_CRYPTO_VU_UMUL (t_double, a, b); + + /* Only lower 32 bits are needed */ + CY_CRYPTO_VU_UMUL (t, t_double, mont_mod_der); + + /* Clear the MSB bit (cut to size length) */ + CY_CRYPTO_VU_LSL1(t, t); + CY_CRYPTO_VU_LSR1(t, t); + + CY_CRYPTO_VU_UMUL (u_double, t, mod); + + CY_CRYPTO_VU_ADD (u_double, u_double, t_double); + + CY_CRYPTO_VU_MOV_STATUS_TO_REG (status); + + CY_CRYPTO_VU_LSR (u_double, u_double, sh); + + CY_CRYPTO_VU_SET_TO_ZERO (t); + CY_CRYPTO_VU_SET_REG (sh, 0, 1); + CY_CRYPTO_VU_SET_BIT (t, sh); + CY_CRYPTO_VU_SET_REG (sh, size, 1); + CY_CRYPTO_VU_LSL (t, t, sh); + + CY_CRYPTO_VU_MOV_REG_TO_STATUS (status); + Cy_Crypto_Core_WaitForReady(); + + CY_CRYPTO_VU_COND_XOR (CY_CRYPTO_VU_COND_CS, u_double, u_double, t); + + /* C = (a >= b) */ + CY_CRYPTO_VU_SUB (t_double, u_double, mod); + + CY_CRYPTO_VU_COND_SWAP_REG (CY_CRYPTO_VU_COND_CS, u_double, t_double); + + CY_CRYPTO_VU_MOV (z, u_double); + + CY_CRYPTO_VU_FREE_MEM ((1 << t_double) | (1 << u_double) | (1 << t)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Rsa_expModByMont +****************************************************************************//** +* +* Perform y = x^e mod n using Montgomery reduction technique to speed-up +* calculation. Suitable for cases with short e. +* +* \param y +* Register index for calculated value. +* +* \param x +* Register index for multiplicand value. +* +* \param e +* Register index for exponent value. +* +* \param n +* Register index for modulo value. +* +* \param size +* modulo size, in Bits +* +*******************************************************************************/ +void Cy_Crypto_Core_Rsa_expModByMont(uint32_t y, + uint32_t x, + uint32_t e, + uint32_t n, + uint32_t barretCoef, + uint32_t inverseModulo, + uint32_t rBar, + uint32_t size) +{ + int32_t i; + uint16_t j; + uint16_t status; + uint16_t carry; + uint16_t clsame; + + uint32_t my_y = 5; + uint32_t my_x = 6; + uint32_t my_e = 7; + uint32_t my_n = 8; + uint32_t R0_1 = 9; + uint32_t n_prime = 10; + uint32_t temp = 11; + uint32_t barrett_u = 12; + uint32_t x_bar = 13; + uint32_t REG = 14; + + + CY_CRYPTO_VU_PUSH_REG(); + + CY_CRYPTO_VU_LD_REG(my_x, x); + CY_CRYPTO_VU_LD_REG(my_y, y); + CY_CRYPTO_VU_LD_REG(my_e, e); + CY_CRYPTO_VU_LD_REG(my_n, n); + CY_CRYPTO_VU_LD_REG(n_prime, inverseModulo); + CY_CRYPTO_VU_LD_REG(barrett_u, barretCoef); + + CY_CRYPTO_VU_MOV(my_y, rBar); + + CY_CRYPTO_VU_ALLOC_MEM(R0_1, size); + CY_CRYPTO_VU_ALLOC_MEM(x_bar, size); + CY_CRYPTO_VU_ALLOC_MEM(temp, size); + + Cy_Crypto_Core_Rsa_MontTransform(x_bar, my_x, barrett_u, my_n, size); + Cy_Crypto_Core_WaitForReady(); + + CY_CRYPTO_VU_MOV(temp, my_e); + CY_CRYPTO_VU_SET_TO_ZERO(R0_1); + CY_CRYPTO_VU_CLSAME(REG, temp, R0_1); + + /* This is needed, otherwise clsame is wrong */ + Cy_Crypto_Core_WaitForReady(); + + clsame = Cy_Crypto_Core_Vu_RegDataPtrRead(REG); + j = Cy_Crypto_Core_Vu_RegSizeRead(temp) + 1 - clsame; + CY_CRYPTO_VU_SET_REG(REG, clsame, 1); + CY_CRYPTO_VU_LSL(temp, temp, REG); + + for (i = j; i > 0; i--) + { + + /* j is number of bits in exponent e */ + Cy_Crypto_Core_Rsa_MontMul(my_y, my_y, my_y, n_prime, my_n, size); + Cy_Crypto_Core_WaitForReady(); + + CY_CRYPTO_VU_LSL1(temp, temp); + status = Cy_Crypto_Core_Vu_StatusRead(); + carry = status & (1 << CY_CRYPTO_VU_STATUS_CARRY); + + if (carry != 0) + { + Cy_Crypto_Core_Rsa_MontMul(my_y, my_y, x_bar, n_prime, my_n, size); + } + } + + CY_CRYPTO_VU_SET_TO_ONE(R0_1); + Cy_Crypto_Core_Rsa_MontMul(my_y, my_y, R0_1, n_prime , my_n, size); + + CY_CRYPTO_VU_FREE_MEM((1 << R0_1) | (1 << x_bar) | (1 << temp)); + CY_CRYPTO_VU_POP_REG(); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Rsa_Proc +****************************************************************************//** +* +* RSA process algorithm based on the Montgomery algorithm +* using Barrett reduction +* +* https://en.wikipedia.org/wiki/RSA_%28cryptosystem%29 +* +* \param cryptoContextPtr +* Pointer to the RSA context +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(cy_stc_crypto_context_rsa_t *cryptoContextPtr) +{ + cy_en_crypto_status_t result = CY_CRYPTO_SUCCESS; + + uint8_t *_expPtr = cryptoContextPtr->keyPtr->pubExpPtr; + uint32_t _expBitLength = cryptoContextPtr->keyPtr->pubExpLength; + uint8_t *_nPtr = cryptoContextPtr->keyPtr->moduloPtr; + uint32_t _nBitLength = cryptoContextPtr->keyPtr->moduloLength; + uint32_t *_messagePtr = (uint32_t*)cryptoContextPtr->messagePtr; + uint32_t _messageByteLength = cryptoContextPtr->messageLength; + uint32_t *_resultPtr = (uint32_t*)cryptoContextPtr->resultPtr; + uint8_t *_barretCoefPtr = cryptoContextPtr->keyPtr->barretCoefPtr; + uint8_t *_inverseModuloPtr = cryptoContextPtr->keyPtr->inverseModuloPtr; + uint8_t *_rBarPtr = cryptoContextPtr->keyPtr->rBarPtr; + + uint32_t _nByteLength = 0; + uint32_t _barretByteLength = 0; + uint32_t _expByteLength = 0; + + uint32_t yReg = 5; + uint32_t xReg = 6; + uint32_t eReg = 7; + uint32_t modReg = 8; + uint32_t inverseModuloReg = 9; + uint32_t barrettReg = 10; + uint32_t rBarReg = 11; + + + /* Clear all Crypto SRAM before operations */ + memset((void*)CRYPTO->MEM_BUFF, 0x00, CPUSS_CRYPTO_BUFF_SIZE * 4); + + CY_CRYPTO_VU_ALLOC_MEM(yReg, _nBitLength); + CY_CRYPTO_VU_ALLOC_MEM(xReg, _nBitLength); + CY_CRYPTO_VU_ALLOC_MEM(eReg, _nBitLength); + CY_CRYPTO_VU_ALLOC_MEM(modReg, _nBitLength); + CY_CRYPTO_VU_ALLOC_MEM(barrettReg, _nBitLength + 1); + CY_CRYPTO_VU_ALLOC_MEM(inverseModuloReg, _nBitLength); + CY_CRYPTO_VU_ALLOC_MEM(rBarReg, _nBitLength); + + _nByteLength = _nBitLength / 8; + if ((_nBitLength % 8) != 0) + { + _nByteLength += 1; + } + + _barretByteLength = (_nBitLength + 1) / 8; + if (((_nBitLength + 1) % 8) != 0) + { + _barretByteLength += 1; + } + + _expByteLength = _expBitLength / 8; + if ((_expBitLength % 8) != 0) + { + _expByteLength += 1; + } + + memcpy((void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(modReg)), _nPtr, _nByteLength); + memcpy((void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(eReg)), _expPtr, _expByteLength); + memcpy((void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(xReg)), _messagePtr, _messageByteLength); + + /* Check coefficients */ + if (_barretCoefPtr == NULL) + { + Cy_Crypto_Core_Rsa_BarrettGetU(barrettReg, modReg, _nBitLength); + Cy_Crypto_Core_WaitForReady(); + } + else + { + memcpy((void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(barrettReg)), + _barretCoefPtr, + _barretByteLength); + } + + if (_rBarPtr == NULL) + { + /* inverseModuloReg used here as temp variable */ + CY_CRYPTO_VU_SET_TO_ONE(inverseModuloReg); + Cy_Crypto_Core_Rsa_MontTransform(rBarReg, inverseModuloReg, barrettReg, modReg, _nBitLength); + Cy_Crypto_Core_WaitForReady(); + } + else + { + memcpy((void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(rBarReg)), + _rBarPtr, + _nByteLength); + } + + if (_inverseModuloPtr == NULL) + { + Cy_Crypto_Core_Rsa_MontCoeff(inverseModuloReg, modReg, _nBitLength); + Cy_Crypto_Core_WaitForReady(); + } + else + { + memcpy((void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(inverseModuloReg)), + _inverseModuloPtr, + _nByteLength); + } + + Cy_Crypto_Core_Rsa_expModByMont(yReg, + xReg, + eReg, + modReg, + barrettReg, + inverseModuloReg, + rBarReg, + _nBitLength); + + Cy_Crypto_Core_Vu_WaitForComplete(); + + /* Copy the result to output buffer */ + memcpy((void*)_resultPtr, (void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(yReg)), _nByteLength); + + CY_CRYPTO_VU_FREE_MEM((1 << yReg) | (1 << xReg) | (1 << eReg) | (1 << modReg) | + (1 << inverseModuloReg) | (1 << barrettReg) | (1 << rBarReg)); + + return (result); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Rsa_Coef +****************************************************************************//** +* +* Calculation constant coefficients to to speed-up Montgomery algorithm. +* These coefficients are: +* coefficient for Barrett reduction, +* binary inverse of the modulo, +* result of (2^moduloLength mod modulo) +* +* \param cryptoContextPtr +* Pointer to the RSA context +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Coef(cy_stc_crypto_context_rsa_t *cryptoContextPtr) +{ + cy_en_crypto_status_t result = CY_CRYPTO_SUCCESS; + + uint8_t *_nPtr = cryptoContextPtr->keyPtr->moduloPtr; + uint32_t _nBitLength = cryptoContextPtr->keyPtr->moduloLength; + uint8_t *_barretCoefPtr = cryptoContextPtr->keyPtr->barretCoefPtr; + uint8_t *_inverseModuloPtr = cryptoContextPtr->keyPtr->inverseModuloPtr; + uint8_t *_rBarPtr = cryptoContextPtr->keyPtr->rBarPtr; + uint32_t _nByteLength; + uint32_t _barretByteLength; + + uint32_t modReg = 11; + uint32_t inverseModuloReg = 12; + uint32_t barrettReg = 13; + uint32_t rBarReg = 14; + + + /* Clear all Crypto SRAM before operations */ + memset((void*)CRYPTO->MEM_BUFF, 0x00, CPUSS_CRYPTO_BUFF_SIZE * 4); + + CY_CRYPTO_VU_ALLOC_MEM(modReg, _nBitLength); + CY_CRYPTO_VU_ALLOC_MEM(barrettReg, _nBitLength + 1); + CY_CRYPTO_VU_ALLOC_MEM(inverseModuloReg, _nBitLength); + CY_CRYPTO_VU_ALLOC_MEM(rBarReg, _nBitLength); + + _nByteLength = _nBitLength / 8; + if ((_nBitLength % 8) != 0) + { + _nByteLength += 1; + } + + _barretByteLength = (_nBitLength + 1) / 8; + if (((_nBitLength + 1) % 8) != 0) + { + _barretByteLength += 1; + } + + /* Copy modulo to Crypto SRAM */ + memcpy((void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(modReg)), + _nPtr, + _nByteLength); + + Cy_Crypto_Core_Rsa_BarrettGetU(barrettReg, modReg, _nBitLength); + Cy_Crypto_Core_WaitForReady(); + + /* Copy calculated Barrett coefficient */ + memcpy((void*)_barretCoefPtr, + (void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(barrettReg)), + _barretByteLength); + + /* inverseModuloReg used here as temp variable */ + CY_CRYPTO_VU_SET_TO_ONE(inverseModuloReg); + Cy_Crypto_Core_Rsa_MontTransform(rBarReg, inverseModuloReg, barrettReg, modReg, _nBitLength); + Cy_Crypto_Core_WaitForReady(); + + /* Copy calculated r-bar = (1 << size) mod modulo */ + memcpy((void*)_rBarPtr, + (void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(rBarReg)), + _nByteLength); + + Cy_Crypto_Core_Rsa_MontCoeff(inverseModuloReg, modReg, _nBitLength); + Cy_Crypto_Core_WaitForReady(); + + /* Copy calculated inverse modulo */ + memcpy((void*)_inverseModuloPtr, + (void*)((uint32_t)CRYPTO->MEM_BUFF + 4 * Cy_Crypto_Core_Vu_RegDataPtrRead(inverseModuloReg)), + _nByteLength); + + CY_CRYPTO_VU_FREE_MEM((1 << modReg) | (1 << inverseModuloReg) | (1 << barrettReg) | (1 << rBarReg)); + + return (result); +} + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_rsa.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_rsa.h new file mode 100644 index 0000000000..86bc2c9e15 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_rsa.h @@ -0,0 +1,62 @@ +/***************************************************************************//** +* \file cy_crypto_core_rsa.h +* \version 1.0 +* +* \brief +* This file provides provides constant and parameters +* for the API of the RSA in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CORE_RSA_H) +#define CY_CRYPTO_CORE_RSA_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) + + +/* Crypto IP condition codes (vector unit) */ +#define CY_CRYPTO_VU_COND_ALWAYS (0x00u) +#define CY_CRYPTO_VU_COND_EQ (0x01u) +#define CY_CRYPTO_VU_COND_NE (0x02u) +#define CY_CRYPTO_VU_COND_CS (0x03u) +#define CY_CRYPTO_VU_COND_CC (0x04u) +#define CY_CRYPTO_VU_COND_HI (0x05u) +#define CY_CRYPTO_VU_COND_LS (0x06u) +#define CY_CRYPTO_VU_COND_EVEN (0x07u) +#define CY_CRYPTO_VU_COND_ODD (0x08u) + + +/* Crypto IP status (vector unit) */ +#define CY_CRYPTO_VU_STATUS_ONE (3u) +#define CY_CRYPTO_VU_STATUS_ZERO (2u) +#define CY_CRYPTO_VU_STATUS_EVEN (1u) +#define CY_CRYPTO_VU_STATUS_CARRY (0u) + + +cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Proc(cy_stc_crypto_context_rsa_t *cryptoContextPtr); +cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Coef(cy_stc_crypto_context_rsa_t *cryptoContextPtr); + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +#if (CY_CRYPTO_USER_PKCS1_5 == 1) +cy_en_crypto_status_t Cy_Crypto_Core_RsaVerify(cy_stc_crypto_context_rsa_ver_t *cryptoContextPtr); +#endif /* #if (CY_CRYPTO_USER_PKCS1_5 == 1) */ + + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_RSA_H) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_sha.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_sha.c new file mode 100644 index 0000000000..e1acdc61f9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_sha.c @@ -0,0 +1,442 @@ +/***************************************************************************//** +* \file cy_crypto_core_sha.c +* \version 1.0 +* +* \brief +* This file provides the source code to the API for the SHA method +* in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_sha.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_str.h" +#include "syslib/cy_syslib.h" +#include + + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) + + +/* Initialization vectors for different modes of the SHA algorithm */ +#if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) +static const uint32_t Sha1InitHash[] = +{ + 0x67452301uL, 0xEFCDAB89uL, 0x98BADCFEuL, 0x10325476uL, + 0xC3D2E1F0uL +}; +#endif /* #if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) +static const uint32_t Sha224InitHash[] = +{ + 0xC1059ED8uL, 0x367CD507uL, 0x3070DD17uL, 0xF70E5939uL, + 0xFFC00B31uL, 0x68581511uL, 0x64F98FA7uL, 0xBEFA4FA4uL +}; + +static const uint32_t Sha256InitHash[] = +{ + 0x6A09E667uL, 0xBB67AE85uL, 0x3C6EF372uL, 0xA54FF53AuL, + 0x510E527FuL, 0x9B05688CuL, 0x1F83D9ABuL, 0x5BE0CD19uL +}; +#endif /* #if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) +static const uint32_t Sha512_224InitHash[] = +{ + 0x8C3D37C8uL, 0x19544DA2uL, 0x73E19966uL, 0x89DCD4D6uL, + 0x1DFAB7AEuL, 0x32FF9C82uL, 0x679DD514uL, 0x582F9FCFuL, + 0x0F6D2B69uL, 0x7BD44DA8uL, 0x77E36F73uL, 0x04C48942uL, + 0x3F9D85A8uL, 0x6A1D36C8uL, 0x1112E6ADuL, 0x91D692A1uL +}; + +static const uint32_t Sha512_256InitHash[] = +{ + 0x22312194uL, 0xFC2BF72CuL, 0x9F555FA3uL, 0xC84C64C2uL, + 0x2393B86BuL, 0x6F53B151uL, 0x96387719uL, 0x5940EABDuL, + 0x96283EE2uL, 0xA88EFFE3uL, 0xBE5E1E25uL, 0x53863992uL, + 0x2B0199FCuL, 0x2C85B8AAuL, 0x0EB72DDCuL, 0x81C52CA2uL +}; + +static const uint32_t Sha384InitHash[] = +{ + 0xCBBB9D5DuL, 0xC1059ED8uL, 0x629A292AuL, 0x367CD507uL, + 0x9159015AuL, 0x3070DD17uL, 0x152FECD8uL, 0xF70E5939uL, + 0x67332667uL, 0xFFC00B31uL, 0x8EB44A87uL, 0x68581511uL, + 0xDB0C2E0DuL, 0x64F98FA7uL, 0x47B5481DuL, 0xBEFA4FA4uL +}; + +static const uint32_t Sha512InitHash[] = +{ + 0x6A09E667uL, 0xF3BCC908uL, 0xBB67AE85uL, 0x84CAA73BuL, + 0x3C6EF372uL, 0xFE94F82BuL, 0xA54FF53AuL, 0x5F1D36F1uL, + 0x510E527FuL, 0xADE682D1uL, 0x9B05688CuL, 0x2B3E6C1FuL, + 0x1F83D9ABuL, 0xFB41BD6BuL, 0x5BE0CD19uL, 0x137E2179uL +}; +#endif /* #if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) */ + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Sha_ProcessBlock +****************************************************************************//** +* +* Performs the SHA calculation on one block. +* All addresses must be 4-Byte aligned! +* +* This function available for CM0+ core only. +* +* \param hashStatePtr +* The pointer to a Hash State. +* +* \param blockPtr +* The pointer to the block whose Hash is being computed. +* +*******************************************************************************/ +void Cy_Crypto_Core_Sha_ProcessBlock(cy_stc_crypto_sha_state_t *hashStatePtr, uint32_t *blockPtr) +{ + Cy_Crypto_SetReg4Instr((uint32_t)blockPtr, + (uint32_t)hashStatePtr->hashPtr, /* Initial hash */ + (uint32_t)hashStatePtr->roundMemPtr, + (uint32_t)hashStatePtr->hashPtr); /* Digest */ + + /* Issue the SHA instruction */ + Cy_Crypto_Run4ParamInstr(CY_CRYPTO_SHA_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT, + CY_CRYPTO_RSRC8_SHIFT, + CY_CRYPTO_RSRC12_SHIFT); + + /* Wait until the SHA instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_SHA_BUSY, CRYPTO->STATUS)) + { + } +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Sha_Init +****************************************************************************//** +* +* The function to initialize SHA operation. +* +* This function available for CM0+ core only. +* +* \param hashStatePtr +* The pointer to a Hash State. +* +* \param mode +* One of these: CY_CRYPTO_SHA256, CY_CRYPTO_SHA1, CY_CRYPTO_SHA256_224, CY_CRYPTO_SHA512, +* CY_CRYPTO_SHA384, CY_CRYPTO_SHA512_224, CY_CRYPTO_SHA512_256 +* +*******************************************************************************/ +void Cy_Crypto_Core_Sha_Init(cy_stc_crypto_sha_state_t *hashStatePtr, + uint8_t *blockPtr, + uint32_t *hashPtr, + uint32_t *roundMemPtr, + cy_en_crypto_sha_mode_t mode) +{ + cy_en_crypto_sha_hw_mode_t shaHwMode; + +#if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) + shaHwMode = CY_CRYPTO_SHA_CTL_MODE_SHA512; +#endif /* #if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) */ + + switch (mode) + { +#if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) + + case CY_CRYPTO_MODE_SHA1: + shaHwMode = CY_CRYPTO_SHA_CTL_MODE_SHA1; + hashStatePtr->initialHashPtr = Sha1InitHash; + hashStatePtr->blockSize = CY_CRYPTO_SHA1_BLOCK_SIZE; + hashStatePtr->hashSize = CY_CRYPTO_SHA1_HASH_SIZE; + hashStatePtr->digestSize = CY_CRYPTO_SHA1_DIGEST_SIZE; + hashStatePtr->roundMemSize = CY_CRYPTO_SHA1_ROUND_MEM_SIZE; + break; +#endif /* #if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) + + case CY_CRYPTO_MODE_SHA224: + shaHwMode = CY_CRYPTO_SHA_CTL_MODE_SHA256; + hashStatePtr->initialHashPtr = Sha224InitHash; + hashStatePtr->blockSize = CY_CRYPTO_SHA256_BLOCK_SIZE; + hashStatePtr->hashSize = CY_CRYPTO_SHA256_HASH_SIZE; + hashStatePtr->digestSize = CY_CRYPTO_SHA224_DIGEST_SIZE; + hashStatePtr->roundMemSize = CY_CRYPTO_SHA256_ROUND_MEM_SIZE; + break; + + case CY_CRYPTO_MODE_SHA256: + shaHwMode = CY_CRYPTO_SHA_CTL_MODE_SHA256; + hashStatePtr->initialHashPtr = Sha256InitHash; + hashStatePtr->blockSize = CY_CRYPTO_SHA256_BLOCK_SIZE; + hashStatePtr->hashSize = CY_CRYPTO_SHA256_HASH_SIZE; + hashStatePtr->digestSize = CY_CRYPTO_SHA256_DIGEST_SIZE; + hashStatePtr->roundMemSize = CY_CRYPTO_SHA256_ROUND_MEM_SIZE; + break; +#endif /* #if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) + + case CY_CRYPTO_MODE_SHA384: + hashStatePtr->initialHashPtr = Sha384InitHash; + hashStatePtr->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; + hashStatePtr->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; + hashStatePtr->digestSize = CY_CRYPTO_SHA384_DIGEST_SIZE; + hashStatePtr->roundMemSize = CY_CRYPTO_SHA512_ROUND_MEM_SIZE; + break; + + case CY_CRYPTO_MODE_SHA512: + hashStatePtr->initialHashPtr = Sha512InitHash; + hashStatePtr->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; + hashStatePtr->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; + hashStatePtr->digestSize = CY_CRYPTO_SHA512_DIGEST_SIZE; + hashStatePtr->roundMemSize = CY_CRYPTO_SHA512_ROUND_MEM_SIZE; + break; + + case CY_CRYPTO_MODE_SHA512_224: + hashStatePtr->initialHashPtr = Sha512_224InitHash; + hashStatePtr->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; + hashStatePtr->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; + hashStatePtr->digestSize = CY_CRYPTO_SHA512_224_DIGEST_SIZE; + hashStatePtr->roundMemSize = CY_CRYPTO_SHA512_ROUND_MEM_SIZE; + break; + + case CY_CRYPTO_MODE_SHA512_256: + hashStatePtr->initialHashPtr = Sha512_256InitHash; + hashStatePtr->blockSize = CY_CRYPTO_SHA512_BLOCK_SIZE; + hashStatePtr->hashSize = CY_CRYPTO_SHA512_HASH_SIZE; + hashStatePtr->digestSize = CY_CRYPTO_SHA512_256_DIGEST_SIZE; + hashStatePtr->roundMemSize = CY_CRYPTO_SHA512_ROUND_MEM_SIZE; + break; +#endif /* #if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) */ + + default: + break; + } + + hashStatePtr->mode = mode; + hashStatePtr->blockPtr = blockPtr; + hashStatePtr->hashPtr = hashPtr; + hashStatePtr->roundMemPtr = roundMemPtr; + + /* Set the SHA mode */ + CRYPTO->SHA_CTL = (uint32_t)(_VAL2FLD(CRYPTO_SHA_CTL_MODE, (uint32_t)shaHwMode)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Sha_Start +****************************************************************************//** +* +* Initializes the initial hash vector. +* +* This function available for CM0+ core only. +* +* \param hashStatePtr +* The pointer to the SHA context. +* +*******************************************************************************/ +void Cy_Crypto_Core_Sha_Start(cy_stc_crypto_sha_state_t *hashStatePtr) +{ + memcpy(hashStatePtr->hashPtr, hashStatePtr->initialHashPtr, hashStatePtr->hashSize); +} + +/******************************************************************************* +* Function Name: Crypto_Server_SHA_Update +****************************************************************************//** +* +* Performs the SHA calculation on one message. +* +* This function available for CM0+ core only. +* +* \param hashStatePtr +* The pointer to the SHA context. +* +* \param messagePtr +* The pointer to the message whose Hash is being computed. +* +* \param messageSize +* The size of the message whose Hash is being computed. +* +*******************************************************************************/ +void Cy_Crypto_Core_Sha_Update(cy_stc_crypto_sha_state_t *hashStatePtr, + uint32_t *messagePtr, + uint32_t messageSize) +{ + uint8_t *blockPtrTmp = hashStatePtr->blockPtr; + uint32_t blockSizeTmp = hashStatePtr->blockSize; + uint32_t blockIdx = messageSize & (blockSizeTmp - 1u); + hashStatePtr->messageSize = messageSize; + + if (messageSize >= blockSizeTmp) + { + while (messageSize >= blockSizeTmp) + { + Cy_Crypto_Core_Sha_ProcessBlock(hashStatePtr, messagePtr); + + /* Use /4 because the pointer is to uint32_t and blockSize is in Bytes */ + messagePtr += (blockSizeTmp / 4u); + messageSize -= blockSizeTmp; + } + } + + /* Copy the end of the message to the block */ + memcpy(blockPtrTmp, messagePtr, blockIdx); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Sha_Finish +****************************************************************************//** +* +* Completes SHA calculation. +* +* This function available for CM0+ core only. +* +* \param hashStatePtr +* The pointer to the SHA context. +* +* \param digestPtr +* The pointer to the calculated hash digest. +* +* \param finalMessageSize +* The final message size, can be different from the messageSize +* if you use command Cy_Crypto_Core_Sha_ProcessBlock() before. +* +*******************************************************************************/ +void Cy_Crypto_Core_Sha_Finish(cy_stc_crypto_sha_state_t *hashStatePtr, + uint32_t *digestPtr, + uint32_t finalMessageSize) +{ + uint32_t *hashTmpPtr = hashStatePtr->hashPtr; + uint8_t *blockTmpPtr = hashStatePtr->blockPtr; + uint32_t blockSizeTmp = hashStatePtr->blockSize; + uint32_t blockIdx = (uint32_t)(hashStatePtr->messageSize & (blockSizeTmp - 1u)); + uint32_t size; + + if (CY_CRYPTO_SHA512_BLOCK_SIZE == blockSizeTmp) + { + size = CY_CRYPTO_SHA512_PAD_SIZE; /* Pad size = 112 */ + } + else + { + size = CY_CRYPTO_SHA256_PAD_SIZE; /* Pad size = 56 */ + } + + /* Append 1 bit to the end of the message */ + blockTmpPtr[blockIdx] = 0x80u; + + /* Clear the rest of the block */ + memset((void* )&blockTmpPtr[blockIdx + 1u], 0x00u, (blockSizeTmp - blockIdx - 1u)); + + if (blockIdx >= size) + { + /* Here we need one additional last block to calculate SHA, prepare it: */ + Cy_Crypto_Core_Sha_ProcessBlock(hashStatePtr, (uint32_t*)blockTmpPtr); + + /* Clear the last block */ + memset(blockTmpPtr, 0x00u, blockSizeTmp); + } + + /* Write at the end length of the message, in Bits */ + blockTmpPtr[blockSizeTmp - 4u] = (uint8_t)((finalMessageSize * 8uL) >> 24u); + blockTmpPtr[blockSizeTmp - 3u] = (uint8_t)((finalMessageSize * 8uL) >> 16u); + blockTmpPtr[blockSizeTmp - 2u] = (uint8_t)((finalMessageSize * 8uL) >> 8u); + blockTmpPtr[blockSizeTmp - 1u] = (uint8_t)(finalMessageSize * 8uL); + + /* Process the last block */ + Cy_Crypto_Core_Sha_ProcessBlock(hashStatePtr, (uint32_t*)blockTmpPtr); + + /* Invert endians of the hash and copy it to digestPtr, re-use the size variable */ + size = (uint32_t)(hashStatePtr->digestSize / 4u); + + for(; size != 0u; size--) + { + *digestPtr = CY_SWAP_ENDIAN32(*hashTmpPtr); + digestPtr++; + hashTmpPtr++; + } + +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Sha_Free +****************************************************************************//** +* +* Clears the used memory buffers. +* +* This function available for CM0+ core only. +* +* \param hashStatePtr +* The pointer to the SHA context. +* +*******************************************************************************/ +void Cy_Crypto_Core_Sha_Free(cy_stc_crypto_sha_state_t *hashStatePtr) +{ + /* Clears the memory buffer. */ + memset(hashStatePtr->blockPtr, 0x00u, hashStatePtr->blockSize); + memset(hashStatePtr->hashPtr, 0x00u, hashStatePtr->hashSize); + memset(hashStatePtr->roundMemPtr, 0x00u, hashStatePtr->roundMemSize); +} + +/******************************************************************************* +* Function Name: Crypto_Core_Sha +****************************************************************************//** +* +* Performs the SHA Hash function. +* +* This function available for CM0+ core only. +* +* \param cryptoShaContext +* the pointer to the stc_crypto_context_t structure which stores all internal variables +* for Crypto driver. +* +* \return +* A Crypto status \ref en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Sha(cy_stc_crypto_context_sha_t *cryptoShaContext) +{ + uint32_t *messageTmpPtr = cryptoShaContext->messagePtr; + uint32_t messageSizeTmp = cryptoShaContext->messageSize; + uint32_t *digestPtr = cryptoShaContext->dstPtr; + cy_en_crypto_sha_mode_t modeTmp = cryptoShaContext->mode; + + /* Allocate CRYPTO_MAX_BLOCK_SIZE Bytes for blockPtr */ + uint8_t *blockPtr = (uint8_t*)CRYPTO->MEM_BUFF; + + /* Allocate CRYPTO_MAX_HASH_SIZE Bytes for hashPtr */ + uint32_t *hashPtr = (uint32_t*)(blockPtr + CY_CRYPTO_MAX_BLOCK_SIZE); + + /* Allocate CRYPTO_MAX_ROUND_MEM_SIZE Bytes for roundMemPtr */ + uint32_t *roundMemPtr = (uint32_t*)((uint8_t*)hashPtr + CY_CRYPTO_MAX_HASH_SIZE); + + /* Allocate space for the structure which stores the SHA context */ + cy_stc_crypto_sha_state_t *hashStatePtr = + (cy_stc_crypto_sha_state_t*)((uint8_t*)roundMemPtr + CY_CRYPTO_MAX_ROUND_MEM_SIZE); + + /* Initialize the hashStatePtr structure with zeros */ + memset(hashStatePtr, 0x00u, sizeof(cy_stc_crypto_sha_state_t)); + + Cy_Crypto_Core_Sha_Init (hashStatePtr, blockPtr, hashPtr, roundMemPtr, modeTmp); + Cy_Crypto_Core_Sha_Start (hashStatePtr); + Cy_Crypto_Core_Sha_Update (hashStatePtr, messageTmpPtr, messageSizeTmp); + Cy_Crypto_Core_Sha_Finish (hashStatePtr, digestPtr, messageSizeTmp); + Cy_Crypto_Core_Sha_Free (hashStatePtr); + + return (CY_CRYPTO_SUCCESS); +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_sha.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_sha.h new file mode 100644 index 0000000000..ce7f62dac0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_sha.h @@ -0,0 +1,115 @@ +/***************************************************************************//** +* \file cy_crypto_core_sha.h +* \version 1.0 +* +* \brief +* This file provides constants and function prototypes +* for the API for the SHA method in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_CRYPTO_CORE_SHA_H) +#define CY_CRYPTO_CORE_SHA_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) + +/** \cond INTERNAL */ + +/* Defines for the SHA algorithm */ +#define CY_CRYPTO_SHA1_BLOCK_SIZE (64u) +#define CY_CRYPTO_SHA256_BLOCK_SIZE (64u) +#define CY_CRYPTO_SHA512_BLOCK_SIZE (128u) +#define CY_CRYPTO_MAX_BLOCK_SIZE (128u) + +#define CY_CRYPTO_SHA256_PAD_SIZE (56uL) +#define CY_CRYPTO_SHA512_PAD_SIZE (112uL) + +#define CY_CRYPTO_SHA1_HASH_SIZE (20u) +#define CY_CRYPTO_SHA256_HASH_SIZE (64u) +#define CY_CRYPTO_SHA512_HASH_SIZE (128u) +#define CY_CRYPTO_MAX_HASH_SIZE (128u) + +#define CY_CRYPTO_SHA1_ROUND_MEM_SIZE (320uL) +#define CY_CRYPTO_SHA256_ROUND_MEM_SIZE (256uL) +#define CY_CRYPTO_SHA512_ROUND_MEM_SIZE (640uL) +#define CY_CRYPTO_MAX_ROUND_MEM_SIZE (640uL) + +/* The structure for storing the SHA context */ +typedef struct +{ + cy_en_crypto_sha_mode_t mode; + uint8_t *blockPtr; + uint32_t blockSize; + uint32_t *hashPtr; + uint32_t hashSize; + uint32_t *roundMemPtr; + uint32_t roundMemSize; + uint32_t messageSize; + uint32_t digestSize; + const uint32_t *initialHashPtr; +} cy_stc_crypto_sha_state_t; + + +typedef enum +{ + +#if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) + CY_CRYPTO_SHA_CTL_MODE_SHA1 = 0u, +#endif /* #if ((CPUSS_CRYPTO_SHA1 == 1) && (CY_CRYPTO_USER_SHA1 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) + CY_CRYPTO_SHA_CTL_MODE_SHA256 = 1u, +#endif /* #if ((CPUSS_CRYPTO_SHA256 == 1) && (CY_CRYPTO_USER_SHA256 == 1)) */ + +#if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) + CY_CRYPTO_SHA_CTL_MODE_SHA512 = 2u, +#endif /* #if ((CPUSS_CRYPTO_SHA512 == 1) && (CY_CRYPTO_USER_SHA512 == 1)) */ + +} cy_en_crypto_sha_hw_mode_t; + + +void Cy_Crypto_Core_Sha_Init(cy_stc_crypto_sha_state_t *hashStatePtr, + uint8_t *blockPtr, + uint32_t *hashPtr, + uint32_t *roundMemPtr, + cy_en_crypto_sha_mode_t mode); + +void Cy_Crypto_Core_Sha_ProcessBlock(cy_stc_crypto_sha_state_t *hashStatePtr, + uint32_t *blockPtr); + +void Cy_Crypto_Core_Sha_Start(cy_stc_crypto_sha_state_t *hashStatePtr); + +void Cy_Crypto_Core_Sha_Update(cy_stc_crypto_sha_state_t *hashStatePtr, + uint32_t *messagePtr, + uint32_t messageSize); + +void Cy_Crypto_Core_Sha_Finish(cy_stc_crypto_sha_state_t *hashStatePtr, + uint32_t *digestPtr, + uint32_t finalMessageSize); + +void Cy_Crypto_Core_Sha_Free(cy_stc_crypto_sha_state_t *hashStatePtr); + +cy_en_crypto_status_t Cy_Crypto_Core_Sha(cy_stc_crypto_context_sha_t *cryptoShaContext); + +/** \endcond */ + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_SHA_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_str.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_str.c new file mode 100644 index 0000000000..1852ff670e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_str.c @@ -0,0 +1,194 @@ +/***************************************************************************//** +* \file cy_crypto_core_str.c +* \version 1.0 +* +* \brief +* This file provides the source code for the string management API +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_crypto_common.h" +#include "cy_crypto_core_str.h" +#include "cy_crypto_core_instructions.h" +#include "cy_crypto_core_util.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) + + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Str_MemCpy +****************************************************************************//** +* +* Function MemCpy uses Crypto HW. +* Memory structures should not overlap! +* There is no alignment restriction. +* +* This function available for CM0+ core only. +* +* \param src +* The pointer to the source of MemCpy. +* +* \param dst +* The pointer to the destination of MemCpy. +* +* \param size +* The size in bytes of the copy operation. +* +*******************************************************************************/ +void Cy_Crypto_Core_Str_MemCpy(void* dstPtr, void const *srcPtr, uint16_t size) +{ + /* Prepare data in the register file for next instruction */ + Cy_Crypto_SetReg3Instr((uint32_t)srcPtr, + (uint32_t)dstPtr, + (uint32_t)size); + + /* Issue the STR_MEMCPY instruction */ + Cy_Crypto_Run3ParamInstr(CY_CRYPTO_STR_MEMCPY_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT, + CY_CRYPTO_RSRC8_SHIFT); + + /* Wait until the STR instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, CRYPTO->STATUS)) + { + } +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Str_MemSet +****************************************************************************//** +* +* Function MemSet uses Crypto HW. +* There is no alignment restriction. +* +* This function available for CM0+ core only. +* +* \param dst +* The pointer to the destination of MemSet. + +* \param data +* The value to be set. + +* \param size +* The size in bytes of the set operation. +* +*******************************************************************************/ +void Cy_Crypto_Core_Str_MemSet(void* dstPtr, uint8_t data, uint16_t size) +{ + Cy_Crypto_SetReg3Instr((uint32_t)dstPtr, + (uint32_t)size, + (uint32_t)data); + + /* Issue the STR_MEMSET instruction */ + Cy_Crypto_Run3ParamInstr(CY_CRYPTO_STR_MEMSET_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC8_SHIFT, + CY_CRYPTO_RSRC12_SHIFT); + + /* Wait until the STR instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, CRYPTO->STATUS)) + { + } +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Str_MemCmp +****************************************************************************//** +* +* Function MemCmp uses Crypto HW. +* There is no alignment restriction. +* +* This function available for CM0+ core only. +* +* \param src0 +* The pointer to the first source of MemCmp. + +* \param src1 +* The pointer to the second source of MemCmp. + +* \param size +* the size in bytes of the compare operation. +* +* \return +* 0 - if Source 1 = Source 2, 1 - if not. +* +*******************************************************************************/ +uint32_t Cy_Crypto_Core_Str_MemCmp(void const *src0Ptr, void const *src1Ptr, uint16_t size) +{ + Cy_Crypto_SetReg3Instr((uint32_t)src0Ptr, + (uint32_t)src1Ptr, + (uint32_t)size); + + /* Issue the STR_MEMCMP instruction */ + Cy_Crypto_Run3ParamInstr(CY_CRYPTO_STR_MEMCMP_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT, + CY_CRYPTO_RSRC8_SHIFT); + + /* Wait until the STR instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, CRYPTO->STATUS)) + { + } + + return((uint32_t)(CRYPTO->STR_RESULT)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Str_MemXor +****************************************************************************//** +* +* Function MemXor uses Crypto HW. +* Memory structures should not overlap! +* There is no alignment restriction. +* +* This function available for CM0+ core only. +* +* \param src0 +* The pointer to the first source of MemXor. + +* \param src1 +* The pointer to the second source of MemXor. + +* \param dest +* The pointer to the destination of MemXor. +* +* \param size +* The size in bytes of the compare operation. +* +*******************************************************************************/ +void Cy_Crypto_Core_Str_MemXor(void const *src0Ptr, void const *src1Ptr, void* dstPtr, uint16_t size) +{ + Cy_Crypto_SetReg4Instr((uint32_t)src0Ptr, + (uint32_t)src1Ptr, + (uint32_t)size, + (uint32_t)dstPtr); + + /* Issue the STR_MEMXOR instruction */ + Cy_Crypto_Run4ParamInstr(CY_CRYPTO_STR_MEMXOR_OPC, + CY_CRYPTO_RSRC0_SHIFT, + CY_CRYPTO_RSRC4_SHIFT, + CY_CRYPTO_RSRC8_SHIFT, + CY_CRYPTO_RSRC12_SHIFT); + + /* Wait until the STR instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_STR_BUSY, CRYPTO->STATUS)) + { + } +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_str.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_str.h new file mode 100644 index 0000000000..7f0c4e5e84 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_str.h @@ -0,0 +1,43 @@ +/***************************************************************************//** +* \file cy_crypto_core_str.h +* \version 1.0 +* +* \brief +* This file provides the headers for the string management API +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_CRYPTO_CORE_STR_H) +#define CY_CRYPTO_CORE_STR_H + +#include "cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_STR == 1) & (CY_CRYPTO_USER_STR == 1)) + + +void Cy_Crypto_Core_Str_MemCpy(void* dstPtr, void const *srcPtr, uint16_t size); +void Cy_Crypto_Core_Str_MemSet(void* dstPtr, uint8_t data, uint16_t size); +uint32_t Cy_Crypto_Core_Str_MemCmp(void const *src0Ptr, void const *src1Ptr, uint16_t size); +void Cy_Crypto_Core_Str_MemXor(void const *src0Ptr, void const *src1Ptr, void* dstPtr, uint16_t size); + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_STR == 1) & (CY_CRYPTO_USER_STR == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_STR_H) */ + + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng.c new file mode 100644 index 0000000000..0360d8ee16 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng.c @@ -0,0 +1,93 @@ +/***************************************************************************//** +* \file cy_crypto_core_trng.c +* \version 1.0 +* +* \brief +* This file provides the source code to the API for the TRNG +* in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_trng.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_trng_config.h" +#include "syslib/cy_syslib.h" + + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) + +/******************************************************************************* +* Function Name: Crypto_Server_Trng_Init +****************************************************************************//** +* +* Initializes the TRND parameters. +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +void Cy_Crypto_Server_Trng_Init(void) +{ + CRYPTO->TR_CTL0 = CY_CRYPTO_TR_CTL0_VAL; + CRYPTO->TR_CTL1 = CY_CRYPTO_TR_CTL1_VAL; + CRYPTO->TR_MON_CTL = CY_CRYPTO_TR_BTSTR_SEL; + CRYPTO->TR_MON_CMD = CY_CRYPTO_TR_START_MON; + CRYPTO->TR_MON_RC_CTL = CY_CRYPTO_TR_RC_CUTOFF; + CRYPTO->TR_MON_AP_CTL = CY_CRYPTO_TR_AC_CUTOFF; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Trng +****************************************************************************//** +* +* Generates a True Random Number and returns it in the +* cryptoTrngContext->trngNumPtr. +* +* This function available for CM0+ core only. +* +* \param cryptoTrngContext +* The pointer to the stc_crypto_context_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Trng(cy_stc_crypto_context_trng_t *cryptoTrngContext) +{ + Cy_Crypto_Server_Trng_Init(); + + CRYPTO->TR_GARO_CTL = (uint32_t)cryptoTrngContext->GAROPol; + CRYPTO->TR_FIRO_CTL = (uint32_t)cryptoTrngContext->FIROPol; + + CRYPTO->INSTR_FF_WR = (uint32_t)(CY_CRYPTO_SET_REG1_OPC << CY_CRYPTO_OPCODE_POS); + + CRYPTO->INSTR_FF_WR = (uint32_t)cryptoTrngContext->max; + + CRYPTO->INSTR_FF_WR = (uint32_t)((uint32_t)CY_CRYPTO_TRNG_OPC << CY_CRYPTO_OPCODE_POS); + + /* Wait until the TRNG instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_TR_BUSY, CRYPTO->STATUS)) + { + } + + *cryptoTrngContext->trngNumPtr = (uint32_t)_FLD2VAL(CRYPTO_TR_RESULT_DATA32, CRYPTO->TR_RESULT); + + return (CY_CRYPTO_SUCCESS); +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng.h new file mode 100644 index 0000000000..40678e30f7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng.h @@ -0,0 +1,37 @@ +/***************************************************************************//** +* \file cy_crypto_core_trng.h +* \version 1.0 +* +* \brief +* This file provides provides constant and parameters +* for the API of the TRNG in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CORE_TRNG_H) +#define CY_CRYPTO_CORE_TRNG_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) + + +cy_en_crypto_status_t Cy_Crypto_Core_Trng(cy_stc_crypto_context_trng_t *cryptoTrngContext); + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) */ +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_TRNG_H) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng_config.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng_config.h new file mode 100644 index 0000000000..1600d040f9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_trng_config.h @@ -0,0 +1,239 @@ +/***************************************************************************//** +* \file cy_crypto_core_trng_config.h +* \version 1.0 +* +* \brief +* This file provides internal (not public) constant and parameters +* for the Crypto TRNG driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CORE_TRNG_CONFIG_H) +#define CY_CRYPTO_CORE_TRNG_CONFIG_H + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_TR == 1)) + + +/** TRNG Configuration default values */ +/** +* Specifies the clock divider that is used to sample oscillator data. +* This clock divider is wrt. "clk_sys". +* "0": sample clock is "clk_sys". +* "1": sample clock is "clk_sys"/2. +* ... +* "255": sample clock is "clk_sys"/256. +*/ +#define CY_CRYPTO_TR_SAMPLE_CLOCK_DIV (0UL) + +/** +* Specifies the clock divider used to produce reduced bits. +* "0": 1 reduced bit is produced for each sample. +* "1": 1 reduced bit is produced for each 2 samples. +* ... +* "255": 1 reduced bit is produced for each 256 samples. +* +* The reduced bits are considered random bits and shifted into TR_RESULT0.DATA32. +*/ +#define CY_CRYPTO_TR_RED_CLOCK_DIV (0UL) + +/** +* Specifies an initialization delay: a number of removed/dropped samples before +* reduced bits are generated. This field should be programmed in the range [1, 255]. +* After starting the oscillators, at least the first 2 samples should be +* removed/dropped to clear the state of internal synchronizers. In addition, +* it is advised to drop at least the second 2 samples from the oscillators +* (to circumvent the semi-predictable oscillator start-up behavior). This results +* in the default field value of "3". the field encoding is as follows: +* "0": 1 sample is dropped. +* "1": 2 samples are dropped. +* ... +* "255": 256 samples are dropped. +* +* The TR_INITIALIZED interrupt cause is set to '1', when the initialization delay is passed. +*/ +#define CY_CRYPTO_TR_INIT_DELAY (3UL) + +/** +* Specifies if the "von Neumann corrector" is disabled or enabled: +* '0': disabled. +* '1': enabled. +* The "von Neumann corrector" post-processes the reduced bits to remove a '0' or '1' bias. +* The corrector operates on reduced bit pairs ("oldest bit, newest bit"): +* "00": no bit is produced. +* "01": '0' bit is produced (oldest bit). +* "10": '1' bit is produced (oldest bit). +* "11": no bit is produced. +* NOTE: The corrector produces bits at a random pace and at a frequency that +* is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, +* and half of the pairs do NOT produce a bit). +*/ +#define CY_CRYPTO_TR_VON_NEUMANN_CORR (1UL) + +/** +* Specifies if the TRNG functionality is stopped on an adaptive proportion test +* detection (when HW sets INTR.TR_AP_DETECT to '1'): +* '0': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). +* '1': Functionality is NOT stopped. +*/ +#define CY_CRYPTO_TR_STOP_ON_AP_DETECT (1UL) + +/** +* Specifies if the TRNG functionality is stopped on a repetition count test detection +* (when HW sets INTR.TR_RC_DETECT to '1'): +* '0': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). +* '1': Functionality is NOT stopped. +*/ +#define CY_CRYPTO_TR_STOP_ON_RC_DETECT (1UL) + +/** FW sets this field to '1' to enable the ring oscillator with 11 inverters. */ +#define CY_CRYPTO_TR_RO11_EN (1UL) + +/** FW sets this field to '1' to enable the ring oscillator with 15 inverters. */ +#define CY_CRYPTO_TR_RO15_EN (1UL) + +/** +* FW sets this field to '1' to enable the fixed Galois ring oscillator +* with 15 inverters. +*/ +#define CY_CRYPTO_TR_GARO15_EN (1UL) + +/** +* FW sets this field to '1' to enable the programmable Galois ring oscillator with up +* to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial. +*/ +#define CY_CRYPTO_TR_GARO31_EN (1UL) + +/** FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters. */ +#define CY_CRYPTO_TR_FIRO15_EN (1UL) + +/** +* FW sets this field to '1' to enable the programmable Fibonacci ring oscillator +* with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial. +*/ +#define CY_CRYPTO_TR_FIRO31_EN (1UL) + +/** +* The polynomial for programmable Galois ring oscillator. The polynomial is represented +* WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned +* so that the more significant bits (bit 30 and down) contain the polynomial and the less +* significant bits (bit 0 and up) contain padding '0's. +*/ +#define CY_CRYPTO_TR_GARO (1UL) + +/** +* The polynomial for the programmable Fibonacci ring oscillator. The polynomial is represented +* WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should +* be aligned so that the more significant bits (bit 30 and down) contain the polynomial +* and the less significant bits (bit 0 and up) contain padding '0's. +*/ +#define CY_CRYPTO_TR_FIRO (1UL) + +/** +* Selection of the bit stream: +* "0": DAS bit stream. +* "1": RED bit stream. +* "2": TR bit stream. +* "3": Undefined. +*/ +#define CY_CRYPTO_TR_BITSTREAM_SEL (0UL) + +/** +* Adaptive proportion (AP) test enable: +* '0': Stopped. +* '1': Started. +* +* On AP detection, HW sets this field to '0' and sets INTR.TR_AP_DETECT to '1. +*/ +#define CY_CRYPTO_TR_START_AP (0UL) + +/** +* Repetition count (RC) test enable: +* '0': Disabled. +* '1': Enabled. +* +* On RC detection, HW sets this field to '0' and sets INTR.TR_RC_DETECT to '1. +*/ +#define CY_CRYPTO_TR_START_RC (0UL) + +/** +* Cut-off count (legal range is [1, 255]): +* "0": Illegal. +* "1": 1 repetition. +* ... +* "255": 255 repetitions. +*/ +#define CY_CRYPTO_TR_CUTOFF_COUNT8 (1UL) + +/** +Cut-off count (legal range is [1, 65535]). +"0": Illegal. +"1": 1 occurrence. +... +"65535": 65535 occurrences. +*/ +#define CY_CRYPTO_TR_CUTOFF_COUNT16 (1UL) + +/** +* The window size (minus 1) : +* "0": 1 bit. +* ... +* "65535": 65536 bits. +*/ +#define CY_CRYPTO_TR_WINDOW_SIZE (1uL) + +/** the composed value for the TR_CTL0 register */ +#define CY_CRYPTO_TR_CTL0_VAL (_VAL2FLD(CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV, CY_CRYPTO_TR_SAMPLE_CLOCK_DIV) | \ + _VAL2FLD(CRYPTO_TR_CTL0_RED_CLOCK_DIV, CY_CRYPTO_TR_RED_CLOCK_DIV) | \ + _VAL2FLD(CRYPTO_TR_CTL0_INIT_DELAY, CY_CRYPTO_TR_INIT_DELAY) | \ + _VAL2FLD(CRYPTO_TR_CTL0_VON_NEUMANN_CORR, CY_CRYPTO_TR_VON_NEUMANN_CORR) | \ + _VAL2FLD(CRYPTO_TR_CTL0_STOP_ON_AP_DETECT, CY_CRYPTO_TR_STOP_ON_AP_DETECT) | \ + _VAL2FLD(CRYPTO_TR_CTL0_STOP_ON_RC_DETECT, CY_CRYPTO_TR_STOP_ON_RC_DETECT)) + +/** The composed value for the TR_CTL1 register */ +#define CY_CRYPTO_TR_CTL1_VAL (_VAL2FLD(CRYPTO_TR_CTL1_RO11_EN, CY_CRYPTO_TR_RO11_EN) | \ + _VAL2FLD(CRYPTO_TR_CTL1_RO15_EN, CY_CRYPTO_TR_RO15_EN) | \ + _VAL2FLD(CRYPTO_TR_CTL1_GARO15_EN, CY_CRYPTO_TR_GARO15_EN) | \ + _VAL2FLD(CRYPTO_TR_CTL1_GARO31_EN, CY_CRYPTO_TR_GARO31_EN) | \ + _VAL2FLD(CRYPTO_TR_CTL1_FIRO15_EN, CY_CRYPTO_TR_FIRO15_EN) | \ + _VAL2FLD(CRYPTO_TR_CTL1_FIRO31_EN, CY_CRYPTO_TR_FIRO31_EN)) + +/** The composed value for the TR_MON_CTL register */ +#define CY_CRYPTO_TR_BTSTR_SEL (_VAL2FLD(CRYPTO_TR_MON_CTL_BITSTREAM_SEL, CY_CRYPTO_TR_BITSTREAM_SEL)) + +/** The composed value for the TR_MON_CMD register */ +#define CY_CRYPTO_TR_START_MON (_VAL2FLD(CRYPTO_TR_MON_CMD_START_AP, CY_CRYPTO_TR_START_AP) | \ + _VAL2FLD(CRYPTO_TR_MON_CMD_START_RC, CY_CRYPTO_TR_START_RC)) + +/** The composed value for the TR_MON_RC_CTL register */ +#define CY_CRYPTO_TR_RC_CUTOFF (_VAL2FLD(CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8, CY_CRYPTO_TR_CUTOFF_COUNT8)) + +/** The composed value for the TR_MON_AP_CTL register */ +#define CY_CRYPTO_TR_AC_CUTOFF (_VAL2FLD(CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16, CY_CRYPTO_TR_CUTOFF_COUNT16) | \ + _VAL2FLD(CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE, CY_CRYPTO_TR_WINDOW_SIZE)) + +/** Default TRNG configuration */ +#define CY_CRYPTO_TR_DEFAULT_CONFIG \ +{ \ + CY_CRYPTO_TR_CTL0_VAL, \ + CY_CRYPTO_TR_CTL1_VAL, \ + CY_CRYPTO_TR_GARO, \ + CY_CRYPTO_TR_FIRO, \ + CY_CRYPTO_TR_BITSTREAM_SEL,\ + CY_CRYPTO_TR_START_MON, \ + CY_CRYPTO_TR_RC_CUTOFF, \ + CY_CRYPTO_TR_AC_CUTOFF \ +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_TR == 1)) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_TRNG_CONFIG_H) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_util.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_util.c new file mode 100644 index 0000000000..814940c544 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_util.c @@ -0,0 +1,485 @@ +/***************************************************************************//** +* \file cy_crypto_core_util.c +* \version 1.0 +* +* \brief +* This file provides the source code to the API for the utils +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "crypto/cy_crypto_core_vu_hw.h" +#include "syslib/cy_syslib.h" +#include + + +#if (CY_CPU_CORTEX_M0P) + +#if (CPUSS_CRYPTO_PRESENT == 1) + +/* The flag to state that an HW error occurred */ +bool cy_crypto_IsHwErrorOccured = false; + +void Cy_Crypto_Core_ErrorHandler(void); + + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Enable +****************************************************************************//** +* +* The function to enable the Crypto hardware. +* +* This function available for CM0+ core only. +* +* \return +* Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Enable(void) +{ + /* Enable Crypto HW */ + CRYPTO->CTL = (uint32_t)(_VAL2FLD(CRYPTO_CTL_ISOLATE, 1uL) | + _VAL2FLD(CRYPTO_CTL_RETAIN, 0uL) | + _VAL2FLD(CRYPTO_CTL_POWER, 1uL) | + _VAL2FLD(CRYPTO_CTL_ENABLED, 1uL)); + + CRYPTO->CTL = (uint32_t)(_VAL2FLD(CRYPTO_CTL_ISOLATE, 0uL) | + _VAL2FLD(CRYPTO_CTL_RETAIN, 0uL) | + _VAL2FLD(CRYPTO_CTL_POWER, 1uL) | + _VAL2FLD(CRYPTO_CTL_ENABLED, 1uL)); + +#if (CPUSS_CRYPTO_VU == 1) + + CRYPTO->VU_CTL1 = (uint32_t)CRYPTO->MEM_BUFF; + + /* Set the stack pointer to the Crypto buff size, in words */ + CY_CRYPTO_VU_SET_REG(15, CPUSS_CRYPTO_BUFF_SIZE, 1); + + /* Clear whole register file */ + CY_CRYPTO_VU_SET_REG(14, 0, 1); + CY_CRYPTO_VU_SET_REG(13, 0, 1); + CY_CRYPTO_VU_SET_REG(12, 0, 1); + CY_CRYPTO_VU_SET_REG(11, 0, 1); + CY_CRYPTO_VU_SET_REG(10, 0, 1); + CY_CRYPTO_VU_SET_REG(9, 0, 1); + CY_CRYPTO_VU_SET_REG(8, 0, 1); + CY_CRYPTO_VU_SET_REG(7, 0, 1); + CY_CRYPTO_VU_SET_REG(6, 0, 1); + CY_CRYPTO_VU_SET_REG(5, 0, 1); + CY_CRYPTO_VU_SET_REG(4, 0, 1); + CY_CRYPTO_VU_SET_REG(3, 0, 1); + CY_CRYPTO_VU_SET_REG(2, 0, 1); + CY_CRYPTO_VU_SET_REG(1, 0, 1); + CY_CRYPTO_VU_SET_REG(0, 0, 1); + +#endif /* #if (CPUSS_CRYPTO_VU == 1) */ + + return (CY_CRYPTO_SUCCESS); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Disable +****************************************************************************//** +* +* Disables the operation of the CRYPTO block. +* +* This function available for CM0+ core only. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_Disable(void) +{ + CRYPTO->CTL = (uint32_t)(_VAL2FLD(CRYPTO_CTL_ISOLATE, 0uL) | + _VAL2FLD(CRYPTO_CTL_RETAIN, 0uL) | + _VAL2FLD(CRYPTO_CTL_POWER, 0uL) | + _VAL2FLD(CRYPTO_CTL_ENABLED, 0uL)); + + return (CY_CRYPTO_SUCCESS); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_CheckHwForErrors +****************************************************************************//** +* +* The function checks if a Crypto HW error occurred. If yes, copy the error +* information from the Crypto registers to the communication structure. +* +* This function available for CM0+ core only. +* +* \param cryptoContext +* The pointer to vcy_stc_crypto_context_t structure which stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Core_CheckHwForErrors(cy_stc_crypto_context_t *cryptoContext) +{ + cy_en_crypto_status_t result = CY_CRYPTO_SUCCESS; + + if (cy_crypto_IsHwErrorOccured) + { + result = CY_CRYPTO_HW_ERROR; + + } + + cryptoContext->hwErrorStatus.errorStatus0 = _FLD2VAL(CRYPTO_ERROR_STATUS0_DATA32, CRYPTO->ERROR_STATUS0); + + cryptoContext->hwErrorStatus.errorStatus1 = (_FLD2VAL(CRYPTO_ERROR_STATUS1_DATA23, CRYPTO->ERROR_STATUS1) | + _FLD2VAL(CRYPTO_ERROR_STATUS1_IDX, CRYPTO->ERROR_STATUS1) | + _FLD2VAL(CRYPTO_ERROR_STATUS1_VALID, CRYPTO->ERROR_STATUS1)); + return (result); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_SetReg1Instr +****************************************************************************//** +* +* Writes one 32-Bit data word into Crypto FIFO. +* +* This function available for CM0+ core only. +* +* \param data0 +* The address of data to be placed into Crypto FIFO +* on the address CRYPTO_REGFILE_R0. +* +*******************************************************************************/ +void Cy_Crypto_SetReg1Instr(uint32_t data0) +{ + /* Check whether FIFO has enough space for 1 instruction */ + while(Cy_Crypto_Core_GetFIFOUsed() >= (CY_CRYPTO_FIFODEPTH - 1u)) + { + } + + CRYPTO->INSTR_FF_WR = (uint32_t)(((uint32_t)CY_CRYPTO_SET_REG1_OPC << CY_CRYPTO_OPCODE_POS) | + (uint32_t)CY_CRYPTO_REGFILE_R0); + + CRYPTO->INSTR_FF_WR = data0; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_SetReg2Instr +****************************************************************************//** +* +* Writes two 32-Bit data words into Crypto FIFO. +* +* This function available for CM0+ core only. +* +* \param data0 +* The address of data to be placed into Crypto FIFO +* on the address CRYPTO_REGFILE_R0. +* +* \param data1 +* The address of data to be placed into Crypto FIFO +* on the address CRYPTO_REGFILE_R1. +* +*******************************************************************************/ +void Cy_Crypto_SetReg2Instr(uint32_t data0, uint32_t data1) +{ + /* Check whether FIFO has enough space for 2 instructions */ + while(Cy_Crypto_Core_GetFIFOUsed() >= (CY_CRYPTO_FIFODEPTH - 2u)) + { + } + + CRYPTO->INSTR_FF_WR = (uint32_t)(((uint32_t)CY_CRYPTO_SET_REG2_OPC << CY_CRYPTO_OPCODE_POS) | + ((uint32_t)CY_CRYPTO_REGFILE_R1 << CY_CRYPTO_RSRC4_SHIFT) | + (uint32_t)CY_CRYPTO_REGFILE_R0); + + CRYPTO->INSTR_FF_WR = data0; + CRYPTO->INSTR_FF_WR = data1; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_SetReg3Instr +****************************************************************************//** +* +* Writes three 32-Bit data words into Crypto FIFO. +* +* This function available for CM0+ core only. +* +* \param data0 +* The address of data to be placed into Crypto FIFO +* on the address CRYPTO_REGFILE_R0. +* +* \param data1 +* The address of data to be placed into Crypto FIFO +* on the address CRYPTO_REGFILE_R1. +* +* \param data2 +* The address of data to be be placed into Crypto FIFO +* on the address CRYPTO_REGFILE_R2. +* +*******************************************************************************/ +void Cy_Crypto_SetReg3Instr(uint32_t data0, uint32_t data1, uint32_t data2) +{ + /* Check whether FIFO has enough space for 3 instructions */ + while(Cy_Crypto_Core_GetFIFOUsed() >= (CY_CRYPTO_FIFODEPTH - 3u)) + { + } + + CRYPTO->INSTR_FF_WR = (uint32_t)( ((uint32_t)CY_CRYPTO_SET_REG3_OPC << CY_CRYPTO_OPCODE_POS) | + ((uint32_t)CY_CRYPTO_REGFILE_R2 << CY_CRYPTO_RSRC8_SHIFT) | + ((uint32_t)CY_CRYPTO_REGFILE_R1 << CY_CRYPTO_RSRC4_SHIFT) | + (uint32_t)CY_CRYPTO_REGFILE_R0 ); + + CRYPTO->INSTR_FF_WR = data0; + CRYPTO->INSTR_FF_WR = data1; + CRYPTO->INSTR_FF_WR = data2; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_SetReg4Instr +****************************************************************************//** +* +* Writes four 32-Bit data words into Crypto FIFO. +* +* This function available for CM0+ core only. +* +* \param data0 +* The address of data to be placed into Crypto FIFO +* on the address CRYPTO_REGFILE_R0. +* +* \param data1 +* The address of data to be placed into Crypto FIFO +* on the address CRYPTO_REGFILE_R1. +* +* \param data2 +* The address of data to be placed into Crypto FIFO +* on the address CRYPTO_REGFILE_R2. +* +* \param data3 +* The address of data to be placed into Crypto FIFO +* on the address CRYPTO_REGFILE_R3. +* +*******************************************************************************/ +void Cy_Crypto_SetReg4Instr(uint32_t data0, uint32_t data1, uint32_t data2, uint32_t data3) +{ + /* Check whether FIFO has enough space for 4 instructions */ + while(Cy_Crypto_Core_GetFIFOUsed() >= (CY_CRYPTO_FIFODEPTH - 4u)) + { + } + + CRYPTO->INSTR_FF_WR = (uint32_t)(((uint32_t)CY_CRYPTO_SET_REG4_OPC << CY_CRYPTO_OPCODE_POS) | + ((uint32_t)CY_CRYPTO_REGFILE_R3 << CY_CRYPTO_RSRC12_SHIFT) | + ((uint32_t)CY_CRYPTO_REGFILE_R2 << CY_CRYPTO_RSRC8_SHIFT) | + ((uint32_t)CY_CRYPTO_REGFILE_R1 << CY_CRYPTO_RSRC4_SHIFT) | + (uint32_t)CY_CRYPTO_REGFILE_R0); + + CRYPTO->INSTR_FF_WR = data0; + CRYPTO->INSTR_FF_WR = data1; + CRYPTO->INSTR_FF_WR = data2; + CRYPTO->INSTR_FF_WR = data3; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Run0ParamInstr +*****************************************************************************//** +* +* Run the Crypto instruction without parameters. +* +* This function available for CM0+ core only. +* +* \param instr +* The Opcode of the called instruction. +* +*******************************************************************************/ +void Cy_Crypto_Run0ParamInstr(uint8_t instr) +{ + /* Check whether FIFO has enough space for 1 instruction */ + while(Cy_Crypto_Core_GetFIFOUsed() >= CY_CRYPTO_FIFODEPTH) + { + } + + CRYPTO->INSTR_FF_WR = (uint32_t)((uint32_t)instr << CY_CRYPTO_OPCODE_POS); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Run1ParamInstr +*****************************************************************************//** +* +* Run the Crypto instruction with one parameter. +* The parameter must be placed into register 0 +* +* This function available for CM0+ core only. +* +* \param instr +* The Opcode of the called instruction. +* +* \param rdst0Shift +* The shift for the instruction operand. +* +*******************************************************************************/ +void Cy_Crypto_Run1ParamInstr(uint8_t instr, + uint32_t rdst0Shift) +{ + /* Check whether FIFO has enough space for 1 instruction */ + while(Cy_Crypto_Core_GetFIFOUsed() >= CY_CRYPTO_FIFODEPTH) + { + } + + CRYPTO->INSTR_FF_WR = (uint32_t)(((uint32_t)instr << CY_CRYPTO_OPCODE_POS) | + ((uint32_t)CY_CRYPTO_REGFILE_R0 << rdst0Shift)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Run2ParamInstr +*****************************************************************************//** +* +* Run the Crypto instruction with two parameters. +* The zero parameter must be placed into register 0, +* the first parameter must be placed into register 1. +* +* This function available for CM0+ core only. +* +* \param instr +* The Opcode of the called instruction. +* +* \param rdst0Shift +* The shift for the zero instruction operand. +* +* \param rdst1Shift +* The shift for the second instruction operand. +* +*******************************************************************************/ +void Cy_Crypto_Run2ParamInstr(uint8_t instr, + uint32_t rdst0Shift, + uint32_t rdst1Shift) +{ + /* Check whether FIFO has enough space for 1 instruction */ + while(Cy_Crypto_Core_GetFIFOUsed() >= CY_CRYPTO_FIFODEPTH) + { + } + + CRYPTO->INSTR_FF_WR = (uint32_t)(((uint32_t)instr << CY_CRYPTO_OPCODE_POS) | + ((uint32_t)CY_CRYPTO_REGFILE_R1 << rdst1Shift) | + ((uint32_t)CY_CRYPTO_REGFILE_R0 << rdst0Shift)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Run3ParamInstr +*****************************************************************************//** +* +* Run the Crypto instruction with three parameters. +* The zero parameter must be placed into register 0, +* the first parameter must be placed into register 1, +* the second parameter must be placed into register 2. +* +* This function available for CM0+ core only. +* +* \param instr +* The Opcode of the called instruction. +* +* \param rdst0Shift +* The shift for the zero instruction operand. +* +* \param rdst1Shift +* The shift for the second instruction operand. +* +** \param rdst2Shift +* The shift for the second instruction operand. +* +*******************************************************************************/ +void Cy_Crypto_Run3ParamInstr(uint8_t instr, + uint8_t rdst0Shift, + uint8_t rdst1Shift, + uint8_t rdst2Shift) +{ + /* Check whether FIFO has enough space for 1 instruction */ + while(Cy_Crypto_Core_GetFIFOUsed() >= CY_CRYPTO_FIFODEPTH) + { + } + + CRYPTO->INSTR_FF_WR = (uint32_t)(((uint32_t)instr << CY_CRYPTO_OPCODE_POS) | + ((uint32_t)CY_CRYPTO_REGFILE_R2 << rdst2Shift) | + ((uint32_t)CY_CRYPTO_REGFILE_R1 << rdst1Shift) | + ((uint32_t)CY_CRYPTO_REGFILE_R0 << rdst0Shift)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Run4ParamInstr +*****************************************************************************//** +* +* Run the Crypto instruction with four parameters. +* The zero parameter must be placed into register 0, +* the first parameter must be placed into register 1, +* the second parameter must be placed into register 2, +* the third parameter must be placed into register 3. +* +* This function available for CM0+ core only. +* +* \param instr +* The Opcode of the called instruction. +* +* \param rdst0Shift +* The shift for the zero instruction operand. +* +* \param rdst1Shift +* The shift for the first instruction operand. +* +* \param rdst2Shift +* The shift for the second instruction operand. +* +* \param rdst3Shift +* The shift for the third instruction operand. +* +*******************************************************************************/ +void Cy_Crypto_Run4ParamInstr(uint8_t instr, + uint32_t rdst0Shift, + uint32_t rdst1Shift, + uint32_t rdst2Shift, + uint32_t rdst3Shift) +{ + /* Check whether FIFO has enough space for 1 instruction */ + while(Cy_Crypto_Core_GetFIFOUsed() >= CY_CRYPTO_FIFODEPTH) + { + } + + CRYPTO->INSTR_FF_WR = (uint32_t)(((uint32_t)instr << CY_CRYPTO_OPCODE_POS) | + ((uint32_t)CY_CRYPTO_REGFILE_R3 << rdst3Shift) | + ((uint32_t)CY_CRYPTO_REGFILE_R2 << rdst2Shift) | + ((uint32_t)CY_CRYPTO_REGFILE_R1 << rdst1Shift) | + ((uint32_t)CY_CRYPTO_REGFILE_R0 << rdst0Shift)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_InvertEndian8 +*****************************************************************************//** +* +* Inverts endianness for eight bytes. +* +* This function available for CM0+ core only. +* +* \param srcVal +* The input data whose endianness will be inverted. +* +* \return +* An input value with inverted endianness. +* +*******************************************************************************/ +uint64_t Cy_Crypto_InvertEndian8(uint64_t srcVal) +{ + uint64_t tmpVal; + + tmpVal = ((srcVal << 8u) & 0xFF00FF00FF00FF00ULL) | ((srcVal >> 8u) & 0x00FF00FF00FF00FFULL); + tmpVal = ((tmpVal << 16u) & 0xFFFF0000FFFF0000ULL) | ((tmpVal >> 16u) & 0x0000FFFF0000FFFFULL); + + return ((tmpVal << 32u) | (tmpVal >> 32u)); +} + +#endif /* #if (CPUSS_CRYPTO_PRESENT == 1) */ +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_util.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_util.h new file mode 100644 index 0000000000..c6254378a6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_util.h @@ -0,0 +1,132 @@ +/***************************************************************************//** +* \file cy_crypto_core_util.h +* \version 1.0 +* +* \brief +* This file provides the headers to the API for the utils +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_CRYPTO_CORE_UTIL_H) +#define CY_CRYPTO_CORE_UTIL_H + +#include "cy_crypto_common.h" +#include "syslib/cy_syslib.h" +#include + + +#if (CY_CPU_CORTEX_M0P) + +#if (CPUSS_CRYPTO_PRESENT == 1) + + +extern bool cy_crypto_IsHwErrorOccured; + +typedef enum { + CY_CRYPTO_CTL_ENABLED_DISABLED = 0u, + CY_CRYPTO_CTL_ENABLED_ENABLED = 1u, +} cy_en_crypto_hw_enable_t; + + +cy_en_crypto_status_t Cy_Crypto_Core_Enable(void); + +cy_en_crypto_status_t Cy_Crypto_Core_Disable(void); + +cy_en_crypto_status_t Cy_Crypto_Core_CheckHwForErrors(cy_stc_crypto_context_t *cryptoContext); + +void Cy_Crypto_SetReg1Instr(uint32_t data0); + +void Cy_Crypto_SetReg2Instr(uint32_t data0, uint32_t data1); + +void Cy_Crypto_SetReg3Instr(uint32_t data0, uint32_t data1, uint32_t data2); + +void Cy_Crypto_SetReg4Instr(uint32_t data0, uint32_t data1, uint32_t data2, uint32_t data3); + +void Cy_Crypto_Run0ParamInstr(uint8_t instr); + +void Cy_Crypto_Run1ParamInstr(uint8_t instr, + uint32_t rdst0Shift); + +void Cy_Crypto_Run2ParamInstr(uint8_t instr, + uint32_t rdst0Shift, + uint32_t rdst1Shift); + +void Cy_Crypto_Run3ParamInstr(uint8_t instr, + uint8_t rdst0Shift, + uint8_t rdst1Shift, + uint8_t rdst2Shift); + +void Cy_Crypto_Run4ParamInstr(uint8_t instr, + uint32_t rdst0Shift, + uint32_t rdst1Shift, + uint32_t rdst2Shift, + uint32_t rdst3Shift); + +uint64_t Cy_Crypto_InvertEndian8(uint64_t srcVal); + +/******************************************************************************* +* Function Name: Crypto_Server_GetFIFOUsed +****************************************************************************//** +* +* Returns the number of instructions in the instruction FIFO. +* The value of this field ranges from 0 to 8 +* +*******************************************************************************/ +__STATIC_INLINE uint8_t Cy_Crypto_Core_GetFIFOUsed(void) +{ + return((uint8_t)_FLD2VAL(CRYPTO_INSTR_FF_STATUS_USED, CRYPTO->INSTR_FF_STATUS)); +} + +/******************************************************************************* +* Function Name: Crypto_Server_WaitForFifoAvailable +*****************************************************************************//** +* +* Waits until number of entries in the instruction FIFO is less than +* specified in EVENT_LEVEL field in FF_CTL register, an event is generated: +* "event" = INSTR_FF_STATUS.USED < EVENT_LEVEL. +* By default EVENT_LEVEL = 0; +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_Crypto_Core_WaitForFifoAvailable(void) +{ + while((_FLD2VAL(CRYPTO_INSTR_FF_STATUS_EVENT, CRYPTO->INSTR_FF_STATUS)) == 0) + { + } +} + +/******************************************************************************* +* Function Name: Crypto_Server_WaitForFifoAvailable ??? +*****************************************************************************//** +* +* Waits until all instruction in FIFO will be completed +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_Crypto_Core_WaitForReady(void) +{ + while((_FLD2VAL(CRYPTO_INSTR_FF_STATUS_BUSY, CRYPTO->INSTR_FF_STATUS)) == 1) + { + } +} + + +#endif /* #if (CPUSS_CRYPTO_PRESENT == 1) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_UTIL_H) */ + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu.c new file mode 100644 index 0000000000..61ac07a75c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu.c @@ -0,0 +1,66 @@ +/***************************************************************************//** +* \file cy_crypto_core_vu.c +* \version 1.0 +* +* \brief +* This file provides the source code to the API for the Vector Unit functions +* in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "crypto/cy_crypto_core_vu.h" +#include "crypto/cy_crypto_core_util.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) + + +/******************************************************************************* +* Function Name: Cy_Crypto_Wait_Vu_ForComplete +****************************************************************************//** +* +* Waits until VU instruction will be completed +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +void Cy_Crypto_Core_Vu_WaitForComplete(void) +{ + /* Wait until the VU instruction is complete */ + while(0uL != _FLD2VAL(CRYPTO_STATUS_VU_BUSY, CRYPTO->STATUS)) + { + } +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Vu_StatusRead +****************************************************************************//** +* +* Returns value of the VU status register +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +uint16_t Cy_Crypto_Core_Vu_StatusRead(void) +{ + Cy_Crypto_Core_WaitForReady(); + + return((uint16_t)CRYPTO->VU_STATUS); +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu.h new file mode 100644 index 0000000000..1bfb726191 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu.h @@ -0,0 +1,136 @@ +/***************************************************************************//** +* \file cy_crypto_core_vu.h +* \version 1.0 +* +* \brief +* This file provides constants and function prototypes +* for the Vector Unit functions in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CORE_VU_H) +#define CY_CRYPTO_CORE_VU_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) + + +/* Function Prototypes */ +void Cy_Crypto_Core_Vu_WaitForComplete(void); +uint16_t Cy_Crypto_Core_Vu_StatusRead(void); + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Vu_RegRead +****************************************************************************//** +* +* Returns size of the data pointed in given register, +* it is lower 14Bit of the 32Bit word +* +* \param srcReg +* +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_Crypto_Core_Vu_RegRead(uint8_t srcReg) +{ + return ((uint32_t)_FLD2VAL(CRYPTO_RF_DATA_DATA32, CRYPTO->RF_DATA[srcReg])); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Vu_RegSizeRead +****************************************************************************//** +* +* Returns size of the data pointed in given register, +* it is lower 14Bit of the 32Bit word +* +* \param srcReg +* +* +*******************************************************************************/ +__STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegSizeRead(uint8_t srcReg) +{ + return ((uint16_t)(_FLD2VAL(CRYPTO_RF_DATA_DATA32, CRYPTO->RF_DATA[srcReg]) & 0x00000fff)); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Vu_RegBitSizeRead +****************************************************************************//** +* +* Returns size of the data pointed in given register, in Bits. +* It is lower 14Bit of the 32Bit word +* +* \param srcReg +* +* +*******************************************************************************/ +__STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegBitSizeRead(uint8_t srcReg) +{ + return ((uint16_t)(_FLD2VAL(CRYPTO_RF_DATA_DATA32, CRYPTO->RF_DATA[srcReg]) & 0x00000fff) + 1); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Vu_RegByteSizeRead +****************************************************************************//** +* +* Returns size of the data pointed in given register, in Bytes. +* It is lower 14Bit of the 32Bit word +* +* \param srcReg +* +* +*******************************************************************************/ +__STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegByteSizeRead(uint8_t srcReg) +{ + return ((uint16_t)(_FLD2VAL(CRYPTO_RF_DATA_DATA32, CRYPTO->RF_DATA[srcReg]) & 0x00000fff) >> 3); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Vu_RegWordRead +****************************************************************************//** +* +* Returns size of the data pointed in given register, in words (uint32_t). +* It is lower 14Bit of the 32Bit word +* +* \param srcReg +* +* +*******************************************************************************/ +__STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegWordSizeRead(uint8_t srcReg) +{ + return ((uint16_t)(_FLD2VAL(CRYPTO_RF_DATA_DATA32, CRYPTO->RF_DATA[srcReg]) & 0x00000fff) >> 5); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Core_Vu_RegDataRead +****************************************************************************//** +* +* Returns the data pointer, in 14-bit format of the data pointed in given register, +* it is upper 16Bit of the 32Bir word. Pointer is in words (uint32_t). +* +* \param srcReg +* +* +*******************************************************************************/ +__STATIC_INLINE uint16_t Cy_Crypto_Core_Vu_RegDataPtrRead(uint8_t srcReg) +{ + return ((uint16_t)(_FLD2VAL(CRYPTO_RF_DATA_DATA32, CRYPTO->RF_DATA[srcReg]) >> 16) & 0x00003fff); +} + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +#endif /* #if (CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_VU_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu_hw.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu_hw.h new file mode 100644 index 0000000000..672f8f17e4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_core_vu_hw.h @@ -0,0 +1,380 @@ +/***************************************************************************//** +* \file cy_crypto_core_vu_hw.h +* \version 1.0 +* +* \brief +* This file provides constants and function prototypes +* for the Vector Unit functions in the Crypto block driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_CRYPTO_CORE_VU_HW_H) +#define CY_CRYPTO_CORE_VU_HW_H + +#include "cy_device_headers.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "syslib/cy_syslib.h" + + +#if (CY_CPU_CORTEX_M0P) + +#if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1)) + + +/* VU Instructions */ +#define CY_CRYPTO_VU_ALLOC_MEM(rdst, size) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_ALLOC_MEM_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)size - 1))) + +#define CY_CRYPTO_VU_CALLOC_MEM(rdst, size) \ +\ + {CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_ALLOC_MEM_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)size - 1)); \ +memset( (CRYPTO->MEM_BUFF + (((CRYPTO->RF_DATA[rdst] >> 16) & 0x00003fff) >> 2)), 0x00, 4 * (size + 31) / 32); } + +#define CY_CRYPTO_VU_FREE_MEM(reg_mask) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_FREE_MEM_OPC << 24) | \ + (uint32_t)reg_mask)) + +#define CY_CRYPTO_VU_SET_REG(rdst, data, size) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_SET_REG_OPC << 24) | \ + ((uint32_t)rdst << 26) | \ + ((uint32_t)data << 12) | \ + ((uint32_t)size - 1))) + +#define CY_CRYPTO_VU_MOV_REG(rdst, rsrc) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_MOV_REG_TO_STATUS_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc << 0))) + +#define CY_CRYPTO_VU_LD_REG(rdst, rsrc) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_LD_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc << 0))) + +#define CY_CRYPTO_VU_ST_REG(rdst, rsrc) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_ST_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc << 0))) + +#define CY_CRYPTO_VU_SWAP_REG(rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_SWAP_REG_OPC << 24) | \ + ((uint32_t)rsrc1 << 4) | \ + ((uint32_t)rsrc0 << 0))) + +#define CY_CRYPTO_VU_COND_SWAP_REG(cc, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_SWAP_REG_OPC << 24) | \ + ((uint32_t)cc << 20) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_MOV_REG_TO_STATUS(rsrc) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_MOV_REG_TO_STATUS_OPC << 24) | (uint32_t)rsrc)) + +#define CY_CRYPTO_VU_MOV_STATUS_TO_REG(rdst) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_MOV_STATUS_TO_REG_OPC << 24) | ((uint32_t)rdst << 12))) + +#define CY_CRYPTO_VU_PUSH_REG() (CRYPTO->INSTR_FF_WR = ((uint32_t)CY_CRYPTO_VU_PUSH_REG_OPC << 24)) + +#define CY_CRYPTO_VU_POP_REG() (CRYPTO->INSTR_FF_WR = ((uint32_t)CY_CRYPTO_VU_POP_REG_OPC << 24)) + +#define CY_CRYPTO_VU_ADD_REG(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_ADD_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_SUB_REG(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_SUB_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_OR_REG(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_OR_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_AND_REG(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_AND_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_XOR_REG(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_XOR_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_NOR_REG(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_NOR_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_NAND_REG(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_NAND_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_MIN_REG(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_MIN_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_MAX_REG(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_MAX_REG_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_LSL(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_LSL_OPC << 24) |\ + ((uint32_t)rdst << 12) |\ + ((uint32_t)rsrc1 << 4) |\ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_LSR(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_LSR_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_LSL1(rdst, rsrc1) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_LSL1_OPC << 24) |\ + ((uint32_t)rdst << 12) |\ + ((uint32_t)rsrc1 << 4))) + +#define CY_CRYPTO_VU_LSL1_WITH_CARRY(rdst, rsrc1) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_LSL1_WITH_CARRY_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4))) + +#define CY_CRYPTO_VU_LSR1(rdst, rsrc1) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_LSR1_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4))) + +#define CY_CRYPTO_VU_LSR1_WITH_CARRY(rdst, rsrc1) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_LSR1_WITH_CARRY_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4))) + +#define CY_CRYPTO_VU_SET_BIT(rdst, rsrc) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_SET_BIT_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + (uint32_t)rsrc)) + +#define CY_CRYPTO_VU_CLR_BIT(rdst, rsrc) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_CLR_BIT_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + (uint32_t)rsrc)) + +#define CY_CRYPTO_VU_INV_BIT(rdst, rsrc) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_INV_BIT_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + (uint32_t)rsrc)) + +#define CY_CRYPTO_VU_GET_BIT(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_GET_BIT_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_CLSAME(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_CLSAME_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_CTSAME(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_CTSAME_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_SET_TO_ZERO(rdst) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_SET_TO_ZERO_OPC << 24) | ((uint32_t)rdst << 12))) + +#define CY_CRYPTO_VU_SET_TO_ONE(rdst) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_SET_TO_ONE_OPC << 24) | ((uint32_t)rdst << 12))) + +#define CY_CRYPTO_VU_MOV(rdst, rsrc) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_MOV_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + (uint32_t)rsrc)) + +#define CY_CRYPTO_VU_COND_MOV(cc, rdst, rsrc) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_MOV_OPC << 24) | \ + ((uint32_t)cc << 20) | \ + ((uint32_t)rdst << 12) | \ + (uint32_t)rsrc)) + +#define CY_CRYPTO_VU_XSQUARE(rdst, rsrc) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_XSQUARE_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + (uint32_t)rsrc)) + +#define CY_CRYPTO_VU_CMP_SUB(rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_CMP_SUB_OPC << 24) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_COND_CMP_SUB(cc, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_CMP_SUB_OPC << 24) | \ + ((uint32_t)cc << 20) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_CMP_DEGREE(rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_CMP_DEGREE_OPC << 24) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_TST(rsrc0) (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_TST_OPC << 24) | (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_XMUL(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_XMUL_OPC << 24) |\ + ((uint32_t)rdst << 12) |\ + ((uint32_t)rsrc1 << 4) |\ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_UMUL(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_UMUL_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_ADD(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_ADD_OPC << 24) |\ + ((uint32_t)rdst << 12) |\ + ((uint32_t)rsrc1 << 4) |\ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_COND_ADD(cc, rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_ADD_OPC << 24) | \ + ((uint32_t)cc << 20) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_SUB(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_SUB_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_COND_SUB(cc, rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_SUB_OPC << 24) | \ + ((uint32_t)cc << 20) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_OR(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_OR_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_AND(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_AND_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_XOR(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_XOR_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_COND_XOR(cc, rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_XOR_OPC << 24) | \ + ((uint32_t)cc << 20) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_NOR(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_NOR_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + +#define CY_CRYPTO_VU_NAND(rdst, rsrc1, rsrc0) \ +\ + (CRYPTO->INSTR_FF_WR = (((uint32_t)CY_CRYPTO_VU_NAND_OPC << 24) | \ + ((uint32_t)rdst << 12) | \ + ((uint32_t)rsrc1 << 4) | \ + (uint32_t)rsrc0)) + + +#endif /* #if ((CPUSS_CRYPTO_PRESENT == 1) && (CPUSS_CRYPTO_VU == 1)) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_CORE_VU_HW_H) */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_server.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_server.c new file mode 100644 index 0000000000..34f7b95d7f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_server.c @@ -0,0 +1,409 @@ +/***************************************************************************//** +* \file cy_crypto_server.c +* \version 1.0 +* +* \brief +* This file provides the source code to the API for Crypto Server +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_device_headers.h" +#include "ipc/cy_ipc_drv.h" +#include "sysint/cy_sysint.h" +#include "syslib/cy_syslib.h" +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_server.h" +#include "crypto/cy_crypto_core_aes.h" +#include "crypto/cy_crypto_core_sha.h" +#include "crypto/cy_crypto_core_hmac.h" +#include "crypto/cy_crypto_core_cmac.h" +#include "crypto/cy_crypto_core_prng.h" +#include "crypto/cy_crypto_core_trng.h" +#include "crypto/cy_crypto_core_rsa.h" +#include "crypto/cy_crypto_core_str.h" +#include "crypto/cy_crypto_core_crc.h" +#include "crypto/cy_crypto_core_des.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_instructions.h" +#include + + +#if (CY_CPU_CORTEX_M0P) + +#if (CPUSS_CRYPTO_PRESENT == 1) + + +/* The number of the interrupt to catch Crypto HW errors */ +IRQn_CM0P_Type cy_crypto_ErrorIrqNum; + +/* + * The global variables to store a pointers on the customer callback functions. + * This variable is global because it is called from an interrupt. + */ +cy_israddress cy_cryptoGetDataHandlerPtr = NULL; +cy_israddress cy_cryptoErrorHandlerPtr = NULL; + +/* + * The global variable to store a pointer to crypto processing context data. + */ +cy_stc_crypto_context_t *processData = NULL; + +/* Functions Prototypes */ +void Cy_Crypto_Server_PopulateHwErrInfo(cy_stc_crypto_context_t *cryptoContextPtr); +void Cy_Crypto_Server_Run(cy_stc_crypto_context_t* data); +void Cy_Crypto_Server_Invoke(void); +void Cy_Crypto_Server_ErrorHandler(void); + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_Start +****************************************************************************//** +* +* Starts the Crypto server on the M0 core, sets up an interrupt +* for the IPC Crypto channel on the M0 core, sets up an interrupt +* to catch Crypto HW errors. Should be invoked only on CM0. +* +* This function available for CM0+ core only. +* +* \param configStruct +* The Crypto configuration structure. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Server_Start(cy_stc_crypto_config_t const *configStruct) +{ + /* Initialize the interrupt controller for M0 and IPC Interrupt */ + cy_stc_sysint_t intrCfg; + + intrCfg.intrSrc = (IRQn_Type)(cpuss_interrupts_ipc0_IRQn + CY_CRYPTO_NOTIFY_INTR); + + intrCfg.intrCm0p = (IRQn_CM0P_Type)(configStruct->cm0NotifyIntrNum); + + intrCfg.intrPriority = configStruct->notifyIntrPrior; + + if (configStruct->userGetDataHandler != NULL) + { + Cy_SysInt_Init(&intrCfg, configStruct->userGetDataHandler); + cy_cryptoGetDataHandlerPtr = configStruct->userGetDataHandler; + } + else + { + Cy_SysInt_Init(&intrCfg, &Cy_Crypto_Server_GetDataHandler); + } + + NVIC_EnableIRQ((IRQn_Type)intrCfg.intrCm0p); + + /* Do not bring up an IPC release interrupt here, only set up a notify interrupt */ + Cy_IPC_DRV_SetIntrMask(Cy_IPC_DRV_GetIntrBaseAddr(CY_CRYPTO_NOTIFY_INTR), CY_IPC_NO_NOTIFIFICATION, (1uL << CY_IPC_CHAN_CRYPTO)); + + /* Initialize and enable an interrupt to handle possible Crypto HW errors */ + intrCfg.intrSrc = (IRQn_Type)(cpuss_interrupt_crypto_IRQn); + + /* Initialize an interrupt to check a Crypto HW error*/ + cy_crypto_ErrorIrqNum = (IRQn_CM0P_Type)(configStruct->cm0CryptoErrorIntrNum); + + intrCfg.intrCm0p = cy_crypto_ErrorIrqNum; + + intrCfg.intrPriority = configStruct->cryptoErrorIntrPrior; + + if (configStruct->userErrorHandler != NULL) + { + Cy_SysInt_Init(&intrCfg, configStruct->userErrorHandler); + cy_cryptoErrorHandlerPtr = configStruct->userErrorHandler; + } + else + { + Cy_SysInt_Init(&intrCfg, &Cy_Crypto_Server_ErrorHandler); + } + + NVIC_ClearPendingIRQ((IRQn_Type)intrCfg.intrCm0p); + NVIC_EnableIRQ((IRQn_Type)intrCfg.intrCm0p); + + return (CY_CRYPTO_SUCCESS); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_Stop +****************************************************************************//** +* +* Stops the Crypto server by disabling the IPC notify interrupt +* and Crypto error interrupt. Should be invoked only on CM0. +* +* This function available for CM0+ core only. +* +* \param configStruct +* The Crypto configuration structure. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Server_Stop(cy_stc_crypto_config_t const *configStruct) +{ + uint32_t interruptMask; + + /* Disable the Notify interrupt from IPC */ + NVIC_DisableIRQ((IRQn_Type)configStruct->cm0NotifyIntrNum); + NVIC_ClearPendingIRQ((IRQn_Type)configStruct->cm0NotifyIntrNum); + + /* Disable the Error interrupt from Crypto */ + NVIC_DisableIRQ((IRQn_Type)configStruct->cm0CryptoErrorIntrNum); + NVIC_ClearPendingIRQ((IRQn_Type)configStruct->cm0CryptoErrorIntrNum); + + /* Disable CRYPTO IPC interrupt */ + interruptMask = Cy_IPC_DRV_GetIntrMask(Cy_IPC_DRV_GetIntrBaseAddr(CY_CRYPTO_NOTIFY_INTR)); + + Cy_IPC_DRV_SetIntrMask(Cy_IPC_DRV_GetIntrBaseAddr(CY_CRYPTO_NOTIFY_INTR), CY_IPC_NO_NOTIFIFICATION, interruptMask & ~(1uL << CY_IPC_CHAN_CRYPTO)); + + cy_cryptoGetDataHandlerPtr = NULL; + cy_cryptoErrorHandlerPtr = NULL; + + return (CY_CRYPTO_SUCCESS); +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_ErrorHandler +****************************************************************************//** +* +* The routine to handle an interrupt caused by the Crypto hardware error. +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +void Cy_Crypto_Server_ErrorHandler(void) +{ + NVIC_ClearPendingIRQ((IRQn_Type)cy_crypto_ErrorIrqNum); + cy_crypto_IsHwErrorOccured = true; +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_Process +****************************************************************************//** +* +* Parses input data received from the Crypto Client +* and runs the appropriate Crypto function. +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +void Cy_Crypto_Server_Process(void) +{ + cy_stc_crypto_context_t* data = processData; + + if (data != NULL) + { + /* Default error */ + data->resp = CY_CRYPTO_HW_NOT_ENABLED; + + if (CY_CRYPTO_INSTR_ENABLE == data->instr) + { + data->resp = Cy_Crypto_Core_Enable(); + } + else + { + /* Check if Crypto HW is enabled */ + if(1uL == (uint32_t)_FLD2VAL(CRYPTO_CTL_ENABLED, CRYPTO->CTL)) + { + data->resp = CY_CRYPTO_SUCCESS; + + switch(data->instr) + { + case CY_CRYPTO_INSTR_DISABLE: + data->resp = Cy_Crypto_Core_Disable(); + break; + +#if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) + case CY_CRYPTO_INSTR_PRNG_INIT: + data->resp = Cy_Crypto_Core_Prng_Init((cy_stc_crypto_context_prng_t*)data->xdata); + break; + + case CY_CRYPTO_INSTR_PRNG: + data->resp = Cy_Crypto_Core_Prng((cy_stc_crypto_context_prng_t*)data->xdata); + break; +#endif /* #if ((CPUSS_CRYPTO_PR == 1) && (CY_CRYPTO_USER_PR == 1)) */ + +#if ((CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) + case CY_CRYPTO_INSTR_TRNG: + data->resp = Cy_Crypto_Core_Trng((cy_stc_crypto_context_trng_t*)data->xdata); + break; +#endif /* #if ((CPUSS_CRYPTO_TR == 1) && (CY_CRYPTO_USER_TR == 1)) */ + +#if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) + case CY_CRYPTO_INSTR_AES_INIT: + data->resp = Cy_Crypto_Core_Aes_Init((cy_stc_crypto_context_aes_t *)data->xdata); + break; + +#if (CY_CRYPTO_USER_AES_ECB == 1) + case CY_CRYPTO_INSTR_AES_ECB: + data->resp = Cy_Crypto_Core_Aes_Ecb((cy_stc_crypto_context_aes_t *)data->xdata); + break; +#endif /* #if (CRYPTO_USER_AES_ECB == 1) */ + +#if (CY_CRYPTO_USER_AES_CBC == 1) + case CY_CRYPTO_INSTR_AES_CBC: + data->resp = Cy_Crypto_Core_Aes_Cbc((cy_stc_crypto_context_aes_t *)data->xdata); + break; +#endif /* #if (CRYPTO_USER_AES_CBC == 1) */ + +#if (CY_CRYPTO_USER_AES_CFB == 1) + case CY_CRYPTO_INSTR_AES_CFB: + data->resp = Cy_Crypto_Core_Aes_Cfb((cy_stc_crypto_context_aes_t *)data->xdata); + break; +#endif /* #if (CRYPTO_USER_AES_CFB == 1) */ + +#if (CY_CRYPTO_USER_AES_CTR == 1) + case CY_CRYPTO_INSTR_AES_CTR: + data->resp = Cy_Crypto_Core_Aes_Ctr((cy_stc_crypto_context_aes_t *)data->xdata); + break; +#endif /* #if (CRYPTO_USER_AES_CTR == 1) */ + +#if (CY_CRYPTO_USER_CMAC == 1) + case CY_CRYPTO_INSTR_CMAC: + data->resp = Cy_Crypto_Core_Cmac((cy_stc_crypto_context_aes_t *)data->xdata); + break; +#endif /* #if (CRYPTO_USER_CMAC == 1) */ + +#endif /* #if ((CPUSS_CRYPTO_AES == 1) && (CY_CRYPTO_USER_AES_ENABLE == 1)) */ + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) + case CY_CRYPTO_INSTR_SHA: + data->resp = Cy_Crypto_Core_Sha((cy_stc_crypto_context_sha_t *)data->xdata); + break; +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_SHA_ENABLE == 1)) */ + +#if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) + case CY_CRYPTO_INSTR_HMAC: + data->resp = Cy_Crypto_Core_Hmac((cy_stc_crypto_context_sha_t *)data->xdata); + break; +#endif /* #if ((CPUSS_CRYPTO_SHA == 1) && (CY_CRYPTO_USER_HMAC == 1)) */ + +#if ((CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) + case CY_CRYPTO_INSTR_MEM_CPY: + Cy_Crypto_Core_Str_MemCpy(((cy_stc_crypto_context_str_t* )data->xdata)->dstPtr, + ((cy_stc_crypto_context_str_t* )data->xdata)->srcPtr0, + (uint16_t)((cy_stc_crypto_context_str_t* )data->xdata)->dataSize ); + break; + + case CY_CRYPTO_INSTR_MEM_SET: + Cy_Crypto_Core_Str_MemSet(((cy_stc_crypto_context_str_t*)data->xdata)->dstPtr, + ((cy_stc_crypto_context_str_t*)data->xdata)->data, + (uint16_t)(((cy_stc_crypto_context_str_t*)data->xdata)->dataSize) ); + break; + + case CY_CRYPTO_INSTR_MEM_CMP: + *(uint32_t* )(((cy_stc_crypto_context_str_t* )data->xdata)->dstPtr) = + Cy_Crypto_Core_Str_MemCmp(((cy_stc_crypto_context_str_t* )data->xdata)->srcPtr0, + ((cy_stc_crypto_context_str_t* )data->xdata)->srcPtr1, + (uint16_t)((cy_stc_crypto_context_str_t* )data->xdata)->dataSize ); + break; + + case CY_CRYPTO_INSTR_MEM_XOR: + Cy_Crypto_Core_Str_MemXor(((cy_stc_crypto_context_str_t* )data->xdata)->srcPtr0, + ((cy_stc_crypto_context_str_t* )data->xdata)->srcPtr1, + ((cy_stc_crypto_context_str_t* )data->xdata)->dstPtr, + (uint16_t)((cy_stc_crypto_context_str_t* )data->xdata)->dataSize ); + break; +#endif /* #if ((CPUSS_CRYPTO_STR == 1) && (CY_CRYPTO_USER_STR == 1)) */ + +#if ((CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) + case CY_CRYPTO_INSTR_CRC_INIT: + data->resp = Cy_Crypto_Core_Crc_Init((cy_stc_crypto_context_crc_t*)data->xdata); + break; + + case CY_CRYPTO_INSTR_CRC: + data->resp = Cy_Crypto_Core_Crc((cy_stc_crypto_context_crc_t*)data->xdata); + break; +#endif /* #if ((CPUSS_CRYPTO_CRC == 1) && (CY_CRYPTO_USER_CRC == 1)) */ + +#if ((CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) + case CY_CRYPTO_INSTR_DES: + data->resp = Cy_Crypto_Core_Des((cy_stc_crypto_context_des_t *)data->xdata); + break; + + case CY_CRYPTO_INSTR_3DES: + data->resp = Cy_Crypto_Core_Tdes((cy_stc_crypto_context_des_t *)data->xdata); + break; +#endif /* #if ((CPUSS_CRYPTO_DES == 1) && (CY_CRYPTO_USER_DES == 1)) */ + +#if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) + case CY_CRYPTO_INSTR_RSA_PROC: + data->resp = Cy_Crypto_Core_Rsa_Proc((cy_stc_crypto_context_rsa_t *)data->xdata); + break; + + case CY_CRYPTO_INSTR_RSA_COEF: + data->resp = Cy_Crypto_Core_Rsa_Coef((cy_stc_crypto_context_rsa_t *)data->xdata); + break; +#endif /* #if ((CPUSS_CRYPTO_VU == 1) && (CY_CRYPTO_USER_VU == 1)) */ + +#if (CY_CRYPTO_USER_PKCS1_5 == 1) + case CY_CRYPTO_INSTR_RSA_VER: + data->resp = Cy_Crypto_Core_RsaVerify((cy_stc_crypto_context_rsa_ver_t *)data->xdata); + break; +#endif /* #if (CY_CRYPTO_USER_PKCS1_5 == 1) */ + + default: + data->resp = CY_CRYPTO_NOT_SUPPORTED; + break; + } + + if (CY_CRYPTO_SUCCESS == data->resp) + { + data->resp = Cy_Crypto_Core_CheckHwForErrors(data); + } + } + } + } +} + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_GetDataHandler +****************************************************************************//** +* +* The IPC Crypto channel notify interrupt-routine, +* receives information from the Crypto client, runs the process +* (if user not setup own handler), +* releases the Crypto IPC channel after the Crypto server completes. +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +void Cy_Crypto_Server_GetDataHandler() +{ + uint32_t interruptMasked; + + interruptMasked = Cy_IPC_DRV_GetIntrStatusMasked(Cy_IPC_DRV_GetIntrBaseAddr(CY_CRYPTO_NOTIFY_INTR)); + + /* + * Check that there is really the IPC Crypto Notify interrupt, + * because the same line can be used for the IPC Crypto Release interrupt. + */ + if((1uL << (CY_IPC_CHAN_CRYPTO + IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Pos)) == (interruptMasked & IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Msk)) + { + Cy_IPC_DRV_ClearIntr(Cy_IPC_DRV_GetIntrBaseAddr(CY_CRYPTO_NOTIFY_INTR), CY_IPC_NO_NOTIFIFICATION, interruptMasked >> IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Pos); + + if(CY_IPC_DRV_SUCCESS == Cy_IPC_DRV_ReadMsgPtr(Cy_IPC_DRV_GetIpcBaseAddress(CY_IPC_CHAN_CRYPTO), (void**)&processData)) + { + if (cy_cryptoGetDataHandlerPtr == NULL) + { + Cy_Crypto_Server_Process(); + } + + /* Release the Crypto IPC channel with the Release interrupt */ + (void)Cy_IPC_DRV_Release(Cy_IPC_DRV_GetIpcBaseAddress(CY_IPC_CHAN_CRYPTO), (1uL << CY_CRYPTO_RELEASE_INTR)); + } + } +} + +#endif /* #if (CPUSS_CRYPTO_PRESENT == 1) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_server.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_server.h new file mode 100644 index 0000000000..bcc6ccf74a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/crypto/cy_crypto_server.h @@ -0,0 +1,51 @@ +/***************************************************************************//** +* \file cy_crypto_server.h +* \version 1.0 +* +* \brief +* This file provides the prototypes for common API +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_CRYPTO_SERVER_H) +#define CY_CRYPTO_SERVER_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CPU_CORTEX_M0P) + +#if (CPUSS_CRYPTO_PRESENT == 1) + + +/** +* \addtogroup group_crypto_functions +* \{ +*/ + +cy_en_crypto_status_t Cy_Crypto_Server_Start(cy_stc_crypto_config_t const *configStruct); + +cy_en_crypto_status_t Cy_Crypto_Server_Stop(cy_stc_crypto_config_t const *configStruct); + +void Cy_Crypto_Server_Process(void); + +void Cy_Crypto_Server_GetDataHandler(void); +void Cy_Crypto_Server_ErrorHandler(void); + +/** \} group_crypto_functions */ + +#endif /* #if (CPUSS_CRYPTO_PRESENT == 1) */ + +#endif /* #if (CY_CPU_CORTEX_M0P) */ + +#endif /* #if !defined(CY_CRYPTO_SERVER_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.c new file mode 100644 index 0000000000..7f5f9922df --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.c @@ -0,0 +1,470 @@ +/***************************************************************************//** +* \file cy_flash.c +* \version 1.0 +* +* \brief +* Provides the public functions for the API for the PSoC 6 Flash Driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_flash.h" + + +/******************************************************************************* +* Function Name: Cy_Flash_WriteRow +****************************************************************************//** +* +* This function writes an array of data to a single row of flash. Reports success or +* or a reason for failure. Does not return until the Write operation is complete. +* Returns immediately and reports a CY_FLASH_DRV_IPC_BUSY error in the case when another +* process is writing to flash. User firmware should not enter the hibernate +* mode until flash Write is complete. The Flash operation is allowed in Sleep and +* Deep-sleep modes. During the Flash operation, the device should not be reset, +* including the XRES pin, a software reset, and watchdog reset sources. Also, +* low-voltage detect circuits should be configured to generate an interrupt instead +* of a reset. Otherwise, portions of flash may undergo unexpected changes. +* +* \param rowAddr Address of the flash row number. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* Address must match row start address. +* +* \param data The pointer to the data which has to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \param contextPtr The pointer to the Flash driver context defined by the user. +* The flash driver context contains configuration data for flash operation. +* +* \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data, cy_stc_flash_context_t* contextPtr) +{ + uint32_t result; + cy_en_flashdrv_status_t retVal = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + +#if (CY_CPU_CORTEX_M0P) + uint32_t interruptState; + uint32_t regVal; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regVal = Cy_IPC_DRV_GetIntrMask(IPC_INTR_STRUCT0); + Cy_IPC_DRV_SetIntrMask(IPC_INTR_STRUCT0, ((regVal >> IPC_INTR_STRUCT_INTR_NOTIFY_Pos) | 0x07u), \ + ((regVal & IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk) | 0x07u)); + + result = Cy_Flash_StartWrite (rowAddr, data, contextPtr); + + /* Check whether the Flash operation was successfully initiated */ + if (result == CY_FLASH_DRV_OPERATION_STARTED) + { + /* Polls whether IPC is released and the Flash operation is performed */ + do + { + result = Cy_Flash_IsWriteComplete(contextPtr); + } + while (result == CY_FLASH_DRV_OPCODE_BUSY); + } + + Cy_SysLib_ExitCriticalSection(interruptState); +#else + if (Cy_Flash_PrepeareContext(rowAddr, data, contextPtr) != CY_FLASH_DRV_INVALID_INPUT_PARAMETERS) + { + Cy_Flash_Proxy Cy_Flash_Cm4Proxy; + Cy_Flash_Cm4Proxy = (Cy_Flash_Proxy)CY_FLASH_CM4_FLASH_PROXY_ADDR; + result = Cy_Flash_Cm4Proxy(contextPtr); + } + else + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } +#endif /* (CY_CPU_CORTEX_M0P) */ + + /* Invalidates the flash cache and buffer */ + FLASHC->FLASH_CMD = FLASHC_FLASH_CMD_INV_Msk; + + retVal = Cy_Flash_ProcessOpcode(result); + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_StartWrite +****************************************************************************//** +* +* Starts writing an array of data to a single row of flash. Returns immediately +* and reports a successful start or reason for failure. Returns immediately and +* reports a CY_FLASH_IPC_BUSY error in the case when another process is writing +* to flash. User firmware should not enter the hibernate mode until flash Write +* is complete. The Flash operation is allowed in Sleep and Deep-sleep modes. +* During the flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage +* detect circuits should be configured to generate an interrupt instead of a reset. +* Otherwise, portions of flash may undergo unexpected changes. +* +* \param rowAddr Address of the flash row number. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* Address must row start address. +* +* \param data The pointer to the data to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \param contextPtr The pointer to the Flash driver context defined by the user. +* The Flash driver context contains configuration data for the Flash operation. +* +* \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data, cy_stc_flash_context_t *contextPtr) +{ + cy_en_flashdrv_status_t result; + + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + /* Checks whether the input parameters are valid */ + if (Cy_Flash_PrepeareContext(rowAddr, data, contextPtr) != CY_FLASH_DRV_INVALID_INPUT_PARAMETERS) + { + /* Tries to acquire the IPC structure and pass the arguments to SROM API */ + if (Cy_IPC_DRV_SendMsgPtr(CY_FLASH_IPC_STRUCT, CY_FLASH_IPC_NOTIFY_STRUCT0, (void*)contextPtr) == CY_IPC_DRV_SUCCESS) + { + /* The Flash operation is successfully initiated */ + result = CY_FLASH_DRV_OPERATION_STARTED; + } + else + { + /* The IPC structure is already locked by another process */ + result = CY_FLASH_DRV_IPC_BUSY; + } + } + else + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_IsWriteComplete +****************************************************************************//** +* +* Reports a successful Write, reason of failure or busy status (CY_FLASH_DRV_OPCODE_BUSY). +* +* \param contextPtr The pointer to the Flash driver context defined by the user. +* +* \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_IsWriteComplete(const cy_stc_flash_context_t* contextPtr) +{ + cy_en_flashdrv_status_t retVal = CY_FLASH_DRV_OPCODE_BUSY; + + /* Checks if the IPC structure is not locked */ + if (Cy_IPC_DRV_GetLockStatus(CY_FLASH_IPC_STRUCT) == CY_IPC_DRV_RELEASED) + { + /* The result of SROM API calling is returned to the driver context */ + retVal = Cy_Flash_ProcessOpcode(contextPtr->opcode); + } + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_RowChecksum +****************************************************************************//** +* +* Returns a checksum value of the specified flash row. +* +* \param rowNum The Cheksum is calculated to the flash row. +* +* \param contextPtr The pointer to the Flash driver context defined by the user. +* +* \param cheksumPtr The pointer to the address whire cheksum is to be stored +* +* \return Returns the status of the Flash operation. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_RowChecksum (uint32_t rowNum, cy_stc_flash_context_t* contextPtr, uint32_t* cheksumPtr) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + uint32_t resTmp; + + /* Checks whether the input parameters are valid */ + if ((rowNum >= CY_FLASH_NUMBER_ROWS) || (contextPtr == NULL)) + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + else + { + /* Prepares arguments to be passed to SROM API */ + contextPtr->opcode = CY_FLASH_OPCODE_CHECKSUM | (rowNum << CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT); + + /* Tries to acquire the IPC structure and pass the arguments to SROM API */ + if (Cy_IPC_DRV_SendMsgPtr(CY_FLASH_IPC_STRUCT, CY_FLASH_IPC_NOTIFY_STRUCT0, (void*)contextPtr) == CY_IPC_DRV_SUCCESS) + { + /* Polls whether IPC is released and the Flash operation is performed */ + while (Cy_IPC_DRV_GetLockStatus(CY_FLASH_IPC_STRUCT) != CY_IPC_DRV_RELEASED) + { + /* Wait till IPC is released */ + } + + resTmp = contextPtr->opcode; + + if((resTmp >> CY_FLASH_ERROR_SHIFT) == CY_FLASH_ERROR_NO_ERROR) + { + result = CY_FLASH_DRV_SUCCESS; + *cheksumPtr = contextPtr->opcode & CY_FLASH_RESULT_MASK; + } + else + { + result = Cy_Flash_ProcessOpcode(result); + } + } + else + { + /* The IPC structure is already locked by another process */ + result = CY_FLASH_DRV_IPC_BUSY; + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_CalculateHash +****************************************************************************//** +* +* Returns a hash value of the specified region of flash. +* +* \param data Start the data address. +* +* \param numberOfBytes The hash value is calculated for the number of bytes after the +* start data address (0 – 1 byte,1- 2 bytes etc). +* +* \param contextPtr The pointer to the Flash driver context defined by the user. +* +* \param hashPtr The pointer to the address whire hash is to be stored +* +* \return Returns the status of the Flash operation. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_CalculateHash (const uint32_t* data, uint32 numberOfBytes, cy_stc_flash_context_t* contextPtr, uint32_t* hashPtr) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + uint32_t resTmp; + + /* Checks whether the input parameters are valid */ + if ((data == NULL) || (contextPtr == NULL)) + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + else + { + /* Prepares arguments to be passed to SROM API */ + contextPtr->opcode = CY_FLASH_OPCODE_HASH; + contextPtr->arg1 = (uint32_t)data; + contextPtr->arg2 = numberOfBytes; + + /* Tries to acquire the IPC structure and pass the arguments to SROM API */ + if (Cy_IPC_DRV_SendMsgPtr(CY_FLASH_IPC_STRUCT, CY_FLASH_IPC_NOTIFY_STRUCT0, (void*)contextPtr) == CY_IPC_DRV_SUCCESS) + { + /* Polls whether IPC is released and the Flash operation is performed */ + while (Cy_IPC_DRV_GetLockStatus(CY_FLASH_IPC_STRUCT) != CY_IPC_DRV_RELEASED) + { + /* Wait till IPC is released */ + } + + resTmp = contextPtr->opcode; + + if((resTmp >> CY_FLASH_ERROR_SHIFT) == CY_FLASH_ERROR_NO_ERROR) + { + result = CY_FLASH_DRV_SUCCESS; + *hashPtr = contextPtr->opcode & CY_FLASH_RESULT_MASK; + } + else + { + result = Cy_Flash_ProcessOpcode(result); + } + } + else + { + /* The IPC structure is already locked by another process */ + result = CY_FLASH_DRV_IPC_BUSY; + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_BoundsCheck +****************************************************************************//** +* +* Returns 1 if Flash addres is out of boundary, otherwise returns 0. +* +* \param flashAddr Address to be checked +* +* \return 1 - out of bound, 0 - in flash bounds +* +*******************************************************************************/ +uint32_t Cy_Flash_BoundsCheck(uint32_t flashAddr) +{ + uint32_t result = 1u; + + if ((flashAddr < CY_FLASH_BASE) || (flashAddr >= (CY_FLASH_BASE + CY_FLASH_SIZE))) + { + if ((flashAddr < CY_WFLASH_BASE) || (flashAddr >= (CY_WFLASH_BASE + CY_WFLASH_SIZE))) + { + if ((flashAddr < SFLASH_BASE) || (flashAddr >= (SFLASH_BASE + SFLASH_SECTION_SIZE))) + { + result = 0u; + } + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_PrepeareContext +****************************************************************************//** +* +* Returns 1 if parameters are correct and initialises contextPtr, otherwise returns +* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS. +* +* \param rowAddr Address of the flash row number. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* Address must match row start address. +* +* \param data The pointer to the data which has to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \param contextPtr The pointer to the Flash driver context defined by the user. +* The flash driver context contains configuration data for flash operation. +* +* \return 1 - Context ready, CY_FLASH_DRV_INVALID_INPUT_PARAMETERS - Wrong arguments +* +*******************************************************************************/ +uint32_t Cy_Flash_PrepeareContext(uint32_t rowAddr, const uint32_t* data, cy_stc_flash_context_t *contextPtr) +{ + uint32_t result; + + if ((Cy_Flash_BoundsCheck(rowAddr) == 0) || (data == NULL) || (contextPtr == NULL)) + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + else + { + if (rowAddr%CY_FLASH_SIZEOF_ROW != 0) + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + else + { + /* Prepares arguments to be passed to SROM API */ + contextPtr->opcode = CY_FLASH_OPCODE_WRITE_ROW; + contextPtr->arg1 = CY_FLASH_CONFIG_DATASIZE; + contextPtr->arg2 = rowAddr; + contextPtr->arg3 = (uint32_t)data; + + result = 1u; + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_ProcessOpcode +****************************************************************************//** +* +* Converts System Call returns to the Flash driver return defines. +* +* \param opcode The value retuned by the System Call. +* +* \return Flash driver return. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode) +{ + cy_en_flashdrv_status_t retVal; + + switch (opcode) + { + case 0UL: + { + retVal = CY_FLASH_DRV_SUCCESS; + break; + } + case CY_FLASH_ROMCODE_SUCCESS: + { + retVal = CY_FLASH_DRV_SUCCESS; + break; + } + case CY_FLASH_ROMCODE_INVALID_PROTECTION: + { + retVal = CY_FLASH_DRV_INV_PROT; + break; + } + case CY_FLASH_ROMCODE_INVALID_FM_PL: + { + retVal = CY_FLASH_DRV_INVALID_FM_PL; + break; + } + case CY_FLASH_ROMCODE_INVALID_FLASH_ADDR: + { + retVal = CY_FLASH_DRV_INVALID_FLASH_ADDR; + break; + } + case CY_FLASH_ROMCODE_ROW_PROTECTED: + { + retVal = CY_FLASH_DRV_ROW_PROTECTED; + break; + } + case CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR: + { + retVal = CY_FLASH_DRV_PROGRESS_NO_ERROR; + break; + } + case CY_FLASH_DRV_INVALID_INPUT_PARAMETERS: + { + retVal = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + break; + } + default: + { + retVal = CY_FLASH_DRV_ERR_UNC; + } + } + + return (retVal); +} + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.h new file mode 100644 index 0000000000..c9cb738718 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.h @@ -0,0 +1,283 @@ +/***************************************************************************//** +* \file cy_flash.h +* \version 1.0 +* +* Provides the API declarations of the Flash driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_FLASH_H) +#define CY_FLASH_H + +/** +* \defgroup group_flash Flash System Routine (Flash) +* \{ +* Internal flash memory programming +* +* Flash memory in PSoC devices provides non-volatile storage for user firmware, +* user configuration data, and bulk data storage. +* +* Flash operations are implemented as system calls. System calls are executed +* out of SROM in the privileged mode of operation. Users have no access to read +* or modify the SROM code. The driver API requests the system call by acquiring +* the Inter-processor communication (IPC) and writing the SROM function opcode +* and parameters to its input registers. As a result, an NMI interrupt is invoked +* and the requested SROM API is executed. The operation status is returned to the +* driver context and a release interrupt is triggered. +* +* Writing to flash can take up to 20 milliseconds. During this time, +* the device should not be reset (including XRES pin, software reset, and +* watchdog) or unexpected changes may be made to portions of the flash. +* Also, the low-voltage detect circuits should be configured to generate an +* interrupt instead of a reset. +* +* The Read while Write violation occurs when the flash Read operation is initiated +* in the same flash sector where the flash Write operation is performing. The +* violation leads to the exception generation. To avoid the Read while Write +* violation, the user has to carefully split the Read and Write operation from the +* same flash sector considering both cores in the multi-processor device. +* Use different flash sectors for code and data storage. The flash is divided +* into four equal sectors. +* +* \section group_flash_configuration Configuration Considerations +* +* There are no specific configuration parameters for the flash operations +* outside the driver API input parameters. +* +* \section group_flash_more_information More Information +* +* See the technical reference manual (TRM) for more information about the Flash architecture. +* +* \section group_flash_MISRA MISRA-C Compliance +* +* The Flash driver has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
19.7AA function shall be used in preference to a function-like macroMacro is used because of performance reasons
+* +* \section group_flash_changelog Changelog +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_flash_macro Macro +* \defgroup group_flash_functions Functions +* \defgroup group_flash_data_structure Data Structures +*/ + +#include +#include +#include + +/*************************************** +* Macro definitions +***************************************/ +/** +* \addtogroup group_flash_macro +* \{ +*/ + +/** Driver major version */ +#define CY_FLASH_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_FLASH_DRV_VERSION_MINOR 0 + +/** +* \defgroup group_flash_returns Flash return values +* \{ +* Specifies return values meaning +*/ +#define CY_FLASH_ID (CY_PDL_DRV_ID(0x14u)) /**< FLASH PDL ID */ + +#define CY_FLASH_ID_INFO (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_INFO ) /**< Return prefix for FLASH driver function status codes */ +#define CY_FLASH_ID_WARNING (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_WARNING) /**< Return prefix for FLASH driver function warning return values */ +#define CY_FLASH_ID_ERROR (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_ERROR) /**< Return prefix for FLASH driver function error return values */ + +/** This enum has the return values of the Flash driver */ +typedef enum +{ + CY_FLASH_DRV_SUCCESS = 0x00ul, /**< Success */ + CY_FLASH_DRV_INV_PROT = ( CY_FLASH_ID_ERROR + 0ul), /**< Invalid device protection state */ + CY_FLASH_DRV_INVALID_FM_PL = ( CY_FLASH_ID_ERROR + 1ul), /**< Invalid flash page latch address */ + CY_FLASH_DRV_INVALID_FLASH_ADDR = ( CY_FLASH_ID_ERROR + 2ul), /**< Invalid flash address */ + CY_FLASH_DRV_ROW_PROTECTED = ( CY_FLASH_ID_ERROR + 3ul), /**< Row is write protected */ + CY_FLASH_DRV_IPC_BUSY = ( CY_FLASH_ID_ERROR + 5ul), /**< IPC structure is already locked by another process */ + CY_FLASH_DRV_INVALID_INPUT_PARAMETERS = ( CY_FLASH_ID_ERROR + 6ul), /**< Input parameters passed to Flash API are not valid */ + CY_FLASH_DRV_ERR_UNC = ( CY_FLASH_ID_ERROR + 0xFul),/**< Unknown error */ + CY_FLASH_DRV_PROGRESS_NO_ERROR = ( CY_FLASH_ID_INFO + 0ul), /**< Command in progress; no error */ + CY_FLASH_DRV_OPERATION_STARTED = ( CY_FLASH_ID_INFO + 1ul), /**< Flash operation is successfully initiated */ + CY_FLASH_DRV_OPCODE_BUSY = ( CY_FLASH_ID_INFO + 2ul), /**< Flash is under operation */ +} cy_en_flashdrv_status_t; + +/** \} group_flash_returns */ + +/** \cond INTERNAL */ +/** Command completed with no errors */ +#define CY_FLASH_ROMCODE_SUCCESS (0xA0000000UL) +/** Invalid device protection state */ +#define CY_FLASH_ROMCODE_INVALID_PROTECTION (0xF0000001UL) +/** Invalid flash page latch address */ +#define CY_FLASH_ROMCODE_INVALID_FM_PL (0xF0000003UL) +/** Invalid flash address */ +#define CY_FLASH_ROMCODE_INVALID_FLASH_ADDR (0xF0000004UL) +/** Row is write protected */ +#define CY_FLASH_ROMCODE_ROW_PROTECTED (0xF0000005UL) +/** Command in progress; no error */ +#define CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR (0xA0000009UL) +/** Flash operation is successfully initiated */ +#define CY_FLASH_IS_OPERATION_STARTED (0x00000010UL) +/** Flash is under operation */ +#define CY_FLASH_IS_BUSY (0x00000040UL) +/** IPC structure is already locked by another process */ +#define CY_FLASH_IS_IPC_BUSY (0x00000080UL) +/** Input parameters passed to Flash API are not valid */ +#define CY_FLASH_IS_INVALID_INPUT_PARAMETERS (0x00000100UL) + +/** Result mask */ +#define CY_FLASH_RESULT_MASK (0xFFFFFFFUL) +/** Error shift */ +#define CY_FLASH_ERROR_SHIFT (28UL) +/** No error */ +#define CY_FLASH_ERROR_NO_ERROR (0xAUL) +/** \endcond */ + + +/** +* \addtogroup group_flash_config_macro Flash configuration +* \{ +* Specifies the parameter values passed to SROM API +*/ + +/** SROM API opcode for flash write operation */ +#if (CY_CPU_CORTEX_M0P) && (!defined(CY8C622PSVP) && !defined(CY8C622PSVP_DUAL)) + #define CY_FLASH_OPCODE_WRITE_ROW (((0x05UL) << 24u) | ((0x01UL) << 8UL)) +#else + #define CY_FLASH_OPCODE_WRITE_ROW ((0x05UL) << 24u) +#endif + +/** SROM API opcode for flash checksum operation */ +#define CY_FLASH_OPCODE_CHECKSUM ((0x0BUL) << 24u) +/** SROM API opcode for flash hash operation */ +#define CY_FLASH_OPCODE_HASH ((0x0DUL) << 24u) +/** SROM API flash row shift for flash checksum operation */ +#define CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT (8u) +/** SROM API flash data size parameter for flash write operation */ +#define CY_FLASH_CONFIG_DATASIZE (0x06UL) +/** SROM API flash verification option for flash write operation */ +#define CY_FLASH_CONFIG_VERIFICATION_EN ((0x01UL) << 16u) + +/** \} group_flash_config_macro */ + + +/** +* \addtogroup group_flash_general_macro Flash general parameters +* \{ +* Provides general information about flash and IPC +*/ + +/** Flash row size */ +#define CY_FLASH_SIZEOF_ROW (CPUSS_FLASHC_PA_SIZE * 4u) +/** Number of flash rows */ +#define CY_FLASH_NUMBER_ROWS (CY_FLASH_SIZE / CY_FLASH_SIZEOF_ROW) +/** Long words flash row size */ +#define CY_FLASH_SIZEOF_ROW_LONG_UNITS (CY_FLASH_SIZEOF_ROW / sizeof(uint32_t)) +/** Calculates the flash address for a given row of flash */ +#define CY_CALCULATE_FLASH_ADDRESS(rowNum) (CY_FLASH_BASE + ((rowNum) * CY_FLASH_SIZEOF_ROW)) +/** IPC channel to be used */ +#define CY_FLASH_IPC_STRUCT ((IPC_STRUCT_Type*) &IPC->STRUCT[CY_IPC_CHAN_SYSCALL]) +/** IPC notify bit for IPC_STRUCT0 (dedicated to flash operation) */ +#define CY_FLASH_IPC_NOTIFY_STRUCT0 (0x1UL) +/** \cond INTERNAL */ +#define CY_FLASH_CM4_FLASH_PROXY_ADDR (0x16001101UL) +/** \endcond */ + +/** \} group_flash_general_macro */ + +/** \} group_flash_macro */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Data Structure definitions +***************************************/ + +/** +* \addtogroup group_flash_data_structure +* \{ +*/ + +/** Flash driver context */ +typedef struct +{ + uint32_t opcode; /**< Specifies the code of flash operation */ + uint32_t arg1; /**< Specifies the configuration of flash operation */ + uint32_t arg2; /**< Specifies the configuration of flash operation */ + uint32_t arg3; /**< Specifies the configuration of flash operation */ +}cy_stc_flash_context_t; + +/** \} group_flash_data_structure */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_flash_functions +* \{ +*/ +cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data, cy_stc_flash_context_t* contextPtr); +cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data, cy_stc_flash_context_t* contextPtr); +cy_en_flashdrv_status_t Cy_Flash_IsWriteComplete(const cy_stc_flash_context_t* contextPtr); +cy_en_flashdrv_status_t Cy_Flash_RowChecksum (uint32_t rowNum, cy_stc_flash_context_t* contextPtr, uint32_t* cheksumPtr); +cy_en_flashdrv_status_t Cy_Flash_CalculateHash (const uint32_t* data, uint32 numberOfBytes, cy_stc_flash_context_t* contextPtr, uint32_t* hashPtr); +/** \cond INTERNAL */ +uint32_t Cy_Flash_BoundsCheck(uint32_t flashAddr); +uint32_t Cy_Flash_PrepeareContext(uint32_t rowAddr, const uint32_t* data, cy_stc_flash_context_t *contextPtr); +cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode); + +typedef cy_en_flashdrv_status_t (*Cy_Flash_Proxy)(cy_stc_flash_context_t *contextPtr); +/** \endcond */ + +/** \} group_flash_functions */ + +#if defined(__cplusplus) +} +#endif + + +#endif /* #if !defined(CY_FLASH_H) */ +/** \endcond */ + + +/** \} group_flash */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.c new file mode 100644 index 0000000000..43c939f4da --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.c @@ -0,0 +1,137 @@ +/***************************************************************************//** +* \file cy_gpio.c +* \version 1.0 +* +* \brief +* Provides an API implementation of the GPIO driver +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_gpio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_GPIO_Pin_Init +****************************************************************************//** +* +* \brief Initialize all pin configuration setting for the pin. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param config +* Pointer to the pin config structure base address +* +* \return +* void +* +* \note +* This function modifies port registers in read-modify-write operations. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config) +{ + cy_en_gpio_status_t status = CY_GPIO_SUCCESS; + uint32_t maskCfgOut; + uint32_t tempReg; + + if((NULL != base) && (NULL != config)) + { + Cy_GPIO_Write(base, pinNum, config->outVal); + Cy_GPIO_SetDrivemode(base, pinNum, config->driveMode); + Cy_GPIO_SetHSIOM(base, pinNum, config->hsiom); + + Cy_GPIO_SetInterruptEdge(base, pinNum, config->intEdge); + Cy_GPIO_SetInterruptMask(base, pinNum, config->intMask); + Cy_GPIO_SetVtrip(base, pinNum, config->vtrip); + + /* Slew rate and Driver strength */ + maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum) | (CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << (pinNum + CY_GPIO_CFG_OUT_DRIVE_OFFSET)); + tempReg = base->CFG_OUT & ~(maskCfgOut); + base->CFG_OUT = tempReg | ((config->slewRate & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum) + | ((config->driveSel & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << (pinNum + CY_GPIO_CFG_OUT_DRIVE_OFFSET)); + + /* SIO specific configuration */ + tempReg = base->CFG_SIO & ~(CY_GPIO_SIO_PIN_MASK); + base->CFG_SIO = tempReg | (((config->vregEn & CY_GPIO_VREG_EN_MASK) + | ((config->ibufMode & CY_GPIO_IBUF_MASK) << CY_GPIO_IBUF_SHIFT) + | ((config->vtripSel & CY_GPIO_VTRIP_SEL_MASK) << CY_GPIO_VTRIP_SEL_SHIFT) + | ((config->vrefSel & CY_GPIO_VREF_SEL_MASK) << CY_GPIO_VREF_SEL_SHIFT) + | ((config->vohSel & CY_GPIO_VOH_SEL_MASK) << CY_GPIO_VOH_SEL_SHIFT)) + << ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET)); + } + else + { + status = CY_GPIO_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Port_Init +****************************************************************************//** +* +* \brief Initialize a complete port of pins from a single init structure. +* +* \param base +* Pointer to the pin's port register base address +* +* \param config +* Pointer to the pin config structure base address +* +* \return +* void +* +*******************************************************************************/ +cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config) +{ + cy_en_gpio_status_t status = CY_GPIO_SUCCESS; + uint32_t portNum; + HSIOM_PRT_Type* baseHSIOM; + + if((NULL != base) && (NULL != config)) + { + portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE; + baseHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); + + base->OUT = config->out; + base->CFG = config->cfg; + base->CFG_IN = config->cfgIn; + base->CFG_OUT = config->cfgOut; + base->INTR_CFG = config->intrCfg; + base->INTR_MASK = config->intrMask; + base->CFG_SIO = config->cfgSIO; + baseHSIOM->PORT_SEL0 = config->sel0Active; + baseHSIOM->PORT_SEL1 = config->sel1Active; + } + else + { + status = CY_GPIO_BAD_PARAM; + } + + return(status); +} + + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.h new file mode 100644 index 0000000000..f25c54beeb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.h @@ -0,0 +1,1719 @@ +/***************************************************************************//** +* \file cy_gpio.h +* \version 1.0 +* +* \brief +* Provides an API declaration of the GPIO driver +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_gpio General Purpose Input Output (GPIO) +* \{ +* The GPIO driver provides an API to configure and access device Input/Output pins. +* IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and +* their variants. +* +* Initialization can be performed either at the port level or by configuring the +* individual pins. For efficient use of code space, port +* configuration should be used in the field. Refer to the product device header files +* for the list of supported ports and pins. +* +* - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit +* (provide specific values) or \ref Cy_GPIO_Pin_Init (provide a filled +* cy_stc_gpio_pin_config_t structure). +* - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled +* cy_stc_gpio_prt_config_t structure. The values in the structure are +* bitfields representing the desired value for each pin in the port. +* - Pin configuration and management is based on the port address and pin number. +* \ref Cy_GPIO_PortToAddr function can optionally be used to calculate the port +* address from the port number at run-time. +* +* Once the pin/port initialization is complete, each pin can be accessed by +* specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API +* functions. +* +* \section group_gpio_configuration Configuration Considerations +* +* 1. Pin muxing is controlled through the High-Speed IO Matrix (HSIOM) selection. +* This allows the pin to connect to signal sources/sinks throughout the device, +* as defined by the pin HSIOM selection options (en_hsiom_sel_t). +* 2. All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW +* control digital pin only) at Power-On-Reset(POR). +* 3. Some API functions perform read-modify-write operations on shared port +* registers. These functions are not thread safe and care must be taken when +* called by the application. +* +* \section group_gpio_more_information More Information +* +* Refer to the technical reference manual (TRM) and the device datasheet. +* +* \section group_gpio_MISRA MISRA-C Compliance] +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA ruleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
14.1RStatic Function '' is not used within this translation unit.
16.7RThe object addressed by the pointer parameter 'base' is not modified +* and so the pointer could be of type 'pointer to const'.
+* +* \section group_gpio_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_gpio_macro Macro +* \defgroup group_gpio_functions Functions +* \{ +* \defgroup group_gpio_functions_init Initialization Functions +* \defgroup group_gpio_functions_gpio GPIO Functions +* \defgroup group_gpio_functions_sio SIO Functions +* \defgroup group_gpio_functions_interrupt Port Interrupt Functions +* \} +* \defgroup group_gpio_data_structures Data structures +* \defgroup group_gpio_enums Enumerated types +*/ + +#if !defined(CY_GPIO_H) +#define CY_GPIO_H + +#include +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_gpio_macro +* \{ +*/ + +/** Driver major version */ +#define CY_GPIO_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_GPIO_DRV_VERSION_MINOR 0 + +/** GPIO driver ID */ +#define CY_GPIO_ID CY_PDL_DRV_ID(0x16u) + +/** \} group_gpio_macro */ + + +/*************************************** +* Enumerations +***************************************/ +/** +* \addtogroup group_gpio_enums +* \{ +*/ + +/** +* GPIO Driver error codes +*/ +typedef enum +{ + CY_GPIO_SUCCESS = 0x00u, /**< Returned successful */ + CY_GPIO_BAD_PARAM = CY_GPIO_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */ +} cy_en_gpio_status_t; + +/** \} group_gpio_enums */ + + +/*************************************** +* Configuration Structures +***************************************/ + +/** +* \addtogroup group_gpio_data_structures +* \{ +*/ + +/** This structure is used to initialize a port of GPIO pins */ +typedef struct { + uint32_t out; /**< Initial output data for the IO pins in the port */ + uint32_t intrMask; /**< Interrupt enable mask for the port interrupt */ + uint32_t intrCfg; /**< Port pin interrupt edge detection configuration */ + uint32_t cfg; /**< Port pin drive modes and input buffer enable configuration */ + uint32_t cfgIn; /**< Port pin input buffer configuration */ + uint32_t cfgOut; /**< Port pin output buffer configuration */ + uint32_t cfgSIO; /**< Port SIO pins configuration */ + uint32_t sel0Active; /**< HSIOM selection for port pins 0,1,2,3 */ + uint32_t sel1Active; /**< HSIOM selection for port pins 4,5,6,7 */ +} cy_stc_gpio_prt_config_t; + +/** This structure is used to initialize a single GPIO pin */ +typedef struct { + uint32_t outVal; /**< Pin output state */ + uint32_t driveMode; /**< Drive mode */ + en_hsiom_sel_t hsiom; /**< HSIOM selection */ + uint32_t intEdge; /**< Interrupt Edge type */ + uint32_t intMask; /**< Interrupt enable mask */ + uint32_t vtrip; /**< Input buffer voltage trip type */ + uint32_t slewRate; /**< Output buffer slew rate */ + uint32_t driveSel; /**< Drive strength */ + uint32_t vregEn; /**< SIO pair output buffer mode */ + uint32_t ibufMode; /**< SIO pair input buffer mode */ + uint32_t vtripSel; /**< SIO pair input buffer trip point */ + uint32_t vrefSel; /**< SIO pair reference voltage for input buffer trip point */ + uint32_t vohSel; /**< SIO pair regulated voltage output level */ +} cy_stc_gpio_pin_config_t; + +/** \} group_gpio_data_structures */ + +/*************************************** +* Constants +***************************************/ + +/** \cond INTERNAL */ + +/* General Constants */ +#define CY_GPIO_PRT_HALF (4UL) /**< Half-way point of a GPIO port */ +#define CY_GPIO_PRT_DEINIT (0UL) /**< De-init value for port registers */ + +/* GPIO Masks */ +#define CY_GPIO_HSIOM_MASK (0x1FUL) /**< HSIOM selection mask */ +#define CY_GPIO_OUT_MASK (0x01UL) /**< Single pin mask for OUT register */ +#define CY_GPIO_IN_MASK (0x01UL) /**< Single pin mask for IN register */ +#define CY_GPIO_CFG_DM_MASK (0x0FUL) /**< Single pin mask for drive mode in CFG register */ +#define CY_GPIO_CFG_IN_VTRIP_SEL_MASK (0x01UL) /**< Single pin mask for VTRIP selection in CFG IN register */ +#define CY_GPIO_CFG_OUT_SLOW_MASK (0x01UL) /**< Single pin mask for slew rate in CFG OUT register */ +#define CY_GPIO_CFG_OUT_DRIVE_SEL_MASK (0x03UL) /**< Single pin mask for drive strength in CFG OUT register */ +#define CY_GPIO_INTR_STATUS_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */ +#define CY_GPIO_INTR_EN_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */ +#define CY_GPIO_INTR_MASKED_MASK (0x01UL) /**< Single pin mask for masked interrupt status in INTR_MASKED register */ +#define CY_GPIO_INTR_SET_MASK (0x01UL) /**< Single pin mask for setting the interrupt in INTR_MASK register */ +#define CY_GPIO_INTR_EDGE_MASK (0x03UL) /**< Single pin mask for interrupt edge type in INTR_EDGE register */ +#define CY_GPIO_INTR_FLT_EDGE_MASK (0x07UL) /**< Single pin mask for setting filtered interrupt */ + +/* SIO Masks */ +#define CY_GPIO_VREG_EN_MASK (0x01UL) /**< Single SIO pin mask for voltage regulation enable */ +#define CY_GPIO_IBUF_MASK (0x01UL) /**< Single SIO pin mask for input buffer */ +#define CY_GPIO_IBUF_SHIFT (0x01UL) /**< Single SIO pin shift for input buffer */ +#define CY_GPIO_VTRIP_SEL_MASK (0x01UL) /**< Single SIO pin mask for the input buffer trip point */ +#define CY_GPIO_VTRIP_SEL_SHIFT (0x02UL) /**< Single SIO pin shift for the input buffer trip point */ +#define CY_GPIO_VREF_SEL_MASK (0x03UL) /**< Single SIO pin mask for voltage reference */ +#define CY_GPIO_VREF_SEL_SHIFT (0x03UL) /**< Single SIO pin shift for voltage reference */ +#define CY_GPIO_VOH_SEL_MASK (0x07UL) /**< Single SIO pin mask for VOH */ +#define CY_GPIO_VOH_SEL_SHIFT (0x05UL) /**< Single SIO pin shift for VOH */ + +/* Special mask for SIO pin pair setting */ +#define CY_GPIO_SIO_ODD_PIN_MASK (0x00FEUL) /**< SIO pin pair selection mask */ +#define CY_GPIO_SIO_PIN_MASK (0x00FFUL) /**< SIO pin pair mask */ + +/* Offsets */ +#define CY_GPIO_HSIOM_OFFSET (3UL) /**< Offset for HSIOM */ +#define CY_GPIO_DRIVE_MODE_OFFSET (2UL) /**< Offset for Drive mode */ +#define CY_GPIO_INBUF_OFFSET (3UL) /**< Offset for input buffer */ +#define CY_GPIO_CFG_OUT_DRIVE_OFFSET (16UL) /**< Offset for drive strength */ +#define CY_GPIO_INTR_CFG_OFFSET (1UL) /**< Offset for interrupt config */ +#define CY_GPIO_INTR_FILT_OFFSET (18UL) /**< Offset for filtered interrupt config */ +#define CY_GPIO_CFG_SIO_OFFSET (2UL) /**< Offset for SIO config */ + +#define CY_GPIO_ZERO (0UL) /**< Constant zero */ + +/** \endcond */ + + +/*************************************** +* Function Constants +***************************************/ + +/** +* \addtogroup group_gpio_macro +* \{ +*/ + +/** +* \defgroup group_gpio_driveModes Pin drive mode +* \{ +* Constants to be used for setting the drive mode of the pin. +*/ +#define CY_GPIO_DM_ANALOG (0x00UL) /**< \brief Analog High-Z. Input buffer off */ +#define CY_GPIO_DM_PULLUP_IN_OFF (0x02UL) /**< \brief Resistive Pull-Up. Input buffer off */ +#define CY_GPIO_DM_PULLDOWN_IN_OFF (0x03UL) /**< \brief Resistive Pull-Down. Input buffer off */ +#define CY_GPIO_DM_OD_DRIVESLOW_IN_OFF (0x04UL) /**< \brief Open Drain, Drives Low. Input buffer off */ +#define CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF (0x05UL) /**< \brief Open Drain, Drives High. Input buffer off */ +#define CY_GPIO_DM_STRONG_IN_OFF (0x06UL) /**< \brief Strong Drive. Input buffer off */ +#define CY_GPIO_DM_PULLUP_DOWN_IN_OFF (0x07UL) /**< \brief Resistive Pull-Up/Down. Input buffer off */ +#define CY_GPIO_DM_HIGHZ (0x08UL) /**< \brief Digital High-Z. Input buffer on */ +#define CY_GPIO_DM_PULLUP (0x0AUL) /**< \brief Resistive Pull-Up. Input buffer on */ +#define CY_GPIO_DM_PULLDOWN (0x0BUL) /**< \brief Resistive Pull-Down. Input buffer on */ +#define CY_GPIO_DM_OD_DRIVESLOW (0x0CUL) /**< \brief Open Drain, Drives Low. Input buffer on */ +#define CY_GPIO_DM_OD_DRIVESHIGH (0x0DUL) /**< \brief Open Drain, Drives High. Input buffer on */ +#define CY_GPIO_DM_STRONG (0x0EUL) /**< \brief Strong Drive. Input buffer on */ +#define CY_GPIO_DM_PULLUP_DOWN (0x0FUL) /**< \brief Resistive Pull-Up/Down. Input buffer on */ +/** \} */ + +/** +* \defgroup group_gpio_vtrip Voltage trip mode +* \{ +* Constants to be used for setting the voltage trip type on the pin. +*/ +#define CY_GPIO_VTRIP_CMOS (0x00UL) /**< \brief Input buffer compatible with CMOS and I2C interfaces */ +#define CY_GPIO_VTRIP_TTL (0x01UL) /**< \brief Input buffer compatible with TTL and MediaLB interfaces */ +/** \} */ + +/** +* \defgroup group_gpio_slewRate Slew Rate Mode +* \{ +* Constants to be used for setting the slew rate of the pin. +*/ +#define CY_GPIO_SLEW_FAST (0x00UL) /**< \brief Fast slew rate */ +#define CY_GPIO_SLEW_SLOW (0x01UL) /**< \brief Slow slew rate */ +/** \} */ + +/** +* \defgroup group_gpio_driveStrength Pin drive strength +* \{ +* Constants to be used for setting the drive strength of the pin. +*/ +#define CY_GPIO_DRIVE_FULL (0x00UL) /**< \brief Full drive strength: Max drive current */ +#define CY_GPIO_DRIVE_1_2 (0x01UL) /**< \brief 1/2 drive strength: 1/2 drive current */ +#define CY_GPIO_DRIVE_1_4 (0x02UL) /**< \brief 1/4 drive strength: 1/4 drive current */ +#define CY_GPIO_DRIVE_1_8 (0x03UL) /**< \brief 1/8 drive strength: 1/8 drive current */ +/** \} */ + +/** +* \defgroup group_gpio_interruptTrigger Interrupt trigger type +* \{ +* Constants to be used for setting the interrupt trigger type on the pin. +*/ +#define CY_GPIO_INTR_DISABLE (0x00UL) /**< \brief Disable the pin interrupt generation */ +#define CY_GPIO_INTR_RISING (0x01UL) /**< \brief Rising-Edge interrupt */ +#define CY_GPIO_INTR_FALLING (0x02UL) /**< \brief Falling-Edge interrupt */ +#define CY_GPIO_INTR_BOTH (0x03UL) /**< \brief Both-Edge interrupt */ +/** \} */ + +/** +* \defgroup group_gpio_sioVreg SIO output buffer mode +* \{ +* Constants to be used for setting the SIO output buffer mode on the pin. +*/ +#define CY_SIO_VREG_UNREGULATED (0x00UL) /**< \brief Unregulated output buffer */ +#define CY_SIO_VREG_REGULATED (0x01UL) /**< \brief Regulated output buffer */ +/** \} */ + +/** +* \defgroup group_gpio_sioIbuf SIO input buffer mode +* \{ +* Constants to be used for setting the SIO input buffer mode on the pin. +*/ +#define CY_SIO_IBUF_SINGLEENDED (0x00UL) /**< \brief Single ended input buffer */ +#define CY_SIO_IBUF_DIFFERENTIAL (0x01UL) /**< \brief Differential input buffer */ +/** \} */ + +/** +* \defgroup group_gpio_sioVtrip SIO input buffer trip-point +* \{ +* Constants to be used for setting the SIO input buffer trip-point of the pin. +*/ +#define CY_SIO_VTRIP_CMOS (0x00UL) /**< \brief CMOS input buffer (single-ended) */ +#define CY_SIO_VTRIP_TTL (0x01UL) /**< \brief TTL input buffer (single-ended) */ +#define CY_SIO_VTRIP_0_5VDDIO_0_5VOH (0x00UL) /**< \brief 0.5xVddio or 0.5xVoh (differential) */ +#define CY_SIO_VTRIP_0_4VDDIO_1_0VREF (0x01UL) /**< \brief 0.4xVddio or 0.4xVoh (differential) */ +/** \} */ + +/** +* \defgroup group_gpio_sioVref SIO reference voltage for input buffer trip-point +* \{ +* Constants to be used for setting the reference voltage of SIO input buffer trip-point. +*/ +#define CY_SIO_VREF_PINREF (0x00UL) /**< \brief Vref from analog pin */ +#define CY_SIO_VREF_1_2V (0x01UL) /**< \brief Vref from internal 1.2V reference */ +#define CY_SIO_VREF_AMUX_A (0x02UL) /**< \brief Vref from AMUXBUS_A */ +#define CY_SIO_VREF_AMUX_B (0x03UL) /**< \brief Vref from AMUXBUS_B */ +/** \} */ + +/** +* \defgroup group_gpio_sioVoh Regulated output voltage level (Voh) and input buffer trip-point of an SIO pair +* \{ +* Constants to be used for setting the Voh and input buffer trip-point of an SIO pair +*/ +#define CY_SIO_VOH_1_00 (0x00UL) /**< \brief Voh = 1 x Reference */ +#define CY_SIO_VOH_1_25 (0x01UL) /**< \brief Voh = 1.25 x Reference */ +#define CY_SIO_VOH_1_49 (0x02UL) /**< \brief Voh = 1.49 x Reference */ +#define CY_SIO_VOH_1_67 (0x03UL) /**< \brief Voh = 1.67 x Reference */ +#define CY_SIO_VOH_2_08 (0x04UL) /**< \brief Voh = 2.08 x Reference */ +#define CY_SIO_VOH_2_50 (0x05UL) /**< \brief Voh = 2.50 x Reference */ +#define CY_SIO_VOH_2_78 (0x06UL) /**< \brief Voh = 2.78 x Reference */ +#define CY_SIO_VOH_4_16 (0x07UL) /**< \brief Voh = 4.16 x Reference */ +/** \} */ + +/** \} group_gpio_macro */ + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_gpio_functions +* \{ +*/ + +/** +* \addtogroup group_gpio_functions_init +* \{ +*/ + +cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type* base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config); +cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config); +__STATIC_INLINE void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, + uint32_t outVal, en_hsiom_sel_t hsiom); +__STATIC_INLINE void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base); +__STATIC_INLINE void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value); +__STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum); + +/** \} group_gpio_functions_init */ + +/** +* \addtogroup group_gpio_functions_gpio +* \{ +*/ + +__STATIC_INLINE uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum); + +/** \} group_gpio_functions_gpio */ + +/** +* \addtogroup group_gpio_functions_sio +* \{ +*/ + +__STATIC_INLINE void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum); + +/** \} group_gpio_functions_sio */ + +/** +* \addtogroup group_gpio_functions_interrupt +* \{ +*/ + +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base); + +#if (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void); +#endif /* (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) */ + +#if (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void); +#endif /* (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) */ + +#if (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void); +#endif /* (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) */ + +#if (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void); +#endif /* (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) */ + +/** \} group_gpio_functions_interrupt */ + + +/******************************************************************************* +* Function Name: Cy_GPIO_Pin_FastInit +****************************************************************************//** +* +* \brief Initialize the most common configuration settings for all pin types. +* +* These include, drive mode, initial output value, and HSIOM connection. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param driveMode +* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros +* +* \param outVal +* Logic state of the output buffer driven to the pin (1 or 0) +* +* \param hsiom +* HSIOM input selection +* +* \return +* void +* +* \note +* This function modifies port registers in read-modify-write operations. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, + uint32_t outVal, en_hsiom_sel_t hsiom) +{ + uint32_t tempReg; + uint32_t portNum; + HSIOM_PRT_Type* portAddrHSIOM; + + tempReg = (base->OUT & ~(CY_GPIO_OUT_MASK << pinNum)); + base->OUT = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum); + + tempReg = (base->CFG & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET))); + base->CFG = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)); + + portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE; + portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); + + if(pinNum < CY_GPIO_PRT_HALF) + { + tempReg = portAddrHSIOM->PORT_SEL0 & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); + portAddrHSIOM->PORT_SEL0 = tempReg | ((hsiom & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); + } + else + { + pinNum -= CY_GPIO_PRT_HALF; + tempReg = portAddrHSIOM->PORT_SEL1 & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); + portAddrHSIOM->PORT_SEL1 = tempReg | ((hsiom & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); + } +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Port_Deinit +****************************************************************************//** +* +* \brief Reset a complete port of pins back to power on reset defaults. +* +* \param base +* Pointer to the pin's port register base address +* +* \return +* void +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base) +{ + uint32_t portNum; + HSIOM_PRT_Type* portAddrHSIOM; + + portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE; + portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); + + base->OUT = CY_GPIO_PRT_DEINIT; + base->CFG = CY_GPIO_PRT_DEINIT; + base->CFG_IN = CY_GPIO_PRT_DEINIT; + base->CFG_OUT = CY_GPIO_PRT_DEINIT; + base->INTR_CFG = CY_GPIO_PRT_DEINIT; + base->INTR_MASK = CY_GPIO_PRT_DEINIT; + base->CFG_SIO = CY_GPIO_PRT_DEINIT; + portAddrHSIOM->PORT_SEL0 = CY_GPIO_PRT_DEINIT; + portAddrHSIOM->PORT_SEL1 = CY_GPIO_PRT_DEINIT; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetHSIOM +****************************************************************************//** +* +* \brief Configures the HSIOM connection to the pin. +* +* Connects the specified High-Speed Input Output Multiplexer (HSIOM) selection +* to the pin. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* HSIOM input selection +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value) +{ + uint32_t portNum; + uint32_t tempReg; + HSIOM_PRT_Type* portAddrHSIOM; + + portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE; + portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); + + if(pinNum < CY_GPIO_PRT_HALF) + { + tempReg = portAddrHSIOM->PORT_SEL0 & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); + portAddrHSIOM->PORT_SEL0 = tempReg | ((value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); + } + else + { + pinNum -= CY_GPIO_PRT_HALF; + tempReg = portAddrHSIOM->PORT_SEL1 & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); + portAddrHSIOM->PORT_SEL1 = tempReg | ((value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); + } +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetHSIOM +****************************************************************************//** +* +* \brief Returns the current HSIOM multiplexer connection to the pin. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* HSIOM input selection +* +*******************************************************************************/ +__STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum) +{ + uint32_t returnValue; + uint32_t portNum; + HSIOM_PRT_Type* portAddrHSIOM; + + portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE; + portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); + + if(pinNum < CY_GPIO_PRT_HALF) + { + returnValue = (portAddrHSIOM->PORT_SEL0 >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK; + } + else + { + pinNum -= CY_GPIO_PRT_HALF; + returnValue = (portAddrHSIOM->PORT_SEL1 >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK; + } + + return (en_hsiom_sel_t)returnValue; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_PortToAddr +****************************************************************************//** +* +* \brief Retrieves the port address based on the given port number. +* +* This is a helper function to calculate the port base address when given a port +* number. It is to be used when pin access needs to be calculated at runtime. +* +* \param portNum +* Port number +* +* \return +* Base address of the port register structure +* +*******************************************************************************/ +__STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum) +{ + GPIO_PRT_Type* base; + + if(portNum < (uint32_t)IOSS_GPIO_GPIO_PORT_NR) + { + base = (GPIO_PRT_Type *)(GPIO_BASE + (GPIO_PRT_SECTION_SIZE * portNum)); + } + else + { + /* Error: Return default base address */ + base = (GPIO_PRT_Type *)(GPIO_BASE); + } + + return (base); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Read +****************************************************************************//** +* +* \brief Reads the current logic level on the input buffer of the pin. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Logic level present on the pin +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->IN >> (pinNum)) & CY_GPIO_IN_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Write +****************************************************************************//** +* +* \brief Write a logic 0 or logic 1 state to the output driver. +* +* This function should be used only for software driven pins. It does not have +* any effect on peripheral driven pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Logic level to drive out on the pin +* +* \return +* void +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + /* Thread-safe: Directly access the pin registers instead of base->OUT */ + if(CY_GPIO_ZERO == value) + { + base->OUT_CLR = CY_GPIO_OUT_MASK << pinNum; + } + else + { + base->OUT_SET = CY_GPIO_OUT_MASK << pinNum; + } +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_ReadOut +****************************************************************************//** +* +* \brief Reads the current logic level on the pin output driver. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Logic level on the pin output driver +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->OUT >> pinNum) & CY_GPIO_OUT_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Set +****************************************************************************//** +* +* \brief Set a pin output to logic state high. +* +* This function should be used only for software driven pins. It does not have +* any effect on peripheral driven pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* void +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum) +{ + base->OUT_SET = CY_GPIO_OUT_MASK << pinNum; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Clr +****************************************************************************//** +* +* \brief Set a pin output to logic state Low. +* +* This function should be used only for software driven pins. It does not have +* any effect on peripheral driven pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* void +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum) +{ + base->OUT_CLR = CY_GPIO_OUT_MASK << pinNum; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Inv +****************************************************************************//** +* +* \brief Set a pin output logic state to the inverse of the current output +* logic state. +* +* This function should be used only for software driven pins. It does not have +* any effect on peripheral driven pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* void +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum) +{ + base->OUT_INV = CY_GPIO_OUT_MASK << pinNum; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetDrivemode +****************************************************************************//** +* +* \brief Configures the pin output buffer drive mode and input buffer enable. +* +* The output buffer drive mode and input buffer enable are combined into a single +* parameter. The drive mode controls the behavior of the pin in general. +* Enabling the input buffer allows the digital pin state to be read but also +* contributes to extra current consumption. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + pinLoc = pinNum << CY_GPIO_DRIVE_MODE_OFFSET; + tempReg = (base->CFG & ~(CY_GPIO_CFG_DM_MASK << pinLoc)); + base->CFG = tempReg | ((value & CY_GPIO_CFG_DM_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetDrivemode +****************************************************************************//** +* +* \brief Returns the pin output buffer drive mode and input buffer enable state. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->CFG >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetVtrip +****************************************************************************//** +* +* \brief Configures the GPIO pin input buffer voltage threshold mode. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + + tempReg = base->CFG_IN & ~(CY_GPIO_CFG_IN_VTRIP_SEL_MASK << pinNum); + base->CFG_IN = tempReg | ((value & CY_GPIO_CFG_IN_VTRIP_SEL_MASK) << pinNum); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetVtrip +****************************************************************************//** +* +* \brief Returns the pin input buffer voltage threshold mode. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->CFG_IN >> pinNum) & CY_GPIO_CFG_IN_VTRIP_SEL_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetSlewRate +****************************************************************************//** +* +* \brief Configures the pin output buffer slew rate. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + + tempReg = base->CFG_OUT & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum); + base->CFG_OUT = tempReg | ((value & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetSlewRate +****************************************************************************//** +* +* \brief Returns the pin output buffer slew rate. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->CFG_OUT >> pinNum) & CY_GPIO_CFG_OUT_SLOW_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetDriveSel +****************************************************************************//** +* +* \brief Configures the pin output buffer drive strength. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + pinLoc = pinNum + CY_GPIO_CFG_OUT_DRIVE_OFFSET; + tempReg = base->CFG_OUT & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc); + base->CFG_OUT = tempReg | ((value & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetDriveSel +****************************************************************************//** +* +* \brief Returns the pin output buffer drive strength. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->CFG_OUT >> (pinNum + CY_GPIO_CFG_OUT_DRIVE_OFFSET)) & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetVregEn +****************************************************************************//** +* +* \brief Configures the SIO pin pair output buffer regulation mode. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + pinLoc = (pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET; + tempReg = base->CFG_SIO & ~(CY_GPIO_VREG_EN_MASK << pinLoc); + base->CFG_SIO = tempReg | ((value & CY_GPIO_VREG_EN_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetVregEn +****************************************************************************//** +* +* \brief Returns the SIO pin pair output buffer regulation mode. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->CFG_SIO >> ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET)) & CY_GPIO_VREG_EN_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetIbufMode +****************************************************************************//** +* +* \brief Configures the SIO pin pair input buffer mode. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT; + tempReg = (base->CFG_SIO & ~(CY_GPIO_IBUF_MASK << pinLoc)); + base->CFG_SIO = tempReg | ((value & CY_GPIO_IBUF_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetIbufMode +****************************************************************************//** +* +* \brief Returns the SIO pin pair input buffer mode. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT)) & CY_GPIO_IBUF_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetVtripSel +****************************************************************************//** +* +* \brief Configures the SIO pin pair input buffer trip point. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT; + tempReg = (base->CFG_SIO & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc)); + base->CFG_SIO = tempReg | ((value & CY_GPIO_VTRIP_SEL_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetVtripSel +****************************************************************************//** +* +* \brief Returns the SIO pin pair input buffer trip point. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT)) & CY_GPIO_VTRIP_SEL_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetVrefSel +****************************************************************************//** +* +* \brief Configures the SIO reference voltage for the input buffer trip point. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT; + tempReg = (base->CFG_SIO & ~(CY_GPIO_VREF_SEL_MASK << pinLoc)); + base->CFG_SIO = tempReg | ((value & CY_GPIO_VREF_SEL_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetVrefSel +****************************************************************************//** +* +* \brief Returns the SIO reference voltage for the input buffer trip point. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT)) & CY_GPIO_VREF_SEL_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetVohSel +****************************************************************************//** +* +* \brief Configures the regulated output reference multiplier for the SIO pin pair. +* +* The regulated output reference controls both the output level of digital output +* pin and the input trip point of digital input pin in the SIO pair. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT; + tempReg = (base->CFG_SIO & ~(CY_GPIO_VOH_SEL_MASK << pinLoc)); + base->CFG_SIO = tempReg | ((value & CY_GPIO_VOH_SEL_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetVohSel +****************************************************************************//** +* +* \brief Returns the regulated output reference multiplier for the SIO pin pair. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT)) & CY_GPIO_VOH_SEL_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptStatus +****************************************************************************//** +* +* \brief Return the current interrupt state of the pin. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* 0 = Pin interrupt condition not detected +* 1 = Pin interrupt condition detected +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->INTR >> pinNum) & CY_GPIO_INTR_STATUS_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_ClearInterrupt +****************************************************************************//** +* +* \brief Clears the triggered pin interrupt. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* void +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum) +{ + /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */ + (void)base->INTR; + + base->INTR = CY_GPIO_INTR_STATUS_MASK << pinNum; + + /* This read ensures that the initial write has been flushed out to the hardware */ + (void)base->INTR; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetInterruptMask +****************************************************************************//** +* +* \brief Configures the pin interrupt to be forwarded to the CPU NVIC. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* 0 = Pin interrupt not forwarded to CPU interrupt controller +* 1 = Pin interrupt masked and forwarded to CPU interrupt controller +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + + tempReg= base->INTR_MASK & ~(CY_GPIO_INTR_EN_MASK << pinNum); + base->INTR_MASK = tempReg | ((value & CY_GPIO_INTR_EN_MASK) << pinNum); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptMask +****************************************************************************//** +* +* \brief Returns the state of the pin interrupt mask to determine whether it is +* configured to be forwarded to the CPU interrupt controller. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* 0 = Pin interrupt not forwarded to CPU interrupt controller +* 1 = Pin interrupt masked and forwarded to CPU interrupt controller +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->INTR_MASK >> pinNum) & CY_GPIO_INTR_EN_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptStatusMasked +****************************************************************************//** +* +* \brief Return the pin's current interrupt state after being masked. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* 0 = Pin interrupt not detected or not forwarded to CPU interrupt controller +* 1 = Pin interrupt detected and forwarded to CPU interrupt controller +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->INTR_MASKED >> pinNum) & CY_GPIO_INTR_MASKED_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetSwInterrupt +****************************************************************************//** +* +* \brief Force a pin interrupt to trigger. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* void +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum) +{ + base->INTR_SET = CY_GPIO_INTR_SET_MASK << pinNum; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetInterruptEdge +****************************************************************************//** +* +* \brief Configures the type of edge that will trigger a pin interrupt. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + pinLoc = pinNum << CY_GPIO_INTR_CFG_OFFSET; + tempReg = base->INTR_CFG & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc); + base->INTR_CFG = tempReg | ((value & CY_GPIO_INTR_EDGE_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptEdge +****************************************************************************//** +* +* \brief Returns the current pin interrupt edge type. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum) +{ + return (base->INTR_CFG >> (pinNum << CY_GPIO_INTR_CFG_OFFSET)) & CY_GPIO_INTR_EDGE_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetFilter +****************************************************************************//** +* +* \brief Configures which pin on the port connects to the port filter. +* +* \param base +* Pointer to the pin's port register base address +* +* \param value +* The number of the port pin to route to the port filter (0...7) +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value) +{ + uint32_t tempReg; + + tempReg = base->INTR_CFG & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET); + base->INTR_CFG = tempReg | ((value & CY_GPIO_INTR_FLT_EDGE_MASK) << CY_GPIO_INTR_FILT_OFFSET); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetFilter +****************************************************************************//** +* +* \brief Returns which pin is currently configured to connect to the port filter. +* +* \param base +* Pointer to the pin's port register base address +* +* \return +* The number of the port pin routed to the port filter (0...7) +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base) +{ + return (base->INTR_CFG >> CY_GPIO_INTR_FILT_OFFSET) & CY_GPIO_INTR_FLT_EDGE_MASK; +} + + +#if (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptCause0 +****************************************************************************//** +* +* \brief Returns the interrupt status for ports 0 to 31. +* +* \return +* 0 = Interrupt not detected on port +* 1 = Interrupt detected and sent to CPU interrupt controller on port +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void) +{ + return GPIO->INTR_CAUSE0; +} + +#endif + +#if (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptCause1 +****************************************************************************//** +* +* \brief Returns the interrupt status for ports 32 to 63. +* +* \return +* 0 = Interrupt not detected on port +* 1 = Interrupt detected and sent to CPU interrupt controller on port +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void) +{ + return GPIO->INTR_CAUSE1; +} + +#endif + +#if (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptCause2 +****************************************************************************//** +* +* \brief Returns the interrupt status for ports 64 to 95. +* +* \return +* 0 = Interrupt not detected on port +* 1 = Interrupt detected and sent to CPU interrupt controller on port +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void) +{ + return GPIO->INTR_CAUSE2; +} + +#endif + +#if (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptCause3 +****************************************************************************//** +* +* \brief Returns the interrupt status for ports 96 to 127. +* +* \return +* 0 = Interrupt not detected on port +* 1 = Interrupt detected and sent to CPU interrupt controller on port +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void) +{ + return GPIO->INTR_CAUSE3; +} + +#endif + +/** \} group_gpio_functions */ + + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_GPIO_H */ + +/** \} group_gpio */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_drv.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_drv.c new file mode 100644 index 0000000000..62cb66b28f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_drv.c @@ -0,0 +1,464 @@ +/***************************************************************************//** +* \file +* \version 1.0 +* +* \breif +* IPC Driver - This source file contains the low level driver code for +* the IPC hardware. +* +******************************************************************************** +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_ipc_drv.h" + + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_LockAcquire +****************************************************************************//** +* +* This function is used to acquire the IPC lock. The function acquires the lock corresponding to the ipcPtr passed. +* +* \param ipcPtr +* This parameter is a handle which represents the base address of the registers of the IPC channel. +* The parameter is generally returned from a call to the \ref Cy_IPC_DRV_GetIpcBaseAddress +* +* \return +* Status for the function: +* CY_IPC_DRV_SUCCESS: The IPC was successfully acquired +* CY_IPC_DRV_ERROR: The IPC was not acquired since it was already acquired by another master +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_DRV_LockAcquire (IPC_STRUCT_Type const * ipcPtr) +{ + cy_en_ipcdrv_status_t retStatus; + + if( 0ul != (IPC_STRUCT_ACQUIRE_SUCCESS_Msk & ipcPtr->ACQUIRE)) + { + retStatus = CY_IPC_DRV_SUCCESS; + } + else + { + retStatus = CY_IPC_DRV_ERROR; + } + return(retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_GetLockStatus +****************************************************************************//** +* +* The function is used to read the lock status of an IPC channel. The function tells the reader if the IPC was in the locked or released state. +* +* \param ipcPtr +* This parameter is a handle which represents the base address of the registers of the IPC channel. +* The parameter is generally returned from a call to the \ref Cy_IPC_DRV_GetIpcBaseAddress +* +* \return +* Status for the function: +* CY_IPC_DRV_LOCKED: The IPC is in the Locked state +* CY_IPC_DRV_RELEASED: The IPC is in the Released state +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_DRV_GetLockStatus (IPC_STRUCT_Type const * ipcPtr) +{ + cy_en_ipcdrv_status_t retStatus; + + if( IPC_STRUCT_ACQUIRE_SUCCESS_Msk == (IPC_STRUCT_ACQUIRE_SUCCESS_Msk & ipcPtr->LOCK_STATUS) ) + { + retStatus = CY_IPC_DRV_LOCKED; + } + else + { + retStatus = CY_IPC_DRV_RELEASED; + } + return(retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_Release +****************************************************************************//** +* +* The function is used to release an IPC from the locked state. +* The function also has a way to specify through a parameter, which IPC interrupts need to be notified during the release event. +* +* \param ipcPtr +* This parameter is a handle which represents the base address of the registers of the IPC channel. +* The parameter is generally returned from a call to the \ref Cy_IPC_DRV_GetIpcBaseAddress +* +* \param releaseEventIntr +* Bit encoded list of IPC interrupt lines that are triggered by a release event +* +* \return +* Status for the function: +* CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC was released +* CY_IPC_DRV_NOT_ACQUIRED: The IPC channel was not acquired before the function call. +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_DRV_Release (IPC_STRUCT_Type* ipcPtr, uint32_t releaseEventIntr) +{ + cy_en_ipcdrv_status_t retStatus; + + /* Check to make sure the IPC is Acquired */ + if( IPC_STRUCT_ACQUIRE_SUCCESS_Msk == ( IPC_STRUCT_ACQUIRE_SUCCESS_Msk & ipcPtr->LOCK_STATUS) ) + { + /* The IPC was acquired, release the IPC channel */ + ipcPtr->RELEASE = (IPC_INTR_STRUCT_INTR_RELEASE_Msk & releaseEventIntr); + retStatus = CY_IPC_DRV_SUCCESS; + } + else /* The IPC channel was already released (not acquired) */ + { + retStatus = CY_IPC_DRV_NOT_ACQUIRED; + } + + return(retStatus); +} + + + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_Notify +****************************************************************************//** +* +* The function generates a notify event to an IPC interrupt structure. +* +* \param ipcPtr +* This parameter is a handle which represents the base address of the registers of the IPC channel. +* The parameter is generally returned from a call to the \ref Cy_IPC_DRV_GetIpcBaseAddress +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt lines that are triggered by a notification +* +* \return +* void +* +*******************************************************************************/ +void Cy_IPC_DRV_Notify (IPC_STRUCT_Type* ipcPtr, uint32_t notifyEventIntr) +{ + ipcPtr->NOTIFY = (IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk & notifyEventIntr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_SendMsgWord +****************************************************************************//** +* +* This function is used to send a 32 bit word message through an IPC channel. +* The function also has an associated notification field that will let the message notify one or multiple IPC interrupts. +* The IPC channel is locked and remains locked after the function returns. The receiver +* of the message should release the channel. +* +* \param ipcPtr +* This parameter is a handle which represents the base address of the registers of the IPC channel. +* The parameter is generally returned from a call to the \ref Cy_IPC_DRV_GetIpcBaseAddress. +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt lines that are triggered by a notification. +* +* \param message +* The message word that is the data placed in the IPC data register. +* +* \return +* Status for the function: +* CY_IPC_DRV_SUCCESS: The send operation was successful +* CY_IPC_DRV_ERROR: The IPC channel is unavailable since it is already locked. +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_DRV_SendMsgWord (IPC_STRUCT_Type* ipcPtr, uint32_t notifyEventIntr, uint32_t message) +{ + cy_en_ipcdrv_status_t retStatus; + + if( CY_IPC_DRV_SUCCESS == Cy_IPC_DRV_LockAcquire(ipcPtr) ) + { + /* If the channel was acquired, send the message. */ + ipcPtr->DATA = message; + ipcPtr->NOTIFY = (IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk & notifyEventIntr); + retStatus = CY_IPC_DRV_SUCCESS; + } + else + { + /* Channel was already acquired, return Error */ + retStatus = CY_IPC_DRV_ERROR; + } + return(retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_ReadMsgWord +****************************************************************************//** +* +* This function is used to read a 32 bit word message through an IPC channel. +* This function assumes that the channel is locked (in order for a valid message). If +* the channel is not locked the message is invalid. The user needs to call +* Cy_IPC_DRV_Release() function after reading the message, to release the lock. +* +* \param ipcPtr +* This parameter is a handle which represents the base address of the registers of the IPC channel. +* The parameter is generally returned from a call to the \ref Cy_IPC_DRV_GetIpcBaseAddress. +* +* \param message +* A variable where the read data is copied. +* +* \return +* Status for the function +* CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC was released. +* CY_IPC_DRV_ERROR: The function encountered an error since the IPC channel was already in a released state meaning the data may be invalid +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_DRV_ReadMsgWord (IPC_STRUCT_Type* ipcPtr, uint32_t * message) +{ + cy_en_ipcdrv_status_t retStatus; + + if( CY_IPC_DRV_LOCKED == Cy_IPC_DRV_GetLockStatus(ipcPtr) ) + { + /* The channel is locked, message is valid. */ + *message = ipcPtr->DATA; + retStatus = CY_IPC_DRV_SUCCESS; + } + else + { + /* The channel is not locked so channel is invalid. */ + retStatus = CY_IPC_DRV_ERROR; + } + return(retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_SendMsgPtr +****************************************************************************//** +* +* This function is used to send a message pointer through an IPC channel. +* The message structure may hold a generic pointer which may contain the address of +* any user data type or structure. This parameter could be a pointer to a 32 bit integer, an +* array or even a data structure defined in the user code. This function acts +* as a transfer engine for sending the pointer. Any memory management of the pointer +* allocation and deallocation is up to the application code. +* The function also has an associated notification field that will let the message +* notify one or multiple interrupts. +* +* \param ipcPtr +* This parameter is a handle which represents the base address of the registers of the IPC channel. +* The parameter is generally returned from a call to the \ref Cy_IPC_DRV_GetIpcBaseAddress +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt lines that are triggered during the release action. +* +* \param msgPtr +* The message pointer that is being sent over the IPC channel +* +* \return +* Status for the function: +* CY_IPC_DRV_SUCCESS: The send operation was successful +* CY_IPC_DRV_ERROR: The IPC channel is unavailable since it is already locked +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_DRV_SendMsgPtr(IPC_STRUCT_Type* ipcPtr, uint32_t notifyEventIntr, void const * msgPtr) +{ + cy_en_ipcdrv_status_t retStatus; + + if( CY_IPC_DRV_SUCCESS == Cy_IPC_DRV_LockAcquire(ipcPtr) ) + { + /* If the channel was acquired, send the message. */ + ipcPtr->DATA = (uint32_t)msgPtr; + ipcPtr->NOTIFY = ((uint32_t)IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk & notifyEventIntr); + retStatus = CY_IPC_DRV_SUCCESS; + } + else + { + /* Chaneel was already acquired, Error */ + retStatus = CY_IPC_DRV_ERROR; + } + return(retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_ReadMsgPtr +****************************************************************************//** +* +* This function is used to read a 32 bit pointer message through an IPC channel. +* +* \param ipcPtr +* This parameter is a handle which represents the base address of the registers of the IPC channel. +* The parameter is generally returned from a call to the \ref Cy_IPC_DRV_GetIpcBaseAddress +* +* \param msgPtr +* Pointer variable to hold the data pointer that is being read from the IPC channel +* +* +* \return +* Status for the function +* CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC was released +* CY_IPC_DRV_ERROR: The function encountered an error since the IPC channel was already in a released state meaning the data in it is invalid +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_DRV_ReadMsgPtr (IPC_STRUCT_Type* ipcPtr, void ** msgPtr) +{ + cy_en_ipcdrv_status_t retStatus; + + if( CY_IPC_DRV_LOCKED == Cy_IPC_DRV_GetLockStatus(ipcPtr) ) + { + /* The channel is locked, message is valid. */ + *msgPtr = (void *)(ipcPtr->DATA); + retStatus = CY_IPC_DRV_SUCCESS; + } + else + { + /* The channel is not locked so channel is invalid. */ + retStatus = CY_IPC_DRV_ERROR; + } + return(retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_SetIntrMask +****************************************************************************//** +* +* This function is used to set the interrupt mask for an IPC Interrupt. +* The mask can be set for release or notification events of all available IPC ports. +* +* \param ipcIntrPtr +* This is a handle to the IPC interrupt. This handle can be calculated from the IPC interrupt number using \ref Cy_IPC_DRV_GetIntrBaseAddr +* +* \param ipcReleaseMask +* An encoded list of all IPC structures that can trigger the interrupt on a release event +* +* \param ipcNotifyMask +* An encoded list of all IPC structures that can trigger the interrupt on a notify event. +* +* \return +* void +* +*******************************************************************************/ +void Cy_IPC_DRV_SetIntrMask (IPC_INTR_STRUCT_Type* ipcIntrPtr, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) +{ + ipcIntrPtr->INTR_MASK = ( ipcNotifyMask << IPC_INTR_STRUCT_INTR_NOTIFY_Pos) | ( ipcReleaseMask & IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_GetIntrMask +****************************************************************************//** +* +* This function is used to read the interrupt mask. + +* \param ipcIntrPtr +* This is a handle to the IPC interrupt. This handle can be calculated from the IPC interrupt number using \ref Cy_IPC_DRV_GetIntrBaseAddr +* +* \return +* The return value is encoded as follows +* +*
Interrupt sources Value +*
Ipc_PORTX_RELEASE Xth bit set +*
Ipc_PORTX_NOTIFY X+16 th bit set +*
+* +*******************************************************************************/ +uint32_t Cy_IPC_DRV_GetIntrMask(IPC_INTR_STRUCT_Type const * ipcIntrPtr) +{ + return(ipcIntrPtr->INTR_MASK); +} + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_GetIntrStatusMasked +****************************************************************************//** +* +* This function is used to read the active unmasked interrupt. This function can be used in the interrupt service routine to +* find which source triggered the interrupt. +* +* \param ipcIntrPtr +* This is a handle to the IPC interrupt. This handle can be calculated from the IPC interrupt number using \ref Cy_IPC_DRV_GetIntrBaseAddr +* +* \return +* The return value is encoded as follows +* +*
Interrupt sources Value +*
Ipc_PORTX_RELEASE Xth bit set +*
Ipc_PORTX_NOTIFY X+16 th bit set +*
+* +*******************************************************************************/ +uint32_t Cy_IPC_DRV_GetIntrStatusMasked (IPC_INTR_STRUCT_Type const * ipcIntrPtr) +{ + return(ipcIntrPtr->INTR_MASKED); +} + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_GetIntrStatus +****************************************************************************//** +* +* This function is used to read the pending interrupts. Note that this read is an unmasked read of the interrupt status +* Interrupt sources read as active by this function would generate interrupts only if they were not masked + +* \param ipcIntrPtr +* This is a handle to the IPC interrupt. This handle can be calculated from the IPC interrupt number using \ref Cy_IPC_DRV_GetIntrBaseAddr +* +* \return +* The return value is encoded as follows +* +*
Interrupt sources Value +*
Ipc_PORTX_RELEASE Xth bit set +*
Ipc_PORTX_NOTIFY X+16 th bit set +*
+* +*******************************************************************************/ +uint32_t Cy_IPC_DRV_GetIntrStatus(IPC_INTR_STRUCT_Type const * ipcIntrPtr) +{ + return(ipcIntrPtr->INTR); +} + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_SetIntr +****************************************************************************//** +* +* This function is used to set the interrupt source. This function can be used to activate interrupts through software. +* Note that interrupt sources set using this interrupt would generate interrupts only if they are not masked +* +* \param ipcIntrPtr +* This is a handle to the IPC interrupt. This handle can be calculated from the IPC interrupt number using \ref Cy_IPC_DRV_GetIntrBaseAddr +* +* \param ipcReleaseMask +* An encoded list of all IPC structures that can trigger the interrupt on a release event +* +* \param ipcNotifyMask +* An encoded list of all IPC structures that can trigger the interrupt on a notify event. +* +* \return +* void +* +*******************************************************************************/ +void Cy_IPC_DRV_SetIntr(IPC_INTR_STRUCT_Type* ipcIntrPtr, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) +{ + ipcIntrPtr->INTR_SET = (ipcNotifyMask << IPC_INTR_STRUCT_INTR_NOTIFY_Pos) | ( ipcReleaseMask & IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk) ; +} + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_ClearIntr +****************************************************************************//** +* +* This function is used to clear the interrupt source. Use this function to clear a pending interrupt source in the interrupt status +* +* \param ipcIntrPtr +* This is a handle to the IPC interrupt. This handle can be calculated from the IPC interrupt number using \ref Cy_IPC_DRV_GetIntrBaseAddr +* +* \param ipcReleaseMask +* An encoded list of all IPC structures that can trigger the interrupt on a release event +* +* \param ipcNotifyMask +* An encoded list of all IPC structures that can trigger the interrupt on a notify event. +* +* \return +* void +* +*******************************************************************************/ +void Cy_IPC_DRV_ClearIntr(IPC_INTR_STRUCT_Type* ipcIntrPtr, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) +{ + ipcIntrPtr->INTR = (ipcNotifyMask << IPC_INTR_STRUCT_INTR_NOTIFY_Pos) | ( ipcReleaseMask & IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk) ; + (void)ipcIntrPtr->INTR; /* Read the register to flush the cache */ +} + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_drv.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_drv.h new file mode 100644 index 0000000000..3d686ae350 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_drv.h @@ -0,0 +1,288 @@ +/***************************************************************************//** +* \file cy_ipc_drv.h +* \version 1.0 +* +* Provides an API declaration of the IPC driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_IPC_DRV_H) +#define CY_IPC_DRV_H + + +/** +* \defgroup group_ipc Inter Process Communication (IPC) +* \{ +* Contains the driver API for low level IPC interface as well as Lock and Pipe +* upper level interfaces. +* +* The IPC driver provides a safe and reliable method to transfer data between +* CPUs or processes in a single device. Hardware locking provides a reliable +* method to ensure that only one device can acquire and transfer data at one +* time so no data is lost or over written by asynchronous processes or CPUs. +* +* The Lock functions made use of a single IPC channel to allow multiple locks +* that can be used by system or user function calls. By default there are +* 128 locks provided, although the user may modify the default value to any +* number, limited only by SRAM. +* +* The Pipe functions provide a method to transfer one or more words of data +* between CPUs or tasks. The data can be defined as a single 32-bit unsigned +* word, an array of data, or a user defined structure. The only limitation is +* that the first word in the array or structure must be a 32-bit unsigned word +* in which a client ID number is passed. The client ID dictates the callback +* function that will be called by the receiver of the message. After the +* callback function returns by the receiver, it will invoke a release callback +* function defined by the sender of the message. +* +* A User Pipe is provided for the user to transfer data between CPUs and +* tasks. +* +* \section group_ipc_configuration Configuration Considerations +* +* All IPC channels have been defined by the system. Users should not +* call any of the low level IPC functions. Only the Lock and Pipe functions +* are accessible by the user. The CyPipe is reserved for system level +* functions such as BLE and CapSense at this time. +* +* \section group_ipc_more_information More Information +* +* See TRM (Technical Reference Manual) for more information on IPC. +* +* \section group_ipc_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
8.8RAn external object or function shall be declared in one and only one +* file.This rule is violated in the following files: +* cy_ipc_pipe.c, cy_ipc_lock.c, cy_ipc_config.c
10.1RThe value of an expression of integer type shall not be +* implicitly converted to a different underlying type.Implicit conversion from signed to unsigned is present in the +* following files: cy_ipc_pipe.c, cy_ipc_config.c
11.4AA cast should not be performed between a pointer to object type +* and a different pointer to object type.In file cy_ipc_pipe.c, the message pointer is set to a void pointer +* because the message structure is defined by the user and is unknown. +*
14.10RAll if ... else if constructs shall be terminated with an else clause. +* In file cy_ipc_pipe.c this rule is violated intentionally and safely. +*
16.7AA pointer parameter in a function prototype should be declared as +* pointer to const if the pointer is not used to modify the addressed +* object.In file cy_ipc_drv.c this rule is violated because the API +* implementation is expected in future to modify the parameter.
16.9RA function identifier shall only be used with either a preceding &, +* or with a parenthesised parameter list, which may be empty.In file cy_ipc_config.c this rule is violated intentionally.
16.10RIf a function returns error information, then that error information +* shall be tested.In file cy_ipc_pipe.c this rule is violated intentionally.
+* +* \section group_ipc_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_ipc_macro Macro +* \defgroup group_ipc_functions Functions +* \defgroup group_ipc_data_structures Data Structures +* \defgroup group_ipc_enums Enumerated Types +* +*/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" + + +/** +* \addtogroup group_ipc_data_structures +* \{ +*/ + +/** \} group_ipc_data_structures */ + +/** +* \addtogroup group_ipc_macro +* \{ +*/ + +/** Driver major version */ +#define CY_IPC_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_IPC_DRV_VERSION_MINOR 0 + +/* defined in the device.h */ + + +/* Constants for ACQUIRE register */ +#define CY_IPC_ACQ_NOT_ACQUIRED (uint32_t)(0x00000000ul) /**< Used to determine if lock was not acquired */ +#define CY_IPC_NO_NOTIFIFICATION (uint32_t)(0x00000000ul) /**< Return value when no notifications have occurred or will be forced */ + +/* Error Code constants */ + + +#define CY_IPC_ID CY_PDL_DRV_ID(0x22u) /**< Software PDL driver ID for IPC */ +#define CY_IPC_ID_INFO (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_INFO ) /**< Return prefix for IPC driver function status codes */ +#define CY_IPC_ID_WARNING (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_WARNING) /**< Return prefix for IPC driver function warning return values */ +#define CY_IPC_ID_ERROR (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_ERROR) /**< Return prefix for IPC driver function error return values */ + + +/** \} group_ipc_macro */ + +/* end of definition in device.h */ + + +/** +* \addtogroup group_ipc_enums +* \{ +*/ + +/** +* This is a list of ENUMs used for function return status. +*/ +typedef enum +{ + CY_IPC_DRV_SUCCESS = 0x00u, /**< Function was successfully executed */ + CY_IPC_DRV_ERROR = ( CY_IPC_ID_ERROR + 1ul), /**< Function was not executed due to an error. Typical conditions for the error explained in the function description */ + CY_IPC_DRV_NOT_ACQUIRED = ( CY_IPC_ID_ERROR + 2ul), /**< IPC was not previously acquired */ + CY_IPC_DRV_RELEASED = ( CY_IPC_ID_INFO + 0ul), /**< IPC was in a released state */ + CY_IPC_DRV_LOCKED = ( CY_IPC_ID_INFO + 1ul) /**< IPC was in a locked/acquired state */ +} cy_en_ipcdrv_status_t; + +/** \} group_ipc_enums */ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +/** +* \addtogroup group_ipc_functions +* \{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif +cy_en_ipcdrv_status_t Cy_IPC_DRV_LockAcquire (IPC_STRUCT_Type const * ipcPtr); +cy_en_ipcdrv_status_t Cy_IPC_DRV_GetLockStatus (IPC_STRUCT_Type const * ipcPtr); +cy_en_ipcdrv_status_t Cy_IPC_DRV_Release (IPC_STRUCT_Type* ipcPtr, uint32_t releaseEventIntr); +void Cy_IPC_DRV_Notify (IPC_STRUCT_Type* ipcPtr, uint32_t notifyEventIntr); +cy_en_ipcdrv_status_t Cy_IPC_DRV_SendMsgWord (IPC_STRUCT_Type* ipcPtr, uint32_t notifyEventIntr, uint32_t message); +cy_en_ipcdrv_status_t Cy_IPC_DRV_ReadMsgWord (IPC_STRUCT_Type* ipcPtr, uint32_t * message); +cy_en_ipcdrv_status_t Cy_IPC_DRV_SendMsgPtr (IPC_STRUCT_Type* ipcPtr, uint32_t notifyEventIntr, void const * msgPtr); +cy_en_ipcdrv_status_t Cy_IPC_DRV_ReadMsgPtr (IPC_STRUCT_Type* ipcPtr, void** msgPtr); + +void Cy_IPC_DRV_SetIntrMask (IPC_INTR_STRUCT_Type* ipcIntrPtr, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask); +uint32_t Cy_IPC_DRV_GetIntrMask(IPC_INTR_STRUCT_Type const * ipcIntrPtr); +uint32_t Cy_IPC_DRV_GetIntrStatusMasked (IPC_INTR_STRUCT_Type const * ipcIntrPtr); +uint32_t Cy_IPC_DRV_GetIntrStatus(IPC_INTR_STRUCT_Type const * ipcIntrPtr); +void Cy_IPC_DRV_SetIntr(IPC_INTR_STRUCT_Type* ipcIntrPtr, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask); +void Cy_IPC_DRV_ClearIntr(IPC_INTR_STRUCT_Type* ipcIntrPtr, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask); + +__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_DRV_GetIpcBaseAddress (uint32_t ipcIndex); +__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_DRV_GetIntrBaseAddr (uint32_t ipcIntrIndex); + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_GetIpcBaseAddress +****************************************************************************//** +* +* This function takes an IPC index as a parameter and returns the base address the IPC registers corresponding to the IPC channel. +* The function returns a zero value if the ipcIndex passed was invalid. +* +* \param ipcIndex +* Represents the hardware IPC index. This is converted to base address of the IPC channel registers. +* +* \return +* Returns a pointer to the base of the IPC registers. If the ipcIndex passed was invalid the function returns zero +* +*******************************************************************************/ +__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_DRV_GetIpcBaseAddress (uint32_t ipcIndex) +{ + CY_ASSERT((uint32_t)CPUSS_IPC_IPC_NR > ipcIndex); + return ( (IPC_STRUCT_Type*) ( &IPC->STRUCT[ipcIndex] ) ); +} + +/******************************************************************************* +* Function Name: Cy_IPC_DRV_GetIntrBaseAddr +****************************************************************************//** +* +* This function takes an IPC index and returns the base address of the IPC interrupt registers corresponding to the IPC Interrupt. +* The function returns a zero value if the ipcIntrIndex passed was invalid. +* +* \param ipcIntrIndex +* Represents the hardware IPC interrupt number. This is converted to the base address of the IPC interrupt registers. +* +* \return +* Returns a pointer to the base of the IPC interrupt registers. If the IpcIntIndex passed was invalid, the function returns zero +* +*******************************************************************************/ +__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_DRV_GetIntrBaseAddr (uint32_t ipcIntrIndex) +{ + CY_ASSERT((uint32_t)CPUSS_IPC_IPC_IRQ_NR > ipcIntrIndex); + return ( (IPC_INTR_STRUCT_Type*) ( &IPC->INTR_STRUCT[ipcIntrIndex] ) ); +} + +/** \} group_ipc_functions */ + +#ifdef __cplusplus +} +#endif + +/** \} group_ipc */ + +#endif /* !defined(CY_IPC_DRV_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_lock.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_lock.c new file mode 100644 index 0000000000..7550fc96b3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_lock.c @@ -0,0 +1,268 @@ +/***************************************************************************//** +* \file +* \version 1.0 +* +* Description: +* IPC Lock Driver - This source file contains the source code for the lock +* level APIs for the IPC interface. +* +******************************************************************************** +* Copyright2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_ipc_drv.h" +#include "cy_ipc_lock.h" + + +/* Assign the IPC structure used for Lock functions */ +IPC_STRUCT_Type* CY_IPC_LOCK_Ptr = (IPC_STRUCT_Type*) &IPC->STRUCT[CY_IPC_CHAN_LOCK]; /**< Pointer to IPC structure used for locks */ + +struct CY_IPC_LOCK_STRUCT { + uint32_t maxLocks; /* Maximum locks in system */ + uint32_t *arrayPtr; /* Pointer to lock array */ +} CY_IPC_LOCK_data; +typedef struct CY_IPC_LOCK_STRUCT CY_IPC_LOCK_STRUCT; + + +/******************************************************************************* +* Function Name: Cy_IPC_LOCK_Init +****************************************************************************//** +* +* This function initializes the lock subsystem. The user must create an array of +* unsigned 32-bit words to hold the lock bits. The amount of locks will be +* the size of the array * 32. The total lock count will always be a multiple of 32. +* Note that only one of the CPUs in a multi-CPU system should call this +* init function and provide a pointer to SRAM that can be shared between all +* the CPUs in the system that will use locks. +* +* \param count +* The maximum number of locks to be supported (multiple of 32). +* +* \param memPtr +* This points to the array of (count/32) words that contain the lock data. +* +* \return +* CY_IPC_LOCK_SUCCESS: Sucessfully initialized +* CY_IPC_LOCK_INIT_ERROR: Init error, count value was zero, or greater than 31 and not a multiple of 32. +* +* +*******************************************************************************/ +cy_en_ipclock_status_t Cy_IPC_LOCK_Init(uint32_t count, uint32_t memPtr[]) +{ + extern IPC_STRUCT_Type* CY_IPC_LOCK_Ptr; + cy_en_ipclock_status_t retStatus = CY_IPC_LOCK_INIT_ERROR; + uint32_t cnt; + + CY_IPC_LOCK_data.maxLocks = count; + CY_IPC_LOCK_data.arrayPtr = memPtr; + + /* Initialize all locks to released */ + for(cnt= 0u ; cnt < (count/CY_IPC_LOCKS_PER_WORD); cnt++) + { + CY_IPC_LOCK_data.arrayPtr[cnt] = (uint32_t)0x00000000ul; + } + + /* Make sure locks start out released */ + (void) Cy_IPC_DRV_Release (CY_IPC_LOCK_Ptr, CY_IPC_NO_NOTIFIFICATION); + + /* Set the IPC Data with the pointer to the array. */ + + if( CY_IPC_DRV_SUCCESS == Cy_IPC_DRV_SendMsgPtr (CY_IPC_LOCK_Ptr, CY_IPC_NO_NOTIFIFICATION, &CY_IPC_LOCK_data)) + { + if(CY_IPC_DRV_SUCCESS == Cy_IPC_DRV_Release (CY_IPC_LOCK_Ptr, CY_IPC_NO_NOTIFIFICATION)) + { + retStatus = CY_IPC_LOCK_SUCCESS; + } + } + + return(retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_LOCK_Acquire +****************************************************************************//** +* +* This functions tries to acquire a lock. If the lock is available, this +* function returns immediately with CY_IPC_LOCK_ERROR_NONE. If the lock is not +* available, this function returns immediately with CY_IPC_LOCK_ERROR_LOCKED. +* +* \param lockNumber +* The lock number to acquire. +* +* \return +* CY_IPC_LOCK_SUCCESS: The lock was acquired +* CY_IPC_LOCK_LOCKED: The lock channel is busy or locked by another process +* CY_IPC_LOCK_NOT_ACQUIRED: Lock was already acquired +* CY_IPC_LOCK_OUT_OF_RANGE: The lock number is not valid +* +* +*******************************************************************************/ +cy_en_ipclock_status_t Cy_IPC_LOCK_Acquire(uint32_t lockNumber) +{ + uint32_t lockIndex, lockMask; + cy_en_ipclock_status_t retStatus = CY_IPC_LOCK_LOCKED; + CY_IPC_LOCK_STRUCT *lockStructPtr; + + /* Check to make sure the Lock channel is released */ + /* If so, check is specific channel can be locked. */ + if(CY_IPC_DRV_SUCCESS == Cy_IPC_DRV_LockAcquire (CY_IPC_LOCK_Ptr)) + { + /* Get the index into the lock array and calculate the mask */ + lockIndex = lockNumber / CY_IPC_LOCKS_PER_WORD; + lockMask = (0x00000001ul) << (lockNumber - (lockIndex * CY_IPC_LOCKS_PER_WORD) ); + + /* Get pointer to structure */ + lockStructPtr = (CY_IPC_LOCK_STRUCT *)CY_IPC_LOCK_Ptr->DATA; + if(lockNumber < lockStructPtr->maxLocks) + { + if((lockStructPtr->arrayPtr[lockIndex] & lockMask) == (uint32_t)0) + { + lockStructPtr->arrayPtr[lockIndex] |= lockMask; + retStatus = CY_IPC_LOCK_SUCCESS; + } + else + { + retStatus = CY_IPC_LOCK_NOT_ACQUIRED; + } + } + else + { + retStatus = CY_IPC_LOCK_OUT_OF_RANGE; + } + /* Do not send an event on a lock acquire when the lock channel */ + /* is released, since the lock was just acquired. */ + (void) Cy_IPC_DRV_Release (CY_IPC_LOCK_Ptr, CY_IPC_NO_NOTIFIFICATION); + } + + return(retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_LOCK_Status +****************************************************************************//** +* +* This function returns the status of any given lock. +* +* \param lockNumber +* The index of the lock to return status. +* +* \return +* CY_IPC_LOCK_STATUS_LOCKED: The lock is in the acquired state. (return a 1) +* CY_IPC_LOCK_STATUS_UNLOCKED: The lock is in the released state. ( return 0) +* CY_IPC_LOCK_OUT_OF_RANGE: The lock number is not valid +* +* +*******************************************************************************/ +cy_en_ipclock_status_t Cy_IPC_LOCK_Status(uint32_t lockNumber) +{ + cy_en_ipclock_status_t retStatus; + uint32_t lockIndex, lockMask; + CY_IPC_LOCK_STRUCT *lockStructPtr; + + lockStructPtr = (CY_IPC_LOCK_STRUCT *)CY_IPC_LOCK_Ptr->DATA; + if(lockNumber < lockStructPtr->maxLocks) + { + /* Get the index into the lock array and calculate the mask */ + lockIndex = lockNumber / CY_IPC_LOCKS_PER_WORD; + lockMask = (0x00000001ul) << (lockNumber - (lockIndex * CY_IPC_LOCKS_PER_WORD) ); + + if((lockStructPtr->arrayPtr[lockIndex] & lockMask) != (uint32_t)0) + { + retStatus = CY_IPC_LOCK_STATUS_LOCKED; + } + else + { + retStatus = CY_IPC_LOCK_STATUS_UNLOCKED; + } + } + else + { + retStatus = CY_IPC_LOCK_OUT_OF_RANGE; + } + return(retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_LOCK_Release +****************************************************************************//** +* +* This functions tries to releases a lock. +* +* \param lockNumber +* The index of the lock in which to release. +* +* \return +* CY_IPC_LOCK_SUCCESS: The lock was released +* CY_IPC_LOCK_NOT_ACQUIRED: The lock was already released +* CY_IPC_LOCK_LOCKED: The lock channel was locked or busy +* CY_IPC_LOCK_OUT_OF_RANGE: The lock number is not valid +* +* +*******************************************************************************/ +cy_en_ipclock_status_t Cy_IPC_LOCK_Release(uint32_t lockNumber) +{ + uint32_t lockIndex, lockMask; + cy_en_ipclock_status_t retStatus = CY_IPC_LOCK_LOCKED; + CY_IPC_LOCK_STRUCT *lockStructPtr; + + /* Check to make sure the Lock channel is released */ + /* If so, check is specific channel can be locked. */ + if(CY_IPC_DRV_SUCCESS == Cy_IPC_DRV_LockAcquire (CY_IPC_LOCK_Ptr)) + { + lockIndex = lockNumber / CY_IPC_LOCKS_PER_WORD; + lockMask = (0x00000001ul) << (lockNumber - (lockIndex * CY_IPC_LOCKS_PER_WORD) ); + + /* Get pointer to structure */ + lockStructPtr = (CY_IPC_LOCK_STRUCT *)CY_IPC_LOCK_Ptr->DATA; + if(lockNumber < lockStructPtr->maxLocks) + { + if((lockStructPtr->arrayPtr[lockIndex] & lockMask) != (uint32_t)0u) + { + lockStructPtr->arrayPtr[lockIndex] &= ~lockMask; + retStatus = CY_IPC_LOCK_SUCCESS; + } + else + { + retStatus = CY_IPC_LOCK_NOT_ACQUIRED; + } + } + else + { + retStatus = CY_IPC_LOCK_OUT_OF_RANGE; + } + /* Release, but do not trigger a release event */ + (void) Cy_IPC_DRV_Release (CY_IPC_LOCK_Ptr, CY_IPC_NO_NOTIFIFICATION); + } + return(retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_LOCK_GetMaxLocks +****************************************************************************//** +* +* This function returns the maximum lock count. +* +* \param +* +* \return +* Returns the maximum lock count as configured. +* +* +*******************************************************************************/ +uint32_t Cy_IPC_LOCK_GetMaxLocks(void) +{ + + CY_IPC_LOCK_STRUCT *lockStructPtr; + + lockStructPtr = (CY_IPC_LOCK_STRUCT *)CY_IPC_LOCK_Ptr->DATA; + + return(lockStructPtr->maxLocks); +} + + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_lock.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_lock.h new file mode 100644 index 0000000000..dc350ac55a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_lock.h @@ -0,0 +1,84 @@ +/***************************************************************************//** +* \file +* \version 1.0 +* +* \brief +* Header file for IPC LOCK functions +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CY_IPC_LOCK_H_ +#define _CY_IPC_LOCK_H_ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "cy_ipc_drv.h" + +/** +* \addtogroup group_ipc_macro +* \{ +*/ + +#define CY_IPC_LOCK_RTN 0x0100ul /**< Software PDL driver ID for IPC lock functions */ +#define CY_IPC_LOCK_ID_INFO (uint32_t)( CY_IPC_ID_INFO | CY_IPC_LOCK_RTN) /**< Return prefix for IPC lock function status codes */ +#define CY_IPC_LOCK_ID_WARNING (uint32_t)( CY_IPC_ID_WARNING | CY_IPC_LOCK_RTN) /**< Return prefix for IPC lock function warning return values */ +#define CY_IPC_LOCK_ID_ERROR (uint32_t)( CY_IPC_ID_ERROR | CY_IPC_LOCK_RTN) /**< Return prefix for IPC lock function error return values */ + +/**< Return constants for IPC lock functions. */ +typedef enum +{ + CY_IPC_LOCK_SUCCESS = (uint32_t)0x00u, /**< No error has occured */ + CY_IPC_LOCK_ERROR_LOCKED = (uint32_t)(CY_IPC_LOCK_ID_ERROR | 1ul), /**< Lock has already been locked */ + CY_IPC_LOCK_ERROR_UNLOCKED = (uint32_t)(CY_IPC_LOCK_ID_ERROR | 2ul), /**< Lock is unlocked */ + CY_IPC_LOCK_INIT_ERROR = (uint32_t)(CY_IPC_LOCK_ID_ERROR | 3ul), /**< Lock API return when the init function has failed */ + CY_IPC_LOCK_OUT_OF_RANGE = (uint32_t)(CY_IPC_LOCK_ID_ERROR | 4ul), /**< Lock API return when lock is out of the range of valid locks */ + + CY_IPC_LOCK_NOT_ACQUIRED = (uint32_t)(CY_IPC_LOCK_ID_INFO | 2ul), /**< Lock API return when lock was not acquired */ + CY_IPC_LOCK_LOCKED = (uint32_t)(CY_IPC_LOCK_ID_INFO | 3ul), /**< Lock API return status when lock was already locked */ + CY_IPC_LOCK_STATUS_LOCKED = (uint32_t)(CY_IPC_LOCK_ID_INFO | 1ul), /**< Lock status return that the channel is locked */ + CY_IPC_LOCK_STATUS_UNLOCKED = (uint32_t)(CY_IPC_LOCK_ID_INFO | 0ul) /**< Lock status return that the channel is unlocked */ +} cy_en_ipclock_status_t; + +#define CY_IPC_LOCKS_PER_WORD (uint32_t)32u /**< 32 locks per word */ + + + +/** \} group_ipc_macro */ + + + +/** \} group_ipc_data_structures */ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +/** +* \addtogroup group_ipc_functions +* \{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif +cy_en_ipclock_status_t Cy_IPC_LOCK_Init(uint32_t count, uint32_t mem_p[]); +cy_en_ipclock_status_t Cy_IPC_LOCK_Acquire(uint32_t lockNumber); +cy_en_ipclock_status_t Cy_IPC_LOCK_Release(uint32_t lockNumber); +cy_en_ipclock_status_t Cy_IPC_LOCK_Status(uint32_t lockNumber); +uint32_t Cy_IPC_LOCK_GetMaxLocks(void); +#ifdef __cplusplus +} +#endif + +/** \} group_ipc_functions */ + +#endif /* _CY_IPC_LOCK_H_ */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_pipe.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_pipe.c new file mode 100644 index 0000000000..731c38a48c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_pipe.c @@ -0,0 +1,345 @@ +/***************************************************************************//** +* \file +* \version 1.0 +* +* Description: +* IPC Pipe Driver - This source file includes code for the Pipe layer on top +* of the IPC driver. +* +******************************************************************************** +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_ipc_pipe.h" + +/* Define a pointer to array of endPoints. */ +cy_stc_ipc_pipe_ep_t * cy_ipc_pipe_epArray; + +/******************************************************************************* +* Function Name: Cy_IPC_PIPE_Config +****************************************************************************//** +* +* This function stores a copy of a pointer to the array of endpoints. All +* access to endpoints will be via the index of the endpoint in this array. +* +* \param theEpArray +* This is the pointer to an array of endpoint structures that the designer +* created and will be used to reference all endpoints. +* +* +* \return +* void +* +*******************************************************************************/ +void Cy_IPC_PIPE_Config(cy_stc_ipc_pipe_ep_t * theEpArray) +{ + /* Keep copy of this endpoint */ + cy_ipc_pipe_epArray = theEpArray; +} + +/******************************************************************************* +* Function Name: Cy_IPC_PIPE_Init +****************************************************************************//** +* +* This function initializes the endpoint of a pipe for the current CPU. An +* endpoint of a pipe is IPC channel that receives a message for the current +* CPU. The current CPU is the CPU that is executing the code. +* After this function is called, the callbackArray needs to be populated +* with the callback functions for that endpoint using the Cy_IPC_PIPE_RegisterCallback() +* function. +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structure) +* that designates the endpoint in which you want to initialize. +* +* \param cbArray +* This is a pointer to the callback function array. Based on the client ID, one +* of the functions in this array is called to process the message. +* +* \param cbCnt +* This is the size of the callback array, or the number of defined clients. +* +* \param epConfig +* This value defines the IPC channel, IPC interrupt number, and the interrupt +* mask for the entire pipe. +* The format of the endPoint configuration +* Bits[31:16] Interrupt Mask +* Bits[15:8 ] IPC interrupt +* Bits[ 7:0 ] IPC channel +* +* \return +* void +* +*******************************************************************************/ +void Cy_IPC_PIPE_Init(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray, uint32_t cbCnt, uint32_t epConfig) +{ + cy_stc_ipc_pipe_ep_t * endPoint; + + endPoint = &cy_ipc_pipe_epArray[epAddr]; + + /* Extract the channel, interrupt and interrupt mask */ + endPoint->ipcChan = (epConfig & CY_IPC_PIPE_CFG_CHAN_MASK) >> CY_IPC_PIPE_CFG_CHAN_SHIFT ; + endPoint->intrChan = (epConfig & CY_IPC_PIPE_CFG_INTR_MASK) >> CY_IPC_PIPE_CFG_INTR_SHIFT; + endPoint->pipeIntMask = (epConfig & CY_IPC_PIPE_CFG_IMASK_MASK) >> CY_IPC_PIPE_CFG_IMASK_SHIFT; + + /* Assign IPC channel to this endpoint */ + endPoint->ipcPtr = Cy_IPC_DRV_GetIpcBaseAddress (endPoint->ipcChan); + + /* Assign interrupt structure to endpoint and Initialize the interrupt mask for this endpoint */ + endPoint->ipcIntrPtr = Cy_IPC_DRV_GetIntrBaseAddr(endPoint->intrChan); + endPoint->ipcIntrPtr->INTR_MASK = endPoint->pipeIntMask | (endPoint->pipeIntMask << 16); /* Only allow notify and release interrupts */ + /* from endpoints in this pipe. */ + /* Save the Client count and the callback array pointer */ + endPoint->clientCount = cbCnt; + endPoint->callbackArray = cbArray; + endPoint->busy = CY_IPC_PIPE_ENDPOINT_NOTBUSY; +} + + +/******************************************************************************* +* Function Name: Cy_IPC_PIPE_SendMessage +****************************************************************************//** +* +* This function is used to send a message from one endpoint to another. It +* generates an interrupt on the endpoint that receives the message and a +* release interrupt to the sender to acknowledge the message has been processed. +* +* \param toAddr +* This parameter is the address (or index in the array of endpoint structures) +* of the endpoint to which you are sending the message. +* +* \param fromAddr +* This parameter is the address (or index in the array of endpoint structures) +* of the endpoint to which the message is being sent. +* +* \param msgPtr +* Pointer to the message structure to be sent. +* +* \param callBackPtr +* Pointer to the Release callback function. +* +* +* \return +* CY_IPC_PIPE_SUCCESS: Message was sent to the other end of the pipe +* CY_IPC_PIPE_BAD_HANDLE: The handle provided for the pipe was not valid +* CY_IPC_PIPE_SEND_BUSY: The pipe is already busy sending a message +* CY_IPC_PIPE_DIR_ERROR: Tried to send on the "to" end of a unidirectional pipe +*******************************************************************************/ +cy_en_ipc_pipe_status_t Cy_IPC_PIPE_SendMessage(uint32_t toAddr, uint32_t fromAddr, void * msgPtr, cy_ipc_pipe_relcallback_ptr_t callBackPtr) +{ + cy_en_ipc_pipe_status_t returnStatus; + uint32_t releaseMask; + uint32_t notifyMask; + + cy_stc_ipc_pipe_ep_t * fromEp; + cy_stc_ipc_pipe_ep_t * toEp; + + toEp = &(cy_ipc_pipe_epArray[toAddr]); + fromEp = &cy_ipc_pipe_epArray[fromAddr]; + + /* Check if IPC channel valid */ + if( toEp->ipcPtr != (void *)0u) + { + if(fromEp->busy == CY_IPC_PIPE_ENDPOINT_NOTBUSY) + { + /* Attempt to acquire the channel */ + if( CY_IPC_DRV_SUCCESS == Cy_IPC_DRV_LockAcquire(toEp->ipcPtr) ) + { + /* Create the release mask for the "fromAddr" channel's interrupt channel */ + releaseMask = (0x0001 << fromEp->intrChan); + + * (uint32_t *) msgPtr &= ~(CY_IPC_PIPE_MSG_RELEASE_MASK); /* Mask out the release mask area */ + releaseMask = ((releaseMask << CY_IPC_PIPE_MSG_RELEASE_SHIFT) & CY_IPC_PIPE_MSG_RELEASE_MASK); /* shift into position */ + * (uint32_t *) msgPtr |= releaseMask; /* OR in the release mask */ + + /* If the channel was acquired, write the message. */ + toEp->ipcPtr->DATA = (uint32_t) msgPtr; + + /* The last thing to do is create the notify event that causes the interrupt */ + /* Create the notify mask for the "toAddr" channel's interrupt channel */ + notifyMask = (0x0001 << toEp->intrChan); + + fromEp->busy = CY_IPC_PIPE_ENDPOINT_BUSY; /* Set the busy flag. The ISR clears this after the release */ + + /* Setup release callback function */ + fromEp->releaseCallbackPtr = callBackPtr; /* Set the callback function */ + + /* Cause notify event/interrupt */ + toEp->ipcPtr->NOTIFY = (IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk & notifyMask); + returnStatus = CY_IPC_PIPE_SUCCESS; + } + else + { + /* Channel was already acquired, return Error */ + returnStatus = CY_IPC_PIPE_ERROR_SEND_BUSY; + } + } + else + { + /* Channel may not be acquired, but the release interrupt has not executed yet */ + returnStatus = CY_IPC_PIPE_ERROR_SEND_BUSY; + } + } + else + { + /* Null pipe handle. */ + returnStatus = CY_IPC_PIPE_ERROR_BAD_HANDLE; + } + return(returnStatus); +} + + + +/******************************************************************************* +* Function Name: Cy_IPC_PIPE_RegisterCallback +****************************************************************************//** +* +* This function registers a callback when a message is received on a pipe. +* The client_ID is the same as the index of the callback function array. The callback +* may be a real function pointer or NULL if no callback is required. +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint to which you want to add callback functions. +* +* \param callBackPtr +* Pointer to the callback function called when the endpoint has received a message. +* +* \param clientId +* The index in the callback array (Client ID) where the function pointer is saved. +* +* +* \return +* CY_IPC_PIPE_SUCCESS: Callback registered successfully +* CY_IPC_PIPE_ERROR_BAD_CLIENT: Client ID out of range, callback not registered. +*******************************************************************************/ +cy_en_ipc_pipe_status_t Cy_IPC_PIPE_RegisterCallback(uint32_t epAddr, cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId) +{ + cy_en_ipc_pipe_status_t returnStatus; /* Return Status */ + cy_stc_ipc_pipe_ep_t * thisEp; + + thisEp = &cy_ipc_pipe_epArray[epAddr]; + + /* Check if clientId is between 0 and less than client count */ + if(clientId <= thisEp->clientCount) + { + /* Copy callback function into callback function pointer array */ + thisEp->callbackArray[clientId] = callBackPtr; + returnStatus = CY_IPC_PIPE_SUCCESS; + } + else + { + returnStatus = CY_IPC_PIPE_ERROR_BAD_CLIENT; + } + return(returnStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_PIPE_RegisterRecvCallbackRel +****************************************************************************//** +* +* This function registers a default callback if a release interrupt +* is generated but the current release callback function is null. +* +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint to which you want to add a release callback function. +* +* \param callBackPtr +* Pointer to the callback executed when the endpoint has received a message. +* +* \return +* None +*******************************************************************************/ +void Cy_IPC_PIPE_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr) +{ + cy_stc_ipc_pipe_ep_t * endPoint; + + endPoint = &cy_ipc_pipe_epArray[epAddr]; + /* Copy callback function into callback function pointer array */ + endPoint->defaultReleaseCbPtr = callBackPtr; +} + +/******************************************************************************* +* Function Name: Cy_IPC_PIPE_ExecCallback +****************************************************************************//** +* +* This function is called by the ISR for a given pipe endpoint to dispatch +* the appropriate callback function based on the client ID for that endpoint. +* +* \param endPoint +* Pointer to endpoint structure. +* +* \return +* None +*******************************************************************************/ +void Cy_IPC_PIPE_ExecCallback(cy_stc_ipc_pipe_ep_t * endPoint) +{ + uint32_t * msgPtr = (void *)0uL; + uint32_t clientID; + uint32_t shadowIntr; + uint32_t releaseMask = (uint32_t)0; + cy_ipc_pipe_callback_ptr_t callbackPtr; + + /* Check to make sure the interrupt was a notify interrupt */ + shadowIntr = endPoint->ipcIntrPtr->INTR_MASKED; + if( 0 != (shadowIntr & IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk)) + { + /* Clear the notify interrupt. */ + endPoint->ipcIntrPtr->INTR = (shadowIntr & IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk); + + if( CY_IPC_DRV_LOCKED == Cy_IPC_DRV_GetLockStatus (endPoint->ipcPtr) ) + { + /* Extract Client ID */ + if( CY_IPC_DRV_SUCCESS == Cy_IPC_DRV_ReadMsgPtr (endPoint->ipcPtr, (void **)&msgPtr)) + { + /* Get release mask */ + releaseMask = (uint32_t)((*msgPtr & CY_IPC_PIPE_MSG_RELEASE_MASK) >> CY_IPC_PIPE_MSG_RELEASE_SHIFT); + + clientID = *msgPtr & CY_IPC_PIPE_MSG_CLIENT_MASK; + /* Make sure client ID is within valid range */ + if(endPoint->clientCount > clientID) + { + callbackPtr = endPoint->callbackArray[clientID]; /* Get the callback function */ + if(callbackPtr != (void *)0) + { + callbackPtr(msgPtr); /* Call the function pointer for "clientID" */ + } + } + } + /* Must always release the IPC channel */ + Cy_IPC_DRV_Release (endPoint->ipcPtr, releaseMask); + } + } + /* Check to make sure the interrupt was a release interrupt */ + if( 0 != (shadowIntr & IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk)) /* Check for a Release interrupt */ + { + /* Clear the release callback function */ + endPoint->ipcIntrPtr->INTR = (shadowIntr & IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk); + + if(endPoint->releaseCallbackPtr != (void *)0) + { + endPoint->releaseCallbackPtr(); + + /* Clear the pointer after it was called */ + endPoint->releaseCallbackPtr = (void *)0; + } + else if( endPoint->defaultReleaseCbPtr != (void *)0) + { + endPoint->defaultReleaseCbPtr(); + } + /* Clear the busy flag when release is detected */ + endPoint->busy = CY_IPC_PIPE_ENDPOINT_NOTBUSY; + } + + (void)endPoint->ipcIntrPtr->INTR; +} + + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_pipe.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_pipe.h new file mode 100644 index 0000000000..d7368903cf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/ipc/cy_ipc_pipe.h @@ -0,0 +1,191 @@ +/***************************************************************************//** +* \file +* \version 1.0 +* +* Description: +* IPC Pipe Driver - This header file contains all the function prototypes, +* structure definitions, pipe constants, and pipe endpoint address definitions. +* +* Warning: The API for the pipe level functions are preliminary and may change +* prior to release. +* +******************************************************************************** +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifndef CY_IPC_PIPE_H +#define CY_IPC_PIPE_H + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "syslib/cy_syslib.h" +#include "cy_ipc_drv.h" + + +/* + * This section defines the system level constants required to define + * callback arrays for the Cypress pipe and the user pipe. These defines + * are used for both the max callback count and maximum clients. +*/ + +typedef void (* cy_ipc_pipe_callback_ptr_t)(uint32_t * msgPtr); /**< Typedef for pipe callback function pointer */ +typedef void (* cy_ipc_pipe_relcallback_ptr_t)(void); /**< Typedef for a pipe release callback function pointer */ +typedef void (** cy_ipc_pipe_callback_array_ptr_t)(uint32_t * msgPtr); /**< Typedef for array of callback function pointers */ + + +/** +* \addtogroup group_ipc_macro +* \{ +*/ + +/* + * The System pipe address is what is used to send a message to one of the + * endpoints of a pipe. Currently the Cypress pipe and the User pipe + * are supported. For parts with extra IPC channels users may create + * their own custom pipes and create their own pipe addresses. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ +#define CY_IPC_PIPE_CFG_IMASK_SHIFT (16UL) /**< Interrupt mask shift value for Pipe functions */ +#define CY_IPC_PIPE_CFG_IMASK_MASK (0xFFFF0000UL) /**< Interrupt mask for endpoint address */ +#define CY_IPC_PIPE_CFG_INTR_SHIFT (8UL) /**< Interrupt shift Pipe functions */ +#define CY_IPC_PIPE_CFG_INTR_MASK (0x0000FF00UL) /**< Interrupt mask for endpoint address */ +#define CY_IPC_PIPE_CFG_CHAN_SHIFT (0UL) /**< Interrupt shift Pipe functions */ +#define CY_IPC_PIPE_CFG_CHAN_MASK (0x000000FFUL) /**< Pipe channel address for endpoint address */ + + + +#define CY_IPC_PIPE_MSG_CLIENT_MASK (0x000000FFul) /**< Client mask for first word of Pipe message */ +#define CY_IPC_PIPE_MSG_USR_MASK (0x0000FF00ul) /**< User data mask for first word of Pipe message */ +#define CY_IPC_PIPE_MSG_RELEASE_MASK (0xFFFF0000ul) /**< Mask for message release mask */ +#define CY_IPC_PIPE_MSG_RELEASE_SHIFT (16UL) /**< Shift require to line up mask to LSb */ + +#define CY_IPC_PIPE_ENDPOINT_BUSY (1UL) /**< Use to set the busy flag when waiting for a release interrupt */ +#define CY_IPC_PIPE_ENDPOINT_NOTBUSY (0UL) /**< Denotes that a release interrupt is not pending */ + +/** \} group_ipc_macro */ + +/** +* \addtogroup group_ipc_data_structures +* \{ +*/ + +/* + * This is the definition of a pipe endpoint. There is one endpoint structure for each CPU in + * a pipe. It contains all the information to process a message sent from one of the other + * CPUs in the pipe. + */ +/** +* This is the definition of a pipe endpoint. There is one endpoint structure for each CPU in +* a pipe. It contains all the information to process a message send from one of the other +* CPUs in the pipe. +*/ +typedef struct +{ + uint32_t ipcChan; /**< IPC channel number used for this endpoint to receive messages */ + uint32_t intrChan; /**< IPC interrupt channel number used for this endpoint to receive interrupts */ + uint32_t pipeIntMask; /**< Release/Notify interrupt mask that includes all endpoints on pipe */ + IPC_STRUCT_Type * ipcPtr; /**< Pointer to receive IPC channel ( If ptr == NULL, cannot receive ) */ + IPC_INTR_STRUCT_Type * ipcIntrPtr; /**< Pointer to IPC interrupt, needed to clear the interrupt */ + uint32_t busy; /**< Endpoint busy flag. If sent no messages can be sent from this endpoint */ + uint32_t clientCount; /**< Client count and size of MsgCallback array */ + cy_ipc_pipe_callback_array_ptr_t callbackArray; /**< Pointer to array of callback functions, one for each Client */ + cy_ipc_pipe_relcallback_ptr_t releaseCallbackPtr; /**< Pointer to release callback function */ + cy_ipc_pipe_relcallback_ptr_t defaultReleaseCbPtr; /**< Pointer to default release callback function */ +} cy_stc_ipc_pipe_ep_t; + +/** \} goup_ipc_data_structures */ + +/** +* \addtogroup group_ipc_macro +* \{ +*/ +/* Status and error types */ +#define CY_IPC_PIPE_RTN 0x0200ul /**< Software PDL driver ID for IPC pipe functions */ +#define CY_IPC_PIPE_ID_INFO (uint32_t)( CY_IPC_ID_INFO | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function status codes */ +#define CY_IPC_PIPE_ID_WARNING (uint32_t)( CY_IPC_ID_WARNING | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function warning return values */ +#define CY_IPC_PIPE_ID_ERROR (uint32_t)( CY_IPC_ID_ERROR | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function error return values */ + + +/**< Return constants for IPC pipe functions. */ +typedef enum +{ + CY_IPC_PIPE_SUCCESS =(uint32_t)0x00u, /**< Pipe API return for no error */ + CY_IPC_PIPE_ERROR_NO_IPC =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 1ul), /**< Pipe API return for no valid IPC channel */ + CY_IPC_PIPE_ERROR_NO_INTR =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 2ul), /**< Pipe API return for no valid interrupt */ + CY_IPC_PIPE_ERROR_BAD_PRIORITY =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 3ul), /**< Pipe API return for bad priority parameter */ + CY_IPC_PIPE_ERROR_BAD_HANDLE =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 4ul), /**< Pipe API return for bad pipe handle */ + CY_IPC_PIPE_ERROR_BAD_ID =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 5ul), /**< Pipe API return for bad pipe ID */ + CY_IPC_PIPE_ERROR_DIR_ERROR =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 6ul), /**< Pipe API return for invalid direction (Not used at this time) */ + CY_IPC_PIPE_ERROR_SEND_BUSY =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 7ul), /**< Pipe API return for pipe is currently busy */ + CY_IPC_PIPE_ERROR_NO_MESSAGE =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 8ul), /**< Pipe API return for no message indicated */ + CY_IPC_PIPE_ERROR_BAD_CPU =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 9ul), /**< Pipe API return for invalid CPU value */ + CY_IPC_PIPE_ERROR_BAD_CLIENT =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 10ul) /**< Pipe API return for client out of range */ +} cy_en_ipc_pipe_status_t; + +/** \} group_ipc_macro */ + + + +/** +* \addtogroup group_ipc_data_structures +* \{ +*/ + + + +/** \cond +* NOTE: This doxygen comment must be placed before some code entity, or else +* it will belong to a random entity that follows it, e.g. group_ipc_functions +* +* Client identifier for a message. +* For a given pipe, traffic across the pipe can be multiplexed with multiple +* senders on one end and multiple receivers on the other end. +* +* The first 32-bit word of the message is used to identify the client that owns +* the message. +* +* The upper 16 bits are the client ID. +* +* The lower 16 bits are for use by the client in any way desired. +* +* The lower 16 bits are preserved (not modified) and not interpreted in any way. +* \endcond +*/ + +/** \} group_ipc_data_structures */ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +/** +* \addtogroup group_ipc_functions +* \{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif +/* The API for the pipes level functions are preliminary and may change prior to release */ +void Cy_IPC_PIPE_Init(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray, uint32_t cbCnt, uint32_t epConfig); +cy_en_ipc_pipe_status_t Cy_IPC_PIPE_SendMessage(uint32_t toAddr, uint32_t fromAddr, void *msg_ptr, cy_ipc_pipe_relcallback_ptr_t callBack_ptr); +cy_en_ipc_pipe_status_t Cy_IPC_PIPE_RegisterCallback(uint32_t epAddr, cy_ipc_pipe_callback_ptr_t callBack_ptr, uint32_t clientID); +void Cy_IPC_PIPE_ExecCallback(cy_stc_ipc_pipe_ep_t * endPoint); +void Cy_IPC_PIPE_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBack_ptr); +void Cy_IPC_PIPE_Config(cy_stc_ipc_pipe_ep_t * theEpArray); +#ifdef __cplusplus +} +#endif + +/** \} group_ipc_functions */ + +#endif /* _CY_IPC_PIPE_H_ */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/profile/cy_profile.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/profile/cy_profile.c new file mode 100644 index 0000000000..80bc3f02b6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/profile/cy_profile.c @@ -0,0 +1,374 @@ +/***************************************************************************//** +* \file cy_profile.c +* \version 1.0 +* +* Provides an API implementation of the energy profiler (EP) driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_profile.h" +#include + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/* # of elements in an array */ +#define CY_N_ELMTS(a) (sizeof(a)/sizeof((a)[0])) + +static uint32_t Cy_Profile_IsPtrValid(const cy_stc_profile_ctr_ptr_t ctrAddr); + +/* control and status information for each counter */ +static cy_stc_profile_ctr_t cy_ep_ctrs[PROFILE_PRFL_CNT_NR]; + + +/* ========================================================================== */ +/* ===================== LOCAL FUNCTIONS SECTION ====================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_Profile_IsPtrValid +****************************************************************************//** +* +* Local utility function: reports (1) whether or not a given pointer points into +* the cy_ep_ctrs[] array, and (2) whether the counter has been assigned. +* +* \param ctrAddr The handle to (address of) the assigned counter +* +* \return CY_PROFILE_SUCCESS, or CY_PROFILE_BAD_PARAM for invalid ctrAddr or counter not +* in use. +* +*******************************************************************************/ +static uint32_t Cy_Profile_IsPtrValid(const cy_stc_profile_ctr_ptr_t ctrAddr) +{ + uint32_t retVal = CY_PROFILE_BAD_PARAM; + /* check for valid ctrAddr */ + uint32_t p_epCtrs = (uint32_t)cy_ep_ctrs; + if ((p_epCtrs <= (uint32_t)ctrAddr) && ((uint32_t)ctrAddr < (p_epCtrs + (uint32_t)sizeof(cy_ep_ctrs)))) + { + if (ctrAddr->used != 0u) /* check for counter being used */ + { + retVal = CY_PROFILE_SUCCESS; + } + } + return (retVal); +} + + +/* ========================================================================== */ +/* ==================== INTERRUPT FUNCTION SECTION ==================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_Profile_ISR +****************************************************************************//** +* +* EP interrupt handler: Increments the overflow member of the counter structure, +* for each counter that is in use and has an overflow. +* +* This handler is not configured or used automatically. You must configure the +* interrupt handler for the EP, using Cy_SysInt_Init(). Typically you configure +* the system to use \ref Cy_Profile_ISR() as the overflow interrupt handler. You +* can provide a custom interrupt handler to perform additional operations if +* required. Your handler can call \ref Cy_Profile_ISR() to handle counter +* overflow. +* +*******************************************************************************/ +void Cy_Profile_ISR(void) +{ + uint32_t ctr; + + /* Grab a copy of the overflow register. Each bit in the register indicates + whether or not the respective counter has overflowed. */ + uint32_t ovflowBits = _FLD2VAL(PROFILE_INTR_MASKED_CNT_OVFLW, PROFILE->INTR_MASKED); + + PROFILE->INTR = ovflowBits; /* clear the sources of the interrupts */ + + /* scan through the overflow bits, i.e., for each counter */ + for (ctr = 0UL; (ctr < (uint32_t)(PROFILE_PRFL_CNT_NR)) && (ovflowBits != 0UL); ctr++) + { + /* Increment the overflow bit only if the counter is being used. + (Which should always be the case.) */ + if (((ovflowBits & 1UL) != 0UL) && (cy_ep_ctrs[ctr].used != 0u)) + { + cy_ep_ctrs[ctr].overflow++; + } + ovflowBits >>= 1; /* check the next bit, by shifting it into the LS position */ + } +} + + +/* ========================================================================== */ +/* ================== GENERAL EP FUNCTIONS SECTION ==================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_Profile_StartProfiling +****************************************************************************//** +* +* Starts profiling. +* +* \note Before calling this function, the user must enable the EP interrupt. +*******************************************************************************/ +void Cy_Profile_StartProfiling(void) +{ + uint32_t i; + + /* clear all of the counter array overflow variables */ + for (i = 0UL; i < CY_N_ELMTS(cy_ep_ctrs); cy_ep_ctrs[i++].overflow = 0UL){} + /* send the hardware command */ + PROFILE->CMD = CY_PROFILE_START_TR; +} + + +/* ========================================================================== */ +/* =================== COUNTER FUNCTIONS SECTION ====================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_Profile_ClearConfiguration +****************************************************************************//** +* +* Clears all counter configuration and sets all counters and overflow counters to 0. +* Calls Cy_Profile_ClearCounters() to clear counter registers. +* +*******************************************************************************/ +void Cy_Profile_ClearConfiguration(void) +{ + (void)memset((void *)cy_ep_ctrs, 0, sizeof(cy_ep_ctrs)); + Cy_Profile_ClearCounters(); +} + +/******************************************************************************* +* Function Name: Cy_Profile_ConfigureCounter +****************************************************************************//** +* +* Assigns a given monitor source to a counter, and loads the CTL register +* bitfields of an assigned counter. +* +* \param monitor The monitor source # +* +* \param duration Events are monitored (0), or duration is monitored (1) +* +* \param refClk The reference clock to use; see \ref cy_en_profile_ref_clk_t. +* In general, it is recommended to use CY_PROFILE_CLK_HF to maximize resolution. +* +* \param weight Weighting factor for the counter value +* +* \return A pointer to the counter data structure. NULL if no counter is +* available. +* +* \note The counter is not enabled by this function. See functions +* \ref Cy_Profile_EnableCounter() and \ref Cy_Profile_DisableCounter(). See the +* Technical Reference Manual chapter on the EP for reference clock considerations. +* +*******************************************************************************/ +cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, uint32_t duration, + cy_en_profile_ref_clk_t refClk, uint32_t weight) +{ + cy_stc_profile_ctr_ptr_t retVal = NULL; /* error value if no counter is available */ + volatile uint8_t i; + /* scan through the counters for an unused one */ + for (i = 0u; (cy_ep_ctrs[i].used != 0u) && (i < CY_N_ELMTS(cy_ep_ctrs)); i++){} + if (i < CY_N_ELMTS(cy_ep_ctrs)) + { /* found one, fill in its data structure */ + cy_ep_ctrs[i].ctrNum = i; + cy_ep_ctrs[i].used = 1u; + cy_ep_ctrs[i].cntAddr = (PROFILE_CNT_STRUCT_Type *)&(PROFILE->CNT_STRUCT[i]); + cy_ep_ctrs[i].ctlRegVals.cntDuration = (uint8_t)duration; + cy_ep_ctrs[i].ctlRegVals.refClkSel = refClk; + cy_ep_ctrs[i].ctlRegVals.monSel = monitor; + cy_ep_ctrs[i].overflow = 0UL; + cy_ep_ctrs[i].weight = weight; + /* pass back the handle to (address of) the counter data structure */ + retVal = &cy_ep_ctrs[i]; + + /* Load the CTL register bitfields of the assigned counter. */ + retVal->cntAddr->CTL = + _VAL2FLD(PROFILE_CNT_STRUCT_CTL_CNT_DURATION, retVal->ctlRegVals.cntDuration) | + _VAL2FLD(PROFILE_CNT_STRUCT_CTL_REF_CLK_SEL, retVal->ctlRegVals.refClkSel) | + _VAL2FLD(PROFILE_CNT_STRUCT_CTL_MON_SEL, retVal->ctlRegVals.monSel); + + } + return (retVal); +} + +/******************************************************************************* +* Function Name: Cy_Profile_FreeCounter +****************************************************************************//** +* +* Frees up a counter from a previously-assigned monitor source. +* \ref Cy_Profile_ConfigureCounter() must have been called for this counter before +* calling this function. +* +* \param ctrAddr The handle to (address of) the assigned counter, which is +* obtained by a call to \ref Cy_Profile_ConfigureCounter() +* +* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. +* +* \note The counter is not disabled by this function. See functions +* \ref Cy_Profile_EnableCounter() and \ref Cy_Profile_DisableCounter(). +*******************************************************************************/ +uint32_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr) +{ + uint32_t retVal = Cy_Profile_IsPtrValid(ctrAddr); + if (retVal == CY_PROFILE_SUCCESS) + { + ctrAddr->used = 0u; + } + return (retVal); +} + +/******************************************************************************* +* Function Name: Cy_Profile_EnableCounter +****************************************************************************//** +* +* Enables an assigned counter. \ref Cy_Profile_ConfigureCounter() must have been +* called for this counter before calling this function. +* +* \param ctrAddr The handle to (address of) the assigned counter, which is +* obtained by a call to \ref Cy_Profile_ConfigureCounter() +* +* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. +* +*******************************************************************************/ +uint32_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr) +{ + uint32_t retVal = Cy_Profile_IsPtrValid(ctrAddr); + if (retVal == CY_PROFILE_SUCCESS) + { + /* set the ENABLED bit */ + ctrAddr->cntAddr->CTL |= _VAL2FLD(PROFILE_CNT_STRUCT_CTL_ENABLED, 1UL); + /* set the INTR_MASK bit for the counter being used */ + PROFILE->INTR_MASK |= (1UL << (ctrAddr->ctrNum)); + } + return (retVal); +} + +/******************************************************************************* +* Function Name: Cy_Profile_DisableCounter +****************************************************************************//** +* +* Disables an assigned counter. \ref Cy_Profile_ConfigureCounter() must have been +* called for this counter before calling this function. +* +* \param ctrAddr The handle to (address of) the assigned counter, which is +* obtained by a call to \ref Cy_Profile_ConfigureCounter() +* +* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. +* +*******************************************************************************/ +uint32_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAddr) +{ + uint32_t retVal = Cy_Profile_IsPtrValid(ctrAddr); + if (retVal == CY_PROFILE_SUCCESS) + { + /* clear the ENABLED bit */ + ctrAddr->cntAddr->CTL &= ~(_VAL2FLD(PROFILE_CNT_STRUCT_CTL_ENABLED, 1UL)); + /* clear the INTR_MASK bit for the counter being used */ + PROFILE->INTR_MASK &= ~(1UL << (ctrAddr->ctrNum)); + } + return (retVal); +} + + +/* ========================================================================== */ +/* ================== CALCULATION FUNCTIONS SECTION =================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_Profile_GetRawCount +****************************************************************************//** +* +* Reports the count value for a specified counter. +* +* \param ctrAddr the handle to (address of) the assigned counter, which is +* obtained by a call to \ref Cy_Profile_ConfigureCounter() +* +* \param result the address to which to write the result +* +* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. +* +*******************************************************************************/ +uint32_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result) +{ + uint32_t retVal = Cy_Profile_IsPtrValid(ctrAddr); + if (retVal == CY_PROFILE_SUCCESS) + { + /* read the counter control register, and the counter current value */ + ctrAddr->ctlReg = ctrAddr->cntAddr->CTL; + ctrAddr->cntReg = ctrAddr->cntAddr->CNT; + + /* report the count with overflow */ + *result = ((uint64_t)(ctrAddr->overflow) << 32) | (uint64_t)(ctrAddr->cntReg); + } + return (retVal); +} + +/******************************************************************************* +* Function Name: Cy_Profile_GetWeightedCount +****************************************************************************//** +* +* Reports the count value for a specified counter, multiplied by the weight +* factor set in \ref Cy_Profile_ConfigureCounter() for that counter. +* +* \param ctrAddr the handle to (address of) the assigned counter, which is +* obtained by a call to \ref Cy_Profile_ConfigureCounter() +* +* \param result the address to which to write the result +* +* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. +* +*******************************************************************************/ +uint32_t Cy_Profile_GetWeightedCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result) +{ + uint64_t temp; + uint32_t retVal = Cy_Profile_GetRawCount(ctrAddr, &temp); + if (retVal == CY_PROFILE_SUCCESS) + { + /* calculate weighted count */ + *result = temp * (uint64_t)(ctrAddr->weight); + } + return (retVal); +} + +/******************************************************************************* +* Function Name: Cy_Profile_GetSumWeightedCounts +****************************************************************************//** +* +* Calls \ref Cy_Profile_GetWeightedCount() for all specified counters. Reports the sum +* across all valid counters. +* +* \param ptrsArray array of handles to (addresses of) assigned counters +* +* \param numCounters number of scanned elements in ptrsArray[] +* +* \return The sum +* +*******************************************************************************/ +uint64_t Cy_Profile_GetSumWeightedCounts(const cy_stc_profile_ctr_ptr_t ptrsArray[], + uint32_t numCounters) +{ + uint64_t daSum = (uint64_t)0ul; + uint64_t num; + uint32_t i; + + for (i = 0ul; i < numCounters; i++) + { + /* ignore error reported by Ep_GetWeightedCount() */ + if (Cy_Profile_GetWeightedCount(ptrsArray[i], &num) == CY_PROFILE_SUCCESS) + { + daSum += num; + } + } + + return (daSum); +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/profile/cy_profile.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/profile/cy_profile.h new file mode 100644 index 0000000000..0f9be7375a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/profile/cy_profile.h @@ -0,0 +1,540 @@ +/***************************************************************************//** +* \file cy_profile.h +* \version 1.0 +* +* Provides an API declaration of the energy profiler (EP) driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_energy_profiler Energy Profiler (Profile) +* \{ +* +* The energy profiler (EP) driver contains an API for configuring and using the +* energy profiler hardware. The profiler enables measurement of the relative +* amount of energy consumed by particular peripherals. Traditional energy +* profilers correlate energy consumption to the program counter, which helps you +* understand when power is consumed. The EP provides additional insight into the +* device so you can identify an asynchronous activity that causes energy +* consumption. In other words, the EP helps you understand where power is consumed. +* +* The EP does not measure or report actual energy consumption. It measures either +* clock cycles or the number of events that have occurred in the profiling window. +* To derive relative energy consumption for each source, you can multiply the +* absolute count (clock cycles or events) for that source by a coefficient. +* +* Many of the sources available for monitoring are asynchronous operations where +* the cause of energy consumption may be difficult to identify using external hardware. +* +* \section group_profile_configuration Configuration Considerations +* +* There is no PSoC Creator component for this peripheral. To use the profiler you +* include the header file and configure the counters by writing code and calling +* the Profiler API functions. +* +* At the highest level, you perform these tasks: +* - Initialize the profiling block +* - Set up the profiling interrupt +* - Configure, initialize, and enable the counters +* - Start and stop profiling +* - Get the results +* - Exit gracefully +* +* The EP manages a set of counters. For each counter you use, you assign the source +* you want monitored, a reference clock, and a coefficient used to calculate results. +* You can also get the raw count for any counter. +* +* Each counter is a 32-bit register that counts either a number of clock cycles, +* or a number of events. It is possible to overflow the 32-bit register. The +* firmware implements a 32-bit overflow counter. Combined with the 32-bit register, +* this gives you a 64-bit counter for each monitored source. The profiler generates +* an interrupt when an overflow occurs. You must configure the interrupt handler +* using Cy_SysInt_Init(). You can use Cy_Profile_ISR() as the interrupt handler. It +* increments the overflow counter for each profiling counter that is in use. +* +* See notes on individual function definitions. +* +* \section group_profile_more_information More Information +* +* See the EP chapter of the device technical reference manual (TRM). +* +* \section group_profile_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
10.1RThe value of an expression of integer type shall not be implicitly converted to a different, underlying type +* if the expression is complex.Using a Cypress defined macro to access memory mapped objects. +* Checking that a function pointer points to within the correct memory region. +* Calculating address of register structure.
10.5RIf the bitwise operators ~ and << are applied to an operand of underlying type uint8 or uint16, the result +* shall be immediately cast to the underlying type of the operand.Using a Cypress-defined macro to access memory-mapped objects.
11.5RDangerous pointer cast results in loss of volatile qualification.Using a Cypress-defined macro to access memory-mapped objects.
12.4RRight hand operand of '&&' or '||' is an expression with possible side effects.Function-like macros are used to achieve more efficient code.
12.7RBitwise operator applied to signed underlying type.Using a Cypress-defined macro to access memory-mapped objects.
16.7AA pointer parameter can be of type 'pointer to const'.The pointer is cast for comparison purposes and thus can't be a const.
19.7AA function shall be used in preference to a function-like macro.Function-like macros are used to achieve more efficient code.
+* +* \section group_profile_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_profile_macro Macro +* \{ +* \defgroup group_profile_macro_return Function return values +* \} +* \defgroup group_profile_functions Functions +* \{ +* \defgroup group_profile_functions_interrupt Interrupt Functions +* \defgroup group_profile_functions_general General Functions +* \defgroup group_profile_functions_counter Counter Functions +* \defgroup group_profile_functions_calculation Calculation Functions +* \} +* \defgroup group_profile_data_structures Data Structures +* \defgroup group_profile_enums Enumerated Types +*/ + +#if !defined(CY_PROFILE_H) +#define CY_PROFILE_H + +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" +#include + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** \addtogroup group_profile_macro +* \{ +*/ + +/** Driver major version */ +#define CY_PROFILE_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_PROFILE_DRV_VERSION_MINOR 0 + +/** Start profiling command for the CMD register */ +#define CY_PROFILE_START_TR 1UL + +/** Stop profiling command for the CMD register */ +#define CY_PROFILE_STOP_TR 2UL + +/** Command to clear all counter registers to 0 */ +#define CY_PROFILE_CLR_ALL_CNT 0x100UL + +/** +* \addtogroup group_profile_returns +* \{ +* Specifies return values meaning +*/ +/** Command completed with no errors */ +#define CY_PROFILE_SUCCESS 0ul +/** Invalid function input parameter */ +#define CY_PROFILE_BAD_PARAM 1ul +/** \} group_profile_returns */ + +/** \} group_profile_macro */ + + +/** +* \addtogroup group_profile_enums +* \{ +*/ + +/** +* The possible values for CTR register, REF_CLK_SEL bitfield. See the +* technical reference manual (TRM) for reference clock considerations. +*/ +typedef enum +{ + CY_PROFILE_CLK_TIMER = 0, /**< See SRSS register CLK_TIMER_CTL.TIMER_SEL */ + CY_PROFILE_CLK_IMO = 1, /**< Internal main oscillator */ + CY_PROFILE_CLK_ECO = 2, /**< External crystal oscillator */ + CY_PROFILE_CLK_LF = 3, /**< See SRSS register CLK_SELECT.LFCLK_SEL */ + CY_PROFILE_CLK_HF = 4, /**< See SRSS registers CLK_ROOT_SELECT[0].ROOT_MUX and CLK_ROOT_SELECT[0].ROOT_DIV */ + CY_PROFILE_CLK_PERI = 5, /**< See CPUSS register CM0_CLOCK_CTL.PERI_INT_DIV */ +} cy_en_profile_ref_clk_t; +/** \} group_profile_enums */ + +/** +* \addtogroup group_profile_data_structures +* \{ +*/ + +/** +* EP counter control register structure. For each counter, holds the CTL register fields. +*/ +typedef struct +{ + uint8_t cntDuration; /**< 0 = events are monitored; 1 = duration is monitored */ + cy_en_profile_ref_clk_t refClkSel; /**< The reference clock used by this counter; 3 bits */ + en_ep_mon_sel_t monSel; /**< The monitor signal to be observed by this counter; # bits = PROFILE_CNT_STRUCT_PRFL_MONITOR_NR_LOG2 */ +} cy_stc_profile_ctr_ctl_t; + +/** +* Structure holding all information for an EP counter. +*/ +typedef struct +{ + uint8_t ctrNum; /**< hardware counter # */ + uint8_t used; /**< used 0 = available, 1 = being used */ + cy_stc_profile_ctr_ctl_t ctlRegVals; /**< counter CTL reg bitfield values */ + PROFILE_CNT_STRUCT_Type * cntAddr; /**< base MMIO addr of counter registers */ + uint32_t ctlReg; /**< also includes enabled/disabled status */ + uint32_t cntReg; /**< current counter value */ + uint32_t overflow; /**< this register and cntReg form a 64-bit counter value */ + uint32_t weight; /**< counter weighting factor */ +} cy_stc_profile_ctr_t; +/** +* Pointer to structure holding all information for an EP counter. +*/ +typedef cy_stc_profile_ctr_t * cy_stc_profile_ctr_ptr_t; +/** \} group_profile_data_structures */ + +/** +* \addtogroup group_profile_functions +* \{ +*/ + +/** +* \addtogroup group_profile_functions_interrupt +* \{ +*/ + + +/* ========================================================================== */ +/* ==================== INTERRUPT FUNCTION SECTION ==================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_Profile_ISR +****************************************************************************//** +* +* EP interrupt handler: Increments the overflow member of the counter structure, +* for each counter that is in use and has an overflow. +* +* This handler is not configured or used automatically. You must configure the +* interrupt handler for the EP, using Cy_SysInt_Init(). Typically you configure +* the system to use \ref Cy_Profile_ISR() as the overflow interrupt handler. You +* can provide a custom interrupt handler to perform additional operations if +* required. Your handler can call \ref Cy_Profile_ISR() to handle counter +* overflow. +* +*******************************************************************************/ +void Cy_Profile_ISR(void); +/** \} group_profile_functions_interrupt */ + +/** +* \addtogroup group_profile_functions_general +* \{ +*/ + + +/* ========================================================================== */ +/* ================== GENERAL EP FUNCTIONS SECTION ==================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_Profile_Init +****************************************************************************//** +* +* Turns on the EP for profiling. It must be called once when energy profiling is +* desired. This does not start a profiling session. Use Cy_Profile_StartProfiling() +* to start a profiling session. +* +* \note Before calling this function, the user must configure the EP interrupt +* so that \ref Cy_Profile_ISR() is executed. +*******************************************************************************/ +__STATIC_INLINE void Cy_Profile_Init(void) +{ + PROFILE->CTL = _VAL2FLD(PROFILE_CTL_ENABLED, 1UL/*enabled */) | + _VAL2FLD(PROFILE_CTL_WIN_MODE, 0UL/*start/stop mode*/); + PROFILE->INTR_MASK = 0UL; /* clear all counter interrupt mask bits */ +} + + +/******************************************************************************* +* Function Name: Cy_Profile_DeInit +****************************************************************************//** +* +* Turns off the EP. It should be called when energy profiling is no longer +* desired. +* +* \note When calling this function, the user should consider also unconfiguring +* the EP interrupt. +*******************************************************************************/ +__STATIC_INLINE void Cy_Profile_DeInit(void) +{ + PROFILE->CTL = _VAL2FLD(PROFILE_CTL_ENABLED, 0UL/*disabled */); + PROFILE->INTR_MASK = 0UL; /* clear all counter interrupt mask bits */ +} + +/******************************************************************************* +* Function Name: Cy_Profile_StartProfiling +****************************************************************************//** +* +* Starts profiling. +* +* \note Before calling this function, the user must enable the EP interrupt. +*******************************************************************************/ +void Cy_Profile_StartProfiling(void); + +/******************************************************************************* +* Function Name: Cy_Profile_StopProfiling +****************************************************************************//** +* +* Stops profiling. +* +* \note When calling this function, the user should also disable the EP +* interrupt. +*******************************************************************************/ +__STATIC_INLINE void Cy_Profile_StopProfiling(void) +{ + PROFILE->CMD = CY_PROFILE_STOP_TR; +} + +/******************************************************************************* +* Function Name: Cy_Profile_IsProfiling +****************************************************************************//** +* +* Reports whether or not profiling is active. +* +* \return 0 = profiling is not active; 1 = profiling is active +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_Profile_IsProfiling(void) +{ + return _FLD2VAL(PROFILE_STATUS_WIN_ACTIVE, PROFILE->STATUS); +} +/** \} group_profile_functions_general */ + +/** +* \addtogroup group_profile_functions_counter +* \{ +*/ + + +/* ========================================================================== */ +/* =================== COUNTER FUNCTIONS SECTION ====================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_Profile_ClearConfiguration +****************************************************************************//** +* +* Clears all counter configuration and sets all counters and overflow counters to 0. +* Calls Cy_Profile_ClearCounters() to clear counter registers. +* +*******************************************************************************/ +void Cy_Profile_ClearConfiguration(void); + +/******************************************************************************* +* Function Name: Cy_Profile_ClearCounters +****************************************************************************//** +* +* Clears all hardware counters to 0. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_Profile_ClearCounters(void) +{ + PROFILE->CMD = CY_PROFILE_CLR_ALL_CNT; +} + +/******************************************************************************* +* Function Name: Cy_Profile_ConfigureCounter +****************************************************************************//** +* +* Assigns a given monitor source to a counter, and loads the CTL register +* bitfields of an assigned counter. +* +* \param monitor The monitor source # +* +* \param duration Events are monitored (0), or duration is monitored (1) +* +* \param refClk The reference clock to use; see \ref cy_en_profile_ref_clk_t. +* In general, you should use CY_PROFILE_CLK_HF to maximize resolution. +* +* \param weight Weighting factor for the counter value +* +* \return A pointer to the counter data structure. NULL if no counter is +* available. +* +* \note The counter is not enabled by this function. See functions +* \ref Cy_Profile_EnableCounter() and \ref Cy_Profile_DisableCounter(). See the +* technical reference manual (TRM) chapter on the EP for reference clock considerations. +* +*******************************************************************************/ +cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, uint32_t duration, + cy_en_profile_ref_clk_t refClk, uint32_t weight); + +/******************************************************************************* +* Function Name: Cy_Profile_FreeCounter +****************************************************************************//** +* +* Frees up a counter from a previously-assigned monitor source. +* \ref Cy_Profile_ConfigureCounter() must have been called for this counter before +* calling this function. +* +* \param ctrAddr The handle to (address of) the assigned counter, which is +* obtained by a call to \ref Cy_Profile_ConfigureCounter(). +* +* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. +* +* \note The counter is not disabled by this function. See functions +* \ref Cy_Profile_EnableCounter() and \ref Cy_Profile_DisableCounter(). +*******************************************************************************/ +uint32_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr); + +/******************************************************************************* +* Function Name: Cy_Profile_EnableCounter +****************************************************************************//** +* +* Enables an assigned counter. \ref Cy_Profile_ConfigureCounter() must have been +* called for this counter before calling this function. +* +* \param ctrAddr The handle to (address of) the assigned counter, which is +* obtained by a call to \ref Cy_Profile_ConfigureCounter(). +* +* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. +* +*******************************************************************************/ +uint32_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr); + +/******************************************************************************* +* Function Name: Cy_Profile_DisableCounter +****************************************************************************//** +* +* Disables an assigned counter. \ref Cy_Profile_ConfigureCounter() must have been +* called for this counter before calling this function. +* +* \param ctrAddr The handle to (address of) the assigned counter, which is +* obtained by a call to \ref Cy_Profile_ConfigureCounter(). +* +* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. +* +*******************************************************************************/ +uint32_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAddr); +/** \} group_profile_functions_counter */ + +/** +* \addtogroup group_profile_functions_calculation +* \{ +*/ + + +/* ========================================================================== */ +/* ================== CALCULATION FUNCTIONS SECTION =================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_Profile_GetRawCount +****************************************************************************//** +* +* Reports the count value for a specified counter. +* +* \param ctrAddr the handle to (address of) the assigned counter, which is +* obtained by a call to \ref Cy_Profile_ConfigureCounter(). +* +* \param result The address to which to write the result. +* +* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. +* +*******************************************************************************/ +uint32_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result); + +/******************************************************************************* +* Function Name: Cy_Profile_GetWeightedCount +****************************************************************************//** +* +* Reports the count value for a specified counter, multiplied by the weight +* factor set in \ref Cy_Profile_ConfigureCounter() for that counter. +* +* \param ctrAddr the handle to (address of) the assigned counter, which is +* obtained by a call to \ref Cy_Profile_ConfigureCounter(). +* +* \param result The address to which to write the result. +* +* \return \ref CY_PROFILE_SUCCESS, or \ref CY_PROFILE_BAD_PARAM for counter not in use. +* +*******************************************************************************/ +uint32_t Cy_Profile_GetWeightedCount(cy_stc_profile_ctr_ptr_t ctrAddr, uint64_t *result); + +/******************************************************************************* +* Function Name: Cy_Profile_GetSumWeightedCounts +****************************************************************************//** +* +* Calls \ref Cy_Profile_GetWeightedCount() for all specified counters. Reports the sum +* across all valid counters. +* +* \param ptrsArray Array of handles to (addresses of) assigned counters +* +* \param numCounters Number of scanned elements in ptrsArray[] +* +* \return The sum +* +*******************************************************************************/ +uint64_t Cy_Profile_GetSumWeightedCounts(const cy_stc_profile_ctr_ptr_t ptrsArray[], + uint32_t numCounters); +/** \} group_profile_functions_calculation */ + +/** \} group_profile_functions */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* CY_PROFILE_H */ + +/** \} group_profile */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/prot/cy_prot.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/prot/cy_prot.c new file mode 100644 index 0000000000..c719ec7ab1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/prot/cy_prot.c @@ -0,0 +1,1587 @@ +/***************************************************************************//** +* \file cy_prot.c +* \version 1.0 +* +* \brief +* Provides an API implementation of the Protection Unit driver +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_prot.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigBusMaster +****************************************************************************//** +* +* \brief Configures the allowed protection contexts, security (secure/non-secure) +* and privilege level of the bus transaction created by the specified master. +* +* \param busMaster +* Indicates which master needs to be configured. Refer to the CY_PROT_MASTER_X +* defines. +* +* \param privileged +* Boolean to define the privilege level of all subsequent bus transfers. +* True - privileged, False - not privileged. +* Note that this is an inherited value. If not inherited, then this bit will +* be used. +* +* \param secure +* Security setting for the master. True - Secure, False - Not secure. +* +* \param pcMask +* This is a 16 bit value of the allowed contexts, it is an OR'ed (|) field of the +* provided defines in cy_prot.h. For example: (PROT_PC1 | PROT_PC3 | PROT_PC4) +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The function completed successfully +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t regVal; + uint32_t * addrMsCtl = (uint32_t *)(PROT_BASE + (uint32_t)(busMaster << CY_PROT_MSX_CTL_SHIFT)); + + if((uint32_t)(pcMask & CY_PROT_MPU_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + regVal = _VAL2FLD(PROT_SMPU_MS0_CTL_NS, !secure) + | _VAL2FLD(PROT_SMPU_MS0_CTL_P, privileged) + | _VAL2FLD(PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1, pcMask); + *addrMsCtl = regVal; + status = (*addrMsCtl != regVal) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_SetActivePC +****************************************************************************//** +* +* \brief Sets the current/active protection context of the specified bus master. +* +* Allowed PC values are 1-15. If this value is not inherited from another bus +* master, the value set through this function is used. +* +* \param busMaster +* The bus master to configure. Refer to the CY_PROT_MASTER_X defines. +* +* \param pc +* Active protection context of the specified master. Note that only those +* protection contexts allowed by the pcMask will take effect. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The function completed successfully +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + PROT_MPU_Type* addrMpu = (PROT_MPU_Type*)(&PROT->CYMPU[busMaster]); + + if(pc >= (uint32_t)CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1) + { + /* Invalid PC value - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + addrMpu->MS_CTL = _VAL2FLD(PROT_MPU_MS_CTL_PC, pc); + status = (addrMpu->MS_CTL != pc) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_GetActivePC +****************************************************************************//** +* +* \brief Returns the active protection context of a master. +* +* \param busMaster +* The bus master, whose protection context is being read. Refer to the +* CY_PROT_MASTER_X defines. +* +* \return +* Active protection context of the master +* +*******************************************************************************/ +uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster) +{ + PROT_MPU_Type* addrMpu = (PROT_MPU_Type*)(&PROT->CYMPU[busMaster]); + + return ((uint32_t)_FLD2VAL(PROT_MPU_MS_CTL_PC, addrMpu->MS_CTL)); +} + + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigMpuStruct +****************************************************************************//** +* +* \brief This function configures a memory protection unit (MPU) struct with its +* protection attributes. +* +* The protection structs act like the gatekeepers for a master's accesses to +* memory, allowing only the permitted transactions to go through. +* +* \param base +* The base address for the MPU struct being configured. +* +* \param config +* Initialization structure containing all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The MPU struct was configured +* CY_PROT_FAILURE | Configuration failed due to a protection violation +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t addrReg; + uint32_t attReg; + + addrReg = _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE, config->subregions) + | _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT)); + attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) + | (((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_NS, !(config->secure)) + | _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE, config->regionSize); + base->ATT = attReg; + base->ADDR = addrReg; + status = ((base->ADDR != addrReg) || (base->ATT != attReg)) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnableMpuStruct +****************************************************************************//** +* +* \brief Enables the MPU struct, which allows the MPU protection attributes to +* take effect. +* +* \param base +* The base address of the MPU struct being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The MPU struct was enabled +* CY_PROT_FAILURE | The MPU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT |= _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, base->ATT) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisableMpuStruct +****************************************************************************//** +* +* \brief Disbles the MPU struct, which prevents the MPU protection attributes +* from taking effect. +* +* \param base +* The base address of the MPU struct being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The MPU struct was disabled +* CY_PROT_FAILURE | The MPU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT &= ~_VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PROT_MPU_MPU_STRUCT_ATT_ENABLED, base->ATT) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigSmpuMasterStruct +****************************************************************************//** +* +* \brief Configures a Shared Memory Protection Unit (SMPU) master protection +* struct with its protection attributes. +* +* This function configures the master struct governing the corresponding slave +* struct pair. It is a mechanism to protect the slave SMPU struct. Since the +* memory location of the slave struct is known, the address, regionSize and +* subregions of the configuration struct are not applicable. +* +* Note that only the user/privileged write permissions are configurable. The +* read and execute permissions are read-only and cannot be configured. +* +* \param base +* The register base address of the protection struct being configured. +* +* \param config +* Initialization structure with all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | SMPU master struct was successfully configured +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t attReg; + + if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + /* ADDR1 is read only. Only configure ATT1 */ + attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) + | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_NS, !(config->secure)) + | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1, config->pcMask) + /* No region size - read only for master structs */ + | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH, config->pcMatch); + if ((attReg & CY_PROT_SMPU_ATT1_MASK) != attReg) + { + /* Invalid parameter was passed */ + status = CY_PROT_BAD_PARAM; + } + else + { + base->ATT1 = attReg; + status = ((base->ATT1 & CY_PROT_SMPU_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + } + + return status; +} + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigSmpuSlaveStruct +****************************************************************************//** +* +* \brief Configures a Shared Memory Protection Unit (SMPU) slave protection +* struct with its protection attributes. +* +* This function configures the slave struct of an SMPU pair, which can protect +* any memory region in a device from invalid bus master accesses. +* +* \param base +* The register base address of the protection structure being configured. +* +* \param config +* Initialization structure with all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | SMPU slave struct was successfully configured +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t addrReg; + uint32_t attReg; + + if(((uint32_t)config->pcMask & CY_PROT_SMPU_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + addrReg= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE, config->subregions) + | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT)); + attReg= ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) + | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_NS, !(config->secure)) + | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1, config->pcMask) + | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE, config->regionSize) + | _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH, config->pcMatch); + base->ATT0 = attReg; + base->ADDR0 = addrReg; + status = ((base->ADDR0 != addrReg) || ((base->ATT0 & CY_PROT_SMPU_ATT0_MASK) != attReg)) + ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnableSmpuMasterStruct +****************************************************************************//** +* +* \brief Enables the Master SMPU structure. +* +* This is an SMPU master struct enable function. The SMPU protection settings +* will take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Master PU struct was enabled +* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT1 |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisableSmpuMasterStruct +****************************************************************************//** +* +* \brief Disables the Master SMPU structure. +* +* This is an SMPU master struct disable function. The SMPU protection settings +* will seize to take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Master PU struct was disabled +* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT1 &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnableSmpuSlaveStruct +****************************************************************************//** +* +* \brief Enables the Slave SMPU structure. +* +* This is an SMPU slave struct enable function. The SMPU protection settings +* will take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Slave PU struct was enabled +* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT0 |= _VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisableSmpuSlaveStruct +****************************************************************************//** +* +* \brief Disables the Slave SMPU structure. +* +* This is an SMPU slave struct disable function. The SMPU protection settings +* will seize to take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Slave PU struct was disabled +* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT0 &= ~_VAL2FLD(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigPpuProgMasterStruct +****************************************************************************//** +* +* \brief Configures a Programmable Peripheral Protection Unit (PPU PROG) master +* protection struct with its protection attributes. +* +* This function configures the master struct governing the corresponding slave +* struct pair. It is a mechanism to protect the slave PPU PROG struct. Since +* the memory location of the slave struct is known, the address, regionSize and +* subregions of the configuration struct are not applicable. +* +* Note that only the user/privileged write permissions are configurable. The +* read and execute permissions are read-only and cannot be configured. +* +* \param base +* The register base address of the protection struct being configured. +* +* \param config +* Initialization structure with all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | PPU PROG master struct was successfully configured +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t attReg; + + if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + /* ADDR1 is read only. Only configure ATT1 */ + attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) + | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PERI_PPU_PR_ATT1_NS, !(config->secure)) + | _VAL2FLD(PERI_PPU_PR_ATT1_PC_MASK_15_TO_1, config->pcMask) + /* No region size - read only for master structs */ + | _VAL2FLD(PERI_PPU_PR_ATT1_PC_MATCH, config->pcMatch); + if ((attReg & CY_PROT_PPU_PROG_ATT1_MASK) != attReg) + { + /* Invalid parameter was passed */ + status = CY_PROT_BAD_PARAM; + } + else + { + base->ATT1 = attReg; + status = ((base->ATT1 & CY_PROT_PPU_PROG_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + } + + return status; +} + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigPpuProgSlaveStruct +****************************************************************************//** +* +* \brief Configures a Programmable Peripheral Protection Unit (PPU PROG) slave +* protection struct with its protection attributes. +* +* This function configures the slave struct of a PPU PROG pair, which can +* protect any peripheral memory region in a device from invalid bus master +* accesses. +* +* Note that the user/privileged execute accesses are read-only and are always +* enabled. +* +* \param base +* The register base address of the protection structure being configured. +* +* \param config +* Initialization structure with all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | PPU PROG slave struct was successfully configured +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t addrReg; + uint32_t attReg; + + if(((uint32_t)config->pcMask & CY_PROT_PPU_PROG_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + addrReg= _VAL2FLD(PERI_PPU_PR_ADDR0_SUBREGION_DISABLE, config->subregions) + | _VAL2FLD(PERI_PPU_PR_ADDR0_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_SHIFT)); + attReg= ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) + | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PERI_PPU_PR_ATT0_NS, !(config->secure)) + | _VAL2FLD(PERI_PPU_PR_ATT0_PC_MASK_15_TO_1, config->pcMask) + | _VAL2FLD(PERI_PPU_PR_ATT0_REGION_SIZE, config->regionSize) + | _VAL2FLD(PERI_PPU_PR_ATT0_PC_MATCH, config->pcMatch); + if ((attReg & CY_PROT_PPU_PROG_ATT0_MASK) != attReg) + { + /* Invalid parameter was passed */ + status = CY_PROT_BAD_PARAM; + } + else + { + base->ATT0 = attReg; + base->ADDR0 = addrReg; + status = ((base->ADDR0 != addrReg) || ((base->ATT0 & CY_PROT_PPU_PROG_ATT0_MASK) != attReg)) + ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnablePpuProgMasterStruct +****************************************************************************//** +* +* \brief Enables the Master PPU PROG structure. +* +* This is a PPU PROG master struct enable function. The PPU PROG protection +* settings will take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Master PU struct was enabled +* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT1 |= _VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_PPU_PR_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisablePpuProgMasterStruct +****************************************************************************//** +* +* \brief Disables the Master PPU PROG structure. +* +* This is a PPU PROG master struct disable function. The PPU PROG protection +* settings will seize to take effect after successful completion of this +* function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Master PU struct was disabled +* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT1 &= ~_VAL2FLD(PERI_PPU_PR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_PPU_PR_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnablePpuProgSlaveStruct +****************************************************************************//** +* +* \brief Enables the Slave PPU PROG structure. +* +* This is a PPU PROG slave struct enable function. The PPU PROG protection +* settings will take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Slave PU struct was enabled +* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT0 |= _VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisablePpuProgSlaveStruct +****************************************************************************//** +* +* \brief Disables the Slave PPU PROG structure. +* +* This is a PPU PROG slave struct disable function. The PPU PROG protection +* settings will seize to take effect after successful completion of this +* function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Slave PU struct was disabled +* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT0 &= ~_VAL2FLD(PERI_PPU_PR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_PPU_PR_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigPpuFixedGrMasterStruct +****************************************************************************//** +* +* \brief Configures a Fixed Peripheral Group Protection Unit (PPU GR) master +* protection struct with its protection attributes. +* +* This function configures the master struct governing the corresponding slave +* struct pair. It is a mechanism to protect the slave PPU GR struct. Since +* the memory location of the slave struct is known, the address, regionSize and +* subregions of the configuration struct are not applicable. +* +* Note that only the user/privileged write permissions are configurable. The +* read and execute permissions are read-only and cannot be configured. +* +* \param base +* The register base address of the protection struct being configured. +* +* \param config +* Initialization structure with all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | PPU GR master struct was successfully configured +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t attReg; + + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + /* ADDR1 is read only. Only configure ATT1 */ + attReg = (((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)) + | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PERI_PPU_GR_ATT1_NS, !(config->secure)) + | _VAL2FLD(PERI_PPU_GR_ATT1_PC_MASK_15_TO_1, config->pcMask) + /* No region size - read only for master structs */ + | _VAL2FLD(PERI_PPU_GR_ATT1_PC_MATCH, config->pcMatch); + if ((attReg & CY_PROT_PPU_GR_ATT1_MASK) != attReg) + { + /* Invalid parameter was passed */ + status = CY_PROT_BAD_PARAM; + } + else + { + base->ATT1 = attReg; + status = ((base->ATT1 & CY_PROT_PPU_GR_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigPpuFixedGrSlaveStruct +****************************************************************************//** +* +* \brief Configures a Fixed Peripheral Group Protection Unit (PPU GR) slave +* protection struct with its protection attributes. +* +* This function configures the slave struct of a PPU GR pair, which can +* protect an entire peripheral MMIO group from invalid bus master accesses. +* Refer to the device Technical Reference manual for details on peripheral +* MMIO grouping and which peripherals belong to which groups. +* +* Each fixed PPU GR is devoted to a defined MMIO group. Hence the address, +* regionSize and subregions of the configuration struct are not applicable. +* +* Note that the user/privileged execute accesses are read-only and are always +* enabled. +* +* \param base +* The register base address of the protection structure being configured. +* +* \param config +* Initialization structure with all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | PPU GR slave struct was successfully configured +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t attReg; + + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + /* ADDR0 is read only. Only configure ATT0 */ + attReg = (uint32_t)(((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK)) + | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PERI_PPU_GR_ATT0_NS, !(config->secure)) + | _VAL2FLD(PERI_PPU_GR_ATT0_PC_MASK_15_TO_1, config->pcMask) + /* No region size - read only */ + | _VAL2FLD(PERI_PPU_GR_ATT0_PC_MATCH, config->pcMatch); + if ((attReg & CY_PROT_PPU_GR_ATT0_MASK) != attReg) + { + /* Invalid parameter was passed */ + status = CY_PROT_BAD_PARAM; + } + else + { + base->ATT0 = attReg; + status = ((base->ATT0 & CY_PROT_PPU_GR_ATT0_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + } + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnablePpuFixedGrMasterStruct +****************************************************************************//** +* +* \brief Enables the Master PPU GR structure. +* +* This is a PPU GR master struct enable function. The PPU GR protection +* settings will take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Master PU struct was enabled +* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT1 |= _VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_PPU_GR_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisablePpuFixedGrMasterStruct +****************************************************************************//** +* +* \brief Disables the Master PPU GR structure. +* +* This is a PPU GR master struct disable function. The PPU GR protection +* settings will seize to take effect after successful completion of this +* function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Master PU struct was disabled +* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT1 &= ~_VAL2FLD(PERI_PPU_GR_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_PPU_GR_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnablePpuFixedGrSlaveStruct +****************************************************************************//** +* +* \brief Enables the Slave PPU GR structure. +* +* This is a PPU GR slave struct enable function. The PPU GR protection +* settings will take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Slave PU struct was enabled +* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT0 |= _VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_PPU_GR_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisablePpuFixedGrSlaveStruct +****************************************************************************//** +* +* \brief Disables the Slave PPU GR structure. +* +* This is a PPU GR slave struct disable function. The PPU GR protection +* settings will seize to take effect after successful completion of this +* function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Slave PU struct was disabled +* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT0 &= ~_VAL2FLD(PERI_PPU_GR_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_PPU_GR_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigPpuFixedSlMasterStruct +****************************************************************************//** +* +* \brief Configures a Fixed Peripheral Slave Protection Unit (PPU SL) master +* protection struct with its protection attributes. +* +* This function configures the master struct governing the corresponding slave +* struct pair. It is a mechanism to protect the slave PPU SL struct. Since +* the memory location of the slave struct is known, the address, regionSize and +* subregions of the configuration struct are not applicable. +* +* Note that only the user/privileged write permissions are configurable. The +* read and execute permissions are read-only and cannot be configured. +* +* \param base +* The register base address of the protection struct being configured. +* +* \param config +* Initialization structure with all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | PPU SL master struct was successfully configured +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t attReg; + + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + /* ADDR1 is read only. Only configure ATT1 */ + attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) + | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PERI_GR_PPU_SL_ATT1_NS, !(config->secure)) + | _VAL2FLD(PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1, config->pcMask) + /* No region size - read only for master structs */ + | _VAL2FLD(PERI_GR_PPU_SL_ATT1_PC_MATCH, config->pcMatch); + if ((attReg & CY_PROT_PPU_SL_ATT1_MASK) != attReg) + { + /* Invalid parameter was passed */ + status = CY_PROT_BAD_PARAM; + } + else + { + base->ATT1 = attReg; + status = ((base->ATT1 & CY_PROT_PPU_SL_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigPpuFixedSlSlaveStruct +****************************************************************************//** +* +* \brief Configures a Fixed Peripheral Slave Protection Unit (PPU SL) slave +* protection struct with its protection attributes. +* +* This function configures the slave struct of a PPU SL pair, which can +* protect an entire peripheral slave instance from invalid bus master accesses. +* For example, TCPWM0, TCPWM1, SCB0 and SCB1 etc. +* +* Each fixed PPU SL is devoted to a defined peripheral slave. Hence the address, +* regionSize and subregions of the configuration struct are not applicable. +* +* Note that the user/privileged execute accesses are read-only and are always +* enabled. +* +* \param base +* The register base address of the protection structure being configured. +* +* \param config +* Initialization structure with all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | PPU SL slave struct was successfully configured +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t attReg; + + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + /* ADDR0 is read only. Only configure ATT0 */ + attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) + | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PERI_GR_PPU_SL_ATT0_NS, !(config->secure)) + | _VAL2FLD(PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1, config->pcMask) + /* No region size - read only */ + | _VAL2FLD(PERI_GR_PPU_SL_ATT0_PC_MATCH, config->pcMatch); + if ((attReg & CY_PROT_PPU_SL_ATT0_MASK) != attReg) + { + /* Invalid parameter was passed */ + status = CY_PROT_BAD_PARAM; + } + else + { + base->ATT0 = attReg; + status = ((base->ATT0 & CY_PROT_PPU_SL_ATT0_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnablePpuFixedSlMasterStruct +****************************************************************************//** +* +* \brief Enables the Master PPU SL structure. +* +* This is a PPU SL master struct enable function. The PPU SL protection +* settings will take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Master PU struct was enabled +* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT1 |= _VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_GR_PPU_SL_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisablePpuFixedSlMasterStruct +****************************************************************************//** +* +* \brief Disables the Master PPU SL structure. +* +* This is a PPU SL master struct disable function. The PPU SL protection +* settings will seize to take effect after successful completion of this +* function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Master PU struct was disabled +* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT1 &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_GR_PPU_SL_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnablePpuFixedSlSlaveStruct +****************************************************************************//** +* +* \brief Enables the Slave PPU SL structure. +* +* This is a PPU SL slave struct enable function. The PPU SL protection +* settings will take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Slave PU struct was enabled +* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT0 |= _VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_GR_PPU_SL_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisablePpuFixedSlSlaveStruct +****************************************************************************//** +* +* \brief Disables the Slave PPU SL structure. +* +* This is a PPU SL slave struct disable function. The PPU SL protection +* settings will seize to take effect after successful completion of this +* function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Slave PU struct was disabled +* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT0 &= ~_VAL2FLD(PERI_GR_PPU_SL_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_GR_PPU_SL_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigPpuFixedRgMasterStruct +****************************************************************************//** +* +* \brief Configures a Fixed Peripheral Region Protection Unit (PPU RG) master +* protection struct with its protection attributes. +* +* This function configures the master struct governing the corresponding slave +* struct pair. It is a mechanism to protect the slave PPU RG struct. Since +* the memory location of the slave struct is known, the address, regionSize and +* subregions of the configuration struct are not applicable. +* +* Note that only the user/privileged write permissions are configurable. The +* read and execute permissions are read-only and cannot be configured. +* +* \param base +* The register base address of the protection struct being configured. +* +* \param config +* Initialization structure with all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | PPU RG master struct was successfully configured +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t attReg; + + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + /* ADDR1 is read only. Only configure ATT1 */ + attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) + | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PERI_GR_PPU_RG_ATT1_NS, !(config->secure)) + | _VAL2FLD(PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1, config->pcMask) + /* No region size - read only for master structs */ + | _VAL2FLD(PERI_GR_PPU_RG_ATT1_PC_MATCH, config->pcMatch); + if ((attReg & CY_PROT_PPU_RG_ATT1_MASK) != attReg) + { + /* Invalid parameter was passed */ + status = CY_PROT_BAD_PARAM; + } + else + { + base->ATT1 = attReg; + status = ((base->ATT1 & CY_PROT_PPU_RG_ATT1_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_ConfigPpuFixedRgSlaveStruct +****************************************************************************//** +* +* \brief Configures a Fixed Peripheral Region Protection Unit (PPU RG) slave +* protection struct with its protection attributes. +* +* This function configures the slave struct of a PPU RG pair, which can +* protect specified regions of peripheral instances. For example, individual +* DW channel structs, SMPU structs, and IPC structs etc. +* +* Each fixed PPU RG is devoted to a defined peripheral region. Hence the address, +* regionSize and subregions of the configuration struct are not applicable. +* +* Note that the user/privileged execute accesses are read-only and are always +* enabled. +* +* \param base +* The register base address of the protection structure being configured. +* +* \param config +* Initialization structure with all the protection attributes. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | PPU RG slave struct was successfully configured +* CY_PROT_FAILURE | The resource is locked +* CY_PROT_BAD_PARAM | An incorrect/invalid parameter was passed +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + uint32_t attReg; + + if(((uint32_t)config->pcMask & CY_PROT_PPU_FIXED_PC_LIMIT_MASK) != 0UL) + { + /* PC mask out of range - not supported in device */ + status = CY_PROT_BAD_PARAM; + } + else + { + /* ADDR0 is read only. Only configure ATT0 */ + attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) + | (uint32_t)(((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION_SHIFT) + | _VAL2FLD(PERI_GR_PPU_RG_ATT0_NS, !(config->secure)) + | _VAL2FLD(PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1, config->pcMask) + /* No region size - read only */ + | _VAL2FLD(PERI_GR_PPU_RG_ATT0_PC_MATCH, config->pcMatch); + if ((attReg & CY_PROT_PPU_RG_ATT0_MASK) != attReg) + { + /* Invalid parameter was passed */ + status = CY_PROT_BAD_PARAM; + } + else + { + base->ATT0 = attReg; + status = ((base->ATT0 & CY_PROT_PPU_RG_ATT0_MASK) != attReg) ? CY_PROT_FAILURE : CY_PROT_SUCCESS; + } + } + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnablePpuFixedRgMasterStruct +****************************************************************************//** +* +* \brief Enables the Master PPU RG structure. +* +* This is a PPU RG master struct enable function. The PPU RG protection +* settings will take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Master PU struct was enabled +* CY_PROT_FAILURE | The Master PU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT1 |= _VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_GR_PPU_RG_ATT1_ENABLED, base->ATT1) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisablePpuFixedRgMasterStruct +****************************************************************************//** +* +* \brief Disables the Master PPU RG structure. +* +* This is a PPU RG master struct disable function. The PPU RG protection +* settings will seize to take effect after successful completion of this +* function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Master PU struct was disabled +* CY_PROT_FAILURE | The Master PU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT1 &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT1_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_GR_PPU_RG_ATT1_ENABLED, base->ATT1) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_EnablePpuFixedRgSlaveStruct +****************************************************************************//** +* +* \brief Enables the Slave PPU RG structure. +* +* This is a PPU RG slave struct enable function. The PPU RG protection +* settings will take effect after successful completion of this function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Slave PU struct was enabled +* CY_PROT_FAILURE | The Slave PU struct is disabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT0 |= _VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_GR_PPU_RG_ATT0_ENABLED, base->ATT0) != CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +/******************************************************************************* +* Function Name: Cy_Prot_DisablePpuFixedRgSlaveStruct +****************************************************************************//** +* +* \brief Disables the Slave PPU RG structure. +* +* This is a PPU RG slave struct disable function. The PPU RG protection +* settings will seize to take effect after successful completion of this +* function call. +* +* \param base +* The base address for the protection unit structure being configured. +* +* \return +* Status of the function call. +* +* Status | Description +* ------------ | ----------- +* CY_PROT_SUCCESS | The Slave PU struct was disabled +* CY_PROT_FAILURE | The Slave PU struct is enabled and possibly locked +* +*******************************************************************************/ +cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base) +{ + cy_en_prot_status_t status = CY_PROT_SUCCESS; + + base->ATT0 &= ~_VAL2FLD(PERI_GR_PPU_RG_ATT0_ENABLED, CY_PROT_STRUCT_ENABLE); + status = (_FLD2VAL(PERI_GR_PPU_RG_ATT0_ENABLED, base->ATT0) == CY_PROT_STRUCT_ENABLE) ? + CY_PROT_FAILURE : CY_PROT_SUCCESS; + + return status; +} + + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/prot/cy_prot.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/prot/cy_prot.h new file mode 100644 index 0000000000..f4001797f1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/prot/cy_prot.h @@ -0,0 +1,558 @@ +/***************************************************************************//** +* \file cy_prot.h +* \version 1.0 +* +* \brief +* Provides an API declaration of the Protection Unit driver +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_prot Protection Unit (Prot) +* \{ +* +* The Protection Unit driver provides an API to configure the Memory Protection +* Units (MPU), Shared Memory Protection Units (SMPU), and Peripheral Protection +* Units (PPU). These are separate from the ARM Core MPUs and provide additional +* mechanisms for securing resource accesses. The Protection units address the +* following concerns in an embedded design: +* - Security requirements. This includes the prevention of malicious attacks +* to access secure memory or peripherals. +* - Safety requirements. This includes detection of accidental (non-malicious) +* SW errors and random HW errors. It is important to enable failure analysis +* to investigate the root cause of a safety violation. +* +* \n +* Memory Protection +* +* Memory protection is provided by MPUs and SMPUs and allows control of +* memory accesses by bus masters (e.g., CM0+, CM4, Crypto): +* - MPUs are used to distinguish user and privileged accesses from a single bus +* master such as task switching in an OS/kernel. For ARM core MPUs, the +* assigned Cypress MPUs for those cores provide additional functionality +* such as protection contexts (PC) and security attributes. +* - SMPUs are used to distinguish memory accesses between bus masters. This is +* achieved by using protection contexts and secure-/non-secure attributes. +* +* \n +* Peripheral Protection +* +* Peripheral protection is provided by PPUs and allows control of peripheral +* register accesses by bus masters. Four types of PPUs are available. +* - Programmable (PROG) PPUs are used to protect any peripheral memory region +* in a device from invalid bus master accesses. It is the most versatile +* type of peripheral protection unit. +* - Fixed Group (GR) PPUs are used to protect an entire peripheral MMIO group +* from invalid bus master accesses. The MMIO grouping information and which +* resource belongs to which group is device specific and can be obtained +* from the device technical reference manual (TRM). +* - Fixed Region (RG) PPUs are used to protect an entire peripheral slave +* instance from invalid bus master accesses. For example, TCPWM0, TCPWM1, +* SCB0, and SCB1, etc. +* - Fixed Slave (SL) PPUs are used to protect specified regions of peripheral +* instances. For example, individual DW channel structs, SMPU structs, and +* IPC structs, etc. +* +* \n +* Driver Usage +* +* Each protection unit is distinguished by its type (e.g. +* PROT_MPU_MPU_STRUCT_Type). The list of supported protection units can be +* obtained from the device header file. Choose a protection unit of interest, +* and call its corresponding Cy_Prot_ConfigStruct() function with its +* software protection unit configuration structure populated. Then enable the +* protection unit by calling the Cy_Prot_EnableStruct() function. +* +* Each bus master can be configured to allow/disallow certain types of accesses +* by calling the Cy_Prot_ConfigBusMaster() function. For example, CM0+ core +* is a bus master. By configuring it to allow only protection contexts (PC) +* 2 and 3, the bus master will be able to set its protection context only to +* 2 or 3. In a thread execution, the CM0+ core can set its protection context +* to 2 by calling Cy_Prot_SetActivePC() and access all regions of memory that +* allow PC=2. A fault will be triggered if a resource is protected with different +* protection settings. +* +* \section group_prot_configuration Configuration Considerations +* +* With the exception of MPUs, Protection structures are implemented in +* hardware as master and slave pairs. The master protection structure protects +* the slave protection structure. The slave protection structure protects the +* memory region that is to be protected. +* For example, a slave protection structure is configured to allow protection +* contexts 3 and 4 to access a set of peripheral registers. The corresponding +* master protection structure can then be used to protect the slave structure +* configuration and allow only protection context 1 to make modifications. +* Any bus master attempting to change the slave protection structure must then +* have a protection context 1. Otherwise an access fault will occur. +* +* \section group_prot_more_information More Information +* +* Refer to Technical Reference Manual (TRM) and the device datasheet. +* +* \section group_prot_MISRA MISRA-C Compliance] +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA ruleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.5RDangerous pointer cast results in loss of volatile qualification.Required to access bus master control register
+* +* \section group_prot_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_prot_macro Macro +* \defgroup group_prot_functions Functions +* \{ +* \defgroup group_prot_functions_busmaster Bus Master and PC Functions +* \defgroup group_prot_functions_mpu MPU Functions +* \defgroup group_prot_functions_smpu SMPU Functions +* \defgroup group_prot_functions_ppu_prog PPU Programmable (PROG) Functions +* \defgroup group_prot_functions_ppu_gr PPU Group (GR) Functions +* \defgroup group_prot_functions_ppu_sl PPU Slave (SL) Functions +* \defgroup group_prot_functions_ppu_rg PPU Region (RG) Functions +* \} +* \defgroup group_prot_data_structures Data structures +* \defgroup group_prot_enums Enumerated types +*/ + +#if !defined(__CY_PROT_H__) +#define __CY_PROT_H__ + +#include +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_prot_macro +* \{ +*/ + +/** Driver major version */ +#define CY_PROT_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_PROT_DRV_VERSION_MINOR 0 + +/** Prot driver ID */ +#define CY_PROT_ID CY_PDL_DRV_ID(0x30u) + +/** \} group_prot_macro */ + +/** +* \addtogroup group_prot_enums +* \{ +*/ + +/** +* Prot Driver error codes +*/ +typedef enum +{ + CY_PROT_SUCCESS = 0x00u, /**< Returned successful */ + CY_PROT_BAD_PARAM = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */ + CY_PROT_FAILURE = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x03u /**< The resource is locked */ +} cy_en_prot_status_t; + +/** +* User/Privileged permission +*/ +typedef enum +{ + CY_PROT_PERM_DISABLED = 0x00u, /**< Read, Write and Execute disabled */ + CY_PROT_PERM_R = 0x01u, /**< Read enabled */ + CY_PROT_PERM_W = 0x02u, /**< Write enabled */ + CY_PROT_PERM_RW = 0x03u, /**< Read and Write enabled */ + CY_PROT_PERM_X = 0x04u, /**< Execute enabled */ + CY_PROT_PERM_RX = 0x05u, /**< Read and Execute enabled */ + CY_PROT_PERM_WX = 0x06u, /**< Write and Execute enabled */ + CY_PROT_PERM_RWX = 0x07u /**< Read, Write and Execute enabled */ +}cy_en_prot_perm_t; + +/** +* Memory region size +*/ +typedef enum +{ + CY_PROT_SIZE_256B = 7u, /**< 256 bytes */ + CY_PROT_SIZE_512B = 8u, /**< 512 bytes */ + CY_PROT_SIZE_1KB = 9u, /**< 1 Kilobyte */ + CY_PROT_SIZE_2KB = 10u, /**< 2 Kilobytes */ + CY_PROT_SIZE_4KB = 11u, /**< 4 Kilobytes */ + CY_PROT_SIZE_8KB = 12u, /**< 8 Kilobytes */ + CY_PROT_SIZE_16KB = 13u, /**< 16 Kilobytes */ + CY_PROT_SIZE_32KB = 14u, /**< 32 Kilobytes */ + CY_PROT_SIZE_64KB = 15u, /**< 64 Kilobytes */ + CY_PROT_SIZE_128KB = 16u, /**< 128 Kilobytes */ + CY_PROT_SIZE_256KB = 17u, /**< 256 Kilobytes */ + CY_PROT_SIZE_512KB = 18u, /**< 512 Kilobytes */ + CY_PROT_SIZE_1MB = 19u, /**< 1 Megabyte */ + CY_PROT_SIZE_2MB = 20u, /**< 2 Megabytes */ + CY_PROT_SIZE_4MB = 21u, /**< 4 Megabytes */ + CY_PROT_SIZE_8MB = 22u, /**< 8 Megabytes */ + CY_PROT_SIZE_16MB = 23u, /**< 16 Megabytes */ + CY_PROT_SIZE_32MB = 24u, /**< 32 Megabytes */ + CY_PROT_SIZE_64MB = 25u, /**< 64 Megabytes */ + CY_PROT_SIZE_128MB = 26u, /**< 128 Megabytes */ + CY_PROT_SIZE_256MB = 27u, /**< 256 Megabytes */ + CY_PROT_SIZE_512MB = 28u, /**< 512 Megabytes */ + CY_PROT_SIZE_1GB = 29u, /**< 1 Gigabyte */ + CY_PROT_SIZE_2GB = 30u, /**< 2 Gigabytes */ + CY_PROT_SIZE_4GB = 31u /**< 4 Gigabytes */ +}cy_en_prot_size_t; + +/** +* Protection Context (PC) +*/ +enum cy_en_prot_pc_t +{ + CY_PROT_PC1 = 1u, /**< PC = 1 */ + CY_PROT_PC2 = 2u, /**< PC = 2 */ + CY_PROT_PC3 = 3u, /**< PC = 3 */ + CY_PROT_PC4 = 4u, /**< PC = 4 */ + CY_PROT_PC5 = 5u, /**< PC = 5 */ + CY_PROT_PC6 = 6u, /**< PC = 6 */ + CY_PROT_PC7 = 7u, /**< PC = 7 */ + CY_PROT_PC8 = 8u, /**< PC = 8 */ + CY_PROT_PC9 = 9u, /**< PC = 9 */ + CY_PROT_PC10 = 10u, /**< PC = 10 */ + CY_PROT_PC11 = 11u, /**< PC = 11 */ + CY_PROT_PC12 = 12u, /**< PC = 12 */ + CY_PROT_PC13 = 13u, /**< PC = 13 */ + CY_PROT_PC14 = 14u, /**< PC = 14 */ + CY_PROT_PC15 = 15u /**< PC = 15 */ +}; + +/** +* Subregion disable (0-7) +*/ +enum cy_en_prot_subreg_t +{ + CY_PROT_SUBREGION_DIS0 = 0x01u, /**< Disable subregion 0 */ + CY_PROT_SUBREGION_DIS1 = 0x02u, /**< Disable subregion 1 */ + CY_PROT_SUBREGION_DIS2 = 0x04u, /**< Disable subregion 2 */ + CY_PROT_SUBREGION_DIS3 = 0x08u, /**< Disable subregion 3 */ + CY_PROT_SUBREGION_DIS4 = 0x10u, /**< Disable subregion 4 */ + CY_PROT_SUBREGION_DIS5 = 0x20u, /**< Disable subregion 5 */ + CY_PROT_SUBREGION_DIS6 = 0x40u, /**< Disable subregion 6 */ + CY_PROT_SUBREGION_DIS7 = 0x80u /**< Disable subregion 7 */ +}; + +/** +* Protection context mask (PC_MASK) +*/ +enum cy_en_prot_pcmask_t +{ + CY_PROT_PCMASK1 = 0x0001u, /**< Mask to allow PC = 1 */ + CY_PROT_PCMASK2 = 0x0002u, /**< Mask to allow PC = 2 */ + CY_PROT_PCMASK3 = 0x0004u, /**< Mask to allow PC = 3 */ + CY_PROT_PCMASK4 = 0x0008u, /**< Mask to allow PC = 4 */ + CY_PROT_PCMASK5 = 0x0010u, /**< Mask to allow PC = 5 */ + CY_PROT_PCMASK6 = 0x0020u, /**< Mask to allow PC = 6 */ + CY_PROT_PCMASK7 = 0x0040u, /**< Mask to allow PC = 7 */ + CY_PROT_PCMASK8 = 0x0080u, /**< Mask to allow PC = 8 */ + CY_PROT_PCMASK9 = 0x0100u, /**< Mask to allow PC = 9 */ + CY_PROT_PCMASK10 = 0x0200u, /**< Mask to allow PC = 10 */ + CY_PROT_PCMASK11 = 0x0400u, /**< Mask to allow PC = 11 */ + CY_PROT_PCMASK12 = 0x0800u, /**< Mask to allow PC = 12 */ + CY_PROT_PCMASK13 = 0x1000u, /**< Mask to allow PC = 13 */ + CY_PROT_PCMASK14 = 0x2000u, /**< Mask to allow PC = 14 */ + CY_PROT_PCMASK15 = 0x4000u /**< Mask to allow PC = 15 */ +}; + +/** \} group_prot_enums */ + + +/*************************************** +* Constants +***************************************/ + +/** \cond INTERNAL */ + +/* General Masks and shifts */ +#define CY_PROT_MSX_CTL_SHIFT (0x02UL) /**< Shift for MSx_CTL register */ +#define CY_PROT_STRUCT_ENABLE (0x01UL) /**< Enable protection unit struct */ +#define CY_PROT_ADDR_SHIFT (8UL) /**< Address shift for MPU, SMPU and PROG PPU structs */ + +/* Permission masks and shifts */ +#define CY_PROT_ATT_PERMISSION_MASK (0x07UL) /**< Protection Unit attribute permission mask */ +#define CY_PROT_ATT_USER_PERMISSION_SHIFT (0x00UL) /**< Protection Unit user attribute permission shift */ +#define CY_PROT_ATT_PRIV_PERMISSION_SHIFT (0x03UL) /**< Protection Unit priliged attribute permission shift */ + +/* Protection Context limit masks */ +#define CY_PROT_MPU_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1) +#define CY_PROT_SMPU_PC_LIMIT_MASK (0xFFFFFFFFUL << CPUSS_SMPU_STRUCT_PC_NR_MINUS1) +#define CY_PROT_PPU_PROG_PC_LIMIT_MASK (0xFFFFFFFFUL << PERI_PPU_PROG_STRUCT_PC_NR_MINUS1) +#define CY_PROT_PPU_FIXED_PC_LIMIT_MASK (0xFFFFFFFFUL << PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1) + +/* Parameter validation masks to check for read-only values */ +#define CY_PROT_SMPU_ATT0_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk)) +#define CY_PROT_SMPU_ATT1_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT1_UR_Msk \ + | PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk \ + | PROT_SMPU_SMPU_STRUCT_ATT1_PR_Msk \ + | PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk \ + | PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk \ + | PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk \ + )) +#define CY_PROT_PPU_PROG_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \ + | PERI_PPU_GR_ATT1_PX_Msk \ + |PERI_PPU_PR_ATT0_PC_MASK_0_Msk \ + )) +#define CY_PROT_PPU_PROG_ATT1_MASK ((uint32_t)~(PERI_PPU_PR_ATT1_UR_Msk \ + | PERI_PPU_PR_ATT1_UX_Msk \ + | PERI_PPU_PR_ATT1_PR_Msk \ + | PERI_PPU_PR_ATT1_PX_Msk \ + | PERI_PPU_PR_ATT1_PC_MASK_0_Msk \ + | PERI_PPU_PR_ATT1_REGION_SIZE_Msk \ + )) +#define CY_PROT_PPU_GR_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \ + | PERI_PPU_GR_ATT0_PX_Msk \ + | PERI_PPU_GR_ATT0_PC_MASK_0_Msk \ + | PERI_PPU_GR_ATT0_REGION_SIZE_Msk \ + )) +#define CY_PROT_PPU_GR_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UR_Msk \ + | PERI_PPU_GR_ATT1_UX_Msk \ + | PERI_PPU_GR_ATT1_PR_Msk \ + | PERI_PPU_GR_ATT1_PX_Msk \ + | PERI_PPU_GR_ATT1_PC_MASK_0_Msk \ + | PERI_PPU_GR_ATT1_REGION_SIZE_Msk \ + )) +#define CY_PROT_PPU_SL_ATT0_MASK ((uint32_t)~(PERI_GR_PPU_SL_ATT0_UX_Msk \ + | PERI_GR_PPU_SL_ATT0_PX_Msk \ + | PERI_GR_PPU_SL_ATT0_PC_MASK_0_Msk \ + | PERI_GR_PPU_SL_ATT0_REGION_SIZE_Msk \ + )) +#define CY_PROT_PPU_SL_ATT1_MASK ((uint32_t)~(PERI_GR_PPU_SL_ATT1_UR_Msk \ + | PERI_GR_PPU_SL_ATT1_UX_Msk \ + | PERI_GR_PPU_SL_ATT1_PR_Msk \ + | PERI_GR_PPU_SL_ATT1_PX_Msk \ + | PERI_GR_PPU_SL_ATT1_PC_MASK_0_Msk \ + | PERI_GR_PPU_SL_ATT1_REGION_SIZE_Msk \ + )) +#define CY_PROT_PPU_RG_ATT0_MASK ((uint32_t)~(PERI_GR_PPU_RG_ATT0_UX_Msk \ + | PERI_GR_PPU_RG_ATT0_PX_Msk \ + | PERI_GR_PPU_RG_ATT0_PC_MASK_0_Msk \ + | PERI_GR_PPU_RG_ATT0_REGION_SIZE_Msk \ + )) +#define CY_PROT_PPU_RG_ATT1_MASK ((uint32_t)~(PERI_GR_PPU_RG_ATT1_UR_Msk \ + | PERI_GR_PPU_RG_ATT1_UX_Msk \ + | PERI_GR_PPU_RG_ATT1_PR_Msk \ + | PERI_GR_PPU_RG_ATT1_PX_Msk \ + | PERI_GR_PPU_RG_ATT1_PC_MASK_0_Msk \ + | PERI_GR_PPU_RG_ATT1_REGION_SIZE_Msk \ + )) + +/** \endcond */ + + +/*************************************** +* Configuration Structures +***************************************/ + +/** +* \addtogroup group_prot_data_structures +* \{ +*/ + +/** Configuration structure for MPU Struct initialization */ +typedef struct +{ + uint32_t* address; /**< Base address of the memory region */ + cy_en_prot_size_t regionSize; /**< Size of the memory region */ + uint8_t subregions; /**< Mask of the 8 subregions to disable */ + cy_en_prot_perm_t userPermission; /**< User permissions for the region */ + cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */ + bool secure; /**< Non Secure = 0, Secure = 1 */ +} cy_stc_mpu_cfg_t; + +/** Configuration structure for SMPU struct initialization */ +typedef struct +{ + uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */ + cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */ + uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */ + cy_en_prot_perm_t userPermission; /**< User permissions for the region */ + cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */ + bool secure; /**< Non Secure = 0, Secure = 1 */ + bool pcMatch; /**< Access evaluation = 0, Matching = 1 */ + uint16_t pcMask; /**< Mask of allowed protection context(s) */ +} cy_stc_smpu_cfg_t; + +/** Configuration structure for Programmable (PROG) PPU (PPU_PR) struct initialization */ +typedef struct +{ + uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */ + cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */ + uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */ + cy_en_prot_perm_t userPermission; /**< User permissions for the region */ + cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */ + bool secure; /**< Non Secure = 0, Secure = 1 */ + bool pcMatch; /**< Access evaluation = 0, Matching = 1 */ + uint16_t pcMask; /**< Mask of allowed protection context(s) */ +} cy_stc_ppu_prog_cfg_t; + +/** Configuration structure for Fixed Group (GR) PPU (PPU_GR) struct initialization */ +typedef struct +{ + cy_en_prot_perm_t userPermission; /**< User permissions for the region */ + cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */ + bool secure; /**< Non Secure = 0, Secure = 1 */ + bool pcMatch; /**< Access evaluation = 0, Matching = 1 */ + uint16_t pcMask; /**< Mask of allowed protection context(s) */ +} cy_stc_ppu_gr_cfg_t; + +/** Configuration structure for Fixed Slave (SL) PPU (PPU_SL) struct initialization */ +typedef struct +{ + cy_en_prot_perm_t userPermission; /**< User permissions for the region */ + cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */ + bool secure; /**< Non Secure = 0, Secure = 1 */ + bool pcMatch; /**< Access evaluation = 0, Matching = 1 */ + uint16_t pcMask; /**< Mask of allowed protection context(s) */ +} cy_stc_ppu_sl_cfg_t; + +/** Configuration structure for Fixed Region (RG) PPU (PPU_RG) struct initialization */ +typedef struct +{ + cy_en_prot_perm_t userPermission; /**< User permissions for the region */ + cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */ + bool secure; /**< Non Secure = 0, Secure = 1 */ + bool pcMatch; /**< Access evaluation = 0, Matching = 1 */ + uint16_t pcMask; /**< Mask of allowed protection context(s) */ +} cy_stc_ppu_rg_cfg_t; + +/** \} group_prot_data_structures */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_prot_functions +* \{ +*/ + +/** +* \addtogroup group_prot_functions_busmaster +* \{ +*/ + +cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask); +cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc); +uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster); + +/** \} group_prot_functions_busmaster */ + +/** +* \addtogroup group_prot_functions_mpu +* \{ +*/ + +cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config); +cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base); +cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base); + +/** \} group_prot_functions_mpu */ + +/** +* \addtogroup group_prot_functions_smpu +* \{ +*/ + +cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config); +cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config); +cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base); +cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base); +cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base); +cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base); + +/** \} group_prot_functions_smpu */ + +/** +* \addtogroup group_prot_functions_ppu_prog +* \{ +*/ + +cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config); +cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config); +cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base); +cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base); +cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base); +cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base); + +/** \} group_prot_functions_ppu_prog */ + +/** +* \addtogroup group_prot_functions_ppu_gr +* \{ +*/ + +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config); +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config); +cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base); +cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base); +cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base); +cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base); + +/** \} group_prot_functions_ppu_gr */ + +/** +* \addtogroup group_prot_functions_ppu_sl +* \{ +*/ + +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config); +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config); +cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base); +cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base); +cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base); +cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base); + +/** \} group_prot_functions_ppu_sl */ + +/** +* \addtogroup group_prot_functions_ppu_rg +* \{ +*/ +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config); +cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config); +cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base); +cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base); +cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base); +cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base); + +/** \} group_prot_functions_ppu_rg */ + +/** \} group_prot_functions */ + +/** \} group_prot */ + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_PROT_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_common.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_common.c new file mode 100644 index 0000000000..e102bd01ef --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_common.c @@ -0,0 +1,412 @@ +/***************************************************************************//** +* \file cy_scb_common.c +* \version 1.0 +* +* Provides common API implementation of the SCB driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_scb_common.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Function Name: Cy_SCB_ReadArrayNoCheck +****************************************************************************//** +* +* Reads an array of data out of the SCB receive FIFO without checking if the +* receive FIFO has enough data elements. +* Before calling this function, make sure that the receive FIFO has enough data +* elements to be read. +* +* \param base +* The pointer to the SCB instance. +* +* \param rxBuf +* The pointer to location to place data read from the receive FIFO. +* The size of the data element defined by the configured data width. +* +* \param size +* The number of data elements read from the receive FIFO. +* +*******************************************************************************/ +void Cy_SCB_ReadArrayNoCheck(CySCB_Type const *base, void *rxBuf, uint32_t size) +{ + uint32_t idx; + + if (Cy_SCB_IsRxDataWidthByte(base)) + { + uint8_t *buf = (uint8_t *) rxBuf; + + /* Get data available in RX FIFO */ + for (idx = 0UL; idx < size; ++idx) + { + buf[idx] = (uint8_t) Cy_SCB_ReadRxFifo(base); + } + } + else + { + uint16_t *buf = (uint16_t *) rxBuf; + + /* Get data available in RX FIFO */ + for (idx = 0UL; idx < size; ++idx) + { + buf[idx] = (uint16_t) Cy_SCB_ReadRxFifo(base); + } + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_ReadArray +****************************************************************************//** +* +* Reads an array of data out of the SCB receive FIFO. +* This function does not block, it returns how many data elements were +* read from the receive FIFO. +* +* \param base +* The pointer to the SCB instance. +* +* \param rxBuf +* The pointer to location to place data read from receive FIFO. +* The item size is defined by the data type which depends on the configured +* data width. +* +* \param size +* The number of data elements to read from the receive FIFO. +* +* \return +* The number of data elements read from the receive FIFO. +* +*******************************************************************************/ +uint32_t Cy_SCB_ReadArray(CySCB_Type const *base, void *rxBuf, uint32_t size) +{ + /* Get available items in RX FIFO */ + uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base); + + /* Adjust items which will be read */ + if (numToCopy > size) + { + numToCopy = size; + } + + /* Get data available in RX FIFO */ + Cy_SCB_ReadArrayNoCheck(base, rxBuf, numToCopy); + + return (numToCopy); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_ReadArrayBlocking +****************************************************************************//** +* +* Reads an array of data out of the SCB receive FIFO. +* This function blocks until the number of data elements specified by the +* size has been read from the receive FIFO. +* +* \param base +* The pointer to the SCB instance. +* +* \param rxBuf +* The pointer to location to place data read from receive FIFO. +* The item size is defined by the data type which depends on the configured +* data width. +* +* \param size +* The number of data elements to read from receive FIFO. +* +*******************************************************************************/ +void Cy_SCB_ReadArrayBlocking(CySCB_Type const *base, void *rxBuf, uint32_t size) +{ + uint32_t numCopied; + uint8_t *buf = (uint8_t *) rxBuf; + + /* Get data from RX FIFO. Stop when the requested size is read. */ + while (size > 0UL) + { + numCopied = Cy_SCB_ReadArray(base, (void *) buf, size); + + buf = &buf[(Cy_SCB_IsRxDataWidthByte(base) ? (numCopied) : (2UL * numCopied))]; + size -= numCopied; + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_Write +****************************************************************************//** +* +* Places a single data element in the SCB transmit FIFO. +* This function does not block and returns how many data elements were placed +* in the transmit FIFO. +* +* \param base +* The pointer to the SCB instance. +* +* \param data +* Data to put in the transmit FIFO. +* The item size is defined by the data type which depends on the configured +* data width. +* +* \return +* The number of data elements placed in the transmit FIFO: 0 or 1. +* +*******************************************************************************/ +uint32_t Cy_SCB_Write(CySCB_Type *base, uint32_t data) +{ + uint32_t numCopied = 0UL; + + if (Cy_SCB_GetFifoSize(base) != Cy_SCB_GetNumInTxFifo(base)) + { + Cy_SCB_WriteTxFifo(base, data); + + numCopied = 1UL; + } + + return (numCopied); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_WriteArrayNoCheck +****************************************************************************//** +* +* Places an array of data in the SCB transmit FIFO without checking if the +* transmit FIFO has enough space. +* Before calling this function, make sure that the transmit FIFO has enough +* space to put all requested data elements. +* +* \param base +* The pointer to the SCB instance. +* +* \param txBuf +* The pointer to data to place in the transmit FIFO. +* The item size is defined by the data type which depends on the configured +* TX data width. +* +* \param size +* The number of data elements to transmit. +* +* \return +* The number of data elements placed in the transmit FIFO. +* +*******************************************************************************/ +void Cy_SCB_WriteArrayNoCheck(CySCB_Type *base, void *txBuf, uint32_t size) +{ + uint32_t idx; + + if (Cy_SCB_IsTxDataWidthByte(base)) + { + uint8_t *buf = (uint8_t *) txBuf; + + /* Put data into TX FIFO */ + for (idx = 0UL; idx < size; ++idx) + { + Cy_SCB_WriteTxFifo(base, (uint32_t) buf[idx]); + } + } + else + { + uint16_t *buf = (uint16_t *) txBuf; + + /* Put data into TX FIFO */ + for (idx = 0UL; idx < size; ++idx) + { + Cy_SCB_WriteTxFifo(base, (uint32_t) buf[idx]); + } + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_WriteArray +****************************************************************************//** +* +* Places an array of data in the SCB transmit FIFO. +* This function does not block and it returns how many data elements were +* placed in the transmit FIFO. +* +* \param base +* The pointer to the SCB instance. +* +* \param txBuf +* The pointer to data to place in the transmit FIFO. +* The item size is defined by the data type which depends on the configured +* TX data width. +* +* \param size +* The number of data elements to transmit. +* +* \return +* The number of data elements placed in the transmit FIFO. +* +*******************************************************************************/ +uint32_t Cy_SCB_WriteArray(CySCB_Type *base, void *txBuf, uint32_t size) +{ + /* Get free entries in TX FIFO */ + uint32_t numToCopy = Cy_SCB_GetFifoSize(base) - Cy_SCB_GetNumInTxFifo(base); + + /* Adjust the data elements to write */ + if (numToCopy > size) + { + numToCopy = size; + } + + Cy_SCB_WriteArrayNoCheck(base, txBuf, numToCopy); + + return (numToCopy); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_WriteArrayBlocking +****************************************************************************//** +* +* Places an array of data in the transmit FIFO. +* This function blocks until the number of data elements specified by the size +* is placed in the transmit FIFO. +* +* \param base +* The pointer to the SCB instance. +* +* \param txBuf +* The pointer to data to place in transmit FIFO. +* The item size is defined by the data type which depends on the configured +* data width. +* +* \param size +* The number of data elements to write into the transmit FIFO. +* +*******************************************************************************/ +void Cy_SCB_WriteArrayBlocking(CySCB_Type *base, void *txBuf, uint32_t size) +{ + uint32_t numCopied; + uint8_t *buf = (uint8_t *) txBuf; + + /* Get data from RX FIFO. Stop when the requested size is read. */ + while (size > 0UL) + { + numCopied = Cy_SCB_WriteArray(base, (void *) buf, size); + + buf = &buf[(Cy_SCB_IsTxDataWidthByte(base) ? (numCopied) : (2UL * numCopied))]; + size -= numCopied; + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_WriteString +****************************************************************************//** +* +* Places a NULL terminated string in the transmit FIFO. +* This function blocks until the entire string is placed in the transmit FIFO. +* +* \param base +* The pointer to the SCB instance. +* +* \param string +* The pointer to the null terminated string array. +* +*******************************************************************************/ +void Cy_SCB_WriteString(CySCB_Type *base, char_t const string[]) +{ + uint32_t idx = 0UL; + uint32_t fifoSize = Cy_SCB_GetFifoSize(base); + + /* Put data from TX FIFO. Stop when string is terminated */ + while (((char_t) 0) != string[idx]) + { + /* Wait for free space to be available */ + while (fifoSize == Cy_SCB_GetNumInTxFifo(base)) + { + } + + Cy_SCB_WriteTxFifo(base, (uint32_t) string[idx]); + ++idx; + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_WriteDefaultArrayNoCheck +****************************************************************************//** +* +* Places a number of the same data elements in the SCB transmit FIFO without +* checking if the transmit FIFO has enough space. The data elements is equal +* to txData parameter. +* Before calling this function make sure that transmit FIFO has enough space +* to put all requested data elements. +* +* \param base +* The pointer to the SCB instance. +* +* \param txData +* The data element to transmit repeatedly. +* +* \param size +* The number of data elements to transmit. +* +*******************************************************************************/ +void Cy_SCB_WriteDefaultArrayNoCheck(CySCB_Type *base, uint32_t txData, uint32_t size) +{ + while (size > 0UL) + { + Cy_SCB_WriteTxFifo(base, txData); + --size; + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_WriteDefaultArray +****************************************************************************//** +* +* Places a number of the same data elements in the SCB transmit FIFO. +* The data elements is equal to the txData parameter. +* +* \param base +* The pointer to the SCB instance. +* +* \param txData +* The data element to transmit repeatedly. +* +* \param size +* The number of data elements to transmit. +* +* \return +* The number of data elements placed in the transmit FIFO. +* +*******************************************************************************/ +uint32_t Cy_SCB_WriteDefaultArray(CySCB_Type *base, uint32_t txData, uint32_t size) +{ + /* Get free entries in TX FIFO */ + uint32_t numToCopy = Cy_SCB_GetFifoSize(base) - Cy_SCB_GetNumInTxFifo(base); + + /* Adjust data elements to write */ + if (numToCopy > size) + { + numToCopy = size; + } + + Cy_SCB_WriteDefaultArrayNoCheck(base, txData, numToCopy); + + return (numToCopy); +} + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_common.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_common.h new file mode 100644 index 0000000000..bbb519c46a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_common.h @@ -0,0 +1,1617 @@ +/***************************************************************************//** +* \file cy_scb_common.h +* \version 1.0 +* +* Provides common API declarations of the SCB driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_scb Serial Communication Block (SCB) +* \{ +* \defgroup group_scb_common Common +* \defgroup group_scb_ezi2c EZI2C (SCB) +* \defgroup group_scb_i2c I2C (SCB) +* \defgroup group_scb_spi SPI (SCB) +* \defgroup group_scb_uart UART (SCB) +* \} */ + +/** +* \addtogroup group_scb_common +* \{ +* +* Common API for the Serial Communication Block. +* +* This is the common API that provides an interface to the SCB hardware. +* The I2C, SPI, and UART drivers use this common API. +* Most users will use individual drivers and do not need to use the common +* API for the SCB. However, you can use the common SCB API to implement +* a custom driver based on the SCB hardware. +* +* \section group_scb_common_configuration Configuration Considerations +* +* This is not a driver and it does not require configuration. +* +* \section group_scb_common_more_information More Information +* +* Refer to the SCB chapter of the technical reference manual (TRM). +* +* \section group_scb_common_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA ruleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and +* a different pointer to object type.The pointer to the buffer memory is void to allow handling of +* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). +*
+* +* \section group_scb_common_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_scb_common_macro Macro +* \defgroup group_scb_common_functions Functions +* \defgroup group_scb_common_data_structures Data Structures +* +*/ + +#if !defined(CY_SCB_COMMON_H) +#define CY_SCB_COMMON_H + +#include +#include +#include +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_scb_common_functions +* \{ +*/ +__STATIC_INLINE uint32_t Cy_SCB_ReadRxFifo (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t rxLevel); +__STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_ClearRxFifo (CySCB_Type *base); + +__STATIC_INLINE void Cy_SCB_WriteTxFifo (CySCB_Type *base, uint32_t data); +__STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t txLevel); +__STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid (CySCB_Type const *base); +__STATIC_INLINE bool Cy_SCB_IsTxComplete (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_ClearTxFifo (CySCB_Type *base); + +__STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode); + +__STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base); + +__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SetRxInterruptMask (CySCB_Type *base, uint32_t interruptMask); +__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask (CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_ClearRxInterrupt (CySCB_Type *base, uint32_t interruptMask); +__STATIC_INLINE void Cy_SCB_SetRxInterrupt (CySCB_Type *base, uint32_t interruptMask); + +__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SetTxInterruptMask (CySCB_Type *base, uint32_t interruptMask); +__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask (CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_ClearTxInterrupt (CySCB_Type *base, uint32_t interruptMask); +__STATIC_INLINE void Cy_SCB_SetTxInterrupt (CySCB_Type *base, uint32_t interruptMask); + +__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SetMasterInterruptMask (CySCB_Type *base, uint32_t interruptMask); +__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask (CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_ClearMasterInterrupt (CySCB_Type *base, uint32_t interruptMask); +__STATIC_INLINE void Cy_SCB_SetMasterInterrupt (CySCB_Type *base, uint32_t interruptMask); + +__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask (CySCB_Type *base, uint32_t interruptMask); +__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask (CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask); +__STATIC_INLINE void Cy_SCB_SetSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask); + +__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SetI2CInterruptMask (CySCB_Type *base, uint32_t interruptMask); +__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask (CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_ClearI2CInterrupt (CySCB_Type *base, uint32_t interruptMask); + +__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SetSpiInterruptMask (CySCB_Type *base, uint32_t interruptMask); +__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask (CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_ClearSpiInterrupt (CySCB_Type *base, uint32_t interruptMask); + + +/*************************************** +* Internal Function Prototypes +***************************************/ + +/** \cond INTERNAL */ +void Cy_SCB_ReadArrayNoCheck (CySCB_Type const *base, void *rxBuf, uint32_t size); +uint32_t Cy_SCB_ReadArray (CySCB_Type const *base, void *rxBuf, uint32_t size); +void Cy_SCB_ReadArrayBlocking (CySCB_Type const *base, void *rxBuf, uint32_t size); +uint32_t Cy_SCB_Write (CySCB_Type *base, uint32_t data); +void Cy_SCB_WriteArrayNoCheck (CySCB_Type *base, void *txBuf, uint32_t size); +uint32_t Cy_SCB_WriteArray (CySCB_Type *base, void *txBuf, uint32_t size); +void Cy_SCB_WriteArrayBlocking(CySCB_Type *base, void *txBuf, uint32_t size); +void Cy_SCB_WriteString (CySCB_Type *base, char_t const string[]); +void Cy_SCB_WriteDefaultArrayNoCheck(CySCB_Type *base, uint32_t txData, uint32_t size); +uint32_t Cy_SCB_WriteDefaultArray (CySCB_Type *base, uint32_t txData, uint32_t size); + +__STATIC_INLINE uint32_t Cy_SCB_GetFifoSize (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base); +__STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base); +__STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base); +/** \endcond */ + +/** \} group_scb_common_functions */ + +/*************************************** +* API Constants +***************************************/ + +/** +* \addtogroup group_scb_common_macro +* \{ +*/ + +/** Driver major version */ +#define CY_SCB_DRV_VERSION_MAJOR (1) + +/** Driver minor version */ +#define CY_SCB_DRV_VERSION_MINOR (0) + +/** SCB driver identifier */ +#define CY_SCB_ID CY_PDL_DRV_ID(0x2AU) + +/** Position for SCB driver sub mode */ +#define CY_SCB_SUB_MODE_Pos (14UL) + +/** EZI2C mode identifier */ +#define CY_SCB_EZI2C_ID (0x0UL << CY_SCB_SUB_MODE_Pos) + +/** EZI2C mode identifier */ +#define CY_SCB_I2C_ID (0x1UL << CY_SCB_SUB_MODE_Pos) + +/** EZI2C mode identifier */ +#define CY_SCB_SPI_ID (0x2UL << CY_SCB_SUB_MODE_Pos) + +/** EZI2C mode identifier */ +#define CY_SCB_UART_ID (0x3UL << CY_SCB_SUB_MODE_Pos) + +/** +* \defgroup group_scb_common_macro_intr_cause SCB Interrupt Causes +* \{ +*/ +/** Interrupt from Master interrupt sources */ +#define CY_SCB_MASTER_INTR SCB_INTR_CAUSE_M_Msk + +/** Interrupt from Slave interrupt sources */ +#define CY_SCB_SLAVE_INTR SCB_INTR_CAUSE_S_Msk + +/** Interrupt from TX interrupt sources */ +#define CY_SCB_TX_INTR SCB_INTR_CAUSE_TX_Msk + +/** Interrupt from RX interrupt sources */ +#define CY_SCB_RX_INTR SCB_INTR_CAUSE_RX_Msk + +/** Interrupt from I2C externally clocked interrupt sources */ +#define CY_SCB_I2C_INTR SCB_INTR_CAUSE_I2C_EC_Msk + +/** Interrupt from SPI externally clocked interrupt sources */ +#define CY_SCB_SPI_INTR SCB_INTR_CAUSE_SPI_EC_Msk +/** \} group_scb_common_macro_intr_cause */ + +/** +* \defgroup group_scb_common_macro_tx_intr TX Interrupt Statuses +* \{ +*/ +/** +* The number of data elements in the TX FIFO is less than the value +* of the TX FIFO level +*/ +#define CY_SCB_TX_INTR_LEVEL SCB_INTR_TX_TRIGGER_Msk + +/** The TX FIFO is not full */ +#define CY_SCB_TX_INTR_NOT_FULL SCB_INTR_TX_NOT_FULL_Msk + +/** The TX FIFO is empty */ +#define CY_SCB_TX_INTR_EMPTY SCB_INTR_TX_EMPTY_Msk + +/** An attempt to write to a full TX FIFO */ +#define CY_SCB_TX_INTR_OVERFLOW SCB_INTR_TX_OVERFLOW_Msk + +/** An attempt to read from an empty TX FIFO */ +#define CY_SCB_TX_INTR_UNDERFLOW SCB_INTR_TX_UNDERFLOW_Msk + +/** The UART transfer is complete: all data elements from the TX FIFO are sent +*/ +#define CY_SCB_TX_INTR_UART_DONE SCB_INTR_TX_UART_DONE_Msk + +/** SmartCard only: UART received a NACK */ +#define CY_SCB_TX_INTR_UART_NACK SCB_INTR_TX_UART_NACK_Msk + +/** +* SmartCard only: the value on the TX line of the UART does not match the +* value on the RX line +*/ +#define CY_SCB_TX_INTR_UART_ARB_LOST SCB_INTR_TX_UART_ARB_LOST_Msk +/** \} group_scb_common_macro_tx_intr */ + +/** +* \defgroup group_scb_common_macro_rx_intr RX Interrupt Statuses +* \{ +*/ +/** +* The number of data elements in the RX FIFO is greater than the value of the +* RX FIFO level +*/ +#define CY_SCB_RX_INTR_LEVEL SCB_INTR_RX_TRIGGER_Msk + +/** The RX FIFO is not empty */ +#define CY_SCB_RX_INTR_NOT_EMPTY SCB_INTR_RX_NOT_EMPTY_Msk + +/** The RX FIFO is full */ +#define CY_SCB_RX_INTR_FULL SCB_INTR_RX_FULL_Msk + +/** An attempt to write to a full RX FIFO */ +#define CY_SCB_RX_INTR_OVERFLOW SCB_INTR_RX_OVERFLOW_Msk + +/** An attempt to read from an empty RX FIFO */ +#define CY_SCB_RX_INTR_UNDERFLOW SCB_INTR_RX_UNDERFLOW_Msk + +/** A UART framing error detected */ +#define CY_SCB_RX_INTR_UART_FRAME_ERROR SCB_INTR_RX_FRAME_ERROR_Msk + +/** A UART parity error detected */ +#define CY_SCB_RX_INTR_UART_PARITY_ERROR SCB_INTR_RX_PARITY_ERROR_Msk + +/** A UART break detected */ +#define CY_SCB_RX_INTR_UART_BREAK_DETECT SCB_INTR_RX_BREAK_DETECT_Msk +/** \} group_scb_common_macro_rx_intr */ + +/** +* \defgroup group_scb_common_macro_slave_intr Slave Interrupt Statuses +* \{ +*/ +/** +* I2C slave lost arbitration: the value driven on the SDA line is not the same +* as the value observed on the SDA line +*/ +#define CY_SCB_SLAVE_INTR_I2C_ARB_LOST SCB_INTR_S_I2C_ARB_LOST_Msk + +/** The I2C slave received a NAK */ +#define CY_SCB_SLAVE_INTR_I2C_NACK SCB_INTR_S_I2C_NACK_Msk + +/** The I2C slave received an ACK */ +#define CY_SCB_SLAVE_INTR_I2C_ACK SCB_INTR_S_I2C_ACK_Msk + +/** +* A Stop or Repeated Start event for a write transfer intended for this slave +* was detected. +*/ +#define CY_SCB_SLAVE_INTR_I2C_WRITE_STOP SCB_INTR_S_I2C_WRITE_STOP_Msk + +/** A Stop or Repeated Start event intended for this slave was detected */ +#define CY_SCB_SLAVE_INTR_I2C_STOP SCB_INTR_S_I2C_STOP_Msk + +/** The I2C slave received a Start condition */ +#define CY_SCB_SLAVE_INTR_I2C_START SCB_INTR_S_I2C_START_Msk + +/** The I2C slave received the matching address */ +#define CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH SCB_INTR_S_I2C_ADDR_MATCH_Msk + +/** The I2C Slave received the general call address */ +#define CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR SCB_INTR_S_I2C_GENERAL_Msk + +/** The I2C slave bus error (detection of unexpected Start or Stop condition) */ +#define CY_SCB_SLAVE_INTR_I2C_BUS_ERROR SCB_INTR_S_I2C_BUS_ERROR_Msk + +/** +* The SPI slave select line is deselected at an expected time during an +* SPI transfer. +*/ +#define CY_SCB_SLAVE_INTR_SPI_BUS_ERROR SCB_INTR_S_SPI_BUS_ERROR_Msk +/** \} group_scb_common_macro_slave_intr */ + +/** +* \defgroup group_scb_common_macro_master_intr Master Interrupt Statuses +* \{ +*/ +/** The I2C master's lost arbitration */ +#define CY_SCB_MASTER_INTR_I2C_ARB_LOST SCB_INTR_M_I2C_ARB_LOST_Msk + +/** The I2C master received a NACK */ +#define CY_SCB_MASTER_INTR_I2C_NACK SCB_INTR_M_I2C_NACK_Msk + +/** The I2C master received an ACK */ +#define CY_SCB_MASTER_INTR_I2C_ACK SCB_INTR_M_I2C_ACK_Msk + +/** The I2C master generated a Stop */ +#define CY_SCB_MASTER_INTR_I2C_STOP SCB_INTR_M_I2C_STOP_Msk + +/** The I2C master bus error (detection of unexpected START or STOP condition) +*/ +#define CY_SCB_MASTER_INTR_I2C_BUS_ERROR SCB_INTR_M_I2C_BUS_ERROR_Msk + +/** +* The SPI master transfer is complete: all data elements transferred from the +* TX FIFO and TX shift register. +*/ +#define CY_SCB_MASTER_INTR_SPI_DONE SCB_INTR_M_SPI_DONE_Msk +/** \} group_scb_common_macro_master_intr */ + +/** +* \defgroup group_scb_common_macro_i2c_intr I2C Interrupt Statuses +* \{ +*/ +/** +* Wake up request: the I2C slave received the matching address. +* Note that this interrupt source triggers in active mode. +*/ +#define CY_SCB_I2C_INTR_WAKEUP SCB_INTR_I2C_EC_WAKE_UP_Msk +/** \} group_scb_common_macro_i2c_intr */ + +/** +* \defgroup group_scb_common_macro_SpiIntrStatuses SPI Interrupt Statuses +* \{ +*/ +/** +* Wake up request: the SPI slave detected an active edge of the slave select +* signal. Note that this interrupt source triggers in active mode. +*/ +#define CY_SCB_SPI_INTR_WAKEUP SCB_INTR_SPI_EC_WAKE_UP_Msk +/** \} group_scb_common_macro_SpiIntrStatuses */ + + +/*************************************** +* Internal Constants +***************************************/ + +/** \cond INTERNAL */ + +/* Default registers values */ +#define CY_SCB_CTRL_DEF_VAL (0x0300000FUL) +#define CY_SCB_I2C_CTRL_DEF_VAL (0x00003F88UL) +#define CY_SCB_SPI_CTRL_DEF_VAL (0x03000000UL) +#define CY_SCB_UART_CTRL_DEF_VAL (0x00300000UL) +#define CY_SCB_UART_RX_CTRL_DEF_VAL (0x000A0002UL) +#define CY_SCB_UART_TX_CTRL_DEF_VAL (0x00000002UL) +#define CY_SCB_RX_CTRL_DEF_VAL (0x00000107UL) +#define CY_SCB_TX_CTRL_DEF_VAL (0x00000107UL) + +/* SCB CTRL modes */ +#define CY_SCB_CTRL_MODE_I2C (0UL) +#define CY_SCB_CTRL_MODE_SPI (1UL) +#define CY_SCB_CTRL_MODE_UART (2UL) + +/* SPI slave select polarity */ +#define CY_SCB_SPI_CTRL_SSEL_POLARITY_Pos SCB_SPI_CTRL_SSEL_POLARITY0_Pos +#define CY_SCB_SPI_CTRL_SSEL_POLARITY_Msk (SCB_SPI_CTRL_SSEL_POLARITY0_Msk | \ + SCB_SPI_CTRL_SSEL_POLARITY1_Msk | \ + SCB_SPI_CTRL_SSEL_POLARITY2_Msk | \ + SCB_SPI_CTRL_SSEL_POLARITY3_Msk) + +/* SPI clock modes: CPHA and CPOL */ +#define CY_SCB_SPI_CTRL_CLK_MODE_Pos SCB_SPI_CTRL_CPHA_Pos +#define CY_SCB_SPI_CTRL_CLK_MODE_Msk (SCB_SPI_CTRL_CPHA_Msk | SCB_SPI_CTRL_CPOL_Msk) + +/* UART parity and parity enable combination */ +#define CY_SCB_UART_RX_CTRL_SET_PARITY_Msk (SCB_UART_RX_CTRL_PARITY_ENABLED_Msk | \ + SCB_UART_RX_CTRL_PARITY_Msk) +#define CY_SCB_UART_RX_CTRL_SET_PARITY_Pos (SCB_UART_RX_CTRL_PARITY_Pos) + +#define CY_SCB_UART_TX_CTRL_SET_PARITY_Msk (SCB_UART_TX_CTRL_PARITY_ENABLED_Msk | \ + SCB_UART_TX_CTRL_PARITY_Msk) +#define CY_SCB_UART_TX_CTRL_SET_PARITY_Pos (SCB_UART_TX_CTRL_PARITY_Pos) + +/* Max number of bits for byte mode */ +#define CY_SCB_BYTE_WIDTH (8UL) + +/* Single unit to wait */ +#define CY_SCB_WAIT_1_UNIT (1U) + +/* Clear interrupt sources */ +#define CY_SCB_CLEAR_ALL_INTR_SRC (0UL) + +/* Hardware FIFO size */ +#define CY_SCB_FIFO_SIZE (128UL) +/** \endcond */ + +/** \} group_scb_common_macro */ + + +/*************************************** +* Inline Function Implementation +***************************************/ + +/** +* \addtogroup group_scb_common_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_SCB_ReadRxFifo +****************************************************************************//** +* +* Reads a data element directly out of the RX FIFO. +* This function does not check if the RX FIFO has data before reading it. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* Data from RX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_ReadRxFifo(CySCB_Type const *base) +{ + return (base->RX_FIFO_RD); +} + +/******************************************************************************* +* Function Name: Cy_SCB_SetRxFifoLevel +****************************************************************************//** +* +* Sets the RX FIFO level. When there are more data elements in the RX FIFO than +* this level, the RX FIFO level interrupt is triggered. +* +* \param base +* The pointer to the SCB instance. +* +* \param rxLevel +* When there are more data elements in the FIFO than this level, the RX level +* interrupt is triggered. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t rxLevel) +{ + base->RX_FIFO_CTRL = _CLR_SET_FLD32U(base->RX_FIFO_CTRL, SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, rxLevel); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetNumInRxFifo +****************************************************************************//** +* +* Returns the number of data elements currently in the RX FIFO. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The number or data elements in RX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base) +{ + return _FLD2VAL(SCB_RX_FIFO_STATUS_USED, base->RX_FIFO_STATUS); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetRxSrValid +****************************************************************************//** +* +* Returns the status of the RX FIFO Shift Register valid bit. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* 1 - RX shift register valid, 0 - RX shift register not valid. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid(CySCB_Type const *base) +{ + return _FLD2VAL(SCB_RX_FIFO_STATUS_SR_VALID, base->RX_FIFO_STATUS); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_ClearRxFifo +****************************************************************************//** +* +* Clears the RX FIFO and shifter. +* +* \param base +* The pointer to the SCB instance. +* +* \note +* If there is partial data in the shifter, it gets cleared and lost. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_ClearRxFifo(CySCB_Type* base) +{ + base->RX_FIFO_CTRL |= (uint32_t) SCB_RX_FIFO_CTRL_CLEAR_Msk; + base->RX_FIFO_CTRL &= (uint32_t) ~SCB_RX_FIFO_CTRL_CLEAR_Msk; + + (void) base->RX_FIFO_CTRL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_WriteTxFifo +****************************************************************************//** +* +* Writes data directly into the TX FIFO. +* This function does not check if the TX FIFO is not full before writing +* into it. +* +* \param base +* The pointer to the SCB instance. +* +* \param data +* Data to write to the TX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_WriteTxFifo(CySCB_Type* base, uint32_t data) +{ + base->TX_FIFO_WR = data; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetTxFifoLevel +****************************************************************************//** +* +* Sets the TX FIFO level, when there are fewer data elements in the TX FIFO than +* this level, the TX FIFO level interrupt is triggered. +* +* \param base +* The pointer to the SCB instance. +* +* \param txLevel +* When there are fewer data elements in the FIFO than this level, the TX level +* interrupt is triggered. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t txLevel) +{ + base->TX_FIFO_CTRL = _CLR_SET_FLD32U(base->TX_FIFO_CTRL, SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, txLevel); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetNumInTxFifo +****************************************************************************//** +* +* Returns the number of data elements currently in the TX FIFO. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The number or data elements in the TX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base) +{ + return _FLD2VAL(SCB_TX_FIFO_STATUS_USED, base->TX_FIFO_STATUS); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetTxSrValid +****************************************************************************//** +* +* Returns the status of the TX FIFO Shift Register valid bit. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* 1 - TX shift register valid, 0 - TX shift register not valid. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid(CySCB_Type const *base) +{ + return _FLD2VAL(SCB_TX_FIFO_STATUS_SR_VALID, base->TX_FIFO_STATUS); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_IsTxComplete +****************************************************************************//** +* +* Checks if the TX FIFO and Shifter are empty and there is no more data to send. +* +* \param base +* Pointer to SPI the SCB instance. +* +* \return +* If true, transmission complete. If false, transmission is not complete. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SCB_IsTxComplete(CySCB_Type const *base) +{ + return (0UL == (Cy_SCB_GetNumInTxFifo(base) + Cy_SCB_GetTxSrValid(base))); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_ClearTxFifo +****************************************************************************//** +* +* Clears the TX FIFO. +* +* \param base +* The pointer to the SCB instance. +* +* \note +* The TX FIFO clear operation also clears the shift register, thus the shifter +* could be cleared in the middle of a data element transfer; resulting in +* "ones" being sent on the bus for the remainder of the transfer. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_ClearTxFifo(CySCB_Type *base) +{ + base->TX_FIFO_CTRL |= (uint32_t) SCB_TX_FIFO_CTRL_CLEAR_Msk; + base->TX_FIFO_CTRL &= (uint32_t) ~SCB_TX_FIFO_CTRL_CLEAR_Msk; + + (void) base->TX_FIFO_CTRL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetByteMode +****************************************************************************//** +* +* Sets whether the RX and TX FIFOs are in byte mode. +* The FIFOs are either 16-bit wide or 8-bit wide (byte mode). +* When the FIFO is in byte mode it is twice as deep, see device datasheet +* for FIFO depths. +* +* \param base +* The pointer to the SCB instance. +* +* \param byteMode +* If true, TX and RX FIFOs are 8-bit wide. If false, the FIFOs are 16-bit wide. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode) +{ + if (byteMode) + { + base->CTRL |= SCB_CTRL_BYTE_MODE_Msk; + } + else + { + base->CTRL &= ~SCB_CTRL_BYTE_MODE_Msk; + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetInterruptCause +****************************************************************************//** +* +* Returns the mask of bits showing the source of the current triggered +* interrupt. This is useful for modes of operation where an interrupt can +* be generated by conditions in multiple interrupt source registers. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The mask with the OR of the following conditions that have been triggered. +* See \ref group_scb_common_macro_intr_cause for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base) +{ + return (base->INTR_CAUSE); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetRxInterruptStatus +****************************************************************************//** +* +* Returns the RX interrupt request register. This register contains the current +* status of the RX interrupt sources. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of the RX interrupt sources. Each constant is a bit field +* value. The value returned may have multiple bits set to indicate the +* current status. +* See \ref group_scb_common_macro_rx_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base) +{ + return (base->INTR_RX); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetRxInterruptMask +****************************************************************************//** +* +* Writes the RX interrupt mask register. This register configures which bits +* from the RX interrupt request register can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* Enabled RX interrupt sources. +* See \ref group_scb_common_macro_rx_intr. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetRxInterruptMask(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_RX_MASK = interruptMask; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetRxInterruptMask +****************************************************************************//** +* +* Returns the RX interrupt mask register. This register specifies which bits +* from the RX interrupt request register trigger can an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* Enabled RX interrupt sources. +* See \ref group_scb_common_macro_rx_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask(CySCB_Type const *base) +{ + return (base->INTR_RX_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetRxInterruptStatusMasked +****************************************************************************//** +* +* Returns the RX interrupt masked request register. This register contains +* a logical AND of corresponding bits from the RX interrupt request and +* mask registers. +* This function is intended to be used in the interrupt service routine to +* identify which of the enabled RX interrupt sources caused the interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of enabled RX interrupt sources. +* See \ref group_scb_common_macro_rx_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base) +{ + return (base->INTR_RX_MASKED); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_ClearRxInterrupt +****************************************************************************//** +* +* Clears the RX interrupt sources in the interrupt request register. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* The RX interrupt sources to be cleared. +* See \ref group_scb_common_macro_rx_intr for the set of constants. +* +* \note +* - CY_SCB_INTR_RX_FIFO_LEVEL interrupt source is not cleared when +* the RX FIFO has more entries than the level. +* - CY_SCB_INTR_RX_NOT_EMPTY interrupt source is not cleared when the +* RX FIFO is not empty. +* - CY_SCB_INTR_RX_FULL interrupt source is not cleared when the +* RX FIFO is full. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_ClearRxInterrupt(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_RX = interruptMask; + (void) base->INTR_RX; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetRxInterrupt +****************************************************************************//** +* +* Sets the RX interrupt sources in the interrupt request register. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* The RX interrupt sources to set in the RX interrupt request register. +* See \ref group_scb_common_macro_rx_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetRxInterrupt(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_RX_SET = interruptMask; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetTxInterruptStatus +****************************************************************************//** +* +* Returns the TX interrupt request register. This register contains the current +* status of the TX interrupt sources. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of TX interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* See \ref group_scb_common_macro_tx_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base) +{ + return (base->INTR_TX); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetTxInterruptMask +****************************************************************************//** +* +* Writes the TX interrupt mask register. This register configures which bits +* from the TX interrupt request register can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* Enabled TX interrupt sources. +* See \ref group_scb_common_macro_tx_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetTxInterruptMask(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_TX_MASK = interruptMask; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetTxInterruptMask +****************************************************************************//** +* +* Returns the TX interrupt mask register. This register specifies which +* bits from the TX interrupt request register can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* Enabled TX interrupt sources. +* See \ref group_scb_common_macro_tx_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask(CySCB_Type const *base) +{ + return (base->INTR_TX_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetTxInterruptStatusMasked +****************************************************************************//** +* +* Returns the TX interrupt masked request register. This register contains +* a logical AND of corresponding bits from the TX interrupt request and +* mask registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled TX interrupt sources caused the interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of enabled TX interrupt sources. +* See \ref group_scb_common_macro_tx_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base) +{ + return (base->INTR_TX_MASKED); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_ClearTxInterrupt +****************************************************************************//** +* +* Clears the TX interrupt sources in the interrupt request register. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* The TX interrupt sources to be cleared. +* See \ref group_scb_common_macro_tx_intr for the set of constants. +* +* \note +* - CY_SCB_INTR_TX_FIFO_LEVEL interrupt source is not cleared when the +* TX FIFO has less entries than the TX level. +* - CY_SCB_INTR_TX_NOT_FULL interrupt source is not cleared when the +* TX FIFO has empty entries in the TX FIFO. +* - CY_SCB_INTR_TX_EMPTY nterrupt source is not cleared when the +* TX FIFO is empty. +* - CY_SCB_INTR_TX_UNDERFLOW interrupt source is not cleared when the +* TX FIFO is empty. Put data into the TX FIFO before clearing it. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_ClearTxInterrupt(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_TX = interruptMask; + (void) base->INTR_TX; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetTxInterrupt +****************************************************************************//** +* +* Sets TX interrupt sources in the interrupt request register. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* The TX interrupt sources to set in the TX interrupt request register. +* See \ref group_scb_common_macro_tx_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetTxInterrupt(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_TX_SET = interruptMask; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetMasterInterruptStatus +****************************************************************************//** +* +* Returns the master interrupt request register. This register contains the current +* status of the master interrupt sources. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of the master interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* See \ref group_scb_common_macro_master_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus (CySCB_Type const *base) +{ + return (base->INTR_M); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetMasterInterruptMask +****************************************************************************//** +* +* Writes the master interrupt mask register. This register specifies which bits +* from the master interrupt request register can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* The master interrupt sources to be enable. +* See \ref group_scb_common_macro_master_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetMasterInterruptMask(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_M_MASK = interruptMask; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetMasterInterruptMask +****************************************************************************//** +* +* Returns the master interrupt mask register. This register specifies which bits +* from the master interrupt request register can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* Enabled master interrupt sources. +* See \ref group_scb_common_macro_master_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask(CySCB_Type const *base) +{ + return (base->INTR_M_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetMasterInterruptStatusMasked +****************************************************************************//** +* +* Returns the master interrupt masked request register. This register contains a +* logical AND of corresponding bits from the master interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of the enabled master interrupt sources caused the interrupt +* event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of enabled master interrupt sources. +* See \ref group_scb_common_macro_master_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base) +{ + return (base->INTR_M_MASKED); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_ClearMasterInterrupt +****************************************************************************//** +* +* Clears master interrupt sources in the interrupt request register. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* The master interrupt sources to be cleared. +* See \ref group_scb_common_macro_master_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_ClearMasterInterrupt(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_M = interruptMask; + (void) base->INTR_M; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetMasterInterrupt +****************************************************************************//** +* +* Sets master interrupt sources in the interrupt request register. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* The master interrupt sources to set in the master interrupt request register. +* See \ref group_scb_common_macro_master_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetMasterInterrupt(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_M_SET = interruptMask; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetSlaveInterruptStatus +****************************************************************************//** +* +* Returns the slave interrupt request register. This register contains the current +* status of the slave interrupt sources. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of the slave interrupt sources. +* Each constant is a bit field value. The value returned may have multiple +* bits set to indicate the current status. +* See \ref group_scb_common_macro_slave_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base) +{ + return (base->INTR_S); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetSlaveInterruptMask +****************************************************************************//** +* +* Writes slave interrupt mask register. +* This register specifies which bits from the slave interrupt request register +* can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* Enabled slave interrupt sources. +* See \ref group_scb_common_macro_slave_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_S_MASK = interruptMask; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetSlaveInterruptMask +****************************************************************************//** +* +* Returns the slave interrupt mask register. +* This register specifies which bits from the slave interrupt request register +* can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* Enabled slave interrupt sources. +* See \ref group_scb_common_macro_slave_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask(CySCB_Type const *base) +{ + return (base->INTR_S_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetSlaveInterruptStatusMasked +****************************************************************************//** +* +* Returns the slave interrupt masked request register. This register contains a +* logical AND of corresponding bits from the slave interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled slave interrupt sources caused the interrupt +* event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of enabled slave interrupt sources. +* See \ref group_scb_common_macro_slave_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base) +{ + return (base->INTR_S_MASKED); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_ClearSlaveInterrupt +****************************************************************************//** +* +* Clears the slave interrupt sources in the interrupt request register. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* Slave interrupt sources to be cleared. +* See \ref group_scb_common_macro_slave_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_S = interruptMask; + (void) base->INTR_S; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetSlaveInterrupt +****************************************************************************//** +* +* Sets slave interrupt sources in the interrupt request register. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* The slave interrupt sources to set in the slave interrupt request register +* See \ref group_scb_common_macro_slave_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_S_SET = interruptMask; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetI2CInterruptStatus +****************************************************************************//** +* +* Returns the I2C interrupt request register. This register contains the +* current status of the I2C interrupt sources. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of the I2C interrupt sources. Each constant is a bit +* field value. +* The value returned may have multiple bits set to indicate the current status. +* See \ref group_scb_common_macro_slave_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base) +{ + return (base->INTR_I2C_EC); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetI2CInterruptMask +****************************************************************************//** +* +* Writes the I2C interrupt mask register. This register specifies which bits +* from the I2C interrupt request register can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* Enabled I2C interrupt sources. +* See \ref group_scb_common_macro_i2c_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetI2CInterruptMask(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_I2C_EC_MASK = interruptMask; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetI2CInterruptMask +****************************************************************************//** +* +* Returns the I2C interrupt mask register. This register specifies which bits +* from the I2C interrupt request register can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* Enabled I2C interrupt sources. +* See \ref group_scb_common_macro_i2c_intr. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask(CySCB_Type const *base) +{ + return (base->INTR_I2C_EC_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetI2CInterruptStatusMasked +****************************************************************************//** +* +* Returns the I2C interrupt masked request register. This register contains +* a logical AND of corresponding bits from I2C interrupt request and mask +* registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled I2C interrupt sources caused the interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of enabled I2C interrupt sources. +* See \ref group_scb_common_macro_i2c_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base) +{ + return (base->INTR_I2C_EC_MASKED); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_ClearI2CInterrupt +****************************************************************************//** +* +* Clears I2C interrupt sources in the interrupt request register. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* The I2C interrupt sources to be cleared. +* See \ref group_scb_common_macro_i2c_intr for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_ClearI2CInterrupt(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_I2C_EC = interruptMask; + (void) base->INTR_I2C_EC; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetSpiInterruptStatus +****************************************************************************//** +* +* Returns the SPI interrupt request register. This register contains the current +* status of the SPI interrupt sources. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of SPI interrupt sources. Each constant is a bit field value. +* The value returned may have multiple bits set to indicate the current status +* See \ref group_scb_common_macro_SpiIntrStatuses for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base) +{ + return (base->INTR_SPI_EC); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SetSpiInterruptMask +****************************************************************************//** +* +* Writes the SPI interrupt mask register. This register specifies which +* bits from the SPI interrupt request register can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* Enabled SPI interrupt sources. +* See \ref group_scb_common_macro_SpiIntrStatuses for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SetSpiInterruptMask(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_SPI_EC_MASK = interruptMask; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetSpiInterruptMask +****************************************************************************//** +* +* Returns the SPI interrupt mask register. This register specifies which bits +* from the SPI interrupt request register can trigger an interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* Enabled SPI interrupt sources. +* See \ref group_scb_common_macro_SpiIntrStatuses for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask(CySCB_Type const *base) +{ + return (base->INTR_SPI_EC_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetSpiInterruptStatusMasked +****************************************************************************//** +* +* Returns the SPI interrupt masked request register. This register contains +* a logical AND of corresponding bits from the SPI interrupt request and +* mask registers. +* This function is intended to be used in the interrupt service routine to +* identify which of enabled SPI interrupt sources caused the interrupt event. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* The current status of enabled SPI interrupt sources. +* See \ref group_scb_common_macro_SpiIntrStatuses for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base) +{ + return (base->INTR_SPI_EC_MASKED); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_ClearSpiInterrupt +****************************************************************************//** +* +* Clears SPI interrupt sources in the interrupt request register. +* +* \param base +* The pointer to the SCB instance. +* +* \param interruptMask +* The SPI interrupt sources to be cleared. +* See \ref group_scb_common_macro_SpiIntrStatuses for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_ClearSpiInterrupt(CySCB_Type *base, uint32_t interruptMask) +{ + base->INTR_SPI_EC = interruptMask; + (void) base->INTR_SPI_EC; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetFifoSize +****************************************************************************//** +* +* Returns the RX and TX FIFO depth. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* FIFO depth. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetFifoSize(CySCB_Type const *base) +{ + return ((0UL != (SCB_CTRL_BYTE_MODE_Msk & base->CTRL)) ? + (CY_SCB_FIFO_SIZE) : (CY_SCB_FIFO_SIZE / 2UL)); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_IsRxDataWidthByte +****************************************************************************//** +* +* Returns true if the RX data width is a byte (8 bits). +* +* \param base +* The pointer to the SCB instance. +* +* \return +* True if the RX data width is a byte (8 bits). +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base) +{ + return (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, base->RX_CTRL) < CY_SCB_BYTE_WIDTH); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_IsTxDataWidthByte +****************************************************************************//** +* +* Returns true if the TX data width is a byte (8 bits). +* +* \param base +* The pointer to the SCB instance. +* +* \return +* If ture, the TX data width is a byte (8 bits). Othewise, false. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base) +{ + return (_FLD2VAL(SCB_TX_CTRL_DATA_WIDTH, base->TX_CTRL) < CY_SCB_BYTE_WIDTH); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_FwBlockReset +****************************************************************************//** +* +* Disables and enables the block to return it into the known state (default): +* FIFOs and interrupt statuses are cleared. +* +* \param base +* The pointer to the SCB instance. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base) +{ + base->CTRL &= (uint32_t) ~SCB_CTRL_ENABLED_Msk; + + /* Clean-up command registers */ + base->I2C_M_CMD = 0UL; + base->I2C_S_CMD = 0UL; + + base->CTRL |= (uint32_t) SCB_CTRL_ENABLED_Msk; + + (void) base->CTRL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_GetRxFifoLevel +****************************************************************************//** +* +* Returns the RX FIFO level when there are more words in the RX FIFO than the +* level, the RX FIFO level interrupt is triggered. +* +* \param base +* The pointer to the SCB instance. +* +* \return +* RX FIFO level. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel(CySCB_Type const *base) +{ + return _FLD2VAL(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, base->RX_FIFO_CTRL); +} +/** \} group_scb_common_functions */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_scb_common */ + +#endif /* (CY_SCB_COMMON_H) */ + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_ezi2c.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_ezi2c.c new file mode 100644 index 0000000000..e61cb2fc53 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_ezi2c.c @@ -0,0 +1,1058 @@ +/***************************************************************************//** +* \file cy_scb_ezi2c.c +* \version 1.0 +* +* Provides EZI2C API implementation of the SCB driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_scb_ezi2c.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* Function Prototypes +***************************************/ + +static void HandleErrors (CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context); +static void HandleAddress (CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context); +static void UpdateRxFifoLevel (CySCB_Type *base, uint32_t bufSize); +static void HandleDataReceive (CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context); +static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context); +static void HandleStop (CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context); +static void UpdateAddressMask (CySCB_Type *base, cy_stc_scb_ezi2c_context_t const *context); + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_Init +****************************************************************************//** +* +* Initializes the SCB for the EZI2C operation. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param config +* The pointer to the configuration structure \ref cy_stc_scb_ezi2c_config_t. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t +* allocated by the user. The structure is used during the EZI2C operation for +* internal configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_ezi2c_status_t +* +* \note +* Ensure that the SCB block is disabled before calling this function. +* +*******************************************************************************/ +cy_en_scb_ezi2c_status_t Cy_SCB_EZI2C_Init(CySCB_Type *base, cy_stc_scb_ezi2c_config_t const *config, + cy_stc_scb_ezi2c_context_t *context) +{ + cy_en_scb_ezi2c_status_t retStatus = CY_SCB_EZI2C_BAD_PARAM; + + if ((NULL != base) && (NULL != config) && (NULL != context)) + { + /* Configure the EZI2C interface */ + base->CTRL = ((config->numberOfAddresses == CY_SCB_EZI2C_TWO_ADDRESSES) ? SCB_CTRL_ADDR_ACCEPT_Msk : 0UL) | + (config->enableWakeFromSleep ? SCB_CTRL_EC_AM_MODE_Msk : 0UL) | + SCB_CTRL_BYTE_MODE_Msk; + + base->I2C_CTRL = CY_SCB_EZI2C_I2C_CTRL; + + /* Configure the RX direction */ + base->RX_CTRL = CY_SCB_EZI2C_RX_CTRL; + base->RX_FIFO_CTRL = 0UL; + + /* Set the default address and mask */ + if (config->numberOfAddresses == CY_SCB_EZI2C_ONE_ADDRESS) + { + context->address2 = 0U; + Cy_SCB_EZI2C_SetAddress1(base, config->slaveAddress1, context); + } + else + { + Cy_SCB_EZI2C_SetAddress1(base, config->slaveAddress1, context); + Cy_SCB_EZI2C_SetAddress2(base, config->slaveAddress2, context); + } + + /* Configure the TX direction */ + base->TX_CTRL = CY_SCB_EZI2C_TX_CTRL; + base->TX_FIFO_CTRL = CY_SCB_EZI2C_HALF_FIFO_SIZE; + + /* Configure interrupt sources */ + base->INTR_SPI_EC_MASK = 0UL; + base->INTR_I2C_EC_MASK = 0UL; + base->INTR_RX_MASK = 0UL; + base->INTR_TX_MASK = 0UL; + base->INTR_M_MASK = 0UL; + base->INTR_S_MASK = CY_SCB_EZI2C_SLAVE_INTR; + + /* Initialize context */ + context->status = 0UL; + context->state = CY_SCB_EZI2C_STATE_IDLE; + + context->subAddrSize = config->subAddressSize; + + context->buf1Size = 0UL; + context->buf1rwBondary = 0UL; + context->baseAddr1 = 0UL; + + context->buf1Size = 0UL; + context->buf1rwBondary = 0UL; + context->baseAddr2 = 0UL; + + retStatus = CY_SCB_EZI2C_SUCCESS; + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_DeInit +****************************************************************************//** +* +* De-initializes the SCB block, returns register values to default. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \note +* Ensure that the SCB block is disabled before calling this function. +* +*******************************************************************************/ +void Cy_SCB_EZI2C_DeInit(CySCB_Type *base) +{ + /* Returns block registers into the default state */ + base->CTRL = CY_SCB_CTRL_DEF_VAL; + base->I2C_CTRL = CY_SCB_I2C_CTRL_DEF_VAL; + + base->RX_CTRL = CY_SCB_RX_CTRL_DEF_VAL; + base->RX_FIFO_CTRL = 0UL; + base->RX_MATCH = 0UL; + + base->TX_CTRL = CY_SCB_TX_CTRL_DEF_VAL; + base->TX_FIFO_CTRL = 0UL; + + base->INTR_SPI_EC_MASK = 0UL; + base->INTR_I2C_EC_MASK = 0UL; + base->INTR_RX_MASK = 0UL; + base->INTR_TX_MASK = 0UL; + base->INTR_M_MASK = 0UL; + base->INTR_S_MASK = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_Disable +****************************************************************************//** +* +* Disables the SCB block and clears context statuses. +* Note that after the block was disabled, the TX and RX FIFOs and hardware +* statuses are cleared. Also, the hardware stops driving the output and +* ignores the input. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t +* allocated by the user. The structure is used during the EZI2C operation for +* internal configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* Calling this function when EZI2C is busy (slave was address and communicates +* with master) may cause transaction corruption because the hardware stops +* driving the output and ignores the input. It is recommenced to ensure that +* EZI2C slave is not busy before calling this function. +* +*******************************************************************************/ +void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context) +{ + base->CTRL &= (uint32_t) ~SCB_CTRL_ENABLED_Msk; + + /* Set the state to default and clear statuses */ + context->status = 0UL; + context->state = CY_SCB_EZI2C_STATE_IDLE; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_DeepSleep +****************************************************************************//** +* +* Configures the EZI2C slave to be a wake-up source from Deep Sleep on address +* match: enables wake-up interrupt. +* Note that a wake-up from the Deep Sleep option must be enabled during +* initialization. If this was not done, this function does nothing. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \note +* Not all SCB blocks are capable to be a wake-up source from Deep Sleep. +* Consult the device datasheet to determine which SCB supports this option. +* +*******************************************************************************/ +void Cy_SCB_EZI2C_DeepSleep(CySCB_Type *base) +{ + if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, base->CTRL)) + { + Cy_SCB_SetI2CInterruptMask(base, CY_SCB_I2C_INTR_WAKEUP); + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_Wakeup +****************************************************************************//** +* +* Disables the wake-up interrupt. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +*******************************************************************************/ +void Cy_SCB_EZI2C_Wakeup(CySCB_Type *base) +{ + if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, base->CTRL)) + { + Cy_SCB_SetI2CInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_GetActivity +****************************************************************************//** +* +* Returns a non-zero value if an I2C read or write cycle has occurred since the +* last time this function was called. All flags are reset to zero at the end of +* this function call, except the \ref CY_SCB_EZI2C_STATUS_BUSY. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t +* allocated by the user. The structure is used during the EZI2C operation for +* internal configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref group_scb_ezi2c_macro_get_activity. +* +*******************************************************************************/ +uint32_t Cy_SCB_EZI2C_GetActivity(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t *context) +{ + uint32_t intrState; + uint32_t locStatus; + + /* Suppress a compiler warning about unused variables */ + (void) base; + + intrState = Cy_SysLib_EnterCriticalSection(); + + locStatus = context->status; + context->status &= CY_SCB_EZI2C_STATUS_BUSY; + + Cy_SysLib_ExitCriticalSection(intrState); + + return (locStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_SetAddress1 +****************************************************************************//** +* +* Sets the primary EZI2C slave address. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param addr +* The 7-bit right justified slave address. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t +* allocated by the user. The structure is used during the EZI2C operation for +* internal configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +void Cy_SCB_EZI2C_SetAddress1(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context) +{ + context->address1 = addr; + + base->RX_MATCH = _CLR_SET_FLD32U(base->RX_MATCH, SCB_RX_MATCH_ADDR, ((uint32_t)((uint32_t) addr << 1UL))); + + UpdateAddressMask(base, context); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_GetAddress1 +****************************************************************************//** +* +* Returns the primary the EZI2C slave address. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* * \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t +* allocated by the user. The structure is used during the EZI2C operation for +* internal configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* The 7-bit right justified slave address. +* +*******************************************************************************/ +uint32_t Cy_SCB_EZI2C_GetAddress1(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return ((uint32_t) context->address1); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_SetBuffer1 +****************************************************************************//** +* +* Sets up the data buffer to be exposed to the I2C master on the primary slave +* address request. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param buf +* The pointer to data buffer. +* +* \param bufSize +* Size of buffer in bytes. +* +* \param rwBoundary +* Number of data bytes starting from the beginning of the buffer with read and +* write access. Data bytes located at rwBoundary or greater are read only. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t +* allocated by the user. The structure is used during the EZI2C operation for +* internal configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* Calling this function in the middle of a transaction intended for the primary +* slave address leads to unexpected behavior. +* +*******************************************************************************/ +void Cy_SCB_EZI2C_SetBuffer1(CySCB_Type const *base, uint8_t *buf, uint32_t bufSize, uint32_t rwBoundary, + cy_stc_scb_ezi2c_context_t *context) +{ + uint32_t intrState; + + /* Suppress a compiler warning about unused variables */ + (void) base; + + CY_ASSERT( !((NULL == buf) && (0UL == bufSize)) ); + + intrState = Cy_SysLib_EnterCriticalSection(); + + context->buf1 = buf; + context->buf1Size = bufSize; + context->buf1rwBondary = rwBoundary; + + Cy_SysLib_ExitCriticalSection(intrState); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_SetAddress2 +****************************************************************************//** +* +* Sets the secondary EZI2C slave address. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param addr +* The 7-bit right justified slave address. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t +* allocated by the user. The structure is used during the EZI2C operation for +* internal configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* Calling this function when EZI2C slave configured for one address operation +* leads to unexpected behavior because it updates address mask. +* +*******************************************************************************/ +void Cy_SCB_EZI2C_SetAddress2(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context) +{ + context->address2 = addr; + + UpdateAddressMask(base, context); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_GetAddress2 +****************************************************************************//** +* +* Returns the secondary the EZI2C slave address. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t +* allocated by the user. The structure is used during the EZI2C operation for +* internal configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* The 7-bit right justified slave address. +* +*******************************************************************************/ +uint32_t Cy_SCB_EZI2C_GetAddress2(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return ((uint32_t) context->address2); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_SetBuffer2 +****************************************************************************//** +* +* Sets up the data buffer to be exposed to the I2C master on the secondary +* slave address request. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param buf +* The pointer to data buffer. +* +* \param bufSize +* Size of buffer in bytes. +* +* \param rwBoundary +* Number of data bytes starting from the beginning of the buffer with read and +* write access. Data bytes located at rwBoundary or greater are read only. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t +* allocated by the user. The structure is used during the EZI2C operation for +* internal configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* Calling this function in the middle of a transaction intended for the +* secondary slave address leads to unexpected behavior. +* +*******************************************************************************/ +void Cy_SCB_EZI2C_SetBuffer2(CySCB_Type const *base, uint8_t *buf, uint32_t bufSize, uint32_t rwBoundary, + cy_stc_scb_ezi2c_context_t *context) +{ + uint32_t intrState; + + /* Suppress a compiler warning about unused variables */ + (void) base; + + CY_ASSERT( !((NULL == buf) && (0UL == bufSize)) ); + + intrState = Cy_SysLib_EnterCriticalSection(); + + context->buf2 = buf; + context->buf2Size = bufSize; + context->buf2rwBondary = rwBoundary; + + Cy_SysLib_ExitCriticalSection(intrState); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_Interrupt +****************************************************************************//** +* +* This is the interrupt function for the SCB configured in the EZI2C mode. +* This function must be called inside the user-defined interrupt service +* routine in order for EZI2C slave to work. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated +* by the user. The structure is used during the EZI2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +void Cy_SCB_EZI2C_Interrupt(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context) +{ + uint32_t slaveIntrStatus; + + /* Handle an I2C wake-up event */ + if (0UL != (CY_SCB_I2C_INTR_WAKEUP & Cy_SCB_GetI2CInterruptStatusMasked(base))) + { + Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP); + } + + /* Get the slave interrupt sources */ + slaveIntrStatus = Cy_SCB_GetSlaveInterruptStatusMasked(base); + + /* Handle the error conditions */ + if (0UL != (CY_SCB_EZI2C_SLAVE_INTR_ERROR & slaveIntrStatus)) + { + HandleErrors(base, context); + + Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_EZI2C_SLAVE_INTR_ERROR); + + /* Triggers stop processing to complete transaction */ + slaveIntrStatus |= CY_SCB_SLAVE_INTR_I2C_STOP; + } + else + { + if ((CY_SCB_EZI2C_STATE_RX_DATA1 == context->state) && + (0UL != (CY_SCB_SLAVE_INTR_I2C_STOP & slaveIntrStatus))) + { + /* Get data from RX FIFO after Stop is generated */ + Cy_SCB_SetRxInterrupt (base, CY_SCB_RX_INTR_LEVEL); + Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL); + } + } + + /* Handle the receive direction (master writes data) */ + if (0UL != (CY_SCB_RX_INTR_LEVEL & Cy_SCB_GetRxInterruptStatusMasked(base))) + { + HandleDataReceive(base, context); + + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); + } + + /* Handle the transaction completion */ + if (0UL != (CY_SCB_SLAVE_INTR_I2C_STOP & slaveIntrStatus)) + { + HandleStop(base, context); + + Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_I2C_STOP); + + /* Update the slave interrupt status */ + slaveIntrStatus = Cy_SCB_GetSlaveInterruptStatusMasked(base); + } + + /* Handle the address byte */ + if (0UL != (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH & slaveIntrStatus)) + { + HandleAddress(base, context); + + Cy_SCB_ClearI2CInterrupt (base, CY_SCB_I2C_INTR_WAKEUP); + Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH); + } + + /* Handle the transmit direction (master reads data) */ + if (0UL != (CY_SCB_TX_INTR_LEVEL & Cy_SCB_GetTxInterruptStatusMasked(base))) + { + HandleDataTransmit(base, context); + + Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL); + } +} + + + +/******************************************************************************* +* Function Name: HandleErrors +****************************************************************************//** +* +* Handles an error conditions. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated +* by the user. The structure is used during the EZI2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void HandleErrors(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context) +{ + context->status |= CY_SCB_EZI2C_STATUS_ERR; + + /* Drop any data available in RX FIFO */ + Cy_SCB_ClearRxFifo(base); + + /* Stop TX and RX processing */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); +} + + +/******************************************************************************* +* Function Name: HandleAddress +****************************************************************************//** +* +* Prepares the EZI2C slave for the following read or write transfer after the +* matched address was received. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated +* by the user. The structure is used during the EZI2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void HandleAddress(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context) +{ + /* Default actions: active is address1, ACK address */ + uint32_t cmd = SCB_I2C_S_CMD_S_ACK_Msk; + context->addr1Active = true; + + if (0U != context->address2) + { + /* Get address from RX FIFO and make it 7-bits */ + uint32_t address = (Cy_SCB_ReadRxFifo(base) >> 1UL); + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); + + /* Decide if address matches */ + if ((address == context->address1) || (address == context->address2)) + { + /* ACK address */ + if (address == context->address2) + { + context->addr1Active = false; + } + + /* Clear the stall stop status and enable the stop interrupt source */ + Cy_SCB_ClearSlaveInterrupt (base, CY_SCB_SLAVE_INTR_I2C_STOP); + Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_EZI2C_SLAVE_INTR); + } + else + { + /* NACK address */ + cmd = SCB_I2C_S_CMD_S_NACK_Msk; + + /* Disable the stop interrupt source */ + Cy_SCB_SetI2CInterruptMask(base, CY_SCB_EZI2C_SLAVE_INTR_NO_STOP); + } + } + + /* Clean-up TX FIFO before continue transaction */ + Cy_SCB_ClearTxFifo(base); + + /* Set the command to an ACK or NACK address */ + base->I2C_S_CMD = cmd; + + if (cmd == SCB_I2C_S_CMD_S_ACK_Msk) + { + context->status |= CY_SCB_EZI2C_STATUS_BUSY; + + /* Prepare for a transaction */ + if (_FLD2BOOL(SCB_I2C_STATUS_S_READ,base->I2C_STATUS)) + { + /* Master read data from slave */ + context->state = CY_SCB_EZI2C_STATE_TX_DATA; + + /* Prepare buffer to transmit */ + if (context->addr1Active) + { + context->curBuf = &context->buf1[context->baseAddr1]; + context->bufSize = context->buf1Size - context->baseAddr1; + } + else + { + context->curBuf = &context->buf2[context->baseAddr2]; + context->bufSize = context->buf2Size - context->baseAddr2; + } + + Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); + } + else + { + /* Master writes data into slave */ + context->state = CY_SCB_EZI2C_STATE_RX_OFFSET_MSB; + + context->bufSize = ((context->addr1Active) ? context->buf1Size : context->buf2Size); + + Cy_SCB_SetRxFifoLevel (base, 0UL); + Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL); + } + } +} + + +/******************************************************************************* +* Function Name: HandleDataReceive +****************************************************************************//** +* +* Updates RX FIFO level to trigger next read from it. It also manages +* auto data NACK feature. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param bufSize +* Size of buffer in bytes. +* +*******************************************************************************/ +static void UpdateRxFifoLevel(CySCB_Type *base, uint32_t bufSize) +{ + uint32_t level; + + if (bufSize > CY_SCB_EZI2C_FIFO_SIZE) + { + /* Continue transaction: there is a space in the buffer */ + level = (bufSize - CY_SCB_EZI2C_FIFO_SIZE); + level = ((level > CY_SCB_EZI2C_FIFO_SIZE) ? CY_SCB_EZI2C_HALF_FIFO_SIZE : level) - 1UL; + } + else + { + /* Prepare to end transaction: after FIFO becomes full NACK next byte. + * NACKed byte is dropped by the hardware. + */ + base->I2C_CTRL |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk; + + level = ((bufSize == 0UL) ? (0UL) : (bufSize - 1UL)); + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } + + Cy_SCB_SetRxFifoLevel(base, level); +} + + +/******************************************************************************* +* Function Name: HandleDataReceive +****************************************************************************//** +* +* Handles data reading from the RX FIFO. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated +* by the user. The structure is used during the EZI2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context) +{ + switch(context->state) + { + case CY_SCB_EZI2C_STATE_RX_OFFSET_MSB: + case CY_SCB_EZI2C_STATE_RX_OFFSET_LSB: + { + /* Default actions: compare base address and ACK it */ + bool checkBaseAddr = true; + + /* Get base address from RX FIFO */ + uint32_t baseAddr = Cy_SCB_ReadRxFifo(base); + + if (context->subAddrSize == CY_SCB_EZI2C_SUB_ADDR16_BITS) + { + if (context->state == CY_SCB_EZI2C_STATE_RX_OFFSET_MSB) + { + /* ACK base address MSB */ + base->I2C_S_CMD = SCB_I2C_S_CMD_S_ACK_Msk; + + /* Temporary store base address MSB */ + context->idx = (uint32_t) (baseAddr << 8UL); + + /* Do not compare until 16 bits are received */ + checkBaseAddr = false; + context->state = CY_SCB_EZI2C_STATE_RX_OFFSET_LSB; + } + else + { + /* Get base address (MSB | LSB) */ + baseAddr |= context->idx; + } + } + + /* Check if received base address is valid */ + if (checkBaseAddr) + { + uint32_t cmd = SCB_I2C_S_CMD_S_ACK_Msk; + + /* Decide if base address within buffer range */ + if (baseAddr < context->bufSize) + { + /* Accept new base address */ + if (context->addr1Active) + { + context->baseAddr1 = baseAddr; + } + else + { + context->baseAddr2 = baseAddr; + } + + /* Store base address to use it later */ + context->idx = baseAddr; + } + else + { + /* Restore valid base address */ + context->idx = ((context->addr1Active) ? context->baseAddr1 : context->baseAddr2); + + /* Base address is out of range - NACK it */ + cmd = SCB_I2C_S_CMD_S_NACK_Msk; + } + + /* Set the command to an ACK or NACK address */ + base->I2C_S_CMD = cmd; + + if (cmd == SCB_I2C_S_CMD_S_ACK_Msk) + { + /* Prepare buffer for a write */ + if (context->addr1Active) + { + context->curBuf = &context->buf1[context->baseAddr1]; + context->bufSize = ((context->baseAddr1 < context->buf1rwBondary) ? + (context->buf1rwBondary - context->baseAddr1) : (0UL)); + } + else + { + context->curBuf = &context->buf2[context->baseAddr2]; + context->bufSize = ((context->baseAddr2 < context->buf2rwBondary) ? + (context->buf2rwBondary - context->baseAddr2) : (0UL)); + } + + /* Choice receive scheme */ + if ((0U != context->address2) || (context->bufSize < CY_SCB_EZI2C_FIFO_SIZE)) + { + /* Handle each byte separately */ + context->state = CY_SCB_EZI2C_STATE_RX_DATA0; + } + else + { + /* Use RX FIFO and auto ACK/NACK features */ + base->I2C_CTRL |= SCB_I2C_CTRL_S_READY_DATA_ACK_Msk; + UpdateRxFifoLevel(base, context->bufSize); + + context->state = CY_SCB_EZI2C_STATE_RX_DATA1; + } + } + } + } + break; + + case CY_SCB_EZI2C_STATE_RX_DATA0: + { + uint32_t byte = Cy_SCB_ReadRxFifo(base); + + /* Check if there is a space to store byte */ + if (context->bufSize > 0UL) + { + /* Continue the transfer: send ACK */ + base->I2C_S_CMD = SCB_I2C_S_CMD_S_ACK_Msk; + + /* Store byte in the buffer */ + context->curBuf[0UL] = (uint8_t) byte; + --context->bufSize; + ++context->curBuf; + + /* Update base address to notice that buffer is modified */ + ++context->idx; + } + else + { + /* Finish a transfer: send a NACK. Drop received byte */ + base->I2C_S_CMD = SCB_I2C_S_CMD_S_NACK_Msk; + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } + } + break; + + case CY_SCB_EZI2C_STATE_RX_DATA1: + { + /* Get the number of bytes to read from RX FIFO */ + uint32_t numToCopy = Cy_SCB_GetRxFifoLevel(base) + 1UL; + + /* Get data from RX FIFO */ + numToCopy = Cy_SCB_ReadArray(base, context->curBuf, numToCopy); + context->bufSize -= numToCopy; + context->curBuf += numToCopy; + + /* Configure next RX FIFO read event */ + UpdateRxFifoLevel(base, context->bufSize); + + /* Update base address to notice that buffer is modified */ + ++context->idx; + } + break; + + default: + break; + } +} + + +/******************************************************************************* +* Function Name: HandleDataTransmit +****************************************************************************//** +* +* Loads the TX FIFO with data from the buffer. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated +* by the user. The structure is used during the EZI2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context) +{ + if (context->bufSize > 0UL) + { + /* Write data into TX FIFO from the buffer */ + uint32_t numToCopy = Cy_SCB_WriteArray(base, context->curBuf, context->bufSize); + context->bufSize -= numToCopy; + context->curBuf += numToCopy; + } + + if (0UL == context->bufSize) + { + /* Write default bytes into the TX FIFO */ + (void) Cy_SCB_WriteDefaultArray(base, CY_SCB_EZI2C_DEFAULT_TX, CY_SCB_EZI2C_FIFO_SIZE); + } +} + + +/******************************************************************************* +* Function Name: HandleStop +****************************************************************************//** +* +* Handles transfer completion. +* It is triggered by a stop or restart condition on the bus. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated +* by the user. The structure is used during the EZI2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void HandleStop(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context) +{ + /* Check for errors */ + if (0UL != (CY_SCB_EZI2C_STATUS_ERR & context->status)) + { + /* Re-enable SCB to get it back into know state: FIFO content and + * interrupt statuses are cleared. + */ + Cy_SCB_FwBlockReset(base); + } + + /* Clean-up hardware to be ready for the next transaction */ + if (CY_SCB_EZI2C_STATE_TX_DATA == context->state) + { + Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } + else + { + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + base->I2C_CTRL &= (uint32_t) ~(SCB_I2C_CTRL_S_READY_DATA_ACK_Msk | + SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk); + } + + /* Update statuses */ + context->status &= (uint32_t) ~CY_SCB_EZI2C_STATUS_BUSY; + + if (context->addr1Active) + { + context->status |= ((CY_SCB_EZI2C_STATE_TX_DATA == context->state) ? CY_SCB_EZI2C_STATUS_READ1 : + ((context->baseAddr1 != context->idx) ? CY_SCB_EZI2C_STATUS_WRITE1 : 0UL)); + } + else + { + context->status |= ((CY_SCB_EZI2C_STATE_TX_DATA == context->state) ? CY_SCB_EZI2C_STATUS_READ2 : + ((context->baseAddr2 != context->idx) ? CY_SCB_EZI2C_STATUS_WRITE2 : 0UL)); + } + + /* Back to idle state */ + context->state = CY_SCB_EZI2C_STATE_IDLE; +} + + +/******************************************************************************* +* Function Name: UpdateAddressMask +****************************************************************************//** +* +* Updates the slave address mask to enable the SCB hardware to receive matching +* slave addresses. +* +* \param base +* The pointer to the EZI2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_ezi2c_context_t allocated +* by the user. The structure is used during the EZI2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void UpdateAddressMask(CySCB_Type *base, cy_stc_scb_ezi2c_context_t const *context) +{ + uint32_t addrMask; + + /* Check how many addresses are used: */ + if (0U != context->address2) + { + /* If (addr1 and addr2) bit matches - mask bit equals 1, otherwise 0 */ + addrMask = (uint32_t) ~((uint32_t) context->address1 ^ (uint32_t) context->address2); + } + else + { + /* All bits have to match for singe address */ + addrMask = CY_SCB_EZI2C_ONE_ADDRESS_MASK; + } + + /* Update hardware address match */ + base->RX_MATCH = _CLR_SET_FLD32U(base->RX_MATCH, SCB_RX_MATCH_MASK, ((uint32_t) addrMask << 1UL)); +} + + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_ezi2c.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_ezi2c.h new file mode 100644 index 0000000000..1d51eaf7b9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_ezi2c.h @@ -0,0 +1,424 @@ +/***************************************************************************//** +* \file cy_scb_ezi2c.h +* \version 1.0 +* +* Provides EZI2C API declarations of the SCB driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \addtogroup group_scb_ezi2c +* \{ +* Driver API for EZI2C slave Peripheral +* +* \warning The EZI2C slave driver state is a prototype and it is not +* recommended for use. +* +* I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard. +* The two-wire hardware interface was developed by Philips Semiconductors +* (now NXP Semiconductors). +* +* The EZI2C slave peripheral driver provides an API to implement I2C slave +* device based on the SCB hardware block. This slave device emulates common +* I2C EEPROM interface that acts like a dual port memory between the external +* master and your code. I2C devices based on SCB hardware are compatible with +* I2C Standard mode, Fast mode, and Fast mode Plus specifications as defined in +* the I2C bus specification. +* +* Features: +* * An industry-standard I2C bus interface +* * Supports standard data rates of 100/400/1000 kbps +* * Emulates a common I2C EEPROM Interface +* * Acts like a dual port memory between the external master and your code +* * Supports Hardware Address Match +* * Supports two hardware addresses with separate buffers +* * Supports Wake from Deep Sleep on address match +* * Simple to set up and use. Once set up, there is no need to call EZI2C API +* at run time. +* +* \section group_scb_ezi2c_configuration Configuration Considerations +* +* To set up the EZI2C slave driver provide the configuration parameters in the +* \ref cy_stc_scb_ezi2c_config_t structure. For the slave the primary slave +* address slaveAddress1 must be provided. The other parameters are optional +* for operation. +* To initialize the driver, call the \ref Cy_SCB_EZI2C_Init function providing +* a pointer to the filled \ref cy_stc_scb_ezi2c_config_t structure and +* allocated \ref cy_stc_scb_ezi2c_context_t. The \ref Cy_SCB_EZI2C_Interrupt +* function must be called in the interrupt handler for selected the +* SCB instance and this interrupt must be enabled in the NVIC. Set up +* EZI2C slave buffers before calling \ref Cy_SCB_EZI2C_Enable using +* \ref Cy_SCB_EZI2C_SetBuffer1 or/and \ref Cy_SCB_EZI2C_SetBuffer2. Finally, +* enable EZI2C slave operation calling \ref Cy_SCB_EZI2C_Enable. +* +* The following operation might not require any EZI2C slave function calls +* because the I2C master is able to access the slave buffer and the application +* can directly access it as well. Note that this is an application level task +* to ensure buffer content integrity. +* +* The master can access buffer access: +* * The master write operations - A base address is always provided and is one +* or two bytes depending on the sub-address size configuration. This base +* address is retained and will be used for later read operations. Following +* the base address is a sequence of bytes that are written into the buffer +* starting from the base address location. The buffer index is incremented +* for each written byte, but this does not affect the base address, which is +* retained. The length of a write operation is limited by the maximum buffer +* read/write region size.\n +* When a master attempts to write outside the read/write region or past the +* end of the buffer, the last byte is NACKed. +* * A read operation always starts from the base address set by the most +* recent write operation. The buffer index is incremented for each read byte. +* Two sequential read operations start from the same base address no matter +* how many bytes were read. The length of a read operation is not limited by +* the maximum size of the data buffer. The EZI2C slave returns 0xFF bytes +* if the read operation passes the end of the buffer.\n +* Typically, a read operation requires the base address to be updated before +* starting the read. In this case, the write and read operations must be +* combined together. The I2C master may use ReStart or Stop/Start conditions +* to combine the operations. The write operation only sets only the base +* address and the following read operation will start from the new base +* address. In cases where the base address remains the same, there is no need +* for a write operation to be performed. +* +* \section group_scb_ezi2c_more_information More Information +* +* For more information on the SCB peripheral, refer to the technical reference +* manual (TRM). +* +* \section group_scb_ezi2c_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required / Advisory)Rule DescriptionDescription of Deviation(s)
14.2RAll non-null statements shall either: a) have at least one side-effect +* however executed, or b) cause control flow to change.The unused function parameters are cast to void. This statement +* has no side-effect and is used to suppress a compiler warning.
+* +* \section group_scb_ezi2c_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_scb_ezi2c_macro Macro +* \defgroup group_scb_ezi2c_functions Functions +* \defgroup group_scb_ezi2c_data_structures Data Structures +* \defgroup group_scb_ezi2c_enums Enumerated Types +*/ + +#if !defined(CY_SCB_EZI2C_H) +#define CY_SCB_EZI2C_H + +#include "cy_scb_common.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Enumerated Types +***************************************/ + +/** +* \addtogroup group_scb_ezi2c_enums +* \{ +*/ + +/** EZI2C status codes */ +typedef enum +{ + /** Operation completed successfully */ + CY_SCB_EZI2C_SUCCESS = 0x00U, + + /** One or more of input parameters are invalid */ + CY_SCB_EZI2C_BAD_PARAM = CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_EZI2C_ID | 1UL, +} cy_en_scb_ezi2c_status_t; + +/** \cond INTERNAL */ +/** EZI2C slave FSM states */ +typedef enum +{ + CY_SCB_EZI2C_STATE_IDLE, + CY_SCB_EZI2C_STATE_RX_OFFSET_MSB, + CY_SCB_EZI2C_STATE_RX_OFFSET_LSB, + CY_SCB_EZI2C_STATE_RX_DATA0, + CY_SCB_EZI2C_STATE_RX_DATA1, + CY_SCB_EZI2C_STATE_TX_DATA +} cy_en_scb_ezi2c_state_t; +/** \endcond */ +/** \} group_scb_ezi2c_enums */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_scb_ezi2c_data_structures +* \{ +*/ + +/** EZI2C Configuration Structure */ +typedef struct cy_stc_scb_ezi2c_config +{ + /** + * Number of supported addresses either (See + * \ref group_scb_ezi2c_macro_num_of_addr for the set of constants) + */ + uint32_t numberOfAddresses; + + /** The 7-bit right justified primary slave address */ + uint8_t slaveAddress1; + + /** The 7-bit right justified secondary slave address */ + uint8_t slaveAddress2; + + /** Size of sub-address, can either be 8 or 16 bits (See + * \ref group_scb_ezi2c_macro_sub_addr_size for the set of constants) + */ + uint32_t subAddressSize; + + /** + * When set, the slave will wake the device from deep sleep on an address + * match (The device datasheet must be consulted to determine which SCBs + * support this mode) + */ + bool enableWakeFromSleep; + + /** Nominal Bus data rate */ + uint32_t dataRateHz; +} cy_stc_scb_ezi2c_config_t; + +/** EZI2C Internal structure, holds data used by EZI2C functions */ +typedef struct cy_stc_scb_ezi2c_context +{ + cy_en_scb_ezi2c_state_t state; /**< Driver state */ + uint32_t status; /**< Communication status */ + + uint8_t address1; /**< Primary slave address (7-bits right justified) */ + uint8_t address2; /**< Secondary slave address (7-bits right justified) */ + uint32_t subAddrSize; /**< Sub-address size */ + + uint32_t idx; /**< Index within buffer during operation */ + uint32_t baseAddr1; /**< Valid base address for primary slave address */ + uint32_t baseAddr2; /**< Valid base address for secondary slave address */ + + bool addr1Active; /**< Defines whether request is intended to primary slave address */ + uint8_t *curBuf; /**< Pointer to the current location in buffer (while it is accessed) */ + uint32_t bufSize; /**< Specifies how many bytes in current buffer left in the buffer */ + + uint8_t *buf1; /**< Pointer to the buffer that exposed on request intended to primary slave address */ + uint32_t buf1Size; /**< Buffer size assigned to the primary slave address */ + uint32_t buf1rwBondary; /**< Read/Write boundary within the buffer assigned to the primary slave address */ + + uint8_t *buf2; /**< Pointer to the buffer that exposed on request intended to secondary slave address */ + uint32_t buf2Size; /**< Buffer size assigned to the secondary slave address */ + uint32_t buf2rwBondary; /**< Read/Write boundary within the buffer assigned to the secondary slave address */ + +} cy_stc_scb_ezi2c_context_t; +/** \} group_scb_ezi2c_data_structures */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_scb_ezi2c_functions +* \{ +*/ +/* Basic functions */ +cy_en_scb_ezi2c_status_t Cy_SCB_EZI2C_Init(CySCB_Type *base, cy_stc_scb_ezi2c_config_t const *config, + cy_stc_scb_ezi2c_context_t *context); +void Cy_SCB_EZI2C_DeInit(CySCB_Type *base); +__STATIC_INLINE void Cy_SCB_EZI2C_Enable(CySCB_Type *base); +void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context); + +/* Low power functions */ +void Cy_SCB_EZI2C_DeepSleep(CySCB_Type *base); +void Cy_SCB_EZI2C_Wakeup (CySCB_Type *base); + +uint32_t Cy_SCB_EZI2C_GetActivity(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t *context); + +/* Configuration functions for address 1 */ +void Cy_SCB_EZI2C_SetAddress1(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context); +uint32_t Cy_SCB_EZI2C_GetAddress1(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context); +void Cy_SCB_EZI2C_SetBuffer1 (CySCB_Type const *base, uint8_t *buf, uint32_t bufSize, uint32_t rwBoundary, + cy_stc_scb_ezi2c_context_t *context); + +/* Configuration functions for address 2 */ +void Cy_SCB_EZI2C_SetAddress2(CySCB_Type *base, uint8_t addr, cy_stc_scb_ezi2c_context_t *context); +uint32_t Cy_SCB_EZI2C_GetAddress2(CySCB_Type const *base, cy_stc_scb_ezi2c_context_t const *context); +void Cy_SCB_EZI2C_SetBuffer2 (CySCB_Type const *base, uint8_t *buf, uint32_t bufSize, uint32_t rwBoundary, + cy_stc_scb_ezi2c_context_t *context); + +/* Interrupt handler */ +void Cy_SCB_EZI2C_Interrupt(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context); +/** \} group_scb_ezi2c_functions */ + + +/*************************************** +* API Constants +***************************************/ + +/** +* \addtogroup group_scb_ezi2c_macro +* \{ +*/ + +/** +* \defgroup group_scb_ezi2c_macro_num_of_addr Number of Addresses +* \{ +*/ +#define CY_SCB_EZI2C_ONE_ADDRESS (0UL) /**< Only one address */ +#define CY_SCB_EZI2C_TWO_ADDRESSES (1UL) /**< Two addresses */ +/** \} group_scb_ezi2c_macro_num_of_addr */ + +/** +* \defgroup group_scb_ezi2c_macro_sub_addr_size Size of Sub-Address +* \{ +*/ +#define CY_SCB_EZI2C_SUB_ADDR8_BITS (0UL) /**< Sub-address is 8 bits */ +#define CY_SCB_EZI2C_SUB_ADDR16_BITS (1UL) /**< Sub-address is 16 bits */ +/** \} group_scb_ezi2c_macro_sub_addr_size */ + +/** +* \defgroup group_scb_ezi2c_macro_get_activity EZI2C Activity Status +* Each EZI2C slave status is encoded in a separate bit, therefore multiple bits +* may be set to indicate the current status. +* \{ +*/ + +/** Read transfer complete. The transfer intended for the primary slave address. +* The error condition status bit must be checked to ensure that read +* transfer was completed successfully. +*/ +#define CY_SCB_EZI2C_STATUS_READ1 (0x01UL) + +/** +* Write transfer complete. The buffer content was modified. The transfer +* intended for the primary slave address. +* The error condition status bit must be checked to ensure that write transfer +* was completed successfully. +*/ +#define CY_SCB_EZI2C_STATUS_WRITE1 (0x02UL) + +/** Read transfer complete. The transfer intended for the secondary slave +* address. +* The error condition status bit must be checked to ensure that read +* transfer was completed successfully. +*/ +#define CY_SCB_EZI2C_STATUS_READ2 (0x04UL) + +/** Write transfer complete. The buffer content was modified. The transfer +* intended for the primary slave address. +* The error condition status bit must be checked to ensure that write transfer +* was completed successfully. +*/ +#define CY_SCB_EZI2C_STATUS_WRITE2 (0x08UL) + +/** A transfer intended for the primary address or secondary address is in +* progress. The status bit is set after an address match and cleared +* on a Stop or ReStart condition. +*/ +#define CY_SCB_EZI2C_STATUS_BUSY (0x10UL) + +/** An error occurred during a transfer intended for the primary or secondary +* slave address. The sources of error are: misplaced Start or Stop condition or +* lost arbitration while slave drives SDA. When CY_SCB_EZI2C_STATUS_ERR is +* set the slave buffer may contain invalid byte. It is recommended to +* discard buffer content in this case. +*/ +#define CY_SCB_EZI2C_STATUS_ERR (0x20UL) +/** \} group_scb_ezi2c_macro_get_activity */ + +/** This value is returned by the slave when the buffer is not configured or +* the master requests more byte than available in the buffer. +*/ +#define CY_SCB_EZI2C_DEFAULT_TX (0xFFUL) + + +/*************************************** +* Internal Constants +***************************************/ + +/** \cond INTERNAL */ +/* Default registers values */ +#define CY_SCB_EZI2C_I2C_CTRL (SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk | SCB_I2C_CTRL_SLAVE_MODE_Msk) +#define CY_SCB_EZI2C_DATA_WIDTH (7UL) +#define CY_SCB_EZI2C_RX_CTRL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, CY_SCB_EZI2C_DATA_WIDTH) | \ + SCB_RX_CTRL_MSB_FIRST_Msk) +#define CY_SCB_EZI2C_TX_CTRL (CY_SCB_EZI2C_RX_CTRL) + +#define CY_SCB_EZI2C_SLAVE_INTR (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_STOP | \ + CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST) +/* Error interrupt sources */ +#define CY_SCB_EZI2C_SLAVE_INTR_ERROR (CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST) + +/* Disables Stop interrupt source */ +#define CY_SCB_EZI2C_SLAVE_INTR_NO_STOP (CY_SCB_EZI2C_SLAVE_INTR & ((uint32_t) ~CY_SCB_SLAVE_INTR_I2C_STOP)) + +/* FIFO size */ +#define CY_SCB_EZI2C_FIFO_SIZE (128UL) +#define CY_SCB_EZI2C_HALF_FIFO_SIZE (CY_SCB_EZI2C_FIFO_SIZE / 2UL) + +#define CY_SCB_EZI2C_ONE_ADDRESS_MASK (0xFFUL) +/** \endcond */ +/** \} group_scb_ezi2c_macro */ + + +/*************************************** +* Inline Function Implementation +***************************************/ + +/** +* \addtogroup group_scb_ezi2c_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_SCB_EZI2C_Enable +****************************************************************************//** +* +* Enables the SCB block for the EZI2C operation +* +* \param base +* The pointer to the EZI2C SCB instance. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_EZI2C_Enable(CySCB_Type *base) +{ + base->CTRL |= SCB_CTRL_ENABLED_Msk; +} +/** \} group_scb_ezi2c_functions */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_scb_ezi2c */ + +#endif /* (CY_SCB_EZI2C_H) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_i2c.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_i2c.c new file mode 100644 index 0000000000..350d7446c3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_i2c.c @@ -0,0 +1,2791 @@ +/***************************************************************************//** +* \file cy_scb_i2c.c +* \version 1.0 +* +* Provides I2C API implementation of the SCB driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_scb_i2c.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Function Prototypes +***************************************/ + +static void SlaveInterrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +static void SlaveHandleAddress (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +static void SlaveHandleDataReceive (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +static void SlaveHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +static void SlaveHandleStop (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); + +static void MasterInterrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +static void MasterHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +static void MasterHandleDataReceive (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +static void MasterHandleStop (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +static void MasterHandleComplete (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); + +static cy_en_scb_i2c_status_t HandleStatus(CySCB_Type *base, uint32_t status, + cy_stc_scb_i2c_context_t *context); +static uint32_t WaitOneUnit(uint32_t *timeout); + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_Init +****************************************************************************//** +* +* Initializes the SCB for the I2C operation. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param config +* The pointer to the configuration structure \ref cy_stc_scb_i2c_config_t. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_i2c_status_t +* +* \note +* Ensure that the SCB block is disabled before calling this function. +* +*******************************************************************************/ +cy_en_scb_i2c_status_t Cy_SCB_I2C_Init(CySCB_Type *base, cy_stc_scb_i2c_config_t const *config, cy_stc_scb_i2c_context_t *context) +{ + cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_BAD_PARAM; + + if ((NULL != base) && (NULL != config) && (NULL != context)) + { + /* Configure the I2C interface */ + base->CTRL = (config->acceptAddrInFifo ? SCB_CTRL_ADDR_ACCEPT_Msk : 0UL) | + (config->enableWakeFromSleep ? SCB_CTRL_EC_AM_MODE_Msk : 0UL) | + SCB_CTRL_BYTE_MODE_Msk; + + base->I2C_CTRL = (config->ackGeneralAddr ? 0UL : SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk) | + _VAL2FLD(CY_SCB_I2C_CTRL_MODE, config->i2cMode); + + /* Configure the RX direction */ + base->RX_CTRL = CY_SCB_I2C_RX_CTRL; + base->RX_FIFO_CTRL = (config->useRxFifo ? (CY_SCB_I2C_FIFO_SIZE - 1UL) : 0UL); + + /* Set the default address and mask */ + base->RX_MATCH = _VAL2FLD(SCB_RX_MATCH_ADDR, ((uint32_t) config->slaveAddress << 1UL)) | + _VAL2FLD(SCB_RX_MATCH_MASK, (uint32_t) config->slaveAddressMask); + + /* Configure the TX direction */ + base->TX_CTRL = CY_SCB_I2C_TX_CTRL; + base->TX_FIFO_CTRL = (config->useTxFifo ? CY_SCB_I2C_HALF_FIFO_SIZE : 1UL); + + /* Configure interrupt sources */ + base->INTR_SPI_EC_MASK = 0UL; + base->INTR_I2C_EC_MASK = 0UL; + base->INTR_RX_MASK = 0UL; + base->INTR_TX_MASK = 0UL; + base->INTR_M_MASK = 0UL; + + base->INTR_S_MASK = (0UL != (CY_SCB_I2C_SLAVE & config->i2cMode)) ? CY_SCB_I2C_SLAVE_INTR : 0UL; + + /* Initialize the context */ + context->useRxFifo = config->useRxFifo; + context->useTxFifo = config->useTxFifo; + + context->state = CY_SCB_I2C_IDLE; + + /* Master-specific */ + context->masterStatus = 0UL; + context->masterBufferIdx = 0UL; + + /* Slave-specific */ + context->slaveStatus = 0UL; + + context->slaveRxBufferIdx = 0UL; + context->slaveRxBufferSize = 0UL; + + context->slaveTxBufferIdx = 0UL; + context->slaveTxBufferSize = 0UL; + + /* Unregister callbacks */ + context->cbEvents = NULL; + context->cbAddr = NULL; + + retStatus = CY_SCB_I2C_SUCCESS; + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_DeInit +****************************************************************************//** +* +* De-initializes the SCB block, returns register values to default. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \note +* Ensure that the SCB block is disabled before calling this function. +* +*******************************************************************************/ +void Cy_SCB_I2C_DeInit(CySCB_Type *base) +{ + /* Returns block registers into the default state */ + base->CTRL = CY_SCB_CTRL_DEF_VAL; + base->I2C_CTRL = CY_SCB_I2C_CTRL_DEF_VAL; + + base->RX_CTRL = CY_SCB_RX_CTRL_DEF_VAL; + base->RX_FIFO_CTRL = 0UL; + base->RX_MATCH = 0UL; + + base->TX_CTRL = CY_SCB_TX_CTRL_DEF_VAL; + base->TX_FIFO_CTRL = 0UL; + + base->INTR_SPI_EC_MASK = 0UL; + base->INTR_I2C_EC_MASK = 0UL; + base->INTR_RX_MASK = 0UL; + base->INTR_TX_MASK = 0UL; + base->INTR_M_MASK = 0UL; + base->INTR_S_MASK = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_Disable +****************************************************************************//** +* +* Disables the SCB block and clears context statuses. +* Note that after the block is disabled, the TX and RX FIFOs and hardware +* statuses are cleared. Also, the hardware stops driving the output and +* ignores the input. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* Calling this function when I2C is busy (master preforms transaction or slave +* was address and communicates with master) may cause transaction corruption +* because the hardware stops driving the output and ignores the input. +* It is recommenced to ensure that I2C is not busy before calling this function. +* +*******************************************************************************/ +void Cy_SCB_I2C_Disable(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + base->CTRL &= (uint32_t) ~SCB_CTRL_ENABLED_Msk; + + /* Set the state to default and clear statuses */ + context->state = CY_SCB_I2C_IDLE; + context->masterStatus = 0UL; + context->slaveStatus = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_DeepSleep +****************************************************************************//** +* +* Configures the I2C slave to be a wake-up source from Deep Sleep on address +* match: configures the wake-up behavior and enables wake-up interrupt. +* Note that a wake-up from the Deep Sleep option must be enabled during +* initialization. If this was not done, this function does nothing. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param wakeupAction +* Determines the slaves behavior after a wake-up: NAKs address (master has to +* retry) or stretches the clock and continues the transaction when the device +* is awaken. +* See \ref group_scb_i2c_macro_wake_up for the set of constants. +* +* \note +* Not all SCB blocks are capable to be a wake-up source from Deep Sleep. +* Consult the device datasheet to determine which SCB supports this option. +* +*******************************************************************************/ +void Cy_SCB_I2C_DeepSleep(CySCB_Type *base, uint32_t wakeupAction) +{ + if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, base->CTRL)) + { + if (CY_SCB_I2C_WAKEUP_NACK == wakeupAction) + { + base->I2C_CTRL |= (uint32_t) SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk; + } + else + { + base->I2C_CTRL &= (uint32_t) ~SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk; + } + + Cy_SCB_SetI2CInterruptMask(base, CY_SCB_I2C_INTR_WAKEUP); + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_Wakeup +****************************************************************************//** +* +* Disables the wake-up interrupt. +* +* \param base +* The pointer to the I2C SCB instance. +* +*******************************************************************************/ +void Cy_SCB_I2C_Wakeup(CySCB_Type *base) +{ + if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, base->CTRL)) + { + Cy_SCB_SetI2CInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SetDataRate +****************************************************************************//** +* +* Configures the SCB to work at the desired data rate. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param dataRateHz +* The desired data Rate in Hz. +* +* \param scbClockkHz +* The frequency of the clock connected to the SCB in kHz. +* +* \return +* The achieved data rate in Hz. +* +* \note +* This function does not change the values of the clock divider connected +* to the SCB, it only changes the SCB clock oversample registers. If this +* function is not able to achieve the desired data rate, then the clock +* divider has to be adjusted. Call this function only while the SCB is +* disabled. For the slave, this function only checks that the attached clock is +* fast enough to meet the desired data rate, it does not change any registers. +* +*******************************************************************************/ +uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t scbClockkHz) +{ + uint32_t actDataRate = 1UL; + + if (CY_SCB_I2C_SLAVE == _FLD2VAL(CY_SCB_I2C_CTRL_MODE, base->I2C_CTRL)) + { + actDataRate = Cy_SCB_I2C_GetDataRate(base, scbClockkHz); + + /* Use an analog filter */ + base->RX_CTRL &= (uint32_t) SCB_RX_CTRL_MEDIAN_Msk; + base->I2C_CFG = CY_SCB_I2C_ENABLE_ANALOG_FITLER; + } + else + { + uint32_t idx = 0UL; + uint32_t dutyCycleLow; + uint32_t dutyCycleHigh; + + uint32_t fstpClockMin = (CY_SCB_I2C_MASTER == _FLD2VAL(CY_SCB_I2C_CTRL_MODE, base->I2C_CTRL)) ? + CY_SCB_I2C_MASTER_FSTP_MIN : CY_SCB_I2C_SLAVE_FSTP_CLK_MIN; + + /* Check the clock to be in the range and set the minimum duty cycle */ + if ((scbClockkHz >= CY_SCB_I2C_MASTER_STD_CLK_MIN) && (scbClockkHz <= CY_SCB_I2C_MASTER_STD_CLK_MAX)) + { + dutyCycleLow = CY_SCB_I2C_MASTER_STD_LOW_MIN; + dutyCycleHigh = CY_SCB_I2C_MASTER_STD_HIGH_MIN; + } + else if ((scbClockkHz >= CY_SCB_I2C_MASTER_FST_MIN) && (scbClockkHz <= CY_SCB_I2C_MASTER_FST_MIN)) + { + dutyCycleLow = CY_SCB_I2C_MASTER_FST_LOW_MIN; + dutyCycleHigh = CY_SCB_I2C_MASTER_FST_HIGH_MIN; + } + else if ((scbClockkHz >= fstpClockMin) && (scbClockkHz <= CY_SCB_I2C_MASTER_FSTP_MAX)) + { + dutyCycleLow = CY_SCB_I2C_MASTER_FSTP_LOW_MIN; + dutyCycleHigh = CY_SCB_I2C_MASTER_FSTP_HIGH_MIN; + } + else + { + /* The clock frequency is too low or it gets to the gap between + * the Fast and Fast Plus data rates + */ + actDataRate = 0UL; + } + + if (actDataRate > 0UL) + { + /* Adjust the duty cycle low and high to reach the requested data rate */ + do + { + /* Calculate the actual data rate */ + actDataRate = (1000U * scbClockkHz) / (dutyCycleLow + dutyCycleHigh); + + if (actDataRate > dataRateHz) + { + /* Increment the duty cycle low or high */ + if (0UL == (idx & 0x1U)) + { + if (dutyCycleLow < CY_SCB_I2C_PHASE_DUTY_CYCLE_MAX) + { + ++dutyCycleLow; + } + } + else + { + if (dutyCycleHigh < CY_SCB_I2C_PHASE_DUTY_CYCLE_MAX) + { + ++dutyCycleHigh; + } + + if (dutyCycleLow == CY_SCB_I2C_PHASE_DUTY_CYCLE_MAX) + { + ++idx; + } + } + + ++idx; + } + else + { + break; + } + } + while ((dutyCycleLow + dutyCycleHigh) < CY_SCB_I2C_DUTY_CYCLE_MAX); + + /* Configure the duty cycle low and high */ + Cy_SCB_I2C_MasterSetLowPhaseDutyCycle (base, dutyCycleLow); + Cy_SCB_I2C_MasterSetHighPhaseDutyCycle(base, dutyCycleHigh); + + /* Update the actual data rate for the case when the low and high duty cycle are max values */ + actDataRate = (1000U * scbClockkHz) / (dutyCycleLow + dutyCycleHigh); + + /* Update the filter settings */ + if (actDataRate > CY_SCB_I2C_SLAVE_FST_DATA_RATE) + { + /* Use a digital filter */ + base->RX_CTRL |= (uint32_t) SCB_RX_CTRL_MEDIAN_Msk; + base->I2C_CFG = CY_SCB_I2C_DISABLE_ANALOG_FITLER; + } + else + { + /* Use an analog filter */ + base->RX_CTRL &= (uint32_t) SCB_RX_CTRL_MEDIAN_Msk; + base->I2C_CFG = CY_SCB_I2C_ENABLE_ANALOG_FITLER; + } + } + } + + return (actDataRate); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_GetDataRate +****************************************************************************//** +* +* Returns the data rate for the selected SCB block. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param scbClockkHz +* The frequency of the clock connected to the SCB in kHz. +* +* \return +* The data rate in Hz. +* +*******************************************************************************/ +uint32_t Cy_SCB_I2C_GetDataRate(CySCB_Type const *base, uint32_t scbClockkHz) +{ + uint32_t actDataRate; + + if (_FLD2VAL(CY_SCB_I2C_CTRL_MODE, base->I2C_CTRL) == CY_SCB_I2C_SLAVE) + { + /* Check the clock frequency range to get maximum supported data rate */ + if ((scbClockkHz >= CY_SCB_I2C_SLAVE_FST_CLK_MIN) && (scbClockkHz <= CY_SCB_I2C_SLAVE_FST_CLK_MAX)) + { + actDataRate = CY_SCB_I2C_SLAVE_FST_DATA_RATE; + } + else if ((scbClockkHz >= CY_SCB_I2C_SLAVE_STD_CLK_MIN) && (scbClockkHz <= CY_SCB_I2C_SLAVE_STD_CLK_MAX)) + { + actDataRate = CY_SCB_I2C_SLAVE_STD_DATA_RATE; + } + else if ((scbClockkHz >= CY_SCB_I2C_SLAVE_FSTP_CLK_MIN) && (scbClockkHz <= CY_SCB_I2C_SLAVE_FSTP_CLK_MAX)) + { + actDataRate = CY_SCB_I2C_SLAVE_FST_DATA_RATE; + } + else + { + /* The clock frequency is too low or it gets to the gap between + * Fast and Fast Plus data rates. + */ + actDataRate = 0UL; + } + } + else + { + uint32_t dutyCycle; + + dutyCycle = (_FLD2VAL(SCB_I2C_CTRL_LOW_PHASE_OVS, base->I2C_CTRL) + 1U); + dutyCycle += (_FLD2VAL(SCB_I2C_CTRL_HIGH_PHASE_OVS, base->I2C_CTRL) + 1U); + + /* Calculate the actual data rate */ + actDataRate = (1000UL * scbClockkHz) / dutyCycle; + } + + return (actDataRate); +} + + +/******************************************************************************* +* I2C Slave API +*******************************************************************************/ + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveGetStatus +****************************************************************************//** +* +* Returns the current I2C slave status. +* This status is a bit mask and the value returned may have multiple bits set. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref group_scb_i2c_macro_slave_status. +* +*******************************************************************************/ +uint32_t Cy_SCB_I2C_SlaveGetStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->slaveStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveConfigReadBuf +****************************************************************************//** +* +* Configures the buffer pointer and the read buffer size. This is the buffer +* that the master reads data from. After this function is called, data +* transfer from the read buffer to the master is handled by +* \ref Cy_SCB_I2C_Interrupt. +* +* When Read transaction is completed (master generated Stop, ReStart or +* error occurred), the \ref CY_SCB_I2C_SLAVE_RD_BUSY status is cleared and +* the \ref CY_SCB_I2C_SLAVE_RD_CMPLT is set, also +* the \ref CY_SCB_I2C_SLAVE_RD_CMPLT_EVENT event is generated. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param rdBuf +* The pointer to the buffer with data to be read by the master. +* +* \param size +* An amount of data the master can read from rdBuf. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* * The Read buffer must not be modified and stay allocated until it has been +* read by the master. +* * If this function has not been called, and the master tries to read data +* from the slave a \ref CY_SCB_I2C_DEFAULT_TX is returned to the master. +* * If the master tries to read more bytes than available in the Read buffer, +* a \ref CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT event occurs. The +* \ref CY_SCB_I2C_DEFAULT_TX is returned to the master if the buffer remains +* empty after an event notification. +* +*******************************************************************************/ +void Cy_SCB_I2C_SlaveConfigReadBuf(CySCB_Type const *base, uint8_t *rdBuf, uint32_t size, + cy_stc_scb_i2c_context_t *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + if (NULL != rdBuf) + { + context->slaveTxBuffer = rdBuf; + context->slaveTxBufferSize = size; + context->slaveTxBufferIdx = 0UL; + context->slaveTxBufferCnt = 0UL; + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveAbortRead +****************************************************************************//** +* +* Aborts the configured slave read buffer to be read by the master. +* If the master reads and "abort operation" is requested, the +* \ref CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT event occurs. The +* \ref CY_SCB_I2C_DEFAULT_TX is returned to the master if the buffer remains +* empty after the event notification. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \sideeffect +* If the TX FIFO is used, this function clears it. +* The TX FIFO clear operation also clears the shift register, thus +* the shifter can be cleared in the middle of a data element transfer, +* corrupting it. The data element corruption means that all bits which has +* not been transmitted are transmitted as "ones" on the bus. +* +*******************************************************************************/ +void Cy_SCB_I2C_SlaveAbortRead(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t intrState; + + /* Suppress a compiler warning about unused variables */ + (void) base; + + intrState = Cy_SysLib_EnterCriticalSection(); + + /* Reset index to make write buffer empty */ + context->slaveTxBufferSize = 0UL; + + if ((context->useTxFifo) && + (0UL != (CY_SCB_I2C_SLAVE_RD_BUSY & context->slaveStatus))) + { + /* Clear TX FIFO from available data */ + Cy_SCB_ClearTxFifo(base); + } + + Cy_SysLib_ExitCriticalSection(intrState); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveGetReadTransferCount +****************************************************************************//** +* +* Returns the number of bytes read by the master since the last time +* \ref Cy_SCB_I2C_SlaveConfigReadBuf is called. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* The number of bytes read by the master. +* +* \note +* * This function returns an invalid value if read transaction was +* aborted or any of listed events occurred during the transaction: +* \ref CY_SCB_I2C_SLAVE_ARB_LOST, \ref CY_SCB_I2C_SLAVE_BUS_ERR. +* * This number is updated only when a transaction completes, either through +* an error or successfully. +* +*******************************************************************************/ +uint32_t Cy_SCB_I2C_SlaveGetReadTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->slaveTxBufferCnt); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveClearReadStatus +****************************************************************************//** +* +* Clears the read status and error conditions flags and returns their values. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref group_scb_i2c_macro_slave_status. +* +* \note +* The \ref CY_SCB_I2C_SLAVE_RD_BUSY flag is not cleared. +* +*******************************************************************************/ +uint32_t Cy_SCB_I2C_SlaveClearReadStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t retStatus; + + /* Suppress a compiler warning about unused variables */ + (void) base; + + retStatus = (context->slaveStatus & CY_SCB_I2C_SLAVE_RD_CLEAR); + context->slaveStatus &= (uint32_t) ~CY_SCB_I2C_SLAVE_RD_CLEAR; + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveConfigWriteBuf +****************************************************************************//** +* +* Configures the buffer pointer and size of the write buffer. This is the buffer +* that the master writes data to. After this function is called data transfer +* from the master into the write buffer is handled by \ref Cy_SCB_I2C_Interrupt. +* +* When write transaction is completed (master generated Stop, ReStart or +* error occurred) the \ref CY_SCB_I2C_SLAVE_WR_BUSY status is cleared and +* the \ref CY_SCB_I2C_SLAVE_WR_CMPLT is set, also +* the \ref CY_SCB_I2C_SLAVE_WR_CMPLT_EVENT event is generated. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param wrBuf +* The pointer to buffer to store data written by the master. +* +* \param size +* Size of wrBuf. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* * The write buffer must not be modified and stay allocated until it has been +* written by the master. +* * If this function has not been called and the master tries to write data +* the 1st byte is NAKed and discarded. +* * If the master writes more bytes than slave can stores in the write buffer +* the \ref CY_SCB_I2C_SLAVE_WR_OVRFL status is set and slave will NACK last +* byte, unless the RX FIFO is used. Then the slave will NAK only after +* RX FIFO becomes full. +* * If the RX FIFO is used the minimum write buffer size is automatically +* the size of the RX FIFO. If write buffer is less than RX FIFO size extra +* bytes are ACKed and stored into RX FIFO but ignored by firmware. +* +*******************************************************************************/ +void Cy_SCB_I2C_SlaveConfigWriteBuf(CySCB_Type const *base, uint8_t *wrBuf, uint32_t size, + cy_stc_scb_i2c_context_t *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + if (NULL != wrBuf) + { + context->slaveRxBuffer = wrBuf; + context->slaveRxBufferSize = size; + context->slaveRxBufferIdx = 0UL; + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveAbortWrite +****************************************************************************//** +* +* Aborts the configured slave write buffer to be written by the master. +* If master writes and "abort operation" is requested the next incoming byte will +* be NAKed. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* If the RX FIFO is used the NAK will not be sent until RX FIFO +* becomes full however bytes accepted after abort request are ignored. +* +*******************************************************************************/ +void Cy_SCB_I2C_SlaveAbortWrite(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t intrState; + + /* Suppress a compiler warning about unused variables */ + (void) base; + + intrState = Cy_SysLib_EnterCriticalSection(); + + /* Reset index to make read buffer empty */ + context->slaveRxBufferSize = 0UL; + + if ((context->useRxFifo) && + (0UL != (CY_SCB_I2C_SLAVE_WR_BUSY & context->slaveStatus))) + { + /* Configure to NACK when RX FIFO is full and disable RX level + * interrupt sources to stop getting data from RX FIFO. + */ + base->I2C_CTRL |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk; + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } + + Cy_SysLib_ExitCriticalSection(intrState); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveGetWriteTransferCount +****************************************************************************//** +* +* Returns the number of bytes written by the master since the last time +* \ref Cy_SCB_I2C_SlaveConfigWriteBuf is called. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* Number of bytes written by the master. +* +* \note +* * This function returns an invalid value if write transaction was +* aborted or any of listed events occurred during the transaction: +* \ref CY_SCB_I2C_SLAVE_ARB_LOST, \ref CY_SCB_I2C_SLAVE_BUS_ERR. +* * This number is only updated when the transaction completes, either through +* an error or successfully. +* +*******************************************************************************/ +uint32_t Cy_SCB_I2C_SlaveGetWriteTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->slaveRxBufferIdx); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveClearWriteStatus +****************************************************************************//** +* +* Clears the write status flags and error conditions flags returns and their +* values. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref group_scb_i2c_macro_slave_status. +* +* \note +* The \ref CY_SCB_I2C_SLAVE_WR_BUSY flag is not cleared. +* +*******************************************************************************/ +uint32_t Cy_SCB_I2C_SlaveClearWriteStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t retStatus; + + /* Suppress a compiler warning about unused variables */ + (void) base; + + retStatus = (context->slaveStatus & CY_SCB_I2C_SLAVE_WR_CLEAR); + context->slaveStatus &= (uint32_t) ~CY_SCB_I2C_SLAVE_WR_CLEAR; + + return (retStatus); +} + + +/******************************************************************************* +* I2C Master API: High level +*******************************************************************************/ + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterGetStatus +****************************************************************************//** +* +* Returns the current I2C master status. +* This status is a bit mask and the value returned may have multiple bits set. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref group_scb_i2c_macro_master_status. +* Note that not all I2C master statuses are returned by this function. Refer to +* more details of each status. +* +* \note +* Status is cleared by calling \ref Cy_SCB_I2C_MasterRead or +* \ref Cy_SCB_I2C_MasterWrite. +* +*******************************************************************************/ +uint32_t Cy_SCB_I2C_MasterGetStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->masterStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterRead +****************************************************************************//** +* +* This function configures the master to automatically read an entire buffer +* of data from the slave device. After the transaction is initiated by this +* function it returns and \ref Cy_SCB_I2C_Interrupt manages further data +* transfer. +* +* When a read transaction is completed (requested number of bytes are read or +* error occurred) the \ref CY_SCB_I2C_MASTER_BUSY status is cleared and +* the \ref CY_SCB_I2C_MASTER_RD_CMPLT_EVENT event is generated. +* +* Note that the master must read at least one byte. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param masterXferConfig +* Master transfer configuration structure +* \ref cy_stc_scb_i2c_master_xfer_config_t. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_i2c_status_t +* +* \note +* The buffer must not be modified and stay allocated until read operation +* completion. +* +*******************************************************************************/ +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterRead(CySCB_Type *base, + cy_stc_scb_i2c_master_xfer_config_t *masterXferConfig, + cy_stc_scb_i2c_context_t *context) +{ + cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY; + + /* Disable I2C slave interrupt sources to protect state */ + Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + if (0UL != (CY_SCB_I2C_IDLE_MASK & context->state)) + { + uint32_t intrState; + + /* Setup context */ + context->masterStatus = CY_SCB_I2C_MASTER_BUSY; + + context->masterBuffer = masterXferConfig->buffer; + context->masterBufferSize = masterXferConfig->bufferSize; + context->masterBufferIdx = 0UL; + context->masterNumBytes = 0UL; + context->masterPause = masterXferConfig->xferPending; + context->masterRdDir = true; + + /* Clean-up hardware before transfer. Note RX FIFO is empty at here */ + Cy_SCB_ClearMasterInterrupt(base, CY_SCB_I2C_MASTER_INTR_ALL); + Cy_SCB_ClearTxFifo(base); + + if (CY_SCB_I2C_IDLE == context->state) + { + /* Generate Start condition */ + base->I2C_M_CMD = SCB_I2C_M_CMD_M_START_ON_IDLE_Msk; + } + else + { + /* Generate ReStart condition. Note if previous transfer was read, + * NACK is generated before ReStart to complete it. + */ + base->I2C_M_CMD = (SCB_I2C_M_CMD_M_START_Msk | (_FLD2BOOL(SCB_I2C_STATUS_M_READ, base->I2C_STATUS) ? + SCB_I2C_M_CMD_M_NACK_Msk : 0UL)); + } + + /* Put address in TX FIFO */ + Cy_SCB_WriteTxFifo(base, (CY_SCB_I2C_READ_XFER | _VAL2FLD(CY_SCB_I2C_ADDRESS, masterXferConfig->slaveAddress))); + + /* Configure interrupt for data reception */ + if ((context->useRxFifo) && (!context->masterPause) && (context->masterBufferSize >= 2UL)) + { + /* Enable Auto data ACK */ + base->I2C_CTRL |= SCB_I2C_CTRL_M_READY_DATA_ACK_Msk; + + /* Adjust level in RX FIFO */ + Cy_SCB_SetRxFifoLevel(base, (context->masterBufferSize <= CY_SCB_I2C_FIFO_SIZE) ? + (context->masterBufferSize - 2UL) : (CY_SCB_I2C_HALF_FIFO_SIZE - 1UL)); + + context->state = CY_SCB_I2C_MASTER_RX1; + } + else + { + /* Adjust level in RX FIFO */ + Cy_SCB_SetRxFifoLevel(base, 0UL); + + context->state = CY_SCB_I2C_MASTER_RX0; + } + + /* Enable interrupt sources to continue transfer. + * Requires critical section to not cause race condition between RX and Master + * interrupt sources. + */ + intrState = Cy_SysLib_EnterCriticalSection(); + Cy_SCB_SetRxInterruptMask (base, CY_SCB_RX_INTR_LEVEL); + Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR); + Cy_SysLib_ExitCriticalSection(intrState); + + retStatus = CY_SCB_I2C_SUCCESS; + } + + /* Enable I2C slave interrupt sources */ + Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_I2C_SLAVE_INTR); + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterAbortRead +****************************************************************************//** +* +* This function requests master to abort read operation by NAKing the next byte +* and generating a Stop condition. The function does not wait until these +* actions are completed therefore next read operation can be initiated only +* after the \ref CY_SCB_I2C_MASTER_BUSY is cleared. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +******************************************************************************/ +void Cy_SCB_I2C_MasterAbortRead(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t intrState; + + intrState = Cy_SysLib_EnterCriticalSection(); + + if (0UL != (CY_SCB_I2C_MASTER_BUSY & context->masterStatus)) + { + if ((CY_SCB_I2C_MASTER_RX0 == context->state) || (CY_SCB_I2C_MASTER_RX1 == context->state)) + { + if (context->useRxFifo) + { + /* Disable RX processing */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + /* Change state and request Stop generation */ + context->state = CY_SCB_I2C_MASTER_STOP; + + /* Enable ACK interrupt source to generate Stop after Start was generated */ + Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR_ALL); + } + else + { + /* Reduce buffer to minimum value and request Stop generation */ + context->masterPause = false; + context->masterBufferSize = 1UL; + } + } + } + else + { + /* Master waits for ReStart */ + if (CY_SCB_I2C_MASTER_WAIT == context->state) + { + /* Generate NAK + Stop */ + base->I2C_M_CMD = (SCB_I2C_M_CMD_M_STOP_Msk | SCB_I2C_M_CMD_M_NACK_Msk); + } + } + + Cy_SysLib_ExitCriticalSection(intrState); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterWrite +****************************************************************************//** +* +* This function configures the master to automatically write an entire buffer +* of data to a slave device. After the transaction is initiated by this +* function it returns and \ref Cy_SCB_I2C_Interrupt manages further data +* transfer. +* +* When a write transaction is completed (requested number of bytes are written +* or error occurred) the \ref CY_SCB_I2C_MASTER_BUSY status is cleared and +* the \ref CY_SCB_I2C_MASTER_WR_CMPLT_EVENT event is generated. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param masterXferConfig +* Master transfer configuration structure +* \ref cy_stc_scb_i2c_master_xfer_config_t. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_i2c_status_t +* +* \note +* The buffer must not be modified and stay allocated until data has been +* copied into TX FIFO. +* +*******************************************************************************/ +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWrite(CySCB_Type *base, + cy_stc_scb_i2c_master_xfer_config_t *masterXferConfig, + cy_stc_scb_i2c_context_t *context) +{ + cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY; + + /* Disable I2C slave interrupt sources to protect state */ + Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + if (0UL != (CY_SCB_I2C_IDLE_MASK & context->state)) + { + uint32_t intrState; + + /* Setup context */ + context->masterStatus = CY_SCB_I2C_MASTER_BUSY; + + context->masterBuffer = masterXferConfig->buffer; + context->masterBufferSize = masterXferConfig->bufferSize; + context->masterBufferIdx = 0UL; + context->masterNumBytes = 0UL; + context->masterPause = masterXferConfig->xferPending; + context->masterRdDir = false; + + /* Clean-up hardware before transfer. Note RX FIFO is empty at here */ + Cy_SCB_ClearMasterInterrupt(base, CY_SCB_I2C_MASTER_INTR_ALL); + Cy_SCB_ClearTxFifo(base); + + if (CY_SCB_I2C_IDLE == context->state) + { + /* Generate Start condition */ + base->I2C_M_CMD = SCB_I2C_M_CMD_M_START_ON_IDLE_Msk; + } + else + { + /* Generate ReStart condition. Note if previous transfer was read, + * NACK is generated before ReStart to complete it. + */ + base->I2C_M_CMD = (SCB_I2C_M_CMD_M_START_Msk | (_FLD2BOOL(SCB_I2C_STATUS_M_READ, base->I2C_STATUS) ? + SCB_I2C_M_CMD_M_NACK_Msk : 0UL)); + } + + /* Put address in TX FIFO */ + Cy_SCB_WriteTxFifo(base, _VAL2FLD(CY_SCB_I2C_ADDRESS, masterXferConfig->slaveAddress)); + + context->state = CY_SCB_I2C_MASTER_TX; + + /* TX FIFO is empty. Set level to start transfer */ + Cy_SCB_SetTxFifoLevel(base, (context->useTxFifo) ? CY_SCB_I2C_HALF_FIFO_SIZE : (1UL)); + + /* Enable interrupt sources to continue transfer. + * Requires critical section to not cause race condition between TX and Master + * interrupt sources. + */ + intrState = Cy_SysLib_EnterCriticalSection(); + Cy_SCB_SetTxInterruptMask (base, CY_SCB_TX_INTR_LEVEL); + Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR); + Cy_SysLib_ExitCriticalSection(intrState); + + retStatus = CY_SCB_I2C_SUCCESS; + } + + /* Enable I2C slave interrupt sources */ + Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_I2C_SLAVE_INTR); + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterAbortWrite +****************************************************************************//** +* +* This function requests master to abort write operation by generating Stop +* condition. The function does not wait until this action is completed, +* therefore next write operation can be initiated only after the +* \ref CY_SCB_I2C_MASTER_BUSY is cleared. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \sideeffect +* If the TX FIFO is used it is cleared before Stop generation. +* The TX FIFO clear operation also clears shift register thus shifter +* could be cleared in the middle of a data element transfer, corrupting it. +* The remaining bits to transfer within corrupted data element are +* complemented with ones. +* +*******************************************************************************/ +void Cy_SCB_I2C_MasterAbortWrite(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t intrState; + + intrState = Cy_SysLib_EnterCriticalSection(); + + if (0UL != (CY_SCB_I2C_MASTER_BUSY & context->masterStatus)) + { + /* Disable TX processing */ + Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + if (context->useTxFifo) + { + /* Clear TX FIFO to allow Stop generation */ + Cy_SCB_ClearTxFifo(base); + } + + if ((CY_SCB_I2C_MASTER_TX == context->state) || (CY_SCB_I2C_MASTER_TX_DONE == context->state)) + { + /* Request Stop generation */ + context->state = CY_SCB_I2C_MASTER_STOP; + + /* Enable ACK interrupt source to trigger Stop generation */ + Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR_ALL); + } + } + else + { + /* Master waits for ReStart */ + if (CY_SCB_I2C_MASTER_WAIT == context->state) + { + /* Generate Stop */ + base->I2C_M_CMD = (SCB_I2C_M_CMD_M_STOP_Msk | SCB_I2C_M_CMD_M_NACK_Msk); + } + } + + Cy_SysLib_ExitCriticalSection(intrState); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterGetTransferCount +****************************************************************************//** +* +* Returns the number of bytes transferred since the last call of +* \ref Cy_SCB_I2C_MasterWrite or \ref Cy_SCB_I2C_MasterRead function. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* Number of bytes read or written by the master. +* +* \note +* * This function returns an invalid value if read or write transaction was +* aborted or any of listed events occurred during the transaction: +* \ref CY_SCB_I2C_MASTER_ARB_LOST, \ref CY_SCB_I2C_MASTER_BUS_ERR or +* \ref CY_SCB_I2C_MASTER_ABORT_START. +* +* * This number is only updated when the transaction completes, either through +* an error or successfully. +* +*******************************************************************************/ +uint32_t Cy_SCB_I2C_MasterGetTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->masterNumBytes); +} + + +/******************************************************************************* +* I2C Master API: Low level +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterSendStart +****************************************************************************//** +* +* Generates a Start condition and sends a slave address with the Read/Write bit. +* This function is blocking and it does not return until the Start condition +* and address byte are sent and a ACK/NAK is received, an error or timeout +* occurred. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param address +* 7 bit right justified slave address. +* +* \param bitRnW +* This sets the value of the Read/Write bit in the address, thus defining +* the direction of the following transfer. +* See \ref group_scb_i2c_macro_direction for the set of constants. +* +* \param timeoutMs +* Defines in milliseconds the time that this function can block for. +* If that time expires, the function returns. If a zero is passed, +* the function waits forever for the action to complete. If a timeout occurs, +* the SCB block is reset. Note The maximum value is sizeof(uint32_t)/1000. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_i2c_status_t +* +* \note +* After a Read transaction is initiated and the slave ACKs the address, at +* least one byte must be read before completing the transaction or changing +* its direction. +* +*******************************************************************************/ +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendStart(CySCB_Type *base, uint32_t address, + uint32_t bitRnW, uint32_t timeoutMs, + cy_stc_scb_i2c_context_t *context) +{ + cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY; + + /* Disable the I2C slave interrupt sources to protect the state */ + Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + if (CY_SCB_I2C_IDLE == context->state) + { + uint32_t locStatus; + + /* Convert the timeout to microseconds */ + uint32_t timeout = (timeoutMs * 1000UL); + + /* Set the read or write direction */ + context->state = CY_SCB_I2C_MASTER_ADDR; + context->masterRdDir = (CY_SCB_I2C_READ_XFER == bitRnW); + + /* Clean up the hardware before a transfer. Note RX FIFO is empty at here */ + Cy_SCB_ClearMasterInterrupt(base, CY_SCB_I2C_MASTER_INTR_ALL); + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_NOT_EMPTY); + Cy_SCB_ClearTxFifo(base); + + /* Generate a Start and send address byte */ + Cy_SCB_WriteTxFifo(base, (_VAL2FLD(CY_SCB_I2C_ADDRESS, address) | bitRnW)); + base->I2C_M_CMD = SCB_I2C_M_CMD_M_START_ON_IDLE_Msk; + + /* Wait for a completion event from the master or slave */ + do + { + locStatus = ((CY_SCB_I2C_MASTER_TX_BYTE_DONE & Cy_SCB_GetMasterInterruptStatus(base)) | + (CY_SCB_I2C_SLAVE_ADDR_DONE & Cy_SCB_GetSlaveInterruptStatus(base))); + + locStatus |= WaitOneUnit(&timeout); + + } while (0UL == locStatus); + + retStatus = HandleStatus(base, locStatus, context); + } + + /* Enable I2C slave interrupt sources */ + Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_I2C_SLAVE_INTR); + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterSendReStart +****************************************************************************//** +* +* Generates a ReStart condition and sends a slave address with the Read/Write +* bit. +* This function is blocking and it does not return until the ReStart condition +* and address byte are sent and an ACK/NAK is received, an error or timeout +* occurred. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param address +* A 7-bit right-justified slave address. +* +* \param bitRnW +* This sets the value of the Read/Write bit in the address, thus defining +* the direction of the following transfer. +* See \ref group_scb_i2c_macro_direction for the set of constants. +* +* \param timeoutMs +* Defines in milliseconds the time that this function can block for. +* If that time expires, the function returns. If a zero is passed, +* the function waits forever for the action to complete. If a timeout occurs, +* the SCB block is reset. Note The maximum value is sizeof(uint32_t)/1000. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_i2c_status_t +* +* \note +* * A successful transaction must be initiated by \ref Cy_SCB_I2C_MasterSendStart +* before calling this function. If this condition is not met, this function +* does nothing and returns \ref CY_SCB_I2C_MASTER_NOT_READY. +* * After a Read transaction is initiated and the slave ACKs the address, +* at least one byte must be read before completing the transaction or +* changing its direction. +* +*******************************************************************************/ +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendReStart(CySCB_Type *base, uint32_t address, + uint32_t bitRnW, uint32_t timeoutMs, + cy_stc_scb_i2c_context_t *context) +{ + cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY; + + if (0UL != (CY_SCB_I2C_MASTER_ACTIVE & context->state)) + { + uint32_t locStatus; + + /* Convert the timeout to microseconds */ + uint32_t timeout = (timeoutMs * 1000UL); + + /* Set the read or write direction */ + context->state = CY_SCB_I2C_MASTER_ADDR; + context->masterRdDir = (CY_SCB_I2C_READ_XFER == bitRnW); + + /* Generate a restart (for write direction) and NACK plus restart for the Read direction */ + base->I2C_M_CMD = SCB_I2C_M_CMD_M_START_Msk | + (_FLD2BOOL(SCB_I2C_STATUS_M_READ, base->I2C_STATUS) ? + SCB_I2C_M_CMD_M_NACK_Msk : 0UL); + + /* Send the address byte */ + Cy_SCB_WriteTxFifo(base, (_VAL2FLD(CY_SCB_I2C_ADDRESS, address) | bitRnW)); + + /* Wait for a completion event from the or slave */ + do + { + locStatus = ((CY_SCB_I2C_MASTER_TX_BYTE_DONE & Cy_SCB_GetMasterInterruptStatus(base)) | + (CY_SCB_I2C_SLAVE_ADDR_DONE & Cy_SCB_GetSlaveInterruptStatus(base))); + + locStatus |= WaitOneUnit(&timeout); + + } while (0UL == locStatus); + + /* Convert the status from register plus timeout to the API status */ + retStatus = HandleStatus(base, locStatus, context); + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterSendStop +****************************************************************************//** +* +* Generates a Stop condition to complete the current transaction. +* This function is blocking and it does not return until the Stop condition +* is generated, an error occurred or timeout occurred. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param timeoutMs +* Defines in milliseconds the time that this function can block for. +* If that time expires, the function returns. If a zero is passed, +* the function waits forever for the action to complete. If a timeout occurs, +* the SCB block is reset. Note The maximum value is sizeof(uint32_t)/1000. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_i2c_status_t +* +* \note +* * A successful transaction must be initiated by +* \ref Cy_SCB_I2C_MasterSendStart or \ref Cy_SCB_I2C_MasterSendReStart +* before calling this function. If this condition is not met, this function +* does nothing and returns. +* \ref CY_SCB_I2C_MASTER_NOT_READY. +* * Even after the slave NAKs the address, this function has to be called +* to complete the transaction. +* +*******************************************************************************/ +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendStop(CySCB_Type *base,uint32_t timeoutMs, + cy_stc_scb_i2c_context_t *context) +{ + cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY; + + if (0UL != (CY_SCB_I2C_MASTER_ACTIVE & context->state)) + { + uint32_t locStatus; + + /* Convert the timeout to microseconds */ + uint32_t timeout = (timeoutMs * 1000UL); + + /* Generate a stop (for Write direction) and NACK plus stop for the Read direction */ + base->I2C_M_CMD = (SCB_I2C_M_CMD_M_STOP_Msk | SCB_I2C_M_CMD_M_NACK_Msk); + + /* Wait for a completion event from the master or slave */ + do + { + locStatus = (CY_SCB_I2C_MASTER_STOP_DONE & Cy_SCB_GetMasterInterruptStatus(base)); + + locStatus |= WaitOneUnit(&timeout); + + } while (0UL == locStatus); + + /* Convert the status from register plus timeout to the API status */ + retStatus = HandleStatus(base, locStatus, context); + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterReadByte +****************************************************************************//** +* +* Reads one byte from a slave and generates an ACK or prepares to generate +* a NAK. The NAK will be generated before a Stop or ReStart condition by +* \ref Cy_SCB_I2C_MasterSendStop or \ref Cy_SCB_I2C_MasterSendReStart function +* appropriately. +* This function is blocking and it does not return until a byte is +* received, an error occurred or timeout occurred. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param ackNack +* A response to a received byte. +* See \ref group_scb_i2c_macro_ack_nack for the set of constants. +* +* \param byte +* The pointer to the location to store the Read byte. +* +* \param timeoutMs +* Defines in milliseconds the time that this function can block for. +* If that time expires, the function returns. If a zero is passed, +* the function waits forever for the action to complete. If a timeout occurs, +* the SCB block is reset. Note The maximum value is sizeof(uint32_t)/1000. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_i2c_status_t +* +* \note +* A successful transaction must be initiated by \ref Cy_SCB_I2C_MasterSendStart +* or \ref Cy_SCB_I2C_MasterSendReStart before calling this function. If this +* condition is not met, this function does nothing and returns +* \ref CY_SCB_I2C_MASTER_NOT_READY. +* +*******************************************************************************/ +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterReadByte(CySCB_Type *base, uint32_t ackNack, + uint8_t *byte, uint32_t timeoutMs, + cy_stc_scb_i2c_context_t *context) +{ + cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY; + + if (CY_SCB_I2C_MASTER_RX0 == context->state) + { + bool rxEmpty; + + uint32_t locStatus; + + /* Convert the timeout to microseconds */ + uint32_t timeout = (timeoutMs * 1000UL); + + /* Wait for ACK/NAK transmission and data byte reception */ + do + { + locStatus = (CY_SCB_I2C_MASTER_RX_BYTE_DONE & Cy_SCB_GetMasterInterruptStatus(base)); + rxEmpty = (0UL == (CY_SCB_RX_INTR_NOT_EMPTY & Cy_SCB_GetRxInterruptStatus(base))); + + locStatus |= WaitOneUnit(&timeout); + + } while ((rxEmpty) && (0UL == locStatus)); + + /* The Read byte if available */ + if (!rxEmpty) + { + /* Get the received data byte */ + *byte = (uint8_t) Cy_SCB_ReadRxFifo(base); + + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_NOT_EMPTY | CY_SCB_RX_INTR_LEVEL); + } + + /* Convert the status from register plus timeout to the API status */ + retStatus = HandleStatus(base, locStatus, context); + + if (CY_SCB_I2C_SUCCESS == retStatus) + { + /* Generate ACK or wait for NAK generation */ + if (CY_SCB_I2C_ACK == ackNack) + { + base->I2C_M_CMD = SCB_I2C_M_CMD_M_ACK_Msk; + } + } + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterWriteByte +****************************************************************************//** +* +* Sends one byte to a slave. +* This function is blocking and it does not return until a byte is +* transmitted, an error occurred or timeout occurred. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param theByte +* The byte to write to a slave. +* +* \param timeoutMs +* Defines in milliseconds the time that this function can block for. +* If that time expires, the function returns. If a zero is passed, +* the function waits forever for the action to complete. If a timeout occurs, +* the SCB block is reset. Note The maximum value is sizeof(uint32_t)/1000. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_i2c_status_t +* +* \note +* A successful transaction must be initiated by \ref Cy_SCB_I2C_MasterSendStart +* or \ref Cy_SCB_I2C_MasterSendReStart before calling this function. If this +* condition is not met, this function does nothing and returns +* \ref CY_SCB_I2C_MASTER_NOT_READY. +* +*******************************************************************************/ +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWriteByte(CySCB_Type *base, uint32_t theByte, + uint32_t timeoutMs, + cy_stc_scb_i2c_context_t *context) +{ + cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_NOT_READY; + + if (CY_SCB_I2C_MASTER_TX == context->state) + { + uint32_t locStatus; + + /* Convert the timeout to microseconds */ + uint32_t timeout = (timeoutMs * 1000UL); + + /* Send the data byte */ + Cy_SCB_WriteTxFifo(base, theByte); + + /* Wait for a completion event from the master or slave */ + do + { + locStatus = (CY_SCB_I2C_MASTER_TX_BYTE_DONE & Cy_SCB_GetMasterInterruptStatus(base)); + locStatus |= WaitOneUnit(&timeout); + + } while (0UL == locStatus); + + /* Convert the status from register plus timeout to the API status */ + retStatus = HandleStatus(base, locStatus, context); + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_Interrupt +****************************************************************************//** +* +* This is the interrupt function for the SCB configured in the I2C mode. +* This function must be called inside the user-defined interrupt service +* routine in order for higher-level functions to work: +* * Slave: Any of the slave functions. +* * Master: \ref Cy_SCB_I2C_MasterRead and \ref Cy_SCB_I2C_MasterWrite. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +void Cy_SCB_I2C_Interrupt(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + if (0UL != (CY_SCB_I2C_MASTER_ACTIVE & context->state)) + { + /* Execute a transfer as the master */ + MasterInterrupt(base, context); + } + else + { + /* Execute a transfer as the slave */ + SlaveInterrupt(base, context); + } +} + + +/******************************************************************************* +* Function Name: SlaveInterrupt +****************************************************************************//** +* +* This is the interrupt function to execute a slave transfer. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void SlaveInterrupt(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t slaveIntrStatus; + + /* Handle an I2C wake-up event */ + if (0UL != (CY_SCB_I2C_INTR_WAKEUP & Cy_SCB_GetI2CInterruptStatusMasked(base))) + { + Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP); + } + + /* Handle the slave interrupt sources */ + slaveIntrStatus = Cy_SCB_GetSlaveInterruptStatusMasked(base); + + /* Handle the error conditions */ + if (0UL != (CY_SCB_I2C_SLAVE_INTR_ERROR & slaveIntrStatus)) + { + /* Update the status */ + context->slaveStatus |= (0UL != (CY_SCB_SLAVE_INTR_I2C_BUS_ERROR & slaveIntrStatus)) ? + CY_SCB_I2C_SLAVE_BUS_ERR : CY_SCB_I2C_SLAVE_ARB_LOST; + + /* Disable the RX interrupt source to drop data into RX FIFO if any */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + /* Add the stop status to back into the default state and set completion statuses */ + slaveIntrStatus |= CY_SCB_SLAVE_INTR_I2C_STOP; + } + else + { + if (0UL != (CY_SCB_SLAVE_INTR_I2C_STOP & slaveIntrStatus)) + { + /* Get data from the RX FIFO after a stop is generated if there is + * space to store it. + */ + if ((Cy_SCB_GetNumInRxFifo(base) > 0UL) && (context->slaveRxBufferSize > 0UL)) + { + Cy_SCB_SetRxInterrupt (base, CY_SCB_RX_INTR_LEVEL); + Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL); + } + } + } + + /* Handle the receive direction (master writes data) */ + if (0UL != (CY_SCB_RX_INTR_LEVEL & Cy_SCB_GetRxInterruptStatusMasked(base))) + { + SlaveHandleDataReceive(base, context); + + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); + } + + /* Handle the transfer completion */ + if (0UL != (CY_SCB_SLAVE_INTR_I2C_STOP & slaveIntrStatus)) + { + SlaveHandleStop(base, context); + + Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_I2C_STOP); + + /* Update the slave interrupt status */ + slaveIntrStatus = Cy_SCB_GetSlaveInterruptStatusMasked(base); + } + + /* Handle the address reception */ + if (0UL != (CY_SCB_I2C_SLAVE_INTR_ADDR & slaveIntrStatus)) + { + SlaveHandleAddress(base, context); + + Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP); + Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_I2C_SLAVE_INTR_ADDR); + } + + /* Handle the transmit direction (master reads data) */ + if (0UL != (CY_SCB_I2C_SLAVE_INTR_TX & Cy_SCB_GetTxInterruptStatusMasked(base))) + { + SlaveHandleDataTransmit(base, context); + + Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL); + } +} + + +/******************************************************************************* +* Function Name: SlaveHandleAddress +****************************************************************************//** +* +* Prepares the slave for the following Read or Write transfer after the +* matched address was received. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void SlaveHandleAddress(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + /* The default command is the ACK address. It can be overridden in an address callback */ + uint32_t cmd = CY_SCB_I2C_ACK; + + /* The callback for the address in RX FIFO or a general call */ + if (NULL != context->cbAddr) + { + uint32_t events = 0UL; + + /* Set an address in the FIFO event if the address accept is enabled */ + if (_FLD2BOOL(SCB_CTRL_ADDR_ACCEPT, base->CTRL)) + { + events = (0UL != (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH & Cy_SCB_GetSlaveInterruptStatusMasked(base))) ? + CY_SCB_I2C_ADDR_IN_FIFO_EVENT : 0UL; + } + + /* Set a general call event if "ignore general call" is disabled */ + if (!_FLD2BOOL(SCB_I2C_CTRL_S_GENERAL_IGNORE, base->I2C_CTRL)) + { + events |= (0UL != (CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR & Cy_SCB_GetSlaveInterruptStatusMasked(base))) ? + CY_SCB_I2C_GENERAL_CALL_EVENT : 0UL; + } + + /* Check presence of events before involve callback */ + if (0UL != events) + { + /* Involve a callback for the address phase and get the ACK/NACK command */ + cmd = context->cbAddr(events); + + /* Clear RX level interrupt after address reception */ + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); + + if (cmd == CY_SCB_I2C_ACK) + { + /* Clear the stall stop status and enable the stop interrupt source */ + Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_I2C_STOP); + Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_I2C_SLAVE_INTR); + } + else + { + /* Disable the stop interrupt source */ + Cy_SCB_SetI2CInterruptMask(base, CY_SCB_I2C_SLAVE_INTR_NO_STOP); + } + } + } + + /* Set the command to an ACK or NACK address */ + base->I2C_S_CMD = cmd; + + if (cmd == CY_SCB_I2C_ACK) + { + bool readDirection = _FLD2BOOL(SCB_I2C_STATUS_S_READ,base->I2C_STATUS); + + /* Notify the user about start of transfer */ + if (NULL != context->cbEvents) + { + context->cbEvents(readDirection ? CY_SCB_I2C_SLAVE_READ_EVENT : CY_SCB_I2C_SLAVE_WRITE_EVENT); + } + + /* Prepare for a transfer */ + if (readDirection) + { + context->state = CY_SCB_I2C_SLAVE_TX; + context->slaveStatus |= CY_SCB_I2C_SLAVE_RD_BUSY; + + /* Prepare to transmit data */ + context->slaveTxBufferIdx = context->slaveTxBufferCnt; + context->slaveRdBufEmpty = false; + Cy_SCB_ClearTxFifo(base); + Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); + } + else + { + uint32_t level = 0UL; + + context->state = CY_SCB_I2C_SLAVE_RX; + context->slaveStatus |= CY_SCB_I2C_SLAVE_WR_BUSY; + + /* Prepare to receive data */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL); + + if (context->useRxFifo) + { + if (context->slaveRxBufferSize > 0UL) + { + /* ACK data automatically until RX FIFO is full */ + base->I2C_CTRL |= SCB_I2C_CTRL_S_READY_DATA_ACK_Msk; + + if (context->slaveRxBufferSize > CY_SCB_I2C_FIFO_SIZE) + { + /* Set a level in RX FIFO to trigger the receive interrupt source */ + level = (context->slaveRxBufferSize - CY_SCB_I2C_FIFO_SIZE); + level = (level > CY_SCB_I2C_FIFO_SIZE) ? ((CY_SCB_I2C_FIFO_SIZE / 2UL) - 1UL) : (level - 1UL); + } + else + { + /* Set a level in RX FIFO to read the number of bytes */ + level = (context->slaveRxBufferSize - 1UL); + + /* NACK when RX FIFO becomes full */ + base->I2C_CTRL |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk; + + /* Disable the RX level interrupt and wait until RX FIFO is full or stops */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } + } + } + + Cy_SCB_SetRxFifoLevel(base, level); + } + } +} + + +/******************************************************************************* +* Function Name: SlaveHandleDataReceive +****************************************************************************//** +* +* Reads data from RX FIFO into the buffer provided by +* \ref Cy_SCB_I2C_SlaveConfigWriteBuf. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void SlaveHandleDataReceive(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + /* Check if there is space to put data */ + if (context->slaveRxBufferSize > 0UL) + { + if (context->useRxFifo) + { + uint32_t level; + + /* Get the number of bytes to read from RX FIFO */ + uint32_t numToCopy = Cy_SCB_GetRxFifoLevel(base) + 1UL; + + /* Get data from RX FIFO */ + numToCopy = Cy_SCB_ReadArray(base, context->slaveRxBuffer, numToCopy); + context->slaveRxBufferIdx += numToCopy; + context->slaveRxBufferSize -= numToCopy; + context->slaveRxBuffer = &context->slaveRxBuffer[numToCopy]; + + /* Prepare to read a next chunk of data */ + if (context->slaveRxBufferSize > CY_SCB_I2C_FIFO_SIZE) + { + level = context->slaveRxBufferSize - CY_SCB_I2C_FIFO_SIZE; + level = ((level > CY_SCB_I2C_FIFO_SIZE) ? (CY_SCB_I2C_FIFO_SIZE / 2UL) : level) - 1UL; + } + else + { + base->I2C_CTRL |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk; + + level = (context->slaveRxBufferSize == 0UL) ? (0UL) : (context->slaveRxBufferSize - 1UL); + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } + + /* Set the RX level to trigger an interrupt */ + Cy_SCB_SetRxFifoLevel(base, level); + } + else + { + /* Continue the transfer: send an ACK */ + base->I2C_S_CMD = SCB_I2C_S_CMD_S_ACK_Msk; + + /* Put data into the RX buffer */ + context->slaveRxBuffer[context->slaveRxBufferIdx] = (uint8_t) Cy_SCB_ReadRxFifo(base); + ++context->slaveRxBufferIdx; + --context->slaveRxBufferSize; + } + } + else + { + /* Finish a transfer: send a NACK and discard the received byte */ + base->I2C_S_CMD = SCB_I2C_S_CMD_S_NACK_Msk; + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } +} + + +/******************************************************************************* +* Function Name: SlaveHandleDataTransmit +****************************************************************************//** +* +* Loads TX FIFO with data provided by \ref Cy_SCB_I2C_SlaveConfigReadBuf. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void SlaveHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t numToCopy; + + /* Notify the user that there is no data to send to the master. + * This event triggers once in scope of a transfer. + */ + if ((!context->slaveRdBufEmpty) && (0UL == context->slaveTxBufferSize)) + { + /* Involve a callback if registered: no data to send */ + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT); + } + + /* Update the Read buffer empty status after a callback is involved */ + context->slaveRdBufEmpty = (0UL == context->slaveTxBufferSize); + + /* Enable the TX level interrupt source to continue sending data */ + Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); + } + + /* Check if the Read buffer was updated in the callback */ + if (context->slaveRdBufEmpty) + { + /* The Read buffer is empty: copy CY_SCB_I2C_DEFAULT_TX into TX FIFO */ + numToCopy = (context->useTxFifo) ? Cy_SCB_GetFifoSize(base) : 1UL; + + numToCopy = Cy_SCB_WriteDefaultArray(base, CY_SCB_I2C_DEFAULT_TX, numToCopy); + context->slaveTxBufferIdx += numToCopy; + + context->slaveStatus |= CY_SCB_I2C_SLAVE_RD_UNDRFL; + } + else + { + if (context->slaveTxBufferSize > 1UL) + { + /* Get the number of bytes to copy into TX FIFO */ + numToCopy = (context->useTxFifo) ? (context->slaveTxBufferSize - 1UL) : (1UL); + + /* Write data into TX FIFO */ + numToCopy = Cy_SCB_WriteArray(base, context->slaveTxBuffer, numToCopy); + context->slaveTxBufferIdx += numToCopy; + context->slaveTxBufferSize -= numToCopy; + context->slaveTxBuffer = &context->slaveTxBuffer[numToCopy]; + } + + /* Put the last byte */ + if ((CY_SCB_I2C_FIFO_SIZE != Cy_SCB_GetNumInTxFifo(base)) && (1UL == context->slaveTxBufferSize)) + { + uint32_t intrStatus; + + /* Put the last data element and make sure that "TX done" will happen for it */ + intrStatus = Cy_SysLib_EnterCriticalSection(); + + Cy_SCB_WriteTxFifo(base, (uint32_t) context->slaveTxBuffer[0UL]); + Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW); + + Cy_SysLib_ExitCriticalSection(intrStatus); + + /* Move the pointers */ + ++context->slaveTxBufferIdx; + context->slaveTxBufferSize = 0UL; + context->slaveTxBuffer = &context->slaveTxBuffer[1UL]; + + /* Enable the TX underflow interrupt to catch when there is no data to send */ + Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_UNDERFLOW); + + if (context->useTxFifo) + { + /* Data is copied into TX FIFO */ + context->slaveStatus |= CY_SCB_I2C_SLAVE_RD_IN_FIFO; + + /* Involve a callback if registered: data copied into TX FIFO */ + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_I2C_SLAVE_RD_IN_FIFO_EVENT); + } + } + } + } +} + + +/******************************************************************************* +* Function Name: SlaveHandleStop +****************************************************************************//** +* +* Handles transfer completion. It is triggered by a stop or restart +* condition on the bus. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void SlaveHandleStop(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t locEvents; + + if (CY_SCB_I2C_SLAVE_RX == context->state) + { + /* If any data is left in RX FIFO, this is an overflow */ + if (Cy_SCB_GetNumInRxFifo(base) > 0UL) + { + context->slaveStatus |= CY_SCB_I2C_SLAVE_WR_OVRFL; + + if (context->useRxFifo) + { + Cy_SCB_ClearRxFifo(base); + } + else + { + (void) Cy_SCB_ReadRxFifo(base); + } + } + + locEvents = (uint32_t) CY_SCB_I2C_SLAVE_WR_CMPLT_EVENT; + context->slaveStatus |= (uint32_t) CY_SCB_I2C_SLAVE_WR_CMPLT; + context->slaveStatus &= (uint32_t) ~CY_SCB_I2C_SLAVE_WR_BUSY; + + /* Clean up the RX direction */ + base->I2C_CTRL &= (uint32_t) ~(SCB_I2C_CTRL_S_READY_DATA_ACK_Msk | + SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk); + + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); + } + else + { + /* The number of bytes left in TX FIFO */ + uint32_t size = Cy_SCB_GetNumInTxFifo(base) + Cy_SCB_GetTxSrValid(base); + + /* Get the number of bytes transferred from the read buffer */ + context->slaveTxBufferCnt = (context->slaveTxBufferIdx - size); + + /* Update buffer pointer and its size if there is no overflow */ + if (0UL == (CY_SCB_I2C_SLAVE_RD_UNDRFL & context->slaveStatus)) + { + context->slaveTxBufferSize += size; + context->slaveTxBuffer -= size; + } + + locEvents = (uint32_t) CY_SCB_I2C_SLAVE_RD_CMPLT_EVENT; + context->slaveStatus |= (uint32_t) CY_SCB_I2C_SLAVE_RD_CMPLT; + context->slaveStatus &= (uint32_t) ~CY_SCB_I2C_SLAVE_RD_BUSY; + + /* Clean up the TX direction */ + Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } + + /* Return scb into the known state after an error */ + if (0UL != (CY_SCB_I2C_SLAVE_INTR_ERROR & Cy_SCB_GetSlaveInterruptStatusMasked(base))) + { + /* After scb IP is reset, the interrupt statuses are cleared */ + Cy_SCB_FwBlockReset(base); + + locEvents |= CY_SCB_I2C_SLAVE_ERR_EVENT; + } + + /* After a stop or error, set the state to idle */ + context->state = CY_SCB_I2C_IDLE; + + /* Call a completion callback if registered */ + if (NULL != context->cbEvents) + { + context->cbEvents(locEvents); + } +} + + +/******************************************************************************* +* Function Name: MasterInterrupt +****************************************************************************//** +* +* This is the interrupt function for the SCB configured in the I2C master. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void MasterInterrupt(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t masterIntrStatus = Cy_SCB_GetMasterInterruptStatusMasked(base); + uint32_t intrCause = Cy_SCB_GetInterruptCause(base); + + /* Check if the slave is active. It can be addressed during the master set-up transfer */ + if (0UL != (CY_SCB_SLAVE_INTR & intrCause)) + { + /* Abort the transfer due to slave operation */ + if (0UL != base->I2C_M_CMD) + { + base->I2C_M_CMD = 0UL; + + context->masterStatus |= CY_SCB_I2C_MASTER_ABORT_START; + } + + context->state = CY_SCB_I2C_MASTER_CMPLT; + } + + /* Check for master error conditions */ + if (0UL != (CY_SCB_MASTER_INTR & intrCause)) + { + /* Master interrupt source is other than ACK */ + if (0UL == (CY_SCB_MASTER_INTR_I2C_ACK & masterIntrStatus)) + { + /* Skip TX processing */ + intrCause &= (uint32_t) ~CY_SCB_TX_INTR; + + /* The master has not received the acknowledgment for slave */ + if (0UL != (CY_SCB_MASTER_INTR_I2C_NACK & masterIntrStatus)) + { + /* Clear NAK interrupt source */ + Cy_SCB_ClearMasterInterrupt(base, CY_SCB_MASTER_INTR_I2C_NACK); + + /* Update status to indicate address or data NAK */ + context->masterStatus |= (0UL == (CY_SCB_MASTER_INTR_I2C_ACK & Cy_SCB_GetMasterInterruptStatus(base))) ? + CY_SCB_I2C_MASTER_ADDR_NAK : CY_SCB_I2C_MASTER_DATA_NAK; + + /* Check if end transaction was not requested before */ + if (!((CY_SCB_I2C_MASTER_WAIT_STOP == context->state) || (CY_SCB_I2C_MASTER_STOP == context->state))) + { + context->state = (context->masterPause) ? CY_SCB_I2C_MASTER_CMPLT : CY_SCB_I2C_MASTER_STOP; + } + else + { + /* Wait for Stop generation because it was requested after all + * bytes were copied into the TX FIFO. + */ + } + } + + /* Complete the transfer: stop, bus error or arbitration lost */ + if (0UL != (CY_SCB_I2C_MASTER_INTR_CMPLT & masterIntrStatus)) + { + /* The master detected a bus error condition */ + if (0UL != (CY_SCB_MASTER_INTR_I2C_BUS_ERROR & masterIntrStatus)) + { + context->masterStatus |= CY_SCB_I2C_MASTER_BUS_ERR; + } + + /* The master detected an arbitration lost condition */ + if (0UL != (CY_SCB_MASTER_INTR_I2C_ARB_LOST & masterIntrStatus)) + { + context->masterStatus |= CY_SCB_I2C_MASTER_ARB_LOST; + } + + context->state = CY_SCB_I2C_MASTER_CMPLT; + } + } + } + + if (0UL != (CY_SCB_RX_INTR & intrCause)) + { + MasterHandleDataReceive(base, context); + + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); + } + + if (0UL != (CY_SCB_TX_INTR & intrCause)) + { + MasterHandleDataTransmit(base, context); + + Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL); + } + + /* Complete the transfer */ + if (CY_SCB_I2C_MASTER_CMPLT == context->state) + { + MasterHandleComplete(base, context); + } + + /* Generate stop to complete transfer */ + if (CY_SCB_I2C_MASTER_STOP == context->state) + { + MasterHandleStop(base, context); + } +} + + +/******************************************************************************* +* Function Name: MasterHandleDataReceive +****************************************************************************//** +* +* Reads data from RX FIFO into the buffer provided by \ref Cy_SCB_I2C_MasterRead. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void MasterHandleDataReceive(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + switch (context->state) + { + case CY_SCB_I2C_MASTER_RX0: + { + /* Put data into the component buffer */ + context->masterBuffer[0UL] = (uint8_t) Cy_SCB_ReadRxFifo(base); + + ++context->masterBufferIdx; + --context->masterBufferSize; + + if (context->masterBufferSize > 0UL) + { + /* Continue the transaction: move pointer send an ACK */ + context->masterBuffer = &context->masterBuffer[1UL]; + base->I2C_M_CMD = SCB_I2C_M_CMD_M_ACK_Msk; + } + else + { + /* Complete the transaction */ + context->state = (context->masterPause) ? CY_SCB_I2C_MASTER_CMPLT : CY_SCB_I2C_MASTER_STOP; + } + } + break; + + case CY_SCB_I2C_MASTER_RX1: + { + uint32_t numToCopied; + + /* Get data from RX FIFO */ + numToCopied = Cy_SCB_ReadArray(base, context->masterBuffer, context->masterBufferSize); + context->masterBufferIdx += numToCopied; + context->masterBufferSize -= numToCopied; + context->masterBuffer = &context->masterBuffer[numToCopied]; + + if (context->masterBufferSize < 2UL) + { + /* Stop ACKing data */ + base->I2C_CTRL &= (uint32_t) ~SCB_I2C_CTRL_M_READY_DATA_ACK_Msk; + + if (1UL == context->masterBufferSize) + { + /* Catch the last byte */ + Cy_SCB_SetRxFifoLevel(base, 0UL); + + context->state = CY_SCB_I2C_MASTER_RX0; + } + else + { + /* Stop RX processing */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + context->state = CY_SCB_I2C_MASTER_STOP; + } + } + else + { + /* Continue the transfer: Adjust the level in RX FIFO */ + Cy_SCB_SetRxFifoLevel(base, (context->masterBufferSize <= CY_SCB_I2C_HALF_FIFO_SIZE) ? + (context->masterBufferSize - 2UL) : (CY_SCB_I2C_HALF_FIFO_SIZE - 1UL)); + } + } + break; + + default: + /* Do nothing: drop data into RX FIFO */ + break; + } +} + + +/******************************************************************************* +* Function Name: MasterHandleDataTransmit +****************************************************************************//** +* +* Loads TX FIFO with data provided by \ref Cy_SCB_I2C_MasterWrite. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void MasterHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + if (CY_SCB_I2C_MASTER_TX_DONE == context->state) + { + context->state = CY_SCB_I2C_MASTER_CMPLT; + } + else if (CY_SCB_I2C_MASTER_TX == context->state) + { + if (context->masterBufferSize > 1UL) + { + /* Get the number of bytes to copy into TX FIFO */ + uint32_t NumToCopy = (context->useTxFifo) ? (context->masterBufferSize - 1UL) : (1UL); + + /* Write data into TX FIFO */ + NumToCopy = Cy_SCB_WriteArray(base, context->masterBuffer, NumToCopy); + context->masterBufferIdx += NumToCopy; + context->masterBufferSize -= NumToCopy; + context->masterBuffer = &context->masterBuffer[NumToCopy]; + } + + /* Put the last byte */ + if ((CY_SCB_I2C_FIFO_SIZE != Cy_SCB_GetNumInTxFifo(base)) && (1UL == context->masterBufferSize)) + { + uint32_t intrStatus; + + /* Put the last data byte into TX FIFO and make sure that TX + * underflow will happen after all data is transfered onto the bus. + */ + intrStatus = Cy_SysLib_EnterCriticalSection(); + + Cy_SCB_WriteTxFifo(base, (uint32_t) context->masterBuffer[0UL]); + Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW); + + Cy_SysLib_ExitCriticalSection(intrStatus); + + ++context->masterBufferIdx; + context->masterBufferSize = 0UL; + } + + /* Complete the transfer */ + if (0UL == context->masterBufferSize) + { + if (context->masterPause) + { + /* Wait until data is transfered onto the bus */ + Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_UNDERFLOW); + + context->state = CY_SCB_I2C_MASTER_TX_DONE; + } + else + { + /* Disable TX processing */ + Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + /* Request Stop generation */ + context->state = CY_SCB_I2C_MASTER_STOP; + } + + if (context->useTxFifo) + { + /* Notify the user that data is in TX FIFO */ + context->masterStatus |= CY_SCB_I2C_MASTER_WR_IN_FIFO; + + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_I2C_MASTER_WR_IN_FIFO_EVENT); + } + } + } + } + else + { + /* Do nothing */ + } +} + + +/******************************************************************************* +* Function Name: MasterHandleComplete +****************************************************************************//** +* +* Handles the transfer completion on a stop or restart - the normal case or +* completion due to an error on the bus or lost arbitration. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void MasterHandleComplete(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + uint32_t masterIntrStatus = Cy_SCB_GetMasterInterruptStatusMasked(base); + + /* Clean-up hardware: disable interrupt sources */ + base->I2C_CTRL &= (uint32_t) ~SCB_I2C_CTRL_M_READY_DATA_ACK_Msk; + + /* Disable the interrupt source for master operation */ + Cy_SCB_SetRxInterruptMask (base, CY_SCB_CLEAR_ALL_INTR_SRC); + Cy_SCB_SetTxInterruptMask (base, CY_SCB_CLEAR_ALL_INTR_SRC); + Cy_SCB_SetMasterInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + Cy_SCB_ClearMasterInterrupt(base, CY_SCB_I2C_MASTER_INTR_ALL); + + /* Operation complete - master is not busy anymore */ + context->masterStatus &= (uint32_t) ~CY_SCB_I2C_MASTER_BUSY; + + /* Get number of byte transferred on the bus */ + if (context->masterRdDir) + { + context->masterNumBytes = context->masterBufferIdx; + } + else + { + context->masterNumBytes = context->masterBufferIdx - + (Cy_SCB_GetNumInTxFifo(base) + Cy_SCB_GetTxSrValid(base)); + } + + /* Clean up after a not completed transfer */ + if (0UL != (CY_SCB_I2C_MASTER_INTR_ERR & masterIntrStatus)) + { + /* Reset the scb IP block when: + * 1. Master mode: Reset IP when arbitration is lost or a bus error occurs. + * 2. Master-Slave mode: Reset IP if it is not the address phase (ACK is 0). + * Otherwise, reset only on a bus error. If "lost arbitration" happened, the slave + * can be addressed, so let the slave accept the address. + */ + + bool resetIp = true; + + /* Check the Master-Slave address an ACK/NACK */ + if (CY_SCB_I2C_MASTER_SLAVE == _FLD2VAL(CY_SCB_I2C_CTRL_MODE, base->I2C_CTRL)) + { + resetIp = ((0UL != (CY_SCB_MASTER_INTR_I2C_ACK & masterIntrStatus)) ? true : + ((0UL != (CY_SCB_MASTER_INTR_I2C_BUS_ERROR & masterIntrStatus)) ? true : false)); + } + + if (resetIp) + { + /* Reset to get it back in an known state */ + Cy_SCB_FwBlockReset(base); + } + + /* Back to the idle state. The master is not active anymore */ + context->state = CY_SCB_I2C_IDLE; + } + else + { + if (context->useRxFifo) + { + /* Clear RX FIFO from remaining data and level interrupt source */ + Cy_SCB_ClearRxFifo(base); + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); + } + + context->state = (context->masterPause) ? CY_SCB_I2C_MASTER_WAIT : CY_SCB_I2C_IDLE; + } + + /* An operation completion callback */ + if (NULL != context->cbEvents) + { + /* Get completion events based on the hardware status */ + uint32_t locEvents = context->masterRdDir ? CY_SCB_I2C_MASTER_RD_CMPLT_EVENT : CY_SCB_I2C_MASTER_WR_CMPLT_EVENT; + + /* Add errors if any */ + locEvents |= (0UL != (CY_SCB_I2C_MASTER_ERR & context->masterStatus)) ? CY_SCB_I2C_MASTER_ERR_EVENT : 0UL; + + context->cbEvents(locEvents); + } +} + + +/******************************************************************************* +* Function Name: MasterHandleComplete +****************************************************************************//** +* +* Handles the stop condition generation +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_i2c_context_t allocated +* by the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void MasterHandleStop(CySCB_Type *base, cy_stc_scb_i2c_context_t *context) +{ + /* Stop RX and TX processing */ + Cy_SCB_SetRxInterruptMask (base, CY_SCB_CLEAR_ALL_INTR_SRC); + Cy_SCB_SetTxInterruptMask (base, CY_SCB_CLEAR_ALL_INTR_SRC); + + if (0UL != base->I2C_M_CMD) + { + /* Enable ACK interrupt source: it triggers after Start or ReStart generation */ + Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR_ALL); + } + else + { + /* Disable ACK interrupt source */ + Cy_SCB_SetMasterInterruptMask(base, CY_SCB_I2C_MASTER_INTR); + + /* Complete transaction generating Stop */ + base->I2C_M_CMD = (SCB_I2C_M_CMD_M_STOP_Msk | SCB_I2C_M_CMD_M_NACK_Msk); + context->state = CY_SCB_I2C_MASTER_WAIT_STOP; + } +} + + +/****************************************************************************** +* Function Name: WaitOneUnit +****************************************************************************//** +* +* Waits for one unit before unblock code execution. +* Note If a timeout value is 0, this function does nothing and returns 0. +* +* \param timeout +* The pointer to a timeout value. +* +* \return +* Returns 0 if a timeout does not expire or the timeout mask. +* +*******************************************************************************/ +static uint32_t WaitOneUnit(uint32_t *timeout) +{ + uint32_t status = 0UL; + + /* If the timeout equal to 0. Ignore the timeout */ + if (*timeout > 0UL) + { + Cy_SysLib_DelayUs(CY_SCB_WAIT_1_UNIT); + --(*timeout); + + if (0UL == *timeout) + { + status = CY_SCB_I2C_MASTER_TIMEOUT_DONE; + } + } + + return (status); +} + + +/****************************************************************************** +* Function Name: HandleStatus +****************************************************************************//** +* +* Convers passed status into the cy_en_scb_i2c_status_t. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param status +* The status to covert. +* +* \return +* \ref cy_en_scb_i2c_status_t +* +*******************************************************************************/ +static cy_en_scb_i2c_status_t HandleStatus(CySCB_Type *base, uint32_t status, cy_stc_scb_i2c_context_t *context) +{ + bool resetBlock = false; + cy_en_scb_i2c_status_t retStatus = CY_SCB_I2C_MASTER_MANUAL_TIMEOUT; + + /* Convert the master status to the API status */ + if (0UL != (CY_SCB_I2C_MASTER_TIMEOUT_DONE & status)) + { + resetBlock = true; + } + else if (0UL != (CY_SCB_I2C_SLAVE_ADDR_DONE & status)) + { + if (0UL != base->I2C_M_CMD) + { + /* Abort the master operation, the slave was addressed first */ + retStatus = CY_SCB_I2C_MASTER_MANUAL_ABORT_START; + + base->I2C_M_CMD = 0UL; + context->state = CY_SCB_I2C_IDLE; + } + } + else if (0UL != (CY_SCB_MASTER_INTR_I2C_BUS_ERROR & status)) + { + retStatus = CY_SCB_I2C_MASTER_MANUAL_BUS_ERR; + resetBlock = true; + } + else if (0UL != (CY_SCB_MASTER_INTR_I2C_ARB_LOST & status)) + { + retStatus = CY_SCB_I2C_MASTER_MANUAL_ARB_LOST; + + if (CY_SCB_I2C_MASTER_ADDR == context->state) + { + /* This is the address phase: + * 1. Master mode: Reset IP when "arbitration lost" occurred. + * 2. Master-Slave mode: If "lost arbitration" occurred, the slave + * can be addressed to let the slave accept the address; do not + * reset IP. + */ + resetBlock = !_FLD2BOOL(SCB_I2C_CTRL_SLAVE_MODE, base->I2C_CTRL); + + context->state = CY_SCB_I2C_IDLE; + } + else + { + resetBlock = true; + } + } + else if (0UL != (CY_SCB_MASTER_INTR_I2C_NACK & status)) + { + /* An address or data was NAKed */ + retStatus = (CY_SCB_I2C_MASTER_ADDR == context->state) ? + CY_SCB_I2C_MASTER_MANUAL_ADDR_NAK : CY_SCB_I2C_MASTER_MANUAL_NAK; + } + else if (0UL != (CY_SCB_MASTER_INTR_I2C_STOP & status)) + { + /* No errors - end of transaction detected */ + retStatus = CY_SCB_I2C_SUCCESS; + + context->state = CY_SCB_I2C_IDLE; + } + else /* No errors - continue trasaction */ + { + retStatus = CY_SCB_I2C_SUCCESS; + + /* The change state */ + if (CY_SCB_I2C_MASTER_ADDR == context->state) + { + context->state = (context->masterRdDir) ? + CY_SCB_I2C_MASTER_RX0 : CY_SCB_I2C_MASTER_TX; + } + } + + if (resetBlock) + { + /* A block reset clears all interrupt sources */ + Cy_SCB_FwBlockReset(base); + + context->state = CY_SCB_I2C_IDLE; + } + else + { + Cy_SCB_ClearMasterInterrupt(base, CY_SCB_I2C_MASTER_INTR_ALL); + } + + return (retStatus); +} + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_i2c.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_i2c.h new file mode 100644 index 0000000000..4dc1484fd0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_i2c.h @@ -0,0 +1,1112 @@ +/***************************************************************************//** +* \file cy_scb_i2c.h +* \version 1.0 +* +* Provides I2C API declarations of the SCB driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \addtogroup group_scb_i2c +* \{ +* Driver API for I2C Bus Peripheral +* +* I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard. +* The two-wire hardware interface was developed by Philips Semiconductors +* (now NXP Semiconductors). +* +* The I2C peripheral driver provides an API to implement I2C slave, master, +* or master-slave devices based on the SCB hardware block. +* I2C devices based on SCB hardware are compatible with I2C +* Standard-mode, Fast-mode, and Fast-mode Plus specifications as defined in +* the I2C-bus specification. +* +* Features: +* * An industry-standard I2C bus interface +* * Supports slave, master, and master-slave operation +* * Supports standard data rates of 100/400/1000 kbps +* * Hardware Address Match, multiple addresses +* * Wake From DeepSleep on Address Match +* +* \section group_scb_i2c_configuration Configuration Considerations +* +* To set up the I2C driver, provide the configuration parameters in the +* \ref cy_stc_scb_i2c_config_t structure. For master configuration, +* provide i2cMode, useRxFifo, and useTxFifo. For slave mode also provide the +* slaveAddress and slaveAddressMask. The other parameters are optional for +* operation. +* To initialize the driver, call the \ref Cy_SCB_I2C_Init function providing the +* filled \ref cy_stc_scb_i2c_config_t structure and allocated +* \ref cy_stc_scb_i2c_context_t. Before calling \ref Cy_SCB_I2C_Enable to start +* the I2C operation, the \ref Cy_SCB_I2C_SetDataRate must be called to set +* the data rate. +* +* Master mode operation: \n +* There are two methods for initiating I2C master transactions. +* These two methods are described below. Only one method should be used +* at a time. They should not be mixed. +* +* * Call \ref Cy_SCB_I2C_MasterRead or \ref Cy_SCB_I2C_MasterWrite to +* communicate with the slave. These functions do not block and only +* start a transaction. After a transfer is started, the +* \ref Cy_SCB_I2C_Interrupt handles the further data transfer until its +* completion. Therefore, \ref Cy_SCB_I2C_Interrupt must be called inside the +* user interrupt handler to make the API above work. To monitor the transfer, +* use \ref Cy_SCB_I2C_MasterGetStatus or \ref Cy_SCB_I2C_RegisterEventCallback +* to register callback function to be notified about +* \ref group_scb_i2c_macro_callback_events. +* +* * Call \ref Cy_SCB_I2C_MasterSendStart to generate a start, send an address +* with the Read/Write direction bit, and receive acknowledgment. After the +* address is ACKed by the slave, the transaction can be continued by calling +* \ref Cy_SCB_I2C_MasterReadByte or \ref Cy_SCB_I2C_MasterWriteByte depending +* on its direction. These functions handle one byte per call, therefore +* they should be called for each byte in the transaction. Note that for the +* Read transaction the last byte must be NAKed. To complete the current +* transaction, call \ref Cy_SCB_I2C_MasterSendStop or call +* \ref Cy_SCB_I2C_MasterSendReStart to complete the current transaction and +* start a new one. Typically, do a restart to change the transaction +* direction without releasing the bus from the master control. +* Note that these functions are blocking and do not require calling +* \ref Cy_SCB_I2C_Interrupt inside the user interrupt handler. Using these +* functions requires extensive knowledge of the I2C protocol to execute +* transactions correctly. +* +* Slave mode operation: +* +* The slave operation is based on the \ref Cy_SCB_I2C_Interrupt that must be +* called inside the user interrupt handler. The Read and Write buffer must +* be provided for the slave to enable communication with the master. Use +* \ref Cy_SCB_I2C_SlaveConfigReadBuf and \ref Cy_SCB_I2C_SlaveConfigWriteBuf +* for this purpose. Note that after transaction completion the buffer must be +* configured again. Otherwise, the same buffer is used starting from the point +* where the master stopped a previous transaction. +* For example: The Read buffer is configured to be 10 bytes and the master Read +* is 8 bytes. If the Read buffer is not configured again, the next master Read +* will start from the 9th byte. +* To monitor the transfer status, use \ref Cy_SCB_I2C_SlaveGetStatus or +* use \ref Cy_SCB_I2C_RegisterEventCallback to register a callback function +* to be notified about \ref group_scb_i2c_macro_callback_events. +* +* \note All slave API (except \ref Cy_SCB_I2C_SlaveAbortRead and +* \ref Cy_SCB_I2C_SlaveAbortWrite) are not interrupt-protected and to +* prevent a race condition, they should be protected from the I2C interruption +* in the place where they are called. +* +* \section group_scb_i2c_more_information More Information +* +* For more information on the SCB peripheral, refer to the technical reference +* manual (TRM). +* +* \section group_scb_i2c_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
13.7RBoolean operations whose results are invariant shall not be +* permitted.The same condition check is executed before and after callback is +* called because after the callback returns, the condition might be not +* true any more.
14.2RAll non-null statements shall either: a) have at least one side-effect +* however executed, or b) cause control flow to change.The unused function parameters are cast to void. This statement +* has no side-effect and is used to suppress a compiler warning.
+* +* \section group_scb_i2c_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_scb_i2c_macro Macro +* \defgroup group_scb_i2c_functions Functions +* \defgroup group_scb_i2c_data_structures Data Structures +* \defgroup group_scb_i2c_enums Enumerated Types +*/ + +#if !defined(CY_SCB_I2C_H) +#define CY_SCB_I2C_H + +#include "cy_scb_common.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Enumerated Types +***************************************/ + +/** +* \addtogroup group_scb_i2c_enums +* \{ +*/ + +/** I2C status codes */ +typedef enum +{ + /** Operation completed successfully */ + CY_SCB_I2C_SUCCESS = 0x00U, + + /** One or more of input parameters are invalid */ + CY_SCB_I2C_BAD_PARAM = CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 1UL, + + /** + * The master is not ready to start a new transaction. + * Either the master is still processing a previous transaction or in the + * master-slave mode the slave operation is in progress. Call this function + * again once that operation is completed or aborted. + */ + CY_SCB_I2C_MASTER_NOT_READY, + + /** + * The master operation timed out before completing. Applicable only for + * the master functions which allows byte processing. + */ + CY_SCB_I2C_MASTER_MANUAL_TIMEOUT, + + /** The slave NACKed the address. Applicable only for the master functions + * which allows byte processing. + */ + CY_SCB_I2C_MASTER_MANUAL_ADDR_NAK, + + /** The slave NACKed the data byte. Applicable only for the master + * functions which allows byte processing. */ + CY_SCB_I2C_MASTER_MANUAL_NAK, + + /** + * The master lost arbitration, the transaction was aborted. Applicable only + * for the master functions which allows byte processing. + */ + CY_SCB_I2C_MASTER_MANUAL_ARB_LOST, + + /** + * The master detected an erroneous start or stop, the transaction was + * aborted. Applicable only for the master functions which allows byte + * processing. + */ + CY_SCB_I2C_MASTER_MANUAL_BUS_ERR, + + /** + * The master transaction was aborted and the slave transaction is on-going + * because the slave was addressed before the master generated a start. + * Applicable only for the master functions which allows byte processing. + */ + CY_SCB_I2C_MASTER_MANUAL_ABORT_START +} cy_en_scb_i2c_status_t; +/** \} group_scb_i2c_enums */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_scb_i2c_data_structures +* \{ +*/ + +/** +* Provides the typedef for the callback function called in the +* \ref Cy_SCB_I2C_Interrupt to notify the user about occurrences of +* \ref group_scb_i2c_macro_callback_events. +*/ +typedef void (* scb_i2c_handle_events_t)(uint32_t event); + +/** +* Provides the typedef for the callback function called in the +* \ref Cy_SCB_I2C_Interrupt to notify the user about occurrences of +* \ref group_scb_i2c_macro_addr_callback_events. +* This callback must return a decision to ACK (continue transaction) or +* NAK (end transaction) the received address. +* See \ref group_scb_i2c_macro_ack_nack for the set of constants. +* Note if the slave configured to accept an address in RX FIFO, it must read +* from it using the \ref Cy_SCB_ReadRxFifo function. +*/ +typedef uint32_t (* scb_i2c_handle_addr_t)(uint32_t event); + +/** I2C Configuration Structure */ +typedef struct cy_stc_scb_i2c_config +{ + /** + * Specifies the mode of operation (See \ref group_scb_i2c_macro_modes + * for the set of constants) + */ + uint32_t i2cMode; + + /** + * If the RX FIFO is used, the possibility of clock stretching is greatly + * reduced, and the interrupt overhead during an I2C transaction is also + * reduced. The reason: the hardware is configured to automatically ACK + * incoming data, and the interrupt is configured to take data out of the + * RX FIFO. + * * For the master mode, the drawback is that the master may receive more + * data than desired due to the interrupt latency. An interrupt fires + * when the second-to-last byte has been received, this interrupt tells + * the hardware to stop receiving data. If the latency of this interrupt + * is longer than 1 transfer of the byte on the I2C bus, then the + * hardware automatically ACKs the following bytes until the interrupt + * is serviced or the RX FIFO becomes full. + * * For the slave mode, the drawback is that the slave will only NACKs + * the master when the RX FIFO becomes full, NOT when the slave write + * firmware buffer becomes full. + * Note that all received extra bytes will be dropped in any mode. + * To avoid these drawbacks, do not enable this option. Then, hardware is + * configured to trigger an interrupt when a byte is available in the + * RX FIFO. After the byte is read, an ACK or NACK decision is made. + * Therefore, each received bytes requires the interrupt service to + * continue the transfer and that leads to increasing the interrupt + * overhead and the possibility of clock stretching. + * This parameter is not available if f acceptAddrInFifo is true. + */ + bool useRxFifo; + + /** + * If the TX FIFO is used, the possibility of clock stretching is greatly + * reduced, and the interrupt overhead during an I2C transaction is + * also reduced. The reason: the TX FIFO is fully loaded with data and + * the interrupt is configured to keep the TX FIFO loaded. + * The drawback of using this option is that the abort operation clears + * the TX FIFO. The TX FIFO clear operation also clears the shift + * register so that the shifter can be cleared in the middle of a byte + * transfer, corrupting it. The remaining bits to transfer within the + * corrupted byte are complemented with 1s. If this is an issue, + * then do not enable this option. + * If the TX FIFO is not used, then data is written to the TX FIFO byte + * by byte. This leads to more interrupts and also increases the + * possibility of clock stretching. + * Use the TX FIFO if the abort function is not used. + */ + bool useTxFifo; + + /** + * The 7-bit right justified slave address, used only for the slave mode + */ + uint8_t slaveAddress; + + /** + * The slave address mask, bit 0, must always be 0. It's used only for the + * slave mode + */ + uint8_t slaveAddressMask; + + /** + * True - the slave address is accepted in RX FIFO, false - the slave + * addresses are not accepted in FIFO + */ + bool acceptAddrInFifo; + + /** + * True - accept the general call address; false - ignore the general + * call address. + */ + bool ackGeneralAddr; + + /** + * When set, the slave will wake the device from deep sleep on an address + * match (the device datasheet must be consulted to determine which SCBs + * support this mode) + */ + bool enableWakeFromSleep; +} cy_stc_scb_i2c_config_t; + +/** I2C Internal structure, holds data used by I2C functions */ +typedef struct cy_stc_scb_i2c_context +{ + bool useRxFifo; /**< Holds RX FIFO configuration */ + bool useTxFifo; /**< Holds TX FIFO configuration */ + + uint32_t state; /**< Holds state of driver */ + + uint32_t masterStatus; /**< Holds master status */ + bool masterPause; /**< Stores how master ends transfer */ + bool masterRdDir; /**< Stores direction of master transfer */ + + uint8_t *masterBuffer; /**< Pointer to master buffer transmit or receive buffer */ + uint32_t masterBufferIdx; /**< Current Read/Write location in master buffer */ + uint32_t masterBufferSize; /**< End of master buffer */ + uint32_t masterNumBytes; /**< Number of bytes sent or received */ + + uint32_t slaveStatus; /**< Holds slave status */ + bool slaveRdBufEmpty; /**< Tracks slave Read buffer empty event */ + + uint8_t *slaveTxBuffer; /**< Pointer to slave TX buffer */ + uint32_t slaveTxBufferIdx; /**< Current Read location in the slave TX buffer */ + uint32_t slaveTxBufferSize; /**< End of slave TX buffer */ + uint32_t slaveTxBufferCnt; /**< Number of transferred bytes */ + + uint8_t *slaveRxBuffer; /**< Pointer to slave RX buffer */ + uint32_t slaveRxBufferIdx; /**< Current Write location in the slave buffer */ + uint32_t slaveRxBufferSize; /**< End of slave buffer */ + + /** + * The pointer to an event callback that is called when an I2C event occurs + */ + scb_i2c_handle_events_t cbEvents; + + /** + * The pointer to an address callback, used only for the slave + */ + scb_i2c_handle_addr_t cbAddr; +} cy_stc_scb_i2c_context_t; + +/** The I2C Master transfer structure */ +typedef struct cy_stc_scb_i2c_master_xfer_config +{ + uint8_t slaveAddress; /**< Address of slave to start transfer with */ + uint8_t *buffer; /**< Pointer to buffer for data to read from slave + or with data to write into slave */ + uint32_t bufferSize; /**< Size of buffer */ + bool xferPending; /**< Transfer operation is pending - + Stop condition will not be generated */ +} cy_stc_scb_i2c_master_xfer_config_t; +/** \} group_scb_i2c_data_structures */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_scb_i2c_functions +* \{ +*/ +/* Basic functions */ +cy_en_scb_i2c_status_t Cy_SCB_I2C_Init(CySCB_Type *base, cy_stc_scb_i2c_config_t const *config, + cy_stc_scb_i2c_context_t *context); +void Cy_SCB_I2C_DeInit (CySCB_Type *base); +__STATIC_INLINE void Cy_SCB_I2C_Enable(CySCB_Type *base); +void Cy_SCB_I2C_Disable(CySCB_Type *base, cy_stc_scb_i2c_context_t *context); + +/* Data rate configuration functions */ +uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t scbClockkHz); +uint32_t Cy_SCB_I2C_GetDataRate(CySCB_Type const *base, uint32_t scbClockkHz); + +/* Configure slave address */ +__STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddress (CySCB_Type *base, uint8_t addr); +__STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddress (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddressMask(CySCB_Type *base, uint8_t addrMask); +__STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddressMask(CySCB_Type const *base); + +/* Configure master oversampling */ +__STATIC_INLINE void Cy_SCB_I2C_MasterSetLowPhaseDutyCycle (CySCB_Type *base, uint32_t clockCycles); +__STATIC_INLINE void Cy_SCB_I2C_MasterSetHighPhaseDutyCycle(CySCB_Type *base, uint32_t clockCycles); + +/* Low power functions */ +void Cy_SCB_I2C_DeepSleep(CySCB_Type *base, uint32_t wakeupAction); +void Cy_SCB_I2C_Wakeup (CySCB_Type *base); + +__STATIC_INLINE bool Cy_SCB_I2C_IsBusBusy (CySCB_Type const *base); + +/* Register callbacks */ +__STATIC_INLINE void Cy_SCB_I2C_RegisterEventCallback(CySCB_Type const *base, scb_i2c_handle_events_t callback, + cy_stc_scb_i2c_context_t *context); +__STATIC_INLINE void Cy_SCB_I2C_RegisterAddrCallback (CySCB_Type const *base, scb_i2c_handle_addr_t callback, + cy_stc_scb_i2c_context_t *context); + +/* Slave functions */ +uint32_t Cy_SCB_I2C_SlaveGetStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context); + +void Cy_SCB_I2C_SlaveConfigReadBuf (CySCB_Type const *base, uint8_t *rdBuf, uint32_t size, + cy_stc_scb_i2c_context_t *context); +void Cy_SCB_I2C_SlaveAbortRead (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +uint32_t Cy_SCB_I2C_SlaveGetReadTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context); +uint32_t Cy_SCB_I2C_SlaveClearReadStatus (CySCB_Type const *base, cy_stc_scb_i2c_context_t *context); + +void Cy_SCB_I2C_SlaveConfigWriteBuf (CySCB_Type const *base, uint8_t *wrBuf, uint32_t size, + cy_stc_scb_i2c_context_t *context); +void Cy_SCB_I2C_SlaveAbortWrite (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +uint32_t Cy_SCB_I2C_SlaveGetWriteTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context); +uint32_t Cy_SCB_I2C_SlaveClearWriteStatus (CySCB_Type const *base, cy_stc_scb_i2c_context_t *context); + +/* Master interrupt processing functions */ +uint32_t Cy_SCB_I2C_MasterGetStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context); + +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterRead(CySCB_Type *base, cy_stc_scb_i2c_master_xfer_config_t* masterXferConfig, + cy_stc_scb_i2c_context_t *context); +void Cy_SCB_I2C_MasterAbortRead (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWrite(CySCB_Type *base, cy_stc_scb_i2c_master_xfer_config_t *masterXferConfig, + cy_stc_scb_i2c_context_t *context); +void Cy_SCB_I2C_MasterAbortWrite (CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +uint32_t Cy_SCB_I2C_MasterGetTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context); + +/* Master manual processing functions */ +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendStart (CySCB_Type *base, uint32_t address, uint32_t bitRnW, uint32_t timeoutMs, + cy_stc_scb_i2c_context_t *context); +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendReStart(CySCB_Type *base, uint32_t address, uint32_t bitRnW, uint32_t timeoutMs, + cy_stc_scb_i2c_context_t *context); +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendStop (CySCB_Type *base,uint32_t timeoutMs, cy_stc_scb_i2c_context_t *context); +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterReadByte (CySCB_Type *base, uint32_t ackNack, uint8_t *byte, uint32_t timeoutMs, + cy_stc_scb_i2c_context_t *context); +cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWriteByte (CySCB_Type *base, uint32_t theByte, uint32_t timeoutMs, + cy_stc_scb_i2c_context_t *context); +/* Interrupt handler */ +void Cy_SCB_I2C_Interrupt(CySCB_Type *base, cy_stc_scb_i2c_context_t *context); +/** \} group_scb_i2c_functions */ + + +/*************************************** +* API Constants +***************************************/ + +/** +* \addtogroup group_scb_i2c_macro +* \{ +*/ + +/** +* \defgroup group_scb_i2c_macro_modes I2C Modes +* \{ +*/ +#define CY_SCB_I2C_SLAVE (1U) /**< Configures SCB for I2C Slave operation */ +#define CY_SCB_I2C_MASTER (2U) /**< Configures SCB for I2C Master operation */ +#define CY_SCB_I2C_MASTER_SLAVE (3U) /**< Configures SCB for I2C Master-Slave operation */ +/** \} group_scb_i2c_macro_modes */ + +/** +* \defgroup group_scb_i2c_macro_slave_status I2C Slave Status +* Each I2C slave status is encoded in a separate bit, therefore multiple bits +* may be set to indicate the current status. +* \{ +*/ +/** There is a Read transaction in progress */ +#define CY_SCB_I2C_SLAVE_RD_BUSY (0x00000001UL) + +/** +* All read data has been loaded to TX FIFO, applicable only if TX FIFO is +* enabled +*/ +#define CY_SCB_I2C_SLAVE_RD_IN_FIFO (0x00000002UL) + +/** +* The master has finished reading data from the slave +*/ +#define CY_SCB_I2C_SLAVE_RD_CMPLT (0x00000004UL) + +/** +* Set when the master tried to read more bytes than available in the configured +* read buffer. The slave is not able to finish the transaction and sends +* \ref CY_SCB_I2C_DEFAULT_TX. +*/ +#define CY_SCB_I2C_SLAVE_RD_UNDRFL (0x00000008UL) + +/** There is a Write transaction in progress */ +#define CY_SCB_I2C_SLAVE_WR_BUSY (0x00000010UL) + +/** +* The master has finished writing data into the slave +*/ +#define CY_SCB_I2C_SLAVE_WR_CMPLT (0x00000020UL) + +/** +* The master attempted to write more bytes than space available in the +* configured Write buffer. Note that all subsequent bytes are dropped. +*/ +#define CY_SCB_I2C_SLAVE_WR_OVRFL (0x00000040UL) + +/** The slave lost arbitration, the transaction was aborted */ +#define CY_SCB_I2C_SLAVE_ARB_LOST (0x00000080UL) + +/** +* The slave captured an error on the bus during a master transaction (sources +* of error is misplaced Start or Stop). +*/ +#define CY_SCB_I2C_SLAVE_BUS_ERR (0x00000100UL) +/** \} group_scb_i2c_macro_slave_status */ + +/** +* \defgroup group_scb_i2c_macro_master_status I2C Master Status +* Each I2C master status is encoded in a separate bit, therefore multiple +* bits may be set to indicate the current status. +* \{ +*/ + +/** +* The master is busy executing operation initiated by \ref Cy_SCB_I2C_MasterRead +* or \ref Cy_SCB_I2C_MasterWrite +*/ +#define CY_SCB_I2C_MASTER_BUSY (0x00010000UL) + +/** +* All Write data has been loaded to the TX FIFO +*/ +#define CY_SCB_I2C_MASTER_WR_IN_FIFO (0x00020000UL) + +/** The slave NACKed the address. */ +#define CY_SCB_I2C_MASTER_ADDR_NAK (0x00100000UL) + +/** Write completed before all bytes were sent (last byte was NAKed) +*/ +#define CY_SCB_I2C_MASTER_DATA_NAK (0x00200000UL) + +/** The master lost arbitration, the transaction was aborted */ +#define CY_SCB_I2C_MASTER_ARB_LOST (0x00400000UL) + +/** +* The master detected an erroneous start or stop, the transaction was aborted +*/ +#define CY_SCB_I2C_MASTER_BUS_ERR (0x00800000UL) + +/** +* The master transaction was aborted and the slave transaction is on-going +* because the slave was addressed before the master generated a start +*/ +#define CY_SCB_I2C_MASTER_ABORT_START (0x01000000UL) +/** \} group_scb_i2c_macro_master_status */ + +/** +* \defgroup group_scb_i2c_macro_direction I2C Direction +* \{ +*/ +#define CY_SCB_I2C_WRITE_XFER (0UL) /**< Current transaction is Write */ +#define CY_SCB_I2C_READ_XFER (1UL) /**< Current transaction is Read */ +/** \} group_scb_i2c_macro_direction */ + +/** +* \defgroup group_scb_i2c_macro_ack_nack I2C ACK NAK +* \{ +*/ +#define CY_SCB_I2C_ACK (SCB_I2C_S_CMD_S_ACK_Msk) /**< Send ACK to current byte */ +#define CY_SCB_I2C_NAK (SCB_I2C_S_CMD_S_NACK_Msk) /**< Send NAK to current byte */ +/** \} group_scb_i2c_macro_ack_nack */ + +/** +* \defgroup group_scb_i2c_macro_wake_up I2C Wakeup Actions +* \{ +*/ +#define CY_SCB_I2C_WAKEUP_STRETCH (0UL) /**< Slave will stretch clock on wakeup */ +#define CY_SCB_I2C_WAKEUP_NACK (1UL) /**< Slave will NAK address on wakeup */ +/** \} group_scb_i2c_macro_wake_up */ + +/** +* \defgroup group_scb_i2c_macro_callback_events I2C Callback Events +* \{ +* Each event is encoded in a separate bit, and therefore it is possible to +* notify about multiple events. +*/ +/** +* Indicates that the slave was addressed and the master wants to read data. +* This event can be used to configure the slave Read buffer. +*/ +#define CY_SCB_I2C_SLAVE_READ_EVENT (0x00000001UL) + +/** +* Indicates that the slave was addressed and the master wants to write data. +* This event can be used to configure the slave Write buffer. +*/ +#define CY_SCB_I2C_SLAVE_WRITE_EVENT (0x00000002UL) + +/** +* All slave data from the configured Read buffer has been loaded to TX FIFO. +* The content of the Read buffer can be modified. Applicable only if TX FIFO is +* enabled. +*/ +#define CY_SCB_I2C_SLAVE_RD_IN_FIFO_EVENT (0x00000004UL) + +/** +* The master has read all data out of the configured Read buffer. +* This event can be used to configure the next Read buffer. If the buffer remains +* empty, the \ref CY_SCB_I2C_DEFAULT_TX bytes are returned to the master. +*/ +#define CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT (0x00000008UL) + +/** +* Indicates the master completed reading from the slave (set by master NAK +* or Stop) +*/ +#define CY_SCB_I2C_SLAVE_RD_CMPLT_EVENT (0x00000010UL) + +/** +* Indicates master completed writing to the slave (set by master Stop +* or Restart) +*/ +#define CY_SCB_I2C_SLAVE_WR_CMPLT_EVENT (0x00000020UL) + +/** +* Indicates the I2C hardware detected an error. +* Check \ref Cy_SCB_I2C_SlaveGetStatus to determine the source of the error. +*/ +#define CY_SCB_I2C_SLAVE_ERR_EVENT (0x00000040UL) + +/** +* All master write data has been loaded to TX FIFO. +* The content of the Write buffer can be modified. Applicable only if +* TX FIFO is enabled. +*/ +#define CY_SCB_I2C_MASTER_WR_IN_FIFO_EVENT (0x00010000UL) + +/** +* Indicates the master completed writing data to the slave +*/ +#define CY_SCB_I2C_MASTER_WR_CMPLT_EVENT (0x00020000UL) + +/** +* Indicates the master completed reading data from the slave +*/ +#define CY_SCB_I2C_MASTER_RD_CMPLT_EVENT (0x00040000UL) + +/** +* Indicates the I2C hardware detected an error. It occurs together with +* \ref CY_SCB_I2C_MASTER_RD_CMPLT_EVENT or \ref CY_SCB_I2C_MASTER_WR_CMPLT_EVENT +* depends on the direction of the transfer. +* Check \ref Cy_SCB_I2C_MasterGetStatus to determine the source of the error. +*/ +#define CY_SCB_I2C_MASTER_ERR_EVENT (0x00080000UL) +/** \} group_scb_i2c_macro_callback_events */ + +/** +* \defgroup group_scb_i2c_macro_addr_callback_events I2C Address Callback Events +* Each event is encoded in a separate bit and therefore it is possible to +* notify about multiple events. +* \{ +*/ +/** +* Indicates the slave was addressed by the general call address +*/ +#define CY_SCB_I2C_GENERAL_CALL_EVENT (0x01UL) + +/** +* The slave address is in the RX FIFO. +* Note that the address must be read from the RX FIFO using the +* \ref Cy_SCB_ReadRxFifo function. +*/ +#define CY_SCB_I2C_ADDR_IN_FIFO_EVENT (0x02UL) +/** \} group_scb_i2c_macro_addr_callback_events */ + +/** +* This value is returned by the slave when there is no data in the +* Read buffer +*/ +#define CY_SCB_I2C_DEFAULT_TX (0xFFUL) + + +/*************************************** +* Internal Constants +***************************************/ + +/** \cond INTERNAL */ + +/* Slave statuses */ +#define CY_SCB_I2C_SLAVE_RD_CLEAR (CY_SCB_I2C_SLAVE_RD_CMPLT | CY_SCB_I2C_SLAVE_RD_IN_FIFO | \ + CY_SCB_I2C_SLAVE_RD_UNDRFL | CY_SCB_I2C_SLAVE_ARB_LOST | \ + CY_SCB_I2C_SLAVE_BUS_ERR) + +#define CY_SCB_I2C_SLAVE_WR_CLEAR (CY_SCB_I2C_SLAVE_WR_CMPLT | CY_SCB_I2C_SLAVE_WR_OVRFL | \ + CY_SCB_I2C_SLAVE_ARB_LOST | CY_SCB_I2C_SLAVE_BUS_ERR) + +/* The position and mask to set the I2C mode */ +#define CY_SCB_I2C_CTRL_MODE_Pos SCB_I2C_CTRL_SLAVE_MODE_Pos +#define CY_SCB_I2C_CTRL_MODE_Msk (SCB_I2C_CTRL_SLAVE_MODE_Msk | SCB_I2C_CTRL_MASTER_MODE_Msk) + +/* RX and TX control register values */ +#define CY_SCB_I2C_DATA_WIDTH (7UL) +#define CY_SCB_I2C_RX_CTRL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \ + SCB_RX_CTRL_MSB_FIRST_Msk) +#define CY_SCB_I2C_TX_CTRL (CY_SCB_I2C_RX_CTRL) + +/* The position and mask to make an address byte */ +#define CY_SCB_I2C_ADDRESS_Pos (1UL) +#define CY_SCB_I2C_ADDRESS_Msk (0xFEUL) + +/* Master error statuses */ +#define CY_SCB_I2C_MASTER_ERR (CY_SCB_I2C_MASTER_ABORT_START | CY_SCB_I2C_MASTER_ADDR_NAK | \ + CY_SCB_I2C_MASTER_DATA_NAK | CY_SCB_I2C_MASTER_BUS_ERR | \ + CY_SCB_I2C_MASTER_ARB_LOST) + +/* Master interrupt masks */ +#define CY_SCB_I2C_MASTER_INTR (CY_SCB_MASTER_INTR_I2C_ARB_LOST | CY_SCB_MASTER_INTR_I2C_BUS_ERROR | \ + CY_SCB_MASTER_INTR_I2C_NACK | CY_SCB_MASTER_INTR_I2C_STOP) + +#define CY_SCB_I2C_MASTER_INTR_ALL (CY_SCB_I2C_MASTER_INTR | CY_SCB_MASTER_INTR_I2C_ACK) + +#define CY_SCB_I2C_MASTER_INTR_ERR (CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST) + +#define CY_SCB_I2C_MASTER_INTR_CMPLT (CY_SCB_I2C_MASTER_INTR_ERR | CY_SCB_MASTER_INTR_I2C_STOP) + +/* Master statuses. */ +#define CY_SCB_I2C_MASTER_TX_BYTE_DONE (CY_SCB_MASTER_INTR_I2C_ACK | CY_SCB_MASTER_INTR_I2C_NACK | \ + CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST) + +#define CY_SCB_I2C_MASTER_RX_BYTE_DONE (CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST) + +#define CY_SCB_I2C_MASTER_STOP_DONE (CY_SCB_MASTER_INTR_I2C_STOP | \ + CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST) + +#define CY_SCB_I2C_MASTER_TIMEOUT_DONE (0x80000000UL) + +/* The slave interrupt mask */ +#define CY_SCB_I2C_SLAVE_INTR (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR | \ + CY_SCB_SLAVE_INTR_I2C_STOP | CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | \ + CY_SCB_SLAVE_INTR_I2C_ARB_LOST) + +#define CY_SCB_I2C_SLAVE_INTR_NO_STOP (CY_SCB_I2C_SLAVE_INTR & (uint32_t) ~CY_SCB_SLAVE_INTR_I2C_STOP) + +#define CY_SCB_I2C_SLAVE_INTR_ADDR (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR) + +#define CY_SCB_I2C_SLAVE_ADDR_DONE (CY_SCB_I2C_SLAVE_INTR_ADDR) + +#define CY_SCB_I2C_SLAVE_INTR_TX (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UNDERFLOW) + +#define CY_SCB_I2C_SLAVE_INTR_ERROR (CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST) + +/* I2C states */ +#define CY_SCB_I2C_IDLE (0x10000000UL) +#define CY_SCB_I2C_IDLE_MASK (0x10000000UL) + +/* Master states */ +#define CY_SCB_I2C_MASTER_ACTIVE (0x00100000UL) +#define CY_SCB_I2C_MASTER_WAIT (0x10100000UL) +#define CY_SCB_I2C_MASTER_RX0 (0x00110000UL) +#define CY_SCB_I2C_MASTER_RX1 (0x00120000UL) +#define CY_SCB_I2C_MASTER_ADDR (0x10130000UL) +#define CY_SCB_I2C_MASTER_TX (0x00140000UL) +#define CY_SCB_I2C_MASTER_TX_DONE (0x00150000UL) +#define CY_SCB_I2C_MASTER_STOP (0x00160000UL) +#define CY_SCB_I2C_MASTER_WAIT_STOP (0x00170000UL) +#define CY_SCB_I2C_MASTER_CMPLT (0x00180000UL) + +/* Slave states */ +#define CY_SCB_I2C_SLAVE_ACTIVE (0x00001000UL) +#define CY_SCB_I2C_SLAVE_RX_MASK (0x00001001UL) +#define CY_SCB_I2C_SLAVE_RX (0x00001001UL) +#define CY_SCB_I2C_SLAVE_TX (0x00001002UL) + +/* FIFO size */ +#define CY_SCB_I2C_FIFO_SIZE (128UL) +#define CY_SCB_I2C_HALF_FIFO_SIZE (CY_SCB_I2C_FIFO_SIZE / 2UL) + +#define CY_SCB_I2C_DEFAULT_RETURN (0xFFUL) + +/* Slave clock limits */ +#define CY_SCB_I2C_SLAVE_STD_CLK_MIN (1550U) +#define CY_SCB_I2C_SLAVE_STD_CLK_MAX (12800U) +#define CY_SCB_I2C_SLAVE_FST_CLK_MIN (7820U) +#define CY_SCB_I2C_SLAVE_FST_CLK_MAX (15380U) +#define CY_SCB_I2C_SLAVE_FSTP_CLK_MIN (15840U) +#define CY_SCB_I2C_SLAVE_FSTP_CLK_MAX (48000U) + +/* I2C data rates max: standard, fast and fast plus modes */ +#define CY_SCB_I2C_SLAVE_STD_DATA_RATE (100000U) +#define CY_SCB_I2C_SLAVE_FST_DATA_RATE (400000U) +#define CY_SCB_I2C_SLAVE_FSTP_DATA_RATE (1000000U) + +/* Master clock and duty cycle limits for standard mode */ +#define CY_SCB_I2C_MASTER_STD_CLK_MIN (1550U) +#define CY_SCB_I2C_MASTER_STD_CLK_MAX (3200U) +#define CY_SCB_I2C_MASTER_STD_LOW_MIN (8U) +#define CY_SCB_I2C_MASTER_STD_HIGH_MIN (8U) + +/* Master clock and duty cycle limits for fast mode */ +#define CY_SCB_I2C_MASTER_FST_MIN (7820U) +#define CY_SCB_I2C_MASTER_FST_MAX (10000U) +#define CY_SCB_I2C_MASTER_FST_LOW_MIN (13U) +#define CY_SCB_I2C_MASTER_FST_HIGH_MIN (8U) + +/* Master clock and duty cycle limits for fast plus mode */ +#define CY_SCB_I2C_MASTER_FSTP_MIN (14320U) +#define CY_SCB_I2C_MASTER_FSTP_MAX (25800U) +#define CY_SCB_I2C_MASTER_FSTP_LOW_MIN (9U) +#define CY_SCB_I2C_MASTER_FSTP_HIGH_MIN (6U) + +/* Master duty cycle limits */ +#define CY_SCB_I2C_PHASE_DUTY_CYCLE_MAX (16U) +#define CY_SCB_I2C_DUTY_CYCLE_MAX (32U) + +/* Analog filter settings. */ +#define CY_SCB_I2C_ENABLE_ANALOG_FITLER (0x002A1013UL) +#define CY_SCB_I2C_DISABLE_ANALOG_FITLER (0x002A0003UL) +/** \endcond */ + +/** \} group_scb_i2c_macro */ + + +/*************************************** +* In-line Function Implementation +***************************************/ + +/** +* \addtogroup group_scb_i2c_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_Enable +****************************************************************************//** +* +* Enables the SCB block for the I2C operation +* +* \param base +* The pointer to the I2C SCB instance. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_I2C_Enable(CySCB_Type *base) +{ + base->CTRL |= SCB_CTRL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_IsBusBusy +****************************************************************************//** +* +* Checks if the I2C bus is busy. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \return +* A bus status: busy or not busy. +* +* \note +* After the SCB block is enabled or reset, the valid bus busy-status returns +* after half of the SCL period. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SCB_I2C_IsBusBusy(CySCB_Type const *base) +{ + return _FLD2BOOL(SCB_I2C_STATUS_BUS_BUSY, base->I2C_STATUS); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveSetAddress +****************************************************************************//** +* +* Sets the slave address for the I2C slave. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param addr +* The 7-bit right justified slave address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddress(CySCB_Type *base, uint8_t addr) +{ + base->RX_MATCH = _CLR_SET_FLD32U(base->RX_MATCH, SCB_RX_MATCH_ADDR, ((uint32_t)((uint32_t) addr << 1UL))); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveGetAddress +****************************************************************************//** +* +* Returns the slave address of the I2C slave. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \return +* The 7-bit right justified slave address. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddress(CySCB_Type const *base) +{ + return (_FLD2VAL(SCB_RX_MATCH_ADDR, base->RX_MATCH) >> 1UL); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveSetAddressMask +****************************************************************************//** +* +* Sets the slave address mask for the I2C slave. The LSBit must always be 0. +* In all other bit positions a 1 indicates that the incoming address must match +* the corresponding bit in the slave address. A 0 in the mask means that the +* incoming address does not need to match. +* Example Slave Address = 0x0c. Slave Address Mask = 0x08. This means that the +* hardware will accept both 0x08 and 0x0c as valid addresses. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param addrMask +* The 8-bit address mask, the upper 7 bits correspond to the slave address. +* LSBit must always be 0. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddressMask(CySCB_Type *base, uint8_t addrMask) +{ + base->RX_MATCH = _CLR_SET_FLD32U(base->RX_MATCH, SCB_RX_MATCH_MASK, ((uint32_t) addrMask)); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_SlaveGetAddressMask +****************************************************************************//** +* +* Returns the slave address mask. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \return +* The 8-bit address mask, the upper 7 bits correspond to the slave address. +* LSBit must always be 0. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddressMask(CySCB_Type const *base) +{ + return _FLD2VAL(SCB_RX_MATCH_MASK, base->RX_MATCH); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterSetLowPhaseDutyCycle +****************************************************************************//** +* +* This function sets the number of SCB clock cycles in the low phase of SCL. +* If \ref Cy_SCB_I2C_SetDataRate is called after this function, the values +* specified in this function are overwritten. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param clockCycles +* The number of SCB clock cycles in the low phase of SCL. +* The valid range is 7 to 16. +* +* \note +* This function should be used at your own risk. Changing the number of clock +* cycles in a phase of SCL may violate the I2C specification. Make this +* change only while the block is disabled. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_I2C_MasterSetLowPhaseDutyCycle(CySCB_Type *base, uint32_t clockCycles) +{ + base->I2C_CTRL = _CLR_SET_FLD32U(base->I2C_CTRL, SCB_I2C_CTRL_LOW_PHASE_OVS, (clockCycles - 1UL)); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_MasterSetHighPhaseDutyCycle +****************************************************************************//** +* +* This function sets the number of SCB clock cycles in the high phase of SCL, +* If \ref Cy_SCB_I2C_SetDataRate is called after this function, the values +* specified in this function get overwritten. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param clockCycles +* The number of SCB clock cycles in the high phase of SCL. +* The valid range is 5 to 16. +* +* \note +* This function should be used at your own risk. Changing the number of clock +* cycles in a phase of SCL may violate the I2C specification. Make this +* change only while the block is disabled. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_I2C_MasterSetHighPhaseDutyCycle(CySCB_Type *base, uint32_t clockCycles) +{ + base->I2C_CTRL = _CLR_SET_FLD32U(base->I2C_CTRL, SCB_I2C_CTRL_HIGH_PHASE_OVS, (clockCycles - 1UL)); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_RegisterEventCallback +****************************************************************************//** +* +* Registers a callback function that notifies that +* \ref group_scb_i2c_macro_callback_events occurred in the +* \ref Cy_SCB_I2C_Interrupt. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param callback +* The pointer to a callback function. +* See \ref scb_i2c_handle_events_t for the function prototype. +* +* \param context +* The pointer to context structure \ref cy_stc_scb_i2c_context_t allocated by +* the user. The structure is used while the I2C operation for internal +* configuration and data keeping. The user should not modify anything in +* this structure. +* +* \note +* To remove the callback, pass NULL as the pointer to the callback function. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_I2C_RegisterEventCallback(CySCB_Type const *base, + scb_i2c_handle_events_t callback, cy_stc_scb_i2c_context_t *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + context->cbEvents = callback; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_I2C_RegisterAddrCallback +****************************************************************************//** +* +* Registers a callback function that notifies that +* \ref group_scb_i2c_macro_addr_callback_events occurred in the +* \ref Cy_SCB_I2C_Interrupt. +* +* \param base +* The pointer to the I2C SCB instance. +* +* \param callback +* The pointer to a callback function. +* See \ref scb_i2c_handle_addr_t for the function prototype. +* +* \param context +* The pointer to context structure \ref cy_stc_scb_i2c_context_t allocated by +* the user. The structure is used during the I2C operation for internal +* configuration and data keeping. The user should not modify anything in +* this structure. +* +* \note +* To remove the callback, pass NULL as the pointer to a callback function. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_I2C_RegisterAddrCallback(CySCB_Type const *base, + scb_i2c_handle_addr_t callback, cy_stc_scb_i2c_context_t *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + context->cbAddr = callback; +} + +/** \} group_scb_i2c_functions */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_scb_i2c */ + +#endif /* (CY_SCB_I2C_H) */ + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_spi.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_spi.c new file mode 100644 index 0000000000..e7727b185a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_spi.c @@ -0,0 +1,766 @@ +/***************************************************************************//** +* \file cy_scb_spi.c +* \version 1.0 +* +* Provides SPI API implementation of the SCB driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_scb_spi.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/* Static functions */ +static void HandleTransmit(CySCB_Type *base, cy_stc_scb_spi_context_t *context); +static void HandleReceive (CySCB_Type *base, cy_stc_scb_spi_context_t *context); +static void DiscardArrayNoCheck(CySCB_Type const *base, uint32_t size); + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_Init +****************************************************************************//** +* +* Initializes the SCB for SPI operation. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param config +* The pointer to the configuration structure \ref cy_stc_scb_spi_config_t. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated +* by the user. The structure is used during the SPI operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* If only SPI functions which do not require context will be used pass NULL +* as pointer to context. +* +* \return +* \ref cy_en_scb_spi_status_t +* +* \note +* Ensure that the SCB block is disabled before calling this function. +* +*******************************************************************************/ +cy_en_scb_spi_status_t Cy_SCB_SPI_Init(CySCB_Type *base, cy_stc_scb_spi_config_t const *config, cy_stc_scb_spi_context_t *context) +{ + cy_en_scb_spi_status_t retStatus = CY_SCB_SPI_BAD_PARAM; + + if ((NULL != base) && (NULL != config)) + { + /* Set SCLK mode for TI - CY_SCB_SPI_CPHA1_CPOL0, NS - CY_SCB_SPI_CPHA0_CPOL0, Motorola - take from config */ + uint32_t locSclkMode = (CY_SCB_SPI_MOTOROLA == config->subMode) ? config->sclkMode : + ((CY_SCB_SPI_NATIONAL == config->subMode) ? CY_SCB_SPI_CPHA0_CPOL0 : CY_SCB_SPI_CPHA1_CPOL0); + + /* Configure an SPI interface */ + base->CTRL = (((config->rxDataWidth <= CY_SCB_BYTE_WIDTH) && (config->txDataWidth <= CY_SCB_BYTE_WIDTH)) ? + SCB_CTRL_BYTE_MODE_Msk : 0UL) | + (config->enableWakeFromSleep ? SCB_CTRL_EC_AM_MODE_Msk : 0UL) | + _VAL2FLD(SCB_CTRL_OVS, (config->oversample - 1UL)) | + _VAL2FLD(SCB_CTRL_MODE, CY_SCB_CTRL_MODE_SPI); + + base->SPI_CTRL = (config->enableTransferSeperation ? 0UL : SCB_SPI_CTRL_SSEL_CONTINUOUS_Msk) | + ((0UL != (CY_SCB_SPI_TI_PRECEDE & config->subMode)) ? SCB_SPI_CTRL_SELECT_PRECEDE_Msk : 0UL) | + (config->enableMisoLateSample ? SCB_SPI_CTRL_LATE_MISO_SAMPLE_Msk : 0UL) | + (config->enableFreeRunSclk ? SCB_SPI_CTRL_SCLK_CONTINUOUS_Msk : 0UL) | + ((CY_SCB_SPI_MASTER == config->spiMode) ? SCB_SPI_CTRL_MASTER_MODE_Msk : 0UL) | + _VAL2FLD(CY_SCB_SPI_CTRL_CLK_MODE, locSclkMode) | + _VAL2FLD(CY_SCB_SPI_CTRL_SSEL_POLARITY, config->ssPolarity) | + _VAL2FLD(SCB_SPI_CTRL_MODE, config->subMode); + + /* Configure the RX direction */ + base->RX_CTRL = (config->enableMsbFirst ? SCB_RX_CTRL_MSB_FIRST_Msk : 0UL) | + (config->enableInputFilter ? SCB_RX_CTRL_MEDIAN_Msk : 0UL) | + _VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, (config->rxDataWidth - 1UL)); + + base->RX_FIFO_CTRL = _VAL2FLD(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, config->rxFifoTriggerLevel); + + /* Configure the TX direction */ + base->TX_CTRL = (config->enableMsbFirst ? SCB_RX_CTRL_MSB_FIRST_Msk : 0UL) | + _VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, (config->txDataWidth - 1UL)); + + base->TX_FIFO_CTRL = _VAL2FLD(SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, config->txFifoTriggerLevel); + + /* Set up interrupt sources */ + base->INTR_TX_MASK = config->txFifoIntEnableMask; + base->INTR_RX_MASK = config->rxFifoIntEnableMask; + base->INTR_M = (config->masterSlaveIntEnableMask & SCB_INTR_M_MASK_SPI_DONE_Msk); + base->INTR_S = (config->masterSlaveIntEnableMask & SCB_INTR_S_MASK_SPI_BUS_ERROR_Msk); + base->INTR_SPI_EC_MASK = 0UL; + + /* Initialize the context */ + if (NULL != context) + { + context->status = 0UL; + + context->txBufIdx = 0UL; + context->rxBufIdx = 0UL; + + context->cbEvents = NULL; + + #if !defined(NDEBUG) + /* Put an initialization key into the initKey variable to verify + * context initialization in the transfer API. + */ + context->initKey = CY_SCB_SPI_INIT_KEY; + #endif /* !(NDEBUG) */ + } + + retStatus = CY_SCB_SPI_SUCCESS; + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_DeInit +****************************************************************************//** +* +* De-initializes the SCB block, returns the register values to default. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \note +* Ensure that the SCB block is disabled before calling this function. +* +*******************************************************************************/ +void Cy_SCB_SPI_DeInit(CySCB_Type *base) +{ + /* SPI interface */ + base->CTRL = CY_SCB_CTRL_DEF_VAL; + base->SPI_CTRL = CY_SCB_SPI_CTRL_DEF_VAL; + + /* RX direction */ + base->RX_CTRL = CY_SCB_RX_CTRL_DEF_VAL; + base->RX_FIFO_CTRL = 0UL; + + /* TX direction */ + base->TX_CTRL = CY_SCB_TX_CTRL_DEF_VAL; + base->TX_FIFO_CTRL = 0UL; + + /* Disable all interrupt sources */ + base->INTR_SPI_EC_MASK = 0UL; + base->INTR_I2C_EC_MASK = 0UL; + base->INTR_RX_MASK = 0UL; + base->INTR_TX_MASK = 0UL; + base->INTR_M_MASK = 0UL; + base->INTR_S_MASK = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_Disable +****************************************************************************//** +* +* Disables the SCB block, clears context statuses and disables +* TX and RX interrupt sources. +* Note that after the block is disabled the TX and RX FIFOs and +* hardware statuses are cleared. Also, the hardware stops driving the output +* and ignores the input. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated +* by the user. The structure is used during the SPI operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* If only SPI functions which do not require context will be used pass NULL +* as pointer to context. +* +* \note +* Calling this function when the SPI is busy (master preforms data transfer or +* slave communicates with the master) may cause transfer corruption because the +* hardware stops driving the output and ignores the input. +* It is recommenced to ensure that the SPI is not busy before calling this +* function. +* +*******************************************************************************/ +void Cy_SCB_SPI_Disable(CySCB_Type *base, cy_stc_scb_spi_context_t *context) +{ + base->CTRL &= (uint32_t) ~SCB_CTRL_ENABLED_Msk; + + if (NULL != context) + { + context->status = 0UL; + + context->rxBufIdx = 0UL; + context->txBufIdx = 0UL; + } + + /* Disable RX and TX interrupt sources for the slave because + * RX overflow and TX underflow are kept enabled after the 1st call of + * Cy_SCB_SPI_Transfer(). + */ + if (!_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL)) + { + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_DeepSleep +****************************************************************************//** +* +* Prepares the SPI for deep sleep operation: clears the SPI wake up interrupt +* history and enables it. The wake-up event is the activation of the +* slave select line. +* This function does nothing if the deep sleep option has not been enabled. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \note +* Not all SCBs support the deep sleep operation, consult the device +* datasheet to determine which SCBs support deep sleep operation. +* +*******************************************************************************/ +void Cy_SCB_SPI_DeepSleep(CySCB_Type *base) +{ + if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, base->CTRL)) + { + /* Clear and enable the SPI wakeup source */ + Cy_SCB_ClearSpiInterrupt (base, CY_SCB_SPI_INTR_WAKEUP); + Cy_SCB_SetSpiInterruptMask(base, CY_SCB_SPI_INTR_WAKEUP); + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_Wakeup +****************************************************************************//** +* +* Disables the wakeup interrupt. +* This function does nothing if the deep sleep option has not been enabled. +* +* \param base +* The pointer to the SPI SCB instance. +* +*******************************************************************************/ +void Cy_SCB_SPI_Wakeup(CySCB_Type *base) +{ + if (_FLD2BOOL(SCB_CTRL_EC_AM_MODE, base->CTRL)) + { + /* Disable the SPI wakeup source */ + Cy_SCB_SetSpiInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } +} + + +/************************* High-Level Functions ******************************** +* The following functions are considered high-level. They provide the layer of +* intelligence to the SCB. These functions require interrupts. +* Low-level and high-level functions should not be mixed because low-level API +* can adversely affect the operation of high-level functions. +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_Transfer +****************************************************************************//** +* +* This function starts an SPI transfer operation. +* It configures transmit and receive buffers for an SPI transfer. +* If the data that will be received is not important, pass NULL as rxBuf. +* If the data that will be transmitted is not important, pass NULL as txBuf +* and then the \ref CY_SCB_SPI_DEFAULT_TX is sent out as each data element. +* +* After the function configures TX and RX interrupt sources, it returns and +* \ref Cy_SCB_SPI_Interrupt manages further data transfer. +* +* * In the master mode, the transfer operation is started after calling this +* function +* * In the slave mode, the transfer is registered and will be started when +* the master request arrives. +* +* When the transfer operation is completed (requested number of data elements +* sent and received), the \ref CY_SCB_SPI_TRANSFER_ACTIVE status is cleared +* and the \ref CY_SCB_SPI_TRANSFER_CMPLT_EVENT event is generated. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param txBuf +* The pointer of the buffer with data to transmit. +* The item size is defined by the data type which depends on the configured +* TX data width. +* +* \param rxBuf +* The pointer to the buffer to store received data. +* The item size is defined by the data type which depends on the configured +* RX data width. +* +* \param size +* The number of data elements to transmit and receive. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated +* by the user. The structure is used during the SPI operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_spi_status_t +* +* \note +* * The buffers must not be modified and stay allocated until the end of the +* transfer. +* * This function overrides all RX and TX FIFO interrupt sources and changes +* the RX and TX FIFO level. +* +*******************************************************************************/ +cy_en_scb_spi_status_t Cy_SCB_SPI_Transfer(CySCB_Type *base, void *txBuf, void *rxBuf, uint32_t size, cy_stc_scb_spi_context_t *context) +{ + cy_en_scb_spi_status_t retStatus = CY_SCB_SPI_TRANSFER_BUSY; + +#if !defined(NDEBUG) + /* Check that the initialization key was set before using the context */ + CY_ASSERT(NULL != context); + CY_ASSERT(CY_SCB_SPI_INIT_KEY == context->initKey); +#endif /* !(NDEBUG) */ + + /* Check if there are no active transfer requests */ + if (0UL == (CY_SCB_SPI_TRANSFER_ACTIVE & context->status)) + { + uint32_t fifoSize = Cy_SCB_GetFifoSize(base); + + /* Set up the context */ + context->status = CY_SCB_SPI_TRANSFER_ACTIVE; + + context->txBuf = txBuf; + context->txBufSize = size; + context->txBufIdx = 0UL; + + context->rxBuf = rxBuf; + context->rxBufSize = size; + context->rxBufIdx = 0UL; + + /* Set the TX interrupt when half of FIFO was transmitted */ + Cy_SCB_SetTxFifoLevel(base, fifoSize / 2UL); + + if (_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL)) + { + /* Trigger an RX interrupt: + * - If the transfer size is equal to or less than FIFO, trigger at the end of the transfer. + * - If the transfer size is greater than FIFO, trigger 1 byte earlier than the TX interrupt. + */ + Cy_SCB_SetRxFifoLevel(base, (size > fifoSize) ? ((fifoSize / 2UL) - 2UL) : (size - 1UL)); + + Cy_SCB_SetMasterInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + /* Enable interrupt sources to perform a transfer */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL); + Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); + } + else + { + /* Trigger an RX interrupt: + * - If the transfer size is equal to or less than half of FIFO, trigger ??at the end of the transfer. + * - If the transfer size is greater than half of FIFO, trigger 1 byte earlier than a TX interrupt. + */ + Cy_SCB_SetRxFifoLevel(base, (size > (fifoSize / 2UL)) ? ((fifoSize / 2UL) - 2UL) : (size - 1UL)); + + Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_SLAVE_INTR_SPI_BUS_ERROR); + + /* Enable interrupt sources to perform a transfer */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_OVERFLOW); + Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UNDERFLOW); + } + + retStatus = CY_SCB_SPI_SUCCESS; + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_AbortTransfer +****************************************************************************//** +* +* Aborts the current SPI transfer. +* It disables the transmit and RX interrupt sources, clears the TX +* and RX FIFOs and the status. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated +* by the user. The structure is used during the SPI operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* In the slave mode and after abort of transfer operation master continue +* sending data it gets into RX FIFO and TX FIFO is underflow as there is +* nothing to send. To drop this data, RX FIFO has to be cleared when +* the transfer is completed. Otherwise, received data will be kept and +* copied to the buffer when \ref Cy_SCB_SPI_Transfer is called. +* +* \sideeffect +* The transmit FIFO clear operation also clears the shift register, so that +* the shifter could be cleared in the middle of a data element transfer, +* corrupting it. The data element corruption means that all bits which has +* not been transmitted are transmitted as "ones" on the bus. +* +*******************************************************************************/ +void Cy_SCB_SPI_AbortTransfer(CySCB_Type *base, cy_stc_scb_spi_context_t *context) +{ + /* Disable interrupt sources */ + Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + if (_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL)) + { + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } + else + { + Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_OVERFLOW); + Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_UNDERFLOW); + } + + /* Clear FIFOs */ + Cy_SCB_SPI_ClearTxFifo(base); + Cy_SCB_SPI_ClearRxFifo(base); + + /* Clear the status to allow a new transfer */ + context->status = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_GetNumTransfered +****************************************************************************//** +* +* Returns the number of data elements transferred since the last call to \ref +* Cy_SCB_SPI_Transfer. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated +* by the user. The structure is used during the SPI operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* The number of data elements transferred. +* +*******************************************************************************/ +uint32_t Cy_SCB_SPI_GetNumTransfered(CySCB_Type const *base, cy_stc_scb_spi_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->rxBufIdx); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_GetTransferStatus +****************************************************************************//** +* +* Returns the status of the transfer operation started by +* \ref Cy_SCB_SPI_Transfer. +* This status is a bit mask and the value returned may have a multiple-bit set. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated +* by the user. The structure is used during the SPI operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref group_scb_spi_macro_xfer_status. +* +* \note +* The status is cleared by calling \ref Cy_SCB_SPI_Transfer or +* \ref Cy_SCB_SPI_AbortTransfer. +* +*******************************************************************************/ +uint32_t Cy_SCB_SPI_GetTransferStatus(CySCB_Type const *base, cy_stc_scb_spi_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->status); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_Interrupt +****************************************************************************//** +* +* This is the interrupt function for the SCB configured in the SPI mode. +* This function must be called inside the user-defined interrupt service +* routine in order for \ref Cy_SCB_SPI_Transfer to work. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated +* by the user. The structure is used during the SPI operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +void Cy_SCB_SPI_Interrupt(CySCB_Type *base, cy_stc_scb_spi_context_t *context) +{ + uint32 locXferErr = 0UL; + + /* Wake up on the slave select condition */ + if (0UL != (CY_SCB_SPI_INTR_WAKEUP & Cy_SCB_GetSpiInterruptStatusMasked(base))) + { + Cy_SCB_ClearSpiInterrupt(base, CY_SCB_SPI_INTR_WAKEUP); + } + + /* The slave error condition */ + if (0UL != (CY_SCB_SLAVE_INTR_SPI_BUS_ERROR & Cy_SCB_GetSlaveInterruptStatusMasked(base))) + { + locXferErr = CY_SCB_SPI_TRANSFER_ERR; + context->status |= CY_SCB_SPI_SLAVE_TRANSFER_ERR; + + Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_SPI_BUS_ERROR); + } + + /* The RX overflow error condition */ + if (0UL != (CY_SCB_RX_INTR_OVERFLOW & Cy_SCB_GetRxInterruptStatusMasked(base))) + { + locXferErr = CY_SCB_SPI_TRANSFER_ERR; + context->status |= CY_SCB_SPI_TRANSFER_OVERFLOW; + + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_OVERFLOW); + } + + /* The TX underflow error condition or slave complete data transfer */ + if (0UL != (CY_SCB_TX_INTR_UNDERFLOW & Cy_SCB_GetTxInterruptStatusMasked(base))) + { + locXferErr = CY_SCB_SPI_TRANSFER_ERR; + context->status |= CY_SCB_SPI_TRANSFER_UNDERFLOW; + + Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UNDERFLOW); + } + + /* Report an error, use a callback */ + if (0UL != locXferErr) + { + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_SPI_TRANSFER_ERR); + } + } + + /* RX direction */ + if (0UL != (CY_SCB_RX_INTR_LEVEL & Cy_SCB_GetRxInterruptStatusMasked(base))) + { + HandleReceive(base, context); + + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); + } + + /* TX direction */ + if (0UL != (CY_SCB_TX_INTR_LEVEL & Cy_SCB_GetTxInterruptStatusMasked(base))) + { + HandleTransmit(base, context); + + Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL); + } + + /* The transfer is complete: all data is loaded in the TX FIFO + * and all data is read from the RX FIFO + */ + if ((0UL != (context->status & CY_SCB_SPI_TRANSFER_ACTIVE)) && + (0UL == context->rxBufSize) && (0UL == context->txBufSize)) + { + /* The transfer is complete */ + context->status &= (uint32_t) ~CY_SCB_SPI_TRANSFER_ACTIVE; + + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_SPI_TRANSFER_CMPLT_EVENT); + } + } +} + + +/******************************************************************************* +* Function Name: HandleReceive +****************************************************************************//** +* +* Reads data from RX FIFO into the buffer provided by \ref Cy_SCB_SPI_Transfer. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated +* by the user. The structure is used during the SPI operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void HandleReceive(CySCB_Type *base, cy_stc_scb_spi_context_t *context) +{ + /* Get data in RX FIFO */ + uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base); + + /* Adjust the number to read */ + if (numToCopy > context->rxBufSize) + { + numToCopy = context->rxBufSize; + } + + /* Move the buffer */ + context->rxBufIdx += numToCopy; + context->rxBufSize -= numToCopy; + + /* Read data from RX FIFO */ + if (NULL != context->rxBuf) + { + uint8_t *buf = (uint8_t *) context->rxBuf; + + Cy_SCB_ReadArrayNoCheck(base, context->rxBuf, numToCopy); + + buf = &buf[(Cy_SCB_IsRxDataWidthByte(base) ? (numToCopy) : (2UL * numToCopy))]; + context->rxBuf = (void *) buf; + } + else + { + /* Discard read data. */ + DiscardArrayNoCheck(base, numToCopy); + } + + if (0UL == context->rxBufSize) + { + /* Disable the RX level interrupt */ + Cy_SCB_SetRxInterruptMask(base, (Cy_SCB_GetRxInterruptMask(base) & (uint32_t) ~CY_SCB_RX_INTR_LEVEL)); + } + else + { + uint32_t level = (_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL)) ? + Cy_SCB_GetFifoSize(base) : (Cy_SCB_GetFifoSize(base) / 2UL); + + if (context->rxBufSize < level) + { + Cy_SCB_SetRxFifoLevel(base, (context->rxBufSize - 1UL)); + } + } +} + + +/******************************************************************************* +* Function Name: HandleTransmit +****************************************************************************//** +* +* Loads TX FIFO with data provided by \ref Cy_SCB_SPI_Transfer. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated +* by the user. The structure is used during the SPI operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void HandleTransmit(CySCB_Type *base, cy_stc_scb_spi_context_t *context) +{ + uint32_t numToCopy; + uint32_t fifoSize = Cy_SCB_GetFifoSize(base); + + numToCopy = fifoSize - Cy_SCB_GetNumInTxFifo(base); + + /* Adjust the number to load */ + if (numToCopy > context->txBufSize) + { + numToCopy = context->txBufSize; + } + + /* Move the buffer */ + context->txBufIdx += numToCopy; + context->txBufSize -= numToCopy; + + /* Load TX FIFO with data */ + if (NULL != context->txBuf) + { + uint8_t *buf = (uint8_t *) context->txBuf; + + Cy_SCB_WriteArrayNoCheck(base, context->txBuf, numToCopy); + + buf = &buf[(Cy_SCB_IsTxDataWidthByte(base) ? (numToCopy) : (2UL * numToCopy))]; + context->txBuf = (void *) buf; + } + else + { + Cy_SCB_WriteDefaultArrayNoCheck(base, CY_SCB_SPI_DEFAULT_TX, numToCopy); + } + + if (0UL == context->txBufSize) + { + /* Data is transferred into TX FIFO */ + context->status |= CY_SCB_SPI_TRANSFER_IN_FIFO; + + /* Disable the TX level interrupt */ + Cy_SCB_SetTxInterruptMask(base, (Cy_SCB_GetTxInterruptMask(base) & (uint32_t) ~CY_SCB_TX_INTR_LEVEL)); + + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_SPI_TRANSFER_IN_FIFO_EVENT); + } + } +} + + +/******************************************************************************* +* Function Name: DiscardArrayNoCheck +****************************************************************************//** +* +* Reads the number of data elements from the SPI RX FIFO. The read data is +* discarded. Before calling this function, make sure that RX FIFO has +* enough data elements to read. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param size +* The number of data elements to read. +* +*******************************************************************************/ +static void DiscardArrayNoCheck(CySCB_Type const *base, uint32_t size) +{ + while (size > 0UL) + { + (void) Cy_SCB_SPI_Read(base); + --size; + } +} + + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_spi.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_spi.h new file mode 100644 index 0000000000..e3878e9ff9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_spi.h @@ -0,0 +1,1233 @@ +/***************************************************************************//** +* \file cy_scb_spi.h +* \version 1.0 +* +* Provides SPI API declarations of the SCB driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \addtogroup group_scb_spi +* \{ +* Driver API for SPI Bus Peripheral. +* +* Three different SPI protocols or modes are supported: +* * The original SPI protocol as defined by Motorola. +* * TI: Uses a short pulse on "spi_select" to indicate a start of transaction. +* * National Semiconductor (Microwire): Transmissions and Receptions occur +* separately. +* In addition to the standard 8-bit word length, the component supports a +* configurable 4- to 16-bit data width for communicating at non-standard SPI +* data widths. +* +* \section group_scb_spi_configuration Configuration Considerations +* +* To set up an SPI, provide configuration parameters in the +* \ref cy_stc_scb_spi_config_t structure. For example: provide spiMode, +* subMode, sclkMode, oversample, rxDataWidth, and txDataWidth. The other +* parameters are optional for operation. +* To initialize driver call \ref Cy_SCB_SPI_Init function providing the pointer +* to populated configuration structure +* \ref cy_stc_scb_spi_config_t and the pointer to allocated context structure +* \ref cy_stc_scb_spi_context_t. +* The clock source connected to the SCB SPI must be configured to provide +* the sufficient frequency and set the appropriate oversampling (only matters +* for the master mode) to reach the desired data rate. Call +* \ref Cy_SCB_SPI_Enable to start the SPI operation after configuration is +* completed. +* +* The SPI API are the same for the master and slave mode operation and +* are divided into two categories: low-level and high-level. Do not +* mix high-level and low-level API because a low-level API can adversely +* affect the operation of a higher level API. +* +* The Low-level API's functions allow interacting directly with the hardware +* and do not use interrupts. These functions do not require context for +* operation, thus NULL can be passed in \ref Cy_SCB_SPI_Init and +* \ref Cy_SCB_SPI_Disable instead of a pointer to the context structure. +* +* * To write data into the TX FIFO, use one of the provided functions: +* \ref Cy_SCB_SPI_Write, \ref Cy_SCB_SPI_WriteArray or +* \ref Cy_SCB_SPI_WriteArrayBlocking. +* Note that in the master mode, putting data into the TX FIFO starts a +* transfer. Due to the SPI nature, the received data is put into the RX FIFO. +* +* * To read data from the RX FIFO, use one of the provided functions: +* \ref Cy_SCB_SPI_Read or \ref Cy_SCB_SPI_ReadArray. +* +* * The statuses can be polled using: \ref Cy_SCB_SPI_GetRxFifoStatus, +* \ref Cy_SCB_SPI_GetTxFifoStatus and \ref Cy_SCB_SPI_GetSlaveMasterStatus. +* The statuses are W1C (Write 1 to Clear) and after a status is set, +* it must be cleared. Note that there are statuses evaluated as level. These +* statuses remain set when an event is true. Therefore, after the clear +* operation, the status is cleared but then it is restored (if event is still +* true). +* For example: the TX FIFO empty interrupt source can be cleared when the +* TX FIFO is not empty. Put at least two data elements (one goes to the +* shifter and next to FIFO) before clearing this status. +* +* The High-level API uses interrupts to execute a transfer. Call +* \ref Cy_SCB_SPI_Transfer to start communication: for the master mode a +* transfer to the slave is started while for the slave mode the Read and Write +* buffers are prepared for the following communication with the master. +* After a transfer is started, the \ref Cy_SCB_SPI_Interrupt handles the +* transfer until its completion. Therefore it must be called inside the +* user interrupt handler to make the high-level API work. To monitor the status +* of the transfer operation, use \ref Cy_SCB_SPI_GetTransferStatus. +* Alternately, use \ref Cy_SCB_SPI_RegisterCallback to register a callback +* function to be notified about \ref group_scb_spi_macro_callback_events. +* +* \section group_scb_spi_more_information More Information +* +* For more information on the SCB peripheral, refer to the technical reference +* manual (TRM). +* +* \section group_scb_spi_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and +* a different pointer to object type.The pointer to the buffer memory is void to allow handling different +* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). +*
14.2RAll non-null statements shall either: a) have at least one side-effect +* however executed, or b) cause control flow to change.The unused function parameters are cast to void. This statement +* has no side-effect and is used to suppress a compiler warning.
20.3RThe validity of values passed to library functions shall be checked. +* The CY_ASSERT() macro is used for verification of pointer to context +* parameter against NULL. This macro halts code execution if +* verification fails what ensures that NULL pointer is not dereference. +*
+* +* \section group_scb_spi_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_scb_spi_macro Macro +* \defgroup group_scb_spi_functions Functions +* \defgroup group_scb_spi_data_structures Data Structures +* \defgroup group_scb_spi_enums Enumerated Types +*/ + +#if !defined(CY_SCB_SPI_H) +#define CY_SCB_SPI_H + +#include "cy_scb_common.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Enumerated Types +***************************************/ + +/** +* \addtogroup group_scb_spi_enums +* \{ +*/ + +/** SPI status codes */ +typedef enum +{ + /** Operation completed successfully */ + CY_SCB_SPI_SUCCESS = 0x00U, + + /** One or more of input parameters are invalid */ + CY_SCB_SPI_BAD_PARAM = CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_SPI_ID | 1UL, + + /** + * The SPI is busy processing a transfer. Call this function again + * once that transfer is completed or aborted. + */ + CY_SCB_SPI_TRANSFER_BUSY +} cy_en_scb_spi_status_t; +/** \} group_scb_spi_enums */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_scb_spi_data_structures +* \{ +*/ + +/** +* Provides the typedef for the callback function called in the +* \ref Cy_SCB_SPI_Interrupt to notify the user about occurrences of +* \ref group_scb_spi_macro_callback_events. +*/ +typedef void (* scb_spi_handle_events_t)(uint32_t event); + + +/** SPI Configuration Structure */ +typedef struct cy_stc_scb_spi_config +{ + /** + * Specifies the mode of operation + * (See \ref group_scb_spi_macro_modes for the set of constants) + */ + uint32_t spiMode; + + /** + * Specifies the submode of SPI operation + * (See \ref group_scb_spi_macro_sub_modes for the set of constants) + */ + uint32_t subMode; + + /** + * Configures the SCLK operation for Motorola sub-mode, ignored for all + * other submodes (See \ref group_scb_spi_macro_sclk_modes for the set + * of constants) + */ + uint32_t sclkMode; + + /** + * Oversample factor for SPI. + * * For the master mode, the data rate is the SCB clock / oversample + * (valid range is 4-16). + * * For the slave mode, the oversample value is ignored. The data rate is + * determined by the SCB clock frequency. See the device datasheet for + * more details. + */ + uint32_t oversample; + + /** + * The width of RX data (valid range 4-16). It must be the same as + * \ref txDataWidth except in National sub-mode. + */ + uint32_t rxDataWidth; + + /** + * The width of TX data (valid range 4-16). It must be the same as + * \ref rxDataWidth except in National sub-mode. + */ + uint32_t txDataWidth; + + /** + * Enables the hardware to shift out the data element MSB first, otherwise, + * LSB first + */ + bool enableMsbFirst; + + /** + * Enables the master to generate a continuous SCLK regardless of whether + * there is data to send + */ + bool enableFreeRunSclk; + + /** + * Enables a digital 3-tap median filter to be applied to the input + * of the RX FIFO to filter glitches on the line. + */ + bool enableInputFilter; + + /** + * Enables the master to sample MISO line one half clock later to allow + * better timings. + */ + bool enableMisoLateSample; + + /** + * Enables the master to transmit each data element separated by a + * de-assertion of the slave select line (only applicable for the master + * mode) + */ + bool enableTransferSeperation; + + /** + * Sets active polarity of each SS line. + * This is a bit mask: bit 0 corresponds to SS0 and so on to SS3. + * 1 means active high, a 0 means active low. + */ + uint32_t ssPolarity; + + /** + * When set, the slave will wake the device when the slave select line + * becomes active. + * Note that not all SCBs support this mode. Consult the device + * datasheet to determine which SCBs support wake from deep sleep. + */ + bool enableWakeFromSleep; + + /** + * When there are more entries in the RX FIFO, then at this level + * the RX trigger output goes high. This output can be connected + * to a DMA channel through a trigger mux. + * Also, it controls the \ref CY_SCB_SPI_RX_TRIGGER interrupt source. + */ + uint32_t rxFifoTriggerLevel; + + /** + * Bits set in this mask will allow events to cause an interrupt + * (See \ref group_scb_spi_macro_rx_fifo_status for the set of constant) + */ + uint32_t rxFifoIntEnableMask; + + /** + * When there are fewer entries in the TX FIFO, then at this level + * the TX trigger output goes high. This output can be connected + * to a DMA channel through a trigger mux. + * Also, it controls the \ref CY_SCB_SPI_TX_TRIGGER interrupt source. + */ + uint32_t txFifoTriggerLevel; + + /** + * Bits set in this mask allow events to cause an interrupt + * (See \ref group_scb_spi_macro_tx_fifo_status for the set of constants) + */ + uint32_t txFifoIntEnableMask; + + /** + * Bits set in this mask allow events to cause an interrupt + * (See \ref group_scb_spi_macro_master_slave_status for the set of + * constants) + */ + uint32_t masterSlaveIntEnableMask; + +}cy_stc_scb_spi_config_t; + +/** SPI internal context structure */ +typedef struct cy_stc_scb_spi_context +{ + uint32_t volatile status; /**< Receive status */ + + void *rxBuf; /**< Pointer to receive buffer */ + uint32_t volatile rxBufSize; /**< Receive buffer size */ + uint32_t volatile rxBufIdx; /**< Pointer to receive buffer */ + + void *txBuf; /**< Pointer to transmit buffer */ + uint32_t volatile txBufSize; /**< Transmit buffer size */ + uint32_t volatile txBufIdx; /**< Index within transmit buffer */ + + /** + * The pointer to an event callback called when an SPI event occurs + */ + scb_spi_handle_events_t cbEvents; + +#if !defined(NDEBUG) + uint32_t initKey; /**< Tracks context initialization */ +#endif /* !(NDEBUG) */ +} cy_stc_scb_spi_context_t; + +/** \} group_scb_spi_data_structures */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_scb_spi_functions +* \{ +*/ + +/* Basic functions */ +cy_en_scb_spi_status_t Cy_SCB_SPI_Init(CySCB_Type *base, cy_stc_scb_spi_config_t const *config, + cy_stc_scb_spi_context_t *context); +void Cy_SCB_SPI_DeInit (CySCB_Type *base); +__STATIC_INLINE void Cy_SCB_SPI_Enable(CySCB_Type *base); +void Cy_SCB_SPI_Disable(CySCB_Type *base, cy_stc_scb_spi_context_t *context); + +/* Low-power functions */ +void Cy_SCB_SPI_DeepSleep(CySCB_Type *base); +void Cy_SCB_SPI_Wakeup (CySCB_Type *base); + +/* Configuration functions */ +__STATIC_INLINE void Cy_SCB_SPI_SetActiveSlaveSelect(CySCB_Type *base, uint32_t slaveSelect); +__STATIC_INLINE void Cy_SCB_SPI_SetActiveSlaveSelectPolarity(CySCB_Type *base, uint32_t slaveSelect, uint32_t polarity); + +/* Bus status */ +__STATIC_INLINE bool Cy_SCB_SPI_IsBusBusy(CySCB_Type const *base); + +/* Low-level: Receive direction */ +__STATIC_INLINE uint32_t Cy_SCB_SPI_Read (CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_SPI_ReadArray(CySCB_Type const *base, void *rxBuf, uint32_t size); + +__STATIC_INLINE uint32_t Cy_SCB_SPI_GetRxFifoStatus (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SPI_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask); +__STATIC_INLINE uint32_t Cy_SCB_SPI_GetNumInRxFifo (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SPI_ClearRxFifo (CySCB_Type *base); + +/* Low-level: Transmit direction */ +__STATIC_INLINE uint32_t Cy_SCB_SPI_Write (CySCB_Type *base, uint32_t data); +__STATIC_INLINE uint32_t Cy_SCB_SPI_WriteArray(CySCB_Type *base, void *txBuf, uint32_t size); +__STATIC_INLINE void Cy_SCB_SPI_WriteArrayBlocking(CySCB_Type *base, void *txBuf, uint32_t size); + +__STATIC_INLINE uint32_t Cy_SCB_SPI_GetTxFifoStatus (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SPI_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask); +__STATIC_INLINE uint32_t Cy_SCB_SPI_GetNumInTxFifo (CySCB_Type const *base); +__STATIC_INLINE bool Cy_SCB_SPI_IsTxComplete (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SPI_ClearTxFifo (CySCB_Type *base); + +/* Low-level: Master or slave status */ +__STATIC_INLINE uint32_t Cy_SCB_SPI_GetSlaveMasterStatus (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_SPI_ClearSlaveMasterStatus(CySCB_Type *base, uint32_t clearMask); + +/* High-level: callback */ +__STATIC_INLINE void Cy_SCB_SPI_RegisterCallback(CySCB_Type const *base, scb_spi_handle_events_t callback, + cy_stc_scb_spi_context_t *context); + +/* High-level: Transfer functions */ +cy_en_scb_spi_status_t Cy_SCB_SPI_Transfer(CySCB_Type *base, void *txBuf, void *rxBuf, uint32_t size, + cy_stc_scb_spi_context_t *context); +void Cy_SCB_SPI_AbortTransfer (CySCB_Type *base, cy_stc_scb_spi_context_t *context); +uint32_t Cy_SCB_SPI_GetNumTransfered (CySCB_Type const *base, cy_stc_scb_spi_context_t const *context); +uint32_t Cy_SCB_SPI_GetTransferStatus(CySCB_Type const *base,cy_stc_scb_spi_context_t const *context); + +/* High-level: Interrupt handler */ +void Cy_SCB_SPI_Interrupt(CySCB_Type *base, cy_stc_scb_spi_context_t *context); +/** \} group_scb_spi_functions */ + + +/*************************************** +* API Constants +***************************************/ + +/** +* \addtogroup group_scb_spi_macro +* \{ +*/ + +/** +* \defgroup group_scb_spi_macro_modes SPI Modes +* \{ +*/ +#define CY_SCB_SPI_SLAVE (0UL) /**< Configures SCB for SPI Slave operation */ +#define CY_SCB_SPI_MASTER (1UL) /**< Configures SCB for SPI Master operation */ +/** \} group_scb_spi_macro_modes */ + +/** +* \defgroup group_scb_spi_macro_sub_modes SPI Submodes +* \{ +*/ +/** Configures an SPI for a standard Motorola SPI operation */ +#define CY_SCB_SPI_MOTOROLA (0UL) + +/** +* Configures the SPI for the TI SPI operation. In the TI mode, the slave select +* is a pulse. In this case, the pulse coincides with the first bit. +*/ +#define CY_SCB_SPI_TI_COINCIDES (1UL) + +/** +* Configures an SPI for the TI SPI operation, in the TI mode. The slave select +* is a pulse. In this case the pulse precedes the first bit. +*/ +#define CY_SCB_SPI_TI_PRECEDES (1UL | CY_SCB_SPI_TI_PRECEDE) + +/** +* Configures an SPI for the National SPI operation. This is a half-duplex +* mode of operation. +*/ +#define CY_SCB_SPI_NATIONAL (2UL) +/** \} group_scb_spi_macro_sub_modes */ + +/** +* \defgroup group_scb_spi_macro_sclk_modes SPI SCLK Modes +* \{ +*/ +#define CY_SCB_SPI_CPHA0_CPOL0 (0UL) /**< Clock is active low, data is changed on first edge */ +#define CY_SCB_SPI_CPHA0_CPOL1 (1UL) /**< Clock is active high, data is changed on first edge */ +#define CY_SCB_SPI_CPHA1_CPOL0 (2UL) /**< Clock is active low, data is changed on second edge */ +#define CY_SCB_SPI_CPHA1_CPOL1 (3UL) /**< Clock is active high, data is changed on second edge */ +/** \} group_scb_spi_macro_sclk_modes */ + +/** +* \defgroup group_scb_spi_macro_slave_select SPI Slave Selects +* \{ +*/ +#define CY_SCB_SPI_SLAVE_SELECT0 (0UL) /**< Master will use Slave Select 0 */ +#define CY_SCB_SPI_SLAVE_SELECT1 (1UL) /**< Master will use Slave Select 1 */ +#define CY_SCB_SPI_SLAVE_SELECT2 (2UL) /**< Master will use Slave Select 2 */ +#define CY_SCB_SPI_SLAVE_SELECT3 (3UL) /**< Master will use Slave Select 3 */ +/** \} group_scb_spi_macro_slave_select */ + +/** +* \defgroup group_scb_spi_macro_tx_fifo_status SPI TX FIFO Statuses +* Each SPI TX FIFO status is encoded in a separate bit. Therefore multiple bits +* may be set to indicate the current status. +* \{ +*/ +/** The number of entries in the TX FIFO is less than the TX FIFO trigger level +* value +*/ +#define CY_SCB_SPI_TX_TRIGGER (SCB_INTR_TX_TRIGGER_Msk) + +/** The TX FIFO is not full, there is a space for more data */ +#define CY_SCB_SPI_TX_NOT_FULL (SCB_INTR_TX_NOT_FULL_Msk) + +/** +* The TX FIFO is empty, note that there may still be data in the shift register. +*/ +#define CY_SCB_SPI_TX_EMPTY (SCB_INTR_TX_EMPTY_Msk) + +/** An attempt to write to the full TX FIFO */ +#define CY_SCB_SPI_TX_OVERFLOW (SCB_INTR_TX_OVERFLOW_Msk) + +/** +* Applicable only for the slave mode. The master tried to read more +* data elements than available. +*/ +#define CY_SCB_SPI_TX_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk) +/** \} group_scb_spi_macro_tx_fifo_status */ + +/** +* \defgroup group_scb_spi_macro_rx_fifo_status SPI RX FIFO Statuses +* \{ +* Each SPI RX FIFO status is encoded in a separate bit. Therefore, multiple +* bits may be set to indicate the current status. +*/ +/** The number of entries in the RX FIFO is more than the RX FIFO trigger +* level value. +*/ +#define CY_SCB_SPI_RX_TRIGGER (SCB_INTR_RX_TRIGGER_Msk) + +/** The RX FIFO is not empty, there is data to read */ +#define CY_SCB_SPI_RX_NOT_EMPTY (SCB_INTR_RX_NOT_EMPTY_Msk) + +/** +* The RX FIFO is full. There is no more space for additional data. +* Any additional data will be dropped. +*/ +#define CY_SCB_SPI_RX_FULL (SCB_INTR_RX_FULL_Msk) + +/** +* The RX FIFO was full and there was an attempt to write to it. +* This additional data was dropped. +*/ +#define CY_SCB_SPI_RX_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk) + +/** An attempt to read from an empty RX FIFO */ +#define CY_SCB_SPI_RX_UNDERFLOW (SCB_INTR_RX_UNDERFLOW_Msk) +/** \} group_scb_spi_macro_rx_fifo_status */ + +/** +* \defgroup group_scb_spi_macro_master_slave_status SPI Master and Slave Statuses +* \{ +*/ +/** The slave was deselected at the wrong time */ +#define CY_SCB_SPI_SLAVE_ERR (SCB_INTR_S_SPI_BUS_ERROR_Msk) + +/** The master has transmitted all data elements from FIFO and shifter */ +#define CY_SCB_SPI_MASTER_DONE (SCB_INTR_M_SPI_DONE_Msk) +/** \} group_scb_spi_macro_master_slave_status */ + +/** +* \defgroup group_scb_spi_macro_xfer_status SPI Transfer Status +* \{ +* Each SPI transfer status is encoded in a separate bit, therefore multiple bits +* may be set to indicate the current status. +*/ +/** +* Transfer started by \ref Cy_SCB_SPI_Transfer is in progress. +*/ +#define CY_SCB_SPI_TRANSFER_ACTIVE (0x01UL) + +/** +* All TX data from \ref Cy_SCB_SPI_Transfer is in the TX FIFO. +*/ +#define CY_SCB_SPI_TRANSFER_IN_FIFO (0x02UL) + +/** The slave was deselected at the wrong time. */ +#define CY_SCB_SPI_SLAVE_TRANSFER_ERR (SCB_INTR_S_SPI_BUS_ERROR_Msk) + +/** +* RX FIFO was full and there was an attempt to write to it. +* This additional data was dropped. +*/ +#define CY_SCB_SPI_TRANSFER_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk) + +/** +* Applicable only for the slave mode. The master tried to read more +* data elements than available in the TX FIFO. +*/ +#define CY_SCB_SPI_TRANSFER_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk) +/** \} group_scb_spi_macro_xfer_status */ + +/** +* \defgroup group_scb_spi_macro_callback_events SPI Callback Events +* \{ +* Only single event is notified by the callback. +*/ +/** All TX data from \ref Cy_SCB_SPI_Transfer is in the TX FIFO.*/ +#define CY_SCB_SPI_TRANSFER_IN_FIFO_EVENT (0x01U) + +/** The transfer started by \ref Cy_SCB_SPI_Transfer is complete.*/ +#define CY_SCB_SPI_TRANSFER_CMPLT_EVENT (0x02U) + +/** +* An error occurred during the transfer. This includes overflow, underflow +* and a transfer error. Check \ref Cy_SCB_SPI_GetTransferStatus. +*/ +#define CY_SCB_SPI_TRANSFER_ERR_EVENT (0x04U) +/** \} group_scb_spi_macro_callback_events */ + +/** +* \defgroup group_scb_spi_macro_polarity SPI Polarity +* \{ +*/ +#define CY_SCB_SPI_ACTIVE_LOW (0UL) /**< Signal in question is active low */ +#define CY_SCB_SPI_ACTIVE_HIGH (1UL) /**< Signal in question is active high */ +/** \} group_scb_spi_macro_polarity */ + +/** Default TX value when no TX buffer is defined */ +#define CY_SCB_SPI_DEFAULT_TX (0x0000FFFFUL) + +/** Data returned by the hardware when an empty RX FIFO is read */ +#define CY_SCB_SPI_RX_NO_DATA (0xFFFFFFFFUL) + + +/*************************************** +* Internal Constants +***************************************/ + +/** \cond INTERNAL */ +#define CY_SCB_SPI_TI_PRECEDE (0x10UL) + +#define CY_SCB_SPI_RX_INTR (CY_SCB_SPI_RX_TRIGGER | CY_SCB_SPI_RX_NOT_EMPTY | CY_SCB_SPI_RX_FULL | \ + CY_SCB_SPI_RX_OVERFLOW | CY_SCB_SPI_RX_UNDERFLOW) + +#define CY_SCB_SPI_TX_INTR (CY_SCB_SPI_TX_TRIGGER | CY_SCB_SPI_TX_NOT_FULL | CY_SCB_SPI_TX_EMPTY | \ + CY_SCB_SPI_TX_OVERFLOW | CY_SCB_SPI_TX_UNDERFLOW) + +#define CY_SCB_SPI_TRANSFER_ERR (CY_SCB_SPI_SLAVE_TRANSFER_ERR | CY_SCB_SPI_TRANSFER_OVERFLOW | \ + CY_SCB_SPI_TRANSFER_UNDERFLOW) + +#define CY_SCB_SPI_INIT_KEY (0x00ABCDEFUL) +/** \endcond */ + +/** \} group_scb_spi_macro */ + + +/*************************************** +* In-line Function Implementation +***************************************/ + +/** +* \addtogroup group_scb_spi_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_Enable +****************************************************************************//** +* +* Enables the SCB block for the SPI operation. +* +* \param base +* The pointer to the SPI SCB instance. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SPI_Enable(CySCB_Type *base) +{ + base->CTRL |= SCB_CTRL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_IsBusBusy +****************************************************************************//** +* +* Returns whether the SPI bus is busy or not. The bus busy is determined using +* the slave select signal. +* * Motorola and National Semiconductor sub-modes: the bus is busy after the +* slave select line is activated and lasts until the slave select line is +* deactivated. +* * Texas Instrument sub-modes: The bus is busy at the moment of the initial +* pulse on the slave select line and lasts until the transfer is complete. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \return +* True - the bus is busy, false - the bus is idle. +* +* \note +* * The SPI master does not assign the slave select line immediately after +* the 1st data element is written into the TX FIFO. It takes up to 2 SCLK +* clocks to assign the slave select line. Before this happens, the bus +* is considered idle. +* * If the SPI master is configured to separate a data elements transfer, +* the bus is busy during each element transfer and is free between them. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SCB_SPI_IsBusBusy(CySCB_Type const *base) +{ + return _FLD2BOOL(SCB_SPI_STATUS_BUS_BUSY, base->SPI_STATUS); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_SetActiveSlaveSelect +****************************************************************************//** +* +* Selects an active slave select line from one of four available. +* This function is applicable for the master and slave. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param slaveSelect +* The slave select line number. +* See \ref group_scb_spi_macro_slave_select for the set of constants. +* +* \note +* The SCB be idle or disabled before calling this function. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SPI_SetActiveSlaveSelect(CySCB_Type *base, uint32_t slaveSelect) +{ + base->SPI_CTRL = _CLR_SET_FLD32U(base->SPI_CTRL, SCB_SPI_CTRL_SSEL, slaveSelect); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_SetActiveSlaveSelectPolarity +****************************************************************************//** +* +* Sets the active polarity for the slave select line. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param slaveSelect +* The slave select line number. +* See \ref group_scb_spi_macro_slave_select for the set of constants. +* +* \param polarity +* The polarity of the slave select line. +* See \ref group_scb_spi_macro_polarity for the set of constants. +* +* \note +* The SCB be idle or disabled before calling this function. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SPI_SetActiveSlaveSelectPolarity(CySCB_Type *base, uint32_t slaveSelect, uint32_t polarity) +{ + uint32_t mask = _VAL2FLD(CY_SCB_SPI_CTRL_SSEL_POLARITY, (1UL << slaveSelect)); + + if (0UL != polarity) + { + base->SPI_CTRL |= (uint32_t) mask; + } + else + { + base->SPI_CTRL &= (uint32_t) ~mask; + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_GetRxFifoStatus +****************************************************************************//** +* +* Returns the current status of the RX FIFO. +* Clear the active statuses to let the SCB hardware update them. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \return +* \ref group_scb_spi_macro_rx_fifo_status +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_SPI_GetRxFifoStatus(CySCB_Type const *base) +{ + return (Cy_SCB_GetRxInterruptStatus(base) & CY_SCB_SPI_RX_INTR); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_ClearRxFifoStatus +****************************************************************************//** +* +* Clears the selected statuses of the RX FIFO. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param clearMask +* The mask of which statuses to clear. +* See \ref group_scb_spi_macro_rx_fifo_status for the set of constants. +* +* \note +* * This status is also used for interrupt generation, so clearing it also +* clears the interrupt sources. +* * Level sensitive statuses such as \ref CY_SCB_SPI_RX_TRIGGER, +* \ref CY_SCB_SPI_RX_NOT_EMPTY and \ref CY_SCB_SPI_RX_FULL set high again after +* being cleared if the condition remains true. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SPI_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask) +{ + Cy_SCB_ClearRxInterrupt(base, clearMask); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_GetNumInRxFifo +****************************************************************************//** +* +* Returns the number of data elements in the SPI RX FIFO. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \return +* The number of data elements in the RX FIFO. +* The size of a data element defined by the configured RX data width. +* +* \note +* This number does not include any data currently in the RX shifter. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_SPI_GetNumInRxFifo(CySCB_Type const *base) +{ + return Cy_SCB_GetNumInRxFifo(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_ClearRxFifo +****************************************************************************//** +* +* Clears all data out of the SPI RX FIFO. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \sideeffect +* Any data currently in the shifter is cleared and lost. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SPI_ClearRxFifo(CySCB_Type *base) +{ + Cy_SCB_ClearRxFifo(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_GetTxFifoStatus +****************************************************************************//** +* +* Returns the current status of the TX FIFO. +* Clear the active statuses to let the SCB hardware update them. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \return +* \ref group_scb_spi_macro_tx_fifo_status +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_SPI_GetTxFifoStatus(CySCB_Type const *base) +{ + return (Cy_SCB_GetTxInterruptStatus(base) & CY_SCB_SPI_TX_INTR); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_ClearTxFifoStatus +****************************************************************************//** +* +* Clears the selected statuses of the TX FIFO. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param clearMask +* The mask of which statuses to clear. +* See \ref group_scb_spi_macro_tx_fifo_status for the set of constants. +* +* \note +* * The status is also used for interrupt generation, so clearing it also +* clears the interrupt sources. +* * Level sensitive statuses such as \ref CY_SCB_SPI_TX_TRIGGER, +* \ref CY_SCB_SPI_TX_EMPTY and \ref CY_SCB_SPI_TX_NOT_FULL set high again after +* being cleared if the condition remains true. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SPI_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask) +{ + Cy_SCB_ClearTxInterrupt(base, clearMask); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_GetNumInTxFifo +****************************************************************************//** +* +* Returns the number of data elements in the SPI TX FIFO. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \return +* The number of data elements in the TX FIFO. +* The size of a data element defined by the configured TX data width. +* +* \note +* This number does not include any data currently in the TX shifter. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_SPI_GetNumInTxFifo(CySCB_Type const *base) +{ + return Cy_SCB_GetNumInTxFifo(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_IsTxComplete +****************************************************************************//** +* +* Checks if the TX FIFO and Shifter are empty and there is no more data to send +* +* \param base +* Pointer to the SPI SCB instance. +* +* \return +* If true, transmission complete. If false, transmission is not complete. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SCB_SPI_IsTxComplete(CySCB_Type const *base) +{ + return Cy_SCB_IsTxComplete(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_ClearTxFifo +****************************************************************************//** +* +* Clears all data out of the SPI TX FIFO. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \sideeffect +* The TX FIFO clear operation also clears the shift register, so that +* the shifter could be cleared in the middle of a data element transfer, +* corrupting it. The data element corruption means that all bits which has +* not been transmitted are transmitted as 1s on the bus. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SPI_ClearTxFifo(CySCB_Type *base) +{ + Cy_SCB_ClearTxFifo(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_GetSlaveMasterStatus +****************************************************************************//** +* +* Returns the current status of either the slave or the master, depending +* on the configured SPI mode. +* Clear the active statuses to let the SCB hardware update them. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \return +* \ref group_scb_spi_macro_master_slave_status +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_SPI_GetSlaveMasterStatus(CySCB_Type const *base) +{ + uint32_t retStatus; + + if (_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL)) + { + retStatus = (Cy_SCB_GetMasterInterruptStatus(base) & CY_SCB_MASTER_INTR_SPI_DONE); + } + else + { + retStatus = (Cy_SCB_GetSlaveInterruptStatus(base) & CY_SCB_SLAVE_INTR_SPI_BUS_ERROR); + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_ClearSlaveMasterStatus +****************************************************************************//** +* +* Clears the selected statuses of either the slave or the master. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param clearMask +* The mask of which statuses to clear. +* See \ref group_scb_spi_macro_master_slave_status for the set of constants. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SPI_ClearSlaveMasterStatus(CySCB_Type *base, uint32_t clearMask) +{ + if (_FLD2BOOL(SCB_SPI_CTRL_MASTER_MODE, base->SPI_CTRL)) + { + Cy_SCB_ClearMasterInterrupt(base, clearMask); + } + else + { + Cy_SCB_ClearSlaveInterrupt(base, clearMask); + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_Read +****************************************************************************//** +* +* Reads a single data element from the SPI RX FIFO. +* This function does not check if the RX FIFO has data before reading it. +* If the RX FIFO is empty, the function returns \ref CY_SCB_SPI_RX_NO_DATA. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \return +* Data from the RX FIFO. +* The data element size is defined by the configured RX data width. +* +* \note +* * This function only reads data available in the RX FIFO. It does not +* initiate an SPI transfer. +* * When in the master mode, writes data into the TX FIFO and waits until +* the transfer is completed before getting data from the RX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_SPI_Read(CySCB_Type const *base) +{ + return Cy_SCB_ReadRxFifo(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_ReadArray +****************************************************************************//** +* +* Reads an array of data out of the SPI RX FIFO. +* This function does not block. It returns how many data elements were read +* from the RX FIFO. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param rxBuf +* The pointer to the location to place data read from the RX FIFO. +* The item size is defined by the data type which depends on the configured +* RX data width. +* +* \param size +* The number of data elements to read from the RX FIFO. +* +* \return +* The number of data elements read from the RX FIFO. +* +* \note +* * This function only reads data available in the RX FIFO. It does not +* initiate an SPI transfer. +* * When in the master mode, writes data into the TX FIFO and waits until +* the transfer is completed before getting data from the RX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_SPI_ReadArray(CySCB_Type const *base, void *rxBuf, uint32_t size) +{ + return Cy_SCB_ReadArray(base, rxBuf, size); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_Write +****************************************************************************//** +* +* Places a single data element in the SPI TX FIFO. +* This function does not block. It returns how many data elements were placed +* in the TX FIFO. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param data +* Data to put in the TX FIFO. +* The item size is defined by the data type, which depends on the configured +* TX data width. +* +* \return +* The number of data elements placed in the TX FIFO: 0 or 1. +* +* \note +* * When in the master mode, writing data into the TX FIFO starts an SPI +* transfer. +* * When in the slave mode, writing data into the TX FIFO does not start +* an SPI transfer. The data is loaded in the TX FIFO and will be sent +* to the master on its request. +* * The SPI interface is full-duplex, therefore reads and writtes occur +* at the same time. Thus for every data element transferred out of the +* TX FIFO, one is transferred into the RX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_SPI_Write(CySCB_Type *base, uint32_t data) +{ + return Cy_SCB_Write(base, data); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_WriteArray +****************************************************************************//** +* +* Places an array of data in the SPI TX FIFO. This function does not +* block. It returns how many data elements were placed in the TX FIFO. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param txBuf +* The pointer to the data to place in the TX FIFO. +* The item size is defined by the data type, which depends on the configured +* TX data width. +* +* \param size +* The number of data elements to transmit. +* +* \return +* The number of data elements placed in the TX FIFO. +* +* \note +* * When in the master mode, writing data into the TX FIFO starts an SPI +* transfer. +* * When in the slave mode, writing data into the TX FIFO does not start +* an SPI transfer. The data is loaded in the TX FIFO and will be sent to +* the master on its request. +* * The SPI interface is full-duplex, therefore reads and writtes occur +* at the same time. Thus for every data element transferred out of the +* TX FIFO, one is transferred into the RX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_SPI_WriteArray(CySCB_Type *base, void *txBuf, uint32_t size) +{ + return Cy_SCB_WriteArray(base, txBuf, size); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_WriteArrayBlocking +****************************************************************************//** +* +* Places an array of data in the SPI TX FIFO. This function blocks +* until the number of data elements specified by size is placed in the SPI +* TX FIFO. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param txBuf +* The pointer to data to place in the TX FIFO. +* The item size is defined by the data type, which depends on the configured +* TX data width. +* +* \param size +* The number of data elements to write into the TX FIFO. +* +* \note +* * When in the master mode, writing data into the TX FIFO starts an SPI +* transfer. +* * When in the slave mode, writing data into the TX FIFO does not start +* an SPI transfer. The data is loaded in the TX FIFO and will be sent to +* the master on its request. +* * The SPI interface is full-duplex, therefore reads and writtes occur +* at the same time. Thus for every data element transferred out of the +* TX FIFO, one is transferred into the RX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SPI_WriteArrayBlocking(CySCB_Type *base, void *txBuf, uint32_t size) +{ + Cy_SCB_WriteArrayBlocking(base, txBuf, size); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_SPI_RegisterCallback +****************************************************************************//** +* +* Registers a callback function, which notifies that +* \ref group_scb_spi_macro_callback_events occurred in the +* \ref Cy_SCB_SPI_Interrupt. +* +* \param base +* The pointer to the SPI SCB instance. +* +* \param callback +* The pointer to the callback function. +* See \ref scb_spi_handle_events_t for the function prototype. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_spi_context_t allocated +* by the user. The structure is used during the SPI operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* To remove the callback, pass NULL as the pointer to the callback function. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_SPI_RegisterCallback(CySCB_Type const *base, + scb_spi_handle_events_t callback, cy_stc_scb_spi_context_t *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + context->cbEvents = callback; +} + +/** \} group_scb_spi_functions */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_scb_spi */ + +#endif /* (CY_SCB_SPI_H) */ + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_uart.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_uart.c new file mode 100644 index 0000000000..c5a57ebe3b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_uart.c @@ -0,0 +1,1181 @@ +/***************************************************************************//** +* \file cy_scb_uart.c +* \version 1.0 +* +* Provides UART API implementation of the SCB driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_scb_uart.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/* Static functions */ +static void HandleDataReceive (CySCB_Type *base, cy_stc_scb_uart_context_t *context); +static void HandleRingBuffer (CySCB_Type *base, cy_stc_scb_uart_context_t *context); +static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context); + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_Init +****************************************************************************//** +* +* Initializes the SCB for UART operation. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param config +* The pointer to configuration structure \ref cy_stc_scb_uart_config_t. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* If only UART functions which do not require context will be used pass NULL +* as pointer to context. +* +* \return +* \ref cy_en_scb_uart_status_t +* +* \note +* Ensure that the SCB block is disabled before calling this function. +* +*******************************************************************************/ +cy_en_scb_uart_status_t Cy_SCB_UART_Init(CySCB_Type *base, cy_stc_scb_uart_config_t const *config, cy_stc_scb_uart_context_t *context) +{ + cy_en_scb_uart_status_t retStatus = CY_SCB_UART_BAD_PARAM; + + if ((NULL != base) && (NULL != config)) + { + uint32_t ovs; + + if ((CY_SCB_UART_IRDA == config->uartMode) && (!config->irdaEnableLowPowerReceiver)) + { + /* For Normal IrDA mode oversampling is always zero */ + ovs = 0UL; + } + else + { + ovs = (config->oversample - 1UL); + } + + /* Configure the UART interface */ + base->CTRL = (config->enableMutliProcessorMode ? SCB_CTRL_ADDR_ACCEPT_Msk : 0UL) | + ((config->dataWidth <= CY_SCB_BYTE_WIDTH) ? SCB_CTRL_BYTE_MODE_Msk : 0UL) | + _VAL2FLD(SCB_CTRL_OVS, ovs) | + _VAL2FLD(SCB_CTRL_MODE, CY_SCB_CTRL_MODE_UART); + + base->UART_CTRL = _VAL2FLD(SCB_UART_CTRL_MODE, config->uartMode); + + /* Configure the RX direction */ + base->UART_RX_CTRL = (config->irdaInvertRx ? SCB_UART_RX_CTRL_POLARITY_Msk : 0UL) | + (config->enableMutliProcessorMode ? SCB_UART_RX_CTRL_MP_MODE_Msk : 0UL) | + (config->dropOnParityError ? SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk : 0UL) | + (config->dropOnFrameError ? SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk : 0UL) | + _VAL2FLD(SCB_UART_RX_CTRL_BREAK_WIDTH, (config->breakWidth - 1UL)) | + _VAL2FLD(SCB_UART_RX_CTRL_STOP_BITS, (config->stopBits - 1UL)) | + _VAL2FLD(CY_SCB_UART_RX_CTRL_SET_PARITY, config->parity); + + base->RX_CTRL = (config->enableMsbFirst ? SCB_RX_CTRL_MSB_FIRST_Msk : 0UL) | + (config->enableInputFilter ? SCB_RX_CTRL_MEDIAN_Msk : 0UL) | + _VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, (config->dataWidth - 1UL)); + + base->RX_MATCH = _VAL2FLD(SCB_RX_MATCH_ADDR, config->receiverAddress) | + _VAL2FLD(SCB_RX_MATCH_MASK, config->receiverAddressMask); + + /* Configure the TX direction */ + base->UART_TX_CTRL = (config->smartCardRetryOnNack ? SCB_UART_TX_CTRL_RETRY_ON_NACK_Msk : 0UL) | + _VAL2FLD(SCB_UART_TX_CTRL_STOP_BITS, (config->stopBits - 1UL)) | + _VAL2FLD(CY_SCB_UART_RX_CTRL_SET_PARITY, config->parity); + + base->TX_CTRL = (config->enableMsbFirst ? SCB_RX_CTRL_MSB_FIRST_Msk : 0UL) | + _VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, (config->dataWidth - 1UL)); + + base->RX_FIFO_CTRL = _VAL2FLD(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, config->rxFifoTriggerLevel); + + /* Configure the flow control */ + base->UART_FLOW_CTRL = (config->enableCts ? SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk : 0UL) | + ((CY_SCB_UART_ACTIVE_HIGH == config->ctsPolarity) ? SCB_UART_FLOW_CTRL_CTS_POLARITY_Msk : 0UL) | + ((CY_SCB_UART_ACTIVE_HIGH == config->rtsPolarity) ? SCB_UART_FLOW_CTRL_RTS_POLARITY_Msk : 0UL) | + _VAL2FLD(SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, config->rtsRxFifoLevel); + + + base->TX_FIFO_CTRL = _VAL2FLD(SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, config->txFifoTriggerLevel); + + /* Set up interrupt sources */ + base->INTR_TX_MASK = config->txFifoIntEnableMask; + base->INTR_RX_MASK = config->rxFifoIntEnableMask; + + /* Initialize context */ + if (NULL != context) + { + context->rxStatus = 0UL; + context->txStatus = 0UL; + + context->rxRingBuf = NULL; + context->rxRingBufSize = 0UL; + + context->rxBufIdx = 0UL; + context->txLeftToTransmit = 0UL; + + context->cbEvents = NULL; + + #if !defined(NDEBUG) + /* Put an initialization key into the initKey variable to verify + * context initialization in the transfer API. + */ + context->initKey = CY_SCB_UART_INIT_KEY; + #endif /* !(NDEBUG) */ + } + + retStatus = CY_SCB_UART_SUCCESS; + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_DeInit +****************************************************************************//** +* +* De-initializes the SCB block, returns the register values to default. +* +* \param base +* The pointer to the UART SCB instance. +* +* \note +* Ensure that the SCB block is disabled before calling this function. +* +*******************************************************************************/ +void Cy_SCB_UART_DeInit(CySCB_Type *base) +{ + /* De-initialize the UART interface */ + base->CTRL = CY_SCB_CTRL_DEF_VAL; + base->UART_CTRL = CY_SCB_UART_CTRL_DEF_VAL; + + /* De-initialize the RX direction */ + base->UART_RX_CTRL = 0UL; + base->RX_CTRL = CY_SCB_RX_CTRL_DEF_VAL; + base->RX_FIFO_CTRL = 0UL; + base->RX_MATCH = 0UL; + + /* De-initialize the TX direction */ + base->UART_TX_CTRL = 0UL; + base->TX_CTRL = CY_SCB_TX_CTRL_DEF_VAL; + base->TX_FIFO_CTRL = 0UL; + + /* De-initialize the flow control */ + base->UART_FLOW_CTRL = 0UL; + + /* De-initialize the interrupt sources */ + base->INTR_SPI_EC_MASK = 0UL; + base->INTR_I2C_EC_MASK = 0UL; + base->INTR_RX_MASK = 0UL; + base->INTR_TX_MASK = 0UL; + base->INTR_M_MASK = 0UL; + base->INTR_S_MASK = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_Disable +****************************************************************************//** +* +* Disables the SCB block and clears context statuses. +* Note that after the block is disabled, the TX and RX FIFOs and +* hardware statuses are cleared. Also, the hardware stops driving the +* output and ignores the input. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* If only UART functions which do not require context will be used pass NULL +* as pointer to context. +* +* \note +* Calling this function when the UART is busy (transmitter preforms data +* transfer or receiver is in the middle of data reception) may result transfer +* corruption because the hardware stops driving the output and ignores +* the input. +* Ensure that the UART is not busy before calling this function. +* +*******************************************************************************/ +void Cy_SCB_UART_Disable(CySCB_Type *base, cy_stc_scb_uart_context_t *context) +{ + base->CTRL &= (uint32_t) ~SCB_CTRL_ENABLED_Msk; + + if (NULL != context) + { + context->rxStatus = 0UL; + context->txStatus = 0UL; + + context->rxBufIdx = 0UL; + context->txLeftToTransmit = 0UL; + } +} + + +/************************* High-Level Functions ******************************** +* The following functions are considered high-level. They provide the layer of +* intelligence to the SCB. These functions require interrupts. +* Low-level and high-level functions should not be mixed because low-level API +* can adversely affect the operation of high-level functions. +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_StartRingBuffer +****************************************************************************//** +* +* Starts the receive ring buffer operation. +* The RX interrupt source is configured to get data from the RX +* FIFO and put into the ring buffer. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param ringBuffer +* Pointer to the user defined ring buffer. +* The item size is defined by the data type which depends on the configured +* data width. +* +* \param size +* The size of the receive ring buffer. +* Note that one data element is used for internal use, so if the size is 32, +* then only 31 data elements are used for data storage. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* * The buffer must not be modified and stay allocated while the ring buffer +* operates. +* * This function overrides the RX interrupt sources and changes the +* RX FIFO level. +* +*******************************************************************************/ +void Cy_SCB_UART_StartRingBuffer(CySCB_Type *base, void *ringBuffer, uint32_t size, cy_stc_scb_uart_context_t *context) +{ +#if !defined(NDEBUG) + /* Check that the initialization key was set before using the context */ + CY_ASSERT(NULL != context); + CY_ASSERT(CY_SCB_UART_INIT_KEY == context->initKey); +#endif /* !(NDEBUG) */ + + if ((NULL != ringBuffer) && (size > 0UL)) + { + uint32_t halfFifoSize = (Cy_SCB_GetFifoSize(base) / 2UL); + + context->rxRingBuf = ringBuffer; + context->rxRingBufSize = size; + context->rxRingBufHead = 0UL; + context->rxRingBufTail = 0UL; + + /* Set up an RX interrupt to handle the ring buffer */ + Cy_SCB_SetRxFifoLevel(base, (size >= halfFifoSize) ? (halfFifoSize - 1UL) : (size - 1UL)); + + Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL); + } +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_StopRingBuffer +****************************************************************************//** +* +* Stops receiving data into the ring buffer, and clears the ring buffer. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +void Cy_SCB_UART_StopRingBuffer(CySCB_Type *base, cy_stc_scb_uart_context_t *context) +{ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + Cy_SCB_UART_ClearRingBuffer(base, context); + + context->rxRingBuf = NULL; + context->rxRingBufSize = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetNumInRingBuffer +****************************************************************************//** +* +* Returns the number of data elements in the ring buffer. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* The number of data elements in the receive ring buffer. +* +* \note +* One data element is used for internal use, so when the buffer is full, +* this function returns (Ring Buffer size - 1). +* +*******************************************************************************/ +uint32_t Cy_SCB_UART_GetNumInRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context) +{ + uint32_t size; + uint32_t locHead = context->rxRingBufHead; + + /* Suppress a compiler warning about unused variables */ + (void) base; + + if (locHead >= context->rxRingBufTail) + { + size = (locHead - context->rxRingBufTail); + } + else + { + size = (locHead + (context->rxBufSize - context->rxRingBufTail)); + } + + return (size); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_ClearRingBuffer +****************************************************************************//** +* +* Clears the ring buffer. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +void Cy_SCB_UART_ClearRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context_t *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + context->rxRingBufHead = context->rxRingBufTail; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_Receive +****************************************************************************//** +* +* This function starts a UART receive operation. +* It configures the receive interrupt sources to get data available in the +* receive FIFO and returns. The \ref Cy_SCB_UART_Interrupt manages the further +* data transfer. +* +* If the ring buffer is enabled, this function first reads data from the ring +* buffer. If there is more data to receive, it configures the receive interrupt +* sources to copy the remaining bytes from the RX FIFO when they arrive. +* +* When the receive operation is completed (requested number of data elements +* received) the \ref CY_SCB_UART_RECEIVE_ACTIVE status is cleared and +* the \ref CY_SCB_UART_RECEIVE_DONE_EVENT event is generated. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param rxBuf +* Pointer to buffer to store received data. +* The item size is defined by the data type which depends on the configured +* data width. +* +* \param size +* The number of data elements to receive. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_uart_status_t +* +* \note +* * The buffer must not be modified and stay allocated until end of the +* receive operation. +* * This function overrides the RX interrupt sources and changes the +* RX FIFO level. +* +*******************************************************************************/ +cy_en_scb_uart_status_t Cy_SCB_UART_Receive(CySCB_Type *base, void *rxBuf, uint32_t size, cy_stc_scb_uart_context_t *context) +{ + cy_en_scb_uart_status_t retStatus = CY_SCB_UART_RECEIVE_BUSY; + +#if !defined(NDEBUG) + /* Check that the initialization key was set before using the context */ + CY_ASSERT(NULL != context); + CY_ASSERT(CY_SCB_UART_INIT_KEY == context->initKey); +#endif /* !(NDEBUG) */ + + /* Check if there are no active transfer requests */ + if (0UL == (context->rxStatus & CY_SCB_UART_RECEIVE_ACTIVE)) + { + uint8_t *tmpBuf = (uint8_t *) rxBuf; + uint32_t numToCopy = 0UL; + + /* Disable the RX interrupt source to stop the ring buffer update */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + if (NULL != context->rxRingBuf) + { + /* Get the items available in the ring buffer */ + numToCopy = Cy_SCB_UART_GetNumInRingBuffer(base, context); + + if (numToCopy > 0UL) + { + uint32_t idx; + uint32_t locTail = context->rxRingBufTail; + bool byteMode = Cy_SCB_IsRxDataWidthByte(base); + + /* Adjust the number of items to be read */ + if (numToCopy > size) + { + numToCopy = size; + } + + /* Copy the data elements from the ring buffer */ + for (idx = 0UL; idx < numToCopy; ++idx) + { + ++locTail; + + if (locTail == context->rxRingBufSize) + { + locTail = 0UL; + } + + if (byteMode) + { + uint8_t *buf = (uint8_t *) rxBuf; + buf[idx] = ((uint8_t *) context->rxRingBuf)[locTail]; + } + else + { + uint16_t *buf = (uint16_t *) rxBuf; + buf[idx] = ((uint16_t *) context->rxRingBuf)[locTail]; + } + } + + /* Update the ring buffer tail after data has been copied */ + context->rxRingBufTail = locTail; + + /* Update with the copied bytes */ + size -= numToCopy; + context->rxBufIdx = numToCopy; + + /* Check if all requested data has been read from the ring buffer */ + if (0UL == size) + { + /* Enable the RX-error interrupt sources to update the error status */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_UART_RECEIVE_ERR); + + /* Call a completion callback if there was no abort receive called + * in the interrupt. The abort clears the number of the received bytes. + */ + if (context->rxBufIdx > 0UL) + { + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_UART_RECEIVE_DONE_EVENT); + } + } + + /* Continue receiving data in the ring buffer */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL); + } + else + { + tmpBuf = &tmpBuf[(byteMode) ? (numToCopy) : (2UL * numToCopy)]; + } + } + } + + /* Set up a direct RX FIFO receive */ + if (size > 0UL) + { + uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL; + + /* Set up context */ + context->rxStatus = CY_SCB_UART_RECEIVE_ACTIVE; + + context->rxBuf = (void *) tmpBuf; + context->rxBufSize = size; + context->rxBufIdx = numToCopy; + + /* Set the RX FIFO level to the trigger interrupt */ + Cy_SCB_SetRxFifoLevel(base, (size > halfFifoSize) ? (halfFifoSize - 1UL) : (size - 1UL)); + + /* Enable the RX interrupt sources to continue data reading */ + Cy_SCB_SetRxInterruptMask(base, CY_SCB_UART_RX_INTR); + } + + retStatus = CY_SCB_UART_SUCCESS; + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_AbortReceive +****************************************************************************//** +* +* Abort the current receive operation by clearing the receive status. +* * If the ring buffer is disabled, the receive interrupt sources are disabled. +* * If the ring buffer is enabled, the receive interrupt source is configured +* to get data from the receive FIFO and put it into the ring buffer. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* * The RX FIFO and ring buffer are not cleared after abort of receive +* operation. +* * If after the abort of the receive operation the transmitter continues +* sending data, it gets into the RX FIFO. To drop this data, the RX FIFO +* and ring buffer (if enabled) have to be cleared when the transmitter +* stops sending data. Otherwise, received data will be kept and copied +* to the buffer when \ref Cy_SCB_UART_Receive is called. +* +*******************************************************************************/ +void Cy_SCB_UART_AbortReceive(CySCB_Type *base, cy_stc_scb_uart_context_t *context) +{ + if (NULL == context->rxRingBuf) + { + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } + + context->rxBufSize = 0UL; + context->rxBufIdx = 0UL; + + context->rxStatus = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetNumReceived +****************************************************************************//** +* +* Returns the number of data elements received since the last call to \ref +* Cy_SCB_UART_Receive. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* The number of data elements received. +* +*******************************************************************************/ +uint32_t Cy_SCB_UART_GetNumReceived(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->rxBufIdx); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetReceiveStatus +****************************************************************************//** +* +* Returns the status of the receive operation. +* This status is a bit mask and the value returned may have multiple bits set. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref group_scb_uart_macro_receive_status. +* +* \note +* The status is only cleared by calling \ref Cy_SCB_UART_Receive again. +* +*******************************************************************************/ +uint32_t Cy_SCB_UART_GetReceiveStatus(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->rxStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_Transmit +****************************************************************************//** +* +* This function starts a UART transmit operation. +* It configures the transmit interrupt sources and returns. +* The \ref Cy_SCB_UART_Interrupt manages the further data transfer. +* +* When the transmit operation is completed (requested number of data elements +* sent on the bus), the \ref CY_SCB_UART_TRANSMIT_ACTIVE status is cleared and +* the \ref CY_SCB_UART_TRANSMIT_DONE_EVENT event is generated. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param txBuf +* Pointer to user data to place in transmit buffer. +* The item size is defined by the data type which depends on the configured +* data width. +* +* \param size +* The number of data elements to transmit. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref cy_en_scb_uart_status_t +* +* \note +* * The buffer must not be modified and stay allocated until its content is +* copied into the TX FIFO. +* * This function overrides the TX FIFO interrupt sources and changes the +* TX FIFO level. +* +*******************************************************************************/ +cy_en_scb_uart_status_t Cy_SCB_UART_Transmit(CySCB_Type *base, void *txBuf, uint32_t size, cy_stc_scb_uart_context_t *context) +{ + cy_en_scb_uart_status_t retStatus = CY_SCB_UART_TRANSMIT_BUSY; + +#if !defined(NDEBUG) + /* Check that the initialization key was set before using the context */ + CY_ASSERT(NULL != context); + CY_ASSERT(CY_SCB_UART_INIT_KEY == context->initKey); +#endif /* !(NDEBUG) */ + + /* Check if there are no active transfer requests */ + if (0UL == (CY_SCB_UART_TRANSMIT_ACTIVE & context->txStatus)) + { + /* Set up context */ + context->txStatus = CY_SCB_UART_TRANSMIT_ACTIVE; + + context->txBuf = txBuf; + context->txBufSize = size; + + /* Set the level in TX FIFO to start a transfer */ + Cy_SCB_SetTxFifoLevel(base, (Cy_SCB_GetFifoSize(base) / 2UL)); + + /* Enable the interrupt sources */ + if (CY_SCB_UART_SMARTCARD == _FLD2VAL(SCB_UART_CTRL_MODE, base->UART_CTRL)) + { + /* Transfer data into TX FIFO and track SmartCard-specific errors */ + Cy_SCB_SetTxInterruptMask(base, CY_SCB_UART_TX_INTR); + } + else + { + /* Transfer data into TX FIFO */ + Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); + } + + retStatus = CY_SCB_UART_SUCCESS; + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_AbortTransmit +****************************************************************************//** +* +* Aborts the current transmit operation. +* It disables the transmit interrupt sources and clears the transmit FIFO +* and status. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \sideeffect +* The transmit FIFO clear operation also clears the shift register, so that +* the shifter could be cleared in the middle of a data element transfer, +* corrupting it. The data element corruption means that all bits which has +* not been transmitted are transmitted as "ones" on the bus. +* +*******************************************************************************/ +void Cy_SCB_UART_AbortTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context) +{ + Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + Cy_SCB_UART_ClearTxFifo(base); + + context->txBufSize = 0UL; + context->txLeftToTransmit = 0UL; + + context->txStatus = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetNumLeftToTransmit +****************************************************************************//** +* +* Returns the number of data elements left to transmit since the last call to +* \ref Cy_SCB_UART_Transmit. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* The number of data elements left to transmit. +* +*******************************************************************************/ +uint32_t Cy_SCB_UART_GetNumLeftToTransmit(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->txLeftToTransmit); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetTransmitStatus +****************************************************************************//** +* +* Returns the status of the transmit operation. +* This status is a bit mask and the value returned may have multiple bits set. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \return +* \ref group_scb_uart_macro_transmit_status. +* +* \note +* The status is only cleared by calling \ref Cy_SCB_UART_Transmit or +* \ref Cy_SCB_UART_AbortTransmit. +* +*******************************************************************************/ +uint32_t Cy_SCB_UART_GetTransmitStatus(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + return (context->txStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_Interrupt +****************************************************************************//** +* +* This is the interrupt function for the SCB configured in the UART mode. +* This function must be called inside a user-defined interrupt service +* routine to make \ref Cy_SCB_UART_Transmit and \ref Cy_SCB_UART_Receive +* work. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +void Cy_SCB_UART_Interrupt(CySCB_Type *base, cy_stc_scb_uart_context_t *context) +{ + if (0UL != (CY_SCB_RX_INTR & Cy_SCB_GetInterruptCause(base))) + { + /* Get RX error events: a frame error, parity error, and overflow */ + uint32_t locRxErr = (CY_SCB_UART_RECEIVE_ERR & Cy_SCB_GetRxInterruptStatusMasked(base)); + + /* Handle the error conditions */ + if (0UL != locRxErr) + { + context->rxStatus |= locRxErr; + + Cy_SCB_ClearRxInterrupt(base, locRxErr); + + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_UART_RECEIVE_ERR_EVENT); + } + } + + /* Break the detect */ + if (0UL != (CY_SCB_RX_INTR_UART_BREAK_DETECT & Cy_SCB_GetRxInterruptStatusMasked(base))) + { + context->rxStatus |= CY_SCB_UART_RECEIVE_BREAK_DETECT; + + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_UART_BREAK_DETECT); + } + + /* Copy the received data */ + if (0UL != (CY_SCB_RX_INTR_LEVEL & Cy_SCB_GetRxInterruptStatusMasked(base))) + { + if (context->rxBufSize > 0UL) + { + HandleDataReceive(base, context); + } + else + { + if (NULL != context->rxRingBuf) + { + HandleRingBuffer(base, context); + } + } + + Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL); + } + } + + if (0UL != (CY_SCB_TX_INTR & Cy_SCB_GetInterruptCause(base))) + { + uint32_t locTxErr = (CY_SCB_UART_TRANSMIT_ERR & Cy_SCB_GetTxInterruptStatusMasked(base)); + + /* Handle the TX error conditions */ + if (0UL != locTxErr) + { + context->txStatus |= locTxErr; + Cy_SCB_ClearTxInterrupt(base, locTxErr); + + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_UART_TRANSMIT_ERR_EVENT); + } + } + + /* Load data to transmit */ + if (0UL != (CY_SCB_TX_INTR_LEVEL & Cy_SCB_GetTxInterruptStatusMasked(base))) + { + HandleDataTransmit(base, context); + + Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL); + } + + /* Handle the TX complete */ + if (0UL != (CY_SCB_TX_INTR_UART_DONE & Cy_SCB_GetTxInterruptStatusMasked(base))) + { + /* Disable all TX interrupt sources */ + Cy_SCB_SetTxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + context->txStatus &= (uint32_t) ~CY_SCB_UART_TRANSMIT_ACTIVE; + context->txLeftToTransmit = 0UL; + + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_UART_TRANSMIT_DONE_EVENT); + } + } + } +} + + + +/******************************************************************************* +* Function Name: HandleDataReceive +****************************************************************************//** +* +* Reads data from the receive FIFO into the buffer provided by +* \ref Cy_SCB_UART_Receive. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void HandleDataReceive(CySCB_Type *base, cy_stc_scb_uart_context_t *context) +{ + uint32_t numCopied; + uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL; + + /* Get data from RX FIFO */ + numCopied = Cy_SCB_UART_GetArray(base, context->rxBuf, context->rxBufSize); + + /* Move the buffer */ + context->rxBufIdx += numCopied; + context->rxBufSize -= numCopied; + + if (0UL == context->rxBufSize) + { + if (NULL != context->rxRingBuf) + { + /* Adjust the level to proceed with the ring buffer */ + Cy_SCB_SetRxFifoLevel(base, (context->rxRingBufSize >= halfFifoSize) ? + (halfFifoSize - 1UL) : (context->rxRingBufSize - 1UL)); + + Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL); + } + else + { + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + } + + /* Update the status */ + context->rxStatus &= (uint32_t) ~CY_SCB_UART_RECEIVE_ACTIVE; + + /* Notify that receive is done in a callback */ + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_UART_RECEIVE_DONE_EVENT); + } + } + else + { + uint8_t *buf = (uint8_t *) context->rxBuf; + + buf = &buf[(Cy_SCB_IsRxDataWidthByte(base) ? (numCopied) : (2UL * numCopied))]; + context->rxBuf = (void *) buf; + + if (context->rxBufSize < halfFifoSize) + { + /* Set the RX FIFO level to trigger an interrupt */ + Cy_SCB_SetRxFifoLevel(base, (context->rxBufSize - 1UL)); + } + } +} + + +/******************************************************************************* +* Function Name: HandleRingBuffer +****************************************************************************//** +* +* Reads data from the receive FIFO into the receive ring buffer. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void HandleRingBuffer(CySCB_Type *base, cy_stc_scb_uart_context_t *context) +{ + uint32_t halfFifoSize = Cy_SCB_GetFifoSize(base) / 2UL; + uint32_t numToCopy = Cy_SCB_GetNumInRxFifo(base); + uint32_t locHead = context->rxRingBufHead; + uint32_t rxData; + + /* Get data into the ring buffer */ + while (numToCopy > 0UL) + { + ++locHead; + + if (locHead == context->rxRingBufSize) + { + locHead = 0UL; + } + + if (locHead == context->rxRingBufTail) + { + /* The ring buffer is full, trigger a callback */ + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_UART_RB_FULL_EVENT); + } + + /* The ring buffer is still full. Disable the RX interrupt not to put data into the ring buffer. + * The data is stored in the RX FIFO until it overflows. Revert the head index. + */ + if (locHead == context->rxRingBufTail) + { + Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC); + + locHead = (locHead > 0UL) ? (locHead - 1UL) : (context->rxRingBufSize - 1UL); + break; + } + } + + /* Get data from RX FIFO. */ + rxData = Cy_SCB_ReadRxFifo(base); + + /* Put a data item in the ring buffer */ + if (Cy_SCB_IsRxDataWidthByte(base)) + { + ((uint8_t *) context->rxRingBuf)[locHead] = (uint8_t) rxData; + } + else + { + ((uint16_t *) context->rxRingBuf)[locHead] = (uint16_t) rxData; + } + + --numToCopy; + } + + /* Update the head index */ + context->rxRingBufHead = locHead; + + /* Get free entries in the ring buffer */ + numToCopy = context->rxRingBufSize - Cy_SCB_UART_GetNumInRingBuffer(base, context); + + if (numToCopy < halfFifoSize) + { + /* Adjust the level to copy to the ring buffer */ + uint32_t level = (numToCopy > 0UL) ? (numToCopy - 1UL) : 0UL; + Cy_SCB_SetRxFifoLevel(base, level); + } +} + + +/******************************************************************************* +* Function Name: HandleDataTransmit +****************************************************************************//** +* +* Loads the transmit FIFO with data provided by \ref Cy_SCB_UART_Transmit. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +*******************************************************************************/ +static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context) +{ + uint32_t numToCopy; + uint32_t fifoSize = Cy_SCB_GetFifoSize(base); + bool byteMode = Cy_SCB_IsTxDataWidthByte(base); + + if (context->txBufSize > 1UL) + { + uint8_t *buf = (uint8_t *) context->txBuf; + + /* Get the number of items left for transmission */ + context->txLeftToTransmit = context->txBufSize; + + /* Put data into TX FIFO */ + numToCopy = Cy_SCB_UART_PutArray(base, context->txBuf, (context->txBufSize - 1UL)); + + /* Move the buffer */ + context->txBufSize -= numToCopy; + + buf = &buf[(byteMode) ? (numToCopy) : (2UL * numToCopy)]; + context->txBuf = (void *) buf; + } + + /* Put the last data item into TX FIFO */ + if ((fifoSize != Cy_SCB_GetNumInTxFifo(base)) && (1UL == context->txBufSize)) + { + uint32_t txData; + uint32_t intrStatus; + + context->txBufSize = 0UL; + + /* Get the last item from the buffer */ + txData = (uint32_t) ((byteMode) ? ((uint8_t *) context->txBuf)[0UL] : + ((uint16_t *) context->txBuf)[0UL]); + + /* Put the last data element and make sure that "TX done" will happen for it */ + intrStatus = Cy_SysLib_EnterCriticalSection(); + + Cy_SCB_WriteTxFifo(base, txData); + Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_UART_DONE); + + Cy_SysLib_ExitCriticalSection(intrStatus); + + /* Disable the level interrupt source and enable "transfer done" */ + Cy_SCB_SetTxInterruptMask(base, (CY_SCB_TX_INTR_UART_DONE | + (Cy_SCB_GetTxInterruptMask(base) & (uint32_t) ~CY_SCB_TX_INTR_LEVEL))); + + /* Data is copied into TX FIFO */ + context->txStatus |= CY_SCB_UART_TRANSMIT_IN_FIFO; + + if (NULL != context->cbEvents) + { + context->cbEvents(CY_SCB_UART_TRANSMIT_IN_FIFO_EVENT); + } + } +} + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_uart.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_uart.h new file mode 100644 index 0000000000..783b2570b0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/scb/cy_scb_uart.h @@ -0,0 +1,1282 @@ +/***************************************************************************//** +* \file cy_scb_uart.h +* \version 1.0 +* +* Provides UART API declarations of the SCB driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \addtogroup group_scb_uart +* \{ +* Driver API for UART +* +* UART - Universal Synchronous/Asynchronous Receiver/Transmitter, +* commonly referred to as RS-232. +* +* Three different UART-like serial interface protocols are supported: +* * UART - the standard mode with an optional UART Hardware flow control. +* * SmartCard - the transfer is similar to the UART transfer, +* but a NACK (negative acknowledgment) may be sent from the +* receiver to the transmitter. Both transmitter and receiver drive the same +* line, although never at the same time. +* * IrDA - the Infra-red Data Association protocol adds a modulation +* scheme to the UART signaling. At the transmitter, bits are modulated. +* At the receiver, bits are demodulated. The modulation scheme uses the +* Return-to-Zero-Inverted (RZI) format. Bit value "0" is signaled by a +* short "1" pulse on the line and bit value "1" is signaled by holding +* the line to "0". +* +* \section group_scb_uart_configuration Configuration Considerations +* +* To set up a UART, provide configuration parameters in the +* \ref cy_stc_scb_uart_config_t structure. For example: provide uartMode, +* overSample, dataWidth, enableMsbFirst, parity, and stopBits. The other +* parameters are optional for operation. +* To initialize the driver, call the \ref Cy_SCB_UART_Init function providing +* filled \ref cy_stc_scb_uart_config_t structure and allocated +* \ref cy_stc_scb_uart_context_t. +* The clock source connected to SCB UART must be configured to provide +* the sufficient frequency and set the appropriate oversampling to reach the +* desired data. +* Call \ref Cy_SCB_UART_Enable to start the UART operation after configuration +* is completed. +* +* The UART API is divided into two categories: low-level and high-level. +* Do not mix high-level and low-level API because low-level APIs can adversely +* affect the operation of higher level API. +* +* The low-level API's functions allow interacting directly with the hardware +* and do not use interrupts. These functions do not require context for +* operation, thus NULL can be passed in \ref Cy_SCB_UART_Init and +* \ref Cy_SCB_UART_Disable instead of a pointer to the context structure. +* +* * To write data into the TX FIFO, use one of the provided functions: +* \ref Cy_SCB_UART_Put, \ref Cy_SCB_UART_PutArray, +* \ref Cy_SCB_UART_PutArrayBlocking or \ref Cy_SCB_UART_PutString. +* Note that putting data into the TX FIFO starts data transfer. +* +* * To read data from the RX FIFO, use one of the provided functions: +* \ref Cy_SCB_UART_Get, \ref Cy_SCB_UART_GetArray or +* \ref Cy_SCB_UART_GetArrayBlocking. +* +* * The statuses can be polled by using: \ref Cy_SCB_UART_GetRxFifoStatus and +* \ref Cy_SCB_UART_GetTxFifoStatus. +* The statuses are W1C (Write 1 to Clear) and after status is set it must +* be cleared. Note that there are statuses that are evaluated as level. These +* statuses remain set when an event is true. Therefore after clear operation +* the status is cleared but then restored (if event is true). +* For example: the TX FIFO empty can be cleared when the TX FIFO is +* NOT empty. You have to put at least (two data elements, one goes to shifter +* and next in FIFO) before clearing this status. +* +* The High Level API uses an interrupt to execute transfer. Call +* \ref Cy_SCB_UART_Transmit to start transmission. Call \ref Cy_SCB_UART_Receive +* to start receive operation. After the operation is started the +* \ref Cy_SCB_UART_Interrupt handles the data transfer until its +* completion. Therefore \ref Cy_SCB_UART_Interrupt must be called inside the +* user interrupt handler to make the high level API work. To monitor status +* of transmit operation, use \ref Cy_SCB_UART_GetTransmitStatus and +* \ref Cy_SCB_UART_GetReceiveStatus to monitor receive status appropriately. +* Alternatively use \ref Cy_SCB_UART_RegisterCallback to register callback +* function to be notified about \ref group_scb_uart_macro_callback_events. +* +* There is also capability to insert a receive ring buffer that operates between +* the RX FIFO and the user buffer. The received data is copied into the ring +* buffer from the RX FIFO. This process runs in the background after the ring +* buffer operation is started by \ref Cy_SCB_UART_StartRingBuffer. +* When \ref Cy_SCB_UART_Receive is called, it first reads data from the ring +* buffer and then sets up an interrupt to receive more data if the required +* amount has not been read yet. +* +* \section group_scb_uart_more_information More Information +* +* For more information on the SCB peripheral, refer to the technical reference +* manual (TRM). +* +* \section group_scb_uart_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and +* a different pointer to object type.The pointer to the buffer memory is void to allow handling different +* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). +*
14.2RAll non-null statements shall either: a) have at least one side-effect +* however executed, or b) cause control flow to change.The unused function parameters are cast to void. This statement +* has no side-effect and is used to suppress a compiler warning.
20.3RThe validity of values passed to library functions shall be checked. +* The CY_ASSERT() macro is used for verification of pointer to context +* parameter against NULL. This macro halts code execution if +* verification fails what ensures that NULL pointer is not dereference. +*
+* +* \section group_scb_uart_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_scb_uart_macro Macro +* \defgroup group_scb_uart_functions Functions +* \defgroup group_scb_uart_data_structures Data Structures +* \defgroup group_scb_uart_enums Enumerated Types +*/ + +#if !defined(CY_SCB_UART_H) +#define CY_SCB_UART_H + +#include "cy_scb_common.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Enumerated Types +***************************************/ + +/** +* \addtogroup group_scb_uart_enums +* \{ +*/ + +/** UART status codes */ +typedef enum +{ + /** Operation completed successfully */ + CY_SCB_UART_SUCCESS = 0x00U, + + /** One or more of input parameters are invalid */ + CY_SCB_UART_BAD_PARAM = CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_UART_ID | 1UL, + + /** + * The UART is busy processing a transmit operation. Call this function + * again once that operation is completed or aborted. + */ + CY_SCB_UART_RECEIVE_BUSY, + + /** + * The UART is busy processing a receive operation. Call this function + * again once that operation is completed or aborted. + */ + CY_SCB_UART_TRANSMIT_BUSY +} cy_en_scb_uart_status_t; +/** \} group_scb_uart_enums */ + + +/*************************************** +* Type Definitions +***************************************/ + +/** +* \addtogroup group_scb_uart_data_structures +* \{ +*/ + +/** +* Provides the typedef for the callback function called in the +* \ref Cy_SCB_UART_Interrupt to notify the user about occurrences of +* \ref group_scb_uart_macro_callback_events. +*/ +typedef void (* scb_uart_handle_events_t)(uint32_t event); + +/** UART configuration structure */ +typedef struct stc_scb_uart_config +{ + /** Specifies the UART's mode of operation + * (See \ref group_scb_uart_macro_modes for the set of constants) + */ + uint32_t uartMode; + + /** + * Oversample factor for UART. + * * The UART baud rate is the SCB Clock frequency / oversample + * (valid range is 8-16). + * * For IrDA, the oversample is always 16, unless + * \ref irdaEnableLowPowerReceiver is enabled. Then the oversample is + * reduced to the \ref group_scb_uart_macro_irda_lp_ovs set. + */ + uint32_t oversample; + + /** The width of UART data (valid range is 5 to 9) */ + uint32_t dataWidth; + + /** + * Enables the hardware to shift out data element MSB first, otherwise, + * LSB first + */ + bool enableMsbFirst; + + /** + * Specifies the number of stop bits in the UART transaction, in half-bit + * increments (See \ref group_scb_uart_macro_stop_bits for the set of + * constants.) + */ + uint32_t stopBits; + + /** Configures the UART parity + * (See \ref group_scb_uart_macro_parity for the set of constants.) + */ + uint32_t parity; + + /** + * Enables a digital 3-tap median filter to be applied to the input + * of the RX FIFO to filter glitches on the line + */ + bool enableInputFilter; + + /** + * Enables the hardware to drop data in the RX FIFO when a parity error is + * detected + */ + bool dropOnParityError; + + /** + * Enables the hardware to drop data in the RX FIFO when a frame error is + * detected + */ + bool dropOnFrameError; + + /** + * Enables the UART operation in Multi-Processor mode which requires + * dataWidth to be 9 bits (the 9th bit is used to indicate address byte) + */ + bool enableMutliProcessorMode; + + /** + * If Multi Processor mode is enabled, this is the address of the RX + * FIFO. If the address matches, data is accepted into the FIFO. If + * it does not match, the data is ignored. + */ + uint32_t receiverAddress; + + /** This is the address mask for the Multi Processor address. 1 indicates + * that the incoming address must match the corresponding bit in the slave + * address. A 0 in the mask indicates that the incoming address does + * not need to match. + */ + uint32_t receiverAddressMask; + + /** + * Enables the hardware to accept the matching address in the RX FIFO. + * This is useful when the device supports more than one address. + */ + bool acceptAddrInFifo; + + /** Inverts the IrDA RX input */ + bool irdaInvertRx; + + /** + * Enables the low-power receive for IrDA mode. + * Note that the transmission must be disabled if this mode is enabled. + */ + bool irdaEnableLowPowerReceiver; + + /** + * Enables retransmission of the frame placed in the TX FIFO when + * NACK is received in SmartCard mode + */ + bool smartCardRetryOnNack; + + /** + * Enables the usage of the CTS input signal for the transmitter. The + * transmitter waits for CTS to be active before sending data + */ + bool enableCts; + + /** Sets the CTS Polarity + * (See \ref group_scb_uart_macro_polarity for the set of constants.) + */ + uint32_t ctsPolarity; + + /** + * When the RX FIFO has fewer entries than rtsRxFifoLevel, the + * RTS signal is active (note to disable RTS, set this field to zero) + */ + uint32_t rtsRxFifoLevel; + + /** Sets the RTS Polarity + * (See \ref group_scb_uart_macro_polarity for the set of constants.) + */ + uint32_t rtsPolarity; + + /** Specifies the number of bits to detect a break condition */ + uint32_t breakWidth; + + /** + * When there are more entries in the RX FIFO than this level + * the RX trigger output goes high. This output can be connected + * to a DMA channel through a trigger mux. + * Also, it controls the \ref CY_SCB_UART_RX_TRIGGER interrupt source. + */ + uint32_t rxFifoTriggerLevel; + + /** + * The bits set in this mask allow the event to cause an interrupt + * (See \ref group_scb_uart_macro_rx_fifo_status for the set of constants.) + */ + uint32_t rxFifoIntEnableMask; + + /** + * When there are fewer entries in the TX FIFO then this level + * the TX trigger output goes high. This output can be connected + * to a DMA channel through a trigger mux. + * Also it controls \ref CY_SCB_UART_TX_TRIGGER interrupt source. + */ + uint32_t txFifoTriggerLevel; + + /** + * Bits set in this mask allows the event to cause an interrupt + * (See \ref group_scb_uart_macro_tx_fifo_status for the set of constants) + */ + uint32_t txFifoIntEnableMask; + + +} cy_stc_scb_uart_config_t; + +/** UART internal context structure */ +typedef struct cy_stc_scb_uart_context +{ + uint32_t volatile txStatus; /**< Transmit status */ + uint32_t volatile rxStatus; /**< Receive status */ + + void *rxRingBuf; /**< Pointer to ring buffer */ + uint32_t volatile rxRingBufSize; /**< Ring buffer size */ + uint32_t volatile rxRingBufHead; /**< Ring buffer head index */ + uint32_t volatile rxRingBufTail; /**< Ring buffer tail index */ + + void *rxBuf; /**< Pointer to receive buffer */ + uint32_t volatile rxBufSize; /**< Receive buffer size */ + uint32_t volatile rxBufIdx; /**< Index within receive buffer */ + + void *txBuf; /**< Pointer to transmit buffer */ + uint32_t volatile txBufSize; /**< Transmit buffer size */ + uint32_t volatile txLeftToTransmit; /**< Number of data elements left to be transmitted */ + + /** + * The pointer to an event callback which is called when a UART event occurs + */ + scb_uart_handle_events_t cbEvents; + +#if !defined(NDEBUG) + uint32_t initKey; /**< Tracks context initialization */ +#endif /* !(NDEBUG) */ +} cy_stc_scb_uart_context_t; +/** \} group_scb_uart_data_structures */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_scb_uart_functions +* \{ +*/ + +/* Basic functions */ +cy_en_scb_uart_status_t Cy_SCB_UART_Init(CySCB_Type *base, cy_stc_scb_uart_config_t const *config, + cy_stc_scb_uart_context_t *context); +void Cy_SCB_UART_DeInit (CySCB_Type *base); +__STATIC_INLINE void Cy_SCB_UART_Enable(CySCB_Type *base); +void Cy_SCB_UART_Disable(CySCB_Type *base, cy_stc_scb_uart_context_t *context); + +/* Configuration functions */ +__STATIC_INLINE void Cy_SCB_UART_EnableCts (CySCB_Type *base); +__STATIC_INLINE void Cy_SCB_UART_DisableCts (CySCB_Type *base); +__STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t rxFifoLevel); +__STATIC_INLINE uint32_t Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const *base); + +__STATIC_INLINE void Cy_SCB_UART_EnableSkipStart (CySCB_Type *base); +__STATIC_INLINE void Cy_SCB_UART_DisableSkipStart(CySCB_Type *base); + +/* Low-level: RX direction functions */ +__STATIC_INLINE uint32_t Cy_SCB_UART_Get (CySCB_Type const *base); +__STATIC_INLINE uint32_t Cy_SCB_UART_GetArray (CySCB_Type const *base, void *rxBuf, uint32_t size); +__STATIC_INLINE void Cy_SCB_UART_GetArrayBlocking(CySCB_Type const *base, void *rxBuf, uint32_t size); + +__STATIC_INLINE uint32_t Cy_SCB_UART_GetRxFifoStatus (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_UART_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask); +__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInRxFifo (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_UART_ClearRxFifo (CySCB_Type *base); + +/* Low-level: TX direction functions */ +__STATIC_INLINE uint32_t Cy_SCB_UART_Put (CySCB_Type *base, uint32_t data); +__STATIC_INLINE uint32_t Cy_SCB_UART_PutArray (CySCB_Type *base, void *txBuf, uint32_t size); +__STATIC_INLINE void Cy_SCB_UART_PutArrayBlocking(CySCB_Type *base, void *txBuf, uint32_t size); +__STATIC_INLINE void Cy_SCB_UART_PutString (CySCB_Type *base, char_t const string[]); + +__STATIC_INLINE uint32_t Cy_SCB_UART_GetTxFifoStatus (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_UART_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask); +__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInTxFifo (CySCB_Type const *base); +__STATIC_INLINE bool Cy_SCB_UART_IsTxComplete (CySCB_Type const *base); +__STATIC_INLINE void Cy_SCB_UART_ClearTxFifo (CySCB_Type *base); + +/* High-level: Callback */ +__STATIC_INLINE void Cy_SCB_UART_RegisterCallback(CySCB_Type const *base, scb_uart_handle_events_t callback, + cy_stc_scb_uart_context_t *context); + +/* High-level: Ring buffer functions */ +void Cy_SCB_UART_StartRingBuffer (CySCB_Type *base, void* ringBuffer, uint32_t size, + cy_stc_scb_uart_context_t *context); +void Cy_SCB_UART_StopRingBuffer (CySCB_Type *base, cy_stc_scb_uart_context_t *context); +uint32_t Cy_SCB_UART_GetNumInRingBuffer(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context); +void Cy_SCB_UART_ClearRingBuffer (CySCB_Type const *base, cy_stc_scb_uart_context_t *context); + +/* High-level: RX direction functions */ +cy_en_scb_uart_status_t Cy_SCB_UART_Receive(CySCB_Type *base, void *rxBuf, uint32_t size, cy_stc_scb_uart_context_t *context); +void Cy_SCB_UART_AbortReceive (CySCB_Type *base, cy_stc_scb_uart_context_t *context); +uint32_t Cy_SCB_UART_GetNumReceived (CySCB_Type const *base, cy_stc_scb_uart_context_t const *context); +uint32_t Cy_SCB_UART_GetReceiveStatus(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context); + +/* High-level: TX direction functions */ +cy_en_scb_uart_status_t Cy_SCB_UART_Transmit(CySCB_Type *base, void *txBuf, uint32_t size, cy_stc_scb_uart_context_t *context); +void Cy_SCB_UART_AbortTransmit (CySCB_Type *base, cy_stc_scb_uart_context_t *context); +uint32_t Cy_SCB_UART_GetNumLeftToTransmit(CySCB_Type const *base, cy_stc_scb_uart_context_t const *context); +uint32_t Cy_SCB_UART_GetTransmitStatus (CySCB_Type const *base, cy_stc_scb_uart_context_t const *context); + +/* High-level: Interrupt handler */ +void Cy_SCB_UART_Interrupt(CySCB_Type *base, cy_stc_scb_uart_context_t *context); +/** \} group_scb_uart_functions */ + + +/*************************************** +* API Constants +***************************************/ + +/** +* \addtogroup group_scb_uart_macro +* \{ +*/ + +/** +* \defgroup group_scb_uart_macro_modes UART Mode Defines +* \{ +*/ +/** Configures the SCB for Standard UART operation */ +#define CY_SCB_UART_STANDARD (0UL) + +/** Configures the SCB for SmartCard operation */ +#define CY_SCB_UART_SMARTCARD (1UL) + +/** Configures the SCB for IrDA operation */ +#define CY_SCB_UART_IRDA (2UL) +/** \} group_scb_uart_macro_modes */ + +/** +* \defgroup group_scb_uart_macro_stop_bits UART Stop Bit Defines +* \{ +*/ +#define CY_SCB_UART_STOP_BITS_1 (2UL) /**< UART looks for 1 Stop Bit */ +#define CY_SCB_UART_STOP_BITS_1_5 (3UL) /**< UART looks for 1.5 Stop Bits */ +#define CY_SCB_UART_STOP_BITS_2 (4UL) /**< UART looks for 2 Stop Bits */ +#define CY_SCB_UART_STOP_BITS_2_5 (5UL) /**< UART looks for 2.5 Stop Bits */ +#define CY_SCB_UART_STOP_BITS_3 (6UL) /**< UART looks for 3 Stop Bits */ +#define CY_SCB_UART_STOP_BITS_3_5 (7UL) /**< UART looks for 3.5 Stop Bits */ +#define CY_SCB_UART_STOP_BITS_4 (8UL) /**< UART looks for 4 Stop Bits */ +/** \} group_scb_uart_macro_stop_bits */ + +/** +* \defgroup group_scb_uart_macro_parity UART Parity Defines +* \{ +*/ +#define CY_SCB_UART_PARITY_NONE (0UL) /**< UART has no parity check */ +#define CY_SCB_UART_PARITY_EVEN (2UL) /**< UART has even parity check */ +#define CY_SCB_UART_PARITY_ODD (3UL) /**< UART has odd parity check */ +/** \} group_scb_uart_macro_parity */ + +/** +* \defgroup group_scb_uart_macro_irda_lp_ovs UART IRDA Low Power Oversample factors +* \{ +*/ +#define CY_SCB_UART_IRDA_LP_OVS16 (1UL) /**< IrDA in low-power mode oversampled by 16 */ +#define CY_SCB_UART_IRDA_LP_OVS32 (2UL) /**< IrDA in low-power mode oversampled by 32 */ +#define CY_SCB_UART_IRDA_LP_OVS48 (3UL) /**< IrDA in low-power mode oversampled by 48 */ +#define CY_SCB_UART_IRDA_LP_OVS96 (4UL) /**< IrDA in low-power mode oversampled by 96 */ +#define CY_SCB_UART_IRDA_LP_OVS192 (5UL) /**< IrDA in low-power mode oversampled by 192 */ +#define CY_SCB_UART_IRDA_LP_OVS768 (6UL) /**< IrDA in low-power mode oversampled by 768 */ +#define CY_SCB_UART_IRDA_LP_OVS1536 (7UL) /**< IrDA in low-power mode oversampled by 1536 */ +/** \} group_scb_uart_macro_irda_lp_ovs */ + +/** +* \defgroup group_scb_uart_macro_polarity UART Polarity Defines +* \{ +*/ +#define CY_SCB_UART_ACTIVE_LOW (0UL) /**< Signal is active low */ +#define CY_SCB_UART_ACTIVE_HIGH (1UL) /**< Signal is active high */ +/** \} group_scb_uart_macro_polarity */ + +/** +* \defgroup group_scb_uart_macro_rx_fifo_status UART Receive FIFO status. +* \{ +*/ +/** The number of entries in the RX FIFO is more than the RX FIFO trigger level +* value +*/ +#define CY_SCB_UART_RX_TRIGGER (SCB_INTR_RX_TRIGGER_Msk) + +/** The RX FIFO is not empty, there is data to read */ +#define CY_SCB_UART_RX_NOT_EMPTY (SCB_INTR_RX_NOT_EMPTY_Msk) + +/** +* The RX FIFO is full, there is no more space for additional data, +* any additional data will be dropped +*/ +#define CY_SCB_UART_RX_FULL (SCB_INTR_RX_FULL_Msk) + +/** +* The RX FIFO was full and there was an attempt to write to it. +* That additional data was dropped. +*/ +#define CY_SCB_UART_RX_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk) + +/** An attempt to read from an empty RX FIFO */ +#define CY_SCB_UART_RX_UNDERFLOW (SCB_INTR_RX_UNDERFLOW_Msk) + +/** The RX FIFO detected a frame error, either a stop or stop-bit error */ +#define CY_SCB_UART_RX_ERR_FRAME (SCB_INTR_RX_FRAME_ERROR_Msk) + +/** The RX FIFO detected a parity error */ +#define CY_SCB_UART_RX_ERR_PARITY (SCB_INTR_RX_PARITY_ERROR_Msk) + +/** The RX FIFO detected a break transmission from the transmitter */ +#define CY_SCB_UART_RX_BREAK_DETECT (SCB_INTR_RX_BREAK_DETECT_Msk) +/** \} group_scb_uart_macro_rx_fifo_status */ + +/** +* \defgroup group_scb_uart_macro_tx_fifo_status UART TX FIFO Statuses +* \{ +*/ +/** The number of entries in the TX FIFO is less than the TX FIFO trigger level +* value +*/ +#define CY_SCB_UART_TX_TRIGGER (SCB_INTR_TX_TRIGGER_Msk) + +/** The TX FIFO is not full, there is a space for more data */ +#define CY_SCB_UART_TX_NOT_FULL (SCB_INTR_TX_NOT_FULL_Msk) + +/** The TX FIFO is empty, note there may still be data in the shift register.*/ +#define CY_SCB_UART_TX_EMPTY (SCB_INTR_TX_EMPTY_Msk) + +/** An attempt to write to the full TX FIFO */ +#define CY_SCB_UART_TX_OVERFLOW (SCB_INTR_TX_OVERFLOW_Msk) + +/** An attempt to read from an empty transmitter FIFO (hardware reads). */ +#define CY_SCB_UART_TX_UNDERFLOW (SCB_INTR_TX_UNDERFLOW_Msk) + +/** All data has been transmitted out of the FIFO, including shifter */ +#define CY_SCB_UART_TX_DONE (SCB_INTR_TX_UART_DONE_Msk) + +/** SmartCard only: the transmitter received a NACK */ +#define CY_SCB_UART_TX_NACK (SCB_INTR_TX_UART_NACK_Msk) + +/** SmartCard only: the transmitter lost arbitration */ +#define CY_SCB_UART_TX_ARB_LOST (SCB_INTR_TX_UART_ARB_LOST_Msk) +/** \} group_scb_uart_macro_tx_fifo_status */ + +/** +* \defgroup group_scb_uart_macro_receive_status UART Receive Statuses +* \{ +*/ +/** The receive operation triggered by \ref Cy_SCB_UART_Receive is in progress */ +#define CY_SCB_UART_RECEIVE_ACTIVE (0x01UL) + +/** +* The hardware RX FIFO was full and there was an attempt to write to it. +* That additional data was dropped. +*/ +#define CY_SCB_UART_RECEIVE_OVERFLOW (SCB_INTR_RX_OVERFLOW_Msk) + +/** The receive hardware detected a frame error, either a start or +* stop bit error +*/ +#define CY_SCB_UART_RECEIVE_ERR_FRAME (SCB_INTR_RX_FRAME_ERROR_Msk) + +/** The receive hardware detected a parity error */ +#define CY_SCB_UART_RECEIVE_ERR_PARITY (SCB_INTR_RX_PARITY_ERROR_Msk) + +/** The receive hardware detected a break transmission from transmitter */ +#define CY_SCB_UART_RECEIVE_BREAK_DETECT (SCB_INTR_RX_BREAK_DETECT_Msk) +/** \} group_scb_uart_macro_receive_status */ + +/** +* \defgroup group_scb_uart_macro_transmit_status UART Transmit Status +* \{ +*/ +/** The transmit operation triggered by \ref Cy_SCB_UART_Transmit is in progress */ +#define CY_SCB_UART_TRANSMIT_ACTIVE (0x01UL) + +/** All data elements specified by \ref Cy_SCB_UART_Transmit are in the TX FIFO */ +#define CY_SCB_UART_TRANSMIT_IN_FIFO (0x02UL) + +/** SmartCard only: the transmitter received a NACK */ +#define CY_SCB_UART_TRANSMIT_NACK (SCB_INTR_TX_UART_NACK_Msk) + +/** SmartCard only: the transmitter lost arbitration */ +#define CY_SCB_UART_TRANSMIT_ARB_LOST (SCB_INTR_TX_UART_ARB_LOST_Msk) +/** \} group_scb_uart_macro_transmit_status */ + +/** +* \defgroup group_scb_uart_macro_callback_events UART Callback Events +* \{ +* Only single event is notified by the callback. +*/ +/** All data elements specified by \ref Cy_SCB_UART_Transmit are in the TX FIFO */ +#define CY_SCB_UART_TRANSMIT_IN_FIFO_EVENT (0x01UL) + +/** +* All data elements specified by \ref Cy_SCB_UART_Transmit have been transmitted. +*/ +#define CY_SCB_UART_TRANSMIT_DONE_EVENT (0x02UL) + +/** All data elements specified by \ref Cy_SCB_UART_Receive have been received */ +#define CY_SCB_UART_RECEIVE_DONE_EVENT (0x04UL) + +/** +* The ring buffer is full, there is no more space for additional data. +* Additional data is stored in the RX FIFO until it becomes full, at which point +* data is dropped. +*/ +#define CY_SCB_UART_RB_FULL_EVENT (0x08UL) + +/** +* An error was detected during the receive operation. This includes overflow, +* frame error, or parity error. Check \ref Cy_SCB_UART_GetReceiveStatus to +* determine the source of the error. +*/ +#define CY_SCB_UART_RECEIVE_ERR_EVENT (0x10UL) + +/** +* An error was detected during the transmit operation. This includes a NACK +* or lost arbitration. Check \ref Cy_SCB_UART_GetTransmitStatus to determine +* the source of the error +*/ +#define CY_SCB_UART_TRANSMIT_ERR_EVENT (0x20UL) +/** \} group_scb_uart_macro_callback_events */ + +/** Data returned by the hardware when an empty RX FIFO is read */ +#define CY_SCB_UART_RX_NO_DATA (0xFFFFFFFFUL) + + +/*************************************** +* Internal Constants +***************************************/ + +/** \cond INTERNAL */ +#define CY_SCB_UART_TX_FIFO_STATUS (CY_SCB_UART_TX_TRIGGER | CY_SCB_UART_TX_NOT_FULL | CY_SCB_UART_TX_EMPTY | \ + CY_SCB_UART_TX_OVERFLOW | CY_SCB_UART_TX_UNDERFLOW | CY_SCB_UART_TX_DONE | \ + CY_SCB_UART_TX_NACK | CY_SCB_UART_TX_ARB_LOST) + +#define CY_SCB_UART_RX_FIFO_STATUS (CY_SCB_UART_RX_TRIGGER | CY_SCB_UART_RX_NOT_EMPTY | CY_SCB_UART_RX_FULL | \ + CY_SCB_UART_RX_OVERFLOW | CY_SCB_UART_RX_UNDERFLOW | CY_SCB_UART_RX_ERR_FRAME | \ + CY_SCB_UART_RX_ERR_PARITY | CY_SCB_UART_RX_BREAK_DETECT) + +#define CY_SCB_UART_TX_INTR (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST) + +#define CY_SCB_UART_RX_INTR (CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UART_FRAME_ERROR | \ + CY_SCB_RX_INTR_UART_PARITY_ERROR | CY_SCB_RX_INTR_UART_BREAK_DETECT) + +#define CY_SCB_UART_RECEIVE_ERR (CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UART_FRAME_ERROR | \ + CY_SCB_RX_INTR_UART_PARITY_ERROR | CY_SCB_RX_INTR_UART_BREAK_DETECT) + +#define CY_SCB_UART_TRANSMIT_ERR (CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST) + +#define CY_SCB_UART_INIT_KEY (0x00ABCDEFUL) +/** \endcond */ + +/** \} group_scb_uart_macro */ + + +/*************************************** +* In-line Function Implementation +***************************************/ + +/** +* \addtogroup group_scb_uart_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_SCB_UART_Enable +****************************************************************************//** +* +* Enables the SCB block for the UART operation. +* +* \param base +* The pointer to the UART SCB instance. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_Enable(CySCB_Type *base) +{ + base->CTRL |= SCB_CTRL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_EnableCts +****************************************************************************//** +* +* Enables the Clear to Send (CTS) input for the UART. The UART will not transmit +* data while this signal is inactive. +* +* \param base +* The pointer to the UART SCB instance. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_EnableCts(CySCB_Type *base) +{ + base->UART_FLOW_CTRL |= SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_DisableCts +****************************************************************************//** +* +* Disables the Clear to Send (CTS) input for the UART. +* See \ref Cy_SCB_UART_EnableCts for the details. +* +* \param base +* The pointer to the UART SCB instance. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_DisableCts(CySCB_Type *base) +{ + base->UART_FLOW_CTRL &= (uint32_t) ~SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_SetRtsFifoLevel +****************************************************************************//** +* +* Sets a level for the Ready To Send (RTS) signal activation. +* When the number of data elements in the receive FIFO is below this level, +* then the RTS output is active. Otherwise, the RTS signal is inactive. +* To disable the RTS signal generation, set this level to zero. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param rxFifoLevel +* The level in the RX FIFO for RTS signal activation. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t rxFifoLevel) +{ + base->UART_FLOW_CTRL = _CLR_SET_FLD32U(base->UART_FLOW_CTRL, SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, rxFifoLevel); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetRtsFifoLevel +****************************************************************************//** +* +* Returns the level in the RX FIFO for the RTS signal activation. +* +* \param base +* The pointer to the UART SCB instance. +* +* \return +* The level in the RX FIFO for RTS signal activation. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const *base) +{ + return _FLD2VAL(SCB_UART_FLOW_CTRL_TRIGGER_LEVEL, base->UART_FLOW_CTRL); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_EnableSkipStart +****************************************************************************//** +* +* Enables the skip start-bit functionality. +* The UART hardware does not synchronize to a start but synchronizes to +* the first rising edge. To create a rising edge, the first data bit must +* be a 1. This feature is useful when the Start edge is used to wake the +* device through a GPIO interrupt. +* +* \param base +* The pointer to the UART SCB instance. +* +* \note +* The skip start-bit feature is applied whenever the UART is disabled due +* to entrance into DeepSleep or after calling \ref Cy_SCB_UART_Disable. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_EnableSkipStart(CySCB_Type *base) +{ + base->UART_RX_CTRL |= SCB_UART_RX_CTRL_SKIP_START_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_DisableSkipStart +****************************************************************************//** +* +* Disable the skip start-bit functionality. +* See \ref Cy_SCB_UART_EnableSkipStart for the details. +* +* \param base +* The pointer to the UART SCB instance. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_DisableSkipStart(CySCB_Type *base) +{ + base->UART_RX_CTRL &= (uint32_t) ~SCB_UART_RX_CTRL_SKIP_START_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_Get +****************************************************************************//** +* +* Reads a single data element from the UART RX FIFO. +* This function does not check whether the RX FIFO has data before reading it. +* If the RX FIFO is empty, the function returns \ref CY_SCB_UART_RX_NO_DATA. +* +* \param base +* The pointer to the UART SCB instance. +* +* \return +* Data from the RX FIFO. +* The data element size is defined by the configured data width. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_UART_Get(CySCB_Type const *base) +{ + return Cy_SCB_ReadRxFifo(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetArray +****************************************************************************//** +* +* Reads an array of data out of the UART RX FIFO. +* This function does not block. It returns how many data elements were read +* from the RX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param rxBuf +* The pointer to the location to place the data read from the RX FIFO. +* The item size is defined by the data type, which depends on the configured +* data width. +* +* \param size +* The number of data elements to read from the RX FIFO. +* +* \return +* The number of data elements read from the RX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_UART_GetArray(CySCB_Type const *base, void *rxBuf, uint32_t size) +{ + return Cy_SCB_ReadArray(base, rxBuf, size); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetArrayBlocking +****************************************************************************//** +* +* Reads an array of data out of the UART RX FIFO. +* This function blocks until the number of data elements specified by the +* size has been read from the RX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param rxBuf +* The pointer to the location to place the data read from the RX FIFO. +* The item size is defined by the data type which depends on the configured +* data width. +* +* \param size +* The number of data elements to read from the RX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_GetArrayBlocking(CySCB_Type const *base, void *rxBuf, uint32_t size) +{ + Cy_SCB_ReadArrayBlocking(base, rxBuf, size); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetRxFifoStatus +****************************************************************************//** +* +* Returns the current status of the RX FIFO. +* Clear the active statuses to let the SCB hardware update them. +* +* \param base +* The pointer to the UART SCB instance. +* +* \return +* \ref group_scb_uart_macro_rx_fifo_status +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_UART_GetRxFifoStatus(CySCB_Type const *base) +{ + return (Cy_SCB_GetRxInterruptStatus(base) & CY_SCB_UART_RX_FIFO_STATUS); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_ClearRxFifoStatus +****************************************************************************//** +* +* Clears the selected statuses of the RX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param clearMask +* The mask whose statuses to clear. +* See \ref group_scb_uart_macro_rx_fifo_status for the set of constants. +* +* \note +* * This status is also used for interrupt generation, so clearing it also +* clears the interrupt sources. +* * Level-sensitive statuses such as \ref CY_SCB_UART_RX_TRIGGER, +* \ref CY_SCB_UART_RX_NOT_EMPTY and \ref CY_SCB_UART_RX_FULL set high again after +* being cleared if the condition remains true. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_ClearRxFifoStatus(CySCB_Type *base, uint32_t clearMask) +{ + Cy_SCB_ClearRxInterrupt(base, clearMask); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetNumInRxFifo +****************************************************************************//** +* +* Returns the number of data elements in the UART RX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \return +* The number of data elements in the RX FIFO. +* The size of date element defined by the configured data width. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInRxFifo(CySCB_Type const *base) +{ + return Cy_SCB_GetNumInRxFifo(base); +} + +/******************************************************************************* +* Function Name: Cy_SCB_UART_ClearRxFifo +****************************************************************************//** +* +* Clears all data out of the UART RX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \sideeffect +* Any data currently in the shifter is cleared and lost. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_ClearRxFifo(CySCB_Type *base) +{ + Cy_SCB_ClearRxFifo(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_Put +****************************************************************************//** +* +* Places a single data element in the UART TX FIFO. +* This function does not block and returns how many data elements were placed +* in the TX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param data +* Data to put in the TX FIFO. +* The item size is defined by the data type which depends on the configured +* data width. +* +* \return +* The number of data elements placed in the TX FIFO: 0 or 1. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_UART_Put(CySCB_Type *base, uint32_t data) +{ + return Cy_SCB_Write(base, data); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_PutArray +****************************************************************************//** +* +* Places an array of data in the UART TX FIFO. +* This function does not block and it returns how many data elements were +* placed in the TX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param txBuf +* The pointer to data to place in the TX FIFO. +* The item size is defined by the data type which depends on the configured +* TX data width. +* +* \param size +* The number of data elements to TX. +* +* \return +* The number of data elements placed in the TX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_UART_PutArray(CySCB_Type *base, void *txBuf, uint32_t size) +{ + return Cy_SCB_WriteArray(base, txBuf, size); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_PutArrayBlocking +****************************************************************************//** +* +* Places an array of data in the UART TX FIFO. +* This function blocks until the number of data elements specified by the size +* is placed in the TX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param txBuf +* The pointer to data to place in the TX FIFO. +* The item size is defined by the data type which depends on the configured +* data width. +* +* \param size +* The number of data elements to write into the TX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_PutArrayBlocking(CySCB_Type *base, void *txBuf, uint32_t size) +{ + Cy_SCB_WriteArrayBlocking(base, txBuf, size); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_PutString +****************************************************************************//** +* +* Places a NULL terminated string in the UART TX FIFO. +* This function blocks until the entire string is placed in the TX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param string +* The pointer to the null terminated string array. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_PutString(CySCB_Type *base, char_t const string[]) +{ + Cy_SCB_WriteString(base, string); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetTxFifoStatus +****************************************************************************//** +* +* Returns the current status of the TX FIFO. +* Clear the active statuses to let the SCB hardware update them. +* +* \param base +* The pointer to the UART SCB instance. +* +* \return +* \ref group_scb_uart_macro_tx_fifo_status +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_UART_GetTxFifoStatus(CySCB_Type const *base) +{ + return (Cy_SCB_GetTxInterruptStatus(base) & CY_SCB_UART_TX_FIFO_STATUS); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_ClearTxFifoStatus +****************************************************************************//** +* +* Clears the selected statuses of the TX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param clearMask +* The mask whose statuses to clear. +* See \ref group_scb_uart_macro_tx_fifo_status for the set of constants. +* +* \note +* * The status is also used for interrupt generation, so clearing it also +* clears the interrupt sources. +* * Level-sensitive statuses such as \ref CY_SCB_UART_TX_TRIGGER, +* \ref CY_SCB_UART_TX_EMPTY and \ref CY_SCB_UART_TX_NOT_FULL set high again after +* being cleared if the condition remains true. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_ClearTxFifoStatus(CySCB_Type *base, uint32_t clearMask) +{ + Cy_SCB_ClearTxInterrupt(base, clearMask); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_GetNumInTxFifo +****************************************************************************//** +* +* Returns the number of data elements in the UART TX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \return +* The number of data elements in the TX FIFO. +* The size of date element defined by the configured data width. +* +* \note +* This number does not include any data currently in the TX shifter. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SCB_UART_GetNumInTxFifo(CySCB_Type const *base) +{ + return Cy_SCB_GetNumInTxFifo(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_IsTxComplete +****************************************************************************//** +* +* Checks if the TX FIFO and Shifter are empty and there is no more data to send +* +* \param base +* Pointer to the UART SCB instance. +* +* \return +* If true, transmission complete. If false, transmission is not complete. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SCB_UART_IsTxComplete(CySCB_Type const *base) +{ + return Cy_SCB_IsTxComplete(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_ClearTxFifo +****************************************************************************//** +* +* Clears all data out of the UART TX FIFO. +* +* \param base +* The pointer to the UART SCB instance. +* +* \sideeffect +* The TX FIFO clear operation also clears the shift register, so that +* the shifter could be cleared in the middle of a data element transfer, +* corrupting it. The data element corruption means that all bits that have +* not been transmitted are transmitted as 1s on the bus. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_ClearTxFifo(CySCB_Type *base) +{ + Cy_SCB_ClearTxFifo(base); +} + + +/******************************************************************************* +* Function Name: Cy_SCB_UART_RegisterCallback +****************************************************************************//** +* +* Registers a callback function that notifies that +* \ref group_scb_uart_macro_callback_events occurred in the +* \ref Cy_SCB_UART_Interrupt. +* +* \param base +* The pointer to the UART SCB instance. +* +* \param callback +* The pointer to the callback function. +* See \ref scb_uart_handle_events_t for the function prototype. +* +* \param context +* The pointer to the context structure \ref cy_stc_scb_uart_context_t allocated +* by the user. The structure is used during the UART operation for internal +* configuration and data keeping. The user should not modify anything +* in this structure. +* +* \note +* To remove the callback, pass NULL as the pointer to the callback function. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SCB_UART_RegisterCallback(CySCB_Type const *base, + scb_uart_handle_events_t callback, cy_stc_scb_uart_context_t *context) +{ + /* Suppress a compiler warning about unused variables */ + (void) base; + + context->cbEvents = callback; +} + +/** \} group_scb_uart_functions */ + +#if defined(__cplusplus) +} +#endif + +/** \} group_scb_uart */ + +#endif /* (CY_SCB_UART_H) */ + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysclk/cy_sysclk.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysclk/cy_sysclk.c new file mode 100644 index 0000000000..a3d89ea34a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysclk/cy_sysclk.c @@ -0,0 +1,1285 @@ +/***************************************************************************//** +* \file cy_sysclk.c +* \version 1.0 +* +* Provides an API implementation of the sysclk driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_sysclk.h" +#include "syslib/cy_syslib.h" +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/* # of elements in an array */ +#define CY_SYSCLK_N_ELMTS(a) (sizeof(a) / sizeof((a)[0])) + +/* ========================================================================== */ +/* =========================== ECO SECTION ============================ */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_EcoConfigure +****************************************************************************//** +* +* This function configures the external crystal oscillator (ECO) trim bits based +* on crystal characteristics. This function should only be called when the ECO is +* disabled. +* +* \param freq Operating frequency of the crystal in Hz. +* +* \param cLoad Crystal load capacitance in pF. +* +* \param esr Effective series resistance of the crystal in ohms. +* +* \param driveLevel Crystal drive level in uW. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - ECO configuration completed successfully
+* CY_SYSCLK_BAD_PARAM - One or more invalid parameters
+* CY_SYSCLK_INVALID_STATE - ECO already enabled +* +* \note +* The following calculations are implemented, generally in floating point: +* freqMHz = freq / 1,000,000 +* max amplitude Vpp = 1,000 * sqrt(drivelevel / 2 / esr) / 3.14 / freqMHz / cLoad +* gm_min mA/V = 5 * 4 * 3.14 * 3.14 * freqMhz^2 * cLoad^2 * 4 * esr / 1,000,000,000 +* # amplifier sections = INT(gm_min / 4.5) +* atrim = if max amplitude < 0.5 then error +* else 2 * the following: +* max amplitude < 0.6: 0 +* max amplitude < 0.7: 1 +* max amplitude < 0.8: 2 +* max amplitude < 0.9: 3 +* max amplitude < 1.15: 5 +* max amplitude < 1.275: 6 +* max amplitude >= 1.275: 7 +* wdtrim = if max amplitude < 0.5 then error +* else 2 * the following: +* max amplitude < 1.2: INT(5 * max amplitude) - 2 +* max amplitude >= 1.2: 3 +* gtrim = if # amplifier sections > 3 then error +* else the following: +* # amplifier sections > 1: # amplifier sections +* # amplifier sections = 1: 0 +* # amplifier sections < 1: 1 +* rtrim = if gtrim = error then error +* else the following: +* freqMHz > 26.8: 0 +* freqMHz > 23.33: 1 +* freqMHz > 16.5: 2 +* freqMHz <= 16.5: 3 +* ftrim = if atrim = error then error +* else INT(atrim / 2) +* +* \note +* This function returns immediately if the ECO is enabled. +*******************************************************************************/ +uint32_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint32_t esr, uint32_t driveLevel) +{ + /* error if ECO is not disabled - any of the 3 enable bits are set */ + uint32_t rtnval = CY_SYSCLK_INVALID_STATE; + if ((SRSS->CLK_ECO_CONFIG & 0xE0000000ul) == 0ul) + { + /* calculate intemediate values */ + float32_t freqMHz = (float32_t)freq / 1000000.0f; + float32_t maxAmplitude = + (1000.0f * ((float32_t)sqrt((float64_t)((float32_t)driveLevel / (2.0f * (float32_t)esr))))) / + (3.14f * freqMHz * (float32_t)cLoad); + float32_t gm_min = + (788.8f /*5 * 4 * 3.14 * 3.14 * 4*/ * freqMHz * freqMHz * (float32_t)cLoad * (float32_t)cLoad) / + 1000000000.0f; + uint32_t nAmpSections = (uint32_t)(gm_min / 4.5f); + + /* error if input parameters cause erroneous intermediate values */ + rtnval = CY_SYSCLK_BAD_PARAM; + if ((maxAmplitude >= 0.5f) && (nAmpSections <= 3ul)) + { + uint32_t atrim, wdtrim, gtrim, rtrim, ftrim, reg; + + atrim = 2ul * (maxAmplitude < 0.6f ? 0ul : + (maxAmplitude < 0.7f ? 1ul : + (maxAmplitude < 0.8f ? 2ul : + (maxAmplitude < 0.9f ? 3ul : + (maxAmplitude < 1.15f ? 5ul : + (maxAmplitude < 1.275f ? 6ul : 7ul)))))); + + wdtrim = 2ul * (maxAmplitude < 1.2f ? (uint32_t)(5.0f * maxAmplitude) - 2ul : 3ul); + + gtrim = (nAmpSections > 1ul ? nAmpSections : + (nAmpSections == 1ul ? 0ul : 1ul)); + + rtrim = (freqMHz > 26.8f ? 0ul : + (freqMHz > 23.33f ? 1ul : + (freqMHz > 16.5f ? 2ul : 3ul))); + + ftrim = atrim / 2ul; + + /* update all fields of trim control register with one write, without + changing the ITRIM field in bits [21:16]: + gtrim: bits [13:12] + rtrim: bits [11:10] + ftrim: bits [9:8] + atrim: bits [7:4] + wdtrim: bits [2:0] + */ + reg = (SRSS->CLK_TRIM_ECO_CTL & ~0x3FFFul); + reg |= (gtrim & 3ul) << 12; + reg |= (rtrim & 3ul) << 10; + reg |= (ftrim & 3ul) << 8; + reg |= (atrim & 0x0Ful) << 4; + reg |= (wdtrim & 7ul); + SRSS->CLK_TRIM_ECO_CTL = reg; + + rtnval = CY_SYSCLK_SUCCESS; + } /* if valid parameters */ + } /* if ECO not enabled */ + + return (rtnval); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_EcoEnable +****************************************************************************//** +* +* Enables the external crystal oscillator (ECO). This function should be called +* after \ref Cy_SysClk_EcoConfigure. +* +* \param timeoutus Amount of time in microseconds to wait for the ECO to lock. +* If a lock does not occur, the ECO is stopped. To avoid waiting for a lock, set +* this paramter to 0. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - ECO successfully enabled
+* CY_SYSCLK_TIMEOUT - Timeout waiting for ECO lock +* +*******************************************************************************/ +uint32_t Cy_SysClk_EcoEnable(uint32_t timeoutus) +{ + uint32_t rtnval; + + /* first set ECO enable */ + SRSS->CLK_ECO_CONFIG |= _VAL2FLD(SRSS_CLK_ECO_CONFIG_ECO_EN, 1ul); /* 1 = enable */ + + /* now do the timeout wait for ECO_STATUS, bit ECO_OK */ + for (; + ((_FLD2VAL(SRSS_CLK_ECO_STATUS_ECO_READY, SRSS->CLK_ECO_STATUS) == 0ul)) &&(timeoutus != 0ul); + timeoutus--) + { + Cy_SysLib_DelayUs(1u); + } + + rtnval = ((timeoutus == 0ul) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS); + return rtnval; +} + + +/* ========================================================================== */ +/* ==================== INPUT MULTIPLEXER SECTION ===================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPathSetSource +****************************************************************************//** +* +* Configures the source for the specified clock path. +* +* \param clkPath Selects which clock path to configure; 0 is the first clock +* path, which is the FLL. +* +* \param source \ref cy_en_clkpath_in_sources_t +* +*******************************************************************************/ +void Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source) +{ + if (source >= CY_SYSCLK_CLKPATH_IN_DSI) + { + SRSS->CLK_DSI_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_DSI_SELECT_DSI_MUX, (uint32_t)source); + SRSS->CLK_PATH_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_PATH_SELECT_PATH_MUX, (uint32_t)CY_SYSCLK_CLKPATH_IN_DSIMUX); + } + else + { + SRSS->CLK_PATH_SELECT[clkPath] = _VAL2FLD(SRSS_CLK_PATH_SELECT_PATH_MUX, (uint32_t)source); + } +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPathGetSource +****************************************************************************//** +* +* Reports which source is selected for the path mux. +* +* \param clkPath Selects which clock path to report; 0 is the first clock path, +* which is the FLL. +* +* \return \ref cy_en_clkpath_in_sources_t +* +*******************************************************************************/ +cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath) +{ + cy_en_clkpath_in_sources_t rtnval = + (cy_en_clkpath_in_sources_t )_FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[clkPath]); + if (rtnval == CY_SYSCLK_CLKPATH_IN_DSIMUX) + { + rtnval = (cy_en_clkpath_in_sources_t)(CY_SYSCLK_CLKPATH_IN_DSI | + (_FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[clkPath]))); + } + return rtnval; +} + + +/* ========================================================================== */ +/* =========================== FLL SECTION ============================ */ +/* ========================================================================== */ +/* min and max FLL output frequencies, in Hz */ +#define CY_SYSCLK_MIN_FLL_CCO_OUTPUT_FREQ 48000000ul +#define CY_SYSCLK_MIN_FLL_OUTPUT_FREQ (CY_SYSCLK_MIN_FLL_CCO_OUTPUT_FREQ / 2u) +#define CY_SYSCLK_MAX_FLL_OUTPUT_FREQ 200000000ul +/* FLL CCO settling time, in microseconds */ +#define CY_SYSCLK_FLL_CCO_SETTLING_TIME 1ul + +/******************************************************************************* +* Function Name: Cy_SysClk_FllConfigure +****************************************************************************//** +* +* Configures the FLL. +* +* \param inputFreq frequency of input source, in Hz +* +* \param outputFreq Desired FLL output frequency, in Hz. Allowable range is +* 24 MHz to 100 MHz (200 MHz with a relatively poor duty cycle. If the output +* frequency is less than 48 MHz, FLL_OUTPUT_DIV must be set; the output divide by +* 2 option is required. +* +* \param outputMode \ref cy_en_fll_pll_output_mode_t +* If output mode is bypass, then the output frequency equals the input source +* frequency regardless of the frequency parameter values. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - FLL successfully configured
+* CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled
+* CY_SYSCLK_BAD_PARAM - desired output frequency is out of valid range +* +* \note +* Do not call this function when the FLL is enabled. If it is, then this function +* returns immediately with an error return value and no register updates. +*******************************************************************************/ +uint32_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode) +{ + uint32_t returnStatus = CY_SYSCLK_SUCCESS; + + /* check for errors */ + if (_FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS->CLK_FLL_CONFIG) != 0u) /* 1 = enabled */ + { + returnStatus = CY_SYSCLK_INVALID_STATE; + } + else if ((outputFreq < CY_SYSCLK_MIN_FLL_OUTPUT_FREQ) || (CY_SYSCLK_MAX_FLL_OUTPUT_FREQ < outputFreq)) /* invalid output frequency */ + { + returnStatus = CY_SYSCLK_BAD_PARAM; + } + else + { /* return status is OK */ + } + + /* no error */ + if (returnStatus == CY_SYSCLK_SUCCESS) /* no errors */ + { + /* If output mode is bypass (input routed directly to output), then done. + The output frequency equals the input frequency regardless of the + frequency parameters. */ + if (outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) + { + cy_stc_fll_manual_config_t config; + uint32_t ccoFreq; + + config.outputMode = outputMode; + /* TRM step 1a,b. Determine if output division by 2 is required. */ + config.enableOutputDiv = (bool)((outputFreq < CY_SYSCLK_MIN_FLL_CCO_OUTPUT_FREQ) ? 1ul : 0ul); + /* TRM step 1c. Compute the CCO frequency from the output division. */ + ccoFreq = outputFreq * ((uint32_t)(config.enableOutputDiv) + 1ul); + /* TRM step 1d,e. Compute the CCO range value from the CCO frequency */ + config.ccoRange = (ccoFreq >= 150000000ul ? CY_SYSCLK_FLL_CCO_RANGE4 : + (ccoFreq >= 113000000ul ? CY_SYSCLK_FLL_CCO_RANGE3 : + (ccoFreq >= 85000000ul ? CY_SYSCLK_FLL_CCO_RANGE2 : + (ccoFreq >= 64000000ul ? CY_SYSCLK_FLL_CCO_RANGE1 : CY_SYSCLK_FLL_CCO_RANGE0)))); + /* TRM step 3. Compute the FLL reference divider value. + Formula is REF_DIV = (1 / precision) * (inputFreq / ccoFreq) + Precision is assumed to be 0.0553%. + Therefore REF_DIV = 1808.019 * inputFreq / ccoFreq + Result is rounded up. */ + config.refDiv = (uint32_t)ceilf((1808.019f * (float32_t)inputFreq) / (float32_t)ccoFreq); + /* TRM step 4. Set the lock tolerance. + Output frequency accuracy = precision * lock tolerance. + Generally a value of 5 is acceptable. */ + config.lockTolerance = 20ul; + /* TRM step 5. Compute the FLL MULT value. Note that we can't integer multiply + ccoFreq * refDiv because it may overflow a 32-bit integer. */ + config.fllMult = CY_SYSCLK_DIV_ROUND(ccoFreq, CY_SYSCLK_DIV_ROUND(inputFreq, config.refDiv)); + /* TRM step 6. Calculate the settling count, using a 1-usec settling time. */ + config.settlingCount = CY_SYSCLK_DIV_ROUNDUP(inputFreq * CY_SYSCLK_FLL_CCO_SETTLING_TIME, 1000000ul); + /* TRM step 7. Calculate the CCO igain and pgain. */ + { + /* CCO gain values based on CCO_RANGE bitfield values */ + const float32_t kCco[] = {46.17112083f, 61.42259619f, 81.71201510f, 108.70353626f, 144.61103156f}; + + /* igain and pgain bitfield values correspond to: 1/256, 1/128, ..., 4, 8 */ + const float32_t gains[] = {0.00390625f, 0.0078125f, 0.015625f, 0.03125f, 0.0625f, 0.125f, 0.25f, + 0.5f, 1.0f, 2.0f, 4.0f, 8.0f}; + + float32_t temp = 0.9f / ((float32_t)(kCco[config.ccoRange] * ((float32_t) config.refDiv / ((float32_t)inputFreq / 1000.0f) ))); + + /* find the largest IGAIN value that is less than kCCO * refDiv /inputFreq */ + for(config.igain = CY_SYSCLK_N_ELMTS(gains) - 1ul; + (gains[config.igain] >= temp) && (config.igain != 0ul); + config.igain--){} + /* then find the largest PGAIN value such that (IGAIN + PGAIN) is less than + kCCO * refDiv /inputFreq */ + for(config.pgain = CY_SYSCLK_N_ELMTS(gains) - 1ul; + ((gains[config.igain] + gains[config.pgain]) >= temp) && (config.pgain != 0ul); + config.pgain--){} + /* final check for exceeding limit; adjust IGAIN and PGAIN downward if needed. */ + while(((gains[config.igain] + gains[config.pgain]) >= temp) && + ((config.igain != 0ul) || (config.pgain != 0ul))) + { + if (config.igain != 0ul) + { + config.igain--; + } + else if (config.pgain != 0ul) + { + config.pgain--; + } + else /* both are zero; exit loop; done the best we can */ + { + } + } + } + + /* configure FLL based on calculated values */ + returnStatus = Cy_SysClk_FllManualConfigure(&config); + } /* if not bypass output mode */ + + else + { /* bypass mode */ + /* update CLK_FLL_CONFIG3 register with divide by 2 parameter */ + CY_SYSCLK_CLR_SET(SRSS->CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, (uint32_t)outputMode); + } + } /* if no error */ + + return (returnStatus); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_FllManualConfigure +****************************************************************************//** +* +* Manually configures the FLL based on user inputs. +* +* \param config \ref cy_stc_fll_manual_config_t +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - FLL successfully configured
+* CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled +* +* \note +* Do not call this function when the FLL is enabled. If it is, then this function +* returns immediately with an error return value and no register updates. +*******************************************************************************/ +uint32_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config) +{ + uint32_t returnStatus = CY_SYSCLK_SUCCESS; + + /* check for errors */ + if (_FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS->CLK_FLL_CONFIG) != 0u) /* 1 = enabled */ + { + returnStatus = CY_SYSCLK_INVALID_STATE; + } + else + { /* return status is OK */ + } + + /* no error */ + if (returnStatus == CY_SYSCLK_SUCCESS) /* no errors */ + { + /* update CLK_FLL_CONFIG register with 2 parameters; FLL_ENABLE is already 0 */ + uint32_t reg = _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_MULT, config->fllMult); + SRSS->CLK_FLL_CONFIG = reg | _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, (uint32_t)(config->enableOutputDiv)); + /* update CLK_FLL_CONFIG2 register with 2 parameters */ + reg = _VAL2FLD(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, config->refDiv); + SRSS->CLK_FLL_CONFIG2 = reg | _VAL2FLD(SRSS_CLK_FLL_CONFIG2_LOCK_TOL, config->lockTolerance); + /* update CLK_FLL_CONFIG3 register with 4 parameters */ + reg = _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, config->igain); + reg |= _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN, config->pgain); + reg |= _VAL2FLD(SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT, config->settlingCount); + SRSS->CLK_FLL_CONFIG3 = reg | _VAL2FLD(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, (uint32_t)(config->outputMode)); + /* update CLK_FLL_CONFIG4 register with 1 parameter; preserve other bits */ + CY_SYSCLK_CLR_SET(SRSS->CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_RANGE, (uint32_t)(config->ccoRange)); + } /* if no error */ + + return (returnStatus); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_FllGetConfiguration +****************************************************************************//** +* +* Reports the FLL configuration settings. +* +* \param config \ref cy_stc_fll_manual_config_t +* +*******************************************************************************/ +void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config) +{ + /* read 2 parameters from CLK_FLL_CONFIG register */ + uint32_t tempReg = SRSS->CLK_FLL_CONFIG; + config->fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, tempReg); + config->enableOutputDiv = (bool)_FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, tempReg); + /* read 2 parameters from CLK_FLL_CONFIG2 register */ + tempReg = SRSS->CLK_FLL_CONFIG2; + config->refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, tempReg); + config->lockTolerance = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_LOCK_TOL, tempReg); + /* read 4 parameters from CLK_FLL_CONFIG3 register */ + tempReg = SRSS->CLK_FLL_CONFIG3; + config->igain = _FLD2VAL(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, tempReg); + config->pgain = _FLD2VAL(SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN, tempReg); + config->settlingCount = _FLD2VAL(SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT, tempReg); + config->outputMode = (cy_en_fll_pll_output_mode_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, tempReg); + /* read 1 parameter from CLK_FLL_CONFIG4 register */ + config->ccoRange = (cy_en_fll_cco_ranges_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG4_CCO_RANGE, SRSS->CLK_FLL_CONFIG4); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_FllEnable +****************************************************************************//** +* +* Enables the FLL. The FLL should be configured before calling this function. +* +* \param timeoutus amount of time in micro seconds to wait for FLL to lock. +* If lock doesn't occur, FLL is stopped. To avoid waiting for lock set this to 0, +* and manually check for lock using \ref Cy_SysClk_FllGetLockStatus. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - FLL successfully enabled
+* CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock +* +*******************************************************************************/ +uint32_t Cy_SysClk_FllEnable(uint32_t timeoutus) +{ + uint32_t rtnval; + bool nonZeroTimeout = (timeoutus != 0ul); + + /* first set the CCO enable bit */ + SRSS->CLK_FLL_CONFIG4 |= _VAL2FLD(SRSS_CLK_FLL_CONFIG4_CCO_ENABLE, 1ul); /* 1 = enable */ + + /* Wait until CCO is ready */ + for (; (_FLD2VAL(SRSS_CLK_FLL_STATUS_CCO_READY, SRSS->CLK_FLL_STATUS) == 0ul) && + (timeoutus != 0ul); + timeoutus--) + { + Cy_SysLib_DelayUs(1u); + } + + /* Set the FLL enable bit, if CCO is ready */ + if ((!nonZeroTimeout) || (nonZeroTimeout && (timeoutus != 0ul))) + { + SRSS->CLK_FLL_CONFIG |= _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, 1ul); /* 1 = enable */ + } + + /* now do the timeout wait for FLL_STATUS, bit LOCKED */ + for (; (_FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS) == 0ul) && + (timeoutus != 0ul); + timeoutus--) + { + Cy_SysLib_DelayUs(1u); + } + + /* If lock doesn't occur, FLL is stopped. */ + if (nonZeroTimeout && (timeoutus == 0ul)) + { + Cy_SysClk_FllDisable(); + } + + rtnval = ((timeoutus == 0ul) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS); + return rtnval; +} + + +/* ========================================================================== */ +/* =========================== PLL SECTION ============================ */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_PllConfigure +****************************************************************************//** +* +* Configures a given PLL. +* The configuration formula used is: +* Fout = pll_clk * (P / Q / div_out), where: +* Fout is the desired output frequency +* pll_clk is the frequency of the input source +* P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. +* Q is the reference divider. Its value is in bitfield REFERENCE_DIV. +* div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. +* +* \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. +* +* \param inputFreq frequency of input source, in Hz; allowed range is 4 MHz to 64 MHz. +* +* \param outputFreq desired output frequency, in Hz; allowed range 1 MHz to 400 MHz, in 4-MHz steps. +* +* \param outputMode \ref cy_en_fll_pll_output_mode_t. If output mode is bypass, then +* the output frequency equals the input source frequency regardless of the +* frequency parameter values. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - PLL successfully configured
+* CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled
+* CY_SYSCLK_BAD_PARAM - invalid clock path number, or input or desired output frequency is out of valid range +* +* \note +* Do not call this function when the PLL is enabled. If it is, then this function +* returns immediately with an error return value and no register updates. +*******************************************************************************/ +uint32_t Cy_SysClk_PllConfigure(uint32_t clkPath, uint32_t inputFreq, uint32_t outputFreq, + cy_en_fll_pll_output_mode_t outputMode) +{ + uint32_t returnStatus = CY_SYSCLK_SUCCESS; + + /* check for error */ + if ((inputFreq < 4000000ul) || (64000000ul < inputFreq)) /* invalid input frequency */ + { + returnStatus = CY_SYSCLK_BAD_PARAM; + } + else if ((outputFreq < 1000000ul) || (400000000ul < outputFreq)) /* invalid output frequency */ + { + returnStatus = CY_SYSCLK_BAD_PARAM; + } + else if ((clkPath == 0ul) || (clkPath > SRSS_NUM_PLL)) /* invalid clock path number */ + { + returnStatus = CY_SYSCLK_BAD_PARAM; + } + else if (_FLD2VAL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS->CLK_PLL_CONFIG[clkPath - 1ul]) != 0u) /* 1 = enabled */ + { + returnStatus = CY_SYSCLK_INVALID_STATE; + } + else + { /* returnStatus is OK */ + } + + /* no errors */ + if (returnStatus == CY_SYSCLK_SUCCESS) + { + uint32_t pBest = 0ul, qBest = 0ul, outBest = 0ul; + + /* If output mode is bypass (input routed directly to output), then done. + The output frequency equals the input frequency regardless of the + frequency parameters. */ + if (outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) + { + /* for each possible value of OUTPUT_DIV and REFERENCE_DIV (Q), try + to find a value for FEEDBACK_DIV (P) that gives an output frequency + as close as possible to the desired output frequency. */ + uint32_t p, q, out; + uint32_t foutBest = 0ul; /* to ensure at least one pass through the for loops below */ + + /* OUTPUT_DIV is 9 bits; range is 2 to 2^9 - 1 */ + for (out = 2ul; (out < 512ul) && (foutBest != outputFreq); out++) + { + /* REFERENCE_DIV (Q) is 5 bits; allowed range is 1 to 2^5 - 1 */ + for (q = 1ul; (q < 31ul) && (foutBest != outputFreq); q++) + { + /* calculate a test value for FEEDBACK_DIV (P) */ + p = CY_SYSCLK_DIV_ROUND(outputFreq * q * out, inputFreq); + /* FEEDBACK_DIV is 7 bits; allowed range is 1 to 50 */ + if ((1u <= p) && (p <= 50u)) + { + /* Calculate what output frequency will actually be produced. + If it's closer to the target than what we have so far, then + save it. */ + uint32_t fout = ((p * inputFreq) / q) / out; + if ((uint32_t)abs((int32_t)fout - (int32_t)outputFreq) < + (uint32_t)abs((int32_t)foutBest - (int32_t)outputFreq)) + { + foutBest = fout; + pBest = p; qBest = q; outBest = out; + } + } + /* exit loops if foutBest equals outputFreq */ + } + } + } /* if not bypass output mode */ + + /* configure PLL based on calculated values */ + returnStatus = Cy_SysClk_PllManualConfigure(clkPath, pBest, qBest, outBest, outputMode); + + } /* if no error */ + + return (returnStatus); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PllManualConfigure +****************************************************************************//** +* +* Manually configures a PLL based on user inputs. +* +* \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. +* +* \param feedbackDiv +* Sets the feedback divider for the selected PLL, valid range is 1 to 50 +* +* \param referenceDiv +* Sets reference divider of PLL, valid range is 1 to 31. (Input Frequency / +* reference divider must be in the range of 4 MHz to 8 MHz. +* +* \param outputDiv +* Sets the output divider, valid range is 1 to 255. To use the PLL as the source +* of an hf_clk this value must be 2 or greater. +* +* \param outputMode +* \ref cy_en_fll_pll_output_mode_t +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - PLL successfully configured
+* CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled
+* CY_SYSCLK_BAD_PARAM - invalid clock path number +* +* \note +* Do not call this function when the PLL is enabled. If it is, then this function +* returns immediately with an error return value and no register updates. +*******************************************************************************/ +uint32_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, uint32_t feedbackDiv, uint32_t referenceDiv, + uint32_t outputDiv, cy_en_fll_pll_output_mode_t outputMode) +{ + uint32_t returnStatus = CY_SYSCLK_SUCCESS; + + /* check for error */ + if ((clkPath == 0ul) || (clkPath > SRSS_NUM_PLL)) /* invalid clock path number */ + { + returnStatus = CY_SYSCLK_BAD_PARAM; + } + else if (_FLD2VAL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS->CLK_PLL_CONFIG[clkPath - 1ul]) != 0u) /* 1 = enabled */ + { + returnStatus = CY_SYSCLK_INVALID_STATE; + } + else + { /* returnStatus is OK */ + } + + /* no errors */ + if (returnStatus == CY_SYSCLK_SUCCESS) + { + clkPath--; /* to correctly access PLL config registers structure */ + /* If output mode is bypass (input routed directly to output), then done. + The output frequency equals the input frequency regardless of the + frequency parameters. */ + if (outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) + { + CY_SYSCLK_CLR_SET(SRSS->CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, feedbackDiv); + CY_SYSCLK_CLR_SET(SRSS->CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, referenceDiv); + CY_SYSCLK_CLR_SET(SRSS->CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, outputDiv); + } + + CY_SYSCLK_CLR_SET(SRSS->CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, (uint32_t)outputMode); + } /* if no error */ + + return (returnStatus); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PllGetConfiguration +****************************************************************************//** +* +* Reports configuration settings for a PLL. +* +* \param clkPath Selects which PLL to report. 1 is the first PLL; 0 is invalid. +* +* \param feedbackDiv +* Pointer to storage for the feedback divider for the selected PLL. +* +* \param referenceDiv +* Pointer to storage for the reference divider for the selected PLL. +* +* \param outputDiv +* Pointer to storage for the output divider for the selected PLL. +* +* \param outputMode +* \ref cy_en_fll_pll_output_mode_t +* +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - PLL data successfully reported
+* CY_SYSCLK_BAD_PARAM - invalid clock path number +* +*******************************************************************************/ +uint32_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, uint32_t *feedbackDiv, uint32_t *referenceDiv, + uint32_t *outputDiv, cy_en_fll_pll_output_mode_t *outputMode) +{ + uint32_t rtnval = CY_SYSCLK_BAD_PARAM; + if ((clkPath != 0ul) && (clkPath <= SRSS_NUM_PLL)) + { + uint32_t tempReg = SRSS->CLK_PLL_CONFIG[clkPath - 1ul]; + *feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, tempReg); + *referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, tempReg); + *outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, tempReg); + *outputMode = (cy_en_fll_pll_output_mode_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, tempReg); + rtnval = CY_SYSCLK_SUCCESS; + } + return (rtnval); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PllEnable +****************************************************************************//** +* +* Enables the PLL. The PLL should be configured before calling this function. +* +* \param clkPath Selects which PLL to enable. 1 is the first PLL; 0 is invalid. +* +* \param timeoutus amount of time in microseconds to wait for the PLL to lock. +* If lock doesn't occur, PLL is stopped. To avoid waiting for lock set this to 0, +* and manually check for lock using \ref Cy_SysClk_PllGetLockStatus. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - PLL successfully enabled
+* CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock
+* CY_SYSCLK_BAD_PARAM - invalid clock path number +* +*******************************************************************************/ +uint32_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus) +{ + uint32_t rtnval = CY_SYSCLK_BAD_PARAM; + if ((clkPath != 0ul) && (clkPath <= SRSS_NUM_PLL)) + { + clkPath--; /* to correctly access PLL config and status registers structures */ + /* first set the PLL enable bit */ + SRSS->CLK_PLL_CONFIG[clkPath] |= _VAL2FLD(SRSS_CLK_PLL_CONFIG_ENABLE, 1ul); /* 1 = enable */ + + /* now do the timeout wait for PLL_STATUS, bit LOCKED */ + for (; (_FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[clkPath]) == 0ul) && + (timeoutus != 0ul); + timeoutus--) + { + Cy_SysLib_DelayUs(1u); + } + rtnval = ((timeoutus == 0ul) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS); + } + return (rtnval); +} + + +/* ========================================================================== */ +/* ==================== Clock Measurement section ==================== */ +/* ========================================================================== */ + +/* Cy_SysClk_InitClkMeasurementCounters() input parameters saved for use later in other functions. */ +static uint32_t clk1FregHz; +static uint32_t clk1Count1; + +/******************************************************************************* +* Function Name: Cy_SysClk_InitClkMeasurementCounters +****************************************************************************//** +* +* Initializes clock measurement counters. +* Measurement counters allow you to measure one clock (clock2) versus another +* clock (clock1). This is done with two hardware counters. One counter (counter1), +* which is clocked off of clock1, is loaded with an initial value and it counts down. +* A second counter (counter2), which is clocked off of clock2, counts up until +* the first counter is done counting down. +* The frequency of clock2 can be determined with the following equation: +* clock2 frequency = (count2/count1) * clock1 frequency +* +* \param clock1 selects which clock is used as the measurement clock +* +* \param clock1FreqHz the frequency of clock1 in Hz +* +* \param count1 sets the initial value for count1 +* +* \param clock2 selects the clock that will be measured by clock1 +* +* \return Error / status code:
+* CY_SYSCLK_INVALID_STATE if already doing a measurement
+* CY_SYSCLK_BAD_PARAM if invalid clock input parameter
+* else CY_SYSCLK_SUCCESS +* +*******************************************************************************/ +uint32_t Cy_SysClk_InitClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t clock1FreqHz, + uint32_t count1, cy_en_meas_clks_t clock2) +{ + uint32_t rtnval = CY_SYSCLK_INVALID_STATE; + if (_FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS->CLK_CAL_CNT1) != 0ul/*1 = done*/) + { + /* if clock1 is a slow clock, + select it in SRSS_CLK_OUTPUT_SLOW.SLOW_SEL0, + select it in SRSS_CLK_OUTPUT_FAST.FAST_SEL0 = SLOW_SEL0 + else if clock1 is a fast clock, + select it in SRSS_CLK_OUTPUT_FAST.FAST_SEL0, + else error, do nothing and return. + + if clock2 is a slow clock, + select it in SRSS_CLK_OUTPUT_SLOW.SLOW_SEL1, + select it in SRSS_CLK_OUTPUT_FAST.FAST_SEL1 = SLOW_SEL1 + else if clock2 is a fast clock, + select it in SRSS_CLK_OUTPUT_FAST.FAST_SEL1, + else error, do nothing and return. + */ + rtnval = CY_SYSCLK_BAD_PARAM; + if ((clock1 < CY_SYSCLK_MEAS_CLK_LAST_CLK) && (clock2 < CY_SYSCLK_MEAS_CLK_LAST_CLK)) + { + if (clock1 < CY_SYSCLK_MEAS_CLK_FAST_CLKS) + { /* slow clock */ + SRSS->CLK_OUTPUT_SLOW = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_SLOW, SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0, (uint32_t)clock1); + SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL0, 7ul/*slow_sel0 output*/); + } /* clock1 slow clock */ + else + { /* fast clock */ + if (clock1 < CY_SYSCLK_MEAS_CLK_PATH_CLKS) + { /* ECO, EXT, ALTHF */ + SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL0, (uint32_t)clock1); + } + else + { /* PATH or HFCLK */ + SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL0, + (((uint32_t)clock1 >> 8) & 0x0Ful) /*use enum bits [11:8]*/); + if (clock1 < CY_SYSCLK_MEAS_CLK_HF_CLKS) + { /* PATH select */ + SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_PATH_SEL0, + ((uint32_t)clock1 & 0x0Ful) /*use enum bits [3:0]*/); + } + else + { /* HFCLK select */ + SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0, + ((uint32_t)clock1 & 0x0Ful) /*use enum bits [3:0]*/); + } + } + } /* clock1 fast clock */ + + if (clock2 < CY_SYSCLK_MEAS_CLK_FAST_CLKS) + { /* slow clock */ + SRSS->CLK_OUTPUT_SLOW = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_SLOW, SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1, (uint32_t)clock2); + SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL1, 7ul/*slow_sel1 output*/); + } /* clock2 slow clock */ + else + { /* fast clock */ + if (clock2 < CY_SYSCLK_MEAS_CLK_PATH_CLKS) + { /* ECO, EXT, ALTHF */ + SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL1, (uint32_t)clock2); + } + else + { /* PATH or HFCLK */ + SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_FAST_SEL1, + (((uint32_t)clock2 >> 8) & 0x0Ful) /*use enum bits [11:8]*/); + if (clock2 < CY_SYSCLK_MEAS_CLK_HF_CLKS) + { /* PATH select */ + SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_PATH_SEL1, + ((uint32_t)clock2 & 0x0Ful) /*use enum bits [3:0]*/); + } + else + { /* HFCLK select */ + SRSS->CLK_OUTPUT_FAST = _CLR_SET_FLD32U(SRSS->CLK_OUTPUT_FAST, SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1, + ((uint32_t)clock2 & 0x0Ful) /*use enum bits [3:0]*/); + } + } + } /* clock2 fast clock */ + + /* Save the remaining input parameters for use later, in other functions. + No error checking is done on these parameters.*/ + clk1FregHz = clock1FreqHz; + clk1Count1 = count1; + + rtnval = CY_SYSCLK_SUCCESS; + } /* if (clock1 < CY_SYSCLK_MEAS_CLK_LAST_CLK && clock2 < CY_SYSCLK_MEAS_CLK_LAST_CLK) */ + } /* if (not done) */ + return (rtnval); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_StartClkMeasurementCounters +****************************************************************************//** +* +* Starts the calibration counters. +* +* \return Error / status code:
+* CY_SYSCLK_INVALID_STATE if already doing a measurement
+* else CY_SYSCLK_SUCCESS +* +* \note Cy_SysClk_InitClkMeasurementCounters() must have been called previously. +*******************************************************************************/ +uint32_t Cy_SysClk_StartClkMeasurementCounters(void) +{ + uint32_t rtnval = CY_SYSCLK_INVALID_STATE; + if (_FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS->CLK_CAL_CNT1) != 0ul/*1 = done*/) + { + /* Counting starts when this register is written with a nonzero value. */ + SRSS->CLK_CAL_CNT1 = clk1Count1; + rtnval = CY_SYSCLK_SUCCESS; + } + return (rtnval); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkMeasurementCountersGetClock2Freq +****************************************************************************//** +* +* Returns the frequency of clock 2 in Hz. The following equation is used: +* clock2 frequency = (count2/count1) * clock1 frequency +* +* \return Frequency of clock 2 in Hz +* +* \note This must only be called if the counters are done. +*******************************************************************************/ +uint32_t Cy_SysClk_ClkMeasurementCountersGetClock2Freq(void) +{ + return (uint32_t) + CY_SYSCLK_DIV_ROUND((uint64_t)_FLD2VAL(SRSS_CLK_CAL_CNT2_CAL_COUNTER2, SRSS->CLK_CAL_CNT2) * clk1FregHz, clk1Count1); +} + +/* ========================================================================== */ +/* ========================== TRIM SECTION ============================ */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_IloTrim +****************************************************************************//** +* +* Trims the ILO to be as close to 32,768 Hz as possible. The clock measurement +* counters should be used to obtain the current frequency of the ILO. This +* frequency should then be passed into this function. This function will then +* use this information to trim the ILO as close as possible to 32,768 Hz. +* +* \param iloFreq current ILO frequency as measured by the measurement counters +* +* \return The achieved ILO frequency in Hz +* +* \note The watchdog timer (WDT) must be unlocked before calling this function. +*******************************************************************************/ +/* target frequency */ +#define CY_SYSCLK_ILO_TARGET_FREQ 32768u + +uint32_t Cy_SysClk_IloTrim(uint32_t iloFreq) +{ + /* Nominal trim step size is 1.5% of "the frequency". Using the target frequency. */ + const uint32_t trimStep = CY_SYSCLK_DIV_ROUND((uint32_t)CY_SYSCLK_ILO_TARGET_FREQ * 15ul, 1000ul); + /* Get the current trim value, and adjust it up or down the appropriate + number of steps. Calculate the new frequency. */ + uint32_t newTrim; + uint32_t newFreq; + uint32_t curTrim = _FLD2VAL(SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM, SRSS->CLK_TRIM_ILO_CTL); + if (iloFreq > CY_SYSCLK_ILO_TARGET_FREQ) + { /* reduce the trim value; calculate new frequency */ + newTrim = curTrim - CY_SYSCLK_DIV_ROUND(iloFreq - CY_SYSCLK_ILO_TARGET_FREQ, trimStep); + newFreq = iloFreq - (trimStep * (curTrim - newTrim)); + } + else + { /* iloFreq too low. Increase the trim value; calculate new frequency. */ + newTrim = curTrim + CY_SYSCLK_DIV_ROUND(CY_SYSCLK_ILO_TARGET_FREQ - iloFreq, trimStep); + newFreq = iloFreq + (trimStep * (newTrim - curTrim)); + } + + /* Update the trim value */ + CY_SYSCLK_CLR_SET(SRSS->CLK_TRIM_ILO_CTL, SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM, newTrim); + + return newFreq; +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PiloTrim +****************************************************************************//** +* +* Trims the PILO to be as close to 32,768 Hz as possible. The clock measurement +* counters should be used to obtain the current frequency of the PILO. This +* frequency should then be passed into this function. This function will then +* use this information to trim the PILO as close as possible to 32,768Hz. +* +* \param piloFreq current PILO frequency as measured by the measurement counters +* +* \return The achieved PILO frequency in Hz +* +*******************************************************************************/ +/* target frequency */ +#define CY_SYSCLK_PILO_TARGET_FREQ 32768u +/* nominal trim step size */ +#define CY_SYSCLK_PILO_TRIM_STEP 1000u + +uint32_t Cy_SysClk_PiloTrim(uint32_t piloFreq) +{ + /* Get the current trim value, and adjust it up or down the appropriate + number of steps. Calculate the new frequency. */ + uint32_t newTrim; + uint32_t newFreq; + uint32_t curTrim = _FLD2VAL(SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ, SRSS->CLK_TRIM_PILO_CTL); + if (piloFreq > CY_SYSCLK_PILO_TARGET_FREQ) + { /* reduce the trim value; calculate new frequency */ + newTrim = curTrim - CY_SYSCLK_DIV_ROUND(piloFreq - CY_SYSCLK_PILO_TARGET_FREQ, CY_SYSCLK_PILO_TRIM_STEP); + newFreq = piloFreq - (CY_SYSCLK_PILO_TRIM_STEP * (curTrim - newTrim)); + } + else + { /* piloFreq too low. Increase the trim value; calculate new frequency. */ + newTrim = curTrim + CY_SYSCLK_DIV_ROUND(CY_SYSCLK_PILO_TARGET_FREQ - piloFreq, CY_SYSCLK_PILO_TRIM_STEP); + newFreq = piloFreq + (CY_SYSCLK_PILO_TRIM_STEP * (newTrim - curTrim)); + } + + /* Update the trim value */ + CY_SYSCLK_CLR_SET(SRSS->CLK_TRIM_PILO_CTL, SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ, newTrim); + + return newFreq; +} + +/* ========================================================================== */ +/* =========================== WCO SECTION ============================ */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_WcoConfigureCsv +****************************************************************************//** +* +* Configure the WCO clock supervisor (CSV). +* +* \param config \ref cy_stc_wco_csv_config_t +* +* \note +* If loss detection is enabled, writes to other register bits are ignored. +* Therefore loss detection is disabled before writing the config structure +* members to the CTL register. Note that one of the config structure members is +* an enable bit. +*******************************************************************************/ +void Cy_SysClk_WcoConfigureCsv(const cy_stc_wco_csv_config_t *config) +{ + #if SRSS_WCOCSV_PRESENT != 0 + /* First clear all bits, including the enable bit; disable loss detection. */ + SRSS->CLK_CSV_WCO_CTL = 0ul; + /* Then write the structure elements (which include an enable bit) to the register. */ + SRSS->CLK_CSV_WCO_CTL = _VAL2FLD(SRSS_CLK_CSV_WCO_CTL_CSV_MUX, (uint32_t)config->SupervisorClock) | + _VAL2FLD(SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_WINDOW, (uint32_t)(config->LossWindow)) | + _VAL2FLD(SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_ACTION, (uint32_t)(config->LossAction)) | + _VAL2FLD(SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_EN, config->enableLossDetection); + #endif /* SRSS_WCOCSV_PRESENT != 0 */ +} + + +/* ========================================================================== */ +/* ======================== clk_hf[n] SECTION ========================= */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_HfClockConfigureCsv +****************************************************************************//** +* +* Configures the ClkHf clock supervisor (CSV). +* +* \param hfClk selects which ClkHf CSV to configure. +* +* \param config \ref cy_stc_hf_csv_config_t +* +* \note +* If loss detection is enabled, writes to other register bits are ignored. +* Therefore loss detection is disabled before writing the config structure +* members to the CTL register. Note that one of the config structure members is +* an enable bit. +*******************************************************************************/ +void Cy_SysClk_HfClockConfigureCsv(uint32_t hfClk, const cy_stc_hf_csv_config_t *config) +{ + #if SRSS_MASK_HFCSV != 0 + /* First update the limit bits; this can be done regardless of enable state. */ + SRSS->CLK_CSV[hfClk].HF_LIMIT = _VAL2FLD(CLK_CSV_HF_LIMIT_UPPER_LIMIT, config->FrequencyUpperLimit) | + _VAL2FLD(CLK_CSV_HF_LIMIT_LOWER_LIMIT, config->FrequencyLowerLimit); + /* Then clear all CTL register bits, including the enable bit; disable loss detection. */ + SRSS->CLK_CSV[hfClk].HF_CTL = 0ul; + /* Finally, write the structure elements (which include an enable bit) to the CTL register. */ + SRSS->CLK_CSV[hfClk].HF_CTL = _VAL2FLD(CLK_CSV_HF_CTL_CSV_LOSS_EN, config->enableLossDetection) | + _VAL2FLD(CLK_CSV_HF_CTL_CSV_LOSS_ACTION, (uint32_t)(config->LossAction)) | + _VAL2FLD(CLK_CSV_HF_CTL_CSV_FREQ_EN, config->enableFrquencyFaultDetection) | + _VAL2FLD(CLK_CSV_HF_CTL_CSV_FREQ_ACTION, (uint32_t)(config->FrequencyAction)) | + _VAL2FLD(CLK_CSV_HF_CTL_CSV_LOSS_WINDOW, (uint32_t)(config->LossWindow)) | + _VAL2FLD(CLK_CSV_HF_CTL_CSV_MUX, (uint32_t)(config->SupervisorClock)) | + _VAL2FLD(CLK_CSV_HF_CTL_CSV_FREQ_WINDOW, config->SupervisingWindow); + #endif /* SRSS_MASK_HFCSV != 0 */ +} + +/* ========================================================================== */ +/* ======================== clk_peri SECTION ========================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphGetFrequency +****************************************************************************//** +* +* Reports the frequency of the output of a given peripheral divider. +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t +* +* \param dividerNum specifies which divider of the selected type to configure +* +* \return The frequency, in Hz +* +* \note +* The reported frequency may be zero, which indicates unknown. This happens if +* the source input is clk_ext, ECO, clk_althf, dsi_out, or clk_altlf. +* +*******************************************************************************/ +uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum) +{ + uint32_t rtnval = 0ul; /* 0 = unknown frequency */ + + /* FLL or PLL configuration parameters */ + union + { + cy_stc_fll_manual_config_t fll; + struct + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + } pll; + } fllpll = {0ul}; + + /* variables holding intermediate clock sources and dividers */ + cy_en_fll_pll_output_mode_t mode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO; /* FLL or PLL mode; n/a for direct */ + uint32_t locked = 0ul; /* FLL or PLL lock status; n/a for direct */ + cy_en_clkpath_in_sources_t source; /* source input for path (FLL, PLL, or direct) */ + uint32_t source_freq; /* source clock frequency, in Hz */ + cy_en_hf_clk_sources_t path; /* source input for root 0 (clk_hf[0]) */ + uint32_t path_freq = 0ul; /* path (FLL, PLL, or direct) frequency, in Hz */ + uint32_t root_div; /* root prescaler (1/2/4/8) */ + uint32_t clk_hf0_div; /* clk_hf[0] predivider to clk_peri */ + + /* clk_peri divider to selected peripheral clock */ + struct + { + uint32_t integer; + uint32_t frac; + } clkdiv = {0ul, 0ul}; + + /* Start by finding the source input for root 0 (clk_hf[0]) */ + path = Cy_SysClk_HfClockGetSource(0ul); + + if (path == CY_SYSCLK_HFCLK_IN_CLKPATH0) /* FLL? (always path #0) */ + { + Cy_SysClk_FllGetConfiguration(&fllpll.fll); + source = Cy_SysClk_ClkPathGetSource(0ul); + mode = fllpll.fll.outputMode; + locked = Cy_SysClk_FllGetLockStatus(); + } + else if ((uint32_t)path <= (uint32_t)SRSS_NUM_PLL) /* PLL? (always path #1 - N)*/ + { + (void)Cy_SysClk_PllGetConfiguration((uint32_t)path, &fllpll.pll.feedbackDiv, &fllpll.pll.referenceDiv, + &fllpll.pll.outputDiv, &mode); + source = Cy_SysClk_ClkPathGetSource((uint32_t)path); + locked = Cy_SysClk_PllGetLockStatus((uint32_t)path); + } + else /* assume clk_path < SRSS_NUM_CLKPATH */ + { /* Direct select path. Use PLL function to get the source. */ + source = Cy_SysClk_ClkPathGetSource((uint32_t)path); + } + + /* get the frequency of the source, i.e., the path mux input */ + switch(source) + { + case CY_SYSCLK_CLKPATH_IN_IMO: /* IMO frequency is fixed at 8 MHz */ + source_freq = 8000000ul; /*Hz*/ + break; + case CY_SYSCLK_CLKPATH_IN_ILO: /* ILO and WCO frequencies are nominally 32.768 kHz */ + case CY_SYSCLK_CLKPATH_IN_WCO: + source_freq = 32768ul; /*Hz*/ + break; + default: + /* don't know the frequency of clk_ext, ECO, clk_althf, dsi_out, or clk_altlf */ + source_freq = 0ul; /* unknown frequency */ + break; + } + if (source_freq != 0ul) + { + /* Calculate the path frequency */ + if (path == CY_SYSCLK_HFCLK_IN_CLKPATH0) /* FLL? (always path #0) */ + { + path_freq = source_freq; /* for bypass mode */ + /* if not bypass mode, apply the dividers calculation */ + if ((mode == CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT) || ((mode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) && (locked != 0ul))) + { + /* Ffll_out = Ffll_clk * FLL_MULT / FLL_REF_DIV / (FLL_OUTPUT_DIV + 1), where: + * FLL_MULT, REFERENCE_DIV, and OUTPUT_DIV are FLL configuration register bitfields + * Check for possible divide by 0. + */ + if (fllpll.fll.refDiv != 0ul) + { + path_freq = (uint32_t)(((uint64_t)path_freq * (uint64_t)fllpll.fll.fllMult) / + (uint64_t)fllpll.fll.refDiv) / + ((uint32_t)(fllpll.fll.enableOutputDiv) + 1ul); + } + else + { + path_freq = 0ul; /* error, one of the divisors is 0 */ + } + } + } + else if ((uint32_t)path <= (uint32_t)SRSS_NUM_PLL) /* PLL? (always path #1 - N)*/ + { + path_freq = source_freq; /* for bypass mode */ + /* if not bypass mode, apply the dividers calculation */ + if ((mode == CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT) || ((mode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) && (locked != 0ul))) + { + /* Fpll_out = Fpll_clk * FEEDBACK_DIV / REFERENCE_DIV / OUTPUT_DIV, where: + * FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV are PLL configuration register bitfields + * Check for possible divide by 0. + */ + if ((fllpll.pll.referenceDiv != 0ul) && (fllpll.pll.outputDiv != 0ul)) + { + path_freq = (uint32_t)(((uint64_t)source_freq * (uint64_t)fllpll.pll.feedbackDiv) / + (uint64_t)fllpll.pll.referenceDiv) / + (uint32_t)fllpll.pll.outputDiv; + } + else + { + path_freq = 0ul; /* error, one of the divisors is 0 */ + } + } + } + else /* assume clk_path < SRSS_NUM_CLKPATH */ + { /* direct select path */ + path_freq = source_freq; + } + + /* get the prescaler value for root 0, or clk_hf[0]: 1/2/4/8 */ + root_div = 1ul << (uint32_t)Cy_SysClk_HfClockGetDivider(0ul); + + /* get the predivider value for clk_hf[0] to clk_peri */ + clk_hf0_div = (uint32_t)Cy_SysClk_PeriClkGetDivider() + 1ul; + + /* get the divider value for clk_peri to the selected peripheral clock */ + switch(dividerType) + { + case CY_SYSCLK_DIV_8_BIT: + case CY_SYSCLK_DIV_16_BIT: + clkdiv.integer = (uint32_t)Cy_SysClk_PeriphGetDivider(dividerType, dividerNum); + /* frac = 0 means it's an integer divider */ + break; + case CY_SYSCLK_DIV_16_5_BIT: + case CY_SYSCLK_DIV_24_5_BIT: + (void)Cy_SysClk_PeriphGetFracDivider(dividerType, dividerNum, &clkdiv.integer, &clkdiv.frac); + break; + default: + break; + } + /* Divide the path input frequency down, and return the result. + Stepping through the following code shows the frequency at each stage. + */ + rtnval = path_freq / root_div; /* clk_hf[0] frequency */ + rtnval /= clk_hf0_div; /* clk_peri frequency */ + /* For fractional dividers, the divider is (int + 1) + frac/32. + * Use the fractional value to round the divider to the nearest integer. + */ + rtnval /= (clkdiv.integer + 1ul + ((clkdiv.frac >= 16ul) ? 1ul : 0ul)); /* peripheral divider output frequency */ + } + + return rtnval; +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysclk/cy_sysclk.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysclk/cy_sysclk.h new file mode 100644 index 0000000000..b05df13f73 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysclk/cy_sysclk.h @@ -0,0 +1,2165 @@ +/***************************************************************************//** +* \file cy_sysclk.h +* \version 1.0 +* +* Provides an API declaration of the sysclk driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_sysclk System Clock (SysClk) +* \{ +* The sysclk driver contains an API for configuring system and peripheral clocks. +* Most of the sysclk driver API functions are simple wrappers for writing to registers +* to configure or manage a particular clock. +* +* In the API reference for this driver each clock has its own section, so all the +* information to manage that clock is in the same place. +* +* \section group_sysclk_configuration Configuration Considerations +* +* \warning When the device is in the Ultra-Low Power (ULP) mode, the maximum frequency of all the clocks is limited to +* the 50 MHz with the exception for the slow clock which is limited to 25 MHz. +* +* There are no general sysclk configuration concerns. Some clocks (for example the PLL) require configuration. +* For such a clock the API provides a configuration structure and a Configure() function to set up the clock. +* See notes on individual function definitions. +* +* \section group_sysclk_more_information More Information +* +* See the Clock Component datasheet. +* See also the sysclk chapter of the device technical reference manual (TRM). +* +* \section group_sysclk_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
1.2RNo reliance on undefined behavior.Calculation of absolute value in FLL and PLL configure.
10.1RThe value of an expression of integer type shall not be implicitly converted to a different, underlying type if the expression is complex.Using a Cypress defined macro to access memory mapped objects. +* Using a Cypress defined macro to divide with rounding.
10.3RA composite integer expression is being cast to a wider type.Using a Cypress defined macro to access memory mapped objects. Calculating clock parameters.
10.4RA composite floating point expression is being cast to double, or unsigned.Using the C library sqrt() function. Casting a floating point calculation result to an integer.
10.5RThe value of an expression of integer type shall not be implicitly converted to a different, underlying type if the expression is complex.Using a Cypress defined macro to access memory mapped objects.
12.1AExtra parentheses recommended.Ternary operator uses constants; extra parentheses not needed.
13.4RThe controlling expression of a for statement shall not contain any objects of floating type.Scanning through a list of floating point values.
18.4RUnions shall not be used.Clock path in \ref Cy_SysClk_PeriphGetFrequency() may use either FLL or PLL.
19.7AA function shall be used in preference to a function-like macro.Function-like macros are used to achieve more efficient code.
+* +* \section group_sysclk_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_sysclk_macro Macros +* \{ +* \defgroup group_sysclk_macro_return Function return values +* \} +* \defgroup group_sysclk_imo Internal Main Oscillator (IMO) +* \defgroup group_sysclk_eco External Crystal Oscillator (ECO) +* \defgroup group_sysclk_muxes Input Multiplexers +* \defgroup group_sysclk_fll Frequency Locked Loop (FLL) +* \defgroup group_sysclk_pll Phase Locked Loop (PLL) +* \defgroup group_sysclk_ilo Internal Low-Speed Oscillator (ILO) +* \defgroup group_sysclk_pilo Precision Internal Low-Speed Oscillator (PILO) +* \defgroup group_sysclk_calclk Clock Measurement +* \defgroup group_sysclk_trim Clock Trim +* \defgroup group_sysclk_wco Watch Crystal Oscillator (WCO) +* \defgroup group_sysclk_clk_hf High-Frequency Clocks +* \defgroup group_sysclk_clk_fast Fast Clock +* \defgroup group_sysclk_clk_peripheral Peripherals Clocks +* \defgroup group_sysclk_clk_slow Slow Clock +* \defgroup group_sysclk_clk_lf Low-Frequency Clock +* \defgroup group_sysclk_clk_timer Timer Clock +* \defgroup group_sysclk_clk_pump Pump Clock +* \defgroup group_sysclk_clk_bak Backup Domain Clock +*/ + +#if !defined(__CY_SYSCLK_H__) +#define __CY_SYSCLK_H__ + +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" +#include + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** +* \addtogroup group_sysclk_macro +* \{ +*/ + +/** Driver major version */ +#define CY_SYSCLK_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_SYSCLK_DRV_VERSION_MINOR 0 + +/** +* \addtogroup group_sysclk_returns +* \{ +* Specifies return values meaning +*/ +/** Command completed with no errors */ +#define CY_SYSCLK_SUCCESS 0ul +/** Invalid function input parameter */ +#define CY_SYSCLK_BAD_PARAM 1ul +/** Status of calibration counters: STARTED */ +#define CY_SYSCLK_STARTED 7ul +/** Status of calibration counters: FINISHED */ +#define CY_SYSCLK_FINISHED 8ul +/** Timeout occurred */ +#define CY_SYSCLK_TIMEOUT 0x10ul +/** Clock is in an invalid state */ +#define CY_SYSCLK_INVALID_STATE 0x11ul +/** \} group_sysclk_returns */ +/** \} group_sysclk_macro */ + +/** \cond INTERNAL */ +/* Generates shorter code for setting register bitfields */ +#define CY_SYSCLK_CLR_SET(reg, field, value) (reg) = _CLR_SET_FLD32U((reg), field, value) +/* Calculate a / b with rounding to the nearest integer. a and b must have the same sign. */ +#define CY_SYSCLK_DIV_ROUND(a, b) (((a) + ((b) / 2u)) / (b)) +/* Calculate a / b with rounding up if remainder != 0. a and b must both be positive. */ +#define CY_SYSCLK_DIV_ROUNDUP(a, b) ((((a) - 1u) / (b)) + 1u) +/** \endcond */ + +/** +* \addtogroup group_sysclk_imo +* \{ +*/ + +/* ========================================================================== */ +/* =========================== IMO SECTION ============================ */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_ImoEnable +****************************************************************************//** +* +* Enables the internal main oscillator (IMO). +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ImoEnable(void) +{ + SRSS->CLK_IMO_CONFIG |= _VAL2FLD(SRSS_CLK_IMO_CONFIG_ENABLE, 1u); /* 1 = enable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ImoDisable +****************************************************************************//** +* +* Disables the internal main oscillator (IMO). +* +* \note +* If the IMO is the source of hf_clk[0] then disabling the IMO disables the CPU. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ImoDisable(void) +{ + SRSS->CLK_IMO_CONFIG &= ~_VAL2FLD(SRSS_CLK_IMO_CONFIG_ENABLE, 1u); /* 0 = disable */ +} +/** \} group_sysclk_imo */ + + +/** +* \addtogroup group_sysclk_eco +* \{ +*/ + +/* ========================================================================== */ +/* =========================== ECO SECTION ============================ */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_EcoConfigure +****************************************************************************//** +* +* This function configures the external crystal oscillator (ECO) trim bits based +* on crystal characteristics. This function should be called only when the ECO is +* disabled. +* +* \param freq Operating frequency of the crystal in Hz. +* +* \param cLoad Crystal load capacitance in pF. +* +* \param esr Effective series resistance of the crystal in ohms. +* +* \param driveLevel Crystal drive level in uW. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - ECO configuration completed successfully
+* CY_SYSCLK_BAD_PARAM - One or more invalid parameters
+* CY_SYSCLK_INVALID_STATE - ECO already enabled +* +* \note +* The following calculations are implemented, generally in floating point: +* freqMHz = freq / 1,000,000 +* max amplitude Vpp = 1,000 * sqrt(drivelevel / 2 / esr) / 3.14 / freqMHz / cLoad +* gm_min mA/V = 5 * 4 * 3.14 * 3.14 * freqMhz^2 * cLoad^2 * 4 * esr / 1,000,000,000 +* # amplifier sections = INT(gm_min / 4.5) +* atrim = if max amplitude < 0.5 then error +* else 2 * the following: +* max amplitude < 0.6: 0 +* max amplitude < 0.7: 1 +* max amplitude < 0.8: 2 +* max amplitude < 0.9: 3 +* max amplitude < 1.15: 5 +* max amplitude < 1.275: 6 +* max amplitude >= 1.275: 7 +* wdtrim = if max amplitude < 0.5 then error +* else 2 * the following: +* max amplitude < 1.2: INT(5 * max amplitude) - 2 +* max amplitude >= 1.2: 3 +* gtrim = if # amplifier sections > 3 then error +* else the following: +* # amplifier sections > 1: # amplifier sections +* # amplifier sections = 1: 0 +* # amplifier sections < 1: 1 +* rtrim = if gtrim = error then error +* else the following: +* freqMHz > 26.8: 0 +* freqMHz > 23.33: 1 +* freqMHz > 16.5: 2 +* freqMHz <= 16.5: 3 +* ftrim = if atrim = error then error +* else INT(atrim / 2) +* +* \note +* This function returns immediately if the ECO is enabled. +*******************************************************************************/ +uint32_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint32_t esr, uint32_t driveLevel); + +/******************************************************************************* +* Function Name: Cy_SysClk_EcoEnable +****************************************************************************//** +* +* Enables the external crystal oscillator (ECO). This function should be called +* after \ref Cy_SysClk_EcoConfigure. +* +* \param timeoutus Amount of time in microseconds to wait for the ECO to lock. +* If a lock does not occur, the ECO is stopped. To avoid waiting for a lock, set +* this parameter to 0. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - ECO successfully enabled
+* CY_SYSCLK_TIMEOUT - Timeout waiting for ECO lock +* +*******************************************************************************/ +uint32_t Cy_SysClk_EcoEnable(uint32_t timeoutus); + +/******************************************************************************* +* Function Name: Cy_SysClk_EcoDisable +****************************************************************************//** +* +* Disables the external crystal oscillator (ECO). This function should not be +* called if the ECO is sourcing clk_hf[0]. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_EcoDisable(void) +{ + SRSS->CLK_ECO_CONFIG &= ~_VAL2FLD(SRSS_CLK_ECO_CONFIG_ECO_EN, 1u); /* 0 = disable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_EcoGetStatus +****************************************************************************//** +* +* Reports the current status of the external crystal oscillator (ECO). +* +* \return +* 0 = ECO does not have sufficient amplitude
+* 1 = ECO has sufficient amplitude but may not be meeting accuracy and duty cycle specifications
+* 2 = ECO has fully stabilized +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void) +{ + uint32_t retval = (SRSS->CLK_ECO_STATUS & 3ul); /* bit 0 = ECO_OK, bit 1 = ECO_READY */ + /* if ECO is not ready, just report the ECO_OK bit. Otherwise report 2 = ECO ready */ + return (((retval & 2ul) == 0) ? retval : 2ul); +} +/** \} group_sysclk_eco */ + + +/** +* \addtogroup group_sysclk_muxes +* \{ +*/ + +/* ========================================================================== */ +/* ==================== INPUT MULTIPLEXER SECTION ===================== */ +/* ========================================================================== */ +/** +* Configures two multiplexers: a DSI multiplexer and a path multiplexer. The +* outputs of these multiplexers generally drive the FLL and the PLLs. See +* CLK_DSI_SELECT registers, DSI_MUX bits, and CLK_PATH_SELECT registers, +* PATH_MUX bits. Used with functions \ref Cy_SysClk_ClkPathSetSource and +* \ref Cy_SysClk_ClkPathGetSource. +* +* \note +* Each path multiplexer output is a source for the corresponding FLL/PLL input +* source multiplexer. +* +* \note The PDL driver cannot use the DSI outputs as sources. This must be done +* through DSI configuration using PSoC Creator. +*/ +typedef enum +{ + CY_SYSCLK_CLKPATH_IN_IMO = 0u, /**< Select the IMO as the output of the path mux */ + CY_SYSCLK_CLKPATH_IN_EXT = 1u, /**< Select the EXT as the output of the path mux */ + CY_SYSCLK_CLKPATH_IN_ECO = 2u, /**< Select the ECO as the output of the path mux */ + CY_SYSCLK_CLKPATH_IN_ALTHF = 3u, /**< Select the ALTHF as the output of the path mux */ + CY_SYSCLK_CLKPATH_IN_DSIMUX = 4u, /**< Select the DSI MUX output as the output of the path mux */ + CY_SYSCLK_CLKPATH_IN_DSI = 0x100u, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux */ + CY_SYSCLK_CLKPATH_IN_ILO = 0x110u, /**< Select the ILO (16) as the output of the DSI mux and path mux */ + CY_SYSCLK_CLKPATH_IN_WCO = 0x111u, /**< Select the WCO (17) as the output of the DSI mux and path mux */ + CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112u, /**< Select the ALTLF (18) as the output of the DSI mux and path mux */ + CY_SYSCLK_CLKPATH_IN_PILO = 0x113u /**< Select the PILO (19) as the output of the DSI mux and path mux */ +} cy_en_clkpath_in_sources_t; + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPathSetSource +****************************************************************************//** +* +* Configures the source for the specified clock path. +* +* \param clkPath Selects which clock path to configure; 0 is the first clock +* path, which is the FLL. +* +* \param source \ref cy_en_clkpath_in_sources_t +* +*******************************************************************************/ +void Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source); + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPathGetSource +****************************************************************************//** +* +* Reports which source is selected for the path mux. +* +* \param clkPath Selects which clock path to report; 0 is the first clock path, +* which is the FLL. +* +* \return \ref cy_en_clkpath_in_sources_t +* +*******************************************************************************/ +cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath); +/** \} group_sysclk_muxes */ + + +/** +* \addtogroup group_sysclk_fll +* \{ +*/ + +/* ========================================================================== */ +/* =========================== FLL SECTION ============================ */ +/* ========================================================================== */ +/** FLL and PLL output mode. +* See registers CLK_FLL_CONFIG3 and CLK_PLL_CONFIG0, bits BYPASS_SEL. +*/ +typedef enum +{ + CY_SYSCLK_FLLPLL_OUTPUT_AUTO = 0u, /**< Output FLL/PLL input source when not locked, and FLL/PLL output when locked. */ + CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 = 1u, /**< Same as AUTO */ + CY_SYSCLK_FLLPLL_OUTPUT_INPUT = 2u, /**< Output FLL/PLL input source regardless of lock status. */ + CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT = 3u /**< Output FLL/PLL output regardless of lock status. This can be dangerous if used to clock hf_clk as FLL/PLL output may be unstable. */ +} cy_en_fll_pll_output_mode_t; + +/** FLL current-controlled oscillator (CCO) frequency ranges. +* See register CLK_FLL_CONFIG4, bits CCO_RANGE. +*/ +typedef enum +{ + CY_SYSCLK_FLL_CCO_RANGE0, /**< Target frequency is in range 48 - 64 MHz. */ + CY_SYSCLK_FLL_CCO_RANGE1, /**< Target frequency is in range 64 - 85 MHz. */ + CY_SYSCLK_FLL_CCO_RANGE2, /**< Target frequency is in range 85 - 113 MHz. */ + CY_SYSCLK_FLL_CCO_RANGE3, /**< Target frequency is in range 113 - 150 MHz. */ + CY_SYSCLK_FLL_CCO_RANGE4 /**< Target frequency is in range 150 - 200 MHz. */ +} cy_en_fll_cco_ranges_t; + +/** Structure containing information for manual configuration of FLL. +*/ +typedef struct +{ + uint32_t fllMult; /**< CLK_FLL_CONFIG register, FLL_MULT bits */ + uint32_t refDiv; /**< CLK_FLL_CONFIG2 register, FLL_REF_DIV bits */ + cy_en_fll_cco_ranges_t ccoRange; /**< CLK_FLL_CONFIG4 register, CCO_RANGE bits */ + bool enableOutputDiv; /**< CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit */ + uint32_t lockTolerance; /**< CLK_FLL_CONFIG2 register, LOCK_TOL bits */ + uint32_t igain; /**< CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits */ + uint32_t pgain; /**< CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits */ + uint32_t settlingCount; /**< CLK_FLL_CONFIG3 register, SETTLING_COUNT bits */ + cy_en_fll_pll_output_mode_t outputMode; /**< CLK_FLL_CONFIG3 register, BYPASS_SEL bits */ +} cy_stc_fll_manual_config_t; + +/******************************************************************************* +* Function Name: Cy_SysClk_FllConfigure +****************************************************************************//** +* +* Configures the FLL. +* +* \param inputFreq frequency of input source, in Hz +* +* \param outputFreq Desired FLL output frequency, in Hz. Allowable range is +* 24 MHz to 100 MHz (200 MHz with a relatively poor duty cycle. If the output +* frequency is less than 48 MHz, FLL_OUTPUT_DIV must be set; the output divide by +* 2 option is required. +* +* \param outputMode \ref cy_en_fll_pll_output_mode_t +* If output mode is bypass, then the output frequency equals the input source +* frequency regardless of the frequency parameter values. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - FLL successfully configured
+* CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled
+* CY_SYSCLK_BAD_PARAM - desired output frequency is out of valid range +* +* \note +* Do not call this function when the FLL is enabled. If it is, then this function +* returns immediately with an error return value and no register updates. +*******************************************************************************/ +uint32_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode); + +/******************************************************************************* +* Function Name: Cy_SysClk_FllManualConfigure +****************************************************************************//** +* +* Manually configures the FLL based on user inputs. +* +* \param config \ref cy_stc_fll_manual_config_t +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - FLL successfully configured
+* CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled +* +* \note +* Do not call this function when the FLL is enabled. If it is, then this function +* returns immediately with an error return value and no register updates. +*******************************************************************************/ +uint32_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config); + +/******************************************************************************* +* Function Name: Cy_SysClk_FllGetConfiguration +****************************************************************************//** +* +* Reports the FLL configuration settings. +* +* \param config \ref cy_stc_fll_manual_config_t +* +*******************************************************************************/ +void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config); + +/******************************************************************************* +* Function Name: Cy_SysClk_FllEnable +****************************************************************************//** +* +* Enables the FLL. The FLL should be configured before calling this function. +* +* \param timeoutus amount of time in micro seconds to wait for FLL to lock. +* If lock doesn't occur, FLL is stopped. To avoid waiting for lock set this to 0, +* and manually check for lock using \ref Cy_SysClk_FllGetLockStatus. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - FLL successfully enabled
+* CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock +* +*******************************************************************************/ +uint32_t Cy_SysClk_FllEnable(uint32_t timeoutus); + +/******************************************************************************* +* Function Name: Cy_SysClk_FllGetLockStatus +****************************************************************************//** +* +* Returns lock status of the FLL +* +* \return 0 = not locked, 1 = locked +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_FllGetLockStatus(void) +{ + return (uint32_t)(_FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_FllLostLock +****************************************************************************//** +* +* Reports whether or not the FLL lost its lock since the last time this function +* was called. Clears the lost lock indicator. +* +* \return 0 = didn't lose lock, 1 = lost lock +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_FllLostLock(void) +{ + uint32_t retval = _FLD2VAL(SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED, SRSS->CLK_FLL_STATUS); + /* write a 1 to clear the unlock occurred bit */ + SRSS->CLK_FLL_STATUS = _VAL2FLD(SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED, 1u); + return (retval); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_FllDisable +****************************************************************************//** +* +* Disables the FLL and the CCO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_FllDisable(void) +{ + SRSS->CLK_FLL_CONFIG &= ~_VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, 1u); /* 0 = disable */ + SRSS->CLK_FLL_CONFIG4 &= ~_VAL2FLD(SRSS_CLK_FLL_CONFIG4_CCO_ENABLE, 1u); /* 0 = disable */ +} +/** \} group_sysclk_fll */ + + +/** +* \addtogroup group_sysclk_pll +* \{ +*/ + +/* ========================================================================== */ +/* =========================== PLL SECTION ============================ */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_PllConfigure +****************************************************************************//** +* +* Configures a given PLL. +* The configuration formula used is: +* Fout = pll_clk * (P / Q / div_out), where: +* Fout is the desired output frequency +* pll_clk is the frequency of the input source +* P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. +* Q is the reference divider. Its value is in bitfield REFERENCE_DIV. +* div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. +* +* \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. +* +* \param inputFreq frequency of input source, in Hz; allowed range is 4 MHz to 64 MHz. +* +* \param outputFreq desired output frequency, in Hz; allowed range 1 MHz to 400 MHz, in 4-MHz steps. +* +* \param outputMode \ref cy_en_fll_pll_output_mode_t. If output mode is bypass, then +* the output frequency equals the input source frequency regardless of the +* frequency parameter values. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - PLL successfully configured
+* CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled
+* CY_SYSCLK_BAD_PARAM - invalid clock path number, or input or desired output frequency is out of valid range +* +* \note +* Do not call this function when the PLL is enabled. If it is, then this function +* returns immediately with an error return value and no register updates. +*******************************************************************************/ +uint32_t Cy_SysClk_PllConfigure(uint32_t clkPath, uint32_t inputFreq, uint32_t outputFreq, + cy_en_fll_pll_output_mode_t outputMode); + +/******************************************************************************* +* Function Name: Cy_SysClk_PllManualConfigure +****************************************************************************//** +* +* Manually configures a PLL based on user inputs. +* +* \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. +* +* \param feedbackDiv +* Sets the feedback divider for the selected PLL, valid range is 1 to 50 +* +* \param referenceDiv +* Sets reference divider of PLL, valid range is 1 to 31. (Input Frequency / +* reference divider must be in the range of 4 MHz to 8 MHz. +* +* \param outputDiv +* Sets the output divider, valid range is 1 to 255. To use the PLL as the source +* of an hf_clk this value must be 2 or greater. +* +* \param outputMode +* \ref cy_en_fll_pll_output_mode_t +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - PLL successfully configured
+* CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled
+* CY_SYSCLK_BAD_PARAM - invalid clock path number +* +* \note +* Do not call this function when the PLL is enabled. If it is, then this function +* returns immediately with an error return value and no register updates. +*******************************************************************************/ +uint32_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, uint32_t feedbackDiv, uint32_t referenceDiv, + uint32_t outputDiv, cy_en_fll_pll_output_mode_t outputMode); + +/******************************************************************************* +* Function Name: Cy_SysClk_PllGetConfiguration +****************************************************************************//** +* +* Reports configuration settings for a PLL. +* +* \param clkPath Selects which PLL to report. 1 is the first PLL; 0 is invalid. +* +* \param feedbackDiv +* Pointer to storage for the feedback divider for the selected PLL. +* +* \param referenceDiv +* Pointer to storage for the reference divider for the selected PLL. +* +* \param outputDiv +* Pointer to storage for the output divider for the selected PLL. +* +* \param outputMode +* \ref cy_en_fll_pll_output_mode_t +* +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - PLL data successfully reported
+* CY_SYSCLK_BAD_PARAM - invalid clock path number +* +*******************************************************************************/ +uint32_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, uint32_t *feedbackDiv, uint32_t *referenceDiv, + uint32_t *outputDiv, cy_en_fll_pll_output_mode_t *outputMode); + +/******************************************************************************* +* Function Name: Cy_SysClk_PllEnable +****************************************************************************//** +* +* Enables the PLL. The PLL should be configured before calling this function. +* +* \param clkPath Selects which PLL to enable. 1 is the first PLL; 0 is invalid. +* +* \param timeoutus amount of time in microseconds to wait for the PLL to lock. +* If lock doesn't occur, PLL is stopped. To avoid waiting for lock set this to 0, +* and manually check for lock using \ref Cy_SysClk_PllGetLockStatus. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - PLL successfully enabled
+* CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock
+* CY_SYSCLK_BAD_PARAM - invalid clock path number +* +*******************************************************************************/ +uint32_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus); + +/******************************************************************************* +* Function Name: Cy_SysClk_PllGetLockStatus +****************************************************************************//** +* +* Reports the lock status of the selected PLL. +* +* \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. +* +* \return 0 = not locked, 1 = locked, 0xFF = invalid clock path number +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_PllGetLockStatus(uint32_t clkPath) +{ + uint32_t retval = 0xFFul; /* invalid clock path number */ + if ((clkPath != 0ul) && (clkPath <= SRSS_NUM_PLL)) + { + retval = _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[clkPath - 1ul]); + } + return (retval); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PllLostLock +****************************************************************************//** +* +* Reports whether or not the selected PLL lost its lock since the last time this +* function was called. Clears the lost lock indicator. +* +* \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. +* +* \return 0 = didn't lose lock, 1 = lost lock, 0xFF = invalid clock path number +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_PllLostLock(uint32_t clkPath) +{ + uint32_t retval = 0xFFul; /* invalid clock path number */ + if ((clkPath != 0ul) && (clkPath <= SRSS_NUM_PLL)) + { + retval = _FLD2VAL(SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED, SRSS->CLK_PLL_STATUS[clkPath - 1ul]); + /* write a 1 to clear the unlock occurred bit */ + SRSS->CLK_PLL_STATUS[clkPath - 1ul] = _VAL2FLD(SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED, 1u); + } + return (retval); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PllDisable +****************************************************************************//** +* +* Disables the selected PLL. +* +* \param clkPath Selects which PLL to disable. 1 is the first PLL; 0 is invalid. +* +* \return Error / status code:
+* CY_SYSCLK_SUCCESS - PLL successfully disabled
+* CY_SYSCLK_BAD_PARAM - invalid clock path number +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_PllDisable(uint32_t clkPath) +{ + uint32_t retval = CY_SYSCLK_BAD_PARAM; + if ((clkPath != 0ul) && (clkPath <= SRSS_NUM_PLL)) + { + SRSS->CLK_PLL_CONFIG[clkPath - 1ul] &= ~_VAL2FLD(SRSS_CLK_PLL_CONFIG_ENABLE, 1u); /* 0 = disable */ + retval = CY_SYSCLK_SUCCESS; + } + return (retval); +} +/** \} group_sysclk_pll */ + + +/** +* \addtogroup group_sysclk_ilo +* \{ +*/ + +/* ========================================================================== */ +/* =========================== ILO SECTION ============================ */ +/* ========================================================================== */ +/** ILO trim modes */ +typedef enum +{ + CY_SYSCLK_ILO_TRIM_BLOCKING = 0u, /**< Function doesn't return until trim completes. */ + CY_SYSCLK_ILO_TRIM_NONBLOCKING = 1u /**< Function returns immediately, must be called multiple times until it is finished. */ +} cy_en_ilo_trim_modes_t; + +/******************************************************************************* +* Function Name: Cy_SysClk_IloEnable +****************************************************************************//** +* +* Enables the ILO. +* +* \note The watchdog timer (WDT) must be unlocked before calling this function. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_IloEnable(void) +{ + SRSS->CLK_ILO_CONFIG |= _VAL2FLD(SRSS_CLK_ILO_CONFIG_ENABLE, 1u); /* 1 = enable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_IloDisable +****************************************************************************//** +* +* Disables the ILO. ILO can't be disabled if WDT is enabled. +* +* \note The watchdog timer (WDT) must be unlocked before calling this function. +* Do not call this function if the WDT is enabled, because the WDT is clocked by +* the ILO. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_IloDisable(void) +{ + SRSS->CLK_ILO_CONFIG &= ~_VAL2FLD(SRSS_CLK_ILO_CONFIG_ENABLE, 1u); /* 0 = disable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_IloHibernateOn +****************************************************************************//** +* +* Controls whether the ILO stays on during a hibernate, or through an XRES or +* brown-out detect (BOD) event. +* +* \param on +* 1 = ILO stays on during hibernate or across XRES/BOD. 0 = ILO turns off for +* hibernate or XRES/BOD. +* +* \note Writes to the register/bit are ignored if the watchdog (WDT) is locked. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on) +{ + CY_SYSCLK_CLR_SET(SRSS->CLK_ILO_CONFIG, SRSS_CLK_ILO_CONFIG_HVILO_BACKUP, (uint32_t)on); +} +/** \} group_sysclk_ilo */ + + +/** +* \addtogroup group_sysclk_pilo +* \{ +*/ + +/* ========================================================================== */ +/* =========================== PILO SECTION =========================== */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_PiloEnable +****************************************************************************//** +* +* Enables the PILO. +* +* \note Requires 1 msec, for delay between enabling the PILO and releasing the +* PILO reset. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PiloEnable(void) +{ + SRSS->CLK_PILO_CONFIG |= _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_EN, 1u); /* 1 = enable */ + Cy_SysLib_Delay(1/*msec*/); + /* release the reset and enable clock output */ + SRSS->CLK_PILO_CONFIG |= (_VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_RESET_N, 1u) | + _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_CLK_EN, 1u)); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PiloDisable +****************************************************************************//** +* +* Disables the PILO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PiloDisable(void) +{ + /* Clear PILO_EN, PILO_RESET_N, and PILO_CLK_EN bitfields. This disables the + PILO and holds the PILO in a reset state. */ + SRSS->CLK_PILO_CONFIG &= ~(_VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_EN, 1u) | + _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_RESET_N, 1u) | + _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_CLK_EN, 1u));} +/** \} group_sysclk_pilo */ + + +/** +* \addtogroup group_sysclk_calclk +* \{ +*/ + +/* ========================================================================== */ +/* ==================== CLOCK MEASUREMENT SECTION ===================== */ +/* ========================================================================== */ +/** Defines all possible clock sources. */ +typedef enum +{ + CY_SYSCLK_MEAS_CLK_ILO = 1u, + CY_SYSCLK_MEAS_CLK_WCO = 2u, + CY_SYSCLK_MEAS_CLK_ALTLF = 4u, + CY_SYSCLK_MEAS_CLK_IMO = 6u, + CY_SYSCLK_MEAS_CLK_PILO = 8u, + CY_SYSCLK_MEAS_CLK_FAST_CLKS = 0x100u, + CY_SYSCLK_MEAS_CLK_ECO = 0x101u, + CY_SYSCLK_MEAS_CLK_EXT = 0x102u, + CY_SYSCLK_MEAS_CLK_ALTHF = 0x103u, + CY_SYSCLK_MEAS_CLK_PATH_CLKS = 0x500u, + CY_SYSCLK_MEAS_CLK_PATH0 = 0x500u, + CY_SYSCLK_MEAS_CLK_PATH1 = 0x501u, + CY_SYSCLK_MEAS_CLK_PATH2 = 0x502u, + CY_SYSCLK_MEAS_CLK_PATH3 = 0x503u, + CY_SYSCLK_MEAS_CLK_PATH4 = 0x504u, + CY_SYSCLK_MEAS_CLK_PATH5 = 0x505u, + CY_SYSCLK_MEAS_CLK_PATH6 = 0x506u, + CY_SYSCLK_MEAS_CLK_PATH7 = 0x507u, + CY_SYSCLK_MEAS_CLK_PATH8 = 0x508u, + CY_SYSCLK_MEAS_CLK_PATH9 = 0x509u, + CY_SYSCLK_MEAS_CLK_PATH10 = 0x50Au, + CY_SYSCLK_MEAS_CLK_PATH11 = 0x50Bu, + CY_SYSCLK_MEAS_CLK_PATH12 = 0x50Cu, + CY_SYSCLK_MEAS_CLK_PATH13 = 0x50Du, + CY_SYSCLK_MEAS_CLK_PATH14 = 0x50Eu, + CY_SYSCLK_MEAS_CLK_PATH15 = 0x50Fu, + CY_SYSCLK_MEAS_CLK_HF_CLKS = 0x600u, + CY_SYSCLK_MEAS_CLK_HFCLK0 = 0x600u, + CY_SYSCLK_MEAS_CLK_HFCLK1 = 0x601u, + CY_SYSCLK_MEAS_CLK_HFCLK2 = 0x602u, + CY_SYSCLK_MEAS_CLK_HFCLK3 = 0x603u, + CY_SYSCLK_MEAS_CLK_HFCLK4 = 0x604u, + CY_SYSCLK_MEAS_CLK_HFCLK5 = 0x605u, + CY_SYSCLK_MEAS_CLK_HFCLK6 = 0x606u, + CY_SYSCLK_MEAS_CLK_HFCLK7 = 0x607u, + CY_SYSCLK_MEAS_CLK_HFCLK8 = 0x608u, + CY_SYSCLK_MEAS_CLK_HFCLK9 = 0x609u, + CY_SYSCLK_MEAS_CLK_HFCLK10 = 0x60Au, + CY_SYSCLK_MEAS_CLK_HFCLK11 = 0x60Bu, + CY_SYSCLK_MEAS_CLK_HFCLK12 = 0x60Cu, + CY_SYSCLK_MEAS_CLK_HFCLK13 = 0x60Du, + CY_SYSCLK_MEAS_CLK_HFCLK14 = 0x60Eu, + CY_SYSCLK_MEAS_CLK_HFCLK15 = 0x60Fu, + CY_SYSCLK_MEAS_CLK_LAST_CLK = 0x610u +} cy_en_meas_clks_t; + +/******************************************************************************* +* Function Name: Cy_SysClk_InitClkMeasurementCounters +****************************************************************************//** +* +* Initializes clock measurement counters. +* Measurement counters allow you to measure one clock (clock2) versus another +* clock (clock1). This is done with two hardware counters. One counter (counter1), +* which is clocked off of clock1, is loaded with an initial value and it counts down. +* A second counter (counter2), which is clocked off of clock2, counts up until +* the first counter is done counting down. +* The frequency of clock2 can be determined with the following equation: +* clock2 frequency = (count2/count1) * clock1 frequency +* +* \param clock1 selects which clock is used as the measurement clock +* +* \param clock1FreqHz the frequency of clock1 in Hz +* +* \param count1 sets the initial value for count1 +* +* \param clock2 selects the clock that will be measured by clock1 +* +* \return Error / status code:
+* CY_SYSCLK_INVALID_STATE if already doing a measurement
+* CY_SYSCLK_BAD_PARAM if invalid clock input parameter
+* else CY_SYSCLK_SUCCESS +* +*******************************************************************************/ +uint32_t Cy_SysClk_InitClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t clock1FreqHz, + uint32_t count1, cy_en_meas_clks_t clock2); + +/******************************************************************************* +* Function Name: Cy_SysClk_StartClkMeasurementCounters +****************************************************************************//** +* +* Starts the calibration counters. +* +* \return Error / status code:
+* CY_SYSCLK_INVALID_STATE if already doing a measurement
+* else CY_SYSCLK_SUCCESS +* +* \note Cy_SysClk_InitClkMeasurementCounters() must have been called previously. +*******************************************************************************/ +uint32_t Cy_SysClk_StartClkMeasurementCounters(void); + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkMeasurementCountersDone +****************************************************************************//** +* +* Checks if the calibration counters are done +* +* \return Status of calibration counters:
+* CY_SYSCLK_FINISHED if done
+* CY_SYSCLK_STARTED if not +* +*******************************************************************************/ +__STATIC_INLINE int32_t Cy_SysClk_ClkMeasurementCountersDone(void) +{ + return ((_FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS->CLK_CAL_CNT1) == 0ul/*0 = not done*/) ? + CY_SYSCLK_STARTED : CY_SYSCLK_FINISHED); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkMeasurementCountersGetClock2Freq +****************************************************************************//** +* +* Returns the frequency of clock 2 in Hz. The following equation is used: +* clock2 frequency = (count2/count1) * clock1 frequency +* +* \return Frequency of clock 2 in Hz +* +* \note This must only be called if the counters are done. +*******************************************************************************/ +uint32_t Cy_SysClk_ClkMeasurementCountersGetClock2Freq(void); +/** \} group_sysclk_calclk */ + + +/** +* \addtogroup group_sysclk_trim +* \{ +*/ + +/* ========================================================================== */ +/* ========================== TRIM SECTION ============================ */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_IloTrim +****************************************************************************//** +* +* Trims the ILO to be as close to 32,768 Hz as possible. The clock measurement +* counters should be used to obtain the current frequency of the ILO. This +* frequency should then be passed into this function. This function will then +* use this information to trim the ILO as close as possible to 32,768 Hz. +* +* \param iloFreq current ILO frequency as measured by the measurement counters +* +* \return The achieved ILO frequency in Hz +* +* \note The watchdog timer (WDT) must be unlocked before calling this function. +*******************************************************************************/ +uint32_t Cy_SysClk_IloTrim(uint32_t iloFreq); + +/******************************************************************************* +* Function Name: Cy_SysClk_PiloTrim +****************************************************************************//** +* +* Trims the PILO to be as close to 32,768 Hz as possible. The clock measurement +* counters should be used to obtain the current frequency of the PILO. This +* frequency should then be passed into this function. This function will then +* use this information to trim the PILO as close as possible to 32,768Hz. +* +* \param piloFreq current PILO frequency as measured by the measurement counters +* +* \return The achieved PILO frequency in Hz +* +*******************************************************************************/ +uint32_t Cy_SysClk_PiloTrim(uint32_t piloFreq); + +/** \} group_sysclk_trim */ + + +/** +* \addtogroup group_sysclk_wco +* \{ +*/ + +/* ========================================================================== */ +/* =========================== WCO SECTION ============================ */ +/* ========================================================================== */ +/** WCO bypass modes */ +typedef enum +{ + CY_SYSCLK_WCO_NOT_BYPASSED = 0u, /**< WCO is not bypassed crystal is used */ + CY_SYSCLK_WCO_BYPASSED = 1u /**< WCO is bypassed external clock must be supplied on XTAL pin */ +} cy_en_wco_bypass_modes_t; + +/** WCO CSV supervisor clock selections */ +typedef enum +{ + CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO, + CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF, + CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO +} cy_en_wco_csv_supervisor_clock_t; + +/** +* Clock supervisor clock loss window. There must be one clock of the supervised +* clock within this many clocks of the supervising clock. +* See registers CLK_CSV_HF_CTL and CLK_CSV_WCO_CTL, bitfield CSV_LOSS_WINDOW. +*/ +typedef enum +{ + CY_SYSCLK_CSV_LOSS_4_CYCLES = 0u, /**< 1 clock must be seen within 4 cycles of the supervising clock. */ + CY_SYSCLK_CSV_LOSS_8_CYCLES = 1u, /**< 1 clock must be seen within 8 cycles of the supervising clock. */ + CY_SYSCLK_CSV_LOSS_16_CYCLES = 2u, /**< 1 clock must be seen within 16 cycles of the supervising clock. */ + CY_SYSCLK_CSV_LOSS_32_CYCLES = 3u, /**< 1 clock must be seen within 32 cycles of the supervising clock. */ + CY_SYSCLK_CSV_LOSS_64_CYCLES = 4u, /**< 1 clock must be seen within 64 cycles of the supervising clock. */ + CY_SYSCLK_CSV_LOSS_128_CYCLES = 5u, /**< 1 clock must be seen within 128 cycles of the supervising clock. */ + CY_SYSCLK_CSV_LOSS_256_CYCLES = 6u, /**< 1 clock must be seen within 256 cycles of the supervising clock. */ + CY_SYSCLK_CSV_LOSS_512_CYCLES = 7u /**< 1 clock must be seen within 512 cycles of the supervising clock. */ +} cy_en_csv_loss_window_t; + +/** +* Clock supervisor error actions. See register CLK_CSV_HF_CTL[CSV_FREQ_ACTION and CSV_LOSS_ACTION]. +*/ +typedef enum +{ + CY_SYSCLK_CSV_ERROR_IGNORE = 0u, /**< Ignore the error reported by the clock supervisor. */ + CY_SYSCLK_CSV_ERROR_FAULT = 1u, /**< Trigger a fault when an error is reported by the clock supervisor. */ + CY_SYSCLK_CSV_ERROR_RESET = 2u, /**< Trigger a reset when an error is reported by the clock supervisor. */ + CY_SYSCLK_CSV_ERROR_FAULT_RESET = 3u /**< Trigger a fault then reset when an error is reported by the supervisor. */ +} cy_en_csv_error_actions_t; + +/** +* This structure is used to configure the clock supervisor for the WCO. +*/ +typedef struct +{ + cy_en_wco_csv_supervisor_clock_t SupervisorClock; /**< supervisor clock selection */ + uint32_t enableLossDetection; /**< 1= enabled, 0= disabled. Note that if loss detection is enabled, writes to other register bits are ignored. */ + cy_en_csv_loss_window_t LossWindow; /**< \ref cy_en_csv_loss_window_t */ + cy_en_csv_error_actions_t LossAction; /**< \ref cy_en_csv_error_actions_t */ +} cy_stc_wco_csv_config_t; + +/******************************************************************************* +* Function Name: Cy_SysClk_WcoEnable +****************************************************************************//** +* +* Enables the WCO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_WcoEnable(void) +{ + BACKUP->CTL |= _VAL2FLD(BACKUP_CTL_WCO_EN, 1u); /* 1 = enable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_WcoDisable +****************************************************************************//** +* +* Disables the WCO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_WcoDisable(void) +{ + BACKUP->CTL &= ~_VAL2FLD(BACKUP_CTL_WCO_EN, 1u); /* 0 = disable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_WcoBypass +****************************************************************************//** +* +* Sets whether the WCO is bypassed or not. If it is bypassed then a 32-kHz clock +* must be provided on the wco_in pin. +* +* \param bypass \ref cy_en_wco_bypass_modes_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass) +{ + CY_SYSCLK_CLR_SET(BACKUP->CTL, BACKUP_CTL_WCO_BYPASS, bypass); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_WcoConfigureCsv +****************************************************************************//** +* +* Configure the WCO clock supervisor (CSV). +* +* \param config \ref cy_stc_wco_csv_config_t +* +* \note +* If loss detection is enabled, writes to other register bits are ignored. +* Therefore loss detection is disabled before writing the config structure +* members to the CTL register. Note that one of the config structure members is +* an enable bit. +*******************************************************************************/ +void Cy_SysClk_WcoConfigureCsv(const cy_stc_wco_csv_config_t *config); +/** \} group_sysclk_wco */ + + +/** +* \addtogroup group_sysclk_clk_hf +* \{ +*/ + +/* ========================================================================== */ +/* ======================== clk_hf[n] SECTION ========================= */ +/* ========================================================================== */ +/** +* Selects which hf_clk input, or root mux, to configure. +* See CLK_ROOT_SELECT registers, bits ROOT_MUX. +* Used with functions \ref Cy_SysClk_HfClockSetSource and \ref Cy_SysClk_HfClockGetSource. +*/ +typedef enum +{ + CY_SYSCLK_HFCLK_IN_CLKPATH0 = 0u, /**< hf_clk input is Clock Path 0 */ + CY_SYSCLK_HFCLK_IN_CLKPATH1 = 1u, /**< hf_clk input is Clock Path 1 */ + CY_SYSCLK_HFCLK_IN_CLKPATH2 = 2u, /**< hf_clk input is Clock Path 2 */ + CY_SYSCLK_HFCLK_IN_CLKPATH3 = 3u, /**< hf_clk input is Clock Path 3 */ + CY_SYSCLK_HFCLK_IN_CLKPATH4 = 4u, /**< hf_clk input is Clock Path 4 */ + CY_SYSCLK_HFCLK_IN_CLKPATH5 = 5u, /**< hf_clk input is Clock Path 5 */ + CY_SYSCLK_HFCLK_IN_CLKPATH6 = 6u, /**< hf_clk input is Clock Path 6 */ + CY_SYSCLK_HFCLK_IN_CLKPATH7 = 7u, /**< hf_clk input is Clock Path 7 */ + CY_SYSCLK_HFCLK_IN_CLKPATH8 = 8u, /**< hf_clk input is Clock Path 8 */ + CY_SYSCLK_HFCLK_IN_CLKPATH9 = 9u, /**< hf_clk input is Clock Path 9 */ + CY_SYSCLK_HFCLK_IN_CLKPATH10 = 10u, /**< hf_clk input is Clock Path 10 */ + CY_SYSCLK_HFCLK_IN_CLKPATH11 = 11u, /**< hf_clk input is Clock Path 11 */ + CY_SYSCLK_HFCLK_IN_CLKPATH12 = 12u, /**< hf_clk input is Clock Path 12 */ + CY_SYSCLK_HFCLK_IN_CLKPATH13 = 13u, /**< hf_clk input is Clock Path 13 */ + CY_SYSCLK_HFCLK_IN_CLKPATH14 = 14u, /**< hf_clk input is Clock Path 14 */ + CY_SYSCLK_HFCLK_IN_CLKPATH15 = 15u, /**< hf_clk input is Clock Path 15 */ +} cy_en_hf_clk_sources_t; + +/** +* hf_clk divider values. See CLK_ROOT_SELECT registers, bits ROOT_DIV. +* Used with functions \ref Cy_SysClk_HfClockSetDivider and \ref Cy_SysClk_HfClockGetDivider. +*/ +typedef enum +{ + CY_SYSCLK_HFCLK_NO_DIVIDE = 0u, /**< don't divide hf_clk. */ + CY_SYSCLK_HFCLK_DIVIDE_BY_2 = 1u, /**< divide hf_clk by 2 */ + CY_SYSCLK_HFCLK_DIVIDE_BY_4 = 2u, /**< divide hf_clk by 4 */ + CY_SYSCLK_HFCLK_DIVIDE_BY_8 = 3u /**< divide hf_clk by 8 */ +} cy_en_hf_clk_dividers_t; + +/** +* hf_clk clock supervisor input sources. See register CLK_CSV_HF_CTL[CSV_MUX]. +*/ +typedef enum +{ + CY_SYSCLK_HFCLK_CSV_SUPERVISOR_IMO = 0u, /**< Supervising clock is the IMO. */ + CY_SYSCLK_HFCLK_CSV_SUPERVISOR_EXT = 1u, /**< Supervising clock is the external clock */ + CY_SYSCLK_HFCLK_CSV_SUPERVISOR_ALTHF = 2u /**< Supervising clock is clk_althf */ +} cy_en_hfclk_csv_supervisor_clock_t; + +/** +* This structure is used to configure the clock supervisor for hf_clk. +*/ +typedef struct +{ + cy_en_hfclk_csv_supervisor_clock_t SupervisorClock; /**< \ref cy_en_hfclk_csv_supervisor_clock_t */ + uint32_t SupervisingWindow; /**< Number of supervising clock cycles */ + uint32_t enableFrquencyFaultDetection; /**< 1= enabled, 0= disabled */ + uint32_t FrequencyLowerLimit; /**< Lowest frequency in kHz that supervised clock can go */ + uint32_t FrequencyUpperLimit; /**< Highest frequency in kHz that supervised clock can go */ + cy_en_csv_error_actions_t FrequencyAction; /**< \ref cy_en_csv_error_actions_t */ + uint32_t enableLossDetection; /**< 1= enabled, 0= disabled */ + cy_en_csv_loss_window_t LossWindow; /**< \ref cy_en_csv_loss_window_t */ + cy_en_csv_error_actions_t LossAction; /**< \ref cy_en_csv_error_actions_t */ +} cy_stc_hf_csv_config_t; + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkHfEnable +****************************************************************************//** +* +* Enables the selected ClkHf. +* +* \param clkHf Selects which ClkHf to enable. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkHfEnable(uint32_t clkHf) +{ + SRSS->CLK_ROOT_SELECT[clkHf] |= _VAL2FLD(SRSS_CLK_ROOT_SELECT_ENABLE, 1ul); /* 1 = enable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkHfDisable +****************************************************************************//** +* +* Disables the selected ClkHf. +* +* \param clkHf Selects which ClkHf to enable. +* +* \note ClkHf[0] cannot be disabled. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkHfDisable(uint32_t clkHf) +{ + SRSS->CLK_ROOT_SELECT[clkHf] &= ~_VAL2FLD(SRSS_CLK_ROOT_SELECT_ENABLE, 1ul); /* 0 = disable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_HfClockSetSource +****************************************************************************//** +* +* Selects the source of the selected ClkHf. +* +* \param hfClk Which ClkHf mux to configure. +* +* \param source \ref cy_en_hf_clk_sources_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_HfClockSetSource(uint32_t hfClk, cy_en_hf_clk_sources_t source) +{ + CY_SYSCLK_CLR_SET(SRSS->CLK_ROOT_SELECT[hfClk], SRSS_CLK_ROOT_SELECT_ROOT_MUX, source); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_HfClockGetSource +****************************************************************************//** +* +* Reports the source of the selected ClkHf. +* +* \param hfClk selects which ClkHf to get the source of. +* +* \return \ref cy_en_hf_clk_sources_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_hf_clk_sources_t Cy_SysClk_HfClockGetSource(uint32_t hfClk) +{ + return (cy_en_hf_clk_sources_t)(_FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[hfClk])); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_HfClockSetDivider +****************************************************************************//** +* +* Sets the pre-divider for a ClkHf. +* +* \param hfClk selects which ClkHf divider to configure. +* +* \param divider \ref cy_en_hf_clk_dividers_t +* +* \note Also call \ref Cy_SysClk_HfClockSetSource to set the ClkHf source. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_HfClockSetDivider(uint32_t hfClk, cy_en_hf_clk_dividers_t divider) +{ + CY_SYSCLK_CLR_SET(SRSS->CLK_ROOT_SELECT[hfClk], SRSS_CLK_ROOT_SELECT_ROOT_DIV, divider); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_HfClockGetDivider +****************************************************************************//** +* +* Reports the pre-divider value for a ClkHf. +* +* \param hfClk selects which ClkHf to check divider of. +* +* \return \ref cy_en_hf_clk_dividers_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_hf_clk_dividers_t Cy_SysClk_HfClockGetDivider(uint32_t hfClk) +{ + return (cy_en_hf_clk_dividers_t)(_FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[hfClk])); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_HfClockConfigureCsv +****************************************************************************//** +* +* Configures the ClkHf clock supervisor (CSV). +* +* \param hfClk selects which ClkHf CSV to configure. +* +* \param config \ref cy_stc_hf_csv_config_t +* +* \note +* If loss detection is enabled, writes to other register bits are ignored. +* Therefore loss detection is disabled before writing the config structure +* members to the CTL register. Note that one of the config structure members is +* an enable bit. +*******************************************************************************/ +void Cy_SysClk_HfClockConfigureCsv(uint32_t hfClk, const cy_stc_hf_csv_config_t *config); +/** \} group_sysclk_clk_hf */ + + +/** +* \addtogroup group_sysclk_clk_fast +* \{ +*/ + +/* ========================================================================== */ +/* ========================= clk_fast SECTION ========================= */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_FastClkSetDivider +****************************************************************************//** +* +* Sets the clock divider for the fast clock, which sources the main processor. +* The source of this divider is hf_clk[0]. +* +* \param divider divider value between 0 and 255. +* Causes integer division of (divider value + 1), or division by 1 to 256. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_FastClkSetDivider(uint32_t divider) +{ + CY_SYSCLK_CLR_SET(CPUSS->CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, divider); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_FastClkGetDivider +****************************************************************************//** +* +* Returns the clock divider for the fast clock. +* +* \return The divider value for the fast clock. +* The integer division done is by (divider value + 1), or division by 1 to 256. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_FastClkGetDivider(void) +{ + return _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); +} +/** \} group_sysclk_clk_fast */ + + +/** +* \addtogroup group_sysclk_clk_peripheral +* \{ +*/ + +/* ========================================================================== */ +/* ======================== clk_peri SECTION ========================== */ +/* ========================================================================== */ +/** Programmable clock divider types */ +typedef enum +{ + CY_SYSCLK_DIV_8_BIT = 0u, /**< Divider Type is an 8 bit divider */ + CY_SYSCLK_DIV_16_BIT = 1u, /**< Divider Type is a 16 bit divider */ + CY_SYSCLK_DIV_16_5_BIT = 2u, /**< Divider Type is a 16.5 bit fractional divider */ + CY_SYSCLK_DIV_24_5_BIT = 3u /**< Divider Type is a 24.5 bit fractional divider */ +} cy_en_divider_types_t; + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriClkSetDivider +****************************************************************************//** +* +* Sets the clock divider for the peripheral clock tree. All peripheral clock +* dividers are sourced from this clock. Also the Cortex M0+ clock divider is +* sourced from this clock. The source of this divider is hf_clk[0] +* +* \param divider divider value between 0 and 255 +* Causes integer division of (divider value + 1), or division by 1 to 256. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PeriClkSetDivider(uint32_t divider) +{ + CY_SYSCLK_CLR_SET(CPUSS->CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, divider); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriClkGetDivider +****************************************************************************//** +* +* Returns the clock divider of peripheral (peri) clock +* +* \return The divider value. +* The integer division done is by (divider value + 1), or division by 1 to 256. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_PeriClkGetDivider(void) +{ + return _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphSetDivider +****************************************************************************//** +* +* Sets one of the programmable clock dividers. This is only used for integer +* dividers. Use \ref Cy_SysClk_PeriphSetFracDivider for setting factional dividers. +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t +* +* \param dividerNum the divider number. +* +* \param dividerValue divider value +* Causes integer division of (divider value + 1), or division by 1 to 256 +* (8-bit divider) or 1 to 65536 (16-bit divider). +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType, + uint32_t dividerNum, uint32_t dividerValue) +{ + switch(dividerType) + { + case CY_SYSCLK_DIV_8_BIT: + CY_SYSCLK_CLR_SET(PERI->DIV_8_CTL[dividerNum], PERI_DIV_8_CTL_INT8_DIV, dividerValue); + break; + case CY_SYSCLK_DIV_16_BIT: + CY_SYSCLK_CLR_SET(PERI->DIV_16_CTL[dividerNum], PERI_DIV_16_CTL_INT16_DIV, dividerValue); + break; + /* the following divider types are invalid for this function, and are ignored */ + case CY_SYSCLK_DIV_16_5_BIT: + case CY_SYSCLK_DIV_24_5_BIT: + default: + break; + } +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphGetDivider +****************************************************************************//** +* +* Returns the integer divider value for the specified divider. One works for +* integer dividers. Use \ref Cy_SysClk_PeriphGetFracDivider to get the fractional +* divider value +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t +* +* \param dividerNum specifies which divider of the selected type to configure +* +* \return The divider value. +* The integer division done is by (divider value + 1), or division by 1 to 256 +* (8-bit divider) or 1 to 65536 (16-bit divider). +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum) +{ + uint32_t retval = 0; /* returns 0 if invalid dividerType */ + + switch(dividerType) + { + case CY_SYSCLK_DIV_8_BIT: + retval = _FLD2VAL(PERI_DIV_8_CTL_INT8_DIV, PERI->DIV_8_CTL[dividerNum]); + break; + case CY_SYSCLK_DIV_16_BIT: + retval = _FLD2VAL(PERI_DIV_16_CTL_INT16_DIV, PERI->DIV_16_CTL[dividerNum]); + break; + /* the following divider types are invalid for this function, and result in an error return */ + case CY_SYSCLK_DIV_16_5_BIT: + case CY_SYSCLK_DIV_24_5_BIT: + default: + break; + } + + return retval; +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphSetFracDivider +****************************************************************************//** +* +* Sets one of the programmable clock dividers. This function should only be used +* for fractional clock dividers. +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t +* +* \param dividerNum specifies which divider of the selected type to configure +* +* \param dividerIntValue the integer divider value +* The source of the divider is peri_clk, which is a divided version of hf_clk[0]. +* The divider value causes integer division of (divider value + 1), or division +* by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider). +* +* \param dividerFracValue the fraction part of the divider +* The fractional divider can be 1-32, thus it divides the clock by 1/32 for each +* count. To divide the clock by 11/32nds set this value to 11. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, + uint32_t dividerIntValue, uint32_t dividerFracValue) +{ /* see CDT 238859 */ + switch(dividerType) + { + case CY_SYSCLK_DIV_16_5_BIT: + CY_SYSCLK_CLR_SET(PERI->DIV_16_5_CTL[dividerNum], PERI_DIV_16_5_CTL_INT16_DIV, dividerIntValue); + CY_SYSCLK_CLR_SET(PERI->DIV_16_5_CTL[dividerNum], PERI_DIV_16_5_CTL_FRAC5_DIV, dividerFracValue); + break; + case CY_SYSCLK_DIV_24_5_BIT: + CY_SYSCLK_CLR_SET(PERI->DIV_24_5_CTL[dividerNum], PERI_DIV_24_5_CTL_INT24_DIV, dividerIntValue); + CY_SYSCLK_CLR_SET(PERI->DIV_24_5_CTL[dividerNum], PERI_DIV_24_5_CTL_FRAC5_DIV, dividerFracValue); + break; + /* the following divider types are invalid for this function, and are ignored */ + case CY_SYSCLK_DIV_8_BIT: + case CY_SYSCLK_DIV_16_BIT: + default: + break; + } +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphGetFracDivider +****************************************************************************//** +* +* Reports the integer and fractional parts of the divider +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t +* +* \param dividerNum specifies which divider of the selected type to configure +* +* \param *dividerIntValue pointer to return integer divider value +* +* \param *dividerFracValue pointer to return fractional divider value +* +* \return None. Loads pointed-to variables. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, + uint32_t *dividerIntValue, uint32_t *dividerFracValue) +{ + switch(dividerType) + { + case CY_SYSCLK_DIV_16_5_BIT: + *dividerIntValue = _FLD2VAL(PERI_DIV_16_5_CTL_INT16_DIV, PERI->DIV_16_5_CTL[dividerNum]); + *dividerFracValue = _FLD2VAL(PERI_DIV_16_5_CTL_FRAC5_DIV, PERI->DIV_16_5_CTL[dividerNum]); + break; + case CY_SYSCLK_DIV_24_5_BIT: + *dividerIntValue = _FLD2VAL(PERI_DIV_24_5_CTL_INT24_DIV, PERI->DIV_24_5_CTL[dividerNum]); + *dividerFracValue = _FLD2VAL(PERI_DIV_24_5_CTL_FRAC5_DIV, PERI->DIV_24_5_CTL[dividerNum]); + break; + /* the following divider types are invalid for this function, and are ignored */ + case CY_SYSCLK_DIV_8_BIT: + case CY_SYSCLK_DIV_16_BIT: + default: + break; + } +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphAssignDivider +****************************************************************************//** +* +* Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB. +* +* \param ipBlock specifies ip block to connect the clock divider to. +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t +* +* \param dividerNum specifies which divider of the selected type to configure +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, + uint32_t dividerNum) +{ + PERI->CLOCK_CTL[ipBlock] = _VAL2FLD(PERI_CLOCK_CTL_TYPE_SEL, dividerType) | + _VAL2FLD(PERI_CLOCK_CTL_DIV_SEL, dividerNum); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphGetAssignedDivider +****************************************************************************//** +* +* Reports which clock divider is assigned to a selected IP block. +* +* \param ipBlock specifies ip block to connect the clock divider to. +* +* \return The divider type and #, where bits [7:6] = type, bits[5:0] = divider +* number within that type +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock) +{ + return PERI->CLOCK_CTL[ipBlock] & 0xFFul; /* bits [7:6] = TYPE_SEL, bits[5:0] = DIV_SEL */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphEnableDivider +****************************************************************************//** +* +* Enables the selected divider. +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t +* +* \param dividerNum specifies which divider of the selected type to configure +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum) +{ + PERI->DIV_CMD = _CLR_SET_FLD32U(PERI->DIV_CMD, PERI_DIV_CMD_TYPE_SEL, dividerType); + PERI->DIV_CMD = _CLR_SET_FLD32U(PERI->DIV_CMD, PERI_DIV_CMD_DIV_SEL, dividerNum); + PERI->DIV_CMD = _CLR_SET_FLD32U(PERI->DIV_CMD, PERI_DIV_CMD_ENABLE, 1ul); /* 1 = enable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphDisableDivider +****************************************************************************//** +* +* Disables the selected divider. +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. +* +* \param dividerNum specifies which divider of the selected type to configure. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum) +{ + PERI->DIV_CMD = _CLR_SET_FLD32U(PERI->DIV_CMD, PERI_DIV_CMD_TYPE_SEL, dividerType); + PERI->DIV_CMD = _CLR_SET_FLD32U(PERI->DIV_CMD, PERI_DIV_CMD_DIV_SEL, dividerNum); + PERI->DIV_CMD = _CLR_SET_FLD32U(PERI->DIV_CMD, PERI_DIV_CMD_DISABLE, 1); /* 1 = disable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphPhaseDisableDivider +****************************************************************************//** +* +* Disables a selected divider, preparatory to aligning it with another divider; +* see \ref Cy_SysClk_PeriphPhaseAlignDivider. +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. +* +* \param dividerNum specifies which divider of the selected type to configure. +* +* \note +* To phase-align a divider, do the following: +* 1. Call this function. +* 2. Call the appropriate Cy_SysClk_PeriphSet...Divider function to configure the +* divider. +* 3. Call Cy_SysClk_PeriphPhaseAlignDivider to enable the divider and do the phase +* alignment. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PeriphPhaseDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum) +{ + /* specify the divider and disable it */ + PERI->DIV_CMD = _VAL2FLD(PERI_DIV_CMD_DISABLE, 1u) /* 1 = disable */ | + _VAL2FLD(PERI_DIV_CMD_TYPE_SEL, dividerType) | + _VAL2FLD(PERI_DIV_CMD_DIV_SEL, dividerNum); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphPhaseAlignDivider +****************************************************************************//** +* +* First disables a selected divider (\ref Cy_SysClk_PeriphPhaseDisableDivider), +* then aligns that divider to another programmable divider, and enables the +* selected divider. +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. +* +* \param dividerNum specifies which divider of the selected type to configure. +* +* \param dividerTypePA type of divider to phase-align to; \ref cy_en_divider_types_t. +* +* \param dividerNumPA divider number of type specified to phase align to. +* +* \note +* To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA +* to 255. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_PeriphPhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, + cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA) +{ + /* first disable the divider that is to be phase-aligned */ + Cy_SysClk_PeriphPhaseDisableDivider(dividerType, dividerNum); + /* then specify the reference divider, and the divider, and enable the divider */ + PERI->DIV_CMD = _VAL2FLD(PERI_DIV_CMD_ENABLE, 1u) /* 1 = enable */ | + _VAL2FLD(PERI_DIV_CMD_PA_TYPE_SEL, dividerTypePA) | + _VAL2FLD(PERI_DIV_CMD_PA_DIV_SEL, dividerNumPA) | + _VAL2FLD(PERI_DIV_CMD_TYPE_SEL, dividerType) | + _VAL2FLD(PERI_DIV_CMD_DIV_SEL, dividerNum); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_PeriphGetFrequency +****************************************************************************//** +* +* Reports the frequency of the output of a given peripheral divider. +* +* \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t +* +* \param dividerNum specifies which divider of the selected type to configure +* +* \return The frequency, in Hz. +* +* \note +* The reported frequency may be zero, which indicates unknown. This happens if +* the source input is clk_ext, ECO, clk_althf, dsi_out, or clk_altlf. +* +*******************************************************************************/ +uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum); +/** \} group_sysclk_clk_peripheral */ + + +/** +* \addtogroup group_sysclk_clk_slow +* \{ +*/ + +/* ========================================================================== */ +/* ========================= clk_slow SECTION ========================= */ +/* ========================================================================== */ +/******************************************************************************* +* Function Name: Cy_SysClk_SlowClkSetDivider +****************************************************************************//** +* +* Sets the clock divider for the slow clock. The source of this clock is the +* peripheral clock (ClkPeri), which is sourced from hf_clk[0]. +* +* \param divider Divider value between 0 and 255. +* Causes integer division of (divider value + 1), or division by 1 to 256. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_SlowClkSetDivider(uint32_t divider) +{ + CY_SYSCLK_CLR_SET(CPUSS->CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, divider); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_SlowClkGetDivider +****************************************************************************//** +* +* Reports the divider value for the slow clock. +* +* \return The divider value. +* The integer division done is by (divider value + 1), or division by 1 to 256. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_SlowClkGetDivider(void) +{ + return _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL); +} +/** \} group_sysclk_clk_slow */ + + +/** +* \addtogroup group_sysclk_clk_lf +* \{ +*/ + +/* ========================================================================== */ +/* ========================== clk_lf SECTION ========================== */ +/* ========================================================================== */ +/** +* Low frequency (lf_clk) input sources. See CLK_SELECT register, LFCLK_SEL bits. +* Used with functions \ref Cy_SysClk_LfClkSetSource, and \ref Cy_SysClk_LfClkGetSource. +*/ +typedef enum +{ + CY_SYSCLK_LFCLK_IN_ILO = 0u, /**< lf_clk is sourced by the internal low speed oscillator (ILO) */ + CY_SYSCLK_LFCLK_IN_WCO = 1u, /**< lf_clk is sourced by the watch crystal oscillator (WCO) */ + CY_SYSCLK_LFCLK_IN_ALTLF = 2u, /**< lf_clk is sourced by the Alternate Low Frequency Clock (ALTLF) */ + CY_SYSCLK_LFCLK_IN_PILO = 3u /**< lf_clk is sourced by the precision low speed oscillator (PILO) */ +} cy_en_lfclk_input_sources_t; + + +/******************************************************************************* +* Function Name: Cy_SysClk_LfClkSetSource +****************************************************************************//** +* +* Sets the source for the low frequency clock(lf_clk). +* +* \param source \ref cy_en_lfclk_input_sources_t +* +* \note The watchdog timer (WDT) must be unlocked before calling this function. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_LfClkSetSource(cy_en_lfclk_input_sources_t source) +{ + CY_SYSCLK_CLR_SET(SRSS->CLK_SELECT, SRSS_CLK_SELECT_LFCLK_SEL, source); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_LfClkGetSource +****************************************************************************//** +* +* Reports the source for the low frequency clock (lf_clk). +* +* \return \ref cy_en_lfclk_input_sources_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_lfclk_input_sources_t Cy_SysClk_LfClkGetSource(void) +{ + return (cy_en_lfclk_input_sources_t)(_FLD2VAL(SRSS_CLK_SELECT_LFCLK_SEL, SRSS->CLK_SELECT)); +} +/** \} group_sysclk_clk_lf */ + + +/** +* \addtogroup group_sysclk_clk_timer +* \{ +*/ + +/* ========================================================================== */ +/* ======================== clk_timer SECTION ========================= */ +/* ========================================================================== */ +/** +* Timer clock (clk_timer) input sources. See CLK_TIMER_CTL register, TIMER_SEL +* and TIMER_HF0_DIV bits. Used with functions \ref Cy_SysClk_ClkTimerSetSource, and +* \ref Cy_SysClk_ClkTimerGetSource. +*/ +typedef enum +{ + CY_SYSCLK_CLKTIMER_IN_IMO = 0u, /**< clk_timer is sourced by the internal main oscillator (IMO) */ + CY_SYSCLK_CLKTIMER_IN_HF0_NODIV = 1u, /**< clk_timer is sourced by clk_hf0 undivided */ + CY_SYSCLK_CLKTIMER_IN_HF0_DIV2 = 0x101u, /**< clk_timer is sourced by clk_hf0 divided by 2 */ + CY_SYSCLK_CLKTIMER_IN_HF0_DIV4 = 0x201u, /**< clk_timer is sourced by clk_hf0 divided by 4 */ + CY_SYSCLK_CLKTIMER_IN_HF0_DIV8 = 0x301u /**< clk_timer is sourced by clk_hf0 divided by 8 */ +} cy_en_clktimer_input_sources_t; + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerSetSource +****************************************************************************//** +* +* Sets the source for the timer clock (clk_timer). The timer clock can be used +* as a source for SYSTICK and one or more of the energy profiler counters. +* +* \param source \ref cy_en_clktimer_input_sources_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_input_sources_t source) +{ + /* set both fields TIMER_SEL and TIMER_HF0_DIV with the same input value */ + SRSS->CLK_TIMER_CTL = + (SRSS->CLK_TIMER_CTL & ~(SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk | SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk)) | + (uint32_t)source; +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerGetSource +****************************************************************************//** +* +* Reports the source for the timer clock (clk_timer). +* +* \return \ref cy_en_clktimer_input_sources_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_clktimer_input_sources_t Cy_SysClk_ClkTimerGetSource(void) +{ + /* return both fields TIMER_SEL and TIMER_HF0_DIV as a single combined value */ + return (cy_en_clktimer_input_sources_t) + (SRSS->CLK_TIMER_CTL & (SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk | SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk)); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerSetDivider +****************************************************************************//** +* +* Sets the divider for the timer clock (clk_timer). +* +* \param divider Divider value; valid range is 0 to 255. Divides the selected +* source (\ref Cy_SysClk_ClkTimerSetSource) by the (value + 1). +* +* \note +* Do not change the divider value while the timer clock is enabled. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint32_t divider) +{ + CY_SYSCLK_CLR_SET(SRSS->CLK_TIMER_CTL, SRSS_CLK_TIMER_CTL_TIMER_DIV, divider); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerGetDivider +****************************************************************************//** +* +* Reports the divider value for the timer clock (clk_timer). +* +* \return The divider value +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_ClkTimerGetDivider(void) +{ + return (uint32_t)_FLD2VAL(SRSS_CLK_TIMER_CTL_TIMER_DIV, SRSS->CLK_TIMER_CTL); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerEnable +****************************************************************************//** +* +* Enables the timer clock (clk_timer). The timer clock can be used as a source +* for SYSTICK and one or more of the energy profiler counters. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void) +{ + SRSS->CLK_TIMER_CTL |= _VAL2FLD(SRSS_CLK_TIMER_CTL_ENABLE, 1ul); /* 1 = enable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerDisable +****************************************************************************//** +* +* Disables the timer clock (clk_timer). +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void) +{ + SRSS->CLK_TIMER_CTL &= ~_VAL2FLD(SRSS_CLK_TIMER_CTL_ENABLE, 1ul); /* 0 = disable */ +} +/** \} group_sysclk_clk_timer */ + +/** +* \addtogroup group_sysclk_clk_pump +* \{ +*/ + +/* ========================================================================== */ +/* ========================= clk_pump SECTION ========================= */ +/* ========================================================================== */ +/** +* Pump clock (clk_pump) input sources. See CLK_SELECT register, PUMP_SEL bits. +* Used with functions \ref Cy_SysClk_ClkPumpSetSource, and +* \ref Cy_SysClk_ClkPumpGetSource. +*/ +typedef enum +{ + CY_SYSCLK_PUMP_IN_CLKPATH0, /**< Pump clock input is clock path 0 */ + CY_SYSCLK_PUMP_IN_CLKPATH1, /**< Pump clock input is clock path 1 */ + CY_SYSCLK_PUMP_IN_CLKPATH2, /**< Pump clock input is clock path 2 */ + CY_SYSCLK_PUMP_IN_CLKPATH3, /**< Pump clock input is clock path 3 */ + CY_SYSCLK_PUMP_IN_CLKPATH4, /**< Pump clock input is clock path 4 */ + CY_SYSCLK_PUMP_IN_CLKPATH5, /**< Pump clock input is clock path 5 */ + CY_SYSCLK_PUMP_IN_CLKPATH6, /**< Pump clock input is clock path 6 */ + CY_SYSCLK_PUMP_IN_CLKPATH7, /**< Pump clock input is clock path 7 */ + CY_SYSCLK_PUMP_IN_CLKPATH8, /**< Pump clock input is clock path 8 */ + CY_SYSCLK_PUMP_IN_CLKPATH9, /**< Pump clock input is clock path 9 */ + CY_SYSCLK_PUMP_IN_CLKPATH10, /**< Pump clock input is clock path 10 */ + CY_SYSCLK_PUMP_IN_CLKPATH11, /**< Pump clock input is clock path 11 */ + CY_SYSCLK_PUMP_IN_CLKPATH12, /**< Pump clock input is clock path 12 */ + CY_SYSCLK_PUMP_IN_CLKPATH13, /**< Pump clock input is clock path 13 */ + CY_SYSCLK_PUMP_IN_CLKPATH14, /**< Pump clock input is clock path 14 */ + CY_SYSCLK_PUMP_IN_CLKPATH15 /**< Pump clock input is clock path 15 */ +} cy_en_clkpump_input_sources_t; + +/** +* Pump clock (clk_pump) divide options. See CLK_SELECT register, PUMP_DIV bits. +* Used with functions \ref Cy_SysClk_ClkPumpSetDivider, and +* \ref Cy_SysClk_ClkPumpGetDivider. +*/ +typedef enum +{ + CY_SYSCLK_PUMP_NO_DIV, /**< No division on pump clock */ + CY_SYSCLK_PUMP_DIV_2, /**< Pump clock divided by 2 */ + CY_SYSCLK_PUMP_DIV_4, /**< Pump clock divided by 4 */ + CY_SYSCLK_PUMP_DIV_8, /**< Pump clock divided by 8 */ + CY_SYSCLK_PUMP_DIV_16 /**< Pump clock divided by 16 */ +} cy_en_clkpump_divide_t; + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpSetSource +****************************************************************************//** +* +* Sets the source for the pump clock (clk_pump). The pump clock can be used for +* the analog pumps in the CTBm block. +* +* \param source \ref cy_en_clkpump_input_sources_t +* +* \note +* Do not change the source while the pump clock is enabled. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_input_sources_t source) +{ + CY_SYSCLK_CLR_SET(SRSS->CLK_SELECT, SRSS_CLK_SELECT_PUMP_SEL, source); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpGetSource +****************************************************************************//** +* +* Reports the source for the pump clock (clk_pump). +* +* \return \ref cy_en_clkpump_input_sources_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_clkpump_input_sources_t Cy_SysClk_ClkPumpGetSource(void) +{ + return (cy_en_clkpump_input_sources_t)_FLD2VAL(SRSS_CLK_SELECT_PUMP_SEL, SRSS->CLK_SELECT); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpSetDivider +****************************************************************************//** +* +* Sets the divider of the pump clock (clk_pump). +* +* \param divider \ref cy_en_clkpump_divide_t +* +* \note +* Do not change the divider value while the pump clock is enabled. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider) +{ + CY_SYSCLK_CLR_SET(SRSS->CLK_SELECT, SRSS_CLK_SELECT_PUMP_DIV, divider); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpGetDivider +****************************************************************************//** +* +* Reports the divider value for the pump clock (clk_pump). +* +* \return \ref cy_en_clkpump_divide_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void) +{ + return (cy_en_clkpump_divide_t)_FLD2VAL(SRSS_CLK_SELECT_PUMP_DIV, SRSS->CLK_SELECT); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpEnable +****************************************************************************//** +* +* Enables the pump clock (clk_pump). The pump clock can be used for the analog +* pumps in the CTBm block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void) +{ + SRSS->CLK_SELECT |= _VAL2FLD(SRSS_CLK_SELECT_PUMP_ENABLE, 1ul); /* 1 = enable */ +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpDisable +****************************************************************************//** +* +* Disables the pump clock (clk_pump). +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void) +{ + SRSS->CLK_SELECT &= ~_VAL2FLD(SRSS_CLK_SELECT_PUMP_ENABLE, 1ul); /* 0 = disable */ +} +/** \} group_sysclk_clk_pump */ + +/** +* \addtogroup group_sysclk_clk_bak +* \{ +*/ + +/* ========================================================================== */ +/* ========================== clk_bak SECTION ========================= */ +/* ========================================================================== */ +/** +* Backup domain clock (clk_bak) input sources. See BACKUP->CTL register, +* CLK_SEL bits. Used with functions \ref Cy_SysClk_ClkBakSetSource, and +* \ref Cy_SysClk_ClkBakGetSource. +*/ +typedef enum +{ + CY_SYSCLK_BAK_IN_WCO, /**< Backup domain clock input is WCO */ + CY_SYSCLK_BAK_IN_CLKLF /**< Backup domain clock input is clk_lf */ +} cy_en_clkbak_input_sources_t; + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkBakSetSource +****************************************************************************//** +* +* Sets the source for the backup domain clock (clk_bak). +* +* \param source \ref cy_en_clkbak_input_sources_t +* +* \note +* Clk_lf is not available in all power modes. For this reason, WCO is the +* preferred source. If the WCO is routed through the clk_lf multiplexer +* (see \ref Cy_SysClk_LfClkSetSource), select WCO directly - do not select clk_lf. +*******************************************************************************/ +__STATIC_INLINE void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_input_sources_t source) +{ + CY_SYSCLK_CLR_SET(BACKUP->CTL, BACKUP_CTL_CLK_SEL, source); +} + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkBakGetSource +****************************************************************************//** +* +* Reports the source for the backup domain clock (clk_bak). +* +* \return \ref cy_en_clkbak_input_sources_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_clkbak_input_sources_t Cy_SysClk_ClkBakGetSource(void) +{ + return (cy_en_clkbak_input_sources_t)_FLD2VAL(BACKUP_CTL_CLK_SEL, BACKUP->CTL); +} + +/** \} group_sysclk_clk_bak */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* __CY_SYSCLK_H__ */ + +/** \} group_sysclk */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysint/cy_sysint.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysint/cy_sysint.c new file mode 100644 index 0000000000..cb724ba75c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysint/cy_sysint.c @@ -0,0 +1,369 @@ +/***************************************************************************//** +* \file +* \version 1.0 +* +* \brief +* Provides an API implementation of the sysint driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_sysint.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_SysInt_Init +****************************************************************************//** +* +* \brief Initializes the referenced interrupt by setting the priority and the +* interrupt vector. Note that the interrupt vector will only be relocated if the +* vector table was moved to __ramVectors in SRAM. Otherwise it is ignored. +* +* Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) +* to enable it. For CM0+, this function also configures the interrupt mux +* connected to the NVIC. Use the CMSIS core function +* NVIC_EnableIRQ(config.intrCm0p) to enable it. +* +* \param config +* Interrupt configuration structure +* +* \param userIsr +* Address of the ISR +* +*******************************************************************************/ +cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr) +{ + cy_en_sysint_status_t status = CY_SYSINT_SUCCESS; + + if(NULL != config) + { + #if (CY_CPU_CORTEX_M0P) + if (config->intrSrc < 0) + { + NVIC_SetPriority(config->intrSrc, config->intrPriority); + } + else + { + /* Configure the interrupt mux */ + Cy_SysInt_SetIntSource(config); + NVIC_SetPriority((IRQn_Type)(config->intrCm0p), config->intrPriority); + } + #else + /* Set the priority */ + NVIC_SetPriority(config->intrSrc, config->intrPriority); + #endif + + /* Only set the new vector if it was moved to __ramVectors */ + if (SCB->VTOR == (uint32_t)&__ramVectors) + { + (void)Cy_SysInt_SetVector(config, userIsr); + } + } + else + { + status = CY_SYSINT_BAD_PARAM; + } + + return(status); +} + + +#if CY_CPU_CORTEX_M0P || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_SysInt_SetIntSource +****************************************************************************//** +* +* \brief Configures the interrupt mux for the specified CM0+ NVIC channel. +* +* Setting this value to 240 disconnects the interrupt source and will +* effectively deactivate the interrupt. +* +* \param config +* Interrupt configuration structure. This must be a positive number. +* +*******************************************************************************/ +void Cy_SysInt_SetIntSource(const cy_stc_sysint_t* config) +{ + /* Calculation of variables and masks */ + uint8_t intrMux = config->intrCm0p; + uint8_t regPos = intrMux >> CY_SYSINT_CM0P_MUX_SHIFT; + uint8_t bitPos = (intrMux - (regPos << CY_SYSINT_CM0P_MUX_SHIFT)) << CY_SYSINT_CM0P_MUX_SCALE; + uint32_t bitMask = (uint32_t)(CY_SYSINT_CM0P_MUX_MASK << bitPos); + uint32_t bitMaskClr = (uint32_t)(~bitMask); + uint32_t bitMaskSet = ((config->intrSrc << bitPos) & bitMask); + + uint32_t tempReg; + + switch(regPos) + { + case CY_SYSINT_CM0P_MUX0: + tempReg = CPUSS->CM0_INT_CTL0 & bitMaskClr; + CPUSS->CM0_INT_CTL0 = tempReg | bitMaskSet; + break; + case CY_SYSINT_CM0P_MUX1: + tempReg = CPUSS->CM0_INT_CTL1 & bitMaskClr; + CPUSS->CM0_INT_CTL1 = tempReg | bitMaskSet; + break; + case CY_SYSINT_CM0P_MUX2: + tempReg = CPUSS->CM0_INT_CTL2 & bitMaskClr; + CPUSS->CM0_INT_CTL2 = tempReg | bitMaskSet; + break; + case CY_SYSINT_CM0P_MUX3: + tempReg = CPUSS->CM0_INT_CTL3 & bitMaskClr; + CPUSS->CM0_INT_CTL3 = tempReg | bitMaskSet; + break; + case CY_SYSINT_CM0P_MUX4: + tempReg = CPUSS->CM0_INT_CTL4 & bitMaskClr; + CPUSS->CM0_INT_CTL4 = tempReg | bitMaskSet; + break; + case CY_SYSINT_CM0P_MUX5: + tempReg = CPUSS->CM0_INT_CTL5 & bitMaskClr; + CPUSS->CM0_INT_CTL5 = tempReg | bitMaskSet; + break; + case CY_SYSINT_CM0P_MUX6: + tempReg = CPUSS->CM0_INT_CTL6 & bitMaskClr; + CPUSS->CM0_INT_CTL6 = tempReg | bitMaskSet; + break; + case CY_SYSINT_CM0P_MUX7: + tempReg = CPUSS->CM0_INT_CTL7 & bitMaskClr; + CPUSS->CM0_INT_CTL7 = tempReg | bitMaskSet; + break; + default: + break; + } +} + + +/******************************************************************************* +* Function Name: Cy_SysInt_GetIntSource +****************************************************************************//** +* +* \brief Gets the interrupt source of CM0+ NVIC channel. +* +* \return +* Interrupt source. A returned value of 240 denotes that the interrupt source +* is disconnected. +* +*******************************************************************************/ +uint32_t Cy_SysInt_GetIntSource(IRQn_CM0P_Type muxSel) +{ + /* Calculation of variables */ + uint8_t regPos = muxSel >> CY_SYSINT_CM0P_MUX_SHIFT; + uint8_t bitPos = (muxSel - (regPos << CY_SYSINT_CM0P_MUX_SHIFT)) << CY_SYSINT_CM0P_MUX_SCALE; + uint32_t bitMask = (uint32_t)(CY_SYSINT_CM0P_MUX_MASK << bitPos); + + uint32_t tempReg; + + switch(regPos) + { + case CY_SYSINT_CM0P_MUX0: + tempReg = (uint32_t)((CPUSS->CM0_INT_CTL0 & bitMask) >> bitPos); + break; + case CY_SYSINT_CM0P_MUX1: + tempReg = (uint32_t)((CPUSS->CM0_INT_CTL1 & bitMask) >> bitPos); + break; + case CY_SYSINT_CM0P_MUX2: + tempReg = (uint32_t)((CPUSS->CM0_INT_CTL2 & bitMask) >> bitPos); + break; + case CY_SYSINT_CM0P_MUX3: + tempReg = (uint32_t)((CPUSS->CM0_INT_CTL3 & bitMask) >> bitPos); + break; + case CY_SYSINT_CM0P_MUX4: + tempReg = (uint32_t)((CPUSS->CM0_INT_CTL4 & bitMask) >> bitPos); + break; + case CY_SYSINT_CM0P_MUX5: + tempReg = (uint32_t)((CPUSS->CM0_INT_CTL5 & bitMask) >> bitPos); + break; + case CY_SYSINT_CM0P_MUX6: + tempReg = (uint32_t)((CPUSS->CM0_INT_CTL6 & bitMask) >> bitPos); + break; + case CY_SYSINT_CM0P_MUX7: + tempReg = (uint32_t)((CPUSS->CM0_INT_CTL7 & bitMask) >> bitPos); + break; + default: + tempReg = CY_SYSINT_CM0P_MUX_ERROR; + break; + } + return tempReg; +} +#endif + +/******************************************************************************* +* Function Name: Cy_SysInt_GetState +****************************************************************************//** +* +* \brief Gets the enabled/disabled state of the Interrupt. +* +* For CM0+, this function returns the state of the CM0+ interrupt mux output +* feeding into the NVIC. +* +* \param config +* Interrupt configuration structure +* +* \return +* 1 if enabled, 0 if disabled +* +*******************************************************************************/ +uint32_t Cy_SysInt_GetState(const cy_stc_sysint_t* config) +{ + #if CY_CPU_CORTEX_M0P + if (config->intrSrc < 0) + { + return (*(NVIC->ISER) >> config->intrSrc) & CY_SYSINT_STATE_MASK; + } + else + { + return (*(NVIC->ISER) >> config->intrCm0p) & CY_SYSINT_STATE_MASK; + } + #else + return (*(NVIC->ISER) >> config->intrSrc) & CY_SYSINT_STATE_MASK; + #endif +} + + +/******************************************************************************* +* Function Name: Cy_SysInt_SetVector +****************************************************************************//** +* +* \brief Changes the ISR vector for the Interrupt. +* +* For CM0+, this function sets the interrupt vector for the interrupt mux +* output feeding into the NVIC. +* +* Note that this function relies on the assumption that the vector table is +* relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will +* return the address of the default ISR location in Flash vector table. +* +* \param config +* Interrrupt configuration structure +* +* \param userIsr +* Address of the ISR to set in the interrupt vector table +* +* \return +* Previous address of the ISR in the interrupt vector table, before the +* function call +* +*******************************************************************************/ +cy_israddress Cy_SysInt_SetVector(const cy_stc_sysint_t* config, cy_israddress userIsr) +{ + cy_israddress prevIsr; + + #if CY_CPU_CORTEX_M0P + /* Only set the new vector if it was moved to __ramVectors */ + if (SCB->VTOR == (uint32_t)&__ramVectors) + { + if (config->intrSrc < 0) + { + prevIsr = __ramVectors[CY_INT_IRQ_BASE + config->intrSrc]; + __ramVectors[CY_INT_IRQ_BASE + config->intrSrc] = userIsr; + } + else + { + prevIsr = __ramVectors[CY_INT_IRQ_BASE + config->intrCm0p]; + __ramVectors[CY_INT_IRQ_BASE + config->intrCm0p] = userIsr; + } + } + else + { + if (config->intrSrc < 0) + { + prevIsr = __Vectors[CY_INT_IRQ_BASE + config->intrSrc]; + } + else + { + prevIsr = __Vectors[CY_INT_IRQ_BASE + config->intrCm0p]; + } + } + #else + /* Only set the new vector if it was moved to __ramVectors */ + if (SCB->VTOR == (uint32_t)&__ramVectors) + { + prevIsr = __ramVectors[CY_INT_IRQ_BASE + config->intrSrc]; + __ramVectors[CY_INT_IRQ_BASE + config->intrSrc] = userIsr; + } + else + { + prevIsr = __Vectors[CY_INT_IRQ_BASE + config->intrSrc]; + } + #endif + + return prevIsr; +} + + +/******************************************************************************* +* Function Name: Cy_SysInt_GetVector +****************************************************************************//** +* +* \brief Gets the address of the current ISR vector for the Interrupt. +* +* For CM0+, this function returns the interrupt vector for the interrupt mux +* output feeding into the NVIC. +* +* Note that this function relies on the assumption that the vector table is +* relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. +* +* \param config +* Interrupt configuration structure +* +* \return +* Address of the ISR in the interrupt vector table +* +*******************************************************************************/ +cy_israddress Cy_SysInt_GetVector(const cy_stc_sysint_t* config) +{ + #if CY_CPU_CORTEX_M0P + /* Only return the SRAM ISR address if it was moved to __ramVectors */ + if (SCB->VTOR == (uint32_t)&__ramVectors) + { + if (config->intrSrc < 0) + { + return __ramVectors[CY_INT_IRQ_BASE + config->intrSrc]; + } + else + { + return __ramVectors[CY_INT_IRQ_BASE + config->intrCm0p]; + } + } + else + { + if (config->intrSrc < 0) + { + return __Vectors[CY_INT_IRQ_BASE + config->intrSrc]; + } + else + { + return __Vectors[CY_INT_IRQ_BASE + config->intrCm0p]; + } + } + #else + /* Only return the SRAM ISR address if it was moved to __ramVectors */ + if (SCB->VTOR == (uint32_t)&__ramVectors) + { + return __ramVectors[CY_INT_IRQ_BASE + config->intrSrc]; + } + else + { + return __Vectors[CY_INT_IRQ_BASE + config->intrSrc]; + } + #endif +} + + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysint/cy_sysint.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysint/cy_sysint.h new file mode 100644 index 0000000000..df84a2d5c9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/sysint/cy_sysint.h @@ -0,0 +1,343 @@ +/***************************************************************************//** +* \file cy_sysint.h +* \version 1.0 +* +* \brief +* Provides an API declaration of the sysint driver +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_sysint System Interrupt (SysInt) +* \{ +* The SysInt driver provides an API to configure the device peripheral interrupts. +* It provides a lightweight interface to complement the CMSIS core NVIC API. +* The provided functions are applicable for all cores in a device and they can +* be used to configure and connect device peripheral interrupts to one or more +* cores. +* +* \n +* Initialization +* +* To configure an interrupt, call Cy_SysInt_Init(). +* Populate the configuration structure (cy_stc_sysint_t) and pass it as a parameter +* along with the ISR address. This initializes the interrupt and +* instructs the CPU to jump to the specified ISR vector upon a valid trigger. +* +* Populating the interrupt configuration structure differs slightly for the CM0+ core. +* This core supports only up to 32 peripheral interrupt channels. To allow all device +* interrupts to be routable to the NVIC of this core, there exists a 240:1 multiplexer +* at each of the 32 NVIC channels. Hence the configuration structure (cy_stc_sysint_t) +* must specify the device interrupt source (intSrc) and the CM0+ NVIC mux (intrCm0p). +* +* \n +* Enable +* +* After initializing an interrupt, use the CMSIS Core NVIC_EnableIRQ() function to +* enable it. The parameter used in this function call differs between the CM0+ cores +* and non-CM0+ cores due to the previously mentioned architectural differences. +* Given an initialization structure named config, the function should be called as +* follows: +* +* - Non-CM0+ : NVIC_EnableIRQ(config.intrSrc) +* - CM0+ : NVIC_EnableIRQ(config.intrCm0p) +* +* \section group_sysint_section_configuration_considerations Configuration Considerations +* +* For the Cortex-M0+ core, NVIC mux positions 28, 29, 30, and 31 are reserved for +* internal use by Cypress. These should not be used by the application code. +* +* \section group_sysint_more_information More Information +* +* Refer to the technical reference manual (TRM) and the device datasheet. +* +* +* \section group_sysint_MISRA MISRA-C Compliance +* +* The sysint driver does not have any specific deviations. +* +* \section group_sysint_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_sysint_macro Macro +* \defgroup group_sysint_globals Global variables +* \defgroup group_sysint_functions Functions +* \defgroup group_sysint_data_structures Data structures +* \defgroup group_sysint_enums Enumerated Types +*/ + + +#if !defined(CY_SYSINT_H) +#define CY_SYSINT_H + +#include +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* Global Variable +***************************************/ + +/** +* \addtogroup group_sysint_globals +* \{ +*/ + +extern const cy_israddress __Vectors[]; /**< Vector table in Flash */ +extern cy_israddress __ramVectors[]; /**< Relocated vector table in SRAM */ + +/** \} group_sysint_globals */ + + +/*************************************** +* Global Interrupt +***************************************/ + +/** +* \addtogroup group_sysint_macro +* \{ +*/ + +/** Driver major version */ +#define CY_SYSINT_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_SYSINT_DRV_VERSION_MINOR 0 + +/** SysInt driver ID */ +#define CY_SYSINT_ID CY_PDL_DRV_ID(0x15u) + +/** \} group_sysint_macro */ + + +/*************************************** +* Enumeration +***************************************/ + +/** +* \addtogroup group_sysint_enums +* \{ +*/ + +/** +* SysInt Driver error codes +*/ +typedef enum +{ + CY_SYSINT_SUCCESS = 0x00u, /**< Returned successful */ + CY_SYSINT_BAD_PARAM = CY_SYSINT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */ +} cy_en_sysint_status_t; + +/** +* Enumeration values for Cortex-M0+ NVIC multiplexer selection. +* Deep-sleep wakeup-capability is determined by the CPUSS_CM0_DPSLP_IRQ_NR +* parameter, where the first N number of muxes have the capability to trigger +* deep-sleep interrupts. A deep-sleep capable interrupt source must be +* connected to one of these muxes to be able to trigger in deep-sleep. +*/ +typedef enum { + NvicMux0 = 0, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 0 */ + NvicMux1 = 1, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 1 */ + NvicMux2 = 2, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 2 */ + NvicMux3 = 3, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 3 */ + NvicMux4 = 4, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 4 */ + NvicMux5 = 5, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 5 */ + NvicMux6 = 6, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 6 */ + NvicMux7 = 7, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 7 */ + NvicMux8 = 8, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 8 */ + NvicMux9 = 9, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 9 */ + NvicMux10 = 10, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 10 */ + NvicMux11 = 11, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 11 */ + NvicMux12 = 12, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 12 */ + NvicMux13 = 13, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 13 */ + NvicMux14 = 14, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 14 */ + NvicMux15 = 15, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 15 */ + NvicMux16 = 16, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 16 */ + NvicMux17 = 17, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 17 */ + NvicMux18 = 18, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 18 */ + NvicMux19 = 19, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 19 */ + NvicMux20 = 20, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 20 */ + NvicMux21 = 21, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 21 */ + NvicMux22 = 22, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 22 */ + NvicMux23 = 23, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 23 */ + NvicMux24 = 24, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 24 */ + NvicMux25 = 25, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 25 */ + NvicMux26 = 26, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 26 */ + NvicMux27 = 27, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 27 */ + NvicMux28 = 28, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 28 */ + NvicMux29 = 29, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 29 */ + NvicMux30 = 30, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 30 */ + NvicMux31 = 31, /**< NVIC Mux for mapping intrSrc to CM0+ NVIC input 31 */ +} IRQn_CM0P_Type; + +/** \} group_sysint_enums */ + + +/*************************************** +* Configuration Structure +***************************************/ + +/** +* \addtogroup group_sysint_data_structures +* \{ +*/ + +/** +* Initialization configuration structure for a single interrupt channel +*/ +typedef struct { + IRQn_Type intrSrc; /**< Interrupt source */ + IRQn_CM0P_Type intrCm0p; /**< (CM0+ only) Maps intrSrc to 32 available CM0+ NVIC inputs */ + uint32_t intrPriority; /**< Interrupt priority number (Refer to __NVIC_PRIO_BITS) */ +} cy_stc_sysint_t; + +/** \} group_sysint_data_structures */ + + +/*************************************** +* Constants +***************************************/ + +/** \cond INTERNAL */ + +#define CY_INT_IRQ_BASE (16u) /**< Start location of interrupts in the vector table */ +#define CY_SYSINT_STATE_MASK (1ul) /**< Mask for interrupt state */ +#define CY_SYSINT_STIR_MASK (0xfful) /**< Mask for software trigger interrupt register */ +#define CY_SYSINT_CM0P_MUX_MASK (0xfful) /**< CM0+ NVIC multiplexer mask */ +#define CY_SYSINT_CM0P_MUX_SHIFT (2u) /**< CM0+ NVIC multiplexer shift */ +#define CY_SYSINT_CM0P_MUX_SCALE (3u) /**< CM0+ NVIC multiplexer scaling value */ + +#define CY_SYSINT_CM0P_MUX0 (0u) /**< CM0+ NVIC multiplexer register 0 */ +#define CY_SYSINT_CM0P_MUX1 (1u) /**< CM0+ NVIC multiplexer register 1 */ +#define CY_SYSINT_CM0P_MUX2 (2u) /**< CM0+ NVIC multiplexer register 2 */ +#define CY_SYSINT_CM0P_MUX3 (3u) /**< CM0+ NVIC multiplexer register 3 */ +#define CY_SYSINT_CM0P_MUX4 (4u) /**< CM0+ NVIC multiplexer register 4 */ +#define CY_SYSINT_CM0P_MUX5 (5u) /**< CM0+ NVIC multiplexer register 5 */ +#define CY_SYSINT_CM0P_MUX6 (6u) /**< CM0+ NVIC multiplexer register 6 */ +#define CY_SYSINT_CM0P_MUX7 (7u) /**< CM0+ NVIC multiplexer register 7 */ + +#define CY_SYSINT_CM0P_MUX_ERROR (0xfffffffful) /**< Invalid CM0+ NVIC multiplexer error code */ + +/** \endcond */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_sysint_functions +* \{ +*/ +cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr); +uint32_t Cy_SysInt_GetState(const cy_stc_sysint_t* config); +cy_israddress Cy_SysInt_SetVector(const cy_stc_sysint_t* config, cy_israddress userIsr); +cy_israddress Cy_SysInt_GetVector(const cy_stc_sysint_t* config); +__STATIC_INLINE void Cy_SysInt_SetIntSourceNMI(const cy_stc_sysint_t* config); +__STATIC_INLINE uint32_t Cy_SysInt_GetIntSourceNMI(void); +#if (CY_CPU_CORTEX_M0P) + void Cy_SysInt_SetIntSource(const cy_stc_sysint_t* config); + uint32_t Cy_SysInt_GetIntSource(IRQn_CM0P_Type muxSel); +#else + __STATIC_INLINE void Cy_SysInt_SoftwareTrig(const cy_stc_sysint_t* config); +#endif + + +/******************************************************************************* +* Function Name: Cy_SysInt_SetIntSourceNMI +****************************************************************************//** +* +* \brief Sets the interrupt source of NMI. +* +* Setting this value to 240 disconnects the interrupt source from the NMI. The +* interrupt source must be a positive number. +* +* For CM0+, this function sets the interrupt mux output feeding into the +* NVIC as the source for NMI. +* +* \param config +* Interrupt configuration structure +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysInt_SetIntSourceNMI(const cy_stc_sysint_t* config) +{ + #if CY_CPU_CORTEX_M0P + CPUSS->CM0_NMI_CTL = config->intrCm0p; + #else + CPUSS->CM4_NMI_CTL = config->intrSrc; + #endif +} + + +/******************************************************************************* +* Function Name: Cy_SysInt_GetIntSourceNMI +****************************************************************************//** +* +* \brief Gets the interrupt source of the NMI. +* +* \return +* Interrupt Source. A value of 240 means that there is no interrupt source +* for the NMI, and an interrupt can be triggered only through software. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysInt_GetIntSourceNMI(void) +{ + #if CY_CPU_CORTEX_M0P + return (CPUSS->CM0_NMI_CTL); + #else + return (CPUSS->CM4_NMI_CTL); + #endif +} + + +#if (!CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_SysInt_SoftwareTrig +****************************************************************************//** +* +* \brief Triggers an interrupt using software (Not applicable for CM0+). +* +* Note Only privileged software can enable unprivileged access to the +* Software Trigger Interrupt Register (STIR). +* +* \param config +* Interrupt configuration structure +* +*******************************************************************************/ +__STATIC_INLINE void Cy_SysInt_SoftwareTrig(const cy_stc_sysint_t* config) +{ + NVIC->STIR = config->intrSrc & CY_SYSINT_STIR_MASK; +} + +#endif + +/** \} group_sysint_functions */ + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_SYSINT_H */ + +/** \} group_sysint */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syslib/cy_syslib.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syslib/cy_syslib.c new file mode 100644 index 0000000000..7aedbebc3b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syslib/cy_syslib.c @@ -0,0 +1,654 @@ +/***************************************************************************//** +* \file cy_syslib.c +* \version 1.0 +* +* Description: +* Provides system API implementation for the Cypress PDL 3.0 syslib driver. +* +******************************************************************************** +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_syslib.h" +#include "ipc/cy_ipc_drv.h" + +/* Flash wait states (LP mode at 1.1v) */ +#define CY_SYSLIB_FLASH_LP_WS_0_FREQ_MAX ( 24UL) +#define CY_SYSLIB_FLASH_LP_WS_1_FREQ_MAX ( 48UL) +#define CY_SYSLIB_FLASH_LP_WS_2_FREQ_MAX ( 72UL) +#define CY_SYSLIB_FLASH_LP_WS_3_FREQ_MAX ( 96UL) +#define CY_SYSLIB_FLASH_LP_WS_4_FREQ_MAX (120UL) + +/* Flash wait states (ULP mode at 0.9v) */ +#define CY_SYSLIB_FLASH_ULP_WS_0_FREQ_MAX ( 16UL) +#define CY_SYSLIB_FLASH_ULP_WS_1_FREQ_MAX ( 33UL) +#define CY_SYSLIB_FLASH_ULP_WS_2_FREQ_MAX ( 50UL) + +/* ROM wait states for the slow clock domain (LP mode at 1.1v) */ +#define CY_SYSLIB_ROM_LP_SLOW_WS_0_FREQ_MAX (100UL) +#define CY_SYSLIB_ROM_LP_SLOW_WS_1_FREQ_MAX (120UL) + +/* ROM wait states for the slow clock domain (ULP mode at 0.9v) */ +#define CY_SYSLIB_ROM_ULP_SLOW_WS_0_FREQ_MAX ( 25UL) +#define CY_SYSLIB_ROM_ULP_SLOW_WS_1_FREQ_MAX ( 50UL) + +/* ROM wait states for the fast clock domain (LP mode at 1.1v) */ +#define CY_SYSLIB_ROM_LP_FAST_WS_0_FREQ_MAX (120UL) + +/* ROM wait states for the slow clock domain (ULP mode at 0.9v) */ +#define CY_SYSLIB_ROM_ULP_FAST_WS_0_FREQ_MAX ( 50UL) + +/* SRAM wait states for the slow clock domain (LP mode at 1.1v) */ +#define CY_SYSLIB_RAM_LP_SLOW_WS_0_FREQ_MAX (100UL) +#define CY_SYSLIB_RAM_LP_SLOW_WS_1_FREQ_MAX (120UL) + +/* SRAM wait states for the slow clock domain (ULP mode at 0.9v) */ +#define CY_SYSLIB_RAM_ULP_SLOW_WS_0_FREQ_MAX ( 25UL) +#define CY_SYSLIB_RAM_ULP_SLOW_WS_1_FREQ_MAX ( 50UL) + +/* SRAM wait states for the fast clock domain (LP mode at 1.1v) */ +#define CY_SYSLIB_RAM_LP_FAST_WS_0_FREQ_MAX (120UL) + +/* SRAM wait states for the fast clock domain (ULP mode at 0.9v) */ +#define CY_SYSLIB_RAM_ULP_FAST_WS_0_FREQ_MAX ( 50UL) + + +#if !defined(NDEBUG) + char_t cy_assertFileName[CY_MAX_FILE_NAME_SIZE]; + uint32_t cy_assertLine; +#endif /* NDEBUG */ + +#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) + cy_stc_fault_frame_t cy_faultFrame; +#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */ + + +static void Cy_SysLib_SetWaitStates_ULP(uint32_t clkHfMHz); +static void Cy_SysLib_SetWaitStates_LP(uint32_t clkHfMHz); + + +/******************************************************************************* +* Function Name: Cy_SysLib_Delay +****************************************************************************//** +* +* The function delays by the specified number of milliseconds. +* By default, the number of cycles to delay is calculated based on the +* SystemCoreClock. +* If the parameter is bigger than CY_DELAY_MS_OVERFLOW(32kHz delay), run an +* additional loop to prevent an overflow. +* +* \param milliseconds The number of milliseconds to delay. +* +*******************************************************************************/ +void Cy_SysLib_Delay(uint32_t milliseconds) +{ + while (milliseconds > CY_DELAY_MS_OVERFLOW) + { + /* This loop prevents overflow. + * At 100MHz, milliseconds * cy_delayFreqKhz it overflows at about 42 seconds + */ + Cy_SysLib_DelayCycles(cy_delay32kMs); + milliseconds -= CY_DELAY_MS_OVERFLOW; + } + + Cy_SysLib_DelayCycles(milliseconds * cy_delayFreqKhz); +} + + +/******************************************************************************* +* Function Name: Cy_SysLib_DelayUs +****************************************************************************//** +* +* The function delays by the specified number of microseconds. +* By default, the number of cycles to delay is calculated based on the +* SystemCoreClock. +* +* \param microseconds The number of microseconds to delay. +* +*******************************************************************************/ +void Cy_SysLib_DelayUs(uint16_t microseconds) +{ + Cy_SysLib_DelayCycles((uint32_t) microseconds * cy_delayFreqMhz); +} + + +/******************************************************************************* +* Function Name: Cy_SysLib_Halt +****************************************************************************//** +* +* This function halts the CPU but only the CPU which calls the function. +* It doesn't affect other CPUs. +* +* \param reason The value to be used during debugging. +* +* \note The function executes the BKPT instruction for halting CPU and is +* intended to be used for debug purposes. A regular use case requires +* Debugger attachment before the function call. +* The BKPT instruction causes the CPU to enter the Debug state. Debug +* tools can use this to investigate the system state, when the +* instruction at a particular address is reached. +* +* \note Execution of a BKPT instruction without a debugger attached produces +* a fault. The fault results in the HardFault exception being taken +* or causes Lockup state if it occurs in the NMI or HardFault handler. +* The default HardFault handler make a software reset if the build option +* is release mode (NDEBUG). If the build option is debug mode, the system +* will stay in the infinite loop of the Cy_SysLib_ProcessingFault() +* function. +* +*******************************************************************************/ +__NO_RETURN void Cy_SysLib_Halt(uint32_t reason) +{ + if(0u != reason) + { + /* To remove an unreferenced local variable warning */ + } + + #if defined (__ARMCC_VERSION) + __breakpoint(0x0); + while(1u) {} + #elif defined(__GNUC__) + __asm(" bkpt 1"); + __builtin_unreachable(); + #elif defined (__ICCARM__) + __asm(" bkpt 1"); + #else + #error "Unsupported toolchain" + #endif /* (__ARMCC_VERSION) */ +} + + +/******************************************************************************* +* Function Name: Cy_SysLib_ClearFlashCacheAndBuffer +****************************************************************************//** +* +* This function invalidates the flash cache and buffer. It ensures the valid +* data is read from flash instead of using outdated data from the cache. +* The caches' LRU structure is also reset to their default state. +* +* \note The operation takes a maximum of three clock cycles on the slowest of +* the clk_slow and clk_fast clocks. +* +*******************************************************************************/ +void Cy_SysLib_ClearFlashCacheAndBuffer(void) +{ + FLASHC->FLASH_CMD = FLASHC_FLASH_CMD_INV_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SysLib_GetResetReason +****************************************************************************//** +* +* The function returns the cause for the latest reset(s) that occurred in +* the system. The reset causes in the registers are two separated parts which +* are HFCLK error and system faults. +* The return results are consolidated reset causes for both parts by +* reading both RES_CAUSE and RES_CAUSE2 registers. +* +* \return The cause of a system reset. +* +* | Name | Value +* |-------------------------------|--------------------- +* | CY_SYSLIB_RESET_HWWDT | 0x00001 (bit0) +* | CY_SYSLIB_RESET_ACT_FAULT | 0x00002 (bit1) +* | CY_SYSLIB_RESET_DPSLP_FAULT | 0x00004 (bit2) +* | CY_SYSLIB_RESET_CSV_WCO_LOSS | 0x00008 (bit3) +* | CY_SYSLIB_RESET_SOFT | 0x00010 (bit4) +* | CY_SYSLIB_RESET_SWWDT0 | 0x00020 (bit5) +* | CY_SYSLIB_RESET_SWWDT1 | 0x00040 (bit6) +* | CY_SYSLIB_RESET_SWWDT2 | 0x00080 (bit7) +* | CY_SYSLIB_RESET_SWWDT3 | 0x00100 (bit8) +* | CY_SYSLIB_RESET_HFCLK_LOSS | 0x10000 (bit16) +* | CY_SYSLIB_RESET_HFCLK_ERR | 0x20000 (bit17) +* +*******************************************************************************/ +uint32_t Cy_SysLib_GetResetReason(void) +{ + uint32_t retVal; + + retVal = SRSS->RES_CAUSE | + ((CY_LO16(SRSS->RES_CAUSE2) > 0u) ? CY_SYSLIB_RESET_HFCLK_LOSS : 0u) | + ((CY_HI16(SRSS->RES_CAUSE2) > 0u) ? CY_SYSLIB_RESET_HFCLK_ERR : 0u); + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SysLib_GetNumHfclkResetCause +****************************************************************************//** +* +* This function returns the number of HF_CLK which is a reset cause (RES_CAUSE2) +* by a loss or an error of the high frequency clock. +* +* The Clock supervisors (CSV) can make a reset as CSV_FREQ_ACTION setting +* when a CSV frequency anomaly is detected. The function returns the index +* of HF_CLK, if a reset occurred due to an anomaly HF_CLK. There are two +* different options for monitoring on HF_CLK which are a frequency loss +* and a frequency error. +* +* \return +* - The number HF_CLK from Clock Supervisor High Frequency Loss: Bits[15:0] +* - The number HF_CLK from Clock Supervisor High Frequency error: Bits[31:16] +* +*******************************************************************************/ +uint32_t Cy_SysLib_GetNumHfclkResetCause(void) +{ + return (SRSS->RES_CAUSE2); +} + + +/******************************************************************************* +* Function Name: Cy_SysLib_ClearResetReason +****************************************************************************//** +* +* This function clears the values of RES_CAUSE and RES_CAUSE2. +* +*******************************************************************************/ +void Cy_SysLib_ClearResetReason(void) +{ + SRSS->RES_CAUSE = SRSS->RES_CAUSE; + SRSS->RES_CAUSE2 = SRSS->RES_CAUSE2; +} + + +#if (CY_CPU_CORTEX_M0P) || defined(CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_SysLib_SoftResetCM4 +****************************************************************************//** +* +* This function performs a CM4 Core software reset using the CM4_PWR_CTL +* register. +* +* \note This function should be called only when the CM4 core is in Deep +* Sleep mode. +* \note This function will not reset CM0+ Core. +* +*******************************************************************************/ +void Cy_SysLib_SoftResetCM4(void) +{ + volatile uint32_t msg = CY_IPC_DATA_FOR_CM4_SOFT_RESET; + + /* Tries to acquire the IPC structure and pass the arguments to SROM API. + * SROM API parameters: + * ipcPtr: IPC_STRUCT0 - IPC Structure 0 reserved for M0+ Secure Access. + * notifyEvent_Intr: 1u - IPC Interrupt Structure 1 is used for Releasing IPC 0 (M0+ NMI Handler). + * msgPtr: &msg - The address of SRAM with the API's parameters. + */ + if(CY_IPC_DRV_SUCCESS != Cy_IPC_DRV_SendMsgPtr(IPC_STRUCT0, 1u, (void *) &msg)) + { + CY_ASSERT(0u != 0u); + } +} +#endif /* CY_CPU_CORTEX_M0P || defined(CY_DOXYGEN) */ + + +/******************************************************************************* +* Function Name: Cy_SysLib_GetUniqueId +****************************************************************************//** +* +* This function returns the silicon unique ID. +* The ID includes Die lot[3]#, Die Wafer#, Die X, Die Y, DIE Sort# and +* Die Minor# +* +* \return +* A combined 64-bit unique ID. +* [63:56] - DIE_MINOR +* [55:48] - DIE_SORT +* [47:40] - DIE_Y +* [39:32] - DIE_X +* [31:24] - DIE_WAFER +* [23:16] - DIE_LOT[2] +* [15: 8] - DIE_LOT[1] +* [ 7: 0] - DIE_LOT[0] +* +*******************************************************************************/ +uint64_t Cy_SysLib_GetUniqueId(void) +{ + uint64_t uniqueId; + + uniqueId = ((uint64_t)SFLASH->DIE_MINOR << CY_UNIQUE_ID_DIE_MINOR_Pos) | + ((uint64_t)SFLASH->DIE_SORT << CY_UNIQUE_ID_DIE_SORT_Pos) | + ((uint64_t)SFLASH->DIE_Y << CY_UNIQUE_ID_DIE_Y_Pos) | + ((uint64_t)SFLASH->DIE_X << CY_UNIQUE_ID_DIE_X_Pos) | + ((uint64_t)SFLASH->DIE_WAFER << CY_UNIQUE_ID_DIE_WAFER_Pos) | + ((uint64_t)SFLASH->DIE_LOT[2u] << CY_UNIQUE_ID_DIE_LOT_2_Pos) | + ((uint64_t)SFLASH->DIE_LOT[1u] << CY_UNIQUE_ID_DIE_LOT_1_Pos) | + ((uint64_t)SFLASH->DIE_LOT[0u] << CY_UNIQUE_ID_DIE_LOT_0_Pos); + + return (uniqueId); +} + + +#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_SysLib_FaultHandler +****************************************************************************//** +* +* This function stores the ARM Cortex registers into a non-zero init area for +* debugging. This function calls Cy_SysLib_ProcessingFault() after storing all +* the information. +* +* \param faultStackAddr The address of the stack pointer, indicates the lowest +* address in the fault stack frame to be stored. +* \note This function stores the fault stack frame only for the first occurred +* fault. +* \note This function sets two flags into the fault structure: one checks +* which core cause fault, another checks the type of fault for CM4 core. +* The flags should be cleared after analysis of the stored +* register values, to have possibility to distinguish the next fault. +* \note The PDL doesn't provide an API which can analyse the stored register +* values. A user has to add additional functions for the analysis, +* if necessary. +* \note The CY_ARM_FAULT_DEBUG macro defines if the Fault Handler is enabled. +* By default it is set to CY_ARM_FAULT_DEBUG_ENABLED and enables the +* Fault Handler. +* If there is a necessity to save memory or have some specific custom +* handler, etc. then CY_ARM_FAULT_DEBUG should be redefined as +* CY_ARM_FAULT_DEBUG_DISABLED. To do this the following definition should +* be added to the compiler Command Line (through the project Build +* Settings): "-D CY_ARM_FAULT_DEBUG=0". +* +*******************************************************************************/ +void Cy_SysLib_FaultHandler(uint32_t const *faultStackAddr) +{ + #if (CY_CPU_CORTEX_M0P) + if(CY_CM0P_FAULT_TYPE != cy_faultFrame.fault) + { + cy_faultFrame.fault = CY_CM0P_FAULT_TYPE; /* CM0P fault occurred. */ + #elif (CY_CPU_CORTEX_M4) + if(CY_CM4_FAULT_TYPE != cy_faultFrame.fault) + { + cy_faultFrame.fault = CY_CM4_FAULT_TYPE; /* CM4 fault occurred. */ + /* Stores the Configurable Fault Status Register state with the fault cause */ + cy_faultFrame.cfsr = SCB->CFSR; + cy_faultFrame.faultType = CY_NON_FPU_FAULT_TYPE; + #endif /* CY_CPU_CORTEX_M0P */ + /* Stores general registers */ + cy_faultFrame.r0 = faultStackAddr[CY_R0_Pos]; + cy_faultFrame.r1 = faultStackAddr[CY_R1_Pos]; + cy_faultFrame.r2 = faultStackAddr[CY_R2_Pos]; + cy_faultFrame.r3 = faultStackAddr[CY_R3_Pos]; + cy_faultFrame.r12 = faultStackAddr[CY_R12_Pos]; + cy_faultFrame.lr = faultStackAddr[CY_LR_Pos]; + cy_faultFrame.pc = faultStackAddr[CY_PC_Pos]; + cy_faultFrame.psr = faultStackAddr[CY_PSR_Pos]; + + #if (CY_CPU_CORTEX_M4) && ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U))) + /* Checks cumulative exception bits for floating-point exceptions */ + if(0U != (__get_FPSCR() & (CY_FPSCR_IXC_Msk | CY_FPSCR_IDC_Msk))) + { + cy_faultFrame.faultType = CY_FPU_FAULT_TYPE; + cy_faultFrame.s0 = faultStackAddr[CY_S0_Pos]; + cy_faultFrame.s1 = faultStackAddr[CY_S1_Pos]; + cy_faultFrame.s2 = faultStackAddr[CY_S2_Pos]; + cy_faultFrame.s3 = faultStackAddr[CY_S3_Pos]; + cy_faultFrame.s4 = faultStackAddr[CY_S4_Pos]; + cy_faultFrame.s5 = faultStackAddr[CY_S5_Pos]; + cy_faultFrame.s6 = faultStackAddr[CY_S6_Pos]; + cy_faultFrame.s7 = faultStackAddr[CY_S7_Pos]; + cy_faultFrame.s8 = faultStackAddr[CY_S8_Pos]; + cy_faultFrame.s9 = faultStackAddr[CY_S9_Pos]; + cy_faultFrame.s10 = faultStackAddr[CY_S10_Pos]; + cy_faultFrame.s11 = faultStackAddr[CY_S11_Pos]; + cy_faultFrame.s12 = faultStackAddr[CY_S12_Pos]; + cy_faultFrame.s13 = faultStackAddr[CY_S13_Pos]; + cy_faultFrame.s14 = faultStackAddr[CY_S14_Pos]; + cy_faultFrame.s15 = faultStackAddr[CY_S15_Pos]; + cy_faultFrame.fpscr = faultStackAddr[CY_FPSCR_Pos]; + } + #endif /* CY_CPU_CORTEX_M4 && __FPU_PRESENT */ + } + + Cy_SysLib_ProcessingFault(); +} + + +/******************************************************************************* +* Function Name: Cy_SysLib_ProcessingFault +****************************************************************************//** +* +* This function determines how to process the current fault state. By default +* in case of exception the system will stay in the infinite loop of this +* function. +* +* \note This function has WEAK option, so the user can redefine the function +* for a custom processing. +* For example the function redefinition could be constructed from fault +* stack processing and NVIC_SystemReset() function call. +* +*******************************************************************************/ +CY_WEAK void Cy_SysLib_ProcessingFault(void) +{ + while(1u) {} +} +#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN) */ + + +/******************************************************************************* +* Function Name: Cy_SysLib_SetWaitStates +****************************************************************************//** +* +* Sets the number of clock cycles the cache will wait for, before it samples +* data coming back from ROM, SRAM, and Flash. +* +* Call this function before increasing the HFClk0 High Frequency clock. +* Call this function optionally after lowering the HFClk0 High Frequency clock +* in order to improve the CPU performance. +* +* Also, call this function before switching core supply regulator voltage (LDO +* or SIMO Buck) from 1.1V to 0.9V. +* Call this function optionally after switching core supply regulator voltage +* from 0.9V to 1.1V in order to improve the CPU performance. +* +* \param ulpMode The device power mode. +* true, if the device should be switched to the ULP mode (nominal voltage of +* the core supply regulator should be switched to 0.9V); +* false, if the device should be switched to the LP mode (nominal voltage of +* the core supply regulator should be switched to 1.1V). +* +* \note Refer to the device TRM for low power modes description. +* +* \param clkHfMHz The HFClk0 clock frequency in MHz. +* +*******************************************************************************/ +void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz) +{ + if (ulpMode) + { + Cy_SysLib_SetWaitStates_ULP(clkHfMHz); + } + else + { + Cy_SysLib_SetWaitStates_LP(clkHfMHz); + } +} + + +/******************************************************************************* +* Function Name: Cy_SysLib_SetWaitStates_LP +****************************************************************************//** +* +* Sets the ROM, SRAM, and Flash wait states for the low power mode. +* This function is called by Cy_SysLib_SetWaitStates(). +* +*******************************************************************************/ +static void Cy_SysLib_SetWaitStates_LP(uint32_t clkHfMHz) +{ + uint32_t waitStates; + + /* ROM */ + if (clkHfMHz < CY_SYSLIB_ROM_LP_SLOW_WS_0_FREQ_MAX) + { + waitStates = 0UL; + } else if (clkHfMHz <= CY_SYSLIB_ROM_LP_SLOW_WS_1_FREQ_MAX) + { + waitStates = 1UL; + } else + { + waitStates = 3UL; + } + CPUSS->ROM_CTL = _CLR_SET_FLD32U(CPUSS->ROM_CTL, CPUSS_ROM_CTL_SLOW_WS, waitStates); + + if (clkHfMHz <= CY_SYSLIB_ROM_LP_FAST_WS_0_FREQ_MAX) + { + waitStates = 0UL; + } else + { + waitStates = 3UL; + } + CPUSS->ROM_CTL = _CLR_SET_FLD32U(CPUSS->ROM_CTL, CPUSS_ROM_CTL_FAST_WS, waitStates); + + /* SRAM */ + if (clkHfMHz < CY_SYSLIB_RAM_LP_SLOW_WS_0_FREQ_MAX) + { + waitStates = 0UL; + } else if (clkHfMHz <= CY_SYSLIB_RAM_LP_SLOW_WS_1_FREQ_MAX) + { + waitStates = 1UL; + } else + { + waitStates = 3UL; + } + CPUSS->RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM0_CTL0, CPUSS_RAM0_CTL0_SLOW_WS, waitStates); + #if defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) + CPUSS->RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM1_CTL0, CPUSS_RAM1_CTL0_SLOW_WS, waitStates); + #endif /* defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) */ + #if defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) + CPUSS->RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM2_CTL0, CPUSS_RAM2_CTL0_SLOW_WS, waitStates); + #endif /* defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) */ + + if (clkHfMHz <= CY_SYSLIB_RAM_LP_FAST_WS_0_FREQ_MAX) + { + waitStates = 0UL; + } else + { + waitStates = 3UL; + } + CPUSS->RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM0_CTL0, CPUSS_RAM0_CTL0_FAST_WS, waitStates); + #if defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) + CPUSS->RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM1_CTL0, CPUSS_RAM1_CTL0_SLOW_WS, waitStates); + #endif /* defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) */ + #if defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) + CPUSS->RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM2_CTL0, CPUSS_RAM2_CTL0_SLOW_WS, waitStates); + #endif /* defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) */ + + /* Flash */ + if (clkHfMHz <= CY_SYSLIB_FLASH_LP_WS_0_FREQ_MAX) + { + waitStates = 0UL; + } else if (clkHfMHz <= CY_SYSLIB_FLASH_LP_WS_1_FREQ_MAX) + { + waitStates = 1UL; + } else if (clkHfMHz <= CY_SYSLIB_FLASH_LP_WS_2_FREQ_MAX) + { + waitStates = 2UL; + } else if (clkHfMHz <= CY_SYSLIB_FLASH_LP_WS_3_FREQ_MAX) + { + waitStates = 3UL; + } else if (clkHfMHz <= CY_SYSLIB_FLASH_LP_WS_4_FREQ_MAX) + { + waitStates = 4UL; + } else + { + waitStates = 5UL; + } + + FLASHC->FLASH_CTL = _CLR_SET_FLD32U(FLASHC->FLASH_CTL, FLASHC_FLASH_CTL_MAIN_WS, waitStates); +} + + +/******************************************************************************* +* Function Name: Cy_SysLib_SetWaitStates_ULP +****************************************************************************//** +* +* Sets the ROM, SRAM, and Flash wait states for the ultra-low power mode. +* This function is called by Cy_SysLib_SetWaitStates(). +* +*******************************************************************************/ +#if (SRSS_SIMOBUCK_PRESENT == 1UL) +static void Cy_SysLib_SetWaitStates_ULP(uint32_t clkHfMHz) +{ + uint32_t waitStates; + + /* ROM */ + if (clkHfMHz < CY_SYSLIB_ROM_ULP_SLOW_WS_0_FREQ_MAX) + { + waitStates = 0UL; + } else if (clkHfMHz <= CY_SYSLIB_ROM_ULP_SLOW_WS_1_FREQ_MAX) + { + waitStates = 1UL; + } else + { + waitStates = 3UL; + } + CPUSS->ROM_CTL = _CLR_SET_FLD32U(CPUSS->ROM_CTL, CPUSS_ROM_CTL_SLOW_WS, waitStates); + + if (clkHfMHz <= CY_SYSLIB_ROM_ULP_FAST_WS_0_FREQ_MAX) + { + waitStates = 0UL; + } else + { + waitStates = 2UL; + } + CPUSS->ROM_CTL = _CLR_SET_FLD32U(CPUSS->ROM_CTL, CPUSS_ROM_CTL_FAST_WS, waitStates); + + /* SRAM */ + if (clkHfMHz < CY_SYSLIB_RAM_ULP_SLOW_WS_0_FREQ_MAX) + { + waitStates = 0UL; + } else if (clkHfMHz <= CY_SYSLIB_RAM_ULP_SLOW_WS_1_FREQ_MAX) + { + waitStates = 1UL; + } else + { + waitStates = 3UL; + } + CPUSS->RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM0_CTL0, CPUSS_RAM0_CTL0_SLOW_WS, waitStates); + #if defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) + CPUSS->RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM1_CTL0, CPUSS_RAM1_CTL0_SLOW_WS, waitStates); + #endif /* defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) */ + #if defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) + CPUSS->RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM2_CTL0, CPUSS_RAM2_CTL0_SLOW_WS, waitStates); + #endif /* defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) */ + + if (clkHfMHz <= CY_SYSLIB_RAM_ULP_FAST_WS_0_FREQ_MAX) + { + waitStates = 0UL; + } else + { + waitStates = 2UL; + } + CPUSS->RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM0_CTL0, CPUSS_RAM0_CTL0_FAST_WS, waitStates); + #if defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) + CPUSS->RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM1_CTL0, CPUSS_RAM1_CTL0_SLOW_WS, waitStates); + #endif /* defined (RAMC1_PRESENT) && (RAMC1_PRESENT == 1UL) */ + #if defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) + CPUSS->RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS->RAM2_CTL0, CPUSS_RAM2_CTL0_SLOW_WS, waitStates); + #endif /* defined (RAMC2_PRESENT) && (RAMC2_PRESENT == 1UL) */ + + /* Flash */ + if (clkHfMHz <= CY_SYSLIB_FLASH_ULP_WS_0_FREQ_MAX) + { + waitStates = 0UL; + } else if (clkHfMHz <= CY_SYSLIB_FLASH_ULP_WS_1_FREQ_MAX) + { + waitStates = 1UL; + } else if (clkHfMHz <= CY_SYSLIB_FLASH_ULP_WS_2_FREQ_MAX) + { + waitStates = 2UL; + } else + { + waitStates = 4UL; + } + + FLASHC->FLASH_CTL = _CLR_SET_FLD32U(FLASHC->FLASH_CTL, FLASHC_FLASH_CTL_MAIN_WS, waitStates); +} +#endif /* (SRSS_SIMOBUCK_PRESENT == 1UL) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syslib/cy_syslib.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syslib/cy_syslib.h new file mode 100644 index 0000000000..8bf6b7e0d8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syslib/cy_syslib.h @@ -0,0 +1,800 @@ +/***************************************************************************//** +* \file cy_syslib.h +* \version 1.0 +* +* Provides an API declaration of the syslib driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_syslib System Library (SysLib) +* \{ +* The system libraries provide APIs that can be called in the user application +* to handle the timing, logical checking or register. +* +* SysLib driver contains a set of different system functions. These functions +* can be called in the application routine. Some features of the system library: +* * Delay functions +* * Register read/write macro +* * Assert and Halt +* * Software reset +* * Reading a reset cause +* * API to invalidate the flash cache and buffer +* * Data manipulation +* * A variable type definition from MISRA-C specifying signedness +* * Cross compiler compatible attributes +* * Get silicon unique ID API +* +* \section group_syslib_configuration Configuration Considerations +* There are no general SysLib configuration concerns. +* +* \section group_syslib_more_information More Information +* Refer to the technical reference manual (TRM). +* +* \section group_syslib_MISRA MISRA Compliance +* The SysLib driver does not have any specific deviations. +* +* \section group_syslib_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_syslib_macro Macro +* \defgroup group_syslib_functions Functions +* \defgroup group_syslib_data_structures Data Structures +* +*/ + +#if !defined(_CY_SYSLIB_H_) +#define _CY_SYSLIB_H_ + +#if !defined(NDEBUG) + #include +#endif /* NDEBUG */ +#include +#include +#include "cy_device_headers.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* defined(__cplusplus) */ + +#if defined( __ICCARM__ ) + /* Suppress the warning for multiple volatile variables in an expression. */ + /* This is common for drivers code and the usage is not order-dependent. */ + #pragma diag_suppress=Pa082 +#endif /* defined( __ICCARM__ ) */ + + +/** +* \addtogroup group_syslib_data_structures +* \{ +*

The base types. Acceptable types from MISRA-C specifying signedness and size. +* These types must not be used. The default types should be used instead. +* These types are left for backward compatibility only.

+*/ + +typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */ +typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */ +typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */ +typedef int8_t int8; /**< Alias to int8_t for backward compatibility */ +typedef int16_t int16; /**< Alias to int16_t for backward compatibility */ +typedef int32_t int32; /**< Alias to int32_t for backward compatibility */ +typedef float float32; /**< Alias to float for backward compatibility */ +typedef double float64; /**< Alias to double for backward compatibility */ +typedef int64_t int64; /**< Alias to int64_t for backward compatibility */ +typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */ +/* Signed or unsigned depending on the compiler selection */ +typedef char char8; /**< Alias to char for backward compatibility */ + +/* MISRA rule 6.3 recommends use specific-length typedef for the basic + * numerical types of signed and unsigned variants of char, float, and double. + */ +typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */ +typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */ +typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */ + +/******************************************************************************* +* Hardware Register Types +*******************************************************************************/ + +typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */ +typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */ +typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */ + +/******************************************************************************* +* General cytypes +*******************************************************************************/ +/** ARM 32-bit status value */ +typedef uint32_t cy_status; + +/** \cond INTERNAL */ +/** ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */ +typedef uint32_t cystatus; +/** \endcond */ + +/** \} group_syslib_data_structures */ + +/** +* \addtogroup group_syslib_macro +* \{ +*/ + +/****************************************************************************** +* Macros +*****************************************************************************/ + +#define CY_CPU_CORTEX_M0P (__CORTEX_M == 0) /**< CM0+ core CPU Code */ +#define CY_CPU_CORTEX_M4 (__CORTEX_M == 4) /**< CM4 core CPU Code */ + +/** Macro to disable the Fault Handler */ +#define CY_ARM_FAULT_DEBUG_DISABLED (0u) +/** Macro to enable the Fault Handler */ +#define CY_ARM_FAULT_DEBUG_ENABLED (1u) + +#if !defined(CY_ARM_FAULT_DEBUG) + /** Macro defines if the Fault Handler is enabled. Enabled by default. */ + #define CY_ARM_FAULT_DEBUG (CY_ARM_FAULT_DEBUG_ENABLED) +#endif /* CY_ARM_FAULT_DEBUG */ + +/** +* \defgroup group_syslib_macro_status_codes Status codes +* \{ +* Function status type codes +*/ +#define CY_PDL_STATUS_CODE_Pos (0u) /**< The module status code position in the status code */ +#define CY_PDL_STATUS_TYPE_Pos (16u) /**< The status type position in the status code */ +#define CY_PDL_MODULE_ID_Pos (18u) /**< The software module ID position in the status code */ +#define CY_PDL_STATUS_INFO (0UL << CY_PDL_STATUS_TYPE_Pos) /**< Information status type */ +#define CY_PDL_STATUS_WARNING (1UL << CY_PDL_STATUS_TYPE_Pos) /**< Warning status type */ +#define CY_PDL_STATUS_ERROR (2UL << CY_PDL_STATUS_TYPE_Pos) /**< Error status type */ +#define CY_PDL_MODULE_ID_Msk (0x3FFFu) /**< The software module ID mask */ +/* Get the software PDL module ID */ +#define CY_PDL_DRV_ID(id) ((uint32_t)((uint32_t)((id) & CY_PDL_MODULE_ID_Msk) << CY_PDL_MODULE_ID_Pos)) +#define CY_SYSLIB_ID CY_PDL_DRV_ID(0x11u) /**< SYSLIB PDL ID */ +/** \} group_syslib_macro_status_codes */ + +/** \} group_syslib_macro */ + +/** +* \addtogroup group_syslib_data_structures +* \{ +*/ +/** The SysLib status code structure. */ +typedef enum +{ + CY_SYSLIB_SUCCESS = 0x00UL, /**< Success status code */ + CY_SYSLIB_BAD_PARAM = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< Bad parameter status code */ + CY_SYSLIB_TIMEOUT = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< Time out status code */ + CY_SYSLIB_INVALID_STATE = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x03UL, /**< Invalid state status code */ + CY_SYSLIB_UNKNOWN = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0xFFUL /**< Unknown status code */ +} cy_en_syslib_status_t; + +#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) +/** The Fault configuration structure. */ +typedef struct +{ + uint32_t fault; /**< Indicates if the fault occurred */ + uint32_t r0; /**< R0 register content */ + uint32_t r1; /**< R1 register content */ + uint32_t r2; /**< R2 register content */ + uint32_t r3; /**< R3 register content */ + uint32_t r12; /**< R12 register content */ + uint32_t lr; /**< LR register content */ + uint32_t pc; /**< PC register content */ + uint32_t psr; /**< PSR register content */ + + #if (CY_CPU_CORTEX_M4) + uint32_t cfsr; /**< CFSR register content */ + uint32_t faultType; /**< FPU or regular fault type */ + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U))) + uint32_t s0; /**< FPU S0 register content */ + uint32_t s1; /**< FPU S1 register content */ + uint32_t s2; /**< FPU S2 register content */ + uint32_t s3; /**< FPU S3 register content */ + uint32_t s4; /**< FPU S4 register content */ + uint32_t s5; /**< FPU S5 register content */ + uint32_t s6; /**< FPU S6 register content */ + uint32_t s7; /**< FPU S7 register content */ + uint32_t s8; /**< FPU S8 register content */ + uint32_t s9; /**< FPU S9 register content */ + uint32_t s10; /**< FPU S10 register content */ + uint32_t s11; /**< FPU S11 register content */ + uint32_t s12; /**< FPU S12 register content */ + uint32_t s13; /**< FPU S13 register content */ + uint32_t s14; /**< FPU S14 register content */ + uint32_t s15; /**< FPU S15 register content */ + uint32_t fpscr; /**< FPU FPSCR register content */ + #endif /* __FPU_PRESENT */ + #endif /* CY_CPU_CORTEX_M4 */ +} cy_stc_fault_frame_t; +#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */ + +/** \} group_syslib_data_structures */ + +/** +* \addtogroup group_syslib_macro +* \{ +*/ + +/** Driver major version */ +#define CY_SYSLIB_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_SYSLIB_DRV_VERSION_MINOR 0 + +/** \cond INTERNAL */ +/** ARM 32-bit Return error / status codes for backward compatibility. +* Do not use them in your code. +*/ +#define CY_RET_SUCCESS (0x00u) /* Successful */ +#define CY_RET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CY_RET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CY_RET_MEMORY (0x03u) /* Memory related failure */ +#define CY_RET_LOCKED (0x04u) /* Resource lock failure */ +#define CY_RET_EMPTY (0x05u) /* No more objects available */ +#define CY_RET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CY_RET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CY_RET_FINISHED (0x08u) /* Operation completed */ +#define CY_RET_CANCELED (0x09u) /* Operation canceled */ +#define CY_RET_TIMEOUT (0x10u) /* Operation timed out */ +#define CY_RET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFu) /* Unknown failure */ + +/** ARM 32-bit Return error / status codes for backward compatibility with the UDB components. +* Do not use them in your code. +*/ +#define CYRET_SUCCESS (0x00u) /* Successful */ +#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CYRET_MEMORY (0x03u) /* Memory related failure */ +#define CYRET_LOCKED (0x04u) /* Resource lock failure */ +#define CYRET_EMPTY (0x05u) /* No more objects available */ +#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08u) /* Operation completed */ +#define CYRET_CANCELED (0x09u) /* Operation canceled */ +#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ +/** \endcond */ + + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/** Get the lower 8 bits of a 16-bit value. */ +#define CY_LO8(x) ((uint8_t) ((x) & 0xFFu)) +/** Get the upper 8 bits of a 16-bit value. */ +#define CY_HI8(x) ((uint8_t) ((uint16_t)(x) >> 8u)) + +/** Get the lower 16 bits of a 32-bit value. */ +#define CY_LO16(x) ((uint16_t) ((x) & 0xFFFFu)) +/** Get the upper 16 bits of a 32-bit value. */ +#define CY_HI16(x) ((uint16_t) ((uint32_t)(x) >> 16u)) + +/** Swap the byte ordering of a 16-bit value */ +#define CY_SWAP_ENDIAN16(x) ((uint16_t)(((x) << 8u) | (((x) >> 8u) & 0x00FFu))) + +/** Swap the byte ordering of a 32-bit value */ +#define CY_SWAP_ENDIAN32(x) ((uint32_t)((((x) >> 24u) & 0x000000FFu) | (((x) & 0x00FF0000u) >> 8u) | \ + (((x) & 0x0000FF00u) << 8u) | ((x) << 24u))) + +/** Swap the byte ordering of a 64-bit value */ +#define CY_SWAP_ENDIAN64(x) ((uint64_t) (((uint64_t) CY_SWAP_ENDIAN32((uint32_t)(x)) << 32u) | \ + CY_SWAP_ENDIAN32((uint32_t)((x) >> 32u)))) + + +/******************************************************************************* +* Memory model definitions +*******************************************************************************/ +#if defined(__ARMCC_VERSION) + + /** To create cross compiler compatible code, use the CY_NOINIT, CY_SECTION, CY_UNUSED, CY_ALIGN + * attributes at the first place of declaration/definition. + * For example: CY_NOINIT uint32_t noinitVar; + */ + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_UNUSED __attribute__ ((unused)) + + /* Specifies the minimum alignment (in bytes) for variables of the specified type. */ + #define CY_ALIGN(align) __ALIGNED(align) + #define CY_WEAK __weak + +#elif defined (__GNUC__) + + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_UNUSED __attribute__ ((unused)) + #define CY_ALIGN(align) __ALIGNED(align) + #define CY_WEAK __attribute__ ((weak)) + +#elif defined (__ICCARM__) + + #define CY_PRAGMA(x) _Pragma(#x) + #define CY_NOINIT __no_init + #define CY_SECTION(name) CY_PRAGMA(section = name) + #define CY_UNUSED + #define CY_ALIGN(align) CY_PRAGMA(data_alignment = align) + #define CY_WEAK __weak + +#else + #error "Unsupported toolchain" +#endif /* (__ARMCC_VERSION) */ + +typedef void (* cy_israddress)(void); /**< Type of ISR callbacks */ + +/** \cond INTERNAL */ +/** Type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */ +typedef void (* cyisraddress)(void); +/** \endcond */ + +#if defined (__ICCARM__) + typedef union { cy_israddress __fun; void * __ptr; } cy_intvec_elem; + /** \cond INTERNAL */ + /** Type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */ + typedef union { cyisraddress __fun; void * __ptr; } intvec_elem; + /** \endcond */ +#endif /* defined (__ICCARM__) */ + +#if !defined(NDEBUG) + /** Max size of file name which stores the ASSERT location */ + #define CY_MAX_FILE_NAME_SIZE (24u) + extern char_t cy_assertFileName[CY_MAX_FILE_NAME_SIZE]; /**< Assert buffer */ + extern uint32_t cy_assertLine; /**< Assert line value */ +#endif /* NDEBUG */ + +#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) + #define CY_R0_Pos (0u) /**< Position of R0 content in fault structure */ + #define CY_R1_Pos (1u) /**< Position of R1 content in fault structure */ + #define CY_R2_Pos (2u) /**< Position of R2 content in fault structure */ + #define CY_R3_Pos (3u) /**< Position of R3 content in fault structure */ + #define CY_R12_Pos (4u) /**< Position of R12 content in fault structure */ + #define CY_LR_Pos (5u) /**< Position of LR content in fault structure */ + #define CY_PC_Pos (6u) /**< Position of PC content in fault structure */ + #define CY_PSR_Pos (7u) /**< Position of PSR content in fault structure */ + #if (CY_CPU_CORTEX_M0P) + #define CY_CM0P_FAULT_TYPE (0xF0F1F2F3u) /**< Flag for indication CM0P core fault */ + #elif (CY_CPU_CORTEX_M4) + #define CY_CM4_FAULT_TYPE (0xF4F5F6F7u) /**< Flag for indication CM4 core fault */ + #define CY_NON_FPU_FAULT_TYPE (0xA1A2A3A4u) /**< Flag for indication CM4 non floating point fault type */ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U))) + #define CY_FPU_FAULT_TYPE (0xA8A9AAABu) /**< Flag for indication CM4 core floating point fault type */ + #define CY_FPSCR_IXC_Msk (0x00000010u) /**< Cumulative exception bit for floating-point exceptions */ + #define CY_FPSCR_IDC_Msk (0x00000080u) /**< Cumulative exception bit for floating-point exceptions */ + #define CY_S0_Pos (8u) /**< Position of FPU S0 content in fault structure */ + #define CY_S1_Pos (9u) /**< Position of FPU S1 content in fault structure */ + #define CY_S2_Pos (10u) /**< Position of FPU S2 content in fault structure */ + #define CY_S3_Pos (11u) /**< Position of FPU S3 content in fault structure */ + #define CY_S4_Pos (12u) /**< Position of FPU S4 content in fault structure */ + #define CY_S5_Pos (13u) /**< Position of FPU S5 content in fault structure */ + #define CY_S6_Pos (14u) /**< Position of FPU S6 content in fault structure */ + #define CY_S7_Pos (15u) /**< Position of FPU S7 content in fault structure */ + #define CY_S8_Pos (16u) /**< Position of FPU S8 content in fault structure */ + #define CY_S9_Pos (17u) /**< Position of FPU S9 content in fault structure */ + #define CY_S10_Pos (18u) /**< Position of FPU S10 content in fault structure */ + #define CY_S11_Pos (19u) /**< Position of FPU S11 content in fault structure */ + #define CY_S12_Pos (20u) /**< Position of FPU S12 content in fault structure */ + #define CY_S13_Pos (21u) /**< Position of FPU S13 content in fault structure */ + #define CY_S14_Pos (22u) /**< Position of FPU S14 content in fault structure */ + #define CY_S15_Pos (23u) /**< Position of FPU S15 content in fault structure */ + #define CY_FPSCR_Pos (24u) /**< Position of FPU FPSCR content in fault structure */ + #endif /* __FPU_PRESENT */ + #endif /* CY_CPU_CORTEX_M0P */ + + extern cy_stc_fault_frame_t cy_faultFrame; /**< Fault frame structure */ +#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */ + + +/******************************************************************************* +* Macro Name: CY_GET_REG8(addr) +****************************************************************************//** +* +* Reads the 8-bit value from the specified address. This function can't be +* used to access the Core register, otherwise a fault occurs. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG8(addr) (*((const volatile uint8_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG8(addr, value) +****************************************************************************//** +* +* Writes an 8-bit value to the specified address. This function can't be +* used to access the Core register, otherwise a fault occurs. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG8(addr, value) (*((volatile uint8_t *)(addr)) = (uint8_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_GET_REG16(addr) +****************************************************************************//** +* +* Reads the 16-bit value from the specified address. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG16(addr) (*((const volatile uint16_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG16(addr, value) +****************************************************************************//** +* +* Writes an 16-bit value to the specified address. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG16(addr, value) (*((volatile uint16_t *)(addr)) = (uint16_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_GET_REG24(addr) +****************************************************************************//** +* +* Reads the 24-bit value from the specified address. +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG24(addr) (uint32_t) ((*((const volatile uint8_t *)(addr))) | \ + (uint32_t) ((*((const volatile uint8_t *)(addr) + 1)) << 8u) | \ + (uint32_t) ((*((const volatile uint8_t *)(addr) + 2)) << 16u)) + + +/******************************************************************************* +* Macro Name: CY_SET_REG24(addr, value) +****************************************************************************//** +* +* Writes an 24-bit value to the specified address. +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG24(addr, value) do \ + { \ + (*((volatile uint8_t *) (addr))) = (uint8_t)(value); \ + (*((volatile uint8_t *) (addr) + 1)) = (uint8_t)((value) >> 8u); \ + (*((volatile uint8_t *) (addr) + 2)) = (uint8_t)((value) >> 16u); \ + } \ + while(0u); + + +/******************************************************************************* +* Macro Name: CY_GET_REG32(addr) +****************************************************************************//** +* +* Reads the 32-bit value from the specified register. The address is the little +* endian order (LSB in lowest address) +* +* \param addr The register address. +* +* \return The read value. +* +*******************************************************************************/ +#define CY_GET_REG32(addr) (*((const volatile uint32_t *)(addr))) + + +/******************************************************************************* +* Macro Name: CY_SET_REG32(addr, value) +****************************************************************************//** +* +* Writes a 32-bit value to the specified register. The address is the little +* endian order (LSB in lowest address) +* +* \param addr The register address. +* +* \param value The value to write. +* +*******************************************************************************/ +#define CY_SET_REG32(addr, value) (*((volatile uint32_t *)(addr)) = (uint32_t)(value)) + + +/******************************************************************************* +* Macro Name: CY_ASSERT +****************************************************************************//** +* +* The macro that evaluates the expression and, if it is false (evaluates to 0), +* the processor is halted. Cy_Halt() is called when the logical expression is +* false to halt the processor. +* The ASSERT location of the file name (including path to file) and line number +* will be stored in a non-zero init area for debugging. They can be accessed +* by cy_assertFileName and assertLine global variables. +* +* \note This macro is evaluated unless NDEBUG is not defined. +* If NDEBUG is defined, just empty do while cycle is generated for this macro +* for the sake of consistency and to avoid MISRA violation. +* NDEBUG is defined by default for a Release build setting and not defined for +* a Debug build setting. +* +* \param x The logical expression. Asserts if false. +* +*******************************************************************************/ +#if !defined(NDEBUG) + #define CY_ASSERT(x) do \ + { \ + if(0u == (uint32_t)(x)) \ + { \ + (void) strncpy(cy_assertFileName, __FILE__, CY_MAX_FILE_NAME_SIZE); \ + cy_assertLine = (uint32_t)(__LINE__); \ + Cy_Halt((uint32_t)0u); \ + } \ + } \ + while(0u) +#else + #define CY_ASSERT(x) do \ + { \ + } \ + while(0u) +#endif /* !defined(NDEBUG) */ + + +/******************************************************************************* +* Macro Name: _CLR_SET_FLD32U +****************************************************************************//** +* +* The macro for setting a register with a name field and value for providing +* get-clear-modify-write operations. +* +*******************************************************************************/ +#define _CLR_SET_FLD32U(reg, field, value) (((reg) & ((uint32_t)(~(field ## _Msk)))) | (_VAL2FLD(field, value))) + + +/******************************************************************************* +* Macro Name: _BOOL2FLD +****************************************************************************//** +* +* Returns a field mask if the value is not false. +* Returns 0, if the value is false. +* +*******************************************************************************/ +#define _BOOL2FLD(field, value) ((value != false) ? field ## _Msk : 0UL) + + +/******************************************************************************* +* Macro Name: _FLD2BOOL +****************************************************************************//** +* +* Returns true, if the value includes the field mask. +* Returns false, if the value doesn't include the field mask. +* +*******************************************************************************/ +#define _FLD2BOOL(field, value) ((value & field ## _Msk) != 0UL) + + +/****************************************************************************** +* Constants +*****************************************************************************/ +/** Defines a 32-kHz clock delay */ +#define CY_DELAY_MS_OVERFLOW (0x8000u) + +/** +* \defgroup group_syslib_macro_reset_cause Reset cause +* \{ +* Define RESET_CAUSE mask values +*/ +/** A basic WatchDog Timer (WDT) reset has occurred since the last power cycle. */ +#define CY_SYSLIB_RESET_HWWDT (0x0001u) +/** The fault logging system requested a reset from its Active logic. */ +#define CY_SYSLIB_RESET_ACT_FAULT (0x0002u) +/** The fault logging system requested a reset from its DeepSleep logic. */ +#define CY_SYSLIB_RESET_DPSLP_FAULT (0x0004u) +/** The clock supervision logic requested a reset due to loss of a watch-crystal clock. */ +#define CY_SYSLIB_RESET_CSV_WCO_LOSS (0x0008u) +/** The CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. */ +#define CY_SYSLIB_RESET_SOFT (0x0010u) +/** The Multi-Counter Watchdog timer #0 reset has occurred since last power cycle. */ +#define CY_SYSLIB_RESET_SWWDT0 (0x0020u) +/** The Multi-Counter Watchdog timer #1 reset has occurred since last power cycle. */ +#define CY_SYSLIB_RESET_SWWDT1 (0x0040u) +/** The Multi-Counter Watchdog timer #2 reset has occurred since last power cycle. */ +#define CY_SYSLIB_RESET_SWWDT2 (0x0080u) +/** The Multi-Counter Watchdog timer #3 reset has occurred since last power cycle. */ +#define CY_SYSLIB_RESET_SWWDT3 (0x0100u) +/** The clock supervision logic requested a reset due to loss of a high-frequency clock. */ +#define CY_SYSLIB_RESET_HFCLK_LOSS (0x10000UL) +/** The clock supervision logic requested a reset due to frequency error of a high-frequency clock. */ +#define CY_SYSLIB_RESET_HFCLK_ERR (0x20000UL) + +/** \} group_syslib_macro_reset_cause */ + +/** Bit[31:24] Opcode = 0x1B (SoftReset) + * Bit[7:1] Type = 1 (Only CM4 reset) + */ +#define CY_IPC_DATA_FOR_CM4_SOFT_RESET (0x1B000002UL) + +/** +* \defgroup group_syslib_macro_unique_id Unique ID +* \{ +* Unique ID fields positions +*/ +#define CY_UNIQUE_ID_DIE_MINOR_Pos (56u) /**< Position of DIE_MINOR field in the silicon Unique ID */ +#define CY_UNIQUE_ID_DIE_SORT_Pos (48u) /**< Position of DIE_SORT field in the silicon Unique ID */ +#define CY_UNIQUE_ID_DIE_Y_Pos (40u) /**< Position of DIE_Y field in the silicon Unique ID */ +#define CY_UNIQUE_ID_DIE_X_Pos (32u) /**< Position of DIE_X field in the silicon Unique ID */ +#define CY_UNIQUE_ID_DIE_WAFER_Pos (24u) /**< Position of DIE_WAFER field in the silicon Unique ID */ +#define CY_UNIQUE_ID_DIE_LOT_2_Pos (16u) /**< Position of DIE_LOT_2 field in the silicon Unique ID */ +#define CY_UNIQUE_ID_DIE_LOT_1_Pos (8u) /**< Position of DIE_LOT_1 field in the silicon Unique ID */ +#define CY_UNIQUE_ID_DIE_LOT_0_Pos (0u) /**< Position of DIE_LOT_0 field in the silicon Unique ID */ + +/** \} group_syslib_macro_unique_id */ + +/** \} group_syslib_macro */ + +/****************************************************************************** +* Function prototypes +******************************************************************************/ + +/** +* \addtogroup group_syslib_functions +* \{ +*/ + +void Cy_SysLib_Delay(uint32_t milliseconds); +void Cy_SysLib_DelayUs(uint16_t microseconds); +/** Delays for the specified number of cycles. + * The function is implemented in assembler for each supported compiler. + * \param cycles The number of cycles to delay. + */ +void Cy_SysLib_DelayCycles(uint32_t cycles); +__NO_RETURN void Cy_SysLib_Halt(uint32_t reason); +void Cy_SysLib_ClearFlashCacheAndBuffer(void); +uint32_t Cy_SysLib_GetResetReason(void); +uint32_t Cy_SysLib_GetNumHfclkResetCause(void); +void Cy_SysLib_ClearResetReason(void); +uint64_t Cy_SysLib_GetUniqueId(void); +#if (CY_CPU_CORTEX_M0P) + void Cy_SysLib_SoftResetCM4(void); +#endif /* CY_CPU_CORTEX_M0P */ +#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN) + void Cy_SysLib_FaultHandler(uint32_t const *faultStackAddr); + CY_WEAK void Cy_SysLib_ProcessingFault(void); +#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */ +void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz); + + +/******************************************************************************* +* Function Name: Cy_SysLib_EnterCriticalSection +****************************************************************************//** +* +* Cy_SysLib_EnterCriticalSection disables interrupts and returns a value +* indicating whether interrupts were previously enabled. +* +* \note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ +* enable bit with interrupts still enabled. +* +* \return +* Returns the current interrupt status. Returns 0 if interrupts were +* previously enabled or 1 if interrupts were previously disabled. +* +*******************************************************************************/ +uint32_t Cy_SysLib_EnterCriticalSection(void); + + +/******************************************************************************* +* Function Name: Cy_SysLib_ExitCriticalSection +****************************************************************************//** +* +* Re-enables interrupts if they were enabled before +* Cy_SysLib_EnterCriticalSection() was called. The argument should be the value +* returned from \ref Cy_SysLib_EnterCriticalSection(). +* +* \param savedIntrStatus +* Puts the saved interrupts status returned by +* the \ref Cy_SysLib_EnterCriticalSection(). +* +*******************************************************************************/ +void Cy_SysLib_ExitCriticalSection(uint32_t savedIntrStatus); + +/** \cond INTERNAL */ +/** Backward compatibility define for the CyDelay() API for the UDB components. +* Do not use it in your code. +*/ +#define CyDelay (Cy_SysLib_Delay) +/** Backward compatibility define for the CyDelayUs() API for the UDB components. +* Do not use it in your code. +*/ +#define CyDelayUs (Cy_SysLib_DelayUs) +/** Backward compatibility define for the CyDelayCycles() API for the UDB components. +* Do not use it in your code. +*/ +#define CyDelayCycles (Cy_SysLib_DelayCycles) +/** Backward compatibility define for the Cy_Halt() API. +* Do not use it in your code. +*/ +#define Cy_Halt (Cy_SysLib_Halt) +/** Backward compatibility define for the Cy_ClearFlashCacheAndBuffer() API. +* Do not use it in your code. +*/ +#define Cy_ClearFlashCacheAndBuffer (Cy_SysLib_ClearFlashCacheAndBuffer) +/** Backward compatibility define for the Cy_SYSLIB_GetResetReason() API. +* Do not use it in your code. +*/ +#define Cy_SYSLIB_GetResetReason (Cy_SysLib_GetResetReason) +/** Backward compatibility define for the Cy_SYSLIB_GetNumHFCLKResetCause() API. +* Do not use it in your code. +*/ +#define Cy_SYSLIB_GetNumHFCLKResetCause (Cy_SysLib_GetNumHfclkResetCause) +/** Backward compatibility define for the Cy_SYSLIB_ClearResetReason() API. +* Do not use it in your code. +*/ +#define Cy_SYSLIB_ClearResetReason (Cy_SysLib_ClearResetReason) +/** Backward compatibility define for the Cy_SYSLIB_GetUniqueId() API. +* Do not use it in your code. +*/ +#define Cy_SYSLIB_GetUniqueId (Cy_SysLib_GetUniqueId) +/** Backward compatibility define for the Cy_SYSLIB_SoftResetCM4() API. +* Do not use it in your code. +*/ +#define Cy_SYSLIB_SoftResetCM4 (Cy_SysLib_SoftResetCM4) +#if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN) + /** Backward compatibility define for the Cy_SYSLIB_FaultHandler() API. + * Do not use it in your code. + */ + #define Cy_SYSLIB_FaultHandler (Cy_SysLib_FaultHandler) + /** Backward compatibility define for the Cy_SYSLIB_ProcessingFault() API. + * Do not use it in your code. + */ + #define Cy_SYSLIB_ProcessingFault (Cy_SysLib_ProcessingFault) +#endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */ +/** Backward compatibility define for the Cy_SYSLIB_SetWaitStates() API. +* Do not use it in your code. +*/ +#define Cy_SYSLIB_SetWaitStates (Cy_SysLib_SetWaitStates) +/** Backward compatibility define for the CyEnterCriticalSection() API for the UDB components. +* Do not use it in your code. +*/ +#define CyEnterCriticalSection (Cy_SysLib_EnterCriticalSection) +/** Backward compatibility define for the CyExitCriticalSection() API for the UDB components. +* Do not use it in your code. +*/ +#define CyExitCriticalSection (Cy_SysLib_ExitCriticalSection) +/** \endcond */ + +/** \} group_syslib_functions */ + +#if defined(__cplusplus) +} +#endif /* defined(__cplusplus) */ + +#endif /* _CY_SYSLIB_H_ */ + +/** \} group_syslib */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syspm/cy_syspm.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syspm/cy_syspm.c new file mode 100644 index 0000000000..4d79820a23 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syspm/cy_syspm.c @@ -0,0 +1,1879 @@ +/***************************************************************************//** +* \file cy_syspm.c +* \version 1.0 +* +* This driver provides the source code to the API for the power management. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#include "cy_syspm.h" + +static cy_stc_syspm_callback_t* callbackRoot = NULL; +static uint32_t currentRegisteredCallbacksNumber = 0u; + +static void Cy_SysPm_SetDelayAfterDeepSleep(void); + +#if(0u != SRSS_SIMOBUCK_PRESENT) + + static void Cy_SysPm_SetVoltageBitForFlash(bool setBit); + +#endif /* (0u != SRSS_SIMOBUCK_PRESENT) */ + + +/******************************************************************************* +* Function Name: Cy_SysPm_ReadStatus +****************************************************************************//** +* +* Reads the status of the core(s). +* +* \return The current power mode. See \ref group_syspm_return_status. +* +*******************************************************************************/ +uint32_t Cy_SysPm_ReadStatus(void) +{ + uint32_t interruptState; + uint32_t pmStatus = 0u; + interruptState = Cy_SysLib_EnterCriticalSection(); + + /* Check whether CM4 is in DeepSleep mode*/ + if((0u != _FLD2VAL(CPUSS_CM4_STATUS_SLEEPING, CPUSS->CM4_STATUS)) && + (0u != _FLD2VAL(CPUSS_CM4_STATUS_SLEEPDEEP, CPUSS->CM4_STATUS))) + { + pmStatus |= CY_SYSPM_STATUS_CM4_DEEPSLEEP; + } + /* Check whether CM4 is in Sleep mode*/ + else if(0u != _FLD2VAL(CPUSS_CM4_STATUS_SLEEPING, CPUSS->CM4_STATUS)) + { + pmStatus |= CY_SYSPM_STATUS_CM4_SLEEP; + } + else + { + pmStatus |= CY_SYSPM_STATUS_CM4_ACTIVE; + } + + /* Check whether CM0p is in DeepSleep mode*/ + if((0u != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPING, CPUSS->CM0_STATUS)) && + (0u != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPDEEP, CPUSS->CM0_STATUS))) + { + pmStatus |= (uint32_t) CY_SYSPM_STATUS_CM0_DEEPSLEEP; + } + /* Check whether CM0p is in Sleep mode*/ + else if (0u != _FLD2VAL(CPUSS_CM0_STATUS_SLEEPING, CPUSS->CM0_STATUS)) + { + pmStatus |= CY_SYSPM_STATUS_CM0_SLEEP; + } + else + { + pmStatus |= CY_SYSPM_STATUS_CM0_ACTIVE; + } + + /* Check whether device is in Low Power mode by reading + * the Active Reference status + */ + if(0u != (_FLD2VAL(SRSS_PWR_CTL_ACT_REF_DIS, SRSS->PWR_CTL))) + { + pmStatus |= CY_SYSPM_STATUS_SYSTEM_LOWPOWER; + } + Cy_SysLib_ExitCriticalSection(interruptState); + + return(pmStatus); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_Sleep +****************************************************************************//** +* +* Sets a CPU core to Sleep mode. +* +* Puts the core into the Sleep power mode, if none of callback functions were +* registered. +* +* If at least one callback function with CY_SYSPM_SLEEP type was registered, the +* next algorithm is executed. +* Prior to entering Sleep mode, all callback functions with CY_SYSPM_SLEEP type +* with CY_SYSPM_CHECK_READY parameter are called allowing a driver +* to signal whether it is ready to enter the low power mode. If any of +* callbacks with CY_SYSPM_SLEEP type with CY_SYSPM_CHECK_READY parameter +* returns CY_SYSPM_FAIL the remaining callback with CY_SYSPM_SLEEP type with +* CY_SYSPM_CHECK_READY parameter calls are skipped. +* After a CY_SYSPM_FAIL, all of the CY_SYSPM_SLEEP callbacks with +* CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the callback +* with callbacks with CY_SYSPM_SLEEP type with CY_SYSPM_CHECK_READY +* parameter calls that occurred up to the point of failure. Sleep mode is not +* entered and the Cy_SysPm_Sleep API returns CY_SYSPM_FAIL. +* +* If all of the callbacks with CY_SYSPM_SLEEP type with CY_SYSPM_CHECK_READY +* parameter calls return CY_SYSPM_SUCCESS then all callbacks with CY_SYSPM_SLEEP +* type with CY_SYSPM_CHECK_FAIL parameters calls are skipped and all callbacks +* with CY_SYSPM_SLEEP type and CY_SYSPM_BEFORE_ENTER parameter calls are +* executed, allowing peripherals to prepare for Sleep. Sleep mode is then +* entered for the CPU. This is a CPU-centric power mode. It means that the CPU +* has entered Sleep mode and its main clock is removed. It is identical to +* Active from a peripheral point of view. Any enabled interrupts can cause a +* wakeup from Sleep mode. +* +* After wakeup from Sleep all of the registered callbacks with CY_SYSPM_SLEEP +* type and with CY_SYSPM_AFTER_EXIT parameter are executed to return peripherals +* to Active operation. The Cy_SysPm_Sleep API returns CY_SYSPM_SUCCESS. +* No callbacks with CY_SYSPM_SLEEP type with CY_SYSPM_BEFORE_ENTER parameter or +* callbacks with CY_SYSPM_SLEEP type and CY_SYSPM_AFTER_EXIT parameter callbacks +* are executed if Sleep mode is not entered. +* +* \param enWaitFor Selects wait for action. See \ref cy_en_syspm_waitfor_t. +* +* \return +* CY_SYSPM_SUCCESS - Entered and exited from Sleep
+* CY_SYSPM_FAIL - Sleep not entered. See \ref cy_en_syspm_status_t. +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_SysPm_Sleep(cy_en_syspm_waitfor_t enWaitFor) +{ + uint32_t interruptState; + cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; + + /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */ + if(0u != currentRegisteredCallbacksNumber) + { + retVal = (cy_en_syspm_status_t) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_READY, 0u); + } + + /* The device (core) can switch into Sleep power mode only when + * all executed registered callback functions with CY_SYSPM_CHECK_READY + * parameter returned CY_SYSPM_SUCCESS. + */ + if(retVal == CY_SYSPM_SUCCESS) + { + /* Call registered callback functions with CY_SYSPM_BEFORE_ENTER + * parameter. Return value is ignored. + */ + interruptState = Cy_SysLib_EnterCriticalSection(); + if(0u != currentRegisteredCallbacksNumber) + { + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_BEFORE_ENTER, 0u); + } + + /* CPU enters Sleep power mode upon execution of WFI/WFE */ + SCB->SCR = _CLR_SET_FLD32U((SCB->SCR), SCB_SCR_SLEEPDEEP, 0u); + + if(enWaitFor != CY_SYSPM_WAIT_FOR_EVENT) + { + __WFI(); + } + else + { + __WFE(); + } + Cy_SysLib_ExitCriticalSection(interruptState); + + /* Call registered callback functions with CY_SYSPM_AFTER_EXIT + * parameter. Return value is ignored. + */ + if(0u != currentRegisteredCallbacksNumber) + { + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_AFTER_EXIT, 0u); + } + } + else + { + /* Execute callback functions with CY_SYSPM_CHECK_FAIL parameter to + * undo everything done in the CY_SYSPM_CHECK_READY callback. Return + * value is ignored. + */ + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_SLEEP, CY_SYSPM_CHECK_FAIL, (uint32_t) retVal); + retVal = CY_SYSPM_FAIL; + } + return retVal; +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_DeepSleep +****************************************************************************//** +* +* Sets a CPU core to DeepSleep mode. +* +* Puts the core into the Deep Sleep power mode. Prior to entering Deep Sleep +* mode, all callbacks with CY_SYSPM_DEEPSLEEP type with CY_SYSPM_CHECK_READY +* parameter registered callbacks are called, allowing a driver to signal whether +* it is ready to enter the power mode. If any CY_SYSPM_DEEPSLEEP +* type with CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL, the +* remaining callback CY_SYSPM_DEEPSLEEP type with CY_SYSPM_CHECK_READY parameter +* calls are skipped. After a CY_SYSPM_FAIL, all of the callbacks with +* CY_SYSPM_DEEPSLEEP type with CY_SYSPM_CHECK_FAIL parameter are executed that +* correspond to the callbacks with CY_SYSPM_DEEPSLEEP type with +* CY_SYSPM_CHECK_READY parameter calls that occurred up to the point of failure. +* Deep Sleep mode is not entered and the Cy_SysPm_Sleep API returns +* CY_SYSPM_FAIL. +* +* If all callbacks with CY_SYSPM_DEEPSLEEP type with CY_SYSPM_CHECK_READY +* parameter calls return CY_SYSPM_SUCCESS, then all callbacks with +* CY_SYSPM_DEEPSLEEP type with CY_SYSPM_CHECK_FAIL parameter calls are skipped +* and all callbacks with CY_SYSPM_DEEPSLEEP type with CY_SYSPM_BEFORE_ENTER +* parameter calls are executed, allowing peripherals to prepare for Deep Sleep. +* Deep Sleep mode is then entered. Any enabled interrupts can cause a wakeup +* from Deep Sleep mode. +* +* If the firmware attempts to enter this mode before the system is ready (that +* is, when PWR_CONTROL.LPM_READY = 0), then the device will go into the (LP) +* Sleep mode instead and automatically enter the DeepSleep mode when the +* system is ready. +* +* The SRSS puts the whole device into DeepSleep mode when all the processors +* are in SLEEPDEEP, there are no busy peripherals, the debugger is not active, +* and the DEEPSLEEP circuits in the SRSS are ready (PWR_CONTROL.LPM_READY=1). +* +* Peripherals not needing a clock or that receive a clock from their external +* interface (e.g. I2C/SPI) continue operating. All circuits using the current +* from Vccdpslp supply are under the current limitation that is controlled +* by DeepSleep regulator. +* +* Wakeup occurs when an interrupt is received from a DeepSleep active +* peripheral. For more details, see the corresponding peripheral's datasheet. +* +* A normal wakeup from DeepSleep returns to either LPActive, LPSleep, Active, or +* Sleep, depending on the previous state and programmed behaviour for the +* particular wakeup interrupt. +* +* After wakeup from Deep Sleep, all of the registered callbacks with +* CY_SYSPM_DEEPSLEEP type with CY_SYSPM_AFTER_EXIT are executed to return +* peripherals to Active operation. The Cy_SysPm_DeepSleep API returns +* CY_SYSPM_SUCCESS. No callbacks are executed with CY_SYSPM_DEEPSLEEP type with +* CY_SYSPM_BEFORE_ENTER or CY_SYSPM_AFTER_EXIT parameter, if Deep Sleep +* mode is not entered. +* +* \param enWaitFor Selects wait for action. See \ref cy_en_syspm_waitfor_t. +* +* \return +* CY_SYSPM_SUCCESS - Entered and exited from DeepSleep
+* CY_SYSPM_FAIL - DeepSleep not entered. See \ref cy_en_syspm_status_t. +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_SysPm_DeepSleep(cy_en_syspm_waitfor_t enWaitFor) +{ + uint32_t interruptState; + cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; + + /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */ + if(0u != currentRegisteredCallbacksNumber) + { + retVal = (cy_en_syspm_status_t) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_CHECK_READY, 0u); + } + + /* The device (core) can switch into Deep Sleep power mode only when + * all executed registered callback functions with CY_SYSPM_CHECK_READY + * parameter returned CY_SYSPM_SUCCESS. + */ + if(retVal == CY_SYSPM_SUCCESS) + { + /* Call registered callback functions with CY_SYSPM_BEFORE_ENTER + * parameter. Return value is ignored. + */ + interruptState = Cy_SysLib_EnterCriticalSection(); + if(0u != currentRegisteredCallbacksNumber) + { + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_BEFORE_ENTER, 0u); + } + Cy_SysPm_SetDelayAfterDeepSleep(); + + /* CPU enters DeepSleep mode upon execution of WFI/WFE */ + SCB->SCR = _CLR_SET_FLD32U((SCB->SCR), SCB_SCR_SLEEPDEEP, 1u); + + if(enWaitFor != CY_SYSPM_WAIT_FOR_EVENT) + { + __WFI(); + } + else + { + __WFE(); + } + Cy_SysLib_ExitCriticalSection(interruptState); + + /* Call registered callback functions with CY_SYSPM_AFTER_EXIT + * parameter. Return value is ignored. + */ + if(0u != currentRegisteredCallbacksNumber) + { + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_AFTER_EXIT, 0u); + } + } + else + { + /* Execute callbacks functions with CY_SYSPM_CHECK_FAIL parameter to + * undo everything done in the CY_SYSPM_CHECK_READY callback. Return + * value is ignored. + */ + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_DEEPSLEEP, CY_SYSPM_CHECK_FAIL, (uint32_t) retVal); + retVal = CY_SYSPM_FAIL; + } + return retVal; +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_Hibernate +****************************************************************************//** +* +* Sets the device into Hibernate mode. +* +* Puts the core into the Hibernate power mode. Prior to entering Hibernate mode +* all callbacks with CY_SYSPM_HIBERNATE type are executed. +* At the first time callbacks with CY_SYSPM_HIBERNATE type and with +* CY_SYSPM_CHECK_READY parameter are called allowing a driver to signal it is +* not ready to enter the power mode. If any of callbacks CY_SYSPM_HIBERNATE type +* with CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL the +* remaining CY_SYSPM_HIBERNATE callbacks with CY_SYSPM_CHECK_READY parameter +* calls are skipped. After a CY_SYSPM_FAIL all of the CY_SYSPM_HIBERNATE +* callbacks with CY_SYSPM_CHECK_FAIL parameter are executed that correspond to +* the CY_SYSPM_HIBERNATE callbacks with CY_SYSPM_CHECK_READY parameter calls +* that occurred up to the point of failure. Hibernate mode is not entered +* and the Cy_SysPm_Hibernate API returns CY_SYSPM_FAIL. +* +* If all CY_SYSPM_HIBERNATE callbacks with CY_SYSPM_CHECK_READY parameter calls +* return CY_SYSPM_SUCCESS, then all CY_SYSPM_HIBERNATE callbacks with +* CY_SYSPM_CHECK_FAIL calls are skipped and all CY_SYSPM_HIBERNATE callbacks +* CY_SYSPM_BEFORE_ENTER parameter calls are executed allowing peripherals to +* prepare for Hibernate. I/O output state is frozen and Hibernate mode is then +* entered. In Hibernate mode all internal supplies are off and no internal state +* is retained. There is no handshake with the CPUs and the chip will begin entry +* to Hibernate immediately. +* +* A wakeup from Hibernate is triggered by toggling the wakeup pin(s), a WDT +* match, or back up domain alarm expiration depending on how the HIBERNATE +* register is configured. A wakeup causes a normal boot procedure to occur. +* To configure the wakeup pin(s), a Digital Input Pin must be configured, and +* resistively pulled up or down to the inverse state of the wakeup polarity. To +* distinguish a wakeup from the Hibernate mode and a general reset event, +* Cy_SysLib_GetResetReason() function can be used. The wakeup pin is +* active-low by default. The wakeup pin polarity can be changed with the +* \ref Cy_SysPm_WakeupPinLevel() function. This function call will not return if +* Hibernate mode is entered. The CY_SYSPM_HIBERNATE callbacks with +* CY_SYSPM_AFTER_EXIT parameter are never executed. +* +* This function freezes IO cells implicitly. It is not possible to enter +* the Hibernate mode before freezing the IO cells. The IO cells remain frozen +* after waking from Hibernate mode until firmware unfreezes them +* with a \ref Cy_SysPm_IoUnfreeze() function call. +* +* \return +* CY_SYSPM_SUCCESS - Not valid as hibernate; can only exit through a reset.
+* CY_SYSPM_FAIL - Hibernate not entered. See \ref cy_en_syspm_status_t. +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_SysPm_Hibernate(void) +{ + cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; + + /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */ + if(0u != currentRegisteredCallbacksNumber) + { + retVal = (cy_en_syspm_status_t) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_READY, 0u); + } + + /* The device (core) can switch into Hibernate power mode only when + * all executed registered callback functions with CY_SYSPM_CHECK_READY + * parameter returned CY_SYSPM_SUCCESS. + */ + if(retVal == CY_SYSPM_SUCCESS) + { + /* Call registered callback functions with CY_SYSPM_BEFORE_ENTER + * parameter. Return value is ignored. + */ + (void) Cy_SysLib_EnterCriticalSection(); + if(0u != currentRegisteredCallbacksNumber) + { + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_BEFORE_ENTER, 0u); + } + + /* Safe retain bit-fields before entering into Hibernate power mode. */ + SRSS->PWR_HIBERNATE &= CY_SYSPM_PWR_RETAIN_HIBERNATE_STATUS; + + /* All three writes to HIBERNATE register use same value: + * PWR_HIBERNATE.FREEZE=1, .UNLOCK=0x3A, .HIBERANTE=1, + */ + SRSS->PWR_HIBERNATE |= CY_SYSPM_PWR_HIBERNATE_UNLOCK | + _VAL2FLD(SRSS_PWR_HIBERNATE_FREEZE, 1u) | + _VAL2FLD(SRSS_PWR_HIBERNATE_HIBERNATE, 1u); + + SRSS->PWR_HIBERNATE |= CY_SYSPM_PWR_HIBERNATE_UNLOCK | + _VAL2FLD(SRSS_PWR_HIBERNATE_FREEZE, 1u) | + _VAL2FLD(SRSS_PWR_HIBERNATE_HIBERNATE, 1u); + + SRSS->PWR_HIBERNATE |= CY_SYSPM_PWR_HIBERNATE_UNLOCK | + _VAL2FLD(SRSS_PWR_HIBERNATE_FREEZE, 1u) | + _VAL2FLD(SRSS_PWR_HIBERNATE_HIBERNATE, 1u); + + /* Wait for transition */ + __WFI(); + + /* The callback functions calls with CY_SYSPM_AFTER_EXIT parameter in + * Hibernate power mode is is not applicable as device wake-up is made + * on device reboot. + */ + + /* A wakeup from Hibernate is performed by toggling of wakeup pins, or + * WDT matches, or Backup domain alarm expires. Depends on what item is + * configured in HIBERNATE register. After a wakeup event, a normal Boot + * procedure occurs. No need to exit from the critical section. + */ + } + else + { + /* Execute callback functions with CY_SYSPM_CHECK_FAIL parameter to + * undo everything done in the CY_SYSPM_CHECK_READY callback. Return + * value is ignored. + */ + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_HIBERNATE, CY_SYSPM_CHECK_FAIL, (uint32_t) retVal); + retVal = CY_SYSPM_FAIL; + } + return retVal; +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_EnterLpMode +****************************************************************************//** +* +* Sets device into Low Power mode. +* +* The low power (LPActive/LPSleep) modes are similar to the Active/Sleep modes. +* The difference is that the current is limited and some functions have limited +* features/performance. +* +* The feature of the low power mode is limited current. Restrictions are placed +* on the clock frequencies and allowed peripherals to achieve current limit. +* +* Before entering low power mode, the user should configure the system so the total +* current drawn from Vccd is less that value presented in the technical +* reference manual (TRM). Refer to TRM for the maximum load for low power +* operation and clock limitations in low power mode with different core supply +* regulator voltages. +* +* * Peripherals can use the knowledge of LPActive/LPSleep mode to make +* trade-offs that consume less current. For more details, see the corresponding +* peripheral's datasheet. +* * High-speed clock sources are available with appropriate predivider settings +* to limit the system current. +* Refer to the TRM for the maximum frequency values for low power operation using +* different Core Regulators output voltages. +* +* Puts the device into the Low Power mode. Prior to entering Low Power mode, all +* registered CY_SYSPM_ENTER_LP_MODE callbacks with CY_SYSPM_CHECK_READY +* parameter are called. This allows a driver to signal it is not ready to enter the +* Low Power mode. If any CY_SYSPM_ENTER_LP_MODE callbacks with +* CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL the remaining +* CY_SYSPM_ENTER_LP_MODE callbacks with CY_SYSPM_CHECK_READY parameter calls are +* skipped. +* After a CY_SYSPM_FAIL all of the CY_SYSPM_ENTER_LP_MODE callbacks with +* CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the +* CY_SYSPM_ENTER_LP_MODE callbacks with CY_SYSPM_CHECK_READY parameter calls +* that occurred up to the point of failure. Low Power mode is not entered and +* the Cy_SysPm_EnterLpMode API returns CY_SYSPM_FAIL. +* +* If all CY_SYSPM_ENTER_LP_MODE callbacks with CY_SYSPM_CHECK_READY parameter +* calls return CY_SYSPM_SUCCESS then all CY_SYSPM_ENTER_LP_MODE callbacks with +* CY_SYSPM_CHECK_FAIL calls are skipped and all CY_SYSPM_ENTER_LP_MODE callbacks +* with CY_SYSPM_BEFORE_ENTER parameter calls are executed. This allows peripherals +* to prepare for Low Power. Low Power mode is then entered. +* +* After entering Low Power mode, all of the registered CY_SYSPM_ENTER_LP_MODE +* callbacks with CY_SYSPM_AFTER_EXIT parameter are executed to complete +* preparing peripherals for Low Power operation. The Cy_SysPm_EnterLpMode API +* returns CY_SYSPM_SUCCESS. No CY_SYSPM_ENTER_LP_MODE callbacks with +* CY_SYSPM_BEFORE_ENTER or CY_SYSPM_AFTER_EXIT parameter are executed, if Low +* Power mode is not entered. +* +* \note The callbacks are not executed if device already is not in low power +* mode. +* +* \return +* CY_SYSPM_SUCCESS - Entered LPActive mode or device is already in LPActive.
+* CY_SYSPM_FAIL - LPActive mode not entered or low power circuits are not ready +* to enter into low power mode. See \ref cy_en_syspm_status_t. +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_SysPm_EnterLpMode(void) +{ + uint32_t interruptState; + cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; + + /* Check whether device is in Low Power mode */ + if(0u == (_FLD2VAL(SRSS_PWR_CTL_ACT_REF_DIS, SRSS->PWR_CTL))) + { + /* The entering into low power mode is permitted when low + * power circuits are ready to enter into low power mode. + */ + if(0u != _FLD2VAL(SRSS_PWR_CTL_LPM_READY, SRSS->PWR_CTL)) + { + /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */ + if(0u != currentRegisteredCallbacksNumber) + { + retVal = (cy_en_syspm_status_t) Cy_SysPm_ExecuteCallback(CY_SYSPM_ENTER_LP_MODE, CY_SYSPM_CHECK_READY, 0u); + } + + /* The device (core) can switch into Low power mode only when + * all executed registered callback functions with CY_SYSPM_CHECK_READY + * parameter returned CY_SYSPM_SUCCESS. + */ + if(retVal == CY_SYSPM_SUCCESS) + { + + /* Call registered callback functions with CY_SYSPM_BEFORE_ENTER + * parameter. Return value is ignored. + */ + interruptState = Cy_SysLib_EnterCriticalSection(); + if(0u != currentRegisteredCallbacksNumber) + { + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ENTER_LP_MODE, CY_SYSPM_BEFORE_ENTER, 0u); + } + /* Configure low-power operating mode for Linear Core regulator */ + if(Cy_SysPm_LdoIsEnabled()) + { + SRSS->PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_LINREG_LPMODE, 1u) | + _VAL2FLD(SRSS_PWR_CTL_PORBOD_LPMODE, 1u) | + _VAL2FLD(SRSS_PWR_CTL_BGREF_LPMODE, 1u)); + } + else + { + /* Configure low-power operating mode for SIMO Buck regulator */ + SRSS->PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_PORBOD_LPMODE, 1u) | + _VAL2FLD(SRSS_PWR_CTL_BGREF_LPMODE, 1u)); + } + + /* This wait time allows the circuits to remove their dependence on + * Active mode circuits, such as the Active Reference + */ + Cy_SysLib_DelayUs(CY_SYSPM_PWR_ACTIVE_TO_LP_WAIT_US); + + /* Disabling active reference */ + SRSS->PWR_CTL |= _VAL2FLD(SRSS_PWR_CTL_ACT_REF_DIS, 1u); + + Cy_SysLib_ExitCriticalSection(interruptState); + + /* Call registered callback functions with CY_SYSPM_AFTER_EXIT + * parameter. Return value is ignored. + */ + if(0u != currentRegisteredCallbacksNumber) + { + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ENTER_LP_MODE, CY_SYSPM_AFTER_EXIT, 0u); + } + } + else + { + /* Execute callbacks functions with CY_SYSPM_CHECK_FAIL parameter to + * undo everything done in the CY_SYSPM_CHECK_READY callback. Return + * value is ignored. + */ + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_ENTER_LP_MODE, CY_SYSPM_CHECK_FAIL, (uint32_t) retVal); + retVal = CY_SYSPM_FAIL; + } + } + else + { + retVal = CY_SYSPM_FAIL; + } + } + else + { + /* Do nothing as device is already in low-power mode. */ + } + return retVal; +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_ExitLpMode +****************************************************************************//** +* +* Sets device out of Low Power mode. +* +* Returns device to the Active mode. In active power mode, operating current can +* be increased to the normal mode limit. Clock frequencies also can be increased +* to the normal mode limit. Refer to the device TRM for current and frequency +* limitations in Active power mode. +* +* Prior to exiting Low Power mode, all registered CY_SYSPM_EXIT_LP_MODE callbacks +* with CY_SYSPM_CHECK_READY parameter are called. This allows +* a driver to signal it is not ready to exit the +* Low Power mode. If any CY_SYSPM_EXIT_LP_MODE callbacks with +* CY_SYSPM_CHECK_READY parameter call returns CY_SYSPM_FAIL, the remaining +* CY_SYSPM_EXIT_LP_MODE callbacks with CY_SYSPM_CHECK_READY parameter calls are +* skipped. After a CY_SYSPM_FAIL, all of the CY_SYSPM_EXIT_LP_MODE callbacks with +* CY_SYSPM_CHECK_FAIL parameter are executed that correspond to the +* CY_SYSPM_EXIT_LP_MODE callbacks with CY_SYSPM_CHECK_READY parameter calls that +* occurred up to the point of failure. Active mode is not entered and the +* Cy_SysPm_ExitLpMode API returns CY_SYSPM_FAIL. +* +* If all CY_SYSPM_EXIT_LP_MODE callbacks with CY_SYSPM_CHECK_READY calls return +* CY_SYSPM_SUCCESS then all CY_SYSPM_EXIT_LP_MODE callbacks with +* CY_SYSPM_CHECK_FAIL parameter calls are skipped and all CY_SYSPM_EXIT_LP_MODE +* callbacks CY_SYSPM_BEFORE_ENTER parameter calls are executed allowing +* peripherals to prepare for Active mode. Low Power mode is then exited. +* +* After exiting Low Power mode all of the registered callbacks are executed +* CY_SYSPM_EXIT_LP_MODE callbacks with CY_SYSPM_AFTER_EXIT parameter to complete +* preparing peripherals for Active mode operation. The Cy_SysPm_ExitLpMode API +* returns CY_SYSPM_SUCCESS. No CY_SYSPM_EXIT_LP_MODE callbacks with +* CY_SYSPM_BEFORE_ENTER or CY_SYSPM_AFTER_EXIT parameter are executed if Low +* Power mode is not exited. +* +* \note The callbacks are not executed if device is already not in a low power +* mode. +* +* \return +* CY_SYSPM_SUCCESS - Exited from LPActive power mode, or device is already in +* Active power.
+* CY_SYSPM_FAIL - the exit from LPActive mode not done, +* see \ref cy_en_syspm_status_t. +* +* \warning This function blocks as it waits until Active Reference is ready +* to enter into normal mode. +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_SysPm_ExitLpMode(void) +{ + uint32_t interruptState; + uint32_t timeOut = CY_SYSPM_WAIT_DELAY_TRYES; + cy_en_syspm_status_t retVal = CY_SYSPM_SUCCESS; + + /* Check if device is in Low Power mode */ + if(0u != (_FLD2VAL(SRSS_PWR_CTL_ACT_REF_DIS, SRSS->PWR_CTL))) + { + /* Call registered callback functions with CY_SYSPM_CHECK_READY parameter */ + if(0u != currentRegisteredCallbacksNumber) + { + retVal = (cy_en_syspm_status_t) Cy_SysPm_ExecuteCallback(CY_SYSPM_EXIT_LP_MODE, CY_SYSPM_CHECK_READY, 0u); + } + + /* The device (core) can switch into Low power mode only in condition + * that all executed registered callback functions with CY_SYSPM_CHECK_READY + * parameter returned CY_SYSPM_SUCCESS + */ + if(retVal == CY_SYSPM_SUCCESS) + { + /* Call registered callback functions with CY_SYSPM_BEFORE_ENTER + * parameter. Return value is ignored. + */ + interruptState = Cy_SysLib_EnterCriticalSection(); + if(0u != currentRegisteredCallbacksNumber) + { + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_EXIT_LP_MODE, CY_SYSPM_BEFORE_ENTER, 0u); + } + + /* Set normal operation mode for Linear Core regulator in condition + * that it is enabled + */ + if(Cy_SysPm_LdoIsEnabled()) + { + SRSS->PWR_CTL &= ((uint32_t)~(_VAL2FLD(SRSS_PWR_CTL_LINREG_LPMODE, 1u))); + } + + /* Configure normal operating mode for POR/BOD circuits and for + * Bandgap Voltage and Current References. + */ + SRSS->PWR_CTL &= ((uint32_t)~(_VAL2FLD(SRSS_PWR_CTL_PORBOD_LPMODE, 1u) | + _VAL2FLD(SRSS_PWR_CTL_ACT_REF_DIS, 1u) | + _VAL2FLD(SRSS_PWR_CTL_VREFBUF_LPMODE, 1u))); + + /* This wait time allows Active Reference to settle */ + Cy_SysLib_DelayUs(CY_SYSPM_PWR_LP_TO_ACTIVE_WAIT_BEFORE_US); + + while((0u == _FLD2VAL(SRSS_PWR_CTL_ACT_REF_OK, SRSS->PWR_CTL)) && (0u != timeOut)) + { + timeOut--; + } + + if(0u == timeOut) + { + retVal = CY_SYSPM_TIMEOUT; + } + + /* Configure the normal operation mode */ + SRSS->PWR_CTL &= (uint32_t) (~_VAL2FLD(SRSS_PWR_CTL_BGREF_LPMODE, 1u)); + + /* This wait time allows the settle Active Reference */ + Cy_SysLib_DelayUs(CY_SYSPM_PWR_LP_TO_ACTIVE_WAIT_AFTER_US); + + Cy_SysLib_ExitCriticalSection(interruptState); + + /* Call registered callback functions with CY_SYSPM_AFTER_EXIT + * parameter. Return value is ignored. + */ + if(0u != currentRegisteredCallbacksNumber) + { + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_EXIT_LP_MODE, CY_SYSPM_AFTER_EXIT, 0u); + } + } + else + { + /* Execute callback functions with CY_SYSPM_CHECK_FAIL parameter to + * undo everything done in the CY_SYSPM_CHECK_READY callback. Return + * value is ignored. + */ + (void) Cy_SysPm_ExecuteCallback(CY_SYSPM_EXIT_LP_MODE, CY_SYSPM_CHECK_FAIL, (uint32_t) retVal); + retVal = CY_SYSPM_FAIL; + } + } + else + { + /* Do nothing as device is already in active power mode. */ + } + return retVal; +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_SleepOnExit +****************************************************************************//** +* +* Set Sleep on the Exit mode. +* +* This API gives a possibility to keep the system in a sleep mode at all times +* and only wakeup to run a single interrupt and then immediately go back to +* sleep. +* +* \param +* enable true - enable Sleep on the Exit mode
false - disable +* Sleep on the Exit mode. +* +*******************************************************************************/ +void Cy_SysPm_SleepOnExit(bool enable) +{ + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + + if(enable) + { + /* Enable SleepOnExit mode */ + SCB->SCR |= _VAL2FLD(SCB_SCR_SLEEPONEXIT, 1u); + } + else + { + /* Disable SleepOnExit mode */ + SCB->SCR &= ((uint32_t) ~(_VAL2FLD(SCB_SCR_SLEEPONEXIT, 1u))); + } + Cy_SysLib_ExitCriticalSection(interruptState); +} + +#if(0u != SRSS_SIMOBUCK_PRESENT) + /******************************************************************************* + * Function Name: Cy_SysPm_SwitchToSimoBuck + ****************************************************************************//** + * + * Switch the power supply regulator to Single-Input Multiple Output (SIMO) + * Buck regulator instead of Linear Regulator. The SIMO Buck core regulator + * can supply Vccd with higher efficiency than the Linear core regulator (LDO) + * under some conditions, such as high external supply voltages. + * + * Before change from LDO to SIMO buck ensure that: + * * Circuit board has connected Vccbuck1 to Vccd and also populated the + * necessary external components for SIMO Buck regulator, including an + * inductor and a capacitor for each output. + * Refer to the device TRM for more details. + * + * * Operating frequencies are reduced so it is within the static timing + * closure limits at the new frequency. + * + * * Current consumption on the core is reduced to meet 0.9 V (nominal) output + * voltage. The main reason is that while changing from LDO to SIMO Buck, + * the switch happens on 0.9 V (nominal). + * + * * Appropriate Wait states values are set for Flash using the + * Cy_SysLib_SetWaitStates() function. Refer to the System Library (syslib) driver + * for more details. + * + * In general, use the next sequence to obtain SIMO Buck 0.9 V (nominal): + * 1) Set appropriate wait states for ULP by calling + * Cy_SysLib_SetWaitStates(true, hfClkFreqMz), where hfClkFreqMz - + * desired frequency of HfClk0 in MHz. + * + * 2) Set 0.9 V (nominal) for LDO regulator. + * + * 3) Switch the regulators by calling the Cy_SysPm_SwitchToSimoBuck() function. + * + * To obtain SIMO Buck 1.1 V (nominal) use next sequence: + * 1) Set appropriate wait states for ULP by calling + * Cy_SysLib_SetWaitStates(true, hfClkFreqMz), where hfClkFreqMz - + * desired frequency of HfClk0 in MHz + * + * 2) Set 0.9 V (nominal) for LDO regulator + * + * 3) Switch the regulators by calling the Cy_SysPm_SwitchToSimoBuck() function + * + * 4) Change SIMO Buck output voltage by calling the + * Cy_SysPm_SimoBuckSetVoltage1(CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_1_1V) + * + * 5) Set appropriate wait states for LP by calling + * Cy_SysLib_SetWaitStates(false, hfClkFreqMz), where hfClkFreqMz - + * desired frequency of HfClk0 in MHz + * + * \warning System does not have a way to know when Vccd is settled at actual + * 0.9 V or 1.1 V for transition, as this voltage depends on conditions + * including load current. The firmware works with + * nominal 0.9 V and 1.1 V voltages. + * + * \warning Please be aware that the Flash access time when core + * output voltage is 0.9 V (nominal) is longer that using 1.1 V (nominal). + * Therefore the clock to the Flash should be decreased. Use the + * Cy_SysLib_SetWaitStates() function to set appropriate wait state values + * for Flash. Call the Cy_SysLib_SetWaitStates() function before + * Cy_SysPm_SwitchToSimoBuck() if you want to change voltage + * into 0.9 V (nominal). Call the Cy_SysLib_SetWaitStates() function after + * Cy_SysPm_SwitchToSimoBuck() if you change voltage from 0.9 V (nominal) + * to 1.1 V (nominal). + * + * \warning There is no way to back to Linear Regulator after SIMO Buck + * regulator supply core. + * + * In addition if 0.9 V (nominal) output is set, the Flash works + * in Read only operation. + * + * If 1.1 V (nominal) output is set, the Flash works in Read and Write + * operation and clock frequencies may be increased up to the static + * timing closure limits for the new voltage. + * Refer to the device TRM for more details. + * + * \note + * Function is applicable for devices with SIMO Buck Regulator. + * + * Function does not have effect if SIMO Buck regulator is already enabled. + * + *******************************************************************************/ + void Cy_SysPm_SwitchToSimoBuck(void) + { + /* Check is the SIMO Buck regulator already enabled */ + if(!Cy_SysPm_SimoBuckIsEnabled()) + { + /* Disable the DeepSleep, nWell, and Retention regulators */ + SRSS->PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_DPSLP_REG_DIS, 1u) | + _VAL2FLD(SRSS_PWR_CTL_RET_REG_DIS, 1u) | + _VAL2FLD(SRSS_PWR_CTL_NWELL_REG_DIS, 1u)); + + /* Configure SIMO Buck regulator */ + SRSS->PWR_BUCK_CTL = _CLR_SET_FLD32U((SRSS->PWR_BUCK_CTL), + SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, + (uint32_t) CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_0_9V); + + SRSS->PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_EN, 1u); + SRSS->PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN, 1u); + + /* Wait for SIMO Buck is stable */ + Cy_SysLib_DelayUs(CY_SYSPM_SIMO_BUCK_CORE_SUPPLY_STABLE_US); + + /* Disable linear regulator LDO as Vbuckout1 and LDO are shorted */ + SRSS->PWR_CTL |= _VAL2FLD(SRSS_PWR_CTL_LINREG_DIS, 1u); + } + } + + + /******************************************************************************* + * Function Name: Cy_SysPm_SimoBuckSetVoltage1 + ****************************************************************************//** + * + * Set the output 1 voltage for an SIMO Buck regulator that can supply cores. + * This output can supply cores instead of the Linear regulator. + * + * When changing from a higher voltage to a lower voltage make sure that: + * * Operating frequency is reduced so it is within the static timing closure + * limits at the new frequency. + * + * * Appropriate Wait states values are set for Flash using the + * Cy_SysLib_SetWaitStates() function. Refer to the System Library (syslib) driver + * for more details. + * + * \warning Please be aware that the Flash access time when core + * output voltage is 0.9 V (nominal) is longer that using 1.1 V (nominal). + * Therefore, the clock to the Flash should be decreased. + * + * In addition if 0.9 V (nominal) output is set, the Flash works in + * Read-only operation. + * + * When changing from a lower voltage to a higher voltage, make sure that + * appropriate wait states values are set for Flash using the + * Cy_SysLib_SetWaitStates() function. Refer to the System Library (syslib) driver + * for more details. + * + * If 1.1 V (nominal) output is set, the Flash works in Read and Write + * operations and clock frequency may now be increased up to the static + * timing closure limits for the new voltage. + * + * \warning System does not have a way to know when Vccd is settled at actual + * 0.9 V or 1.1 V for transition, as this voltage depends on conditions + * including load current. The firmware works with nominal + * 0.9 V and 1.1 V voltages. + * + * \param + * voltage Desired output 1 regulator voltage (Vccbuck1). + * See \ref cy_en_syspm_simo_buck_voltage1_t + * + *******************************************************************************/ + void Cy_SysPm_SimoBuckSetVoltage1(cy_en_syspm_simo_buck_voltage1_t voltage) + { + /* Check is the required voltage is equal to current voltage */ + if(voltage != Cy_SysPm_SimoBuckGetVoltage1()) + { + /* Set analog signal bit for flash before voltage is changed + * from 1.1V to 0.9V + */ + if(CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_0_9V == voltage) + { + Cy_SysPm_SetVoltageBitForFlash(true); + } + + /* The system may continue operating while the voltage on Vccd + * discharges to the new voltage. The time it takes to reach the + * new voltage depends on conditions, including the load current on + * Vccd and the external capacitor size. + */ + SRSS->PWR_BUCK_CTL = + _CLR_SET_FLD32U((SRSS->PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage); + + /* Delay for the supply to stabilize at the new voltage is required + * when changing from a lower voltage to a higher voltage. + */ + if(CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_1_1V == voltage) + { + Cy_SysLib_DelayUs(CY_SYSPM_SIMO_BUCK_IS_STABLE_US); + + /* Set analog signal bit for flash before voltage is changed + * from 0.9 V to 1.1 V. + */ + Cy_SysPm_SetVoltageBitForFlash(false); + } + } + } + + + /******************************************************************************* + * Function Name: Cy_SysPm_SimoBuckGetVoltage1 + ****************************************************************************//** + * + * Get current nominal output 1 voltage (Vccbuck1) of the SIMO Buck regulator. + * + * \note The actual device output 1 voltage (Vccbuck1) can be different from the + * actual voltage as actual voltage value depends on conditions including + * load current. + * + * \note The actual device output 1 voltage (Vccbuck1) can be different from the + * nominal voltage as actual voltage value depends on conditions including + * load current. + * + * \return + * Nominal output voltage 1 (Vccbuck1) of the SIMO Buck regulator. + * See \ref cy_en_syspm_simo_buck_voltage1_t. + * + *******************************************************************************/ + cy_en_syspm_simo_buck_voltage1_t Cy_SysPm_SimoBuckGetVoltage1(void) + { + uint32_t retVal; + retVal = _FLD2VAL(SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, SRSS->PWR_BUCK_CTL); + + return((cy_en_syspm_simo_buck_voltage1_t) retVal); + } + + + /******************************************************************************* + * Function Name: Cy_SysPm_EnableVoltage2 + ****************************************************************************//** + * + * Enable output 2 voltage (Vbuckrf) of the SIMO Buck regulator. The output 2 + * voltage (Vbuckrf) of the SIMO Buck regulator is used to supply the BLE HW block. + * + * The SIMO Buck regulator should be enabled before the Cy_SysPm_EnableVoltage2() + * function call. + * + * \note The function does not have effect if SIMO Buck regulator is disabled. + * + *******************************************************************************/ + void Cy_SysPm_EnableVoltage2(void) + { + if(!Cy_SysPm_SimoBuckIsEnabled()) + { + /* Enable SIMO Buck output 2 */ + SRSS->PWR_BUCK_CTL2 |= _VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, 1u); + + /* Wait until output is stable */ + Cy_SysLib_DelayUs(CY_SYSPM_SIMO_BUCK_BLE_SUPPLY_STABLE_US); + } + } + + + /******************************************************************************* + * Function Name: Cy_SysPm_EnableVoltage2 + ****************************************************************************//** + * + * Disable output 2 voltage (Vbuckrf) of the SIMO Buck regulator. The output 2 + * voltage (Vbuckrf) of the SIMO Buck regulator is used to supply the BLE HW block. + * + *******************************************************************************/ + void Cy_SysPm_DisableVoltage2(void) + { + /* Disable Vbuck2 output */ + SRSS->PWR_BUCK_CTL2 &= ((uint32_t) ~ (_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, 1u))); + } + + + /******************************************************************************* + * Function Name: Cy_SysPm_SimoBuckSetVoltage2 + ****************************************************************************//** + * + * Set current voltage 2 voltage of the SIMO Buck regulator. + * + * \param + * voltage voltage of Linear regulator. + * See \ref cy_en_syspm_simo_buck_voltage2_t. + * + *******************************************************************************/ + void Cy_SysPm_SimoBuckSetVoltage2(cy_en_syspm_simo_buck_voltage2_t voltage) + { + if(voltage != Cy_SysPm_SimoBuckGetVoltage2()) + { + SRSS->PWR_BUCK_CTL2 = + _CLR_SET_FLD32U((SRSS->PWR_BUCK_CTL2), SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL, (uint32_t) voltage); + + Cy_SysLib_DelayUs(CY_SYSPM_SIMO_BUCK_IS_STABLE_US); + } + + } + + + /******************************************************************************* + * Function Name: Cy_SysPm_SimoBuckGetVoltage2 + ****************************************************************************//** + * + * Get current output 2 voltage (Vbuckrf) of the SIMO Buck regulator. + * + * \note The actual device output 2 voltage (Vbuckrf) can be different from the + * nominal voltage as actual voltage value depends on conditions including + * load current. + * + * \return + * Nominal output voltage of the SIMO Buck regulator output 2 voltage (Vbuckrf). + * See \ref cy_en_syspm_simo_buck_voltage2_t. + * + *******************************************************************************/ + cy_en_syspm_simo_buck_voltage2_t Cy_SysPm_SimoBuckGetVoltage2(void) + { + uint32_t retVal; + retVal = _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL, SRSS->PWR_BUCK_CTL2); + + return((cy_en_syspm_simo_buck_voltage2_t) retVal); + } + + + /******************************************************************************* + * Function Name: Cy_SysPm_SimoBuckOutputIsEnabled + ****************************************************************************//** + * + * Get current output status of the SIMO Buck outputs. + * + * \param + * output SIMO Buck regulator output. See \ref cy_en_syspm_buck_out_t. + * + * \return + * current state of requested output. True if requested output is enabled. + * False if requested output is disabled. + * + *******************************************************************************/ + bool Cy_SysPm_SimoBuckOutputIsEnabled(cy_en_syspm_buck_out_t output) + { + bool retVal; + if(output == CY_SYSPM_BUCK_VBUCK_1) + { + retVal = ((0u != _FLD2VAL(SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN, SRSS->PWR_BUCK_CTL)) ? true : false); + } + else + { + if((0u != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, SRSS->PWR_BUCK_CTL2)) || + (0u != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN, SRSS->PWR_BUCK_CTL2))) + { + retVal = true; + } + else + { + retVal = false; + } + } + return(retVal); + } + + + /******************************************************************************* + * Function Name: Cy_SysPm_SimoBuckIsEnabled + ****************************************************************************//** + * + * Get current status of SIMO Buck regulator. + * + * \return + * current state of the SIMO Buck regulator. True if SIMO Buck regulator is enabled, + * false if it is disabled + * + *******************************************************************************/ + bool Cy_SysPm_SimoBuckIsEnabled(void) + { + return((0u !=_FLD2VAL(SRSS_PWR_BUCK_CTL_BUCK_EN, SRSS->PWR_BUCK_CTL)) ? true : false); + } + + + /******************************************************************************* + * Function Name: Cy_SysPm_SimoBuckSetHwControl + ****************************************************************************//** + * + * Set hardware control for SIMO Buck output 2 (Vbuckrf) + * + * Hardware control for Vbuckrf output. When this bit is set, the value in + * BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the + * product has supporting hardware, it can directly control the enable signal + * for Vbuckrf. + * + * \param + * output enable/disable SIMO Buck regulator outputs, + * see \ref cy_en_syspm_buck_out. + * + *******************************************************************************/ + void Cy_SysPm_SimoBuckSetHwControl(bool hwControl) + { + if(hwControl) + { + SRSS->PWR_BUCK_CTL2 |= _VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, 1u); + } + else + { + SRSS->PWR_BUCK_CTL2 &= ((uint32_t)~(_VAL2FLD(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, 1u))); + } + } + + + /******************************************************************************* + * Function Name: Cy_SysPm_SimoBuckGetHwControl + ****************************************************************************//** + * + * Get hardware control for Vbuckrf + * + * Hardware control for Vbuckrf output. When this bit is set, the value in + * BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the + * product has supporting hardware, it can directly control the enable signal + * for Vbuckrf. + * + * \return + * true if HW control is set, false if FW control is set for SIMO Buck output 2 + * + *******************************************************************************/ + bool Cy_SysPm_SimoBuckGetHwControl(void) + { + return((0u != _FLD2VAL(SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL, SRSS->PWR_BUCK_CTL2)) ? true : false); + } + +#endif /* (0u != SRSS_SIMOBUCK_PRESENT) */ + + +/******************************************************************************* +* Function Name: Cy_SysPm_LdoSetVoltage +****************************************************************************//** +* +* Set the voltage on linear regulator (LDO). +* When changing from a higher voltage to a lower voltage make sure that: +* * Operating frequencies are reduced so these are within the static timing +* closure limits at the new frequency. +* +* * Current consumption on core is reduced to meet new output voltage. +* +* * Appropriate Wait states values are set for Flash using the +* Cy_SysLib_SetWaitStates() function. Refer to the System Library (syslib) driver +* for more details. +* +* \warning Please be aware that the Flash access time in condition that core +* output voltage is 0.9 V (nominal) is longer that using 1.1 V (nominal). +* Therefore the clock to the Flash should be decreased. +* +* In addition if 0.9 V (nominal) output is set, the Flash works in Read +* only operation. +* +* When changing from a lower voltage to a higher voltage make sure that +* appropriate Wait states values is set for Flash using the +* Cy_SysLib_SetWaitStates() function. Refer to System Library (syslib) driver +* for more details. +* +* If 1.1 V (nominal) output is set, the Flash works in Read and Write +* operations. Clock frequency may now be increased up to the static +* timing closure limits for the new voltage. +* +* \note The actual device Vccd voltage can be different from the +* nominal voltage as actual voltage value depends on conditions including +* load current. +* +* \param +* voltage Desired output regulator voltage. +* See \ref cy_en_syspm_ldo_voltage_t voltage +* +*******************************************************************************/ +void Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage) +{ + if(voltage != Cy_SysPm_LdoGetVoltage()) + { + /* Set analog signal bit for flash before voltage is changed + * from 1.1V to 0.9V + */ + if(CY_SYSPM_LDO_VOLTAGE_0_9V == voltage) + { + Cy_SysPm_SetVoltageBitForFlash(true); + } + + /* The system may continue operating while the voltage on Vccd + * discharges to the new voltage. The time it takes to reach the + * new voltage depends on conditions, including the load current on + * Vccd and the external capacitor size + */ + SRSS->PWR_TRIM_PWRSYS_CTL = + _CLR_SET_FLD32U((SRSS->PWR_TRIM_PWRSYS_CTL), SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, voltage); + + if(CY_SYSPM_LDO_VOLTAGE_1_1V == voltage) + { + /* Delay for the supply to stabilize at the new higher voltage */ + Cy_SysLib_DelayUs(CY_SYSPM_LDO_IS_STABLE_US); + + /* Set analog signal bit to flash macro register after output voltage is 1.1 V */ + Cy_SysPm_SetVoltageBitForFlash(false); + } + } +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_LdoGetVoltage +****************************************************************************//** +* +* Get current output voltage value of Linear regulator. +* +* \note The actual device Vccd voltage can be different from the +* nominal voltage as actual voltage value depends on conditions including +* load current. +* +* \return +* Nominal output voltage of the Linear regulator. +* See \ref cy_en_syspm_ldo_voltage_t. +* +*******************************************************************************/ +cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void) +{ + uint32_t retVal; + retVal = _FLD2VAL(SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM, SRSS->PWR_TRIM_PWRSYS_CTL); + + return((cy_en_syspm_ldo_voltage_t) retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_LdoIsEnabled +****************************************************************************//** +* +* Read the current status of Linear regulator. +* +* \return +* True means the Linear regulator is enabled. False means it is if disabled +* +*******************************************************************************/ +bool Cy_SysPm_LdoIsEnabled(void) +{ + return((0u != _FLD2VAL(SRSS_PWR_CTL_LINREG_DIS, SRSS->PWR_CTL)) ? false : true); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_WakeupPinLevel +****************************************************************************//** +* +* This function enables/disables wakeup pins and configure their active +* (high or low) level. +* +* A wake up from the Hibernate mode can be performed by toggling the wakeup pins, +* causing a normal boot procedure to occur. A wakeup is supported by up to +* two pins with programmable polarity. These pins may be connected to IO pins +* or on-chip peripherals under some conditions. +* Setting the wakeup pin to this level will cause a wakeup from the Hibernate +* mode. The wakeup pins are active-low by default. +* +* Configure only one pin at one API call. +* +* \param +* pinNum Selects the wakeup pin. The valid range is [0-1]. The number of the pin. +* +* \param enPinLevel Selects polarity. See \ref cy_en_syspm_pinstate_t. +* +* pinNum value corresponds to an appropriate pin. For example, value 1 +* corresponds to second wakeup pin. For information about wakeup pin +* assignment in specific families devices, refer to the appropriate device +* TRM. +* +*******************************************************************************/ +void Cy_SysPm_WakeupPinLevel(uint32_t pinNum, cy_en_syspm_pinstate_t enPinLevel) +{ + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + + pinNum &= CY_SYSPM_PWR_MASK_HIBPIN_PIN_MASK; + + if (CY_SYSPM_PIN_HIGH_LEVEL == enPinLevel) + { + /* Set high level of selected wakeup pin */ + SRSS->PWR_HIBERNATE |= + _VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, (CY_SYSPM_WAKEUP_PIN_BIT << pinNum)) | + _VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, (CY_SYSPM_WAKEUP_PIN_BIT << pinNum)); + } + else if(CY_SYSPM_PIN_LOW_LEVEL == enPinLevel) + { + /* Set low level of selected wakeup pin */ + SRSS->PWR_HIBERNATE |= + _VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, (CY_SYSPM_WAKEUP_PIN_BIT << pinNum)); + + SRSS->PWR_HIBERNATE &= + ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, (CY_SYSPM_WAKEUP_PIN_BIT << pinNum))); + } + else + { + /* Disable selected wakeup pin */ + SRSS->PWR_HIBERNATE &= + ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, (CY_SYSPM_WAKEUP_PIN_BIT << pinNum))); + } + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_WakeupLpCompLevel +****************************************************************************//** +* +* This function is configure wakeup low-power comparators (LPComp) and +* assigns their active (high or low) level. +* +* A wake up from the Hibernate mode can be performed by toggling the LPComps, +* causing a normal boot procedure to occur. A wakeup is supported by up to +* two LPComps with programmable polarity. These LPComp may be connected to IO +* pins or on-chip peripherals under some conditions. +* Setting the LPComp to this level will cause a wakeup from the Hibernate +* mode. The wakeup LPComp are active-low by default. +* +* Configure one of the LPComps at one API call. +* +* \note The Low-power comparators should be configured and enabled before +* switching into the Hibernate low power mode. Refer to LPComp +* driver description for more details. +* +* \param +* lpCompNum Selects the LPComp. The valid range is [0-1]. The number of the LPComp. +* +* \param enLpCompLevel Selects polarity. See \ref cy_en_syspm_lpcomp_state_t. +* +* lpCompNum value corresponds to an appropriate LPComp. For example, value 1 +* corresponds to second LP Comparator. For information about wakeup LPComp +* assignment in specific families devices, refer to the appropriate device +* TRM. +* +*******************************************************************************/ +void Cy_SysPm_WakeupLpCompLevel(uint32_t lpCompNum, cy_en_syspm_lpcomp_state_t enLpCompLevel) +{ + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + + lpCompNum &= CY_SYSPM_LPCOMPARATOR_MASK; + + if(CY_SYSPM_LPCOMP_HIGH_LEVEL == enLpCompLevel) + { + /* Set high level of selected wakeup pin */ + SRSS->PWR_HIBERNATE |= + _VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, CY_SYSPM_LPCOMPARATOR_BIT << lpCompNum) | + _VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, (CY_SYSPM_LPCOMPARATOR_BIT << lpCompNum)); + } + else if(CY_SYSPM_LPCOMP_LOW_LEVEL == enLpCompLevel) + { + /* Set low level of selected wakeup pin */ + SRSS->PWR_HIBERNATE |= + _VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, (CY_SYSPM_LPCOMPARATOR_BIT << lpCompNum)); + + SRSS->PWR_HIBERNATE &= + ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_POLARITY_HIBPIN, (CY_SYSPM_LPCOMPARATOR_BIT << lpCompNum))); + } + else + { + /* Disable selected wakeup pin */ + SRSS->PWR_HIBERNATE &= + ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBPIN, (CY_SYSPM_LPCOMPARATOR_BIT << lpCompNum))); + } + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_WakeupWdt +****************************************************************************//** +* +* This function enables/disables the Watchdog (WDT) to wake up the device from +* Hibernate power mode after WDT interrupt. +* +* \note The WDT should be configured and enabled before entering into Hibernate +* power mode. +* +* A wakeup from the Hibernate mode can be performed by the Watchdog interrupt, +* causing a normal boot procedure to occur. +* The wakeup is performed by a WDT interrupt and a normal boot procedure +* after device reset. Device can wake up from Hibernate after WDT device reset, +* if WDT was not configured to wake up the device on its interrupt and WDT +* was enabled. +* Refer to Watchdog Timer (WDT) driver description for more details. +* +* \param +* configureWdt true if WDT interrupt should wake up device from Hibernate and
+* false if WDT interrupt should not wake up device from Hibernate. +* +*******************************************************************************/ +void Cy_SysPm_WakeupWdt(bool configureWdt) +{ + if(configureWdt) + { + SRSS->PWR_HIBERNATE |= _VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBWDT, 1u); + } + else + { + SRSS->PWR_HIBERNATE &= ((uint32_t) (~_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBWDT, 1u))); + } +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_WakeupRtc +****************************************************************************//** +* +* This function enables/disables the alarms from RTC to wake up the device from +* Hibernate power mode after RTC alarm assert. +* +* \note The RTC alarm should be configured and enabled before entering into +* Hibernate power mode. +* +* A wakeup from the Hibernate mode can be performed by the RTC alarm, +* causing a normal boot procedure to occur. +* The wakeup is performed by the RTC alarm and a normal boot procedure +* after device reset. +* Refer to Real-Time Clock (RTC) driver description for more details. +* +* \param +* configureRtc true if RTC alarm should wake up device from Hibernate
+* false if RTC alarm should not wake up device from Hibernate +* +*******************************************************************************/ +void Cy_SysPm_WakeupRtc(bool configureRtc) +{ + if(configureRtc) + { + SRSS->PWR_HIBERNATE |= _VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBALARM, 1u); + } + else + { + SRSS->PWR_HIBERNATE &= ((uint32_t) ~_VAL2FLD(SRSS_PWR_HIBERNATE_MASK_HIBALARM, 1u)); + } +} + + + +/******************************************************************************* +* Function Name: Cy_SysPm_RegisterCallback +****************************************************************************//** +* +* Registers a new syspm callback. +* +* \note The registered callbacks will be executed in order of how callbacks were +* registered: the first registered callback will be always the first executed. And the +* last registered callback will be executed as the last callback. +* +* A callback is a function called after an event in a driver or +* middleware-module has occurred. The handler callback API will be executed if +* specific event occurs. See \ref cy_stc_syspm_callback_t. +* +* \param +* handler syspm callback structure. See \ref cy_stc_syspm_callback_t. +* +* \return +* True: callback was registered;
+* False: callback was not registered. +* +* It is allowed to register up to 32 callbacks. +* +*******************************************************************************/ +bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler) +{ + uint32_t interruptState; + volatile bool regCallbackReturnValue = true; + cy_stc_syspm_callback_t* currentCallback = callbackRoot; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + /* Check if the maximum callbacks were registered */ + if((CY_SYSPM_PWR_MAX_CALLBACKS_NUMBER > currentRegisteredCallbacksNumber) && + (handler->Callback != NULL)) + { + /* Check if was at least one callback registered */ + if(callbackRoot == NULL) + { + callbackRoot = handler; + handler->nextItm = NULL; + + currentRegisteredCallbacksNumber++; + } + else + { + /* Check was the required callback already registered */ + while(regCallbackReturnValue && (currentCallback->nextItm != NULL)) + { + if((currentCallback == handler) && (currentCallback->base == handler->base)) + { + /* Condition to switch-off from checking loop and return false as requested callback is + * already registered + */ + regCallbackReturnValue = false; + } + + currentCallback = currentCallback->nextItm; + } + + /* Check last element of callback list */ + if((currentCallback == handler) && (currentCallback->base == handler->base)) + { + /* Condition to switch of from checking and return false */ + regCallbackReturnValue = false; + } + + if(false != regCallbackReturnValue) + { + /* Condition when last registered callback was found */ + currentCallback->nextItm = handler; + handler->nextItm = NULL; + + currentRegisteredCallbacksNumber++; + } + } + } + else + { + regCallbackReturnValue = false; + } + Cy_SysLib_ExitCriticalSection(interruptState); + + return(regCallbackReturnValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_UnregisterCallback +****************************************************************************//** +* +* Unregister a callback. +* +* The registered callback can be unregistered. Otherwise, false will be +* returned. +* +* \param +* handler the list item and callback handler. See +* \ref cy_stc_syspm_callback_t. +* +* \return +* True: on success
+* False: if it was not unregistered. +* +*******************************************************************************/ +bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t* handler) +{ + uint32_t interruptState; + volatile bool unRegCallbackValue; + volatile bool unRegCallbackCheckStatus; + + cy_stc_syspm_callback_t* currentCallback = callbackRoot; + cy_stc_syspm_callback_t* nextCallback; + + unRegCallbackCheckStatus = true; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + /* Check if was at least one callback registered */ + if(0u != currentRegisteredCallbacksNumber) + { + if((callbackRoot == handler) && (callbackRoot->base == handler->base)) + { + callbackRoot = callbackRoot->nextItm; + unRegCallbackCheckStatus = false; + unRegCallbackValue = true; + currentRegisteredCallbacksNumber--; + } + + while(unRegCallbackCheckStatus && (currentCallback != NULL)) + { + /* Searching callback by handler */ + if(currentCallback->nextItm == handler) + { + nextCallback = currentCallback->nextItm; + + /* Check is it required callback by it address */ + if((nextCallback->base == handler->base) && (currentCallback->nextItm == handler)) + { + currentCallback->nextItm = handler->nextItm; + unRegCallbackCheckStatus = false; + unRegCallbackValue = true; + currentRegisteredCallbacksNumber--; + } + } + else + { + unRegCallbackValue = false; + } + currentCallback = currentCallback->nextItm; + } + } + else + { + unRegCallbackValue = false; + } + Cy_SysLib_ExitCriticalSection(interruptState); + + return(unRegCallbackValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_ExecuteCallback +****************************************************************************//** +* +* Internal API that executes all registered callbacks with type. +* \note The registered callbacks will be executed in order of how callbacks were +* registered: the first registered callback will be first executed. And the +* last registered callback will be executed as the last callback. +* +* Executed callbacks in the registered callback list from index 0 to index +* lastCallback-1. If lastCallback = 0 then all callbacks are executed. Callbacks +* are executed until the first one that returns CY_SYSPM_FAIL. Returns the +* index+1 of the callback that failed. If no callbacks are registered, returns +* CY_SYSPM_SUCCESS. +* +* \param +* type callback type. See \ref cy_en_syspm_callback_type_t. +* +* \param +* mode callback mode. See \ref cy_en_syspm_callback_mode_t. +* +* \param +* lastCallback Index+1 of last registered callback to execute. +* if lastCallback = 0 - Execute all registered callbacks +* +* \return +* CY_SYSPM_SUCCESS Callback successfully completed or nor callbacks registered. +* Something different than CY_SYSPM_SUCCESS - Index+1 of callback that failed. +* +*******************************************************************************/ +uint32_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, + cy_en_syspm_callback_mode_t mode, + uint32_t lastCallback) +{ + uint32_t executedCallbacksCounter = 0u; + uint32_t retVal = (uint32_t) CY_SYSPM_SUCCESS; + cy_stc_syspm_callback_t* currentCallback = callbackRoot; + + if(0u == lastCallback) + { + lastCallback = CY_SYSPM_PWR_MAX_CALLBACKS_NUMBER; + } + + while((currentCallback != NULL) && (retVal != ((uint32_t) CY_SYSPM_FAIL)) && (0u != lastCallback)) + { + if (currentCallback->type == type) + { + retVal = (uint32_t) currentCallback->Callback(currentCallback->base, currentCallback->content, mode); + executedCallbacksCounter++; + lastCallback--; + } + currentCallback = currentCallback->nextItm; + } + + /* Return Index+1 of callback that failed if callback function returned + * CY_SYSPM_FAIL + */ + if(retVal == (uint32_t) CY_SYSPM_FAIL) + { + retVal = executedCallbacksCounter; + } + return retVal; +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_GetIoFreezeStatus +****************************************************************************//** +* +* Checks whether IoFreeze is enabled. +* +* \return Returns TRUE if IOs are frozen
FALSE if IOs are unfrozen. +* +******************************************************************************/ +bool Cy_SysPm_GetIoFreezeStatus(void) +{ + return(0u != _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS->PWR_HIBERNATE)); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_IoFreeze +****************************************************************************//** +* +* Freezes IOs. +* +* Freezes IO-Cells directly to save the IO-Cell state on a wakeup from the +* Hibernate. You don't need to call this function before entering the +* Hibernate mode, because Cy_SysPm_Hibernate() function freezes IO-Cells +* implicitly. +* +******************************************************************************/ +void Cy_SysPm_IoFreeze(void) +{ + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + + /* Check the FREEZE state to avoid recurrent IO-Cells freeze attempt, + * because the second call to this function will cause an accidental switch + * to the Hibernate mode (the system will enter Hibernate mode immediately + * after writing to Hibernate bit because both UNLOCK and FREEZE were set + * correctly in previous call to this function). + */ + if(0u == _FLD2VAL(SRSS_PWR_HIBERNATE_FREEZE, SRSS->PWR_HIBERNATE)) + { + /* Clear unlock field for correct freeze of IO-Cells */ + SRSS->PWR_HIBERNATE = _CLR_SET_FLD32U((SRSS->PWR_HIBERNATE), SRSS_PWR_HIBERNATE_UNLOCK, 0u); + + /* Preserve last-reset reason and disable overriding by peripherals next + * pin-freeze command + */ + SRSS->PWR_HIBERNATE |= CY_SYSPM_PWR_HIBERNATE_UNLOCK | + _VAL2FLD(SRSS_PWR_HIBERNATE_FREEZE, 1u) | + _VAL2FLD(SRSS_PWR_HIBERNATE_HIBERNATE, 1u); + + /* If reading after writing, read this register three times to delay + * enough time for internal settling. + */ + (void) SRSS->PWR_HIBERNATE; + (void) SRSS->PWR_HIBERNATE; + + /* Second write causes freeze of IO-Cells to save IO-Cell state */ + SRSS->PWR_HIBERNATE = SRSS->PWR_HIBERNATE; + } + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_IoUnfreeze +****************************************************************************//** +* +* Unfreezes the IOs. +* +* The IO-Cells remain frozen after awaking from the Hibernate mode until the +* firmware unfreezes them after booting. The call of this function unfreezes the +* IO-Cells explicitly. +* +* If the firmware intent is to retain the data value on the port, then the +* value must be read and re-written to the data register before calling this +* API. Furthermore, the drive mode must be re-programmed. If this is not done, +* the pin state will change to default state the moment the freeze is removed. +* +*******************************************************************************/ +void Cy_SysPm_IoUnfreeze(void) +{ + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + + /* Preserve last reset reason and wakeup polarity. Then, unfreeze I/O: + * write PWR_HIBERNATE.FREEZE=0, .UNLOCK=0x3A, .HIBERANTE=0, + */ + SRSS->PWR_HIBERNATE = + CY_SYSPM_PWR_HIBERNATE_UNLOCK | (SRSS->PWR_HIBERNATE & CY_SYSPM_PWR_RETAIN_HIBERNATE_STATUS); + + /* If reading stands after writing, read this register three times to delay + * enough time for internal settling. + */ + (void) SRSS->PWR_HIBERNATE; + (void) SRSS->PWR_HIBERNATE; + + /* Lock HIBERNATE mode: write PWR_HIBERNATE.HIBERNATE=0, UNLOCK=0x00, HIBERANTE=0, .TOKEN */ + SRSS->PWR_HIBERNATE &= CY_SYSPM_PWR_RETAIN_HIBERNATE_STATUS; + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_SetDelayAfterDeepSleep +****************************************************************************//** +* +* \Internal function for setting the delay after switching the device from +* DeepSleep power mode. +* +* If ECO or PLL is enabled, the 17 us delay should be +* configured before entering into the DeepSleep. If ECO or PLL are +* disabled, the delay is not required. +* +*******************************************************************************/ +static void Cy_SysPm_SetDelayAfterDeepSleep(void) +{ + uint32_t clkPath = 0u; + uint32_t waitClocks = 0u; + + if (_FLD2VAL(SRSS_CLK_ECO_CONFIG_ECO_EN, SRSS->CLK_ECO_CONFIG) == 0u) + { + while((CY_SYSPM_PWR_MAX_PLL_NUMBER > clkPath) && (CY_SYSPM_PWR_TRIM_WAKE_CNTS != waitClocks)) + { + if(_FLD2VAL(SRSS_CLK_PLL_CONFIG_ENABLE, SRSS->CLK_PLL_CONFIG[clkPath]) != 0u) + { + waitClocks = CY_SYSPM_PWR_TRIM_WAKE_CNTS; + } + clkPath++; + } + } + else + { + waitClocks = CY_SYSPM_PWR_TRIM_WAKE_CNTS; + } + + if(0u != waitClocks) + { + SRSS->PWR_TRIM_WAKE_CTL = + _CLR_SET_FLD32U((SRSS->PWR_TRIM_WAKE_CTL), SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY, waitClocks); + } +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_SetVoltageBitForFlash +****************************************************************************//** +* +* Internal function that changes the Vcc setting for flash. +* +* \param +* setBit set/clear bit for flash macro register. This bit should be set when +* voltage for core regulators is less than 0.99 V. This bit should be set if +* output voltage for core regulators is higher than 0.99 V. +* +* +*******************************************************************************/ +static void Cy_SysPm_SetVoltageBitForFlash(bool setBit) +{ + if(setBit) + { + FLASHC_FM_CTL->ANA_CTL0 |= _VAL2FLD(FLASHC_FM_CTL_ANA_CTL0_VCC_SEL, 1u); + } + else + { + FLASHC_FM_CTL->ANA_CTL0 &= ((uint32_t) (~_VAL2FLD(FLASHC_FM_CTL_ANA_CTL0_VCC_SEL, 1u))); + } +} + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syspm/cy_syspm.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syspm/cy_syspm.h new file mode 100644 index 0000000000..1c70f0e65c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/syspm/cy_syspm.h @@ -0,0 +1,820 @@ +/***************************************************************************//** +* \file cy_syspm.h +* \version 1.0 +* +* Provides the function definitions for the power management API. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* +*******************************************************************************/ + +/** +* \defgroup group_syspm System Power Management (SysPm) +* \{ +* Power Modes +* +* Devices support the following power modes (in the order of +* high-to-low power consumption): Active, Sleep, Low Power (LP) Active, +* LP Sleep, DeepSleep, and Hibernate. +* Active and Sleep are the standard ARM-defined power modes, supported by the +* ARM CPUs. +* DeepSleep is a lower-power mode where high-frequency clocks are disabled. +* Most of the register state is retained and the platform supports saving a +* configurable amount of the SRAM state. +* Hibernate is an even lower power mode that is entered from firmware, +* just like DeepSleep. However, on a wakeup the CPU and all peripherals go +* through a full reset. +* +* The power mode library is used to enter low-power states to reduce system +* power consumption in power sensitive designs. This library allows the user to +* individually power down each CPU into Sleep or DeepSleep. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
CM0+ ModeCM4 ModePower Mode (SRSS)Mode Description
ActiveActiveNormalAll Clocks and peripherals may operate or optionally can +* be disabled. Current load limitation is set as for +* active power mode(*1).
SleepActiveNormalAll Clocks and peripherals may operate or optionally can +* be disabled. Current load limitation is set as for +* active power mode(*1).
DeepSleepActiveNormalAll Clocks and peripherals may operate or optionally can +* be disabled. Current load limitation is set as for +* active power mode(*1).
SleepSleepNormalAll Clocks and peripherals may operate, CPUs Off. Current load +* limitation is set as for active power mode(*1).
DeepSleepSleepNormalAll Clocks and peripherals may operate, CPUs Off. Current load +* limitation is set as for active power mode(*1).
ActiveDeepSleepNormalAll Clocks and peripherals may operate or optionally can +* be disabled. Current load limitation is set as for +* active power mode(*1).
SleepDeepSleepNormalAll Clocks and peripherals may operate, CPUs Off. Current load +* limitation is set as for active power mode(*1).
DeepSleepDeepSleepDeepSleepAll the MHz clocks are off, but so is the DSI routing, and most Analog +* and voltage references are off by default. Only ILO/WCO may operate, +* limited peripherals.
Active (LPActive)Active (LPActive)Low powerAll the MHz clocks frequencies are decreased to meet current load +* limitations (*1). Peripherals are also slowed and optionally disabled +* to meet current load limitations in LPActive power mode.
Sleep (LPSleep)Active (LPActive)Low powerAll the MHz clocks frequencies are decreased to meet current load +* limitations (*1). Peripherals are also slowed and optionally disabled +* to meet current load limitations in LPActive power mode.
DeepSleepActive (LPActive)Low powerAll the MHz clocks frequencies are decreased to meet current load +* limitations (*1). Peripherals are also slowed and optionally disabled +* to meet current load limitations in LPActive power mode.
Active (LPActive)Sleep (LPSleep)Low powerAll the MHz clocks frequencies are decreased to meet current load +* limitations (*1). Peripherals are also slowed and optionally disabled +* to meet current load limitations in LPActive power mode.
Sleep (LPSleep)Sleep (LPSleep)Low powerAll the MHz clocks frequencies are decreased to meet current load +* limitations (*1). Peripherals are also slowed and optionally disabled +* to meet current load limitations in LPActive power mode. +* CPUs are off.
DeepSleepSleep (LPSleep)Low powerAll the MHz clocks frequencies are decreased to meet current load +* limitations (*1). Peripherals are also slowed and optionally disabled +* to meet current load limitations in LPActive power mode. +* CPUs are off
Active (LPActive)DeepSleepLow powerAll the MHz clocks frequencies are decreased to meet current load +* limitations (*1). Peripherals are also slowed and optionally disabled +* to meet current load limitations in LPActive power mode.
DeepSleepDeepSleepDeepSleepThe entire chip is in a DeepSleep mode, since it forces the MHz +* clocks, DSI, UDBs, most peripherals, analog, etc., to be shut down. +* Only ILO/WCO may operate, limited peripherals
--HibernateOnce Hibernate mode is set, everything goes into Hibernate mode. +* Only ILO may operate to assert wake-up device using WDT or RTC.
+* +* (*1) For more details about power modes and current load limitations refer to +* the device Technical Reference Manual (TRM). +* +* Power modes: +* * Active - In this mode the CPU executes code, and all logic and memories +* are powered. Firmware may decide to disable clocks for specific peripherals +* and to power down specific analog power domains. The chip enters Active upon +* initial reset. For internally-generated resets, the chip enters the most +* recently used power mode among Active and LPActive. +* +* * Sleep - In this mode the CPU does not execute code and its clock is +* stopped. It is identical to ACTIVE from a peripheral point of view. +* +* * LPActive - LPActive (Low Power Active) is similar to Active, with clock +* restrictions and limited/slowed peripheral to achieve a lower system current. +* +* * LPSleep - LPSleep (Low Power Sleep) mode operates the same as Sleep mode +* with the clocking limitations of LPActive mode to further reduce system power. +* +* * DeepSleep - In DeepSleep mode the main system clock is off for CPU, Flash, +* and high-speed logic. Optionally, the low frequency (32.768 kHz) clock +* remains on, and low-frequency peripherals continue operating. +* Peripherals that do not need a clock or receive a clock from their external +* interface (e.g., I2C/SPI) continue operating, and all circuits that draw +* current from the Vccdpslp supply are subject to the current sourcing +* limitations of the DeepSleep Regulator (if the core is supplied by the +* Linear core regulator). If the core is supplied by the SIMO Buck regulator all +* deepsleep peripherals are supplied by Vbuck1. +* A normal wakeup from DeepSleep returns to either LPActive, LPSleep, Active, or +* Sleep, depending on the previous state and programmed behavior for the +* configured wakeup interrupt. +* Likewise, a debug wakeup from DeepSleep returns to LPSleep or Sleep, depending +* on which mode was used to enter DeepSleep. +* +* * Hibernate - Is the lowest power mode available when external supplies are +* present. It is intended for applications in a dormant state. +* Hibernate is implemented using high voltage logic and switches off all +* internal regulators. The Backup domain continues functioning normally. +* The I/O's state is frozen so that the output driver state is held. +* Note in this mode the CPU and all peripherals lose state, so the system and +* firmware reboot on a wakeup event. +* Wakeup is supported from device specific pin(s) with programmable +* polarity. Additionally, unregulated peripherals can wake the device under +* some conditions. For example, a low-power comparator can wake the device by +* comparing two external voltages but may not support comparison to an +* internally-generated voltage. The Backup domain remains functional, and if +* present it can schedule an alarm to wake the device from Hibernate using RTC. +* The combination of Hibernate and Backup alarms can yield low current duty +* cycling for applications, such as waking once per second for a CapSense +* scan. Alternatively, the Watchdog Timer (WDT) can be configured to wake-up the device by +* WDT interrupt. +* Backup memory (BMEM) can be used to store system state for use on the +* next reboot. +* +* The system can wakeup from Hibernate power mode by configuring: +* * Wakeup pins +* * WDT interrupt +* * LPComparator +* * WDT reset - this can be configured without using the syspm driver. Just +* configure and enable the WDT before entering Hibernate power mode. All +* other events require use of the API from the syspm driver. +* +* * XRES - is the state of the part when XRES is applied. This is obviously a +* reset condition, but it is also considered a power mode because some low-power +* applications, such as remote controls, expect very low current consumption +* when XRES is asserted. +* +* * OFF - The OFF state simply represents the state of the part with no power +* applied to it (except perhaps the Backup domain). In some applications, power +* to the device will be switched on and off by another device in the system to +* make the product implement the lowest power consumption level. +* +* Wakeup time after a reset is device-dependent because of the boot run-time. +* The wakeup time varies depending on the number and type of trim parameters and +* the size of device Flash. +* +* For ARM-based devices, an interrupt is required for the CPU to +* wake up. +* +* * All pending interrupts should be cleared before the device is put into a +* low-power mode, even if they are masked. +* +* \section group_syspm_section_configuration Configuration Considerations +* After initial device boot the device goes into Active power mode. After some +* code execution the device could be sent into low power modes. The +* Cy_SysPm_Sleep() and Cy_SysPm_DeepSleep() functions only switch the core that +* calls the function into Sleep or DeepSleep. To set the whole device into Sleep +* or DeepSleep device, ensure that each core calls the sleep functions. +* +* There are situations when the device does not switch into DeepSleep power +* mode immediately after the second core calls Cy_SysPm_DeepSleep(). The device +* will switch into DeepSleep mode automatically a little bit later, after the +* low-power circuits are ready to switch into DeepSleep. +* Refer to the Cy_SysPm_DeepSleep() description for more details. +* +* If you call Cy_SysPm_Hibernate() the device will be switched +* into Hibernate power mode directly, as there is no handshake between cores. +* +* Before switching into LPActive power mode ensure that the device meets the +* current load limitation by decreasing the Mhz clocks, and slowing or disabling +* peripherals. +* Refer to the device TRM for more details about current load limitations in +* different low-power modes. +* +* The syspm driver implements a syspm callbacks mechanism. Using a +* syspm callback, you can perform actions right before entering +* low-power mode, and directly after switching out of low-power mode. With the +* callback mechanism you can prevent switching into low power mode if, for +* example, some required peripheral is not ready to enter into requested +* low-power mode. +* +* Fill in the cy_stc_syspm_callback_t structure for each callback function. +* Each callback function is of the type cy_SysPMCallback. You assign +* the mode for each callback function. Refer to cy_en_syspm_callback_mode_t. +* Also refer to Cy_SysPm_Sleep(), Cy_SysPm_DeepSleep(), Cy_SysPm_EnterLpMode(), +* Cy_SysPm_ExitLpMode(), Cy_SysPm_Hibernate() for more details. +* +* Refer to Cy_SysPm_RegisterCallback() description for more details +* about registering a callback. You may have up to 32 callback functions. +* +* \section group_syspm_section_more_information More Information +* +* For more information on the Power Modes (syspm) driver, +* refer to the Technical Reference Manual (TRM). +* +* \section group_syspm_MISRA MISRA-C Compliance +* The syspm driver does not have any specific deviations. +* +* \section group_syspm_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_syspm_macro Macro +* \defgroup group_syspm_functions Functions +* \defgroup group_syspm_data_structures Data Structures +* \defgroup group_syspm_data_enumerates Enumerated types +*/ + +#ifndef _CY_SYSPM_H_ +#define _CY_SYSPM_H_ + +#include +#include +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* Register Constants +*******************************************************************************/ + +/** +* \addtogroup group_syspm_macro +* \{ +*/ + +/** Driver major version */ +#define CY_SYSPM_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_SYSPM_DRV_VERSION_MINOR 0 + +/** \cond INTERNAL */ + +/** Internal define for SysPm_DeepSleep() function */ +#define CY_SYSPM_PWR_TRIM_WAKE_CNTS (0x8Bu) + +/** Internal define for Cy_SysPm_ExitLpMode() function */ +#define CY_SYSPM_WAIT_DELAY_TRYES (100u) + +/** Internal define for SysPm_SwitchToSimoBuck() function */ +#define CY_SYSPM_1M_THRESHOLD (1000000u) + +/** Internal define for SysPm_WakeupPinLevel() function */ +#define CY_SYSPM_PWR_MASK_HIBPIN_PIN_MASK (0x03u) + +/** Internal define for SysPm_WakeupPinLevel() function */ +#define CY_SYSPM_WAKEUP_PIN_BIT (1ul) + +/* Internal define for Cy_SysPm_WakeupLpCompLevel() function */ +#define CY_SYSPM_LPCOMPARATOR_BIT (4ul) + +/* Define for mask for LPComs in Cy_SysPm_WakeupLpCompLevel() function */ +#define CY_SYSPM_LPCOMPARATOR_MASK (12u) + +/** \endcond */ + +/** syspm driver identifier */ +#define CY_SYSPM_ID (CY_PDL_DRV_ID(0x10u)) + +/** +* \defgroup group_syspm_return_status Power Mode Status +* \{ +* Current power mode status defines +*/ + +/** CM4 is Active */ +#define CY_SYSPM_STATUS_CM4_ACTIVE (0x01u) + +/** CM4 is in Sleep */ +#define CY_SYSPM_STATUS_CM4_SLEEP (0x02u) + +/** CM4 is in DeepSleep */ +#define CY_SYSPM_STATUS_CM4_DEEPSLEEP (0x04u) + +/** CM4 is Lop Power mode */ +#define CY_SYSPM_STATUS_CM4_LOWPOWER (0x80u) + +/** CM0 is Active */ +#define CY_SYSPM_STATUS_CM0_ACTIVE ((uint32_t) ((uint32_t)0x01u << 8u)) + +/** CM0 is in Sleep */ +#define CY_SYSPM_STATUS_CM0_SLEEP ((uint32_t) ((uint32_t)0x02u << 8u)) + +/** CM0 is in DeepSleep */ +#define CY_SYSPM_STATUS_CM0_DEEPSLEEP ((uint32_t) ((uint32_t)0x04u << 8u)) + +/** CM4 is in Low Power mode */ +#define CY_SYSPM_STATUS_CM0_LOWPOWER ((uint32_t) ((uint32_t)0x80u << 8u)) + +/** Device is in Low Power mode*/ +#define CY_SYSPM_STATUS_SYSTEM_LOWPOWER ((uint32_t) (CY_SYSPM_STATUS_CM0_LOWPOWER | (CY_SYSPM_STATUS_CM4_LOWPOWER))) + +/** \} group_syspm_return_status */ + +/** Define to update token to indicate Hibernate mode transition */ +#define CY_SYSPM_PWR_HIBERNATE_TOKEN_HIBERNATE (0xf1u) + +/** Wait time for transition device from Active into the LPActive */ +#define CY_SYSPM_PWR_ACTIVE_TO_LP_WAIT_US (1u) + +/** Wait time for transition device from Active into the LPActive before Active +* reference is settled +*/ +#define CY_SYSPM_PWR_LP_TO_ACTIVE_WAIT_BEFORE_US (8u) + +/** Wait time for transition device from Active into the LPActive after Active +* reference is settled +*/ +#define CY_SYSPM_PWR_LP_TO_ACTIVE_WAIT_AFTER_US (1u) + +/** Maximum callbacks number */ +#define CY_SYSPM_PWR_MAX_CALLBACKS_NUMBER (32u) + +/** Mask to unlock Hibernate mode */ +#define CY_SYSPM_PWR_HIBERNATE_UNLOCK ((uint32_t) 0x3Au << SRSS_PWR_HIBERNATE_UNLOCK_Pos) + +/** Mask to retain Hibernate status */ +#define CY_SYSPM_PWR_RETAIN_HIBERNATE_STATUS ((uint32_t) SRSS_PWR_HIBERNATE_TOKEN_Msk |\ + SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk |\ + SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk |\ + SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk |\ + SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk) + + +/** Maximum value of callbacks */ +#define CY_SYSPM_PWR_MAX_PLL_NUMBER (16u) + +/** Definition for delay of SIMO Buck supply regulator after it is enabled */ +#define CY_SYSPM_SIMO_BUCK_CORE_SUPPLY_STABLE_US (900u) + +/** Definition for delay of SIMO Buck output 2 */ +#define CY_SYSPM_SIMO_BUCK_BLE_SUPPLY_STABLE_US (600u) + +/** Definition for delay of Linear Regulator after it output voltage +* is changed +*/ +#define CY_SYSPM_LDO_IS_STABLE_US (9u) + +/** Definition for delay of core supply regulator after it output voltage +* is changed +*/ +#define CY_SYSPM_SIMO_BUCK_IS_STABLE_US (200u) +/** \} group_syspm_macro */ + +/******************************************************************************* +* Configuration Structures +*******************************************************************************/ + +/** +* \addtogroup group_syspm_data_enumerates +* \{ +*/ + +/** This enumeration is used to initialize the wakeup pin state */ +typedef enum +{ + CY_SYSPM_PIN_DISABLED, /**< Disable selected wakeup pin */ + CY_SYSPM_PIN_HIGH_LEVEL, /**< Configure high level for selected wakeup-pin */ + CY_SYSPM_PIN_LOW_LEVEL /**< Configure low level for selected wakeup-pin */ +} cy_en_syspm_pinstate_t; + + +/** This enumeration is used to initialize the Low-power Comparator +* (LPComp) state +*/ +typedef enum +{ + CY_SYSPM_LPCOMP_DISABLED, /**< Disable selected LPComp */ + CY_SYSPM_LPCOMP_HIGH_LEVEL, /**< Configure high level for selected LPComp */ + CY_SYSPM_LPCOMP_LOW_LEVEL /**< Configure low level for selected LPComp */ +} cy_en_syspm_lpcomp_state_t; + +/** +* This enumeration is used to initialize a wait action - an interrupt or +* event. Refer to the CMSIS for the WFE and WFI instruction explanations. +*/ +typedef enum +{ + CY_SYSPM_WAIT_FOR_INTERRUPT, /**< Wait for interrupt */ + CY_SYSPM_WAIT_FOR_EVENT /**< Wait for event */ +} cy_en_syspm_waitfor_t; + +/** +* The enumeration for core voltages for both the SIMO Buck and the +* Linear Regulator +*/ +typedef enum +{ + CY_SYSPM_LDO_VOLTAGE_0_9V = 0x05u, /**< 0.9 V nominal core voltage */ + CY_SYSPM_LDO_VOLTAGE_1_1V = 0x17u /**< 1.1 V nominal core voltage */ +} cy_en_syspm_ldo_voltage_t; + +/** +* The enumeration for core voltages for both the SIMO Buck and the +* Linear Regulator +*/ +typedef enum +{ + CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_0_9V = 0x01u, /**< 0.9 V nominal core voltage */ + CY_SYSPM_SIMO_BUCK_OUT1_VOLTAGE_1_1V = 0x05u /**< 1.1 V nominal core voltage */ +} cy_en_syspm_simo_buck_voltage1_t; + + +/** +* The enumeration for core voltages for both the SIMO Buck and the +* Linear Regulator +*/ +typedef enum +{ + CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_0_95V = 0u, /**< 0.95 V nominal core voltage */ + CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_0V, /**< 1.0 V nominal core voltage */ + CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_05V, /**< 1.05 V nominal core voltage */ + CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_1V, /**< 1.1 V nominal core voltage */ + CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_2V, /**< 1.2 V nominal core voltage */ + CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_3V, /**< 1.3 V nominal core voltage */ + CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_4V, /**< 1.4 V nominal core voltage */ + CY_SYSPM_SIMO_BUCK_OUT2_VOLTAGE_1_5V, /**< 1.5 V nominal core voltage */ +} cy_en_syspm_simo_buck_voltage2_t; + +/** +* The enumeration are used to configure SIMO Buck regulator outputs +*/ +typedef enum +{ + CY_SYSPM_BUCK_VBUCK_1, /**< SIMO Buck output 1 Voltage (Vback1) */ + CY_SYSPM_BUCK_VRF /**< SIMO Buck out 2 Voltage (Vbackrf) */ +} cy_en_syspm_buck_out_t; + +/** SysPm status definitions */ +typedef enum +{ + CY_SYSPM_SUCCESS = 0x00u, /**< Successful */ + CY_SYSPM_BAD_PARAM = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */ + CY_SYSPM_TIMEOUT = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x02u, /**< Time-out occurs */ + CY_SYSPM_INVALID_STATE = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0x03u, /**< Operation not setup or is in an + improper state */ + CY_SYSPM_FAIL = CY_SYSPM_ID | CY_PDL_STATUS_ERROR | 0xFFu /**< Unknown failure */ +} cy_en_syspm_status_t; + +/** +* This enumeration is used for selecting the low power mode on which the +* appropriate registered callback handler will be executed. For example, +* registered callback with type CY_SYSPM_SLEEP will be executed while +* switching into the Sleep power mode. +*/ +typedef enum +{ + CY_SYSPM_SLEEP, /**< Sleep enum callback type */ + CY_SYSPM_DEEPSLEEP, /**< DeepSleep enum callback type */ + CY_SYSPM_HIBERNATE, /**< Hibernate enum callback type */ + CY_SYSPM_ENTER_LP_MODE, /**< Enter LPActive mode enum callback type */ + CY_SYSPM_EXIT_LP_MODE, /**< Exit LPActive mode enum callback type */ +} cy_en_syspm_callback_type_t; + +/** Callback mode enumeration. This enum define the callback mode */ +typedef enum +{ + CY_SYSPM_CHECK_READY, /**< Callbacks with this mode are executed before entering into low-power mode. + It checks if device is ready to enter low-power mode */ + CY_SYSPM_CHECK_FAIL, /**< Callbacks with this mode are executed after the previous callbacks execution + with CY_SYSPM_CHECK_READY returned CY_SYSPM_FAIL. Callback with + CY_SYSPM_CHECK_FAIL mode should rollback the actions which were done in + callbacks executed previously with CY_SYSPM_CHECK_READY */ + CY_SYSPM_BEFORE_ENTER, /**< Actions that should be done before enter low-power mode */ + CY_SYSPM_AFTER_EXIT, /**< Actions that should be done after exit low-power mode */ +} cy_en_syspm_callback_mode_t; + +/** \} group_syspm_data_enumerates */ + +/** +* \addtogroup group_syspm_data_structures +* \{ +*/ + +/** Type for syspm callbacks */ +typedef cy_en_syspm_status_t (*Cy_SysPmCallback) (void *base, void *content, cy_en_syspm_callback_mode_t mode); + +/** The structure which contain the syspm callback configuration elements */ +typedef struct cy_stc_syspm_callback +{ + Cy_SysPmCallback Callback; /**< Callback handler function */ + cy_en_syspm_callback_type_t type; /**< Callback type, see \ref cy_en_syspm_callback_type_t */ + void *base; /**< Base address of HW instance, matches with driver name in + the API for base address */ + void *content; /**< Content for handler function */ + struct cy_stc_syspm_callback *nextItm; /**< Next list item */ +} cy_stc_syspm_callback_t; +/** \} group_syspm_data_structures */ + +/** +* \addtogroup group_syspm_functions +* \{ +*/ +__STATIC_INLINE bool Cy_SysPm_Cm4IsActive(void); +__STATIC_INLINE bool Cy_SysPm_Cm4IsSleep(void); +__STATIC_INLINE bool Cy_SysPm_Cm4IsDeepSleep(void); +__STATIC_INLINE bool Cy_SysPm_Cm4IsLowPower(void); +__STATIC_INLINE bool Cy_SysPm_Cm0IsActive(void); +__STATIC_INLINE bool Cy_SysPm_Cm0IsSleep(void); +__STATIC_INLINE bool Cy_SysPm_Cm0IsDeepSleep(void); +__STATIC_INLINE bool Cy_SysPm_Cm0IsLowPower(void); +__STATIC_INLINE bool Cy_SysPm_IsLowPower(void); + +uint32_t Cy_SysPm_ReadStatus(void); +cy_en_syspm_status_t Cy_SysPm_Sleep(cy_en_syspm_waitfor_t enWaitFor); +cy_en_syspm_status_t Cy_SysPm_DeepSleep(cy_en_syspm_waitfor_t enWaitFor); +cy_en_syspm_status_t Cy_SysPm_Hibernate(void); +cy_en_syspm_status_t Cy_SysPm_EnterLpMode(void); +cy_en_syspm_status_t Cy_SysPm_ExitLpMode(void); +void Cy_SysPm_SleepOnExit(bool enable); + +void Cy_SysPm_WakeupPinLevel(uint32_t pinNum, cy_en_syspm_pinstate_t enPinLevel); +void Cy_SysPm_WakeupLpCompLevel(uint32_t lpCompNum, cy_en_syspm_lpcomp_state_t enLpCompLevel); +void Cy_SysPm_WakeupWdt(bool configureWdt); +void Cy_SysPm_WakeupRtc(bool configureRtc); + +bool Cy_SysPm_RegisterCallback(cy_stc_syspm_callback_t* handler); +bool Cy_SysPm_UnregisterCallback(cy_stc_syspm_callback_t* handler); +uint32_t Cy_SysPm_ExecuteCallback(cy_en_syspm_callback_type_t type, + cy_en_syspm_callback_mode_t mode, + uint32_t lastCallback); + +bool Cy_SysPm_GetIoFreezeStatus(void); +void Cy_SysPm_IoFreeze(void); +void Cy_SysPm_IoUnfreeze(void); + +void Cy_SysPm_LdoSetVoltage(cy_en_syspm_ldo_voltage_t voltage); +cy_en_syspm_ldo_voltage_t Cy_SysPm_LdoGetVoltage(void); +bool Cy_SysPm_LdoIsEnabled(void); + +#if(0u != SRSS_SIMOBUCK_PRESENT) + + void Cy_SysPm_SwitchToSimoBuck(void); + void Cy_SysPm_SimoBuckSetVoltage1(cy_en_syspm_simo_buck_voltage1_t voltage); + cy_en_syspm_simo_buck_voltage1_t Cy_SysPm_SimoBuckGetVoltage1(void); + + void Cy_SysPm_EnableVoltage2(void); + void Cy_SysPm_DisableVoltage2(void); + void Cy_SysPm_SimoBuckSetVoltage2(cy_en_syspm_simo_buck_voltage2_t voltage); + cy_en_syspm_simo_buck_voltage2_t Cy_SysPm_SimoBuckGetVoltage2(void); + + bool Cy_SysPm_SimoBuckOutputIsEnabled(cy_en_syspm_buck_out_t output); + bool Cy_SysPm_SimoBuckIsEnabled(void); + + void Cy_SysPm_SimoBuckSetHwControl(bool hwControl); + bool Cy_SysPm_SimoBuckGetHwControl(void); + +#endif /* (0u != SRSS_SIMOBUCK_PRESENT) */ + + +/******************************************************************************* +* Function Name: Cy_SysPm_Cm4IsActive +****************************************************************************//** +* +* Check if CM4 is in Active mode. +* +* \return +* true - if CM4 is in Active mode, false - if CM4 is not in Active mode. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysPm_Cm4IsActive(void) +{ + return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_ACTIVE) != 0u); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_Cm4IsSleep +****************************************************************************//** +* +* Check if CM4 is in Sleep mode. +* +* \return +* true - if CM4 is in Sleep mode, false - if CM4 is not in Sleep mode. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysPm_Cm4IsSleep(void) +{ + return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_SLEEP) != 0u); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_Cm4IsDeepSleep +****************************************************************************//** +* +* Check if CM4 is in DeepSleep mode. +* +* \return +* true - if CM4 is in DeepSleep mode, false - if CM4 is not in DeepSleep mode. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysPm_Cm4IsDeepSleep(void) +{ + return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_DEEPSLEEP) != 0u); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_Cm4IsLowPower +****************************************************************************//** +* +* Check if CM4 is in LowPower mode. +* +* \return +* true - if CM4 is in LowPower mode, false - if CM4 is not in LowPower mode. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysPm_Cm4IsLowPower(void) +{ + return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM4_LOWPOWER) != 0u); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_Cm0IsActive +****************************************************************************//** +* +* Check if CM0+ is in Active mode. +* +* \return +* true - if CM0+ is in Active mode, false - if CM0+ is not in Active mode. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysPm_Cm0IsActive(void) +{ + return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_ACTIVE) != 0u); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_Cm0IsSleep +****************************************************************************//** +* +* Check if CM0+ is in Sleep mode. +* +* \return +* true - if CM0+ is in Sleep mode, false - if CM0+ is not in Sleep mode. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysPm_Cm0IsSleep(void) +{ + return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_SLEEP) != 0u); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_Cm0IsDeepSleep +****************************************************************************//** +* +* Check if CM0+ is in DeepSleep mode. +* +* \return +* true - if CM0+ is in DeepSleep mode, false - if CM0+ is not in DeepSleep mode. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysPm_Cm0IsDeepSleep(void) +{ + return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_DEEPSLEEP) != 0u); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_Cm0IsLowPower +****************************************************************************//** +* +* Check if CM0+ is in LowPower mode. +* +* \return +* true - if CM0+ is in LowPower mode, false - if CM0+ is not in LowPower mode. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysPm_Cm0IsLowPower(void) +{ + return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_CM0_LOWPOWER) != 0u); +} + + +/******************************************************************************* +* Function Name: Cy_SysPm_IsLowPower +****************************************************************************//** +* +* Check if device is in Low Power mode. +* +* \return +* true - system is in Low Power mode, +* false - if system is is not in Low Power mode. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysPm_IsLowPower(void) +{ + return((Cy_SysPm_ReadStatus() & CY_SYSPM_STATUS_SYSTEM_LOWPOWER) != 0u); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _CY_SYSPM_H_ */ + +/** \} group_syspm_functions*/ +/** \} group_syspm */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/systick/cy_systick.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/systick/cy_systick.c new file mode 100644 index 0000000000..c9e3ece8cc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/systick/cy_systick.c @@ -0,0 +1,335 @@ +/***************************************************************************//** +* \file cy_systick.c +* \version 1.0 +* +* Provides the API definitions of the SisTick driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include +#include "cy_systick.h" +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" + + +static Cy_SysTick_Callback Cy_SysTick_Callbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; +static void Cy_SysTick_ServiceCallbacks(void); + + +/******************************************************************************* +* Function Name: Cy_SysTick_Init +****************************************************************************//** +* +* Initializes the callback addresses with pointers to NULL, associates the +* SysTick system vector with the function responsible for calling +* registered callback functions, configures the SysTick timer to generate an +* interrupt periodically. +* +* \param clockSource The SysTick clock source \ref cy_en_systick_clock_source_t +* \param interval The SysTick reload value. +* +* \sideeffect Clears the SysTick count flag if it was set. +* +*******************************************************************************/ +void Cy_SysTick_Init(cy_en_systick_clock_source_t clockSource, uint32_t interval) +{ + uint32_t i; + + for (i = 0u; iCTRL |= SysTick_CTRL_ENABLE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_Disable +****************************************************************************//** +* +* Disables the SysTick timer and its interrupt. +* +* \sideeffect Clears the SysTick count flag if it was set +* +*******************************************************************************/ +void Cy_SysTick_Disable(void) +{ + Cy_SysTick_DisableInterrupt(); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_EnableInterrupt +****************************************************************************//** +* +* Enables the SysTick interrupt. +* +* \sideeffect Clears the SysTick count flag if it was set +* +*******************************************************************************/ +void Cy_SysTick_EnableInterrupt(void) +{ + SysTick->CTRL = SysTick->CTRL | SysTick_CTRL_TICKINT_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_DisableInterrupt +****************************************************************************//** +* +* Disables the SysTick interrupt. +* +* \sideeffect Clears the SysTick count flag if it was set +* +*******************************************************************************/ +void Cy_SysTick_DisableInterrupt(void) +{ + SysTick->CTRL = SysTick->CTRL & ~SysTick_CTRL_TICKINT_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_SetReload +****************************************************************************//** +* +* Sets the value the counter is set to on a startup and after it reaches zero. +* This function does not change or reset the current sysTick counter value, so +* it should be cleared using the Cy_SysTick_Clear() API. +* +* \param value: The valid range is [0x0-0x00FFFFFF]. The counter reset value. +* +*******************************************************************************/ +void Cy_SysTick_SetReload(uint32_t value) +{ + SysTick->LOAD = (value & SysTick_LOAD_RELOAD_Msk); +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_GetReload +****************************************************************************//** +* +* Gets the value the counter is set to on a startup and after it reaches zero. +* +* \return The counter reset value. +* +*******************************************************************************/ +uint32_t Cy_SysTick_GetReload(void) +{ + return (SysTick->LOAD); +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_GetValue +****************************************************************************//** +* +* Gets the current SysTick counter value. +* +* \return The current SysTick counter value. +* +*******************************************************************************/ +uint32_t Cy_SysTick_GetValue(void) +{ + return (SysTick->VAL); +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_SetClockSource +****************************************************************************//** +* +* Sets the clock source for the SysTick counter. +* +* Clears the SysTick count flag if it was set. If the clock source is not ready +* this function call will have no effect. After changing the clock source to the +* low frequency clock, the counter and reload register values will remain +* unchanged so the time to the interrupt will be significantly longer and vice +* versa. +* +* Changing the SysTick clock source and/or its frequency will change +* the interrupt interval and that Cy_SysTick_SetReload() should be +* called to compensate this change. +* +* \param clockSource \ref cy_en_systick_clock_source_t Clock source. +* +*******************************************************************************/ +void Cy_SysTick_SetClockSource(cy_en_systick_clock_source_t clockSource) +{ + if (clockSource == CY_SYSTICK_CLOCK_SOURCE_CLK_CPU) + { + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + } + else + { + CPUSS->SYSTICK_CTL = _VAL2FLD(CPUSS_SYSTICK_CTL_CLOCK_SOURCE, (uint32_t) clockSource); + SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk; + } +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_GetClockSource +****************************************************************************//** +* +* Gets the clock source for the SysTick counter. +* +* \returns \ref cy_en_systick_clock_source_t Clock source +* +*******************************************************************************/ +cy_en_systick_clock_source_t Cy_SysTick_GetClockSource(void) +{ + cy_en_systick_clock_source_t returnValue; + + if ((SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) != 0u) + { + returnValue = CY_SYSTICK_CLOCK_SOURCE_CLK_CPU; + } + else + { + returnValue = (cy_en_systick_clock_source_t)_FLD2VAL(CPUSS_SYSTICK_CTL_CLOCK_SOURCE, CPUSS->SYSTICK_CTL); + } + + return(returnValue); +} + +/******************************************************************************* +* Function Name: Cy_SysTick_GetCountFlag +****************************************************************************//** +* +* The count flag is set, once the SysTick counter reaches zero. +* The flag is cleared on read. +* +* \return Returns a non-zero value if a flag is set, otherwise a zero is +* returned. +* +* \sideeffect Clears the SysTick count flag if it was set. +* +*******************************************************************************/ +uint32_t Cy_SysTick_GetCountFlag(void) +{ + return (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk); +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_Clear +****************************************************************************//** +* +* Clears the SysTick counter for a well-defined startup. +* +*******************************************************************************/ +void Cy_SysTick_Clear(void) +{ + SysTick->VAL = 0u; +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_SetCallback +****************************************************************************//** +* +* This function allows up to five user-defined interrupt service routine +* functions to be associated with the SysTick interrupt. These are specified +* through the use of pointers to the function. +* +* \param number The number of the callback function addresses to be set. +* The valid range is from 0 to 4. +* +* \param function The pointer to the function that will be associated with the +* SysTick ISR for the specified number. +* +* \return Returns the address of the previous callback function. +* The NULL is returned if the specified address in not set. +* +* \sideeffect +* The registered callback functions will be executed in the interrupt. +* +*******************************************************************************/ +Cy_SysTick_Callback Cy_SysTick_SetCallback(uint32_t number, Cy_SysTick_Callback function) +{ + Cy_SysTick_Callback retVal; + + retVal = Cy_SysTick_Callbacks[number]; + Cy_SysTick_Callbacks[number] = function; + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_GetCallback +****************************************************************************//** +* +* The function gets the specified callback pointer. +* +* \param number The number of the callback function address to get. The valid +* range is from 0 to 4. +* +* \return +* Returns the address of the specified callback function. +* The NULL is returned if the specified address in not initialized. +* +*******************************************************************************/ +Cy_SysTick_Callback Cy_SysTick_GetCallback(uint32_t number) +{ + return ((Cy_SysTick_Callback) Cy_SysTick_Callbacks[number]); +} + + +/******************************************************************************* +* Function Name: Cy_SysTick_ServiceCallbacks +****************************************************************************//** +* +* The system Tick timer interrupt routine. +* +*******************************************************************************/ +static void Cy_SysTick_ServiceCallbacks(void) +{ + uint32_t i; + + /* Verify that tick timer flag was set */ + if (0u != Cy_SysTick_GetCountFlag()) + { + for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++) + { + if (Cy_SysTick_Callbacks[i] != (void *) 0) + { + (void)(Cy_SysTick_Callbacks[i])(); + } + } + } +} + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/systick/cy_systick.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/systick/cy_systick.h new file mode 100644 index 0000000000..949984ada5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/systick/cy_systick.h @@ -0,0 +1,170 @@ +/***************************************************************************//** +* \file cy_systick.h +* \version 1.0 +* +* Provides the API declarations of the SysTick driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CY_SYSTICK_H_ +#define _CY_SYSTICK_H_ + +/** +* \defgroup group_arm_system_timer ARM System Timer (SysTick) +* \{ +* Provides a SysTick API. +* +* \section group_systick_configuration Configuration Considerations +* +* The SysTick timer is part of the CPU. The timer is a down counter with a +* 24-bit reload/tick value that is clocked by the FastClk/SlowClk. The timer has +* the capability to generate an interrupt when the set number of ticks expires +* and the counter is reloaded. This interrupt is available as part of the Nested +* Vectored Interrupt Controller (NVIC) for service by the CPU and can be used +* for general purpose timing control in user code. +* +* Changing the SysTick clock source and/or its frequency will change the +* interrupt interval and therefore Cy_SysTick_SetReload() should be called to +* compensate for this change. +* +* Because the timer is independent of the CPU (except for the clock), this can be +* handy in applications requiring precise timing that do not have a dedicated +* timer/counter available for the job. +* +* \section group_systick_more_information More Information +* +* Refer to the SysTick section of the ARM reference guide for complete details +* on the registers and their use. +* +* \section group_systick_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
8.8RequiredAn external object or function shall be declared in one and only one file.The variable is not used within project, so is defined without previous declaration.
+* +* \section group_systick_changelog Changelog +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_systick_macro Macro +* \defgroup group_systick_functions Functions +* \defgroup group_systick_data_structures Data Structures +*/ + +#include +#include +#include "syslib/cy_syslib.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \cond */ +extern cy_israddress __ramVectors[]; +typedef void (*Cy_SysTick_Callback)(void); +/** \endcond */ + +/** +* \addtogroup group_systick_data_structures +* \{ +*/ +typedef enum +{ + /** The low frequency clock clk_lf is selected. The precision of this clock depends on whether the low frequency + clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise) */ + CY_SYSTICK_CLOCK_SOURCE_CLK_LF = 0u, + + /** The internal main oscillator (IMO) clock clk_imo is selected. */ + CY_SYSTICK_CLOCK_SOURCE_CLK_IMO = 1u, + + /** The external crystal oscillator (ECO) clock clk_eco is selected. */ + CY_SYSTICK_CLOCK_SOURCE_CLK_ECO = 2u, + + /** The SRSS clk_timer is selected. The clk_timer is a divided/gated version of clk_hf or clk_imo. */ + CY_SYSTICK_CLOCK_SOURCE_CLK_TIMER = 3u, + + /** The CPU clock is selected. */ + CY_SYSTICK_CLOCK_SOURCE_CLK_CPU = 4u, +} cy_en_systick_clock_source_t; + +/** \} group_systick_data_structures */ + + +/** +* \addtogroup group_systick_functions +* \{ +*/ + +void Cy_SysTick_Init(cy_en_systick_clock_source_t clockSource, uint32_t interval); +void Cy_SysTick_Enable(void); +void Cy_SysTick_Disable(void); +void Cy_SysTick_EnableInterrupt(void); +void Cy_SysTick_DisableInterrupt(void); +void Cy_SysTick_SetReload(uint32_t value); +uint32_t Cy_SysTick_GetReload(void); +uint32_t Cy_SysTick_GetValue(void); +Cy_SysTick_Callback Cy_SysTick_SetCallback(uint32_t number, Cy_SysTick_Callback function); +Cy_SysTick_Callback Cy_SysTick_GetCallback(uint32_t number); +void Cy_SysTick_SetClockSource(cy_en_systick_clock_source_t clockSource); +cy_en_systick_clock_source_t Cy_SysTick_GetClockSource(void); + +uint32_t Cy_SysTick_GetCountFlag(void); +void Cy_SysTick_Clear(void); + +/** \} group_systick_functions */ + + +/** +* \addtogroup group_systick_macro +* \{ +*/ + +/** Driver major version */ +#define SYSTICK_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define SYSTICK_DRV_VERSION_MINOR 0 + +/** Number of the callbacks assigned to the SysTick interrupt */ +#define CY_SYS_SYST_NUM_OF_CALLBACKS (5u) + +/** Interrupt number in the vector table */ +#define CY_SYSTICK_IRQ_NUM (15u) + +/** \} group_systick_macro */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _CY_SYSTICK_H_ */ + +/** \} group_systick */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm.h new file mode 100644 index 0000000000..5288a744be --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm.h @@ -0,0 +1,591 @@ +/***************************************************************************//** +* \file cy_tcpwm.h +* \version 1.0 +* +* The header file of the TCPWM driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_tcpwm Timer Counter PWM (TCPWM) +* \{ +* \defgroup group_tcpwm_common Common +* \defgroup group_tcpwm_counter Timer/Counter (TCPWM) +* \defgroup group_tcpwm_pwm PWM (TCPWM) +* \defgroup group_tcpwm_quaddec Quadrature Decoder (TCPWM) +* \} */ + +/** +* \addtogroup group_tcpwm +* \{ +* +* The TCPWM driver is a multifunction driver that implements core +* microcontroller functionality including Timer Counter, PWM, and +* Quadrature Decoder using the TCPWM block. +* +* The driver is based on a hardware structure designed to share the same +* hardware across the various modes of operation. This structure +* allows a single driver to provide a flexible set of functions. +* +* A TCPWM is a collection of counters that can all be triggered simultaneously. +* For each function call, the base register address of the TCPWM being used must +* be passed first, followed by the index of the counter you want to touch next. +* For some functions, you can manage multiple counters simultaneously. You +* provide a bit field representing each counter, rather than the single counter +* index). +* +* The TCPWM supports three operating modes: +* * Timer/Counter +* * PWM +* * Quadrature Decoder +* +* \n +* \b Timer/Counter +* +* Use this mode whenever a specific timing interval or measurement is +* needed. Examples include: +* * Creating a periodic interrupt for running other system tasks +* * Measuring frequency of an input signal +* * Measuring pulse width of an input signal +* * Measuring time between two external events +* * Counting events +* * Triggering other system resources after x number events +* * Capturing time stamps when events occur +* +* The Timer/Counter has the following features: +* * 16- or 32-bit Timer/Counter +* * Programmable Period Register +* * Programmable Compare Register. Compare value can be swapped with a +* buffered compare value on comparison event +* * Capture with buffer register +* * Count Up, Count Down, or Count Up and Down Counting modes +* * Continuous or One Shot Run modes +* * Interrupt and Output on Overflow, Underflow, Capture, or Compare +* * Start, Reload, Stop, Capture, and Count Inputs +* +* \n +* \b PWM +* +* Use this mode when an output square wave is needed with a specific +* period and duty cycle, such as: +* * Creating arbitrary square wave outputs +* * Driving an LED (changing the brightness) +* * Driving Motors (dead time assertion available) +* +* The PWM has the following features: +* * 16- or 32-bit Counter +* * Two Programmable Period registers that can be swapped on overflow +* * Two Output Compare registers that can be swapped on overflow and/or +* underflow +* * Left Aligned, Right Aligned, Center Aligned, and Asymmetric Aligned modes +* * Continuous or One Shot run modes +* * Pseudo Random mode +* * Two PWM outputs with Dead Time insertion, and programmable polarity +* * Interrupt and Output on Overflow, Underflow, or Compare +* * Start, Reload, Stop, Swap (Capture), and Count Inputs +* +* \n +* \b Quadrature \b Decoder +* +* A quadrature decoder is used to decode the output of a quadrature encoder. +* A quadrature encoder senses the position, velocity, and direction of +* an object (for example a rotating axle, or a spinning mouse ball). +* A quadrature decoder can also be used for precision measurement of speed, +* acceleration, and position of a motor's rotor, or with a rotary switch to +* determine user input. \n +* +* The Quadrature Decoder has the following features: +* * 16- or 32-bit Counter +* * Counter Resolution of x1, x2, and x4 the frequency of the phiA (Count) and +* phiB (Start) inputs +* * Index (Reload) Input to determine absolute position +* * A positive edge on phiA increments the counter when phiB is 0 and decrements +* the counter when phiB is 1 +* +* \section group_tcpwm_configuration Configuration Considerations +* +* For each mode, the TCPWM driver has a configuration structure, an Init +* function, and an Enable function. +* +* Provide the configuration parameters in the appropriate structure (see +* \ref group_tcpwm_data_structures). Then call the appropriate Init function: +* \ref Cy_TCPWM_Counter_Init, \ref Cy_TCPWM_PWM_Init, or +* \ref Cy_TCPWM_QuadDec_Init. Provide the address of the filled structure as a +* parameter. To enable the counter, call the appropriate Enable function: +* \ref Cy_TCPWM_Counter_Enable, \ref Cy_TCPWM_PWM_Enable, or +* \ref Cy_TCPWM_QuadDec_Enable). +* +* Many functions work with an individual counter. You can also manage multiple +* counters simultaneously for certain functions. These are listed in the +* \ref group_tcpwm_functions_common functions +* section of the TCPWM. You can enable, disable, or trigger (in various ways) +* multiple counters simultaneously. For these functions you provide a bit field +* representing each counter in the TCPWM you want to control. You can +* represent the bit field as an ORed mask of each counter, like +* ((1u << cntNumX) | (1u << cntNumX) | (1u << cntNumX)), where X is the counter +* number from 0 to 31. +* +* \note +* * If none of the input terminals (start, reload(index)) are used, the +* software event \ref Cy_TCPWM_TriggerStart or +* \ref Cy_TCPWM_TriggerReloadOrIndex must be called to start the counting. +* * If count input terminal is not used, the \ref CY_TCPWM_INPUT_LEVEL macro +* should be set for the countInputMode parameter and the \ref CY_TCPWM_INPUT_1 +* macro should be set for the countInputMode parameter in the configuration +* structure (\ref group_tcpwm_data_structures) of the appropriate mode. +* +* \section group_tcpwm_more_information More Information +* +* For more information on the TCPWM peripheral, refer to the technical +* reference manual (TRM). +* +* \section group_tcpwm_MISRA MISRA-C Compliance +* The tcpwm driver does not have any specific deviations +* +* \section group_tcpwm_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+*/ + +/** \} group_tcpwm */ + +/** +* \addtogroup group_tcpwm_common +* Common API for the Timer Counter PWM Block. +* \{ +* \defgroup group_tcpwm_macro_common Macro +* \defgroup group_tcpwm_functions_common Functions +* \defgroup group_tcpwm_data_structures_common Data Structures +* \defgroup group_tcpwm_enums Enumerated Types +*/ + + +#if !defined(CY_TCPWM_H) +#define CY_TCPWM_H + +#include +#include +#include +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_tcpwm_macro_common +* \{ +*/ + +/** Driver major version */ +#define CY_TCPWM_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_TCPWM_DRV_VERSION_MINOR 0 + + +/****************************************************************************** +* API Constants +******************************************************************************/ + +/** TCPWM driver identifier */ +#define CY_TCPWM_ID (CY_PDL_DRV_ID(0x2Du)) + +/** \defgroup group_tcpwm_input_selection TCPWM Input Selection +* \{ +* Selects which input to use +*/ +#define CY_TCPWM_INPUT_0 (0u) /**< Input is tied to logic 0 */ +#define CY_TCPWM_INPUT_1 (1u) /**< Input is tied to logic 1 */ +#define CY_TCPWM_INPUT_TRIG_0 (2u) /**< Input is connected to the trigger input 0 */ +#define CY_TCPWM_INPUT_TRIG_1 (3u) /**< Input is connected to the trigger input 1 */ +#define CY_TCPWM_INPUT_TRIG_2 (4u) /**< Input is connected to the trigger input 2 */ +#define CY_TCPWM_INPUT_TRIG_3 (5u) /**< Input is connected to the trigger input 3 */ +#define CY_TCPWM_INPUT_TRIG_4 (6u) /**< Input is connected to the trigger input 4 */ +#define CY_TCPWM_INPUT_TRIG_5 (7u) /**< Input is connected to the trigger input 5 */ +#define CY_TCPWM_INPUT_TRIG_6 (8u) /**< Input is connected to the trigger input 6 */ +#define CY_TCPWM_INPUT_TRIG_7 (9u) /**< Input is connected to the trigger input 7 */ +#define CY_TCPWM_INPUT_TRIG_8 (10u) /**< Input is connected to the trigger input 8 */ +#define CY_TCPWM_INPUT_TRIG_9 (11u) /**< Input is connected to the trigger input 9 */ +#define CY_TCPWM_INPUT_TRIG_10 (12u) /**< Input is connected to the trigger input 10 */ +#define CY_TCPWM_INPUT_TRIG_11 (13u) /**< Input is connected to the trigger input 11 */ +#define CY_TCPWM_INPUT_TRIG_12 (14u) /**< Input is connected to the trigger input 12 */ +#define CY_TCPWM_INPUT_TRIG_13 (15u) /**< Input is connected to the trigger input 13 */ + +/** Input is defined by Creator, and Init() function does not need to configure input */ +#define CY_TCPWM_INPUT_CREATOR (65535u) +/** \} group_tcpwm_input_selection */ + +/** +* \defgroup group_tcpwm_input_modes Input Modes +* \{ +* Configures how TCPWM inputs behave +*/ +/** A rising edge triggers the event (Capture, Start, Reload, etc..) */ +#define CY_TCPWM_INPUT_RISINGEDGE (0u) +/** A falling edge triggers the event (Capture, Start, Reload, etc..) */ +#define CY_TCPWM_INPUT_FALLINGEDGE (1u) +/** A rising edge or falling edge triggers the event (Capture, Start, Reload, etc..) */ +#define CY_TCPWM_INPUT_EITHEREDGE (2u) +/** The event is triggered on each edge of the TCPWM clock if the input is high */ +#define CY_TCPWM_INPUT_LEVEL (3u) +/** \} group_tcpwm_input_modes */ + +/** +* \defgroup group_tcpwm_interrupt_sources Interrupt Sources +* \{ +* Interrupt Sources +*/ +#define CY_TCPWM_INT_ON_TC (1u) /**< Interrupt on Terminal count(TC) */ +#define CY_TCPWM_INT_ON_CC (2u) /**< Interrupt on Compare/Capture(CC) */ +#define CY_TCPWM_INT_NONE (0u) /**< No Interrupt */ +#define CY_TCPWM_INT_ON_CC_OR_TC (3u) /**< Interrupt on TC or CC */ +/** \} group_tcpwm_interrupt_sources */ + + +/*************************************** +* Registers Constants +***************************************/ + +/** +* \defgroup group_tcpwm_reg_const Default registers constants +* \{ +* Default constants for CNT Registers +*/ +#define CY_TCPWM_CNT_CTRL_DEFAULT (0x0u) /**< Default value for CTRL register */ +#define CY_TCPWM_CNT_COUNTER_DEFAULT (0x0u) /**< Default value for COUNTER register */ +#define CY_TCPWM_CNT_CC_DEFAULT (0xFFFFFFFFu) /**< Default value for CC register */ +#define CY_TCPWM_CNT_CC_BUFF_DEFAULT (0xFFFFFFFFu) /**< Default value for CC_BUFF register */ +#define CY_TCPWM_CNT_PERIOD_DEFAULT (0xFFFFFFFFu) /**< Default value for PERIOD register */ +#define CY_TCPWM_CNT_PERIOD_BUFF_DEFAULT (0xFFFFFFFFu) /**< Default value for PERIOD_BUFF register */ +#define CY_TCPWM_CNT_TR_CTRL0_DEFAULT (0x10u) /**< Default value for TR_CTRL0 register */ +#define CY_TCPWM_CNT_TR_CTRL1_DEFAULT (0x3FFu) /**< Default value for TR_CTRL1 register */ +#define CY_TCPWM_CNT_TR_CTRL2_DEFAULT (0x3Fu) /**< Default value for TR_CTRL2 register */ +#define CY_TCPWM_CNT_INTR_DEFAULT (0x3u) /**< Default value for INTR register */ +#define CY_TCPWM_CNT_INTR_SET_DEFAULT (0x0u) /**< Default value for INTR_SET register */ +#define CY_TCPWM_CNT_INTR_MASK_DEFAULT (0x0u) /**< Default value for INTR_MASK register */ +/** \} group_tcpwm_reg_const */ + +/** Position of Up counting counter status */ +#define CY_TCPWM_CNT_STATUS_UP_POS (0x1u) +/** Initial value for the counter in the Up counting mode */ +#define CY_TCPWM_CNT_UP_INIT_VAL (0x0u) +/** Initial value for the counter in the Up/Down counting modes */ +#define CY_TCPWM_CNT_UP_DOWN_INIT_VAL (0x1u) +/** \} group_tcpwm_macro_common */ + + +/******************************************************************************* + * Enumerations + ******************************************************************************/ + + /** +* \addtogroup group_tcpwm_enums +* \{ +*/ + +/** TCPWM status definitions */ +typedef enum +{ + CY_TCPWM_SUCCESS = 0x00u, /**< Successful */ + CY_TCPWM_BAD_PARAM = CY_TCPWM_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */ +} cy_en_tcpwm_status_t; +/** \} group_tcpwm_enums */ + +/******************************************************************************* +* Function Prototypes +*******************************************************************************/ + +/** +* \addtogroup group_tcpwm_functions_common +* \{ +*/ + +__STATIC_INLINE void Cy_TCPWM_Enable_Multiple(TCPWM_Type *base, uint32_t counters); +__STATIC_INLINE void Cy_TCPWM_Disable_Multiple(TCPWM_Type *base, uint32_t counters); +__STATIC_INLINE void Cy_TCPWM_TriggerStart(TCPWM_Type *base, uint32_t counters); +__STATIC_INLINE void Cy_TCPWM_TriggerReloadOrIndex(TCPWM_Type *base, uint32_t counters); +__STATIC_INLINE void Cy_TCPWM_TriggerStopOrKill(TCPWM_Type *base, uint32_t counters); +__STATIC_INLINE void Cy_TCPWM_TriggerCaptureOrSwap(TCPWM_Type *base, uint32_t counters); +__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatus(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_ClearInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source); +__STATIC_INLINE void Cy_TCPWM_SetInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source); +__STATIC_INLINE void Cy_TCPWM_SetInterruptMask(TCPWM_Type *base, uint32_t cntNum, uint32_t mask); +__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptMask(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatusMasked(TCPWM_Type const *base, uint32_t cntNum); + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Enable_Multiple +****************************************************************************//** +* +* Enables the counter(s) in the TCPWM block. Multiple blocks can be started +* simultaneously. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param counters +* A bit field representing each counter in the TCPWM block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_Enable_Multiple(TCPWM_Type *base, uint32_t counters) +{ + base->CTRL_SET = counters; +} + +/******************************************************************************* +* Function Name: Cy_TCPWM_Disable_Multiple +****************************************************************************//** +* +* Disables the counter(s) in the TCPWM block. Multiple TCPWM can be disabled +* simultaneously. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param counters +* A bit field representing each counter in the TCPWM block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_Disable_Multiple(TCPWM_Type *base, uint32_t counters) +{ + base->CTRL_CLR = counters; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_TriggerStart +****************************************************************************//** +* +* Triggers a software start on the selected TCPWMs. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param counters +* A bit field representing each counter in the TCPWM block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_TriggerStart(TCPWM_Type *base, uint32_t counters) +{ + base->CMD_START = counters; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_TriggerReloadOrIndex +****************************************************************************//** +* +* Triggers a software reload event (or index in QuadDec mode). +* +* \param base +* The pointer to a TCPWM instance +* +* \param counters +* A bit field representing each counter in the TCPWM block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_TriggerReloadOrIndex(TCPWM_Type *base, uint32_t counters) +{ + base->CMD_RELOAD = counters; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_TriggerStopOrKill +****************************************************************************//** +* +* Triggers a stop in the Timer Counter mode, or a kill in the PWM mode. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param counters +* A bit field representing each counter in the TCPWM block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_TriggerStopOrKill(TCPWM_Type *base, uint32_t counters) +{ + + base->CMD_STOP = counters; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_TriggerCaptureOrSwap +****************************************************************************//** +* +* Triggers a Capture in the Timer Counter mode, and a Swap in the PWM mode. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param counters +* A bit field representing each counter in the TCPWM block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_TriggerCaptureOrSwap(TCPWM_Type *base, uint32_t counters) +{ + base->CMD_CAPTURE = counters; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_GetInterruptStatus +****************************************************************************//** +* +* Returns which event triggered the interrupt. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +*. See \ref group_tcpwm_interrupt_sources +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatus(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].INTR); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_ClearInterrupt +****************************************************************************//** +* +* Clears Active Interrupt Source +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param source +* source to clear. See \ref group_tcpwm_interrupt_sources +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_ClearInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source) +{ + base->CNT[cntNum].INTR = source; + (void)base->CNT[cntNum].INTR; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_SetInterrupt +****************************************************************************//** +* +* Triggers an interrupt via a software write. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param source +* The source to set an interrupt. See \ref group_tcpwm_interrupt_sources. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_SetInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source) +{ + base->CNT[cntNum].INTR_SET = source; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_SetInterruptMask +****************************************************************************//** +* +* Sets an interrupt mask. A 1 means that when the event occurs, it will cause an +* interrupt; a 0 means no interrupt will be triggered. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param mask +*. See \ref group_tcpwm_interrupt_sources +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_SetInterruptMask(TCPWM_Type *base, uint32_t cntNum, uint32_t mask) +{ + base->CNT[cntNum].INTR_MASK = mask; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_GetInterruptMask +****************************************************************************//** +* +* Returns the interrupt mask. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* Interrupt Mask. See \ref group_tcpwm_interrupt_sources +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptMask(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].INTR_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_GetInterruptStatusMasked +****************************************************************************//** +* +* Returns which masked interrupt triggered the interrupt. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* Interrupt Mask. See \ref group_tcpwm_interrupt_sources +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatusMasked(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].INTR_MASKED); +} + +/** \} group_tcpwm_functions_common */ + +/** \} group_tcpwm_common */ + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_TCPWM_H */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_counter.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_counter.c new file mode 100644 index 0000000000..f60b0b50c4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_counter.c @@ -0,0 +1,137 @@ +/***************************************************************************//** +* \file cy_tcpwm_counter.c +* \version 1.0 +* +* \brief +* The source file of the tcpwm driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_tcpwm_counter.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_Init +****************************************************************************//** +* +* Initializes the counter in the TCPWM block for the Counter operation. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param config +* The pointer to configuration structure. See \ref cy_stc_tcpwm_counter_config_t. +* +* \return error / status code. See \ref cy_en_tcpwm_status_t. +* +*******************************************************************************/ +cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_counter_config_t const *config) +{ + cy_en_tcpwm_status_t status = CY_TCPWM_BAD_PARAM; + + if ((NULL != base) && (NULL != config)) + { + base->CNT[cntNum].CTRL = ( _VAL2FLD(TCPWM_CNT_CTRL_GENERIC, config->clockPrescaler) | + _VAL2FLD(TCPWM_CNT_CTRL_ONE_SHOT, config->runMode) | + _VAL2FLD(TCPWM_CNT_CTRL_UP_DOWN_MODE, config->countDirection) | + _VAL2FLD(TCPWM_CNT_CTRL_MODE, config->compareOrCapture) | + (config->enableCompareSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk : 0uL)); + + if (CY_TCPWM_COUNTER_COUNT_UP == config->runMode) + { + base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_UP_INIT_VAL; + } + else if (CY_TCPWM_COUNTER_COUNT_DOWN == config->runMode) + { + base->CNT[cntNum].COUNTER = config->period; + } + else + { + base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_UP_DOWN_INIT_VAL; + } + + base->CNT[cntNum].CC = config->compare0; + base->CNT[cntNum].CC_BUFF = config->compare1; + base->CNT[cntNum].PERIOD = config->period; + + if (CY_TCPWM_INPUT_CREATOR != config->countInput) + { + base->CNT[cntNum].TR_CTRL0 = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_CAPTURE_SEL, config->captureInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, config->reloadInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, config->startInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->stopInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->countInput)); + } + + base->CNT[cntNum].TR_CTRL1 = (_VAL2FLD(TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE, config->captureInputMode) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_RELOAD_EDGE, config->reloadInputMode) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_START_EDGE, config->startInputMode) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_STOP_EDGE, config->stopInputMode) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_COUNT_EDGE, config->countInputMode)); + + base->CNT[cntNum].INTR_MASK = config->interruptSources; + + status = CY_TCPWM_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_DeInit +****************************************************************************//** +* +* De-initializes the counter in the TCPWM block, returns register values to +* default. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param config +* The pointer to configuration structure. See \ref cy_stc_tcpwm_counter_config_t. +* +*******************************************************************************/ +void Cy_TCPWM_Counter_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_counter_config_t const *config) +{ + base->CNT[cntNum].CTRL = CY_TCPWM_CNT_CTRL_DEFAULT; + base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_COUNTER_DEFAULT; + base->CNT[cntNum].CC = CY_TCPWM_CNT_CC_DEFAULT; + base->CNT[cntNum].CC_BUFF = CY_TCPWM_CNT_CC_BUFF_DEFAULT; + base->CNT[cntNum].PERIOD = CY_TCPWM_CNT_PERIOD_DEFAULT; + base->CNT[cntNum].PERIOD_BUFF = CY_TCPWM_CNT_PERIOD_BUFF_DEFAULT; + base->CNT[cntNum].TR_CTRL1 = CY_TCPWM_CNT_TR_CTRL1_DEFAULT; + base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_CNT_TR_CTRL2_DEFAULT; + base->CNT[cntNum].INTR = CY_TCPWM_CNT_INTR_DEFAULT; + base->CNT[cntNum].INTR_SET = CY_TCPWM_CNT_INTR_SET_DEFAULT; + base->CNT[cntNum].INTR_MASK = CY_TCPWM_CNT_INTR_MASK_DEFAULT; + + if (CY_TCPWM_INPUT_CREATOR != config->countInput) + { + base->CNT[cntNum].TR_CTRL0 = CY_TCPWM_CNT_TR_CTRL0_DEFAULT; + } +} + + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_counter.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_counter.h new file mode 100644 index 0000000000..c390fd470d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_counter.h @@ -0,0 +1,484 @@ +/***************************************************************************//** +* \file cy_tcpwm_counter.h +* \version 1.0 +* +* \brief +* The header file of the TCPWM Timer Counter driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_tcpwm_macro_counter Macro +* \defgroup group_tcpwm_functions_counter Functions +* \defgroup group_tcpwm_data_structures_counter Data Structures +* \} */ + +#if !defined(CY_TCPWM_COUNTER_H) +#define CY_TCPWM_COUNTER_H + +#include "cy_tcpwm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_tcpwm_counter +* \{ +* Driver API for Timer/Counter. +*/ + +/** +* \addtogroup group_tcpwm_data_structures_counter +* \{ +*/ + +/** Counter Timer configuration structure */ +typedef struct cy_stc_tcpwm_counter_config +{ + uint32_t period; /**< Sets the period of the counter */ + /** Sets the clock prescaler inside the TCWPM block. See \ref group_tcpwm_counter_clk_prescalers */ + uint32_t clockPrescaler; + uint32_t runMode; /**< Sets the Counter Timer Run mode. See \ref group_tcpwm_counter_run_modes */ + uint32_t countDirection; /**< Sets the counter direction. See \ref group_tcpwm_counter_direction */ + /** The counter can either compare or capture a value. See \ref group_tcpwm_counter_compare_capture */ + uint32_t compareOrCapture; + uint32_t compare0; /**< Sets the value for Compare0*/ + uint32_t compare1; /**< Sets the value for Compare1*/ + bool enableCompareSwap; /**< If enabled, the compare values are swapped each time the comparison is true */ + /** Enabled an interrupt on the terminal count, capture or compare. See \ref group_tcpwm_interrupt_sources */ + uint32_t interruptSources; + uint32_t captureInputMode; /**< Configures how the capture input behaves. See \ref group_tcpwm_input_modes */ + /** Selects which input the capture uses, the inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t captureInput; + uint32_t reloadInputMode; /**< Configures how the reload input behaves. See \ref group_tcpwm_input_modes */ + /** Selects which input the reload uses, the inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t reloadInput; + uint32_t startInputMode; /**< Configures how the start input behaves. See \ref group_tcpwm_input_modes */ + /** Selects which input the start uses, the inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t startInput; + uint32_t stopInputMode; /**< Configures how the stop input behaves. See \ref group_tcpwm_input_modes */ + /** Selects which input the stop uses, the inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t stopInput; + uint32_t countInputMode; /**< Configures how the count input behaves. See \ref group_tcpwm_input_modes */ + /** Selects which input the count uses, the inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t countInput; +}cy_stc_tcpwm_counter_config_t; +/** \} group_tcpwm_data_structures_counter */ + +/** +* \addtogroup group_tcpwm_macro_counter +* \{ +* \defgroup group_tcpwm_counter_run_modes Counter Run Modes +* \{ +* Run modes for the counter timer. +*/ +#define CY_TCPWM_COUNTER_ONESHOT (1u) /**< Counter runs once and then stops */ +#define CY_TCPWM_COUNTER_CONTINUOUS (0u) /**< Counter runs forever */ +/** \} group_tcpwm_counter_run_modes */ + +/** \defgroup group_tcpwm_counter_direction Counter Direction +* The counter directions. +* \{ +*/ +#define CY_TCPWM_COUNTER_COUNT_UP (0u) /**< Counter counts up */ +#define CY_TCPWM_COUNTER_COUNT_DOWN (1u) /**< Counter counts down */ +/** Counter counts up and down terminal count only occurs on underflow. */ +#define CY_TCPWM_COUNTER_COUNT_UP_DOWN0 (2u) +/** Counter counts up and down terminal count occurs on both overflow and underflow. */ +#define CY_TCPWM_COUNTER_COUNT_UP_DOWN1 (3u) +/** \} group_tcpwm_counter_direction */ + +/** \defgroup group_tcpwm_counter_clk_prescalers Counter CLK Prescalers +* \{ +* The clock prescaler values. +*/ +#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_1 (0u) /**< Divide by 1 */ +#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_2 (1u) /**< Divide by 2 */ +#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_4 (2u) /**< Divide by 4 */ +#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_8 (3u) /**< Divide by 8 */ +#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_16 (4u) /**< Divide by 16 */ +#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_32 (5u) /**< Divide by 32 */ +#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_64 (6u) /**< Divide by 64 */ +#define CY_TCPWM_COUNTER_PRESCALER_DIVBY_128 (7u) /**< Divide by 128 */ +/** \} group_tcpwm_counter_clk_prescalers */ + +/** \defgroup group_tcpwm_counter_compare_capture Counter Compare Capture +* \{ +* A compare or capture mode. +*/ +#define CY_TCPWM_COUNTER_MODE_CAPTURE (2u) /**< Timer/Counter is in Capture Mode */ +#define CY_TCPWM_COUNTER_MODE_COMPARE (0u) /**< Timer/Counter is in Compare Mode */ +/** \} group_tcpwm_counter_compare_capture */ + +/** \defgroup group_tcpwm_counter_status Counter Status +* \{ +* The counter status. +*/ +#define CY_TCPWM_COUNTER_STATUS_DOWN_COUNTING (0x1uL) /**< Timer/Counter is down counting */ +#define CY_TCPWM_COUNTER_STATUS_UP_COUNTING (0x2uL) /**< Timer/Counter is up counting */ + +/** Timer/Counter is running */ +#define CY_TCPWM_COUNTER_STATUS_COUNTER_RUNNING (TCPWM_CNT_STATUS_RUNNING_Msk) +/** \} group_tcpwm_counter_status */ +/** \} group_tcpwm_macro_counter */ + + +/******************************************************************************* +* Function Prototypes +*******************************************************************************/ + +/** +* \addtogroup group_tcpwm_functions_counter +* \{ +*/ +cy_en_tcpwm_status_t Cy_TCPWM_Counter_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_counter_config_t const *config); +void Cy_TCPWM_Counter_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_counter_config_t const *config); +__STATIC_INLINE void Cy_TCPWM_Counter_Enable(TCPWM_Type *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_Counter_Disable(TCPWM_Type *base, uint32_t cntNum); +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetStatus(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCapture(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCaptureBuf(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_Counter_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0); +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare0(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_Counter_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1); +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare1(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_Counter_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable); +__STATIC_INLINE void Cy_TCPWM_Counter_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count); +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCounter(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_Counter_SetPeriod(TCPWM_Type *base, uint32_t cntNum, uint32_t period); +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetPeriod(TCPWM_Type const *base, uint32_t cntNum); + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_Enable +****************************************************************************//** +* +* Enables the counter in the TCPWM block for the Counter operation. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_Counter_Enable(TCPWM_Type *base, uint32_t cntNum) +{ + base->CTRL_SET = (1uL << cntNum); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_Disable +****************************************************************************//** +* +* Disables the counter in the TCPWM block. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_Counter_Disable(TCPWM_Type *base, uint32_t cntNum) +{ + base->CTRL_CLR = (1uL << cntNum); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_GetStatus +****************************************************************************//** +* +* Returns the status of the Counter Timer. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The status. See \ref group_tcpwm_counter_status +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetStatus(TCPWM_Type const *base, uint32_t cntNum) +{ + uint32_t status = base->CNT[cntNum].STATUS; + + /* Generates proper up counting status. Is not generated by HW */ + status &= ~CY_TCPWM_COUNTER_STATUS_UP_COUNTING; + status |= ((~status & CY_TCPWM_COUNTER_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) << + CY_TCPWM_CNT_STATUS_UP_POS); + + return(status); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_GetCapture +****************************************************************************//** +* +* Returns the capture value when the capture mode is enabled. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The capture value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCapture(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].CC); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_GetCaptureBuf +****************************************************************************//** +* +* Returns the buffered capture value when the capture mode is enabled. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The buffered capture value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCaptureBuf(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].CC_BUFF); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_SetCompare0 +****************************************************************************//** +* +* Sets the compare value for Compare0 when the compare mode is enabled. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param compare0 +* The Compare0 value. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_Counter_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0) +{ + base->CNT[cntNum].CC = compare0; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_GetCompare0 +****************************************************************************//** +* +* Returns compare value 0. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* Compare value 0. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare0(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].CC); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_SetCompare1 +****************************************************************************//** +* +* Sets the compare value for Compare1 when the compare mode is enabled. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param compare1 +* The Compare1 value. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_Counter_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1) +{ + base->CNT[cntNum].CC_BUFF = compare1; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_GetCompare1 +****************************************************************************//** +* +* Returns compare value 1. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* Compare value 1. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCompare1(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].CC_BUFF); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_EnableCompareSwap +****************************************************************************//** +* +* Enables the comparison swap when the comparison value is true. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param enable +* true = swap enabled, false = swap disabled +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_Counter_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable) +{ + if (enable) + { + base->CNT[cntNum].CTRL |= TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk; + } + else + { + base->CNT[cntNum].CTRL &= ~TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk; + } +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_SetCounter +****************************************************************************//** +* +* Sets the value of the counter. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param count +* The value to write into the counter. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_Counter_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count) +{ + base->CNT[cntNum].COUNTER = count; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_GetCounter +****************************************************************************//** +* +* Returns the value in the counter. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The current counter value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetCounter(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].COUNTER); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_SetPeriod +****************************************************************************//** +* +* Sets the value of the period register. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param period +* The value to write into a period. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_Counter_SetPeriod(TCPWM_Type *base, uint32_t cntNum, uint32_t period) +{ + base->CNT[cntNum].PERIOD = period; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_Counter_GetPeriod +****************************************************************************//** +* +* Returns the value in the period register. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The current period value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_Counter_GetPeriod(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].PERIOD); +} +/** \} group_tcpwm_functions_counter */ + +/** \} group_tcpwm_counter */ + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_TCPWM_COUNTER_H */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_pwm.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_pwm.c new file mode 100644 index 0000000000..125531d8db --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_pwm.c @@ -0,0 +1,153 @@ +/***************************************************************************//** +* \file cy_tcpwm_pwm.c +* \version 1.0 +* +* \brief +* The source file of the tcpwm driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_tcpwm_pwm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_Init +****************************************************************************//** +* +* Initializes the counter in the TCPWM block for the PWM operation. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_tcpwm_pwm_config_t. +* +* \return error / status code. See \ref cy_en_tcpwm_status_t. +* +*******************************************************************************/ +cy_en_tcpwm_status_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config) +{ + cy_en_tcpwm_status_t status = CY_TCPWM_BAD_PARAM; + + if ((NULL != base) && (NULL != config)) + { + base->CNT[cntNum].CTRL = ( (config->enableCompareSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk : 0uL) | + (config->enablePeriodSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk : 0uL) | + _VAL2FLD(TCPWM_CNT_CTRL_ONE_SHOT, config->runMode) | + _VAL2FLD(TCPWM_CNT_CTRL_UP_DOWN_MODE, config->pwmAlignment) | + _VAL2FLD(TCPWM_CNT_CTRL_MODE, config->pwmMode) | + _VAL2FLD(TCPWM_CNT_CTRL_QUADRATURE_MODE, + (config->invertPWMOut | (config->invertPWMOutN << 1u))) | + (config->killMode << CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_POS) | + _VAL2FLD(TCPWM_CNT_CTRL_GENERIC, ((CY_TCPWM_PWM_MODE_DEADTIME == config->pwmMode) ? + config->deadTimeClocks : config->clockPrescaler))); + + if (CY_TCPWM_PWM_MODE_PSEUDORANDOM == config->pwmMode) + { + base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_UP_DOWN_INIT_VAL; + base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_PWM_MODE_PR; + } + else + { + if (CY_TCPWM_PWM_LEFT_ALIGN == config->pwmAlignment) + { + base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_UP_INIT_VAL; + base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_PWM_MODE_LEFT; + } + else if (CY_TCPWM_PWM_RIGHT_ALIGN == config->pwmAlignment) + { + base->CNT[cntNum].COUNTER = config->period0; + base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_PWM_MODE_RIGHT; + } + else + { + base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_UP_DOWN_INIT_VAL; + base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM; + } + } + + base->CNT[cntNum].CC = config->compare0; + base->CNT[cntNum].CC_BUFF = config->compare1; + base->CNT[cntNum].PERIOD = config->period0; + base->CNT[cntNum].PERIOD_BUFF = config->period1; + + if (CY_TCPWM_INPUT_CREATOR != config->countInput) + { + base->CNT[cntNum].TR_CTRL0 = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_CAPTURE_SEL, config->swapInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, config->reloadInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, config->startInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->killInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->countInput)); + } + + base->CNT[cntNum].TR_CTRL1 = (_VAL2FLD(TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE, config->swapInputMode) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_RELOAD_EDGE, config->reloadInputMode) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_START_EDGE, config->startInputMode) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_STOP_EDGE, config->killInputMode) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_COUNT_EDGE, config->countInputMode)); + + base->CNT[cntNum].INTR_MASK = config->interruptSources; + + status = CY_TCPWM_SUCCESS; + } + + return(status); +} + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_DeInit +****************************************************************************//** +* +* De-initializes the counter in the TCPWM block, returns register values to +* default. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_tcpwm_pwm_config_t. +* +*******************************************************************************/ +void Cy_TCPWM_PWM_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config) +{ + base->CNT[cntNum].CTRL = CY_TCPWM_CNT_CTRL_DEFAULT; + base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_COUNTER_DEFAULT; + base->CNT[cntNum].CC = CY_TCPWM_CNT_CC_DEFAULT; + base->CNT[cntNum].CC_BUFF = CY_TCPWM_CNT_CC_BUFF_DEFAULT; + base->CNT[cntNum].PERIOD = CY_TCPWM_CNT_PERIOD_DEFAULT; + base->CNT[cntNum].PERIOD_BUFF = CY_TCPWM_CNT_PERIOD_BUFF_DEFAULT; + base->CNT[cntNum].TR_CTRL1 = CY_TCPWM_CNT_TR_CTRL1_DEFAULT; + base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_CNT_TR_CTRL2_DEFAULT; + base->CNT[cntNum].INTR = CY_TCPWM_CNT_INTR_DEFAULT; + base->CNT[cntNum].INTR_SET = CY_TCPWM_CNT_INTR_SET_DEFAULT; + base->CNT[cntNum].INTR_MASK = CY_TCPWM_CNT_INTR_MASK_DEFAULT; + + if (CY_TCPWM_INPUT_CREATOR != config->countInput) + { + base->CNT[cntNum].TR_CTRL0 = CY_TCPWM_CNT_TR_CTRL0_DEFAULT; + } +} + + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_pwm.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_pwm.h new file mode 100644 index 0000000000..09c4a3ec47 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_pwm.h @@ -0,0 +1,576 @@ +/***************************************************************************//** +* \file cy_tcpwm_pwm.h +* \version 1.0 +* +* \brief +* The header file of the TCPWM PWM driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_tcpwm_macro_pwm Macro +* \defgroup group_tcpwm_functions_pwm Functions +* \defgroup group_tcpwm_data_structures_pwm Data Structures +* \} */ + +#if !defined(CY_TCPWM_PWM_H) +#define CY_TCPWM_PWM_H + +#include "cy_tcpwm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_tcpwm_pwm +* Driver API for PWM. +* \{ +*/ + +/** +* \addtogroup group_tcpwm_data_structures_pwm +* \{ +*/ + +/** PWM configuration structure */ +typedef struct cy_stc_tcpwm_pwm_config +{ + uint32_t pwmMode; /**< Sets the PWM mode. See \ref group_tcpwm_pwm_modes */ + /** Sets the clock prescaler inside the TCWPM block. See \ref group_tcpwm_pwm_clk_prescalers */ + uint32_t clockPrescaler; + uint32_t pwmAlignment; /**< Sets the PWM alignment. See \ref group_tcpwm_pwm_alignment */ + uint32_t deadTimeClocks; /**< The number of dead time-clocks if PWM with dead time is chosen */ + uint32_t runMode; /**< Sets the PWM run mode. See \ref group_tcpwm_pwm_run_modes */ + uint32_t period0; /**< Sets the period0 of the pwm */ + uint32_t period1; /**< Sets the period1 of the pwm */ + bool enablePeriodSwap; /**< Enables swapping of period 0 and period 1 on terminal count */ + uint32_t compare0; /**< Sets the value for Compare0 */ + uint32_t compare1; /**< Sets the value for Compare1 */ + bool enableCompareSwap; /**< If enabled, the compare values are swapped on the terminal count */ + /** Enables an interrupt on the terminal count, capture or compare. See \ref group_tcpwm_interrupt_sources */ + uint32_t interruptSources; + uint32_t invertPWMOut; /**< Inverts the PWM output */ + uint32_t invertPWMOutN; /**< Inverts the PWM_n output */ + uint32_t killMode; /**< Configures the PWM kill modes. See \ref group_tcpwm_pwm_kill_modes */ + uint32_t swapInputMode; /**< Configures how the swap input behaves. See \ref group_tcpwm_input_modes */ + /** Selects which input the swap uses. Inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t swapInput; + uint32_t reloadInputMode; /**< Configures how the reload input behaves. See \ref group_tcpwm_input_modes */ + /** Selects which input the reload uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t reloadInput; + uint32_t startInputMode; /**< Configures how the start input behaves. See \ref group_tcpwm_input_modes */ + /** Selects which input the start uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t startInput; + uint32_t killInputMode; /**< Configures how the kill input behaves. See \ref group_tcpwm_input_modes */ + /** Selects which input the kill uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t killInput; + uint32_t countInputMode; /**< Configures how the count input behaves. See \ref group_tcpwm_input_modes */ + /** Selects which input the count uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t countInput; +}cy_stc_tcpwm_pwm_config_t; +/** \} group_tcpwm_data_structures_pwm */ + +/** +* \addtogroup group_tcpwm_macro_pwm +* \{ +* \defgroup group_tcpwm_pwm_run_modes PWM run modes +* \{ +* Run modes for the pwm timer. +*/ +#define CY_TCPWM_PWM_ONESHOT (1u) /**< Counter runs once and then stops */ +#define CY_TCPWM_PWM_CONTINUOUS (0u) /**< Counter runs forever */ +/** \} group_tcpwm_pwm_run_modes */ + +/** \defgroup group_tcpwm_pwm_modes PWM modes +* \{ +* Sets the PWM modes. +*/ +#define CY_TCPWM_PWM_MODE_PWM (4u) /**< Standard PWM Mode*/ +#define CY_TCPWM_PWM_MODE_DEADTIME (5u) /**< PWM with deadtime mode*/ +#define CY_TCPWM_PWM_MODE_PSEUDORANDOM (6u) /**< Pseudo Random PWM */ +/** \} group_tcpwm_pwm_modes */ + +/** \defgroup group_tcpwm_pwm_alignment PWM Alignment +* Sets the alignment of the PWM. +* \{ +*/ +#define CY_TCPWM_PWM_LEFT_ALIGN (0u) /**< PWM is left aligned, meaning it starts high */ +#define CY_TCPWM_PWM_RIGHT_ALIGN (1u) /**< PWM is right aligned, meaning it starts low */ +/** PWM is centered aligned, terminal count only occurs on underflow */ +#define CY_TCPWM_PWM_CENTER_ALIGN (2u) +/** PWM is asymmetrically aligned, terminal count occurs on overflow and underflow */ +#define CY_TCPWM_PWM_ASYMMETRIC_ALIGN (3u) +/** \} group_tcpwm_pwm_alignment */ + +/** \defgroup group_tcpwm_pwm_kill_modes PWM kill modes +* Sets the kill mode for the PWM. +* \{ +*/ +#define CY_TCPWM_PWM_STOP_ON_KILL (2u) /**< PWM stops counting on kill */ +#define CY_TCPWM_PWM_SYNCH_KILL (1u) /**< PWM output is killed after next TC*/ +#define CY_TCPWM_PWM_ASYNC_KILL (0u) /**< PWM output is killed instantly */ +/** \} group_tcpwm_pwm_kill_modes */ + +/** \defgroup group_tcpwm_pwm_clk_prescalers PWM CLK Prescaler values +* \{ +* Clock prescaler values. +*/ +#define CY_TCPWM_PWM_PRESCALER_DIVBY_1 (0u) /**< Divide by 1 */ +#define CY_TCPWM_PWM_PRESCALER_DIVBY_2 (1u) /**< Divide by 2 */ +#define CY_TCPWM_PWM_PRESCALER_DIVBY_4 (2u) /**< Divide by 4 */ +#define CY_TCPWM_PWM_PRESCALER_DIVBY_8 (3u) /**< Divide by 8 */ +#define CY_TCPWM_PWM_PRESCALER_DIVBY_16 (4u) /**< Divide by 16 */ +#define CY_TCPWM_PWM_PRESCALER_DIVBY_32 (5u) /**< Divide by 32 */ +#define CY_TCPWM_PWM_PRESCALER_DIVBY_64 (6u) /**< Divide by 64 */ +#define CY_TCPWM_PWM_PRESCALER_DIVBY_128 (7u) /**< Divide by 128 */ +/** \} group_tcpwm_pwm_clk_prescalers */ + +/** \defgroup group_tcpwm_pwm_output_invert PWM output invert +* \{ +* Output invert modes. +*/ +#define CY_TCPWM_PWM_INVERT_ENABLE (1u) /**< Invert the output mode */ +#define CY_TCPWM_PWM_INVERT_DISABLE (0u) /**< Do not invert the output mode */ +/** \} group_tcpwm_pwm_output_invert */ + +/** \defgroup group_tcpwm_pwm_status PWM Status +* \{ +* The counter status. +*/ +#define CY_TCPWM_PWM_STATUS_DOWN_COUNTING (0x1uL) /**< PWM is down counting */ +#define CY_TCPWM_PWM_STATUS_UP_COUNTING (0x2uL) /**< PWM is up counting */ +#define CY_TCPWM_PWM_STATUS_COUNTER_RUNNING (TCPWM_CNT_STATUS_RUNNING_Msk) /**< PWM counter is running */ +/** \} group_tcpwm_pwm_status */ + + +/*************************************** +* Registers Constants +***************************************/ + +/** \cond INTERNAL */ +#define CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_POS (2u) +#define CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_MASK (0x3uL << CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_POS) +/** \endcond */ + +/** \defgroup group_tcpwm_pwm_output_configuration PWM output signal configuration +* \{ +* The configuration of PWM output signal for PWM alignment. +*/ +#define CY_TCPWM_PWM_TR_CTRL2_SET (0uL) /**< Set define for PWM output signal configuration */ +#define CY_TCPWM_PWM_TR_CTRL2_CLEAR (1uL) /**< Clear define for PWM output signal configuration */ +#define CY_TCPWM_PWM_TR_CTRL2_INVERT (2uL) /**< Invert define for PWM output signal configuration */ +#define CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE (3uL) /**< No change define for PWM output signal configuration */ + +/** The configuration of PWM output signal in Pseudo Random Mode */ +#define CY_TCPWM_PWM_MODE_PR (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE)) + +/** The configuration of PWM output signal for Left alignment */ +#define CY_TCPWM_PWM_MODE_LEFT (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_SET) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE)) + +/** The configuration of PWM output signal for Right alignment */ +#define CY_TCPWM_PWM_MODE_RIGHT (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_SET) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_NO_CHANGE) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR)) + +/** The configuration of PWM output signal for Center and Asymmetric alignment */ +#define CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_INVERT) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_SET) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR)) +/** \} group_tcpwm_pwm_output_configuration */ +/** \} group_tcpwm_macro_pwm */ + + +/******************************************************************************* +* Function Prototypes +*******************************************************************************/ + +/** +* \addtogroup group_tcpwm_functions_pwm +* \{ +*/ + +cy_en_tcpwm_status_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config); +void Cy_TCPWM_PWM_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config); +__STATIC_INLINE void Cy_TCPWM_PWM_Enable(TCPWM_Type *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_PWM_Disable(TCPWM_Type *base, uint32_t cntNum); +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetStatus(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0); +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare0(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1); +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare1(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_PWM_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable); +__STATIC_INLINE void Cy_TCPWM_PWM_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count); +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCounter(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod0(TCPWM_Type *base, uint32_t cntNum, uint32_t period0); +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod0(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod1(TCPWM_Type *base, uint32_t cntNum, uint32_t period1); +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod1(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cntNum, bool enable); + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_Enable +****************************************************************************//** +* +* Enables the counter in the TCPWM block for the PWM operation. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_PWM_Enable(TCPWM_Type *base, uint32_t cntNum) +{ + base->CTRL_SET = (1uL << cntNum); +} + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_Disable +****************************************************************************//** +* +* Disables the counter in the TCPWM block. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_PWM_Disable(TCPWM_Type *base, uint32_t cntNum) +{ + base->CTRL_CLR = (1uL << cntNum); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_GetStatus +****************************************************************************//** +* +* Returns the status of the PWM. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The status. See \ref group_tcpwm_pwm_status +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetStatus(TCPWM_Type const *base, uint32_t cntNum) +{ + uint32_t status = base->CNT[cntNum].STATUS; + + /* Generates proper up counting status, does not generated by HW */ + status &= ~CY_TCPWM_PWM_STATUS_UP_COUNTING; + status |= ((~status & CY_TCPWM_PWM_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) << + CY_TCPWM_CNT_STATUS_UP_POS); + + return(status); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_SetCompare0 +****************************************************************************//** +* +* Sets the compare value for Compare0 when the compare mode enabled. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param compare0 +* The Compare0 value. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare0(TCPWM_Type *base, uint32_t cntNum, uint32_t compare0) +{ + base->CNT[cntNum].CC = compare0; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_GetCompare0 +****************************************************************************//** +* +* Returns compare value 0. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* Compare value 0. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare0(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].CC); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_SetCompare1 +****************************************************************************//** +* +* Sets the compare value for Compare1 when the compare mode is enabled. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param compare1 +* The Compare1 value. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_PWM_SetCompare1(TCPWM_Type *base, uint32_t cntNum, uint32_t compare1) +{ + base->CNT[cntNum].CC_BUFF = compare1; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_GetCompare1 +****************************************************************************//** +* +* Returns compare value 1. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* Compare value 1. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCompare1(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].CC_BUFF); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_EnableCompareSwap +****************************************************************************//** +* +* Enables the comparison swap on OV and/or UN, depending on the PWM alignment. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param enable +* true = swap enabled; false = swap disabled +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_PWM_EnableCompareSwap(TCPWM_Type *base, uint32_t cntNum, bool enable) +{ + if (enable) + { + base->CNT[cntNum].CTRL |= TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk; + } + else + { + base->CNT[cntNum].CTRL &= ~TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk; + } +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_SetCounter +****************************************************************************//** +* +* Sets the value of the counter. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param count +* The value to write into the counter. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_PWM_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count) +{ + base->CNT[cntNum].COUNTER = count; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_GetCounter +****************************************************************************//** +* +* Returns the value in the counter. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The current counter value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetCounter(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].COUNTER); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_SetPeriod0 +****************************************************************************//** +* +* Sets the value of the period register. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param period0 +* The value to write into a period. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod0(TCPWM_Type *base, uint32_t cntNum, uint32_t period0) +{ + base->CNT[cntNum].PERIOD = period0; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_GetPeriod0 +****************************************************************************//** +* +* Returns the value in the period register. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The current period value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod0(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].PERIOD); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_SetPeriod1 +****************************************************************************//** +* +* Sets the value of the period register. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param period1 +* The value to write into a period1. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_PWM_SetPeriod1(TCPWM_Type *base, uint32_t cntNum, uint32_t period1) +{ + base->CNT[cntNum].PERIOD_BUFF = period1; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_GetPeriod1 +****************************************************************************//** +* +* Returns the value in the period register. +* +* \param base +* The pointer to a COUNTER PWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The current period value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_PWM_GetPeriod1(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].PERIOD_BUFF); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_PWM_EnablePeriodSwap +****************************************************************************//** +* +* Enables a period swap on OV and/or UN, depending on the PWM alignment +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param enable +* true = swap enabled; false = swap disabled +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_PWM_EnablePeriodSwap(TCPWM_Type *base, uint32_t cntNum, bool enable) +{ + if (enable) + { + base->CNT[cntNum].CTRL |= TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk; + } + else + { + base->CNT[cntNum].CTRL &= ~TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk; + } +} + +/** \} group_tcpwm_functions_pwm */ + +/** \} group_tcpwm_pwm */ + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_TCPWM_PWM_H */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_quaddec.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_quaddec.c new file mode 100644 index 0000000000..9558e49d51 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_quaddec.c @@ -0,0 +1,116 @@ +/***************************************************************************//** +* \file cy_tcpwm_quaddec.c +* \version 1.0 +* +* \brief +* The source file of the tcpwm driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_tcpwm_quaddec.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_TCPWM_QuadDec_Init +****************************************************************************//** +* +* Initializes the counter in the TCPWM block for the QuadDec operation. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_tcpwm_quaddec_config_t. +* +* \return error / status code. See \ref cy_en_tcpwm_status_t. +* +*******************************************************************************/ +cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config) +{ + cy_en_tcpwm_status_t status = CY_TCPWM_BAD_PARAM; + + if ((NULL != base) && (NULL != config)) + { + base->CNT[cntNum].CTRL = ( _VAL2FLD(TCPWM_CNT_CTRL_QUADRATURE_MODE, config->resolution) | + _VAL2FLD(TCPWM_CNT_CTRL_MODE, CY_TCPWM_QUADDEC_CTRL_QUADDEC_MODE)); + + if (CY_TCPWM_INPUT_CREATOR != config->phiAInput) + { + base->CNT[cntNum].TR_CTRL0 = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->phiAInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, config->phiBInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, config->indexInput) | + _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->stopInput)); + } + + base->CNT[cntNum].TR_CTRL1 = (_VAL2FLD(TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE, CY_TCPWM_INPUT_LEVEL) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_COUNT_EDGE, CY_TCPWM_INPUT_LEVEL) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_START_EDGE, CY_TCPWM_INPUT_LEVEL) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_RELOAD_EDGE, config->indexInputMode) | + _VAL2FLD(TCPWM_CNT_TR_CTRL1_STOP_EDGE, config->stopInputMode)); + + base->CNT[cntNum].INTR_MASK = config->interruptSources; + + status = CY_TCPWM_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_QuadDec_DeInit +****************************************************************************//** +* +* De-initializes the counter in the TCPWM block, returns register values to +* default. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_tcpwm_quaddec_config_t. +* +*******************************************************************************/ +void Cy_TCPWM_QuadDec_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config) +{ + base->CNT[cntNum].CTRL = CY_TCPWM_CNT_CTRL_DEFAULT; + base->CNT[cntNum].COUNTER = CY_TCPWM_CNT_COUNTER_DEFAULT; + base->CNT[cntNum].CC = CY_TCPWM_CNT_CC_DEFAULT; + base->CNT[cntNum].CC_BUFF = CY_TCPWM_CNT_CC_BUFF_DEFAULT; + base->CNT[cntNum].PERIOD = CY_TCPWM_CNT_PERIOD_DEFAULT; + base->CNT[cntNum].PERIOD_BUFF = CY_TCPWM_CNT_PERIOD_BUFF_DEFAULT; + base->CNT[cntNum].TR_CTRL1 = CY_TCPWM_CNT_TR_CTRL1_DEFAULT; + base->CNT[cntNum].TR_CTRL2 = CY_TCPWM_CNT_TR_CTRL2_DEFAULT; + base->CNT[cntNum].INTR = CY_TCPWM_CNT_INTR_DEFAULT; + base->CNT[cntNum].INTR_SET = CY_TCPWM_CNT_INTR_SET_DEFAULT; + base->CNT[cntNum].INTR_MASK = CY_TCPWM_CNT_INTR_MASK_DEFAULT; + + if (CY_TCPWM_INPUT_CREATOR != config->phiAInput) + { + base->CNT[cntNum].TR_CTRL0 = CY_TCPWM_CNT_TR_CTRL0_DEFAULT; + } +} + + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_quaddec.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_quaddec.h new file mode 100644 index 0000000000..adbb7c826f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/tcpwm/cy_tcpwm_quaddec.h @@ -0,0 +1,281 @@ +/***************************************************************************//** +* \file cy_tcpwm_quaddec.h +* \version 1.0 +* +* \brief +* The header file of the TCPWM Quadrature Decoder driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_tcpwm_macro_quaddec Macro +* \defgroup group_tcpwm_functions_quaddec Functions +* \defgroup group_tcpwm_data_structures_quaddec Data Structures +* \} */ + +#if !defined(CY_TCPWM_QUADDEC_H) +#define CY_TCPWM_QUADDEC_H + +#include "cy_tcpwm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_tcpwm_quaddec +* Driver API for Quadrature Decoder. +* \{ +*/ + +/** +* \addtogroup group_tcpwm_data_structures_quaddec +* \{ +*/ + +/** Quadrature Decoder configuration structure */ +typedef struct cy_stc_tcpwm_quaddec_config +{ + /** Selects the quadrature encoding mode. See \ref group_tcpwm_quaddec_resolution */ + uint32_t resolution; + /** Enables an interrupt on the terminal count, capture or compare. See \ref group_tcpwm_interrupt_sources */ + uint32_t interruptSources; + /** Configures how the index input behaves. See \ref group_tcpwm_input_modes */ + uint32_t indexInputMode; + /** Selects which input the index uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t indexInput; + /** Configures how the stop input behaves. See \ref group_tcpwm_input_modes */ + uint32_t stopInputMode; + /** Selects which input the stop uses. The inputs are device-specific. See \ref group_tcpwm_input_selection */ + uint32_t stopInput; + /** Selects which input the phiA uses. The inputs are device specific. See \ref group_tcpwm_input_selection */ + uint32_t phiAInput; + /** Selects which input the phiB uses. The inputs are device specific. See \ref group_tcpwm_input_selection */ + uint32_t phiBInput; + +}cy_stc_tcpwm_quaddec_config_t; +/** \} group_tcpwm_data_structures_quaddec */ + +/** +* \addtogroup group_tcpwm_macro_quaddec +* \{ +* \defgroup group_tcpwm_quaddec_resolution QuadDec Resolution +* \{ +* The quadrature decoder resolution. +*/ +#define CY_TCPWM_QUADDEC_X1 (0u) /**< X1 mode */ +#define CY_TCPWM_QUADDEC_X2 (1u) /**< X2 mode */ +#define CY_TCPWM_QUADDEC_X4 (2u) /**< X4 mode */ +/** \} group_tcpwm_quaddec_resolution */ + +/** \defgroup group_tcpwm_quaddec_status QuadDec Status +* \{ +* The counter status. +*/ +#define CY_TCPWM_QUADDEC_STATUS_DOWN_COUNTING (0x1uL) /**< QuadDec is down counting */ +#define CY_TCPWM_QUADDEC_STATUS_UP_COUNTING (0x2uL) /**< QuadDec is up counting */ +/** QuadDec the counter is running */ +#define CY_TCPWM_QUADDEC_STATUS_COUNTER_RUNNING (TCPWM_CNT_STATUS_RUNNING_Msk) +/** \} group_tcpwm_quaddec_status */ + + +/*************************************** +* Registers Constants +***************************************/ +/** \cond INTERNAL */ +#define CY_TCPWM_QUADDEC_CTRL_QUADDEC_MODE (0x3uL) /**< Quadrature encoding mode for CTRL register */ +/** \endcond */ +/** \} group_tcpwm_macro_quaddec */ + + +/******************************************************************************* +* Function Prototypes +*******************************************************************************/ + +/** +* \addtogroup group_tcpwm_functions_quaddec +* \{ +*/ + +cy_en_tcpwm_status_t Cy_TCPWM_QuadDec_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config); +void Cy_TCPWM_QuadDec_DeInit(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_quaddec_config_t const *config); +__STATIC_INLINE void Cy_TCPWM_QuadDec_Enable(TCPWM_Type *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_QuadDec_Disable(TCPWM_Type *base, uint32_t cntNum); +__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetStatus(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCapture(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCaptureBuf(TCPWM_Type const *base, uint32_t cntNum); +__STATIC_INLINE void Cy_TCPWM_QuadDec_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count); +__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCounter(TCPWM_Type const *base, uint32_t cntNum); + + +/******************************************************************************* +* Function Name: Cy_TCPWM_QuadDec_Enable +****************************************************************************//** +* +* Enables the counter in the TCPWM block for the QuadDec operation. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_QuadDec_Enable(TCPWM_Type *base, uint32_t cntNum) +{ + base->CTRL_SET = (1uL << cntNum); +} + +/******************************************************************************* +* Function Name: Cy_TCPWM_QuadDec_Disable +****************************************************************************//** +* +* Disables the counter in the TCPWM block. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_QuadDec_Disable(TCPWM_Type *base, uint32_t cntNum) +{ + base->CTRL_CLR = (1uL << cntNum); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_QuadDec_GetStatus +****************************************************************************//** +* +* Returns the status of the QuadDec. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The status. See \ref group_tcpwm_quaddec_status +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetStatus(TCPWM_Type const *base, uint32_t cntNum) +{ + uint32_t status = base->CNT[cntNum].STATUS; + + /* Generates proper up counting status, does not generated by HW */ + status &= ~CY_TCPWM_QUADDEC_STATUS_UP_COUNTING; + status |= ((~status & CY_TCPWM_QUADDEC_STATUS_DOWN_COUNTING & (status >> TCPWM_CNT_STATUS_RUNNING_Pos)) << + CY_TCPWM_CNT_STATUS_UP_POS); + + return(status); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_QuadDec_GetCapture +****************************************************************************//** +* +* Returns the capture value. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The capture value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCapture(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].CC); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_QuadDec_GetCaptureBuf +****************************************************************************//** +* +* Returns the buffered capture value. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The buffered capture value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCaptureBuf(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].CC_BUFF); +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_QuadDec_SetCounter +****************************************************************************//** +* +* Sets the value of the counter. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \param count +* The value to write into the counter. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_TCPWM_QuadDec_SetCounter(TCPWM_Type *base, uint32_t cntNum, uint32_t count) +{ + base->CNT[cntNum].COUNTER = count; +} + + +/******************************************************************************* +* Function Name: Cy_TCPWM_QuadDec_GetCounter +****************************************************************************//** +* +* Returns the value in the counter. +* +* \param base +* The pointer to a TCPWM instance. +* +* \param cntNum +* The Counter instance number in the selected TCPWM. +* +* \return +* The current counter value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_TCPWM_QuadDec_GetCounter(TCPWM_Type const *base, uint32_t cntNum) +{ + return(base->CNT[cntNum].COUNTER); +} + +/** \} group_tcpwm_functions_quaddec */ + +/** \} group_tcpwm_quaddec */ + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_TCPWM_QUADDEC_H */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/trigmux/cy_trigmux.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/trigmux/cy_trigmux.c new file mode 100644 index 0000000000..f7411e3563 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/trigmux/cy_trigmux.c @@ -0,0 +1,112 @@ +/***************************************************************************//** +* \file +* \version 1.0 +* +* \brief Trigger mux APIs. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#include "cy_trigmux.h" + + +/******************************************************************************* +* Function Name: Cy_TrigMux_Connect +****************************************************************************//** +* +* This function connects an input trigger source and output trigger. +* +* \param inTrig +* An input selection for the trigger mux. +* - Bits 11:8 represent the trigger group selection. +* - Bits 6:0 select the input trigger number in the trigger group. +* +* \param outTrig +* The output of the trigger mux. This refers to the consumer of the trigger mux. +* - Bits 11:8 represent the trigger group selection. +* - Bits 6:0 select the output trigger number in the trigger group. +* +* \param invert +* - CY_TR_MUX_TR_INV_ENABLE: The output trigger is inverted. +* - CY_MUX_TR_INV_DISABLE: The output trigger is not inverted. +* +* \param trigType +* - TRIGGER_TYPE_EDGE: The trigger is synchronized to the consumer blocks clock +* and a two-cycle pulse is generated on this clock. +* - TRIGGER_TYPE_LEVEL: The trigger is a simple level output. +* +* \return +* A status +* - 0: Successful connection made. +* - 1: An invalid input selection corresponding to the output. +* Generally when the trigger groups do not match. +* +*******************************************************************************/ +cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, uint32_t invert, en_trig_type_t trigType) +{ + volatile uint32_t* trOutCtlAddr; + cy_en_trigmux_status_t retVal = CY_TRIGMUX_BAD_PARAM; + + if ((inTrig & CY_TR_GROUP_MASK) == (outTrig & CY_TR_GROUP_MASK)) + { + trOutCtlAddr = &(PERI->TR_GR[(outTrig & CY_TR_GROUP_MASK) >> CY_TR_GROUP_SHIFT].TR_OUT_CTL[outTrig & CY_TR_MASK]); + + *trOutCtlAddr = _VAL2FLD(PERI_TR_GR_TR_OUT_CTL_TR_SEL, inTrig) | + _VAL2FLD(PERI_TR_GR_TR_OUT_CTL_TR_INV, invert) | + _VAL2FLD(PERI_TR_GR_TR_OUT_CTL_TR_EDGE, trigType); + + retVal = CY_TRIGMUX_SUCCESS; + } + + return retVal; +} + + +/******************************************************************************* +* Function Name: Cy_TrigMux_SwTrigger +****************************************************************************//** +* +* This function generates a software trigger on an input trigger line. +* All output triggers connected to this input trigger will be triggered. +* The function also verifies that there is no activated trigger before +* generating another activation. +* +* \param trigLine +* The input of the trigger mux. +* - Bit 12 represents if the signal is an input/output. +* - Bits 11:8 represent the trigger group selection. +* - Bits 6:0 select the output trigger number in the trigger group. +* +* \param cycles +* The number of cycles during which the trigger remains activated. +* - The valid range: 1-254 cycles. +* +* \return +* A status +* - 0: If there was not an already activated trigger. +* - 1: If there was an already activated trigger. +* +*******************************************************************************/ +cy_en_trigmux_status_t Cy_TrigMux_SwTrigger(uint32_t trigLine, uint32_t cycles) +{ + cy_en_trigmux_status_t retVal = CY_TRIGMUX_INVALID_STATE; + + if (PERI_TR_CMD_ACTIVATE_Msk != (PERI->TR_CMD & PERI_TR_CMD_ACTIVATE_Msk)) + { + PERI->TR_CMD = _VAL2FLD(PERI_TR_CMD_TR_SEL, (trigLine & CY_TR_MASK)) | + _VAL2FLD(PERI_TR_CMD_GROUP_SEL, ((trigLine & CY_TR_GROUP_MASK) >> CY_TR_GROUP_SHIFT)) | + _VAL2FLD(PERI_TR_CMD_COUNT, cycles) | + _VAL2FLD(PERI_TR_CMD_OUT_SEL, (trigLine & CY_TR_OUT_CTL_MASK) >> CY_TR_OUT_CTL_SHIFT) | + _VAL2FLD(PERI_TR_CMD_ACTIVATE, CY_TR_ACTIVATE_ENABLE); + + retVal = CY_TRIGMUX_SUCCESS; + } + + return retVal; +} + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/trigmux/cy_trigmux.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/trigmux/cy_trigmux.h new file mode 100644 index 0000000000..d9e44467f7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/trigmux/cy_trigmux.h @@ -0,0 +1,199 @@ +/******************************************************************************* +* \file cy_trigmux.h +* \version 1.0 +* +* This file provides constants and parameter values for the Trigger multiplexer driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_trigmux Trigger multiplexer (TrigMux) +* \{ +* The trigger multiplexer provides access to the multiplexer that selects a set +* of trigger output signals from different peripheral blocks to route them to the +* specific trigger input of another peripheral block. +* +* The TrigMux driver is based on the trigger multiplexer's hardware block. +* The Trigger multiplexer block consists of multiple trigger multiplexers. +* These trigger multiplexers are grouped in trigger groups. All the trigger +* multiplexers in the trigger group share similar input options. The trigger +* multiplexer groups are either reduction multiplexers or distribution multiplexers. +* The reduction multiplexer groups have input options that are the trigger outputs +* coming from the different peripheral blocks and the reduction multiplexer groups +* route them to intermediate signals. The distribution multiplexer groups have input +* options from these intermediate signals and route them back to multiple peripheral +* blocks as their trigger inputs. +* +* The trigger architecture of the PSoC device is explained in the technical reference +* manual (TRM). Refer to the TRM to better understand the trigger multiplexer routing +* architecture available. +* +* \section group_trigmux_section_Configuration_Considerations Configuration Considerations +* +* +* To route a trigger signal from one peripheral in the PSoC +* to another, the user must configure a reduction multiplexer and a distribution +* multiplexer. The Cy_TrigMux_connect() is used to configure a trigger multiplexer connection. +* The user will need two calls of this API, one for the reduction multiplexer and another +* for the distribution multiplexer, to achieve the trigger connection from a source +* peripheral to a destination peripheral. The Cy_TrigMux_connect() function has two main +* parameters, inTrig and outTrig that refer to the input and output trigger signals +* connected using the multiplexer. +* +* These parameters are represented in the following format: +* \image html trigmux/docs/trigmux_parameter.png +* In addition, the Cy_TrigMux_connect() function also has an invert and trigger type parameter. +* Refer to the API reference for a detailed description of this parameter. +* All the constants associated with the different trigger signals in the system +* (input and output) are defined as constants in the device configuration header file. +* The constants for TrigMux in the device configuration header file are divided into four +* types based on the signal being input/output and being part of a reduction/distribution +* trigger multiplexer. +* +* The four types of the input/output parameters are: +* 1) The parameters for the reduction multiplexer's inputs (input signals of TrigMux); +* 2) The parameters for the reduction multiplexer's outputs (intermediate signals); +* 3) The parameters for the distribution multiplexer's inputs (intermediate signals); +* 4) The parameters for the distribution multiplexer's outputs (output signals of TrigMux). +* Refer to the TRM for a more detailed description of this architecture and different options. +* +* The steps to connect one peripheral block to the other: +* +* Step 1. Find the trigger group number in the Trigger Group Inputs section of the device +* configuration header file that corresponds to the output of the first peripheral block. +* For example, TRIG10_IN_CPUSS_DW0_TR_OUT4 input of the reduction multiplexers belongs +* to Trigger Group 10. +* +* Step 2. Find the trigger group number in the Trigger Group Outputs section of the device +* configuration header file that corresponds to the input of the second peripheral block. +* For example, TRIG3_OUT_TCPWM1_TR_IN0 output of the distribution multiplexer belongs to +* Trigger Group 3. +* +* Step 3. Find the same trigger group number in the Trigger Group Inputs section of the +* device configuration header file that corresponds to the trigger group number found in +* Step 1. Select the reduction multiplexer output that can be connected to the trigger group +* found in Step 2. For example, TRIG3_IN_TR_GROUP10_OUTPUT5 means that Reduction Multiplexer +* Output 5 of Trigger Group 10 can be connected to Trigger Group 3. +* +* Step 4. Find the same trigger group number in the Trigger Group Outputs section of the +* device configuration header file that corresponds to the trigger group number found in Step 2. +* Select the distribution multiplexer input that can be connected to the trigger group found +* in Step 1. For example, TRIG10_OUT_TR_GROUP3_INPUT1 means that the Distribution Multiplexer +* Input 1 of Trigger Group 3 can be connected to the output of the reduction multiplexer +* in Trigger Group 10 found in Step 3. +* +* Step 5. Call Cy_TrigMux_Connect() API twice: the first call - with the constants for the +* inTrig and outTrig parameters found in Steps 1 and Step 4, the second call - with the +* constants for the inTrig and outTrig parameters found in Steps 2 and Step 3. +* For example, +* Cy_TrigMux_Connect(TRIG10_IN_CPUSS_DW0_TR_OUT4, TRIG10_OUT_TR_GROUP3_INPUT1, +* TR_MUX_TR_INV_DISABLE, TRIGGER_TYPE_LEVEL); +* Cy_TrigMux_Connect(TRIG3_IN_TR_GROUP10_OUTPUT5, TRIG3_OUT_TCPWM1_TR_IN0, +* TR_MUX_TR_INV_DISABLE, TRIGGER_TYPE_LEVEL); +* +* \section group_trigmux_more_information More Information +* For more information on the TrigMux peripheral, refer to the technical reference manual (TRM). +* +* \section group_trigmux_MISRA MISRA-C Compliance +* The TrigMux driver does not have any specific deviations. +* +* \section group_trigmux_Changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_trigmux_macro Macro +* \defgroup group_trigmux_functions Functions +* \defgroup group_trigmux_enums Enumerated Types +*/ + +#if !defined(CY_TRIGMUX_H) +#define CY_TRIGMUX_H + +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_trigmux_macro +* \{ +*/ + +/** The driver major version */ +#define CY_TRIGMUX_DRV_VERSION_MAJOR 1 + +/** The driver minor version */ +#define CY_TRIGMUX_DRV_VERSION_MINOR 0 + +/**< TRIGMUX PDL ID */ +#define CY_TRIGMUX_ID CY_PDL_DRV_ID(0x33u) /**< The trigger multiplexer driver identifier */ + +#define CY_TR_MUX_TR_INV_ENABLE (0x01u) /**< Enable trigger invert */ +#define CY_TR_MUX_TR_INV_DISABLE (0x00u) /**< Disable trigger invert */ + +/** \cond */ + +#define CY_TR_ACTIVATE_ENABLE (0x01u) +#define CY_TR_GROUP_MASK (0x0F00u) +#define CY_TR_MASK (0x007Fu) +#define CY_TR_GROUP_SHIFT (0x08u) +#define CY_TR_OUT_CTL_MASK (0x1000u) +#define CY_TR_OUT_CTL_SHIFT (12u) + +/** \endcond */ + +/** \} group_trigmux_macro */ + + +/** +* \addtogroup group_trigmux_enums +* \{ +*/ + +/****************************************************************************** + * Enumerations + *****************************************************************************/ + +/** The TRIGMUX error codes. */ +typedef enum +{ + CY_TRIGMUX_SUCCESS = 0x00u, /**< Successful */ + CY_TRIGMUX_BAD_PARAM = CY_TRIGMUX_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */ + CY_TRIGMUX_INVALID_STATE = CY_TRIGMUX_ID | CY_PDL_STATUS_ERROR | 0x02u /**< Operation not setup or is in an improper state */ +} cy_en_trigmux_status_t; + +/** \} group_trigmux_enums */ + +/** +* \addtogroup group_trigmux_functions +* \{ +*/ + +cy_en_trigmux_status_t Cy_TrigMux_Connect(uint32_t inTrig, uint32_t outTrig, uint32_t invert, en_trig_type_t trigType); +cy_en_trigmux_status_t Cy_TrigMux_SwTrigger(uint32_t trigLine, uint32_t cycles); + +/** \} group_trigmux_functions */ + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_TRIGMUX_H */ + +/** \} group_lpcomp */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/wdt/cy_wdt.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/wdt/cy_wdt.c new file mode 100644 index 0000000000..6e4662419c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/wdt/cy_wdt.c @@ -0,0 +1,303 @@ +/***************************************************************************//** +* \file cy_wdt.c +* \version 1.0 +* +* This file provides the source code to the API for the WDT driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_wdt.h" +#include "syslib/cy_syslib.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +static bool Cy_WDT_Locked(void); + + +/******************************************************************************* +* Function Name: Cy_WDT_Init +****************************************************************************//** +* +* Initialize the Watchdog Timer to its default state. +* +* The default setting of WDT is given as following: +* Whole the Watchdog Timer register counter bits are checked against the match. +* WDT match value is equal - 4096. +* +*******************************************************************************/ +void Cy_WDT_Init(void) +{ + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + + /* Unlocking WDT by two writes */ + SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_SRSS_WDT_LOCK_BIT0); + + SRSS->WDT_CTL |= CY_SRSS_WDT_LOCK_BIT1; + + /* Disabling WDT and setting default values */ + Cy_WDT_Disable(); + + Cy_WDT_SetMatch(CY_SRSS_WDT_DEFAULT_MATCH_VALUE); + + Cy_WDT_SetIgnoreBits(CY_SRSS_WDT_DEFAULT_IGNORE_BITS); + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_WDT_Enable +****************************************************************************//** +* +* Enables Watchdog Timer. +* +*******************************************************************************/ +void Cy_WDT_Enable(void) +{ + SRSS->WDT_CTL |= _VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1u); +} + + +/******************************************************************************* +* Function Name: Cy_WDT_Disable +****************************************************************************//** +* +* Disables Watchdog Timer. Watchdog Timer should be unlocked before it is being +* disabled. Call Cy_WDT_Unlock() API to unlock WDT. +* +*******************************************************************************/ +void Cy_WDT_Disable(void) +{ + SRSS->WDT_CTL &= ((uint32_t) ~(_VAL2FLD(SRSS_WDT_CTL_WDT_EN, 1u))); +} + + +/******************************************************************************* +* Function Name: Cy_WDT_Lock +****************************************************************************//** +* +* Locks out configuration changes to the Watchdog Timer register. +* +* After this function is called, the WDT configuration cannot be changed until +* Cy_WDT_Unlock() is called. +* +*******************************************************************************/ +void Cy_WDT_Lock(void) +{ + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + + SRSS->WDT_CTL |= _VAL2FLD(SRSS_WDT_CTL_WDT_LOCK, CY_SRSS_WDT_LOCK_BITS); + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_WDT_Locked +****************************************************************************//** +* \internal +* Reports the WDT lock state. +* +* \return TRUE - if WDT is locked, and FALSE - if WDT is unlocked. +* \endinternal +*******************************************************************************/ +static bool Cy_WDT_Locked(void) +{ + /* Prohibits writing to WDT registers and LFCLK */ + return (0u != _FLD2VAL(SRSS_WDT_CTL_WDT_LOCK, SRSS->WDT_CTL)); +} + + +/******************************************************************************* +* Function Name: Cy_WDT_Unlock +****************************************************************************//** +* +* \brief Unlocks the Watchdog Timer configuration register. +* +*******************************************************************************/ +void Cy_WDT_Unlock(void) +{ + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + + /* Removing WDT lock requires to be done by two writes */ + SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_SRSS_WDT_LOCK_BIT0); + + SRSS->WDT_CTL |= CY_SRSS_WDT_LOCK_BIT1; + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: WDT_SetMatch +****************************************************************************//** +* +* Configures the WDT counter match comparison value. Watchdog Timer +* should be unlocked before changing the match value. Call the Cy_WDT_Unlock() +* function to unlock WDT. +* +* \param match The valid valid range is [0-65535]. The value to be used to match +* against the counter. +* +*******************************************************************************/ +void Cy_WDT_SetMatch(uint32_t match) +{ + if (false == Cy_WDT_Locked()) + { + SRSS->WDT_MATCH = _CLR_SET_FLD32U((SRSS->WDT_MATCH), SRSS_WDT_MATCH_MATCH, match); + } +} + + +/******************************************************************************* +* Function Name: Cy_WDT_GetMatch +****************************************************************************//** +* +* Reads the WDT counter match comparison value. +* +* \return The counter match value. +* +*******************************************************************************/ +uint32_t Cy_WDT_GetMatch(void) +{ + return ((uint32_t) _FLD2VAL(SRSS_WDT_MATCH_MATCH, SRSS->WDT_MATCH)); +} + + +/******************************************************************************* +* Function Name: Cy_WDT_GetCount +****************************************************************************//** +* +* Reads the current WDT counter value. +* +* \return A live counter value. +* +*******************************************************************************/ +uint32_t Cy_WDT_GetCount(void) +{ + return ((uint32_t) _FLD2VAL(SRSS_WDT_CNT_COUNTER, SRSS->WDT_CNT)); +} + + +/******************************************************************************* +* Function Name: Cy_WDT_SetIgnoreBits +****************************************************************************//** +* +* Configures the number of the most significant bits of the Watchdog Timer that +* are not checked against the match. Watchdog Timer should be unlocked before +* ignore bits setting. Call the Cy_WDT_Unlock() API to unlock WDT. +* +* \param +* bitsNum The number of the most significant bits. Valid range is [0-15]. +* The bitsNum over 12 are considered as 12. +* +* \details The value of bitsNum controls the time-to-reset of the Watchdog Timer +* (which happens after 3 successive matches). +* +* \warning As this function change the WDT interrupt period, there are possible +* situations when device can go into infinite WDT resets loop. Such situations +* are caused by condition that WDT reset occurs faster that device start-up. +* +*******************************************************************************/ +void Cy_WDT_SetIgnoreBits(uint32_t bitsNum) +{ + if (false == Cy_WDT_Locked()) + { + SRSS->WDT_MATCH = _CLR_SET_FLD32U((SRSS->WDT_MATCH), SRSS_WDT_MATCH_IGNORE_BITS, bitsNum); + } +} + + +/******************************************************************************* +* Function Name: Cy_WDT_GetIgnoreBits +****************************************************************************//** +* +* Reads the number of the most significant bits of the Watchdog Timer that are +* not checked against the match. +* +* \return The number of the most significant bits. +* +*******************************************************************************/ +uint32_t Cy_WDT_GetIgnoreBits(void) +{ + return((uint32_t) _FLD2VAL(SRSS_WDT_MATCH_IGNORE_BITS ,SRSS->WDT_MATCH)); +} + + +/******************************************************************************* +* Function Name: Cy_WDT_ClearInterrupt +****************************************************************************//** +* +* Cleans the WDT match flag which is set every time the WDT counter reaches a +* WDT match value. Two unserviced interrupts lead to a system reset +* (i.e. at the third match). +* +*******************************************************************************/ +void Cy_WDT_ClearInterrupt(void) +{ + SRSS->SRSS_INTR |= _VAL2FLD(SRSS_SRSS_INTR_WDT_MATCH, 1u); + + /* Read SRSS register to ensure that the initial clearing write has been + * flushed out to the hardware. + */ + (void) SRSS->SRSS_INTR; +} + + +/******************************************************************************* +* Function Name: Cy_WDT_MaskInterrupt +****************************************************************************//** +* +* After masking interrupts from WDT, they are not passed to CPU. +* This function does not disable the WDT-reset generation. +* +*******************************************************************************/ +void Cy_WDT_MaskInterrupt(void) +{ + SRSS->SRSS_INTR_MASK &= (uint32_t)(~ _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1u)); +} + + +/******************************************************************************* +* Function Name: Cy_WDT_UnmaskInterrupt +****************************************************************************//** +* +* After unmasking interrupts from WDT, they are passed to CPU. +* This function does not impact the reset generation. +* +*******************************************************************************/ +void Cy_WDT_UnmaskInterrupt(void) +{ + SRSS->SRSS_INTR_MASK |= _VAL2FLD(SRSS_SRSS_INTR_MASK_WDT_MATCH, 1u); +} + + +/******************************************************************************* +* Function Name: Cy_WDT_ClearWatchdog +****************************************************************************//** +* +* Clears ("feeds") the watchdog, do prevents a XRES device reset. +* +*******************************************************************************/ +void Cy_WDT_ClearWatchdog(void) +{ + Cy_WDT_ClearInterrupt(); +} + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/wdt/cy_wdt.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/wdt/cy_wdt.h new file mode 100644 index 0000000000..67783ebd6b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/wdt/cy_wdt.h @@ -0,0 +1,261 @@ +/***************************************************************************//** +* \file cy_wdt.h +* \version 1.0 +* +* This file provides constants and parameter values for the WDT driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* +*******************************************************************************/ + +/** +* \defgroup group_wdt Watchdog Timer (WDT) +* \{ +* +* The Watchdog Timer is a 16-bit free-running up-counter that can issue +* interrupts and device reset if its interrupts are not handled. +* Use the Watchdog Timer for two main purposes.
+* The First use case is recovering from a CPU or firmware failure. +* A timeout period is set up in the watchdog timer, and if a timeout occurs, the +* device is reset (WRES).
+* The Second use case is to generate periodic interrupts. +* +* A "reset cause" register exists, and the firmware should check this register +* at startup. An appropriate action can be taken if a WRES reset is detected. +* +* The user's firmware periodically resets the timeout period (clears or "feeds" +* the watchdog) before a timeout occurs. If the firmware fails to do so, that is +* considered to be a CPU crash or a firmware failure, and the reason for a +* device reset. +* The WDT can generate an interrupt instead of a device reset. The Interrupt +* Service Routine (ISR) can handle the interrupt either as a periodic interrupt, +* or as an early indication of a firmware failure and respond accordingly. +* +* Functional Description
+* The WDT generates an interrupt when the count value in the counter equals the +* configured match value. +* +* It is important that the counter is not reset on a match. When the counter +* reaches a match value, it generates an interrupt and then keeps counting up +* till it overflows and rolls back to zero and reaches the match value again, at +* which point another interrupt is generated. +* +* To use a WDT to generate a periodic interrupt, the match value should be +* incremented in the ISR. As a result, the next WDT interrupt is generated when +* the counter reaches a new match value. +* +* You can also reduce the entire WDT counter period by +* specifying the number of most significant bits that are cut-off in the WDT +* counter. For example, if the Cy_WDT_SetIgnoreBits() function is called with +* parameter 3, the WDT counter becomes a 13-bit free-running up-counter. +* +* Power Modes
+* WDT can operate in all possible low power modes. +* Operation during Hibernate mode is possible because the logic and +* high-voltage internal low oscillator (ILO) are supplied by the external +* high-voltage supply (Vddd). The WDT can be configured to wake the device from +* Hibernate mode. +* +* In Active or LPActive mode, an interrupt request from the WDT is sent to the +* CPU via IRQ 22. In Sleep, LPSleep or Deep Sleep power mode, the CPU subsystem +* is powered down, so the interrupt request from the WDT is sent directly to the +* WakeUp Interrupt Controller (WIC), which will then wake up the CPU. The +* CPU then acknowledges the interrupt request and executes the ISR. +* +* After waking from Deep Sleep, an internal timer value is set to zero until the +* ILO loads the register with the correct value. This can cause an increase in +* low-power mode current consumption. The work around is to wait for the first +* negative edge of the ILO clock before allowing the WDT_CNT register to be read +* by the Cy_WDT_GetCount() function. +* +* Clock Source
+* The WDT is clocked by the 32 kHz ILO. The WDT reset must be disabled +* before disabling the ILO. Otherwise, any register write to disable the ILO is +* ignored. Enabling the WDT reset automatically enables the ILO. +* According to the device datasheet, the ILO accuracy is +/-30% over voltage +* and temperature. This means that the timeout period may vary by 30% from the +* configured value. Appropriate margins should be added while configuring WDT +* intervals to make sure that unwanted device resets do not occur on some +* devices. +* +* Refer to the device datasheet for more information on the oscillator accuracy. +* +* Register Locking
+* You can prevent accidental corruption of the WDT configuration by calling +* the Cy_WDT_Lock() function. When the WDT is locked, any writing to the WDT_*, +* CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers is +* ignored. +* Call the Cy_WDT_Unlock() function to allow WDT registers modification. +* +* Clearing WDT
+* The ILO clock is asynchronous to the SysClk. As a result it generally +* takes three ILO cycles for WDT register changes to come into effect. It is +* important to remember that a WDT should be cleared at least four cycles +* (3 + 1 for sure) before a timeout occurs, especially when small +* match values / low-toggle bit numbers are used. +* +* \warning There is a risk of situations when WDT reset can be generated +* faster than device start-up. Be aware of such situations by calculating the +* start-up time and WDT reset time. The WDT reset time should be always smaller +* than device start-up time. +* +* Reset Detection
+* Use the Cy_SysLib_GetResetReason() function to detect whether the WDT has +* triggered a device reset. +* +* Interrupt Configuration
+* The Global Signal Reference and Interrupt components can be used for ISR +* configuration. If the WDT is configured to generate an interrupt, the pending +* interrupts must be cleared within the ISR (otherwise, the interrupt will be +* generated continuously). +* A pending interrupt to the WDT block must be cleared by the call to the +* Cy_WDT_ClearInterrupt() function. The call to the function will clear the +* unhandled WDT interrupt counter. +* +* Use the WDT ISR as a timer to trigger certain actions +* and to change a next WDT match value. +* +* Ensure that the interrupts from the WDT are passed to the CPU to avoid +* unregistered interrupts. Unregistered WDT interrupts result in continuous +* device reset. To avoid a continuous device reset, call +* Cy_WDT_UnmaskInterrupt(). After that, call the WDT API functions for interrupt +* handling/clearing. +* +* \section group_wdt_configuration Configuration Considerations +* +* To start the WDT, make sure that ILO is enabled. +* After the ILO is enabled, ensure that the WDT is unlocked and disabled by calling +* the Cy_WDT_Unlock() and Cy_WDT_Disable() functions. Set the WDT match value by +* calling Cy_WDT_SetMatch() with the required match value. If needed, set the +* ignore bits for reducing the WDT counter period by calling Cy_WDT_SetIgnoreBits() +* function. After the WDT configuration is set, call Cy_WDT_Enable(). +* +* \note Enable a WDT if the power supply can produce +* sudden brownout events that may compromise the CPU functionality. This +* ensures that the system can recover after a brownout. +* +* When the WDT is used to protect against system crashes, the +* WDT interrupt should be cleared by a portion of the code that is not directly +* associated with the WDT interrupt. +* Otherwise, it is possible that the main firmware loop has crashed or is in an +* endless loop, but the WDT interrupt vector continues to operate and service +* the WDT. The user should: +* * Feed the watchdog by clearing the interrupt bit regularly in the main body +* of the firmware code. +* +* * Guarantee that the interrupt is cleared at least once every WDT period. +* +* * Use the WDT ISR only as a timer to trigger certain actions and to change the +* next match value. +* +* \section group_wdt_section_more_information More Information +* +* For more information on the WDT peripheral, refer to the technical reference +* manual (TRM). +* +* \section group_wdt_MISRA MISRA-C Compliance +* The WDT driver does not have any specific deviations. +* +* \section group_wdt_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_wdt_macro Macro +* \defgroup group_wdt_functions Functions +* +*/ + +#if !defined(_WDT_H_) +#define _WDT_H_ + +#include +#include +#include "cy_device_headers.h" + + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* +* Function Prototypes +*******************************************************************************/ + +/** +* \addtogroup group_wdt_functions +* @{ +*/ + /* WDT API */ + void Cy_WDT_Init(void); + void Cy_WDT_Enable(void); + void Cy_WDT_Disable(void); + void Cy_WDT_Lock(void); + void Cy_WDT_Unlock(void); + void Cy_WDT_SetMatch(uint32_t match); + uint32_t Cy_WDT_GetMatch(void); + uint32_t Cy_WDT_GetCount(void); + void Cy_WDT_SetIgnoreBits(uint32_t bitsNum); + uint32_t Cy_WDT_GetIgnoreBits(void); + void Cy_WDT_ClearInterrupt(void); + void Cy_WDT_MaskInterrupt(void); + void Cy_WDT_UnmaskInterrupt(void); + void Cy_WDT_ClearWatchdog(void); +/** \} group_wdt_functions */ + + +/******************************************************************************* +* Function Constants +*******************************************************************************/ + +/** +* \addtogroup group_wdt_macro +* \{ +*/ + +/** Driver major version */ +#define CY_WDT_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_WDT_DRV_VERSION_MINOR 0 + +/** Internal define for first iteration of WDT unlocking */ +#define CY_SRSS_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u) + +/** Internal define for second iteration of WDT unlocking */ +#define CY_SRSS_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u) + +/** WDT default match value */ +#define CY_SRSS_WDT_DEFAULT_MATCH_VALUE ((uint32_t) 4096u) + +/** Default match value of WDT ignore bits */ +#define CY_SRSS_WDT_DEFAULT_IGNORE_BITS (0u) + +/** Default match value of WDT ignore bits */ +#define CY_SRSS_WDT_LOCK_BITS (3u) + +/** WDT driver identifier */ +#define CY_WDT_ID CY_PDL_DRV_ID(0x34u) + +/** \} group_wdt_macro */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _WDT_H_ */ + +/** \} group_wdt */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_backup.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_backup.h new file mode 100644 index 0000000000..0295b344ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_backup.h @@ -0,0 +1,221 @@ +/***************************************************************************//** +* \file cyip_backup.h +* +* \brief +* BACKUP IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_BACKUP_H_ +#define _CYIP_BACKUP_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ BACKUP ================ */ +/* =========================================================================================================================== */ + +#define BACKUP_SECTION_SIZE 0x00010000UL + +/** + * \brief SRSS Backup Domain (BACKUP) + */ +typedef struct { /*!< BACKUP Structure */ + __IOM uint32_t CTL; /*!< 0x00000000 Control */ + __IM uint32_t RESERVED; + __IOM uint32_t RTC_RW; /*!< 0x00000008 RTC Read Write register */ + __IOM uint32_t CAL_CTL; /*!< 0x0000000C Oscillator calibration for absolute frequency */ + __IM uint32_t STATUS; /*!< 0x00000010 Status */ + __IOM uint32_t RTC_TIME; /*!< 0x00000014 Calendar Seconds, Minutes, Hours, Day of Week */ + __IOM uint32_t RTC_DATE; /*!< 0x00000018 Calendar Day of Month, Month, Year */ + __IOM uint32_t ALM1_TIME; /*!< 0x0000001C Alarm 1 Seconds, Minute, Hours, Day of Week */ + __IOM uint32_t ALM1_DATE; /*!< 0x00000020 Alarm 1 Day of Month, Month */ + __IOM uint32_t ALM2_TIME; /*!< 0x00000024 Alarm 2 Seconds, Minute, Hours, Day of Week */ + __IOM uint32_t ALM2_DATE; /*!< 0x00000028 Alarm 2 Day of Month, Month */ + __IOM uint32_t INTR; /*!< 0x0000002C Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000030 Interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000034 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x00000038 Interrupt masked request register */ + __IM uint32_t OSCCNT; /*!< 0x0000003C 32kHz oscillator counter */ + __IM uint32_t TICKS; /*!< 0x00000040 128Hz tick counter */ + __IOM uint32_t PMIC_CTL; /*!< 0x00000044 PMIC control register */ + __IM uint32_t RESERVED1[1006]; + __IOM uint32_t BREG[8]; /*!< 0x00001000 Backup register region */ + __IM uint32_t RESERVED2[15288]; + __IOM uint32_t TRIM; /*!< 0x0000FF00 Trim Register */ +} BACKUP_Type; /*!< Size = 65284 (0xFF04) */ + + +/* ====================================================== BACKUP.CTL ======================================================= */ +#define BACKUP_CTL_WCO_EN_Pos (3UL) /*!< BACKUP CTL: WCO_EN (Bit 3) */ +#define BACKUP_CTL_WCO_EN_Msk (0x8UL) /*!< BACKUP CTL: WCO_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_CTL_CLK_SEL_Pos (8UL) /*!< BACKUP CTL: CLK_SEL (Bit 8) */ +#define BACKUP_CTL_CLK_SEL_Msk (0x300UL) /*!< BACKUP CTL: CLK_SEL (Bitfield-Mask: 0x03) */ +#define BACKUP_CTL_PRESCALER_Pos (12UL) /*!< BACKUP CTL: PRESCALER (Bit 12) */ +#define BACKUP_CTL_PRESCALER_Msk (0x3000UL) /*!< BACKUP CTL: PRESCALER (Bitfield-Mask: 0x03) */ +#define BACKUP_CTL_WCO_BYPASS_Pos (16UL) /*!< BACKUP CTL: WCO_BYPASS (Bit 16) */ +#define BACKUP_CTL_WCO_BYPASS_Msk (0x10000UL) /*!< BACKUP CTL: WCO_BYPASS (Bitfield-Mask: 0x01) */ +#define BACKUP_CTL_VDDBAK_CTL_Pos (17UL) /*!< BACKUP CTL: VDDBAK_CTL (Bit 17) */ +#define BACKUP_CTL_VDDBAK_CTL_Msk (0x60000UL) /*!< BACKUP CTL: VDDBAK_CTL (Bitfield-Mask: 0x03) */ +#define BACKUP_CTL_VBACKUP_MEAS_Pos (19UL) /*!< BACKUP CTL: VBACKUP_MEAS (Bit 19) */ +#define BACKUP_CTL_VBACKUP_MEAS_Msk (0x80000UL) /*!< BACKUP CTL: VBACKUP_MEAS (Bitfield-Mask: 0x01) */ +#define BACKUP_CTL_EN_CHARGE_KEY_Pos (24UL) /*!< BACKUP CTL: EN_CHARGE_KEY (Bit 24) */ +#define BACKUP_CTL_EN_CHARGE_KEY_Msk (0xff000000UL) /*!< BACKUP CTL: EN_CHARGE_KEY (Bitfield-Mask: 0xff) */ +/* ===================================================== BACKUP.RTC_RW ===================================================== */ +#define BACKUP_RTC_RW_READ_Pos (0UL) /*!< BACKUP RTC_RW: READ (Bit 0) */ +#define BACKUP_RTC_RW_READ_Msk (0x1UL) /*!< BACKUP RTC_RW: READ (Bitfield-Mask: 0x01) */ +#define BACKUP_RTC_RW_WRITE_Pos (1UL) /*!< BACKUP RTC_RW: WRITE (Bit 1) */ +#define BACKUP_RTC_RW_WRITE_Msk (0x2UL) /*!< BACKUP RTC_RW: WRITE (Bitfield-Mask: 0x01) */ +/* ==================================================== BACKUP.CAL_CTL ===================================================== */ +#define BACKUP_CAL_CTL_CALIB_VAL_Pos (0UL) /*!< BACKUP CAL_CTL: CALIB_VAL (Bit 0) */ +#define BACKUP_CAL_CTL_CALIB_VAL_Msk (0x3fUL) /*!< BACKUP CAL_CTL: CALIB_VAL (Bitfield-Mask: 0x3f) */ +#define BACKUP_CAL_CTL_CALIB_SIGN_Pos (6UL) /*!< BACKUP CAL_CTL: CALIB_SIGN (Bit 6) */ +#define BACKUP_CAL_CTL_CALIB_SIGN_Msk (0x40UL) /*!< BACKUP CAL_CTL: CALIB_SIGN (Bitfield-Mask: 0x01) */ +#define BACKUP_CAL_CTL_CAL_OUT_Pos (31UL) /*!< BACKUP CAL_CTL: CAL_OUT (Bit 31) */ +#define BACKUP_CAL_CTL_CAL_OUT_Msk (0x80000000UL) /*!< BACKUP CAL_CTL: CAL_OUT (Bitfield-Mask: 0x01) */ +/* ===================================================== BACKUP.STATUS ===================================================== */ +#define BACKUP_STATUS_RTC_BUSY_Pos (0UL) /*!< BACKUP STATUS: RTC_BUSY (Bit 0) */ +#define BACKUP_STATUS_RTC_BUSY_Msk (0x1UL) /*!< BACKUP STATUS: RTC_BUSY (Bitfield-Mask: 0x01) */ +#define BACKUP_STATUS_WCO_OK_Pos (2UL) /*!< BACKUP STATUS: WCO_OK (Bit 2) */ +#define BACKUP_STATUS_WCO_OK_Msk (0x4UL) /*!< BACKUP STATUS: WCO_OK (Bitfield-Mask: 0x01) */ +/* ==================================================== BACKUP.RTC_TIME ==================================================== */ +#define BACKUP_RTC_TIME_RTC_SEC_Pos (0UL) /*!< BACKUP RTC_TIME: RTC_SEC (Bit 0) */ +#define BACKUP_RTC_TIME_RTC_SEC_Msk (0x7fUL) /*!< BACKUP RTC_TIME: RTC_SEC (Bitfield-Mask: 0x7f) */ +#define BACKUP_RTC_TIME_RTC_MIN_Pos (8UL) /*!< BACKUP RTC_TIME: RTC_MIN (Bit 8) */ +#define BACKUP_RTC_TIME_RTC_MIN_Msk (0x7f00UL) /*!< BACKUP RTC_TIME: RTC_MIN (Bitfield-Mask: 0x7f) */ +#define BACKUP_RTC_TIME_RTC_HOUR_Pos (16UL) /*!< BACKUP RTC_TIME: RTC_HOUR (Bit 16) */ +#define BACKUP_RTC_TIME_RTC_HOUR_Msk (0x3f0000UL) /*!< BACKUP RTC_TIME: RTC_HOUR (Bitfield-Mask: 0x3f) */ +#define BACKUP_RTC_TIME_CTRL_12HR_Pos (22UL) /*!< BACKUP RTC_TIME: CTRL_12HR (Bit 22) */ +#define BACKUP_RTC_TIME_CTRL_12HR_Msk (0x400000UL) /*!< BACKUP RTC_TIME: CTRL_12HR (Bitfield-Mask: 0x01) */ +#define BACKUP_RTC_TIME_RTC_DAY_Pos (24UL) /*!< BACKUP RTC_TIME: RTC_DAY (Bit 24) */ +#define BACKUP_RTC_TIME_RTC_DAY_Msk (0x7000000UL) /*!< BACKUP RTC_TIME: RTC_DAY (Bitfield-Mask: 0x07) */ +/* ==================================================== BACKUP.RTC_DATE ==================================================== */ +#define BACKUP_RTC_DATE_RTC_DATE_Pos (0UL) /*!< BACKUP RTC_DATE: RTC_DATE (Bit 0) */ +#define BACKUP_RTC_DATE_RTC_DATE_Msk (0x3fUL) /*!< BACKUP RTC_DATE: RTC_DATE (Bitfield-Mask: 0x3f) */ +#define BACKUP_RTC_DATE_RTC_MON_Pos (8UL) /*!< BACKUP RTC_DATE: RTC_MON (Bit 8) */ +#define BACKUP_RTC_DATE_RTC_MON_Msk (0x1f00UL) /*!< BACKUP RTC_DATE: RTC_MON (Bitfield-Mask: 0x1f) */ +#define BACKUP_RTC_DATE_RTC_YEAR_Pos (16UL) /*!< BACKUP RTC_DATE: RTC_YEAR (Bit 16) */ +#define BACKUP_RTC_DATE_RTC_YEAR_Msk (0xff0000UL) /*!< BACKUP RTC_DATE: RTC_YEAR (Bitfield-Mask: 0xff) */ +/* =================================================== BACKUP.ALM1_TIME ==================================================== */ +#define BACKUP_ALM1_TIME_ALM_SEC_Pos (0UL) /*!< BACKUP ALM1_TIME: ALM_SEC (Bit 0) */ +#define BACKUP_ALM1_TIME_ALM_SEC_Msk (0x7fUL) /*!< BACKUP ALM1_TIME: ALM_SEC (Bitfield-Mask: 0x7f) */ +#define BACKUP_ALM1_TIME_ALM_SEC_EN_Pos (7UL) /*!< BACKUP ALM1_TIME: ALM_SEC_EN (Bit 7) */ +#define BACKUP_ALM1_TIME_ALM_SEC_EN_Msk (0x80UL) /*!< BACKUP ALM1_TIME: ALM_SEC_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_ALM1_TIME_ALM_MIN_Pos (8UL) /*!< BACKUP ALM1_TIME: ALM_MIN (Bit 8) */ +#define BACKUP_ALM1_TIME_ALM_MIN_Msk (0x7f00UL) /*!< BACKUP ALM1_TIME: ALM_MIN (Bitfield-Mask: 0x7f) */ +#define BACKUP_ALM1_TIME_ALM_MIN_EN_Pos (15UL) /*!< BACKUP ALM1_TIME: ALM_MIN_EN (Bit 15) */ +#define BACKUP_ALM1_TIME_ALM_MIN_EN_Msk (0x8000UL) /*!< BACKUP ALM1_TIME: ALM_MIN_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_ALM1_TIME_ALM_HOUR_Pos (16UL) /*!< BACKUP ALM1_TIME: ALM_HOUR (Bit 16) */ +#define BACKUP_ALM1_TIME_ALM_HOUR_Msk (0x3f0000UL) /*!< BACKUP ALM1_TIME: ALM_HOUR (Bitfield-Mask: 0x3f) */ +#define BACKUP_ALM1_TIME_ALM_HOUR_EN_Pos (23UL) /*!< BACKUP ALM1_TIME: ALM_HOUR_EN (Bit 23) */ +#define BACKUP_ALM1_TIME_ALM_HOUR_EN_Msk (0x800000UL) /*!< BACKUP ALM1_TIME: ALM_HOUR_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_ALM1_TIME_ALM_DAY_Pos (24UL) /*!< BACKUP ALM1_TIME: ALM_DAY (Bit 24) */ +#define BACKUP_ALM1_TIME_ALM_DAY_Msk (0x7000000UL) /*!< BACKUP ALM1_TIME: ALM_DAY (Bitfield-Mask: 0x07) */ +#define BACKUP_ALM1_TIME_ALM_DAY_EN_Pos (31UL) /*!< BACKUP ALM1_TIME: ALM_DAY_EN (Bit 31) */ +#define BACKUP_ALM1_TIME_ALM_DAY_EN_Msk (0x80000000UL) /*!< BACKUP ALM1_TIME: ALM_DAY_EN (Bitfield-Mask: 0x01) */ +/* =================================================== BACKUP.ALM1_DATE ==================================================== */ +#define BACKUP_ALM1_DATE_ALM_DATE_Pos (0UL) /*!< BACKUP ALM1_DATE: ALM_DATE (Bit 0) */ +#define BACKUP_ALM1_DATE_ALM_DATE_Msk (0x3fUL) /*!< BACKUP ALM1_DATE: ALM_DATE (Bitfield-Mask: 0x3f) */ +#define BACKUP_ALM1_DATE_ALM_DATE_EN_Pos (7UL) /*!< BACKUP ALM1_DATE: ALM_DATE_EN (Bit 7) */ +#define BACKUP_ALM1_DATE_ALM_DATE_EN_Msk (0x80UL) /*!< BACKUP ALM1_DATE: ALM_DATE_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_ALM1_DATE_ALM_MON_Pos (8UL) /*!< BACKUP ALM1_DATE: ALM_MON (Bit 8) */ +#define BACKUP_ALM1_DATE_ALM_MON_Msk (0x1f00UL) /*!< BACKUP ALM1_DATE: ALM_MON (Bitfield-Mask: 0x1f) */ +#define BACKUP_ALM1_DATE_ALM_MON_EN_Pos (15UL) /*!< BACKUP ALM1_DATE: ALM_MON_EN (Bit 15) */ +#define BACKUP_ALM1_DATE_ALM_MON_EN_Msk (0x8000UL) /*!< BACKUP ALM1_DATE: ALM_MON_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_ALM1_DATE_ALM_EN_Pos (31UL) /*!< BACKUP ALM1_DATE: ALM_EN (Bit 31) */ +#define BACKUP_ALM1_DATE_ALM_EN_Msk (0x80000000UL) /*!< BACKUP ALM1_DATE: ALM_EN (Bitfield-Mask: 0x01) */ +/* =================================================== BACKUP.ALM2_TIME ==================================================== */ +#define BACKUP_ALM2_TIME_ALM_SEC_Pos (0UL) /*!< BACKUP ALM2_TIME: ALM_SEC (Bit 0) */ +#define BACKUP_ALM2_TIME_ALM_SEC_Msk (0x7fUL) /*!< BACKUP ALM2_TIME: ALM_SEC (Bitfield-Mask: 0x7f) */ +#define BACKUP_ALM2_TIME_ALM_SEC_EN_Pos (7UL) /*!< BACKUP ALM2_TIME: ALM_SEC_EN (Bit 7) */ +#define BACKUP_ALM2_TIME_ALM_SEC_EN_Msk (0x80UL) /*!< BACKUP ALM2_TIME: ALM_SEC_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_ALM2_TIME_ALM_MIN_Pos (8UL) /*!< BACKUP ALM2_TIME: ALM_MIN (Bit 8) */ +#define BACKUP_ALM2_TIME_ALM_MIN_Msk (0x7f00UL) /*!< BACKUP ALM2_TIME: ALM_MIN (Bitfield-Mask: 0x7f) */ +#define BACKUP_ALM2_TIME_ALM_MIN_EN_Pos (15UL) /*!< BACKUP ALM2_TIME: ALM_MIN_EN (Bit 15) */ +#define BACKUP_ALM2_TIME_ALM_MIN_EN_Msk (0x8000UL) /*!< BACKUP ALM2_TIME: ALM_MIN_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_ALM2_TIME_ALM_HOUR_Pos (16UL) /*!< BACKUP ALM2_TIME: ALM_HOUR (Bit 16) */ +#define BACKUP_ALM2_TIME_ALM_HOUR_Msk (0x3f0000UL) /*!< BACKUP ALM2_TIME: ALM_HOUR (Bitfield-Mask: 0x3f) */ +#define BACKUP_ALM2_TIME_ALM_HOUR_EN_Pos (23UL) /*!< BACKUP ALM2_TIME: ALM_HOUR_EN (Bit 23) */ +#define BACKUP_ALM2_TIME_ALM_HOUR_EN_Msk (0x800000UL) /*!< BACKUP ALM2_TIME: ALM_HOUR_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_ALM2_TIME_ALM_DAY_Pos (24UL) /*!< BACKUP ALM2_TIME: ALM_DAY (Bit 24) */ +#define BACKUP_ALM2_TIME_ALM_DAY_Msk (0x7000000UL) /*!< BACKUP ALM2_TIME: ALM_DAY (Bitfield-Mask: 0x07) */ +#define BACKUP_ALM2_TIME_ALM_DAY_EN_Pos (31UL) /*!< BACKUP ALM2_TIME: ALM_DAY_EN (Bit 31) */ +#define BACKUP_ALM2_TIME_ALM_DAY_EN_Msk (0x80000000UL) /*!< BACKUP ALM2_TIME: ALM_DAY_EN (Bitfield-Mask: 0x01) */ +/* =================================================== BACKUP.ALM2_DATE ==================================================== */ +#define BACKUP_ALM2_DATE_ALM_DATE_Pos (0UL) /*!< BACKUP ALM2_DATE: ALM_DATE (Bit 0) */ +#define BACKUP_ALM2_DATE_ALM_DATE_Msk (0x3fUL) /*!< BACKUP ALM2_DATE: ALM_DATE (Bitfield-Mask: 0x3f) */ +#define BACKUP_ALM2_DATE_ALM_DATE_EN_Pos (7UL) /*!< BACKUP ALM2_DATE: ALM_DATE_EN (Bit 7) */ +#define BACKUP_ALM2_DATE_ALM_DATE_EN_Msk (0x80UL) /*!< BACKUP ALM2_DATE: ALM_DATE_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_ALM2_DATE_ALM_MON_Pos (8UL) /*!< BACKUP ALM2_DATE: ALM_MON (Bit 8) */ +#define BACKUP_ALM2_DATE_ALM_MON_Msk (0x1f00UL) /*!< BACKUP ALM2_DATE: ALM_MON (Bitfield-Mask: 0x1f) */ +#define BACKUP_ALM2_DATE_ALM_MON_EN_Pos (15UL) /*!< BACKUP ALM2_DATE: ALM_MON_EN (Bit 15) */ +#define BACKUP_ALM2_DATE_ALM_MON_EN_Msk (0x8000UL) /*!< BACKUP ALM2_DATE: ALM_MON_EN (Bitfield-Mask: 0x01) */ +#define BACKUP_ALM2_DATE_ALM_EN_Pos (31UL) /*!< BACKUP ALM2_DATE: ALM_EN (Bit 31) */ +#define BACKUP_ALM2_DATE_ALM_EN_Msk (0x80000000UL) /*!< BACKUP ALM2_DATE: ALM_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== BACKUP.INTR ====================================================== */ +#define BACKUP_INTR_ALARM1_Pos (0UL) /*!< BACKUP INTR: ALARM1 (Bit 0) */ +#define BACKUP_INTR_ALARM1_Msk (0x1UL) /*!< BACKUP INTR: ALARM1 (Bitfield-Mask: 0x01) */ +#define BACKUP_INTR_ALARM2_Pos (1UL) /*!< BACKUP INTR: ALARM2 (Bit 1) */ +#define BACKUP_INTR_ALARM2_Msk (0x2UL) /*!< BACKUP INTR: ALARM2 (Bitfield-Mask: 0x01) */ +#define BACKUP_INTR_CENTURY_Pos (2UL) /*!< BACKUP INTR: CENTURY (Bit 2) */ +#define BACKUP_INTR_CENTURY_Msk (0x4UL) /*!< BACKUP INTR: CENTURY (Bitfield-Mask: 0x01) */ +/* ==================================================== BACKUP.INTR_SET ==================================================== */ +#define BACKUP_INTR_SET_ALARM1_Pos (0UL) /*!< BACKUP INTR_SET: ALARM1 (Bit 0) */ +#define BACKUP_INTR_SET_ALARM1_Msk (0x1UL) /*!< BACKUP INTR_SET: ALARM1 (Bitfield-Mask: 0x01) */ +#define BACKUP_INTR_SET_ALARM2_Pos (1UL) /*!< BACKUP INTR_SET: ALARM2 (Bit 1) */ +#define BACKUP_INTR_SET_ALARM2_Msk (0x2UL) /*!< BACKUP INTR_SET: ALARM2 (Bitfield-Mask: 0x01) */ +#define BACKUP_INTR_SET_CENTURY_Pos (2UL) /*!< BACKUP INTR_SET: CENTURY (Bit 2) */ +#define BACKUP_INTR_SET_CENTURY_Msk (0x4UL) /*!< BACKUP INTR_SET: CENTURY (Bitfield-Mask: 0x01) */ +/* =================================================== BACKUP.INTR_MASK ==================================================== */ +#define BACKUP_INTR_MASK_ALARM1_Pos (0UL) /*!< BACKUP INTR_MASK: ALARM1 (Bit 0) */ +#define BACKUP_INTR_MASK_ALARM1_Msk (0x1UL) /*!< BACKUP INTR_MASK: ALARM1 (Bitfield-Mask: 0x01) */ +#define BACKUP_INTR_MASK_ALARM2_Pos (1UL) /*!< BACKUP INTR_MASK: ALARM2 (Bit 1) */ +#define BACKUP_INTR_MASK_ALARM2_Msk (0x2UL) /*!< BACKUP INTR_MASK: ALARM2 (Bitfield-Mask: 0x01) */ +#define BACKUP_INTR_MASK_CENTURY_Pos (2UL) /*!< BACKUP INTR_MASK: CENTURY (Bit 2) */ +#define BACKUP_INTR_MASK_CENTURY_Msk (0x4UL) /*!< BACKUP INTR_MASK: CENTURY (Bitfield-Mask: 0x01) */ +/* ================================================== BACKUP.INTR_MASKED =================================================== */ +#define BACKUP_INTR_MASKED_ALARM1_Pos (0UL) /*!< BACKUP INTR_MASKED: ALARM1 (Bit 0) */ +#define BACKUP_INTR_MASKED_ALARM1_Msk (0x1UL) /*!< BACKUP INTR_MASKED: ALARM1 (Bitfield-Mask: 0x01) */ +#define BACKUP_INTR_MASKED_ALARM2_Pos (1UL) /*!< BACKUP INTR_MASKED: ALARM2 (Bit 1) */ +#define BACKUP_INTR_MASKED_ALARM2_Msk (0x2UL) /*!< BACKUP INTR_MASKED: ALARM2 (Bitfield-Mask: 0x01) */ +#define BACKUP_INTR_MASKED_CENTURY_Pos (2UL) /*!< BACKUP INTR_MASKED: CENTURY (Bit 2) */ +#define BACKUP_INTR_MASKED_CENTURY_Msk (0x4UL) /*!< BACKUP INTR_MASKED: CENTURY (Bitfield-Mask: 0x01) */ +/* ===================================================== BACKUP.OSCCNT ===================================================== */ +#define BACKUP_OSCCNT_CNT32KHZ_Pos (0UL) /*!< BACKUP OSCCNT: CNT32KHZ (Bit 0) */ +#define BACKUP_OSCCNT_CNT32KHZ_Msk (0xffUL) /*!< BACKUP OSCCNT: CNT32KHZ (Bitfield-Mask: 0xff) */ +/* ===================================================== BACKUP.TICKS ====================================================== */ +#define BACKUP_TICKS_CNT128HZ_Pos (0UL) /*!< BACKUP TICKS: CNT128HZ (Bit 0) */ +#define BACKUP_TICKS_CNT128HZ_Msk (0x3fUL) /*!< BACKUP TICKS: CNT128HZ (Bitfield-Mask: 0x3f) */ +/* ==================================================== BACKUP.PMIC_CTL ==================================================== */ +#define BACKUP_PMIC_CTL_UNLOCK_Pos (8UL) /*!< BACKUP PMIC_CTL: UNLOCK (Bit 8) */ +#define BACKUP_PMIC_CTL_UNLOCK_Msk (0xff00UL) /*!< BACKUP PMIC_CTL: UNLOCK (Bitfield-Mask: 0xff) */ +#define BACKUP_PMIC_CTL_POLARITY_Pos (16UL) /*!< BACKUP PMIC_CTL: POLARITY (Bit 16) */ +#define BACKUP_PMIC_CTL_POLARITY_Msk (0x10000UL) /*!< BACKUP PMIC_CTL: POLARITY (Bitfield-Mask: 0x01) */ +#define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Pos (29UL) /*!< BACKUP PMIC_CTL: PMIC_EN_OUTEN (Bit 29) */ +#define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Msk (0x20000000UL) /*!< BACKUP PMIC_CTL: PMIC_EN_OUTEN (Bitfield-Mask: 0x01) */ +#define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Pos (30UL) /*!< BACKUP PMIC_CTL: PMIC_ALWAYSEN (Bit 30) */ +#define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Msk (0x40000000UL) /*!< BACKUP PMIC_CTL: PMIC_ALWAYSEN (Bitfield-Mask: 0x01) */ +#define BACKUP_PMIC_CTL_PMIC_EN_Pos (31UL) /*!< BACKUP PMIC_CTL: PMIC_EN (Bit 31) */ +#define BACKUP_PMIC_CTL_PMIC_EN_Msk (0x80000000UL) /*!< BACKUP PMIC_CTL: PMIC_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== BACKUP.BREG ====================================================== */ +#define BACKUP_BREG_BREG_Pos (0UL) /*!< BACKUP BREG: BREG (Bit 0) */ +#define BACKUP_BREG_BREG_Msk (0xffffffffUL) /*!< BACKUP BREG: BREG (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== BACKUP.TRIM ====================================================== */ +#define BACKUP_TRIM_TRIM_Pos (0UL) /*!< BACKUP TRIM: TRIM (Bit 0) */ +#define BACKUP_TRIM_TRIM_Msk (0x3fUL) /*!< BACKUP TRIM: TRIM (Bitfield-Mask: 0x3f) */ + + +#endif /* _CYIP_BACKUP_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ble.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ble.h new file mode 100644 index 0000000000..05a14b8d7d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ble.h @@ -0,0 +1,2219 @@ +/***************************************************************************//** +* \file cyip_ble.h +* +* \brief +* BLE IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_BLE_H_ +#define _CYIP_BLE_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ BLE ================ */ +/* =========================================================================================================================== */ + +#define BLE_RCB_RCBLL_SECTION_SIZE 0x00000100UL +#define BLE_RCB_SECTION_SIZE 0x00000200UL +#define BLE_BLELL_SECTION_SIZE 0x0001E000UL +#define BLE_BLESS_SECTION_SIZE 0x00001000UL +#define BLE_SECTION_SIZE 0x00020000UL + +/** + * \brief Radio Control Bus (RCB) & Link Layer controller (BLE_RCB_RCBLL) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 RCB LL control register. */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t INTR; /*!< 0x00000010 Master interrupt request register. */ + __IOM uint32_t INTR_SET; /*!< 0x00000014 Master interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000018 Master interrupt mask register. */ + __IM uint32_t INTR_MASKED; /*!< 0x0000001C Master interrupt masked request register */ + __IOM uint32_t RADIO_REG1_ADDR; /*!< 0x00000020 Address of Register#1 in Radio (MDON) */ + __IOM uint32_t RADIO_REG2_ADDR; /*!< 0x00000024 Address of Register#2 in Radio (RSSI) */ + __IOM uint32_t RADIO_REG3_ADDR; /*!< 0x00000028 Address of Register#3 in Radio (ACCL) */ + __IOM uint32_t RADIO_REG4_ADDR; /*!< 0x0000002C Address of Register#4 in Radio (ACCH) */ + __IOM uint32_t RADIO_REG5_ADDR; /*!< 0x00000030 Address of Register#5 in Radio (RSSI ENERGY) */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t CPU_WRITE_REG; /*!< 0x00000040 N/A */ + __IOM uint32_t CPU_READ_REG; /*!< 0x00000044 N/A */ + __IM uint32_t RESERVED2[46]; +} BLE_RCB_RCBLL_Type; /*!< Size = 72 (0x48) */ + +/** + * \brief Radio Control Bus (RCB) controller (BLE_RCB) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 RCB control register. */ + __IM uint32_t STATUS; /*!< 0x00000004 RCB status register. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t TX_CTRL; /*!< 0x00000010 Transmitter control register. */ + __IOM uint32_t TX_FIFO_CTRL; /*!< 0x00000014 Transmitter FIFO control register. */ + __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000018 Transmitter FIFO status register. */ + __OM uint32_t TX_FIFO_WR; /*!< 0x0000001C Transmitter FIFO write register. */ + __IOM uint32_t RX_CTRL; /*!< 0x00000020 Receiver control register. */ + __IOM uint32_t RX_FIFO_CTRL; /*!< 0x00000024 Receiver FIFO control register. */ + __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000028 Receiver FIFO status register. */ + __IM uint32_t RX_FIFO_RD; /*!< 0x0000002C Receiver FIFO read register. */ + __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x00000030 Receiver FIFO read register. */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t INTR; /*!< 0x00000040 Master interrupt request register. */ + __IOM uint32_t INTR_SET; /*!< 0x00000044 Master interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000048 Master interrupt mask register. */ + __IM uint32_t INTR_MASKED; /*!< 0x0000004C Master interrupt masked request register */ + __IM uint32_t RESERVED2[44]; + BLE_RCB_RCBLL_Type RCBLL; /*!< 0x00000100 Radio Control Bus (RCB) & Link Layer controller */ +} BLE_RCB_Type; /*!< Size = 512 (0x200) */ + +/** + * \brief Bluetooth Low Energy Link Layer (BLE_BLELL) + */ +typedef struct { + __OM uint32_t COMMAND_REGISTER; /*!< 0x00000000 Instruction Register */ + __IM uint32_t RESERVED; + __IOM uint32_t EVENT_INTR; /*!< 0x00000008 Event(Interrupt) status and Clear register */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENT_ENABLE; /*!< 0x00000010 Event indications enable. */ + __IM uint32_t RESERVED2; + __IOM uint32_t ADV_PARAMS; /*!< 0x00000018 Advertising parameters register. */ + __IOM uint32_t ADV_INTERVAL_TIMEOUT; /*!< 0x0000001C Advertising interval register. */ + __IOM uint32_t ADV_INTR; /*!< 0x00000020 Advertising interrupt status and Clear register */ + __IM uint32_t ADV_NEXT_INSTANT; /*!< 0x00000024 Advertising next instant. */ + __IOM uint32_t SCAN_INTERVAL; /*!< 0x00000028 Scan Interval Register */ + __IOM uint32_t SCAN_WINDOW; /*!< 0x0000002C Scan window Register */ + __IOM uint32_t SCAN_PARAM; /*!< 0x00000030 Scanning parameters register */ + __IM uint32_t RESERVED3; + __IOM uint32_t SCAN_INTR; /*!< 0x00000038 Scan interrupt status and Clear register */ + __IM uint32_t SCAN_NEXT_INSTANT; /*!< 0x0000003C Advertising next instant. */ + __IOM uint32_t INIT_INTERVAL; /*!< 0x00000040 Initiator Interval Register */ + __IOM uint32_t INIT_WINDOW; /*!< 0x00000044 Initiator window Register */ + __IOM uint32_t INIT_PARAM; /*!< 0x00000048 Initiator parameters register */ + __IM uint32_t RESERVED4; + __IOM uint32_t INIT_INTR; /*!< 0x00000050 Scan interrupt status and Clear register */ + __IM uint32_t INIT_NEXT_INSTANT; /*!< 0x00000054 Initiator next instant. */ + __IOM uint32_t DEVICE_RAND_ADDR_L; /*!< 0x00000058 Lower 16 bit random address of the device. */ + __IOM uint32_t DEVICE_RAND_ADDR_M; /*!< 0x0000005C Middle 16 bit random address of the device. */ + __IOM uint32_t DEVICE_RAND_ADDR_H; /*!< 0x00000060 Higher 16 bit random address of the device. */ + __IM uint32_t RESERVED5; + __IOM uint32_t PEER_ADDR_L; /*!< 0x00000068 Lower 16 bit address of the peer device. */ + __IOM uint32_t PEER_ADDR_M; /*!< 0x0000006C Middle 16 bit address of the peer device. */ + __IOM uint32_t PEER_ADDR_H; /*!< 0x00000070 Higher 16 bit address of the peer device. */ + __IM uint32_t RESERVED6; + __IOM uint32_t WL_ADDR_TYPE; /*!< 0x00000078 whitelist address type */ + __IOM uint32_t WL_ENABLE; /*!< 0x0000007C whitelist valid entry bit */ + __IOM uint32_t TRANSMIT_WINDOW_OFFSET; /*!< 0x00000080 Transmit window offset */ + __IOM uint32_t TRANSMIT_WINDOW_SIZE; /*!< 0x00000084 Transmit window size */ + __IOM uint32_t DATA_CHANNELS_L0; /*!< 0x00000088 Data channel map 0 (lower word) */ + __IOM uint32_t DATA_CHANNELS_M0; /*!< 0x0000008C Data channel map 0 (middle word) */ + __IOM uint32_t DATA_CHANNELS_H0; /*!< 0x00000090 Data channel map 0 (upper word) */ + __IM uint32_t RESERVED7; + __IOM uint32_t DATA_CHANNELS_L1; /*!< 0x00000098 Data channel map 1 (lower word) */ + __IOM uint32_t DATA_CHANNELS_M1; /*!< 0x0000009C Data channel map 1 (middle word) */ + __IOM uint32_t DATA_CHANNELS_H1; /*!< 0x000000A0 Data channel map 1 (upper word) */ + __IM uint32_t RESERVED8; + __IOM uint32_t CONN_INTR; /*!< 0x000000A8 Connection interrupt status and Clear register */ + __IM uint32_t CONN_STATUS; /*!< 0x000000AC Connection channel status */ + __IOM uint32_t CONN_INDEX; /*!< 0x000000B0 Connection Index register */ + __IM uint32_t RESERVED9; + __IOM uint32_t WAKEUP_CONFIG; /*!< 0x000000B8 Wakeup configuration */ + __IM uint32_t RESERVED10; + __IOM uint32_t WAKEUP_CONTROL; /*!< 0x000000C0 Wakeup control */ + __IOM uint32_t CLOCK_CONFIG; /*!< 0x000000C4 Clock control */ + __IM uint32_t TIM_COUNTER_L; /*!< 0x000000C8 Reference Clock */ + __IOM uint32_t WAKEUP_CONFIG_EXTD; /*!< 0x000000CC Wakeup configuration extended */ + __IM uint32_t RESERVED11[2]; + __IOM uint32_t POC_REG__TIM_CONTROL; /*!< 0x000000D8 BLE Time Control */ + __IM uint32_t RESERVED12; + __IOM uint32_t ADV_TX_DATA_FIFO; /*!< 0x000000E0 Advertising data transmit FIFO. Access ADVCH_TX_FIFO. */ + __IM uint32_t RESERVED13; + __IOM uint32_t ADV_SCN_RSP_TX_FIFO; /*!< 0x000000E8 Advertising scan response data transmit FIFO. Access + ADVCH_TX_FIFO. */ + __IM uint32_t RESERVED14[3]; + __IM uint32_t INIT_SCN_ADV_RX_FIFO; /*!< 0x000000F8 advertising scan response data receive data FIFO. Access + ADVRX_FIFO. */ + __IM uint32_t RESERVED15; + __IOM uint32_t CONN_INTERVAL; /*!< 0x00000100 Connection Interval */ + __IOM uint32_t SUP_TIMEOUT; /*!< 0x00000104 Supervision timeout */ + __IOM uint32_t SLAVE_LATENCY; /*!< 0x00000108 Slave Latency */ + __IOM uint32_t CE_LENGTH; /*!< 0x0000010C Connection event length */ + __IOM uint32_t PDU_ACCESS_ADDR_L_REGISTER; /*!< 0x00000110 Access address (lower) */ + __IOM uint32_t PDU_ACCESS_ADDR_H_REGISTER; /*!< 0x00000114 Access address (upper) */ + __IOM uint32_t CONN_CE_INSTANT; /*!< 0x00000118 Connection event instant */ + __IOM uint32_t CE_CNFG_STS_REGISTER; /*!< 0x0000011C connection configuration & status register */ + __IM uint32_t NEXT_CE_INSTANT; /*!< 0x00000120 Next connection event instant */ + __IM uint32_t CONN_CE_COUNTER; /*!< 0x00000124 connection event counter */ + __IOM uint32_t DATA_LIST_SENT_UPDATE__STATUS; /*!< 0x00000128 data list sent update and status */ + __IOM uint32_t DATA_LIST_ACK_UPDATE__STATUS; /*!< 0x0000012C data list ack update and status */ + __IOM uint32_t CE_CNFG_STS_REGISTER_EXT; /*!< 0x00000130 connection configuration & status register */ + __IOM uint32_t CONN_EXT_INTR; /*!< 0x00000134 Connection extended interrupt status and Clear register */ + __IOM uint32_t CONN_EXT_INTR_MASK; /*!< 0x00000138 Connection Extended Interrupt mask */ + __IM uint32_t RESERVED16; + __IOM uint32_t DATA_MEM_DESCRIPTOR[5]; /*!< 0x00000140 Data buffer descriptor 0 to 4 */ + __IM uint32_t RESERVED17[3]; + __IOM uint32_t WINDOW_WIDEN_INTVL; /*!< 0x00000160 Window widen for interval */ + __IOM uint32_t WINDOW_WIDEN_WINOFF; /*!< 0x00000164 Window widen for offset */ + __IM uint32_t RESERVED18[2]; + __IOM uint32_t LE_RF_TEST_MODE; /*!< 0x00000170 Direct Test Mode control */ + __IM uint32_t DTM_RX_PKT_COUNT; /*!< 0x00000174 Direct Test Mode receive packet count */ + __IOM uint32_t LE_RF_TEST_MODE_EXT; /*!< 0x00000178 Direct Test Mode control */ + __IM uint32_t RESERVED19[3]; + __IM uint32_t TXRX_HOP; /*!< 0x00000188 Channel Address register */ + __IM uint32_t RESERVED20; + __IOM uint32_t TX_RX_ON_DELAY; /*!< 0x00000190 Transmit/Receive data delay */ + __IM uint32_t RESERVED21[5]; + __IOM uint32_t ADV_ACCADDR_L; /*!< 0x000001A8 ADV packet access code low word */ + __IOM uint32_t ADV_ACCADDR_H; /*!< 0x000001AC ADV packet access code high word */ + __IOM uint32_t ADV_CH_TX_POWER_LVL_LS; /*!< 0x000001B0 Advertising channel transmit power setting */ + __IOM uint32_t ADV_CH_TX_POWER_LVL_MS; /*!< 0x000001B4 Advertising channel transmit power setting extension */ + __IOM uint32_t CONN_CH_TX_POWER_LVL_LS; /*!< 0x000001B8 Connection channel transmit power setting */ + __IOM uint32_t CONN_CH_TX_POWER_LVL_MS; /*!< 0x000001BC Connection channel transmit power setting extension */ + __IOM uint32_t DEV_PUB_ADDR_L; /*!< 0x000001C0 Device public address lower register */ + __IOM uint32_t DEV_PUB_ADDR_M; /*!< 0x000001C4 Device public address middle register */ + __IOM uint32_t DEV_PUB_ADDR_H; /*!< 0x000001C8 Device public address higher register */ + __IM uint32_t RESERVED22; + __IOM uint32_t OFFSET_TO_FIRST_INSTANT; /*!< 0x000001D0 Offset to first instant */ + __IOM uint32_t ADV_CONFIG; /*!< 0x000001D4 Advertiser configuration register */ + __IOM uint32_t SCAN_CONFIG; /*!< 0x000001D8 Scan configuration register */ + __IOM uint32_t INIT_CONFIG; /*!< 0x000001DC Initiator configuration register */ + __IOM uint32_t CONN_CONFIG; /*!< 0x000001E0 Connection configuration register */ + __IM uint32_t RESERVED23; + __IOM uint32_t CONN_PARAM1; /*!< 0x000001E8 Connection parameter 1 */ + __IOM uint32_t CONN_PARAM2; /*!< 0x000001EC Connection parameter 2 */ + __IOM uint32_t CONN_INTR_MASK; /*!< 0x000001F0 Connection Interrupt mask */ + __IOM uint32_t SLAVE_TIMING_CONTROL; /*!< 0x000001F4 slave timing control */ + __IOM uint32_t RECEIVE_TRIG_CTRL; /*!< 0x000001F8 Receive trigger control */ + __IM uint32_t RESERVED24; + __IM uint32_t LL_DBG_1; /*!< 0x00000200 LL debug register 1 */ + __IM uint32_t LL_DBG_2; /*!< 0x00000204 LL debug register 2 */ + __IM uint32_t LL_DBG_3; /*!< 0x00000208 LL debug register 3 */ + __IM uint32_t LL_DBG_4; /*!< 0x0000020C LL debug register 4 */ + __IM uint32_t LL_DBG_5; /*!< 0x00000210 LL debug register 5 */ + __IM uint32_t LL_DBG_6; /*!< 0x00000214 LL debug register 6 */ + __IM uint32_t LL_DBG_7; /*!< 0x00000218 LL debug register 7 */ + __IM uint32_t LL_DBG_8; /*!< 0x0000021C LL debug register 8 */ + __IM uint32_t LL_DBG_9; /*!< 0x00000220 LL debug register 9 */ + __IM uint32_t LL_DBG_10; /*!< 0x00000224 LL debug register 10 */ + __IM uint32_t RESERVED25[2]; + __IOM uint32_t PEER_ADDR_INIT_L; /*!< 0x00000230 Lower 16 bit address of the peer device for INIT. */ + __IOM uint32_t PEER_ADDR_INIT_M; /*!< 0x00000234 Middle 16 bit address of the peer device for INIT. */ + __IOM uint32_t PEER_ADDR_INIT_H; /*!< 0x00000238 Higher 16 bit address of the peer device for INIT. */ + __IM uint32_t RESERVED26[3]; + __IOM uint32_t INIT_WINDOW_TIMER_CTRL; /*!< 0x00000248 Initiator Window NI timer control */ + __IOM uint32_t CONN_CONFIG_EXT; /*!< 0x0000024C Connection extended configuration register */ + __IM uint32_t RESERVED27[2]; + __IOM uint32_t DPLL_CONFIG; /*!< 0x00000258 DPLL & CY Correlator configuration register */ + __IM uint32_t RESERVED28; + __IOM uint32_t INIT_NI_VAL; /*!< 0x00000260 Initiator Window NI instant */ + __IM uint32_t INIT_WINDOW_OFFSET; /*!< 0x00000264 Initiator Window offset captured at conn request */ + __IM uint32_t INIT_WINDOW_NI_ANCHOR_PT; /*!< 0x00000268 Initiator Window NI anchor point captured at conn request */ + __IM uint32_t RESERVED29[78]; + __IOM uint32_t CONN_UPDATE_NEW_INTERVAL; /*!< 0x000003A4 Connection update new interval */ + __IOM uint32_t CONN_UPDATE_NEW_LATENCY; /*!< 0x000003A8 Connection update new latency */ + __IOM uint32_t CONN_UPDATE_NEW_SUP_TO; /*!< 0x000003AC Connection update new supervision timeout */ + __IOM uint32_t CONN_UPDATE_NEW_SL_INTERVAL; /*!< 0x000003B0 Connection update new Slave Latency X Conn interval Value */ + __IM uint32_t RESERVED30[3]; + __IOM uint32_t CONN_REQ_WORD0; /*!< 0x000003C0 Connection request address word 0 */ + __IOM uint32_t CONN_REQ_WORD1; /*!< 0x000003C4 Connection request address word 1 */ + __IOM uint32_t CONN_REQ_WORD2; /*!< 0x000003C8 Connection request address word 2 */ + __IOM uint32_t CONN_REQ_WORD3; /*!< 0x000003CC Connection request address word 3 */ + __IOM uint32_t CONN_REQ_WORD4; /*!< 0x000003D0 Connection request address word 4 */ + __IOM uint32_t CONN_REQ_WORD5; /*!< 0x000003D4 Connection request address word 5 */ + __IOM uint32_t CONN_REQ_WORD6; /*!< 0x000003D8 Connection request address word 6 */ + __IOM uint32_t CONN_REQ_WORD7; /*!< 0x000003DC Connection request address word 7 */ + __IOM uint32_t CONN_REQ_WORD8; /*!< 0x000003E0 Connection request address word 8 */ + __IOM uint32_t CONN_REQ_WORD9; /*!< 0x000003E4 Connection request address word 9 */ + __IOM uint32_t CONN_REQ_WORD10; /*!< 0x000003E8 Connection request address word 10 */ + __IOM uint32_t CONN_REQ_WORD11; /*!< 0x000003EC Connection request address word 11 */ + __IM uint32_t RESERVED31[389]; + __IOM uint32_t PDU_RESP_TIMER; /*!< 0x00000A04 PDU response timer/Generic Timer (MMMS mode) */ + __IM uint32_t NEXT_RESP_TIMER_EXP; /*!< 0x00000A08 Next response timeout instant */ + __IM uint32_t NEXT_SUP_TO; /*!< 0x00000A0C Next supervision timeout instant */ + __IOM uint32_t LLH_FEATURE_CONFIG; /*!< 0x00000A10 Feature enable */ + __IOM uint32_t WIN_MIN_STEP_SIZE; /*!< 0x00000A14 Window minimum step size */ + __IOM uint32_t SLV_WIN_ADJ; /*!< 0x00000A18 Slave window adjustment */ + __IOM uint32_t SL_CONN_INTERVAL; /*!< 0x00000A1C Slave Latency X Conn Interval Value */ + __IOM uint32_t LE_PING_TIMER_ADDR; /*!< 0x00000A20 LE Ping connection timer address */ + __IOM uint32_t LE_PING_TIMER_OFFSET; /*!< 0x00000A24 LE Ping connection timer offset */ + __IM uint32_t LE_PING_TIMER_NEXT_EXP; /*!< 0x00000A28 LE Ping timer next expiry instant */ + __IM uint32_t LE_PING_TIMER_WRAP_COUNT; /*!< 0x00000A2C LE Ping Timer wrap count */ + __IM uint32_t RESERVED32[244]; + __IOM uint32_t TX_EN_EXT_DELAY; /*!< 0x00000E00 Transmit enable extension delay */ + __IOM uint32_t TX_RX_SYNTH_DELAY; /*!< 0x00000E04 Transmit/Receive enable delay */ + __IOM uint32_t EXT_PA_LNA_DLY_CNFG; /*!< 0x00000E08 External TX PA and RX LNA delay configuration */ + __IM uint32_t RESERVED33; + __IOM uint32_t LL_CONFIG; /*!< 0x00000E10 Link Layer additional configuration */ + __IM uint32_t RESERVED34[59]; + __IOM uint32_t LL_CONTROL; /*!< 0x00000F00 LL Backward compatibility */ + __IOM uint32_t DEV_PA_ADDR_L; /*!< 0x00000F04 Device Resolvable/Non-Resolvable Private address lower register*/ + __IOM uint32_t DEV_PA_ADDR_M; /*!< 0x00000F08 Device Resolvable/Non-Resolvable Private address middle + register */ + __IOM uint32_t DEV_PA_ADDR_H; /*!< 0x00000F0C Device Resolvable/Non-Resolvable Private address higher + register */ + __IOM uint32_t RSLV_LIST_ENABLE[16]; /*!< 0x00000F10 Resolving list entry control bit */ + __IM uint32_t RESERVED35[20]; + __IOM uint32_t WL_CONNECTION_STATUS; /*!< 0x00000FA0 whitelist valid entry bit */ + __IM uint32_t RESERVED36[535]; + __IOM uint32_t CONN_RXMEM_BASE_ADDR_DLE; /*!< 0x00001800 DLE Connection RX memory base address */ + __IM uint32_t RESERVED37[1023]; + __IOM uint32_t CONN_TXMEM_BASE_ADDR_DLE; /*!< 0x00002800 DLE Connection TX memory base address */ + __IM uint32_t RESERVED38[16383]; + __IOM uint32_t CONN_1_PARAM_MEM_BASE_ADDR; /*!< 0x00012800 Connection Parameter memory base address for connection 1 */ + __IM uint32_t RESERVED39[31]; + __IOM uint32_t CONN_2_PARAM_MEM_BASE_ADDR; /*!< 0x00012880 Connection Parameter memory base address for connection 2 */ + __IM uint32_t RESERVED40[31]; + __IOM uint32_t CONN_3_PARAM_MEM_BASE_ADDR; /*!< 0x00012900 Connection Parameter memory base address for connection 3 */ + __IM uint32_t RESERVED41[31]; + __IOM uint32_t CONN_4_PARAM_MEM_BASE_ADDR; /*!< 0x00012980 Connection Parameter memory base address for connection 4 */ + __IM uint32_t RESERVED42[1439]; + __IOM uint32_t NI_TIMER; /*!< 0x00014000 Next Instant Timer */ + __IOM uint32_t US_OFFSET; /*!< 0x00014004 Micro-second Offset */ + __IOM uint32_t NEXT_CONN; /*!< 0x00014008 Next Connection */ + __IOM uint32_t NI_ABORT; /*!< 0x0001400C Abort next scheduled connection */ + __IM uint32_t RESERVED43[4]; + __IM uint32_t CONN_NI_STATUS; /*!< 0x00014020 Connection NI Status */ + __IM uint32_t NEXT_SUP_TO_STATUS; /*!< 0x00014024 Next Supervision timeout Status */ + __IM uint32_t MMMS_CONN_STATUS; /*!< 0x00014028 Connection Status */ + __IM uint32_t BT_SLOT_CAPT_STATUS; /*!< 0x0001402C BT Slot Captured Status */ + __IM uint32_t US_CAPT_STATUS; /*!< 0x00014030 Micro-second Capture Status */ + __IM uint32_t US_OFFSET_STATUS; /*!< 0x00014034 Micro-second Offset Status */ + __IM uint32_t ACCU_WINDOW_WIDEN_STATUS; /*!< 0x00014038 Accumulated Window Widen Status */ + __IM uint32_t EARLY_INTR_STATUS; /*!< 0x0001403C Status when early interrupt is raised */ + __IOM uint32_t MMMS_CONFIG; /*!< 0x00014040 Multi-Master Multi-Slave Config */ + __IM uint32_t US_COUNTER; /*!< 0x00014044 Running US of the current BT Slot */ + __IOM uint32_t US_CAPT_PREV; /*!< 0x00014048 Previous captured US of the BT Slot */ + __IM uint32_t EARLY_INTR_NI; /*!< 0x0001404C NI at early interrupt */ + __IM uint32_t RESERVED44[12]; + __IM uint32_t MMMS_MASTER_CREATE_BT_CAPT; /*!< 0x00014080 BT slot capture for master connection creation */ + __IM uint32_t MMMS_SLAVE_CREATE_BT_CAPT; /*!< 0x00014084 BT slot capture for slave connection creation */ + __IM uint32_t MMMS_SLAVE_CREATE_US_CAPT; /*!< 0x00014088 Micro second capture for slave connection creation */ + __IM uint32_t RESERVED45[29]; + __IOM uint32_t MMMS_DATA_MEM_DESCRIPTOR[16]; /*!< 0x00014100 Data buffer descriptor 0 to 15 */ + __IM uint32_t RESERVED46[48]; + __IOM uint32_t CONN_1_DATA_LIST_SENT; /*!< 0x00014200 data list sent update and status for connection 1 */ + __IOM uint32_t CONN_1_DATA_LIST_ACK; /*!< 0x00014204 data list ack update and status for connection 1 */ + __IOM uint32_t CONN_1_CE_DATA_LIST_CFG; /*!< 0x00014208 Connection specific pause resume for connection 1 */ + __IM uint32_t RESERVED47; + __IOM uint32_t CONN_2_DATA_LIST_SENT; /*!< 0x00014210 data list sent update and status for connection 2 */ + __IOM uint32_t CONN_2_DATA_LIST_ACK; /*!< 0x00014214 data list ack update and status for connection 2 */ + __IOM uint32_t CONN_2_CE_DATA_LIST_CFG; /*!< 0x00014218 Connection specific pause resume for connection 2 */ + __IM uint32_t RESERVED48; + __IOM uint32_t CONN_3_DATA_LIST_SENT; /*!< 0x00014220 data list sent update and status for connection 3 */ + __IOM uint32_t CONN_3_DATA_LIST_ACK; /*!< 0x00014224 data list ack update and status for connection 3 */ + __IOM uint32_t CONN_3_CE_DATA_LIST_CFG; /*!< 0x00014228 Connection specific pause resume for connection 3 */ + __IM uint32_t RESERVED49; + __IOM uint32_t CONN_4_DATA_LIST_SENT; /*!< 0x00014230 data list sent update and status for connection 4 */ + __IOM uint32_t CONN_4_DATA_LIST_ACK; /*!< 0x00014234 data list ack update and status for connection 4 */ + __IOM uint32_t CONN_4_CE_DATA_LIST_CFG; /*!< 0x00014238 Connection specific pause resume for connection 4 */ + __IM uint32_t RESERVED50[113]; + __IOM uint32_t MMMS_ADVCH_NI_ENABLE; /*!< 0x00014400 Enable bits for ADV_NI, SCAN_NI and INIT_NI */ + __IOM uint32_t MMMS_ADVCH_NI_VALID; /*!< 0x00014404 Next instant valid for ADV, SCAN, INIT */ + __IOM uint32_t MMMS_ADVCH_NI_ABORT; /*!< 0x00014408 Abort the next instant of ADV, SCAN, INIT */ + __IM uint32_t RESERVED51; + __IOM uint32_t CONN_PARAM_NEXT_SUP_TO; /*!< 0x00014410 Register to configure the supervision timeout for next + scheduled connection */ + __IOM uint32_t CONN_PARAM_ACC_WIN_WIDEN; /*!< 0x00014414 Register to configure Accumulated window widening for next + scheduled connection */ + __IM uint32_t RESERVED52[2]; + __IOM uint32_t HW_LOAD_OFFSET; /*!< 0x00014420 Register to configure offset from connection anchor point at + which connection parameter memory should be read */ + __IM uint32_t ADV_RAND; /*!< 0x00014424 Random number generated by Hardware for ADV NI calculation */ + __IM uint32_t MMMS_RX_PKT_CNTR; /*!< 0x00014428 Packet Counter of packets in RX FIFO in MMMS mode */ + __IM uint32_t RESERVED53; + __IM uint32_t CONN_RX_PKT_CNTR[8]; /*!< 0x00014430 Packet Counter for Individual connection index */ + __IM uint32_t RESERVED54[236]; + __IOM uint32_t WHITELIST_BASE_ADDR; /*!< 0x00014800 Whitelist base address */ + __IM uint32_t RESERVED55[47]; + __IOM uint32_t RSLV_LIST_PEER_IDNTT_BASE_ADDR; /*!< 0x000148C0 Resolving list base address for storing Peer Identity address */ + __IM uint32_t RESERVED56[47]; + __IOM uint32_t RSLV_LIST_PEER_RPA_BASE_ADDR; /*!< 0x00014980 Resolving list base address for storing resolved Peer RPA + address */ + __IM uint32_t RESERVED57[47]; + __IOM uint32_t RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR; /*!< 0x00014A40 Resolving list base address for storing Resolved received + INITA RPA */ + __IM uint32_t RESERVED58[47]; + __IOM uint32_t RSLV_LIST_TX_INIT_RPA_BASE_ADDR; /*!< 0x00014B00 Resolving list base address for storing generated TX INITA + RPA */ + __IM uint32_t RESERVED59[9535]; +} BLE_BLELL_Type; /*!< Size = 84740 (0x14B04) */ + +/** + * \brief Bluetooth Low Energy Subsystem Miscellaneous (BLE_BLESS) + */ +typedef struct { + __IM uint32_t RESERVED[24]; + __IOM uint32_t DDFT_CONFIG; /*!< 0x00000060 BLESS DDFT configuration register */ + __IOM uint32_t XTAL_CLK_DIV_CONFIG; /*!< 0x00000064 Crystal clock divider configuration register */ + __IOM uint32_t INTR_STAT; /*!< 0x00000068 Link Layer interrupt status register */ + __IOM uint32_t INTR_MASK; /*!< 0x0000006C Link Layer interrupt mask register */ + __IOM uint32_t LL_CLK_EN; /*!< 0x00000070 Link Layer primary clock enable */ + __IOM uint32_t LF_CLK_CTRL; /*!< 0x00000074 BLESS LF clock control and BLESS revision ID indicator */ + __IOM uint32_t EXT_PA_LNA_CTRL; /*!< 0x00000078 External TX PA and RX LNA control */ + __IM uint32_t RESERVED1; + __IM uint32_t LL_PKT_RSSI_CH_ENERGY; /*!< 0x00000080 Link Layer Last Received packet RSSI/Channel energy and + channel number */ + __IM uint32_t RESERVED2[7]; + __IOM uint32_t MT_CFG; /*!< 0x000000A0 MT Configuration Register */ + __IOM uint32_t MT_DELAY_CFG; /*!< 0x000000A4 MT Delay configuration for state transitions */ + __IOM uint32_t MT_DELAY_CFG2; /*!< 0x000000A8 MT Delay configuration for state transitions */ + __IOM uint32_t MT_DELAY_CFG3; /*!< 0x000000AC MT Delay configuration for state transitions */ + __IOM uint32_t MT_VIO_CTRL; /*!< 0x000000B0 MT Configuration Register to control VIO switches */ + __IM uint32_t MT_STATUS; /*!< 0x000000B4 MT Status Register */ + __IM uint32_t PWR_CTRL_SM_ST; /*!< 0x000000B8 Link Layer Power Control FSM Status Register */ + __IM uint32_t RESERVED3; + __IOM uint32_t HVLDO_CTRL; /*!< 0x000000C0 HVLDO Configuration register */ + __IOM uint32_t MISC_EN_CTRL; /*!< 0x000000C4 Radio Buck and Active regulator enable control */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t EFUSE_CONFIG; /*!< 0x000000D0 EFUSE mode configuration register */ + __IOM uint32_t EFUSE_TIM_CTRL1; /*!< 0x000000D4 EFUSE timing control register (common for Program and Read + modes) */ + __IOM uint32_t EFUSE_TIM_CTRL2; /*!< 0x000000D8 EFUSE timing control Register (for Read) */ + __IOM uint32_t EFUSE_TIM_CTRL3; /*!< 0x000000DC EFUSE timing control Register (for Program) */ + __IM uint32_t EFUSE_RDATA_L; /*!< 0x000000E0 EFUSE Lower read data */ + __IM uint32_t EFUSE_RDATA_H; /*!< 0x000000E4 EFUSE higher read data */ + __IOM uint32_t EFUSE_WDATA_L; /*!< 0x000000E8 EFUSE lower write word */ + __IOM uint32_t EFUSE_WDATA_H; /*!< 0x000000EC EFUSE higher write word */ + __IOM uint32_t DIV_BY_625_CFG; /*!< 0x000000F0 Divide by 625 for FW Use */ + __IM uint32_t DIV_BY_625_STS; /*!< 0x000000F4 Output of divide by 625 divider */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t PACKET_COUNTER0; /*!< 0x00000100 Packet counter 0 */ + __IOM uint32_t PACKET_COUNTER2; /*!< 0x00000104 Packet counter 2 */ + __IOM uint32_t IV_MASTER0; /*!< 0x00000108 Master Initialization Vector 0 */ + __IOM uint32_t IV_SLAVE0; /*!< 0x0000010C Slave Initialization Vector 0 */ + __OM uint32_t ENC_KEY[4]; /*!< 0x00000110 Encryption Key register 0-3 */ + __IOM uint32_t MIC_IN0; /*!< 0x00000120 MIC input register */ + __IM uint32_t MIC_OUT0; /*!< 0x00000124 MIC output register */ + __IOM uint32_t ENC_PARAMS; /*!< 0x00000128 Encryption Parameter register */ + __IOM uint32_t ENC_CONFIG; /*!< 0x0000012C Encryption Configuration */ + __IOM uint32_t ENC_INTR_EN; /*!< 0x00000130 Encryption Interrupt enable */ + __IOM uint32_t ENC_INTR; /*!< 0x00000134 Encryption Interrupt status and clear register */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t B1_DATA_REG[4]; /*!< 0x00000140 Programmable B1 Data register (0-3) */ + __IOM uint32_t ENC_MEM_BASE_ADDR; /*!< 0x00000150 Encryption memory base address */ + __IM uint32_t RESERVED7[875]; + __IOM uint32_t TRIM_LDO_0; /*!< 0x00000F00 LDO Trim register 0 */ + __IOM uint32_t TRIM_LDO_1; /*!< 0x00000F04 LDO Trim register 1 */ + __IOM uint32_t TRIM_LDO_2; /*!< 0x00000F08 LDO Trim register 2 */ + __IOM uint32_t TRIM_LDO_3; /*!< 0x00000F0C LDO Trim register 3 */ + __IOM uint32_t TRIM_MXD[4]; /*!< 0x00000F10 MXD die Trim registers */ + __IM uint32_t RESERVED8[4]; + __IOM uint32_t TRIM_LDO_4; /*!< 0x00000F30 LDO Trim register 4 */ + __IOM uint32_t TRIM_LDO_5; /*!< 0x00000F34 LDO Trim register 5 */ + __IM uint32_t RESERVED9[50]; +} BLE_BLESS_Type; /*!< Size = 3896 (0xF38) */ + +/** + * \brief Bluetooth Low Energy Subsystem (BLE) + */ +typedef struct { /*!< BLE Structure */ + BLE_RCB_Type RCB; /*!< 0x00000000 Radio Control Bus (RCB) controller */ + __IM uint32_t RESERVED[896]; + BLE_BLELL_Type BLELL; /*!< 0x00001000 Bluetooth Low Energy Link Layer */ + BLE_BLESS_Type BLESS; /*!< 0x0001F000 Bluetooth Low Energy Subsystem Miscellaneous */ +} BLE_Type; /*!< Size = 131072 (0x20000) */ + + +/* ================================================== BLE_RCB_RCBLL.CTRL =================================================== */ +#define BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Pos (0UL) /*!< BLE_RCB_RCBLL CTRL: RCBLL_CTRL (Bit 0) */ +#define BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Msk (0x1UL) /*!< BLE_RCB_RCBLL CTRL: RCBLL_CTRL (Bitfield-Mask: 0x01) */ +#define BLE_RCB_RCBLL_CTRL_RCBLL_CPU_REQ_Pos (1UL) /*!< BLE_RCB_RCBLL CTRL: RCBLL_CPU_REQ (Bit 1) */ +#define BLE_RCB_RCBLL_CTRL_RCBLL_CPU_REQ_Msk (0x2UL) /*!< BLE_RCB_RCBLL CTRL: RCBLL_CPU_REQ (Bitfield-Mask: 0x01) */ +#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_WRITE_Pos (2UL) /*!< BLE_RCB_RCBLL CTRL: CPU_SINGLE_WRITE (Bit 2) */ +#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_WRITE_Msk (0x4UL) /*!< BLE_RCB_RCBLL CTRL: CPU_SINGLE_WRITE (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_READ_Pos (3UL) /*!< BLE_RCB_RCBLL CTRL: CPU_SINGLE_READ (Bit 3) */ +#define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_READ_Msk (0x8UL) /*!< BLE_RCB_RCBLL CTRL: CPU_SINGLE_READ (Bitfield-Mask: 0x01) */ +#define BLE_RCB_RCBLL_CTRL_ALLOW_CPU_ACCESS_TX_RX_Pos (4UL) /*!< BLE_RCB_RCBLL CTRL: ALLOW_CPU_ACCESS_TX_RX (Bit 4) */ +#define BLE_RCB_RCBLL_CTRL_ALLOW_CPU_ACCESS_TX_RX_Msk (0x10UL) /*!< BLE_RCB_RCBLL CTRL: ALLOW_CPU_ACCESS_TX_RX (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_RCBLL_CTRL_ENABLE_RADIO_BOD_Pos (5UL) /*!< BLE_RCB_RCBLL CTRL: ENABLE_RADIO_BOD (Bit 5) */ +#define BLE_RCB_RCBLL_CTRL_ENABLE_RADIO_BOD_Msk (0x20UL) /*!< BLE_RCB_RCBLL CTRL: ENABLE_RADIO_BOD (Bitfield-Mask: 0x01)*/ +/* ================================================== BLE_RCB_RCBLL.INTR =================================================== */ +#define BLE_RCB_RCBLL_INTR_RCB_LL_DONE_Pos (0UL) /*!< BLE_RCB_RCBLL INTR: RCB_LL_DONE (Bit 0) */ +#define BLE_RCB_RCBLL_INTR_RCB_LL_DONE_Msk (0x1UL) /*!< BLE_RCB_RCBLL INTR: RCB_LL_DONE (Bitfield-Mask: 0x01) */ +#define BLE_RCB_RCBLL_INTR_SINGLE_WRITE_DONE_Pos (2UL) /*!< BLE_RCB_RCBLL INTR: SINGLE_WRITE_DONE (Bit 2) */ +#define BLE_RCB_RCBLL_INTR_SINGLE_WRITE_DONE_Msk (0x4UL) /*!< BLE_RCB_RCBLL INTR: SINGLE_WRITE_DONE (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_RCBLL_INTR_SINGLE_READ_DONE_Pos (3UL) /*!< BLE_RCB_RCBLL INTR: SINGLE_READ_DONE (Bit 3) */ +#define BLE_RCB_RCBLL_INTR_SINGLE_READ_DONE_Msk (0x8UL) /*!< BLE_RCB_RCBLL INTR: SINGLE_READ_DONE (Bitfield-Mask: 0x01)*/ +/* ================================================ BLE_RCB_RCBLL.INTR_SET ================================================= */ +#define BLE_RCB_RCBLL_INTR_SET_RCB_LL_DONE_Pos (0UL) /*!< BLE_RCB_RCBLL INTR_SET: RCB_LL_DONE (Bit 0) */ +#define BLE_RCB_RCBLL_INTR_SET_RCB_LL_DONE_Msk (0x1UL) /*!< BLE_RCB_RCBLL INTR_SET: RCB_LL_DONE (Bitfield-Mask: 0x01) */ +#define BLE_RCB_RCBLL_INTR_SET_SINGLE_WRITE_DONE_Pos (2UL) /*!< BLE_RCB_RCBLL INTR_SET: SINGLE_WRITE_DONE (Bit 2) */ +#define BLE_RCB_RCBLL_INTR_SET_SINGLE_WRITE_DONE_Msk (0x4UL) /*!< BLE_RCB_RCBLL INTR_SET: SINGLE_WRITE_DONE (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_RCBLL_INTR_SET_SINGLE_READ_DONE_Pos (3UL) /*!< BLE_RCB_RCBLL INTR_SET: SINGLE_READ_DONE (Bit 3) */ +#define BLE_RCB_RCBLL_INTR_SET_SINGLE_READ_DONE_Msk (0x8UL) /*!< BLE_RCB_RCBLL INTR_SET: SINGLE_READ_DONE (Bitfield-Mask: 0x01)*/ +/* ================================================ BLE_RCB_RCBLL.INTR_MASK ================================================ */ +#define BLE_RCB_RCBLL_INTR_MASK_RCB_LL_DONE_Pos (0UL) /*!< BLE_RCB_RCBLL INTR_MASK: RCB_LL_DONE (Bit 0) */ +#define BLE_RCB_RCBLL_INTR_MASK_RCB_LL_DONE_Msk (0x1UL) /*!< BLE_RCB_RCBLL INTR_MASK: RCB_LL_DONE (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_WRITE_DONE_Pos (2UL) /*!< BLE_RCB_RCBLL INTR_MASK: SINGLE_WRITE_DONE (Bit 2) */ +#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_WRITE_DONE_Msk (0x4UL) /*!< BLE_RCB_RCBLL INTR_MASK: SINGLE_WRITE_DONE (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_READ_DONE_Pos (3UL) /*!< BLE_RCB_RCBLL INTR_MASK: SINGLE_READ_DONE (Bit 3) */ +#define BLE_RCB_RCBLL_INTR_MASK_SINGLE_READ_DONE_Msk (0x8UL) /*!< BLE_RCB_RCBLL INTR_MASK: SINGLE_READ_DONE (Bitfield-Mask: 0x01)*/ +/* =============================================== BLE_RCB_RCBLL.INTR_MASKED =============================================== */ +#define BLE_RCB_RCBLL_INTR_MASKED_RCB_LL_DONE_Pos (0UL) /*!< BLE_RCB_RCBLL INTR_MASKED: RCB_LL_DONE (Bit 0) */ +#define BLE_RCB_RCBLL_INTR_MASKED_RCB_LL_DONE_Msk (0x1UL) /*!< BLE_RCB_RCBLL INTR_MASKED: RCB_LL_DONE (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_WRITE_DONE_Pos (2UL) /*!< BLE_RCB_RCBLL INTR_MASKED: SINGLE_WRITE_DONE (Bit 2) */ +#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_WRITE_DONE_Msk (0x4UL) /*!< BLE_RCB_RCBLL INTR_MASKED: SINGLE_WRITE_DONE (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_READ_DONE_Pos (3UL) /*!< BLE_RCB_RCBLL INTR_MASKED: SINGLE_READ_DONE (Bit 3) */ +#define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_READ_DONE_Msk (0x8UL) /*!< BLE_RCB_RCBLL INTR_MASKED: SINGLE_READ_DONE (Bitfield-Mask: 0x01)*/ +/* ============================================= BLE_RCB_RCBLL.RADIO_REG1_ADDR ============================================= */ +#define BLE_RCB_RCBLL_RADIO_REG1_ADDR_REG_ADDR_Pos (0UL) /*!< BLE_RCB_RCBLL RADIO_REG1_ADDR: REG_ADDR (Bit 0) */ +#define BLE_RCB_RCBLL_RADIO_REG1_ADDR_REG_ADDR_Msk (0xffffUL) /*!< BLE_RCB_RCBLL RADIO_REG1_ADDR: REG_ADDR (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_RCB_RCBLL.RADIO_REG2_ADDR ============================================= */ +#define BLE_RCB_RCBLL_RADIO_REG2_ADDR_REG_ADDR_Pos (0UL) /*!< BLE_RCB_RCBLL RADIO_REG2_ADDR: REG_ADDR (Bit 0) */ +#define BLE_RCB_RCBLL_RADIO_REG2_ADDR_REG_ADDR_Msk (0xffffUL) /*!< BLE_RCB_RCBLL RADIO_REG2_ADDR: REG_ADDR (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_RCB_RCBLL.RADIO_REG3_ADDR ============================================= */ +#define BLE_RCB_RCBLL_RADIO_REG3_ADDR_REG_ADDR_Pos (0UL) /*!< BLE_RCB_RCBLL RADIO_REG3_ADDR: REG_ADDR (Bit 0) */ +#define BLE_RCB_RCBLL_RADIO_REG3_ADDR_REG_ADDR_Msk (0xffffUL) /*!< BLE_RCB_RCBLL RADIO_REG3_ADDR: REG_ADDR (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_RCB_RCBLL.RADIO_REG4_ADDR ============================================= */ +#define BLE_RCB_RCBLL_RADIO_REG4_ADDR_REG_ADDR_Pos (0UL) /*!< BLE_RCB_RCBLL RADIO_REG4_ADDR: REG_ADDR (Bit 0) */ +#define BLE_RCB_RCBLL_RADIO_REG4_ADDR_REG_ADDR_Msk (0xffffUL) /*!< BLE_RCB_RCBLL RADIO_REG4_ADDR: REG_ADDR (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_RCB_RCBLL.RADIO_REG5_ADDR ============================================= */ +#define BLE_RCB_RCBLL_RADIO_REG5_ADDR_REG_ADDR_Pos (0UL) /*!< BLE_RCB_RCBLL RADIO_REG5_ADDR: REG_ADDR (Bit 0) */ +#define BLE_RCB_RCBLL_RADIO_REG5_ADDR_REG_ADDR_Msk (0xffffUL) /*!< BLE_RCB_RCBLL RADIO_REG5_ADDR: REG_ADDR (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_RCB_RCBLL.CPU_WRITE_REG ============================================== */ +#define BLE_RCB_RCBLL_CPU_WRITE_REG_ADDR_Pos (0UL) /*!< BLE_RCB_RCBLL CPU_WRITE_REG: ADDR (Bit 0) */ +#define BLE_RCB_RCBLL_CPU_WRITE_REG_ADDR_Msk (0xffffUL) /*!< BLE_RCB_RCBLL CPU_WRITE_REG: ADDR (Bitfield-Mask: 0xffff) */ +#define BLE_RCB_RCBLL_CPU_WRITE_REG_WRITE_DATA_Pos (16UL) /*!< BLE_RCB_RCBLL CPU_WRITE_REG: WRITE_DATA (Bit 16) */ +#define BLE_RCB_RCBLL_CPU_WRITE_REG_WRITE_DATA_Msk (0xffff0000UL) /*!< BLE_RCB_RCBLL CPU_WRITE_REG: WRITE_DATA (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_RCB_RCBLL.CPU_READ_REG =============================================== */ +#define BLE_RCB_RCBLL_CPU_READ_REG_ADDR_Pos (0UL) /*!< BLE_RCB_RCBLL CPU_READ_REG: ADDR (Bit 0) */ +#define BLE_RCB_RCBLL_CPU_READ_REG_ADDR_Msk (0xffffUL) /*!< BLE_RCB_RCBLL CPU_READ_REG: ADDR (Bitfield-Mask: 0xffff) */ +#define BLE_RCB_RCBLL_CPU_READ_REG_READ_DATA_Pos (16UL) /*!< BLE_RCB_RCBLL CPU_READ_REG: READ_DATA (Bit 16) */ +#define BLE_RCB_RCBLL_CPU_READ_REG_READ_DATA_Msk (0xffff0000UL) /*!< BLE_RCB_RCBLL CPU_READ_REG: READ_DATA (Bitfield-Mask: 0xffff)*/ + + +/* ===================================================== BLE_RCB.CTRL ====================================================== */ +#define BLE_RCB_CTRL_TX_CLK_EDGE_Pos (1UL) /*!< BLE_RCB CTRL: TX_CLK_EDGE (Bit 1) */ +#define BLE_RCB_CTRL_TX_CLK_EDGE_Msk (0x2UL) /*!< BLE_RCB CTRL: TX_CLK_EDGE (Bitfield-Mask: 0x01) */ +#define BLE_RCB_CTRL_RX_CLK_EDGE_Pos (2UL) /*!< BLE_RCB CTRL: RX_CLK_EDGE (Bit 2) */ +#define BLE_RCB_CTRL_RX_CLK_EDGE_Msk (0x4UL) /*!< BLE_RCB CTRL: RX_CLK_EDGE (Bitfield-Mask: 0x01) */ +#define BLE_RCB_CTRL_RX_CLK_SRC_Pos (3UL) /*!< BLE_RCB CTRL: RX_CLK_SRC (Bit 3) */ +#define BLE_RCB_CTRL_RX_CLK_SRC_Msk (0x8UL) /*!< BLE_RCB CTRL: RX_CLK_SRC (Bitfield-Mask: 0x01) */ +#define BLE_RCB_CTRL_SCLK_CONTINUOUS_Pos (4UL) /*!< BLE_RCB CTRL: SCLK_CONTINUOUS (Bit 4) */ +#define BLE_RCB_CTRL_SCLK_CONTINUOUS_Msk (0x10UL) /*!< BLE_RCB CTRL: SCLK_CONTINUOUS (Bitfield-Mask: 0x01) */ +#define BLE_RCB_CTRL_SSEL_POLARITY_Pos (5UL) /*!< BLE_RCB CTRL: SSEL_POLARITY (Bit 5) */ +#define BLE_RCB_CTRL_SSEL_POLARITY_Msk (0x20UL) /*!< BLE_RCB CTRL: SSEL_POLARITY (Bitfield-Mask: 0x01) */ +#define BLE_RCB_CTRL_LEAD_Pos (8UL) /*!< BLE_RCB CTRL: LEAD (Bit 8) */ +#define BLE_RCB_CTRL_LEAD_Msk (0x300UL) /*!< BLE_RCB CTRL: LEAD (Bitfield-Mask: 0x03) */ +#define BLE_RCB_CTRL_LAG_Pos (10UL) /*!< BLE_RCB CTRL: LAG (Bit 10) */ +#define BLE_RCB_CTRL_LAG_Msk (0xc00UL) /*!< BLE_RCB CTRL: LAG (Bitfield-Mask: 0x03) */ +#define BLE_RCB_CTRL_DIV_ENABLED_Pos (12UL) /*!< BLE_RCB CTRL: DIV_ENABLED (Bit 12) */ +#define BLE_RCB_CTRL_DIV_ENABLED_Msk (0x1000UL) /*!< BLE_RCB CTRL: DIV_ENABLED (Bitfield-Mask: 0x01) */ +#define BLE_RCB_CTRL_DIV_Pos (13UL) /*!< BLE_RCB CTRL: DIV (Bit 13) */ +#define BLE_RCB_CTRL_DIV_Msk (0x7e000UL) /*!< BLE_RCB CTRL: DIV (Bitfield-Mask: 0x3f) */ +#define BLE_RCB_CTRL_ADDR_WIDTH_Pos (19UL) /*!< BLE_RCB CTRL: ADDR_WIDTH (Bit 19) */ +#define BLE_RCB_CTRL_ADDR_WIDTH_Msk (0x780000UL) /*!< BLE_RCB CTRL: ADDR_WIDTH (Bitfield-Mask: 0x0f) */ +#define BLE_RCB_CTRL_DATA_WIDTH_Pos (23UL) /*!< BLE_RCB CTRL: DATA_WIDTH (Bit 23) */ +#define BLE_RCB_CTRL_DATA_WIDTH_Msk (0x800000UL) /*!< BLE_RCB CTRL: DATA_WIDTH (Bitfield-Mask: 0x01) */ +#define BLE_RCB_CTRL_ENABLED_Pos (31UL) /*!< BLE_RCB CTRL: ENABLED (Bit 31) */ +#define BLE_RCB_CTRL_ENABLED_Msk (0x80000000UL) /*!< BLE_RCB CTRL: ENABLED (Bitfield-Mask: 0x01) */ +/* ==================================================== BLE_RCB.STATUS ===================================================== */ +#define BLE_RCB_STATUS_BUS_BUSY_Pos (0UL) /*!< BLE_RCB STATUS: BUS_BUSY (Bit 0) */ +#define BLE_RCB_STATUS_BUS_BUSY_Msk (0x1UL) /*!< BLE_RCB STATUS: BUS_BUSY (Bitfield-Mask: 0x01) */ +/* ==================================================== BLE_RCB.TX_CTRL ==================================================== */ +#define BLE_RCB_TX_CTRL_MSB_FIRST_Pos (0UL) /*!< BLE_RCB TX_CTRL: MSB_FIRST (Bit 0) */ +#define BLE_RCB_TX_CTRL_MSB_FIRST_Msk (0x1UL) /*!< BLE_RCB TX_CTRL: MSB_FIRST (Bitfield-Mask: 0x01) */ +#define BLE_RCB_TX_CTRL_FIFO_RECONFIG_Pos (1UL) /*!< BLE_RCB TX_CTRL: FIFO_RECONFIG (Bit 1) */ +#define BLE_RCB_TX_CTRL_FIFO_RECONFIG_Msk (0x2UL) /*!< BLE_RCB TX_CTRL: FIFO_RECONFIG (Bitfield-Mask: 0x01) */ +#define BLE_RCB_TX_CTRL_TX_ENTRIES_Pos (2UL) /*!< BLE_RCB TX_CTRL: TX_ENTRIES (Bit 2) */ +#define BLE_RCB_TX_CTRL_TX_ENTRIES_Msk (0x7cUL) /*!< BLE_RCB TX_CTRL: TX_ENTRIES (Bitfield-Mask: 0x1f) */ +/* ================================================= BLE_RCB.TX_FIFO_CTRL ================================================== */ +#define BLE_RCB_TX_FIFO_CTRL_TX_TRIGGER_LEVEL_Pos (0UL) /*!< BLE_RCB TX_FIFO_CTRL: TX_TRIGGER_LEVEL (Bit 0) */ +#define BLE_RCB_TX_FIFO_CTRL_TX_TRIGGER_LEVEL_Msk (0x1fUL) /*!< BLE_RCB TX_FIFO_CTRL: TX_TRIGGER_LEVEL (Bitfield-Mask: 0x1f)*/ +#define BLE_RCB_TX_FIFO_CTRL_CLEAR_Pos (16UL) /*!< BLE_RCB TX_FIFO_CTRL: CLEAR (Bit 16) */ +#define BLE_RCB_TX_FIFO_CTRL_CLEAR_Msk (0x10000UL) /*!< BLE_RCB TX_FIFO_CTRL: CLEAR (Bitfield-Mask: 0x01) */ +/* ================================================ BLE_RCB.TX_FIFO_STATUS ================================================= */ +#define BLE_RCB_TX_FIFO_STATUS_USED_Pos (0UL) /*!< BLE_RCB TX_FIFO_STATUS: USED (Bit 0) */ +#define BLE_RCB_TX_FIFO_STATUS_USED_Msk (0x1fUL) /*!< BLE_RCB TX_FIFO_STATUS: USED (Bitfield-Mask: 0x1f) */ +#define BLE_RCB_TX_FIFO_STATUS_SR_VALID_Pos (15UL) /*!< BLE_RCB TX_FIFO_STATUS: SR_VALID (Bit 15) */ +#define BLE_RCB_TX_FIFO_STATUS_SR_VALID_Msk (0x8000UL) /*!< BLE_RCB TX_FIFO_STATUS: SR_VALID (Bitfield-Mask: 0x01) */ +#define BLE_RCB_TX_FIFO_STATUS_RD_PTR_Pos (16UL) /*!< BLE_RCB TX_FIFO_STATUS: RD_PTR (Bit 16) */ +#define BLE_RCB_TX_FIFO_STATUS_RD_PTR_Msk (0xf0000UL) /*!< BLE_RCB TX_FIFO_STATUS: RD_PTR (Bitfield-Mask: 0x0f) */ +#define BLE_RCB_TX_FIFO_STATUS_WR_PTR_Pos (24UL) /*!< BLE_RCB TX_FIFO_STATUS: WR_PTR (Bit 24) */ +#define BLE_RCB_TX_FIFO_STATUS_WR_PTR_Msk (0xf000000UL) /*!< BLE_RCB TX_FIFO_STATUS: WR_PTR (Bitfield-Mask: 0x0f) */ +/* ================================================== BLE_RCB.TX_FIFO_WR =================================================== */ +#define BLE_RCB_TX_FIFO_WR_DATA_Pos (0UL) /*!< BLE_RCB TX_FIFO_WR: DATA (Bit 0) */ +#define BLE_RCB_TX_FIFO_WR_DATA_Msk (0xffffffffUL) /*!< BLE_RCB TX_FIFO_WR: DATA (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== BLE_RCB.RX_CTRL ==================================================== */ +#define BLE_RCB_RX_CTRL_MSB_FIRST_Pos (0UL) /*!< BLE_RCB RX_CTRL: MSB_FIRST (Bit 0) */ +#define BLE_RCB_RX_CTRL_MSB_FIRST_Msk (0x1UL) /*!< BLE_RCB RX_CTRL: MSB_FIRST (Bitfield-Mask: 0x01) */ +/* ================================================= BLE_RCB.RX_FIFO_CTRL ================================================== */ +#define BLE_RCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos (0UL) /*!< BLE_RCB RX_FIFO_CTRL: TRIGGER_LEVEL (Bit 0) */ +#define BLE_RCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk (0xfUL) /*!< BLE_RCB RX_FIFO_CTRL: TRIGGER_LEVEL (Bitfield-Mask: 0x0f) */ +#define BLE_RCB_RX_FIFO_CTRL_CLEAR_Pos (16UL) /*!< BLE_RCB RX_FIFO_CTRL: CLEAR (Bit 16) */ +#define BLE_RCB_RX_FIFO_CTRL_CLEAR_Msk (0x10000UL) /*!< BLE_RCB RX_FIFO_CTRL: CLEAR (Bitfield-Mask: 0x01) */ +/* ================================================ BLE_RCB.RX_FIFO_STATUS ================================================= */ +#define BLE_RCB_RX_FIFO_STATUS_USED_Pos (0UL) /*!< BLE_RCB RX_FIFO_STATUS: USED (Bit 0) */ +#define BLE_RCB_RX_FIFO_STATUS_USED_Msk (0x1fUL) /*!< BLE_RCB RX_FIFO_STATUS: USED (Bitfield-Mask: 0x1f) */ +#define BLE_RCB_RX_FIFO_STATUS_SR_VALID_Pos (15UL) /*!< BLE_RCB RX_FIFO_STATUS: SR_VALID (Bit 15) */ +#define BLE_RCB_RX_FIFO_STATUS_SR_VALID_Msk (0x8000UL) /*!< BLE_RCB RX_FIFO_STATUS: SR_VALID (Bitfield-Mask: 0x01) */ +#define BLE_RCB_RX_FIFO_STATUS_RD_PTR_Pos (16UL) /*!< BLE_RCB RX_FIFO_STATUS: RD_PTR (Bit 16) */ +#define BLE_RCB_RX_FIFO_STATUS_RD_PTR_Msk (0xf0000UL) /*!< BLE_RCB RX_FIFO_STATUS: RD_PTR (Bitfield-Mask: 0x0f) */ +#define BLE_RCB_RX_FIFO_STATUS_WR_PTR_Pos (24UL) /*!< BLE_RCB RX_FIFO_STATUS: WR_PTR (Bit 24) */ +#define BLE_RCB_RX_FIFO_STATUS_WR_PTR_Msk (0xf000000UL) /*!< BLE_RCB RX_FIFO_STATUS: WR_PTR (Bitfield-Mask: 0x0f) */ +/* ================================================== BLE_RCB.RX_FIFO_RD =================================================== */ +#define BLE_RCB_RX_FIFO_RD_DATA_Pos (0UL) /*!< BLE_RCB RX_FIFO_RD: DATA (Bit 0) */ +#define BLE_RCB_RX_FIFO_RD_DATA_Msk (0xffffffffUL) /*!< BLE_RCB RX_FIFO_RD: DATA (Bitfield-Mask: 0xffffffff) */ +/* =============================================== BLE_RCB.RX_FIFO_RD_SILENT =============================================== */ +#define BLE_RCB_RX_FIFO_RD_SILENT_DATA_Pos (0UL) /*!< BLE_RCB RX_FIFO_RD_SILENT: DATA (Bit 0) */ +#define BLE_RCB_RX_FIFO_RD_SILENT_DATA_Msk (0xffffffffUL) /*!< BLE_RCB RX_FIFO_RD_SILENT: DATA (Bitfield-Mask: 0xffffffff)*/ +/* ===================================================== BLE_RCB.INTR ====================================================== */ +#define BLE_RCB_INTR_RCB_DONE_Pos (0UL) /*!< BLE_RCB INTR: RCB_DONE (Bit 0) */ +#define BLE_RCB_INTR_RCB_DONE_Msk (0x1UL) /*!< BLE_RCB INTR: RCB_DONE (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_TX_FIFO_TRIGGER_Pos (8UL) /*!< BLE_RCB INTR: TX_FIFO_TRIGGER (Bit 8) */ +#define BLE_RCB_INTR_TX_FIFO_TRIGGER_Msk (0x100UL) /*!< BLE_RCB INTR: TX_FIFO_TRIGGER (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_TX_FIFO_NOT_FULL_Pos (9UL) /*!< BLE_RCB INTR: TX_FIFO_NOT_FULL (Bit 9) */ +#define BLE_RCB_INTR_TX_FIFO_NOT_FULL_Msk (0x200UL) /*!< BLE_RCB INTR: TX_FIFO_NOT_FULL (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_TX_FIFO_EMPTY_Pos (10UL) /*!< BLE_RCB INTR: TX_FIFO_EMPTY (Bit 10) */ +#define BLE_RCB_INTR_TX_FIFO_EMPTY_Msk (0x400UL) /*!< BLE_RCB INTR: TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_TX_FIFO_OVERFLOW_Pos (11UL) /*!< BLE_RCB INTR: TX_FIFO_OVERFLOW (Bit 11) */ +#define BLE_RCB_INTR_TX_FIFO_OVERFLOW_Msk (0x800UL) /*!< BLE_RCB INTR: TX_FIFO_OVERFLOW (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_TX_FIFO_UNDERFLOW_Pos (12UL) /*!< BLE_RCB INTR: TX_FIFO_UNDERFLOW (Bit 12) */ +#define BLE_RCB_INTR_TX_FIFO_UNDERFLOW_Msk (0x1000UL) /*!< BLE_RCB INTR: TX_FIFO_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_RX_FIFO_TRIGGER_Pos (16UL) /*!< BLE_RCB INTR: RX_FIFO_TRIGGER (Bit 16) */ +#define BLE_RCB_INTR_RX_FIFO_TRIGGER_Msk (0x10000UL) /*!< BLE_RCB INTR: RX_FIFO_TRIGGER (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_RX_FIFO_NOT_EMPTY_Pos (17UL) /*!< BLE_RCB INTR: RX_FIFO_NOT_EMPTY (Bit 17) */ +#define BLE_RCB_INTR_RX_FIFO_NOT_EMPTY_Msk (0x20000UL) /*!< BLE_RCB INTR: RX_FIFO_NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_RX_FIFO_FULL_Pos (18UL) /*!< BLE_RCB INTR: RX_FIFO_FULL (Bit 18) */ +#define BLE_RCB_INTR_RX_FIFO_FULL_Msk (0x40000UL) /*!< BLE_RCB INTR: RX_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_RX_FIFO_OVERFLOW_Pos (19UL) /*!< BLE_RCB INTR: RX_FIFO_OVERFLOW (Bit 19) */ +#define BLE_RCB_INTR_RX_FIFO_OVERFLOW_Msk (0x80000UL) /*!< BLE_RCB INTR: RX_FIFO_OVERFLOW (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_RX_FIFO_UNDERFLOW_Pos (20UL) /*!< BLE_RCB INTR: RX_FIFO_UNDERFLOW (Bit 20) */ +#define BLE_RCB_INTR_RX_FIFO_UNDERFLOW_Msk (0x100000UL) /*!< BLE_RCB INTR: RX_FIFO_UNDERFLOW (Bitfield-Mask: 0x01) */ +/* =================================================== BLE_RCB.INTR_SET ==================================================== */ +#define BLE_RCB_INTR_SET_RCB_DONE_Pos (0UL) /*!< BLE_RCB INTR_SET: RCB_DONE (Bit 0) */ +#define BLE_RCB_INTR_SET_RCB_DONE_Msk (0x1UL) /*!< BLE_RCB INTR_SET: RCB_DONE (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_SET_TX_FIFO_TRIGGER_Pos (8UL) /*!< BLE_RCB INTR_SET: TX_FIFO_TRIGGER (Bit 8) */ +#define BLE_RCB_INTR_SET_TX_FIFO_TRIGGER_Msk (0x100UL) /*!< BLE_RCB INTR_SET: TX_FIFO_TRIGGER (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_SET_TX_FIFO_NOT_FULL_Pos (9UL) /*!< BLE_RCB INTR_SET: TX_FIFO_NOT_FULL (Bit 9) */ +#define BLE_RCB_INTR_SET_TX_FIFO_NOT_FULL_Msk (0x200UL) /*!< BLE_RCB INTR_SET: TX_FIFO_NOT_FULL (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_SET_TX_FIFO_EMPTY_Pos (10UL) /*!< BLE_RCB INTR_SET: TX_FIFO_EMPTY (Bit 10) */ +#define BLE_RCB_INTR_SET_TX_FIFO_EMPTY_Msk (0x400UL) /*!< BLE_RCB INTR_SET: TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_SET_TX_FIFO_OVERFLOW_Pos (11UL) /*!< BLE_RCB INTR_SET: TX_FIFO_OVERFLOW (Bit 11) */ +#define BLE_RCB_INTR_SET_TX_FIFO_OVERFLOW_Msk (0x800UL) /*!< BLE_RCB INTR_SET: TX_FIFO_OVERFLOW (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_SET_TX_FIFO_UNDERFLOW_Pos (12UL) /*!< BLE_RCB INTR_SET: TX_FIFO_UNDERFLOW (Bit 12) */ +#define BLE_RCB_INTR_SET_TX_FIFO_UNDERFLOW_Msk (0x1000UL) /*!< BLE_RCB INTR_SET: TX_FIFO_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_SET_RX_FIFO_TRIGGER_Pos (16UL) /*!< BLE_RCB INTR_SET: RX_FIFO_TRIGGER (Bit 16) */ +#define BLE_RCB_INTR_SET_RX_FIFO_TRIGGER_Msk (0x10000UL) /*!< BLE_RCB INTR_SET: RX_FIFO_TRIGGER (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_SET_RX_FIFO_NOT_EMPTY_Pos (17UL) /*!< BLE_RCB INTR_SET: RX_FIFO_NOT_EMPTY (Bit 17) */ +#define BLE_RCB_INTR_SET_RX_FIFO_NOT_EMPTY_Msk (0x20000UL) /*!< BLE_RCB INTR_SET: RX_FIFO_NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_SET_RX_FIFO_FULL_Pos (18UL) /*!< BLE_RCB INTR_SET: RX_FIFO_FULL (Bit 18) */ +#define BLE_RCB_INTR_SET_RX_FIFO_FULL_Msk (0x40000UL) /*!< BLE_RCB INTR_SET: RX_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_SET_RX_FIFO_OVERFLOW_Pos (19UL) /*!< BLE_RCB INTR_SET: RX_FIFO_OVERFLOW (Bit 19) */ +#define BLE_RCB_INTR_SET_RX_FIFO_OVERFLOW_Msk (0x80000UL) /*!< BLE_RCB INTR_SET: RX_FIFO_OVERFLOW (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_SET_RX_FIFO_UNDERFLOW_Pos (20UL) /*!< BLE_RCB INTR_SET: RX_FIFO_UNDERFLOW (Bit 20) */ +#define BLE_RCB_INTR_SET_RX_FIFO_UNDERFLOW_Msk (0x100000UL) /*!< BLE_RCB INTR_SET: RX_FIFO_UNDERFLOW (Bitfield-Mask: 0x01) */ +/* =================================================== BLE_RCB.INTR_MASK =================================================== */ +#define BLE_RCB_INTR_MASK_RCB_DONE_Pos (0UL) /*!< BLE_RCB INTR_MASK: RCB_DONE (Bit 0) */ +#define BLE_RCB_INTR_MASK_RCB_DONE_Msk (0x1UL) /*!< BLE_RCB INTR_MASK: RCB_DONE (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASK_TX_FIFO_TRIGGER_Pos (8UL) /*!< BLE_RCB INTR_MASK: TX_FIFO_TRIGGER (Bit 8) */ +#define BLE_RCB_INTR_MASK_TX_FIFO_TRIGGER_Msk (0x100UL) /*!< BLE_RCB INTR_MASK: TX_FIFO_TRIGGER (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASK_TX_FIFO_NOT_FULL_Pos (9UL) /*!< BLE_RCB INTR_MASK: TX_FIFO_NOT_FULL (Bit 9) */ +#define BLE_RCB_INTR_MASK_TX_FIFO_NOT_FULL_Msk (0x200UL) /*!< BLE_RCB INTR_MASK: TX_FIFO_NOT_FULL (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASK_TX_FIFO_EMPTY_Pos (10UL) /*!< BLE_RCB INTR_MASK: TX_FIFO_EMPTY (Bit 10) */ +#define BLE_RCB_INTR_MASK_TX_FIFO_EMPTY_Msk (0x400UL) /*!< BLE_RCB INTR_MASK: TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASK_TX_FIFO_OVERFLOW_Pos (11UL) /*!< BLE_RCB INTR_MASK: TX_FIFO_OVERFLOW (Bit 11) */ +#define BLE_RCB_INTR_MASK_TX_FIFO_OVERFLOW_Msk (0x800UL) /*!< BLE_RCB INTR_MASK: TX_FIFO_OVERFLOW (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASK_TX_FIFO_UNDERFLOW_Pos (12UL) /*!< BLE_RCB INTR_MASK: TX_FIFO_UNDERFLOW (Bit 12) */ +#define BLE_RCB_INTR_MASK_TX_FIFO_UNDERFLOW_Msk (0x1000UL) /*!< BLE_RCB INTR_MASK: TX_FIFO_UNDERFLOW (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_INTR_MASK_RX_FIFO_TRIGGER_Pos (16UL) /*!< BLE_RCB INTR_MASK: RX_FIFO_TRIGGER (Bit 16) */ +#define BLE_RCB_INTR_MASK_RX_FIFO_TRIGGER_Msk (0x10000UL) /*!< BLE_RCB INTR_MASK: RX_FIFO_TRIGGER (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASK_RX_FIFO_NOT_EMPTY_Pos (17UL) /*!< BLE_RCB INTR_MASK: RX_FIFO_NOT_EMPTY (Bit 17) */ +#define BLE_RCB_INTR_MASK_RX_FIFO_NOT_EMPTY_Msk (0x20000UL) /*!< BLE_RCB INTR_MASK: RX_FIFO_NOT_EMPTY (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_INTR_MASK_RX_FIFO_FULL_Pos (18UL) /*!< BLE_RCB INTR_MASK: RX_FIFO_FULL (Bit 18) */ +#define BLE_RCB_INTR_MASK_RX_FIFO_FULL_Msk (0x40000UL) /*!< BLE_RCB INTR_MASK: RX_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASK_RX_FIFO_OVERFLOW_Pos (19UL) /*!< BLE_RCB INTR_MASK: RX_FIFO_OVERFLOW (Bit 19) */ +#define BLE_RCB_INTR_MASK_RX_FIFO_OVERFLOW_Msk (0x80000UL) /*!< BLE_RCB INTR_MASK: RX_FIFO_OVERFLOW (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASK_RX_FIFO_UNDERFLOW_Pos (20UL) /*!< BLE_RCB INTR_MASK: RX_FIFO_UNDERFLOW (Bit 20) */ +#define BLE_RCB_INTR_MASK_RX_FIFO_UNDERFLOW_Msk (0x100000UL) /*!< BLE_RCB INTR_MASK: RX_FIFO_UNDERFLOW (Bitfield-Mask: 0x01)*/ +/* ================================================== BLE_RCB.INTR_MASKED ================================================== */ +#define BLE_RCB_INTR_MASKED_RCB_DONE_Pos (0UL) /*!< BLE_RCB INTR_MASKED: RCB_DONE (Bit 0) */ +#define BLE_RCB_INTR_MASKED_RCB_DONE_Msk (0x1UL) /*!< BLE_RCB INTR_MASKED: RCB_DONE (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASKED_TX_FIFO_TRIGGER_Pos (8UL) /*!< BLE_RCB INTR_MASKED: TX_FIFO_TRIGGER (Bit 8) */ +#define BLE_RCB_INTR_MASKED_TX_FIFO_TRIGGER_Msk (0x100UL) /*!< BLE_RCB INTR_MASKED: TX_FIFO_TRIGGER (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_INTR_MASKED_TX_FIFO_NOT_FULL_Pos (9UL) /*!< BLE_RCB INTR_MASKED: TX_FIFO_NOT_FULL (Bit 9) */ +#define BLE_RCB_INTR_MASKED_TX_FIFO_NOT_FULL_Msk (0x200UL) /*!< BLE_RCB INTR_MASKED: TX_FIFO_NOT_FULL (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_INTR_MASKED_TX_FIFO_EMPTY_Pos (10UL) /*!< BLE_RCB INTR_MASKED: TX_FIFO_EMPTY (Bit 10) */ +#define BLE_RCB_INTR_MASKED_TX_FIFO_EMPTY_Msk (0x400UL) /*!< BLE_RCB INTR_MASKED: TX_FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASKED_TX_FIFO_OVERFLOW_Pos (11UL) /*!< BLE_RCB INTR_MASKED: TX_FIFO_OVERFLOW (Bit 11) */ +#define BLE_RCB_INTR_MASKED_TX_FIFO_OVERFLOW_Msk (0x800UL) /*!< BLE_RCB INTR_MASKED: TX_FIFO_OVERFLOW (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_INTR_MASKED_TX_FIFO_UNDERFLOW_Pos (12UL) /*!< BLE_RCB INTR_MASKED: TX_FIFO_UNDERFLOW (Bit 12) */ +#define BLE_RCB_INTR_MASKED_TX_FIFO_UNDERFLOW_Msk (0x1000UL) /*!< BLE_RCB INTR_MASKED: TX_FIFO_UNDERFLOW (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_INTR_MASKED_RX_FIFO_TRIGGER_Pos (16UL) /*!< BLE_RCB INTR_MASKED: RX_FIFO_TRIGGER (Bit 16) */ +#define BLE_RCB_INTR_MASKED_RX_FIFO_TRIGGER_Msk (0x10000UL) /*!< BLE_RCB INTR_MASKED: RX_FIFO_TRIGGER (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_INTR_MASKED_RX_FIFO_NOT_EMPTY_Pos (17UL) /*!< BLE_RCB INTR_MASKED: RX_FIFO_NOT_EMPTY (Bit 17) */ +#define BLE_RCB_INTR_MASKED_RX_FIFO_NOT_EMPTY_Msk (0x20000UL) /*!< BLE_RCB INTR_MASKED: RX_FIFO_NOT_EMPTY (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_INTR_MASKED_RX_FIFO_FULL_Pos (18UL) /*!< BLE_RCB INTR_MASKED: RX_FIFO_FULL (Bit 18) */ +#define BLE_RCB_INTR_MASKED_RX_FIFO_FULL_Msk (0x40000UL) /*!< BLE_RCB INTR_MASKED: RX_FIFO_FULL (Bitfield-Mask: 0x01) */ +#define BLE_RCB_INTR_MASKED_RX_FIFO_OVERFLOW_Pos (19UL) /*!< BLE_RCB INTR_MASKED: RX_FIFO_OVERFLOW (Bit 19) */ +#define BLE_RCB_INTR_MASKED_RX_FIFO_OVERFLOW_Msk (0x80000UL) /*!< BLE_RCB INTR_MASKED: RX_FIFO_OVERFLOW (Bitfield-Mask: 0x01)*/ +#define BLE_RCB_INTR_MASKED_RX_FIFO_UNDERFLOW_Pos (20UL) /*!< BLE_RCB INTR_MASKED: RX_FIFO_UNDERFLOW (Bit 20) */ +#define BLE_RCB_INTR_MASKED_RX_FIFO_UNDERFLOW_Msk (0x100000UL) /*!< BLE_RCB INTR_MASKED: RX_FIFO_UNDERFLOW (Bitfield-Mask: 0x01)*/ + + +/* ============================================== BLE_BLELL.COMMAND_REGISTER =============================================== */ +#define BLE_BLELL_COMMAND_REGISTER_COMMAND_Pos (0UL) /*!< BLE_BLELL COMMAND_REGISTER: COMMAND (Bit 0) */ +#define BLE_BLELL_COMMAND_REGISTER_COMMAND_Msk (0xffUL) /*!< BLE_BLELL COMMAND_REGISTER: COMMAND (Bitfield-Mask: 0xff) */ +/* ================================================= BLE_BLELL.EVENT_INTR ================================================== */ +#define BLE_BLELL_EVENT_INTR_ADV_INTR_Pos (0UL) /*!< BLE_BLELL EVENT_INTR: ADV_INTR (Bit 0) */ +#define BLE_BLELL_EVENT_INTR_ADV_INTR_Msk (0x1UL) /*!< BLE_BLELL EVENT_INTR: ADV_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_INTR_SCAN_INTR_Pos (1UL) /*!< BLE_BLELL EVENT_INTR: SCAN_INTR (Bit 1) */ +#define BLE_BLELL_EVENT_INTR_SCAN_INTR_Msk (0x2UL) /*!< BLE_BLELL EVENT_INTR: SCAN_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_INTR_INIT_INTR_Pos (2UL) /*!< BLE_BLELL EVENT_INTR: INIT_INTR (Bit 2) */ +#define BLE_BLELL_EVENT_INTR_INIT_INTR_Msk (0x4UL) /*!< BLE_BLELL EVENT_INTR: INIT_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_INTR_CONN_INTR_Pos (3UL) /*!< BLE_BLELL EVENT_INTR: CONN_INTR (Bit 3) */ +#define BLE_BLELL_EVENT_INTR_CONN_INTR_Msk (0x8UL) /*!< BLE_BLELL EVENT_INTR: CONN_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_INTR_SM_INTR_Pos (4UL) /*!< BLE_BLELL EVENT_INTR: SM_INTR (Bit 4) */ +#define BLE_BLELL_EVENT_INTR_SM_INTR_Msk (0x10UL) /*!< BLE_BLELL EVENT_INTR: SM_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_INTR_DSM_INTR_Pos (5UL) /*!< BLE_BLELL EVENT_INTR: DSM_INTR (Bit 5) */ +#define BLE_BLELL_EVENT_INTR_DSM_INTR_Msk (0x20UL) /*!< BLE_BLELL EVENT_INTR: DSM_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_INTR_ENC_INTR_Pos (6UL) /*!< BLE_BLELL EVENT_INTR: ENC_INTR (Bit 6) */ +#define BLE_BLELL_EVENT_INTR_ENC_INTR_Msk (0x40UL) /*!< BLE_BLELL EVENT_INTR: ENC_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_INTR_RSSI_RX_DONE_INTR_Pos (7UL) /*!< BLE_BLELL EVENT_INTR: RSSI_RX_DONE_INTR (Bit 7) */ +#define BLE_BLELL_EVENT_INTR_RSSI_RX_DONE_INTR_Msk (0x80UL) /*!< BLE_BLELL EVENT_INTR: RSSI_RX_DONE_INTR (Bitfield-Mask: 0x01)*/ +/* ================================================ BLE_BLELL.EVENT_ENABLE ================================================= */ +#define BLE_BLELL_EVENT_ENABLE_ADV_INT_EN_Pos (0UL) /*!< BLE_BLELL EVENT_ENABLE: ADV_INT_EN (Bit 0) */ +#define BLE_BLELL_EVENT_ENABLE_ADV_INT_EN_Msk (0x1UL) /*!< BLE_BLELL EVENT_ENABLE: ADV_INT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_ENABLE_SCN_INT_EN_Pos (1UL) /*!< BLE_BLELL EVENT_ENABLE: SCN_INT_EN (Bit 1) */ +#define BLE_BLELL_EVENT_ENABLE_SCN_INT_EN_Msk (0x2UL) /*!< BLE_BLELL EVENT_ENABLE: SCN_INT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_ENABLE_INIT_INT_EN_Pos (2UL) /*!< BLE_BLELL EVENT_ENABLE: INIT_INT_EN (Bit 2) */ +#define BLE_BLELL_EVENT_ENABLE_INIT_INT_EN_Msk (0x4UL) /*!< BLE_BLELL EVENT_ENABLE: INIT_INT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_ENABLE_CONN_INT_EN_Pos (3UL) /*!< BLE_BLELL EVENT_ENABLE: CONN_INT_EN (Bit 3) */ +#define BLE_BLELL_EVENT_ENABLE_CONN_INT_EN_Msk (0x8UL) /*!< BLE_BLELL EVENT_ENABLE: CONN_INT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_ENABLE_SM_INT_EN_Pos (4UL) /*!< BLE_BLELL EVENT_ENABLE: SM_INT_EN (Bit 4) */ +#define BLE_BLELL_EVENT_ENABLE_SM_INT_EN_Msk (0x10UL) /*!< BLE_BLELL EVENT_ENABLE: SM_INT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_ENABLE_DSM_INT_EN_Pos (5UL) /*!< BLE_BLELL EVENT_ENABLE: DSM_INT_EN (Bit 5) */ +#define BLE_BLELL_EVENT_ENABLE_DSM_INT_EN_Msk (0x20UL) /*!< BLE_BLELL EVENT_ENABLE: DSM_INT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_ENABLE_ENC_INT_EN_Pos (6UL) /*!< BLE_BLELL EVENT_ENABLE: ENC_INT_EN (Bit 6) */ +#define BLE_BLELL_EVENT_ENABLE_ENC_INT_EN_Msk (0x40UL) /*!< BLE_BLELL EVENT_ENABLE: ENC_INT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_EVENT_ENABLE_RSSI_RX_DONE_INT_EN_Pos (7UL) /*!< BLE_BLELL EVENT_ENABLE: RSSI_RX_DONE_INT_EN (Bit 7) */ +#define BLE_BLELL_EVENT_ENABLE_RSSI_RX_DONE_INT_EN_Msk (0x80UL) /*!< BLE_BLELL EVENT_ENABLE: RSSI_RX_DONE_INT_EN (Bitfield-Mask: 0x01)*/ +/* ================================================= BLE_BLELL.ADV_PARAMS ================================================== */ +#define BLE_BLELL_ADV_PARAMS_TX_ADDR_Pos (0UL) /*!< BLE_BLELL ADV_PARAMS: TX_ADDR (Bit 0) */ +#define BLE_BLELL_ADV_PARAMS_TX_ADDR_Msk (0x1UL) /*!< BLE_BLELL ADV_PARAMS: TX_ADDR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_PARAMS_ADV_TYPE_Pos (1UL) /*!< BLE_BLELL ADV_PARAMS: ADV_TYPE (Bit 1) */ +#define BLE_BLELL_ADV_PARAMS_ADV_TYPE_Msk (0x6UL) /*!< BLE_BLELL ADV_PARAMS: ADV_TYPE (Bitfield-Mask: 0x03) */ +#define BLE_BLELL_ADV_PARAMS_ADV_FILT_POLICY_Pos (3UL) /*!< BLE_BLELL ADV_PARAMS: ADV_FILT_POLICY (Bit 3) */ +#define BLE_BLELL_ADV_PARAMS_ADV_FILT_POLICY_Msk (0x18UL) /*!< BLE_BLELL ADV_PARAMS: ADV_FILT_POLICY (Bitfield-Mask: 0x03)*/ +#define BLE_BLELL_ADV_PARAMS_ADV_CHANNEL_MAP_Pos (5UL) /*!< BLE_BLELL ADV_PARAMS: ADV_CHANNEL_MAP (Bit 5) */ +#define BLE_BLELL_ADV_PARAMS_ADV_CHANNEL_MAP_Msk (0xe0UL) /*!< BLE_BLELL ADV_PARAMS: ADV_CHANNEL_MAP (Bitfield-Mask: 0x07)*/ +#define BLE_BLELL_ADV_PARAMS_RX_ADDR_Pos (8UL) /*!< BLE_BLELL ADV_PARAMS: RX_ADDR (Bit 8) */ +#define BLE_BLELL_ADV_PARAMS_RX_ADDR_Msk (0x100UL) /*!< BLE_BLELL ADV_PARAMS: RX_ADDR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_PARAMS_ADV_LOW_DUTY_CYCLE_Pos (10UL) /*!< BLE_BLELL ADV_PARAMS: ADV_LOW_DUTY_CYCLE (Bit 10) */ +#define BLE_BLELL_ADV_PARAMS_ADV_LOW_DUTY_CYCLE_Msk (0x400UL) /*!< BLE_BLELL ADV_PARAMS: ADV_LOW_DUTY_CYCLE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_PARAMS_INITA_RPA_CHECK_Pos (11UL) /*!< BLE_BLELL ADV_PARAMS: INITA_RPA_CHECK (Bit 11) */ +#define BLE_BLELL_ADV_PARAMS_INITA_RPA_CHECK_Msk (0x800UL) /*!< BLE_BLELL ADV_PARAMS: INITA_RPA_CHECK (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_PARAMS_TX_ADDR_PRIV_Pos (12UL) /*!< BLE_BLELL ADV_PARAMS: TX_ADDR_PRIV (Bit 12) */ +#define BLE_BLELL_ADV_PARAMS_TX_ADDR_PRIV_Msk (0x1000UL) /*!< BLE_BLELL ADV_PARAMS: TX_ADDR_PRIV (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_PARAMS_ADV_RCV_IA_IN_PRIV_Pos (13UL) /*!< BLE_BLELL ADV_PARAMS: ADV_RCV_IA_IN_PRIV (Bit 13) */ +#define BLE_BLELL_ADV_PARAMS_ADV_RCV_IA_IN_PRIV_Msk (0x2000UL) /*!< BLE_BLELL ADV_PARAMS: ADV_RCV_IA_IN_PRIV (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_PARAMS_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV_Pos (14UL) /*!< BLE_BLELL ADV_PARAMS: ADV_RPT_PEER_NRPA_ADDR_IN_PRIV (Bit 14)*/ +#define BLE_BLELL_ADV_PARAMS_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV_Msk (0x4000UL) /*!< BLE_BLELL ADV_PARAMS: ADV_RPT_PEER_NRPA_ADDR_IN_PRIV (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_PARAMS_RCV_TX_ADDR_Pos (15UL) /*!< BLE_BLELL ADV_PARAMS: RCV_TX_ADDR (Bit 15) */ +#define BLE_BLELL_ADV_PARAMS_RCV_TX_ADDR_Msk (0x8000UL) /*!< BLE_BLELL ADV_PARAMS: RCV_TX_ADDR (Bitfield-Mask: 0x01) */ +/* ============================================ BLE_BLELL.ADV_INTERVAL_TIMEOUT ============================================= */ +#define BLE_BLELL_ADV_INTERVAL_TIMEOUT_ADV_INTERVAL_Pos (0UL) /*!< BLE_BLELL ADV_INTERVAL_TIMEOUT: ADV_INTERVAL (Bit 0) */ +#define BLE_BLELL_ADV_INTERVAL_TIMEOUT_ADV_INTERVAL_Msk (0x7fffUL) /*!< BLE_BLELL ADV_INTERVAL_TIMEOUT: ADV_INTERVAL (Bitfield-Mask: 0x7fff)*/ +/* ================================================== BLE_BLELL.ADV_INTR =================================================== */ +#define BLE_BLELL_ADV_INTR_ADV_STRT_INTR_Pos (0UL) /*!< BLE_BLELL ADV_INTR: ADV_STRT_INTR (Bit 0) */ +#define BLE_BLELL_ADV_INTR_ADV_STRT_INTR_Msk (0x1UL) /*!< BLE_BLELL ADV_INTR: ADV_STRT_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_INTR_ADV_CLOSE_INTR_Pos (1UL) /*!< BLE_BLELL ADV_INTR: ADV_CLOSE_INTR (Bit 1) */ +#define BLE_BLELL_ADV_INTR_ADV_CLOSE_INTR_Msk (0x2UL) /*!< BLE_BLELL ADV_INTR: ADV_CLOSE_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_INTR_ADV_TX_INTR_Pos (2UL) /*!< BLE_BLELL ADV_INTR: ADV_TX_INTR (Bit 2) */ +#define BLE_BLELL_ADV_INTR_ADV_TX_INTR_Msk (0x4UL) /*!< BLE_BLELL ADV_INTR: ADV_TX_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_INTR_SCAN_RSP_TX_INTR_Pos (3UL) /*!< BLE_BLELL ADV_INTR: SCAN_RSP_TX_INTR (Bit 3) */ +#define BLE_BLELL_ADV_INTR_SCAN_RSP_TX_INTR_Msk (0x8UL) /*!< BLE_BLELL ADV_INTR: SCAN_RSP_TX_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_INTR_Pos (4UL) /*!< BLE_BLELL ADV_INTR: SCAN_REQ_RX_INTR (Bit 4) */ +#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_INTR_Msk (0x10UL) /*!< BLE_BLELL ADV_INTR: SCAN_REQ_RX_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_INTR_CONN_REQ_RX_INTR_Pos (5UL) /*!< BLE_BLELL ADV_INTR: CONN_REQ_RX_INTR (Bit 5) */ +#define BLE_BLELL_ADV_INTR_CONN_REQ_RX_INTR_Msk (0x20UL) /*!< BLE_BLELL ADV_INTR: CONN_REQ_RX_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_INTR_SLV_CONNECTED_Pos (6UL) /*!< BLE_BLELL ADV_INTR: SLV_CONNECTED (Bit 6) */ +#define BLE_BLELL_ADV_INTR_SLV_CONNECTED_Msk (0x40UL) /*!< BLE_BLELL ADV_INTR: SLV_CONNECTED (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_INTR_ADV_TIMEOUT_Pos (7UL) /*!< BLE_BLELL ADV_INTR: ADV_TIMEOUT (Bit 7) */ +#define BLE_BLELL_ADV_INTR_ADV_TIMEOUT_Msk (0x80UL) /*!< BLE_BLELL ADV_INTR: ADV_TIMEOUT (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_INTR_ADV_ON_Pos (8UL) /*!< BLE_BLELL ADV_INTR: ADV_ON (Bit 8) */ +#define BLE_BLELL_ADV_INTR_ADV_ON_Msk (0x100UL) /*!< BLE_BLELL ADV_INTR: ADV_ON (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_INTR_SLV_CONN_PEER_RPA_UNMCH_INTR_Pos (9UL) /*!< BLE_BLELL ADV_INTR: SLV_CONN_PEER_RPA_UNMCH_INTR (Bit 9)*/ +#define BLE_BLELL_ADV_INTR_SLV_CONN_PEER_RPA_UNMCH_INTR_Msk (0x200UL) /*!< BLE_BLELL ADV_INTR: SLV_CONN_PEER_RPA_UNMCH_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR_Pos (10UL) /*!< BLE_BLELL ADV_INTR: SCAN_REQ_RX_PEER_RPA_UNMCH_INTR (Bit 10)*/ +#define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR_Msk (0x400UL) /*!< BLE_BLELL ADV_INTR: SCAN_REQ_RX_PEER_RPA_UNMCH_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_INTR_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos (11UL) /*!< BLE_BLELL ADV_INTR: INIT_ADDR_MATCH_PRIV_MISMATCH_INTR (Bit 11)*/ +#define BLE_BLELL_ADV_INTR_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk (0x800UL) /*!< BLE_BLELL ADV_INTR: INIT_ADDR_MATCH_PRIV_MISMATCH_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_INTR_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos (12UL) /*!< BLE_BLELL ADV_INTR: SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR (Bit 12)*/ +#define BLE_BLELL_ADV_INTR_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk (0x1000UL) /*!< BLE_BLELL ADV_INTR: SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR (Bitfield-Mask: 0x01)*/ +/* ============================================== BLE_BLELL.ADV_NEXT_INSTANT =============================================== */ +#define BLE_BLELL_ADV_NEXT_INSTANT_ADV_NEXT_INSTANT_Pos (0UL) /*!< BLE_BLELL ADV_NEXT_INSTANT: ADV_NEXT_INSTANT (Bit 0) */ +#define BLE_BLELL_ADV_NEXT_INSTANT_ADV_NEXT_INSTANT_Msk (0xffffUL) /*!< BLE_BLELL ADV_NEXT_INSTANT: ADV_NEXT_INSTANT (Bitfield-Mask: 0xffff)*/ +/* ================================================ BLE_BLELL.SCAN_INTERVAL ================================================ */ +#define BLE_BLELL_SCAN_INTERVAL_SCAN_INTERVAL_Pos (0UL) /*!< BLE_BLELL SCAN_INTERVAL: SCAN_INTERVAL (Bit 0) */ +#define BLE_BLELL_SCAN_INTERVAL_SCAN_INTERVAL_Msk (0xffffUL) /*!< BLE_BLELL SCAN_INTERVAL: SCAN_INTERVAL (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.SCAN_WINDOW ================================================= */ +#define BLE_BLELL_SCAN_WINDOW_SCAN_WINDOW_Pos (0UL) /*!< BLE_BLELL SCAN_WINDOW: SCAN_WINDOW (Bit 0) */ +#define BLE_BLELL_SCAN_WINDOW_SCAN_WINDOW_Msk (0xffffUL) /*!< BLE_BLELL SCAN_WINDOW: SCAN_WINDOW (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.SCAN_PARAM ================================================== */ +#define BLE_BLELL_SCAN_PARAM_TX_ADDR_Pos (0UL) /*!< BLE_BLELL SCAN_PARAM: TX_ADDR (Bit 0) */ +#define BLE_BLELL_SCAN_PARAM_TX_ADDR_Msk (0x1UL) /*!< BLE_BLELL SCAN_PARAM: TX_ADDR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_SCAN_PARAM_SCAN_TYPE_Pos (1UL) /*!< BLE_BLELL SCAN_PARAM: SCAN_TYPE (Bit 1) */ +#define BLE_BLELL_SCAN_PARAM_SCAN_TYPE_Msk (0x6UL) /*!< BLE_BLELL SCAN_PARAM: SCAN_TYPE (Bitfield-Mask: 0x03) */ +#define BLE_BLELL_SCAN_PARAM_SCAN_FILT_POLICY_Pos (3UL) /*!< BLE_BLELL SCAN_PARAM: SCAN_FILT_POLICY (Bit 3) */ +#define BLE_BLELL_SCAN_PARAM_SCAN_FILT_POLICY_Msk (0x18UL) /*!< BLE_BLELL SCAN_PARAM: SCAN_FILT_POLICY (Bitfield-Mask: 0x03)*/ +#define BLE_BLELL_SCAN_PARAM_DUP_FILT_EN_Pos (5UL) /*!< BLE_BLELL SCAN_PARAM: DUP_FILT_EN (Bit 5) */ +#define BLE_BLELL_SCAN_PARAM_DUP_FILT_EN_Msk (0x20UL) /*!< BLE_BLELL SCAN_PARAM: DUP_FILT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_SCAN_PARAM_DUP_FILT_CHK_ADV_DIR_Pos (6UL) /*!< BLE_BLELL SCAN_PARAM: DUP_FILT_CHK_ADV_DIR (Bit 6) */ +#define BLE_BLELL_SCAN_PARAM_DUP_FILT_CHK_ADV_DIR_Msk (0x40UL) /*!< BLE_BLELL SCAN_PARAM: DUP_FILT_CHK_ADV_DIR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_PARAM_SCAN_RSP_ADVA_CHECK_Pos (7UL) /*!< BLE_BLELL SCAN_PARAM: SCAN_RSP_ADVA_CHECK (Bit 7) */ +#define BLE_BLELL_SCAN_PARAM_SCAN_RSP_ADVA_CHECK_Msk (0x80UL) /*!< BLE_BLELL SCAN_PARAM: SCAN_RSP_ADVA_CHECK (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_PARAM_SCAN_RCV_IA_IN_PRIV_Pos (8UL) /*!< BLE_BLELL SCAN_PARAM: SCAN_RCV_IA_IN_PRIV (Bit 8) */ +#define BLE_BLELL_SCAN_PARAM_SCAN_RCV_IA_IN_PRIV_Msk (0x100UL) /*!< BLE_BLELL SCAN_PARAM: SCAN_RCV_IA_IN_PRIV (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_PARAM_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV_Pos (9UL) /*!< BLE_BLELL SCAN_PARAM: SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV (Bit 9)*/ +#define BLE_BLELL_SCAN_PARAM_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV_Msk (0x200UL) /*!< BLE_BLELL SCAN_PARAM: SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV (Bitfield-Mask: 0x01)*/ +/* ================================================== BLE_BLELL.SCAN_INTR ================================================== */ +#define BLE_BLELL_SCAN_INTR_SCAN_STRT_INTR_Pos (0UL) /*!< BLE_BLELL SCAN_INTR: SCAN_STRT_INTR (Bit 0) */ +#define BLE_BLELL_SCAN_INTR_SCAN_STRT_INTR_Msk (0x1UL) /*!< BLE_BLELL SCAN_INTR: SCAN_STRT_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_SCAN_INTR_SCAN_CLOSE_INTR_Pos (1UL) /*!< BLE_BLELL SCAN_INTR: SCAN_CLOSE_INTR (Bit 1) */ +#define BLE_BLELL_SCAN_INTR_SCAN_CLOSE_INTR_Msk (0x2UL) /*!< BLE_BLELL SCAN_INTR: SCAN_CLOSE_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_INTR_SCAN_TX_INTR_Pos (2UL) /*!< BLE_BLELL SCAN_INTR: SCAN_TX_INTR (Bit 2) */ +#define BLE_BLELL_SCAN_INTR_SCAN_TX_INTR_Msk (0x4UL) /*!< BLE_BLELL SCAN_INTR: SCAN_TX_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_SCAN_INTR_ADV_RX_INTR_Pos (3UL) /*!< BLE_BLELL SCAN_INTR: ADV_RX_INTR (Bit 3) */ +#define BLE_BLELL_SCAN_INTR_ADV_RX_INTR_Msk (0x8UL) /*!< BLE_BLELL SCAN_INTR: ADV_RX_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_SCAN_INTR_SCAN_RSP_RX_INTR_Pos (4UL) /*!< BLE_BLELL SCAN_INTR: SCAN_RSP_RX_INTR (Bit 4) */ +#define BLE_BLELL_SCAN_INTR_SCAN_RSP_RX_INTR_Msk (0x10UL) /*!< BLE_BLELL SCAN_INTR: SCAN_RSP_RX_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_INTR_ADV_RX_PEER_RPA_UNMCH_INTR_Pos (5UL) /*!< BLE_BLELL SCAN_INTR: ADV_RX_PEER_RPA_UNMCH_INTR (Bit 5) */ +#define BLE_BLELL_SCAN_INTR_ADV_RX_PEER_RPA_UNMCH_INTR_Msk (0x20UL) /*!< BLE_BLELL SCAN_INTR: ADV_RX_PEER_RPA_UNMCH_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_INTR_ADV_RX_SELF_RPA_UNMCH_INTR_Pos (6UL) /*!< BLE_BLELL SCAN_INTR: ADV_RX_SELF_RPA_UNMCH_INTR (Bit 6) */ +#define BLE_BLELL_SCAN_INTR_ADV_RX_SELF_RPA_UNMCH_INTR_Msk (0x40UL) /*!< BLE_BLELL SCAN_INTR: ADV_RX_SELF_RPA_UNMCH_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_INTR_SCANA_TX_ADDR_NOT_SET_INTR_Pos (7UL) /*!< BLE_BLELL SCAN_INTR: SCANA_TX_ADDR_NOT_SET_INTR (Bit 7) */ +#define BLE_BLELL_SCAN_INTR_SCANA_TX_ADDR_NOT_SET_INTR_Msk (0x80UL) /*!< BLE_BLELL SCAN_INTR: SCANA_TX_ADDR_NOT_SET_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_INTR_SCAN_ON_Pos (8UL) /*!< BLE_BLELL SCAN_INTR: SCAN_ON (Bit 8) */ +#define BLE_BLELL_SCAN_INTR_SCAN_ON_Msk (0x100UL) /*!< BLE_BLELL SCAN_INTR: SCAN_ON (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_SCAN_INTR_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos (9UL) /*!< BLE_BLELL SCAN_INTR: PEER_ADDR_MATCH_PRIV_MISMATCH_INTR (Bit 9)*/ +#define BLE_BLELL_SCAN_INTR_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk (0x200UL) /*!< BLE_BLELL SCAN_INTR: PEER_ADDR_MATCH_PRIV_MISMATCH_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_INTR_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos (10UL) /*!< BLE_BLELL SCAN_INTR: SELF_ADDR_MATCH_PRIV_MISMATCH_INTR (Bit 10)*/ +#define BLE_BLELL_SCAN_INTR_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk (0x400UL) /*!< BLE_BLELL SCAN_INTR: SELF_ADDR_MATCH_PRIV_MISMATCH_INTR (Bitfield-Mask: 0x01)*/ +/* ============================================== BLE_BLELL.SCAN_NEXT_INSTANT ============================================== */ +#define BLE_BLELL_SCAN_NEXT_INSTANT_NEXT_SCAN_INSTANT_Pos (0UL) /*!< BLE_BLELL SCAN_NEXT_INSTANT: NEXT_SCAN_INSTANT (Bit 0) */ +#define BLE_BLELL_SCAN_NEXT_INSTANT_NEXT_SCAN_INSTANT_Msk (0xffffUL) /*!< BLE_BLELL SCAN_NEXT_INSTANT: NEXT_SCAN_INSTANT (Bitfield-Mask: 0xffff)*/ +/* ================================================ BLE_BLELL.INIT_INTERVAL ================================================ */ +#define BLE_BLELL_INIT_INTERVAL_INIT_SCAN_INTERVAL_Pos (0UL) /*!< BLE_BLELL INIT_INTERVAL: INIT_SCAN_INTERVAL (Bit 0) */ +#define BLE_BLELL_INIT_INTERVAL_INIT_SCAN_INTERVAL_Msk (0xffffUL) /*!< BLE_BLELL INIT_INTERVAL: INIT_SCAN_INTERVAL (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.INIT_WINDOW ================================================= */ +#define BLE_BLELL_INIT_WINDOW_INIT_SCAN_WINDOW_Pos (0UL) /*!< BLE_BLELL INIT_WINDOW: INIT_SCAN_WINDOW (Bit 0) */ +#define BLE_BLELL_INIT_WINDOW_INIT_SCAN_WINDOW_Msk (0xffffUL) /*!< BLE_BLELL INIT_WINDOW: INIT_SCAN_WINDOW (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.INIT_PARAM ================================================== */ +#define BLE_BLELL_INIT_PARAM_TX_ADDR_Pos (0UL) /*!< BLE_BLELL INIT_PARAM: TX_ADDR (Bit 0) */ +#define BLE_BLELL_INIT_PARAM_TX_ADDR_Msk (0x1UL) /*!< BLE_BLELL INIT_PARAM: TX_ADDR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_INIT_PARAM_RX_ADDR__RX_TX_ADDR_Pos (1UL) /*!< BLE_BLELL INIT_PARAM: RX_ADDR__RX_TX_ADDR (Bit 1) */ +#define BLE_BLELL_INIT_PARAM_RX_ADDR__RX_TX_ADDR_Msk (0x2UL) /*!< BLE_BLELL INIT_PARAM: RX_ADDR__RX_TX_ADDR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_PARAM_INIT_FILT_POLICY_Pos (3UL) /*!< BLE_BLELL INIT_PARAM: INIT_FILT_POLICY (Bit 3) */ +#define BLE_BLELL_INIT_PARAM_INIT_FILT_POLICY_Msk (0x8UL) /*!< BLE_BLELL INIT_PARAM: INIT_FILT_POLICY (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_PARAM_INIT_RCV_IA_IN_PRIV_Pos (4UL) /*!< BLE_BLELL INIT_PARAM: INIT_RCV_IA_IN_PRIV (Bit 4) */ +#define BLE_BLELL_INIT_PARAM_INIT_RCV_IA_IN_PRIV_Msk (0x10UL) /*!< BLE_BLELL INIT_PARAM: INIT_RCV_IA_IN_PRIV (Bitfield-Mask: 0x01)*/ +/* ================================================== BLE_BLELL.INIT_INTR ================================================== */ +#define BLE_BLELL_INIT_INTR_INIT_INTERVAL_EXPIRE_INTR_Pos (0UL) /*!< BLE_BLELL INIT_INTR: INIT_INTERVAL_EXPIRE_INTR (Bit 0) */ +#define BLE_BLELL_INIT_INTR_INIT_INTERVAL_EXPIRE_INTR_Msk (0x1UL) /*!< BLE_BLELL INIT_INTR: INIT_INTERVAL_EXPIRE_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_INTR_INIT_CLOSE_WINDOW_INR_Pos (1UL) /*!< BLE_BLELL INIT_INTR: INIT_CLOSE_WINDOW_INR (Bit 1) */ +#define BLE_BLELL_INIT_INTR_INIT_CLOSE_WINDOW_INR_Msk (0x2UL) /*!< BLE_BLELL INIT_INTR: INIT_CLOSE_WINDOW_INR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_INTR_INIT_TX_START_INTR_Pos (2UL) /*!< BLE_BLELL INIT_INTR: INIT_TX_START_INTR (Bit 2) */ +#define BLE_BLELL_INIT_INTR_INIT_TX_START_INTR_Msk (0x4UL) /*!< BLE_BLELL INIT_INTR: INIT_TX_START_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_INTR_MASTER_CONN_CREATED_Pos (4UL) /*!< BLE_BLELL INIT_INTR: MASTER_CONN_CREATED (Bit 4) */ +#define BLE_BLELL_INIT_INTR_MASTER_CONN_CREATED_Msk (0x10UL) /*!< BLE_BLELL INIT_INTR: MASTER_CONN_CREATED (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_INTR_ADV_RX_SELF_ADDR_UNMCH_INTR_Pos (5UL) /*!< BLE_BLELL INIT_INTR: ADV_RX_SELF_ADDR_UNMCH_INTR (Bit 5)*/ +#define BLE_BLELL_INIT_INTR_ADV_RX_SELF_ADDR_UNMCH_INTR_Msk (0x20UL) /*!< BLE_BLELL INIT_INTR: ADV_RX_SELF_ADDR_UNMCH_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_INTR_ADV_RX_PEER_ADDR_UNMCH_INTR_Pos (6UL) /*!< BLE_BLELL INIT_INTR: ADV_RX_PEER_ADDR_UNMCH_INTR (Bit 6)*/ +#define BLE_BLELL_INIT_INTR_ADV_RX_PEER_ADDR_UNMCH_INTR_Msk (0x40UL) /*!< BLE_BLELL INIT_INTR: ADV_RX_PEER_ADDR_UNMCH_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_INTR_INITA_TX_ADDR_NOT_SET_INTR_Pos (7UL) /*!< BLE_BLELL INIT_INTR: INITA_TX_ADDR_NOT_SET_INTR (Bit 7) */ +#define BLE_BLELL_INIT_INTR_INITA_TX_ADDR_NOT_SET_INTR_Msk (0x80UL) /*!< BLE_BLELL INIT_INTR: INITA_TX_ADDR_NOT_SET_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_INTR_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos (8UL) /*!< BLE_BLELL INIT_INTR: INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR (Bit 8)*/ +#define BLE_BLELL_INIT_INTR_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk (0x100UL) /*!< BLE_BLELL INIT_INTR: INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_INTR_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos (9UL) /*!< BLE_BLELL INIT_INTR: INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR (Bit 9)*/ +#define BLE_BLELL_INIT_INTR_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk (0x200UL) /*!< BLE_BLELL INIT_INTR: INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR (Bitfield-Mask: 0x01)*/ +/* ============================================== BLE_BLELL.INIT_NEXT_INSTANT ============================================== */ +#define BLE_BLELL_INIT_NEXT_INSTANT_INIT_NEXT_INSTANT_Pos (0UL) /*!< BLE_BLELL INIT_NEXT_INSTANT: INIT_NEXT_INSTANT (Bit 0) */ +#define BLE_BLELL_INIT_NEXT_INSTANT_INIT_NEXT_INSTANT_Msk (0xffffUL) /*!< BLE_BLELL INIT_NEXT_INSTANT: INIT_NEXT_INSTANT (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_BLELL.DEVICE_RAND_ADDR_L ============================================== */ +#define BLE_BLELL_DEVICE_RAND_ADDR_L_DEVICE_RAND_ADDR_L_Pos (0UL) /*!< BLE_BLELL DEVICE_RAND_ADDR_L: DEVICE_RAND_ADDR_L (Bit 0)*/ +#define BLE_BLELL_DEVICE_RAND_ADDR_L_DEVICE_RAND_ADDR_L_Msk (0xffffUL) /*!< BLE_BLELL DEVICE_RAND_ADDR_L: DEVICE_RAND_ADDR_L (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_BLELL.DEVICE_RAND_ADDR_M ============================================== */ +#define BLE_BLELL_DEVICE_RAND_ADDR_M_DEVICE_RAND_ADDR_M_Pos (0UL) /*!< BLE_BLELL DEVICE_RAND_ADDR_M: DEVICE_RAND_ADDR_M (Bit 0)*/ +#define BLE_BLELL_DEVICE_RAND_ADDR_M_DEVICE_RAND_ADDR_M_Msk (0xffffUL) /*!< BLE_BLELL DEVICE_RAND_ADDR_M: DEVICE_RAND_ADDR_M (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_BLELL.DEVICE_RAND_ADDR_H ============================================== */ +#define BLE_BLELL_DEVICE_RAND_ADDR_H_DEVICE_RAND_ADDR_H_Pos (0UL) /*!< BLE_BLELL DEVICE_RAND_ADDR_H: DEVICE_RAND_ADDR_H (Bit 0)*/ +#define BLE_BLELL_DEVICE_RAND_ADDR_H_DEVICE_RAND_ADDR_H_Msk (0xffffUL) /*!< BLE_BLELL DEVICE_RAND_ADDR_H: DEVICE_RAND_ADDR_H (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.PEER_ADDR_L ================================================= */ +#define BLE_BLELL_PEER_ADDR_L_PEER_ADDR_L_Pos (0UL) /*!< BLE_BLELL PEER_ADDR_L: PEER_ADDR_L (Bit 0) */ +#define BLE_BLELL_PEER_ADDR_L_PEER_ADDR_L_Msk (0xffffUL) /*!< BLE_BLELL PEER_ADDR_L: PEER_ADDR_L (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.PEER_ADDR_M ================================================= */ +#define BLE_BLELL_PEER_ADDR_M_PEER_ADDR_M_Pos (0UL) /*!< BLE_BLELL PEER_ADDR_M: PEER_ADDR_M (Bit 0) */ +#define BLE_BLELL_PEER_ADDR_M_PEER_ADDR_M_Msk (0xffffUL) /*!< BLE_BLELL PEER_ADDR_M: PEER_ADDR_M (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.PEER_ADDR_H ================================================= */ +#define BLE_BLELL_PEER_ADDR_H_PEER_ADDR_H_Pos (0UL) /*!< BLE_BLELL PEER_ADDR_H: PEER_ADDR_H (Bit 0) */ +#define BLE_BLELL_PEER_ADDR_H_PEER_ADDR_H_Msk (0xffffUL) /*!< BLE_BLELL PEER_ADDR_H: PEER_ADDR_H (Bitfield-Mask: 0xffff)*/ +/* ================================================ BLE_BLELL.WL_ADDR_TYPE ================================================= */ +#define BLE_BLELL_WL_ADDR_TYPE_WL_ADDR_TYPE_Pos (0UL) /*!< BLE_BLELL WL_ADDR_TYPE: WL_ADDR_TYPE (Bit 0) */ +#define BLE_BLELL_WL_ADDR_TYPE_WL_ADDR_TYPE_Msk (0xffffUL) /*!< BLE_BLELL WL_ADDR_TYPE: WL_ADDR_TYPE (Bitfield-Mask: 0xffff)*/ +/* ================================================== BLE_BLELL.WL_ENABLE ================================================== */ +#define BLE_BLELL_WL_ENABLE_WL_ENABLE_Pos (0UL) /*!< BLE_BLELL WL_ENABLE: WL_ENABLE (Bit 0) */ +#define BLE_BLELL_WL_ENABLE_WL_ENABLE_Msk (0xffffUL) /*!< BLE_BLELL WL_ENABLE: WL_ENABLE (Bitfield-Mask: 0xffff) */ +/* =========================================== BLE_BLELL.TRANSMIT_WINDOW_OFFSET ============================================ */ +#define BLE_BLELL_TRANSMIT_WINDOW_OFFSET_TX_WINDOW_OFFSET_Pos (0UL) /*!< BLE_BLELL TRANSMIT_WINDOW_OFFSET: TX_WINDOW_OFFSET (Bit 0)*/ +#define BLE_BLELL_TRANSMIT_WINDOW_OFFSET_TX_WINDOW_OFFSET_Msk (0xffffUL) /*!< BLE_BLELL TRANSMIT_WINDOW_OFFSET: TX_WINDOW_OFFSET (Bitfield-Mask: 0xffff)*/ +/* ============================================ BLE_BLELL.TRANSMIT_WINDOW_SIZE ============================================= */ +#define BLE_BLELL_TRANSMIT_WINDOW_SIZE_TX_WINDOW_SIZE_Pos (0UL) /*!< BLE_BLELL TRANSMIT_WINDOW_SIZE: TX_WINDOW_SIZE (Bit 0) */ +#define BLE_BLELL_TRANSMIT_WINDOW_SIZE_TX_WINDOW_SIZE_Msk (0xffUL) /*!< BLE_BLELL TRANSMIT_WINDOW_SIZE: TX_WINDOW_SIZE (Bitfield-Mask: 0xff)*/ +/* ============================================== BLE_BLELL.DATA_CHANNELS_L0 =============================================== */ +#define BLE_BLELL_DATA_CHANNELS_L0_DATA_CHANNELS_L0_Pos (0UL) /*!< BLE_BLELL DATA_CHANNELS_L0: DATA_CHANNELS_L0 (Bit 0) */ +#define BLE_BLELL_DATA_CHANNELS_L0_DATA_CHANNELS_L0_Msk (0xffffUL) /*!< BLE_BLELL DATA_CHANNELS_L0: DATA_CHANNELS_L0 (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_BLELL.DATA_CHANNELS_M0 =============================================== */ +#define BLE_BLELL_DATA_CHANNELS_M0_DATA_CHANNELS_M0_Pos (0UL) /*!< BLE_BLELL DATA_CHANNELS_M0: DATA_CHANNELS_M0 (Bit 0) */ +#define BLE_BLELL_DATA_CHANNELS_M0_DATA_CHANNELS_M0_Msk (0xffffUL) /*!< BLE_BLELL DATA_CHANNELS_M0: DATA_CHANNELS_M0 (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_BLELL.DATA_CHANNELS_H0 =============================================== */ +#define BLE_BLELL_DATA_CHANNELS_H0_DATA_CHANNELS_H0_Pos (0UL) /*!< BLE_BLELL DATA_CHANNELS_H0: DATA_CHANNELS_H0 (Bit 0) */ +#define BLE_BLELL_DATA_CHANNELS_H0_DATA_CHANNELS_H0_Msk (0x1fUL) /*!< BLE_BLELL DATA_CHANNELS_H0: DATA_CHANNELS_H0 (Bitfield-Mask: 0x1f)*/ +/* ============================================== BLE_BLELL.DATA_CHANNELS_L1 =============================================== */ +#define BLE_BLELL_DATA_CHANNELS_L1_DATA_CHANNELS_L1_Pos (0UL) /*!< BLE_BLELL DATA_CHANNELS_L1: DATA_CHANNELS_L1 (Bit 0) */ +#define BLE_BLELL_DATA_CHANNELS_L1_DATA_CHANNELS_L1_Msk (0xffffUL) /*!< BLE_BLELL DATA_CHANNELS_L1: DATA_CHANNELS_L1 (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_BLELL.DATA_CHANNELS_M1 =============================================== */ +#define BLE_BLELL_DATA_CHANNELS_M1_DATA_CHANNELS_M1_Pos (0UL) /*!< BLE_BLELL DATA_CHANNELS_M1: DATA_CHANNELS_M1 (Bit 0) */ +#define BLE_BLELL_DATA_CHANNELS_M1_DATA_CHANNELS_M1_Msk (0xffffUL) /*!< BLE_BLELL DATA_CHANNELS_M1: DATA_CHANNELS_M1 (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_BLELL.DATA_CHANNELS_H1 =============================================== */ +#define BLE_BLELL_DATA_CHANNELS_H1_DATA_CHANNELS_H1_Pos (0UL) /*!< BLE_BLELL DATA_CHANNELS_H1: DATA_CHANNELS_H1 (Bit 0) */ +#define BLE_BLELL_DATA_CHANNELS_H1_DATA_CHANNELS_H1_Msk (0x1fUL) /*!< BLE_BLELL DATA_CHANNELS_H1: DATA_CHANNELS_H1 (Bitfield-Mask: 0x1f)*/ +/* ================================================== BLE_BLELL.CONN_INTR ================================================== */ +#define BLE_BLELL_CONN_INTR_CONN_CLOSED_Pos (0UL) /*!< BLE_BLELL CONN_INTR: CONN_CLOSED (Bit 0) */ +#define BLE_BLELL_CONN_INTR_CONN_CLOSED_Msk (0x1UL) /*!< BLE_BLELL CONN_INTR: CONN_CLOSED (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CONN_INTR_CONN_ESTB_Pos (1UL) /*!< BLE_BLELL CONN_INTR: CONN_ESTB (Bit 1) */ +#define BLE_BLELL_CONN_INTR_CONN_ESTB_Msk (0x2UL) /*!< BLE_BLELL CONN_INTR: CONN_ESTB (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CONN_INTR_MAP_UPDT_DONE_Pos (2UL) /*!< BLE_BLELL CONN_INTR: MAP_UPDT_DONE (Bit 2) */ +#define BLE_BLELL_CONN_INTR_MAP_UPDT_DONE_Msk (0x4UL) /*!< BLE_BLELL CONN_INTR: MAP_UPDT_DONE (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CONN_INTR_START_CE_Pos (3UL) /*!< BLE_BLELL CONN_INTR: START_CE (Bit 3) */ +#define BLE_BLELL_CONN_INTR_START_CE_Msk (0x8UL) /*!< BLE_BLELL CONN_INTR: START_CE (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CONN_INTR_CLOSE_CE_Pos (4UL) /*!< BLE_BLELL CONN_INTR: CLOSE_CE (Bit 4) */ +#define BLE_BLELL_CONN_INTR_CLOSE_CE_Msk (0x10UL) /*!< BLE_BLELL CONN_INTR: CLOSE_CE (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CONN_INTR_CE_TX_ACK_Pos (5UL) /*!< BLE_BLELL CONN_INTR: CE_TX_ACK (Bit 5) */ +#define BLE_BLELL_CONN_INTR_CE_TX_ACK_Msk (0x20UL) /*!< BLE_BLELL CONN_INTR: CE_TX_ACK (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CONN_INTR_CE_RX_Pos (6UL) /*!< BLE_BLELL CONN_INTR: CE_RX (Bit 6) */ +#define BLE_BLELL_CONN_INTR_CE_RX_Msk (0x40UL) /*!< BLE_BLELL CONN_INTR: CE_RX (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CONN_INTR_CON_UPDT_DONE_Pos (7UL) /*!< BLE_BLELL CONN_INTR: CON_UPDT_DONE (Bit 7) */ +#define BLE_BLELL_CONN_INTR_CON_UPDT_DONE_Msk (0x80UL) /*!< BLE_BLELL CONN_INTR: CON_UPDT_DONE (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CONN_INTR_DISCON_STATUS_Pos (8UL) /*!< BLE_BLELL CONN_INTR: DISCON_STATUS (Bit 8) */ +#define BLE_BLELL_CONN_INTR_DISCON_STATUS_Msk (0x700UL) /*!< BLE_BLELL CONN_INTR: DISCON_STATUS (Bitfield-Mask: 0x07) */ +#define BLE_BLELL_CONN_INTR_RX_PDU_STATUS_Pos (11UL) /*!< BLE_BLELL CONN_INTR: RX_PDU_STATUS (Bit 11) */ +#define BLE_BLELL_CONN_INTR_RX_PDU_STATUS_Msk (0x3800UL) /*!< BLE_BLELL CONN_INTR: RX_PDU_STATUS (Bitfield-Mask: 0x07) */ +#define BLE_BLELL_CONN_INTR_PING_TIMER_EXPIRD_INTR_Pos (14UL) /*!< BLE_BLELL CONN_INTR: PING_TIMER_EXPIRD_INTR (Bit 14) */ +#define BLE_BLELL_CONN_INTR_PING_TIMER_EXPIRD_INTR_Msk (0x4000UL) /*!< BLE_BLELL CONN_INTR: PING_TIMER_EXPIRD_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_PING_NEARLY_EXPIRD_INTR_Pos (15UL) /*!< BLE_BLELL CONN_INTR: PING_NEARLY_EXPIRD_INTR (Bit 15) */ +#define BLE_BLELL_CONN_INTR_PING_NEARLY_EXPIRD_INTR_Msk (0x8000UL) /*!< BLE_BLELL CONN_INTR: PING_NEARLY_EXPIRD_INTR (Bitfield-Mask: 0x01)*/ +/* ================================================= BLE_BLELL.CONN_STATUS ================================================= */ +#define BLE_BLELL_CONN_STATUS_RECEIVE_PACKET_COUNT_Pos (12UL) /*!< BLE_BLELL CONN_STATUS: RECEIVE_PACKET_COUNT (Bit 12) */ +#define BLE_BLELL_CONN_STATUS_RECEIVE_PACKET_COUNT_Msk (0xf000UL) /*!< BLE_BLELL CONN_STATUS: RECEIVE_PACKET_COUNT (Bitfield-Mask: 0x0f)*/ +/* ================================================= BLE_BLELL.CONN_INDEX ================================================== */ +#define BLE_BLELL_CONN_INDEX_CONN_INDEX_Pos (0UL) /*!< BLE_BLELL CONN_INDEX: CONN_INDEX (Bit 0) */ +#define BLE_BLELL_CONN_INDEX_CONN_INDEX_Msk (0xffffUL) /*!< BLE_BLELL CONN_INDEX: CONN_INDEX (Bitfield-Mask: 0xffff) */ +/* ================================================ BLE_BLELL.WAKEUP_CONFIG ================================================ */ +#define BLE_BLELL_WAKEUP_CONFIG_OSC_STARTUP_DELAY_Pos (0UL) /*!< BLE_BLELL WAKEUP_CONFIG: OSC_STARTUP_DELAY (Bit 0) */ +#define BLE_BLELL_WAKEUP_CONFIG_OSC_STARTUP_DELAY_Msk (0xffUL) /*!< BLE_BLELL WAKEUP_CONFIG: OSC_STARTUP_DELAY (Bitfield-Mask: 0xff)*/ +#define BLE_BLELL_WAKEUP_CONFIG_DSM_OFFSET_TO_WAKEUP_INSTANT_Pos (10UL) /*!< BLE_BLELL WAKEUP_CONFIG: DSM_OFFSET_TO_WAKEUP_INSTANT (Bit 10)*/ +#define BLE_BLELL_WAKEUP_CONFIG_DSM_OFFSET_TO_WAKEUP_INSTANT_Msk (0xfc00UL) /*!< BLE_BLELL WAKEUP_CONFIG: DSM_OFFSET_TO_WAKEUP_INSTANT (Bitfield-Mask: 0x3f)*/ +/* =============================================== BLE_BLELL.WAKEUP_CONTROL ================================================ */ +#define BLE_BLELL_WAKEUP_CONTROL_WAKEUP_INSTANT_Pos (0UL) /*!< BLE_BLELL WAKEUP_CONTROL: WAKEUP_INSTANT (Bit 0) */ +#define BLE_BLELL_WAKEUP_CONTROL_WAKEUP_INSTANT_Msk (0xffffUL) /*!< BLE_BLELL WAKEUP_CONTROL: WAKEUP_INSTANT (Bitfield-Mask: 0xffff)*/ +/* ================================================ BLE_BLELL.CLOCK_CONFIG ================================================= */ +#define BLE_BLELL_CLOCK_CONFIG_ADV_CLK_GATE_EN_Pos (0UL) /*!< BLE_BLELL CLOCK_CONFIG: ADV_CLK_GATE_EN (Bit 0) */ +#define BLE_BLELL_CLOCK_CONFIG_ADV_CLK_GATE_EN_Msk (0x1UL) /*!< BLE_BLELL CLOCK_CONFIG: ADV_CLK_GATE_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_SCAN_CLK_GATE_EN_Pos (1UL) /*!< BLE_BLELL CLOCK_CONFIG: SCAN_CLK_GATE_EN (Bit 1) */ +#define BLE_BLELL_CLOCK_CONFIG_SCAN_CLK_GATE_EN_Msk (0x2UL) /*!< BLE_BLELL CLOCK_CONFIG: SCAN_CLK_GATE_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_INIT_CLK_GATE_EN_Pos (2UL) /*!< BLE_BLELL CLOCK_CONFIG: INIT_CLK_GATE_EN (Bit 2) */ +#define BLE_BLELL_CLOCK_CONFIG_INIT_CLK_GATE_EN_Msk (0x4UL) /*!< BLE_BLELL CLOCK_CONFIG: INIT_CLK_GATE_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_CONN_CLK_GATE_EN_Pos (3UL) /*!< BLE_BLELL CLOCK_CONFIG: CONN_CLK_GATE_EN (Bit 3) */ +#define BLE_BLELL_CLOCK_CONFIG_CONN_CLK_GATE_EN_Msk (0x8UL) /*!< BLE_BLELL CLOCK_CONFIG: CONN_CLK_GATE_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_CORECLK_GATE_EN_Pos (4UL) /*!< BLE_BLELL CLOCK_CONFIG: CORECLK_GATE_EN (Bit 4) */ +#define BLE_BLELL_CLOCK_CONFIG_CORECLK_GATE_EN_Msk (0x10UL) /*!< BLE_BLELL CLOCK_CONFIG: CORECLK_GATE_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_SYSCLK_GATE_EN_Pos (5UL) /*!< BLE_BLELL CLOCK_CONFIG: SYSCLK_GATE_EN (Bit 5) */ +#define BLE_BLELL_CLOCK_CONFIG_SYSCLK_GATE_EN_Msk (0x20UL) /*!< BLE_BLELL CLOCK_CONFIG: SYSCLK_GATE_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_PHY_CLK_GATE_EN_Pos (6UL) /*!< BLE_BLELL CLOCK_CONFIG: PHY_CLK_GATE_EN (Bit 6) */ +#define BLE_BLELL_CLOCK_CONFIG_PHY_CLK_GATE_EN_Msk (0x40UL) /*!< BLE_BLELL CLOCK_CONFIG: PHY_CLK_GATE_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_LLH_IDLE_Pos (7UL) /*!< BLE_BLELL CLOCK_CONFIG: LLH_IDLE (Bit 7) */ +#define BLE_BLELL_CLOCK_CONFIG_LLH_IDLE_Msk (0x80UL) /*!< BLE_BLELL CLOCK_CONFIG: LLH_IDLE (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CLOCK_CONFIG_LPO_CLK_FREQ_SEL_Pos (8UL) /*!< BLE_BLELL CLOCK_CONFIG: LPO_CLK_FREQ_SEL (Bit 8) */ +#define BLE_BLELL_CLOCK_CONFIG_LPO_CLK_FREQ_SEL_Msk (0x100UL) /*!< BLE_BLELL CLOCK_CONFIG: LPO_CLK_FREQ_SEL (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_LPO_SEL_EXTERNAL_Pos (9UL) /*!< BLE_BLELL CLOCK_CONFIG: LPO_SEL_EXTERNAL (Bit 9) */ +#define BLE_BLELL_CLOCK_CONFIG_LPO_SEL_EXTERNAL_Msk (0x200UL) /*!< BLE_BLELL CLOCK_CONFIG: LPO_SEL_EXTERNAL (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_SM_AUTO_WKUP_EN_Pos (10UL) /*!< BLE_BLELL CLOCK_CONFIG: SM_AUTO_WKUP_EN (Bit 10) */ +#define BLE_BLELL_CLOCK_CONFIG_SM_AUTO_WKUP_EN_Msk (0x400UL) /*!< BLE_BLELL CLOCK_CONFIG: SM_AUTO_WKUP_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_SM_INTR_EN_Pos (12UL) /*!< BLE_BLELL CLOCK_CONFIG: SM_INTR_EN (Bit 12) */ +#define BLE_BLELL_CLOCK_CONFIG_SM_INTR_EN_Msk (0x1000UL) /*!< BLE_BLELL CLOCK_CONFIG: SM_INTR_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_AUTO_WKUP_DISABLE_Pos (13UL) /*!< BLE_BLELL CLOCK_CONFIG: DEEP_SLEEP_AUTO_WKUP_DISABLE (Bit 13)*/ +#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_AUTO_WKUP_DISABLE_Msk (0x2000UL) /*!< BLE_BLELL CLOCK_CONFIG: DEEP_SLEEP_AUTO_WKUP_DISABLE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_SLEEP_MODE_EN_Pos (14UL) /*!< BLE_BLELL CLOCK_CONFIG: SLEEP_MODE_EN (Bit 14) */ +#define BLE_BLELL_CLOCK_CONFIG_SLEEP_MODE_EN_Msk (0x4000UL) /*!< BLE_BLELL CLOCK_CONFIG: SLEEP_MODE_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_MODE_EN_Pos (15UL) /*!< BLE_BLELL CLOCK_CONFIG: DEEP_SLEEP_MODE_EN (Bit 15) */ +#define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_MODE_EN_Msk (0x8000UL) /*!< BLE_BLELL CLOCK_CONFIG: DEEP_SLEEP_MODE_EN (Bitfield-Mask: 0x01)*/ +/* ================================================ BLE_BLELL.TIM_COUNTER_L ================================================ */ +#define BLE_BLELL_TIM_COUNTER_L_TIM_REF_CLOCK_Pos (0UL) /*!< BLE_BLELL TIM_COUNTER_L: TIM_REF_CLOCK (Bit 0) */ +#define BLE_BLELL_TIM_COUNTER_L_TIM_REF_CLOCK_Msk (0xffffUL) /*!< BLE_BLELL TIM_COUNTER_L: TIM_REF_CLOCK (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_BLELL.WAKEUP_CONFIG_EXTD ============================================== */ +#define BLE_BLELL_WAKEUP_CONFIG_EXTD_DSM_LF_OFFSET_Pos (0UL) /*!< BLE_BLELL WAKEUP_CONFIG_EXTD: DSM_LF_OFFSET (Bit 0) */ +#define BLE_BLELL_WAKEUP_CONFIG_EXTD_DSM_LF_OFFSET_Msk (0x1fUL) /*!< BLE_BLELL WAKEUP_CONFIG_EXTD: DSM_LF_OFFSET (Bitfield-Mask: 0x1f)*/ +/* ============================================ BLE_BLELL.POC_REG__TIM_CONTROL ============================================= */ +#define BLE_BLELL_POC_REG__TIM_CONTROL_BB_CLK_FREQ_MINUS_1_Pos (3UL) /*!< BLE_BLELL POC_REG__TIM_CONTROL: BB_CLK_FREQ_MINUS_1 (Bit 3)*/ +#define BLE_BLELL_POC_REG__TIM_CONTROL_BB_CLK_FREQ_MINUS_1_Msk (0xf8UL) /*!< BLE_BLELL POC_REG__TIM_CONTROL: BB_CLK_FREQ_MINUS_1 (Bitfield-Mask: 0x1f)*/ +#define BLE_BLELL_POC_REG__TIM_CONTROL_START_SLOT_OFFSET_Pos (8UL) /*!< BLE_BLELL POC_REG__TIM_CONTROL: START_SLOT_OFFSET (Bit 8)*/ +#define BLE_BLELL_POC_REG__TIM_CONTROL_START_SLOT_OFFSET_Msk (0xf00UL) /*!< BLE_BLELL POC_REG__TIM_CONTROL: START_SLOT_OFFSET (Bitfield-Mask: 0x0f)*/ +/* ============================================== BLE_BLELL.ADV_TX_DATA_FIFO =============================================== */ +#define BLE_BLELL_ADV_TX_DATA_FIFO_ADV_TX_DATA_Pos (0UL) /*!< BLE_BLELL ADV_TX_DATA_FIFO: ADV_TX_DATA (Bit 0) */ +#define BLE_BLELL_ADV_TX_DATA_FIFO_ADV_TX_DATA_Msk (0xffffUL) /*!< BLE_BLELL ADV_TX_DATA_FIFO: ADV_TX_DATA (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_BLELL.ADV_SCN_RSP_TX_FIFO ============================================= */ +#define BLE_BLELL_ADV_SCN_RSP_TX_FIFO_SCAN_RSP_DATA_Pos (0UL) /*!< BLE_BLELL ADV_SCN_RSP_TX_FIFO: SCAN_RSP_DATA (Bit 0) */ +#define BLE_BLELL_ADV_SCN_RSP_TX_FIFO_SCAN_RSP_DATA_Msk (0xffffUL) /*!< BLE_BLELL ADV_SCN_RSP_TX_FIFO: SCAN_RSP_DATA (Bitfield-Mask: 0xffff)*/ +/* ============================================ BLE_BLELL.INIT_SCN_ADV_RX_FIFO ============================================= */ +#define BLE_BLELL_INIT_SCN_ADV_RX_FIFO_ADV_SCAN_RSP_RX_DATA_Pos (0UL) /*!< BLE_BLELL INIT_SCN_ADV_RX_FIFO: ADV_SCAN_RSP_RX_DATA (Bit 0)*/ +#define BLE_BLELL_INIT_SCN_ADV_RX_FIFO_ADV_SCAN_RSP_RX_DATA_Msk (0xffffUL) /*!< BLE_BLELL INIT_SCN_ADV_RX_FIFO: ADV_SCAN_RSP_RX_DATA (Bitfield-Mask: 0xffff)*/ +/* ================================================ BLE_BLELL.CONN_INTERVAL ================================================ */ +#define BLE_BLELL_CONN_INTERVAL_CONNECTION_INTERVAL_Pos (0UL) /*!< BLE_BLELL CONN_INTERVAL: CONNECTION_INTERVAL (Bit 0) */ +#define BLE_BLELL_CONN_INTERVAL_CONNECTION_INTERVAL_Msk (0xffffUL) /*!< BLE_BLELL CONN_INTERVAL: CONNECTION_INTERVAL (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.SUP_TIMEOUT ================================================= */ +#define BLE_BLELL_SUP_TIMEOUT_SUPERVISION_TIMEOUT_Pos (0UL) /*!< BLE_BLELL SUP_TIMEOUT: SUPERVISION_TIMEOUT (Bit 0) */ +#define BLE_BLELL_SUP_TIMEOUT_SUPERVISION_TIMEOUT_Msk (0xffffUL) /*!< BLE_BLELL SUP_TIMEOUT: SUPERVISION_TIMEOUT (Bitfield-Mask: 0xffff)*/ +/* ================================================ BLE_BLELL.SLAVE_LATENCY ================================================ */ +#define BLE_BLELL_SLAVE_LATENCY_SLAVE_LATENCY_Pos (0UL) /*!< BLE_BLELL SLAVE_LATENCY: SLAVE_LATENCY (Bit 0) */ +#define BLE_BLELL_SLAVE_LATENCY_SLAVE_LATENCY_Msk (0xffffUL) /*!< BLE_BLELL SLAVE_LATENCY: SLAVE_LATENCY (Bitfield-Mask: 0xffff)*/ +/* ================================================== BLE_BLELL.CE_LENGTH ================================================== */ +#define BLE_BLELL_CE_LENGTH_CONNECTION_EVENT_LENGTH_Pos (0UL) /*!< BLE_BLELL CE_LENGTH: CONNECTION_EVENT_LENGTH (Bit 0) */ +#define BLE_BLELL_CE_LENGTH_CONNECTION_EVENT_LENGTH_Msk (0xffffUL) /*!< BLE_BLELL CE_LENGTH: CONNECTION_EVENT_LENGTH (Bitfield-Mask: 0xffff)*/ +/* ========================================= BLE_BLELL.PDU_ACCESS_ADDR_L_REGISTER ========================================== */ +#define BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER_PDU_ACCESS_ADDRESS_LOWER_BITS_Pos (0UL) /*!< BLE_BLELL PDU_ACCESS_ADDR_L_REGISTER: PDU_ACCESS_ADDRESS_LOWER_BITS (Bit 0)*/ +#define BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER_PDU_ACCESS_ADDRESS_LOWER_BITS_Msk (0xffffUL) /*!< BLE_BLELL PDU_ACCESS_ADDR_L_REGISTER: PDU_ACCESS_ADDRESS_LOWER_BITS (Bitfield-Mask: 0xffff)*/ +/* ========================================= BLE_BLELL.PDU_ACCESS_ADDR_H_REGISTER ========================================== */ +#define BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER_PDU_ACCESS_ADDRESS_HIGHER_BITS_Pos (0UL) /*!< BLE_BLELL PDU_ACCESS_ADDR_H_REGISTER: PDU_ACCESS_ADDRESS_HIGHER_BITS (Bit 0)*/ +#define BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER_PDU_ACCESS_ADDRESS_HIGHER_BITS_Msk (0xffffUL) /*!< BLE_BLELL PDU_ACCESS_ADDR_H_REGISTER: PDU_ACCESS_ADDRESS_HIGHER_BITS (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_CE_INSTANT =============================================== */ +#define BLE_BLELL_CONN_CE_INSTANT_CE_INSTANT_Pos (0UL) /*!< BLE_BLELL CONN_CE_INSTANT: CE_INSTANT (Bit 0) */ +#define BLE_BLELL_CONN_CE_INSTANT_CE_INSTANT_Msk (0xffffUL) /*!< BLE_BLELL CONN_CE_INSTANT: CE_INSTANT (Bitfield-Mask: 0xffff)*/ +/* ============================================ BLE_BLELL.CE_CNFG_STS_REGISTER ============================================= */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_INDEX_LAST_ACK_INDEX_Pos (0UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: DATA_LIST_INDEX_LAST_ACK_INDEX (Bit 0)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_INDEX_LAST_ACK_INDEX_Msk (0xfUL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: DATA_LIST_INDEX_LAST_ACK_INDEX (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_HEAD_UP_Pos (4UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: DATA_LIST_HEAD_UP (Bit 4)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_HEAD_UP_Msk (0x10UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: DATA_LIST_HEAD_UP (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_SPARE_Pos (5UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: SPARE (Bit 5) */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_SPARE_Msk (0x20UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: SPARE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_MD_Pos (6UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: MD (Bit 6) */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_MD_Msk (0x40UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: MD (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_MAP_INDEX__CURR_INDEX_Pos (7UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: MAP_INDEX__CURR_INDEX (Bit 7)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_MAP_INDEX__CURR_INDEX_Msk (0x80UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: MAP_INDEX__CURR_INDEX (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_PAUSE_DATA_Pos (8UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: PAUSE_DATA (Bit 8) */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_PAUSE_DATA_Msk (0x100UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: PAUSE_DATA (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_CONN_ACTIVE_Pos (10UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: CONN_ACTIVE (Bit 10) */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_CONN_ACTIVE_Msk (0x400UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: CONN_ACTIVE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_CURRENT_PDU_INDEX_Pos (12UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: CURRENT_PDU_INDEX (Bit 12)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_CURRENT_PDU_INDEX_Msk (0xf000UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER: CURRENT_PDU_INDEX (Bitfield-Mask: 0x0f)*/ +/* =============================================== BLE_BLELL.NEXT_CE_INSTANT =============================================== */ +#define BLE_BLELL_NEXT_CE_INSTANT_NEXT_CE_INSTANT_Pos (0UL) /*!< BLE_BLELL NEXT_CE_INSTANT: NEXT_CE_INSTANT (Bit 0) */ +#define BLE_BLELL_NEXT_CE_INSTANT_NEXT_CE_INSTANT_Msk (0xffffUL) /*!< BLE_BLELL NEXT_CE_INSTANT: NEXT_CE_INSTANT (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_CE_COUNTER =============================================== */ +#define BLE_BLELL_CONN_CE_COUNTER_CONNECTION_EVENT_COUNTER_Pos (0UL) /*!< BLE_BLELL CONN_CE_COUNTER: CONNECTION_EVENT_COUNTER (Bit 0)*/ +#define BLE_BLELL_CONN_CE_COUNTER_CONNECTION_EVENT_COUNTER_Msk (0xffffUL) /*!< BLE_BLELL CONN_CE_COUNTER: CONNECTION_EVENT_COUNTER (Bitfield-Mask: 0xffff)*/ +/* ======================================== BLE_BLELL.DATA_LIST_SENT_UPDATE__STATUS ======================================== */ +#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_LIST_INDEX__TX_SENT_3_0_Pos (0UL) /*!< BLE_BLELL DATA_LIST_SENT_UPDATE__STATUS: LIST_INDEX__TX_SENT_3_0 (Bit 0)*/ +#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_LIST_INDEX__TX_SENT_3_0_Msk (0xfUL) /*!< BLE_BLELL DATA_LIST_SENT_UPDATE__STATUS: LIST_INDEX__TX_SENT_3_0 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_SET_CLEAR_Pos (7UL) /*!< BLE_BLELL DATA_LIST_SENT_UPDATE__STATUS: SET_CLEAR (Bit 7)*/ +#define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_SET_CLEAR_Msk (0x80UL) /*!< BLE_BLELL DATA_LIST_SENT_UPDATE__STATUS: SET_CLEAR (Bitfield-Mask: 0x01)*/ +/* ======================================== BLE_BLELL.DATA_LIST_ACK_UPDATE__STATUS ========================================= */ +#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_LIST_INDEX__TX_ACK_3_0_Pos (0UL) /*!< BLE_BLELL DATA_LIST_ACK_UPDATE__STATUS: LIST_INDEX__TX_ACK_3_0 (Bit 0)*/ +#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_LIST_INDEX__TX_ACK_3_0_Msk (0xfUL) /*!< BLE_BLELL DATA_LIST_ACK_UPDATE__STATUS: LIST_INDEX__TX_ACK_3_0 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_SET_CLEAR_Pos (7UL) /*!< BLE_BLELL DATA_LIST_ACK_UPDATE__STATUS: SET_CLEAR (Bit 7)*/ +#define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_SET_CLEAR_Msk (0x80UL) /*!< BLE_BLELL DATA_LIST_ACK_UPDATE__STATUS: SET_CLEAR (Bitfield-Mask: 0x01)*/ +/* ========================================== BLE_BLELL.CE_CNFG_STS_REGISTER_EXT =========================================== */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_TX_2M_Pos (0UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER_EXT: TX_2M (Bit 0) */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_TX_2M_Msk (0x1UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER_EXT: TX_2M (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_RX_2M_Pos (1UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER_EXT: RX_2M (Bit 1) */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_RX_2M_Msk (0x2UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER_EXT: RX_2M (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_SN_Pos (2UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER_EXT: SN (Bit 2) */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_SN_Msk (0x4UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER_EXT: SN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_NESN_Pos (3UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER_EXT: NESN (Bit 3) */ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_NESN_Msk (0x8UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER_EXT: NESN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_LAST_UNMAPPED_CHANNEL_Pos (8UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER_EXT: LAST_UNMAPPED_CHANNEL (Bit 8)*/ +#define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_LAST_UNMAPPED_CHANNEL_Msk (0x3f00UL) /*!< BLE_BLELL CE_CNFG_STS_REGISTER_EXT: LAST_UNMAPPED_CHANNEL (Bitfield-Mask: 0x3f)*/ +/* ================================================ BLE_BLELL.CONN_EXT_INTR ================================================ */ +#define BLE_BLELL_CONN_EXT_INTR_DATARATE_UPDATE_Pos (0UL) /*!< BLE_BLELL CONN_EXT_INTR: DATARATE_UPDATE (Bit 0) */ +#define BLE_BLELL_CONN_EXT_INTR_DATARATE_UPDATE_Msk (0x1UL) /*!< BLE_BLELL CONN_EXT_INTR: DATARATE_UPDATE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_EXT_INTR_EARLY_INTR_Pos (1UL) /*!< BLE_BLELL CONN_EXT_INTR: EARLY_INTR (Bit 1) */ +#define BLE_BLELL_CONN_EXT_INTR_EARLY_INTR_Msk (0x2UL) /*!< BLE_BLELL CONN_EXT_INTR: EARLY_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CONN_EXT_INTR_GEN_TIMER_INTR_Pos (2UL) /*!< BLE_BLELL CONN_EXT_INTR: GEN_TIMER_INTR (Bit 2) */ +#define BLE_BLELL_CONN_EXT_INTR_GEN_TIMER_INTR_Msk (0x4UL) /*!< BLE_BLELL CONN_EXT_INTR: GEN_TIMER_INTR (Bitfield-Mask: 0x01)*/ +/* ============================================= BLE_BLELL.CONN_EXT_INTR_MASK ============================================== */ +#define BLE_BLELL_CONN_EXT_INTR_MASK_DATARATE_UPDATE_Pos (0UL) /*!< BLE_BLELL CONN_EXT_INTR_MASK: DATARATE_UPDATE (Bit 0) */ +#define BLE_BLELL_CONN_EXT_INTR_MASK_DATARATE_UPDATE_Msk (0x1UL) /*!< BLE_BLELL CONN_EXT_INTR_MASK: DATARATE_UPDATE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_EXT_INTR_MASK_EARLY_INTR_Pos (1UL) /*!< BLE_BLELL CONN_EXT_INTR_MASK: EARLY_INTR (Bit 1) */ +#define BLE_BLELL_CONN_EXT_INTR_MASK_EARLY_INTR_Msk (0x2UL) /*!< BLE_BLELL CONN_EXT_INTR_MASK: EARLY_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_EXT_INTR_MASK_GEN_TIMER_INTR_Pos (2UL) /*!< BLE_BLELL CONN_EXT_INTR_MASK: GEN_TIMER_INTR (Bit 2) */ +#define BLE_BLELL_CONN_EXT_INTR_MASK_GEN_TIMER_INTR_Msk (0x4UL) /*!< BLE_BLELL CONN_EXT_INTR_MASK: GEN_TIMER_INTR (Bitfield-Mask: 0x01)*/ +/* ============================================= BLE_BLELL.DATA_MEM_DESCRIPTOR ============================================= */ +#define BLE_BLELL_DATA_MEM_DESCRIPTOR_LLID_Pos (0UL) /*!< BLE_BLELL DATA_MEM_DESCRIPTOR: LLID (Bit 0) */ +#define BLE_BLELL_DATA_MEM_DESCRIPTOR_LLID_Msk (0x3UL) /*!< BLE_BLELL DATA_MEM_DESCRIPTOR: LLID (Bitfield-Mask: 0x03) */ +#define BLE_BLELL_DATA_MEM_DESCRIPTOR_DATA_LENGTH_Pos (2UL) /*!< BLE_BLELL DATA_MEM_DESCRIPTOR: DATA_LENGTH (Bit 2) */ +#define BLE_BLELL_DATA_MEM_DESCRIPTOR_DATA_LENGTH_Msk (0x3fcUL) /*!< BLE_BLELL DATA_MEM_DESCRIPTOR: DATA_LENGTH (Bitfield-Mask: 0xff)*/ +/* ============================================= BLE_BLELL.WINDOW_WIDEN_INTVL ============================================== */ +#define BLE_BLELL_WINDOW_WIDEN_INTVL_WINDOW_WIDEN_INTVL_Pos (0UL) /*!< BLE_BLELL WINDOW_WIDEN_INTVL: WINDOW_WIDEN_INTVL (Bit 0)*/ +#define BLE_BLELL_WINDOW_WIDEN_INTVL_WINDOW_WIDEN_INTVL_Msk (0xfffUL) /*!< BLE_BLELL WINDOW_WIDEN_INTVL: WINDOW_WIDEN_INTVL (Bitfield-Mask: 0xfff)*/ +/* ============================================= BLE_BLELL.WINDOW_WIDEN_WINOFF ============================================= */ +#define BLE_BLELL_WINDOW_WIDEN_WINOFF_WINDOW_WIDEN_WINOFF_Pos (0UL) /*!< BLE_BLELL WINDOW_WIDEN_WINOFF: WINDOW_WIDEN_WINOFF (Bit 0)*/ +#define BLE_BLELL_WINDOW_WIDEN_WINOFF_WINDOW_WIDEN_WINOFF_Msk (0xfffUL) /*!< BLE_BLELL WINDOW_WIDEN_WINOFF: WINDOW_WIDEN_WINOFF (Bitfield-Mask: 0xfff)*/ +/* =============================================== BLE_BLELL.LE_RF_TEST_MODE =============================================== */ +#define BLE_BLELL_LE_RF_TEST_MODE_TEST_FREQUENCY_Pos (0UL) /*!< BLE_BLELL LE_RF_TEST_MODE: TEST_FREQUENCY (Bit 0) */ +#define BLE_BLELL_LE_RF_TEST_MODE_TEST_FREQUENCY_Msk (0x3fUL) /*!< BLE_BLELL LE_RF_TEST_MODE: TEST_FREQUENCY (Bitfield-Mask: 0x3f)*/ +#define BLE_BLELL_LE_RF_TEST_MODE_DTM_STATUS__DTM_CONT_RXEN_Pos (6UL) /*!< BLE_BLELL LE_RF_TEST_MODE: DTM_STATUS__DTM_CONT_RXEN (Bit 6)*/ +#define BLE_BLELL_LE_RF_TEST_MODE_DTM_STATUS__DTM_CONT_RXEN_Msk (0x40UL) /*!< BLE_BLELL LE_RF_TEST_MODE: DTM_STATUS__DTM_CONT_RXEN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LE_RF_TEST_MODE_PKT_PAYLOAD_Pos (7UL) /*!< BLE_BLELL LE_RF_TEST_MODE: PKT_PAYLOAD (Bit 7) */ +#define BLE_BLELL_LE_RF_TEST_MODE_PKT_PAYLOAD_Msk (0x380UL) /*!< BLE_BLELL LE_RF_TEST_MODE: PKT_PAYLOAD (Bitfield-Mask: 0x07)*/ +#define BLE_BLELL_LE_RF_TEST_MODE_DTM_CONT_TXEN_Pos (13UL) /*!< BLE_BLELL LE_RF_TEST_MODE: DTM_CONT_TXEN (Bit 13) */ +#define BLE_BLELL_LE_RF_TEST_MODE_DTM_CONT_TXEN_Msk (0x2000UL) /*!< BLE_BLELL LE_RF_TEST_MODE: DTM_CONT_TXEN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LE_RF_TEST_MODE_DTM_DATA_2MBPS_Pos (15UL) /*!< BLE_BLELL LE_RF_TEST_MODE: DTM_DATA_2MBPS (Bit 15) */ +#define BLE_BLELL_LE_RF_TEST_MODE_DTM_DATA_2MBPS_Msk (0x8000UL) /*!< BLE_BLELL LE_RF_TEST_MODE: DTM_DATA_2MBPS (Bitfield-Mask: 0x01)*/ +/* ============================================== BLE_BLELL.DTM_RX_PKT_COUNT =============================================== */ +#define BLE_BLELL_DTM_RX_PKT_COUNT_RX_PACKET_COUNT_Pos (0UL) /*!< BLE_BLELL DTM_RX_PKT_COUNT: RX_PACKET_COUNT (Bit 0) */ +#define BLE_BLELL_DTM_RX_PKT_COUNT_RX_PACKET_COUNT_Msk (0xffffUL) /*!< BLE_BLELL DTM_RX_PKT_COUNT: RX_PACKET_COUNT (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_BLELL.LE_RF_TEST_MODE_EXT ============================================= */ +#define BLE_BLELL_LE_RF_TEST_MODE_EXT_DTM_PACKET_LENGTH_Pos (0UL) /*!< BLE_BLELL LE_RF_TEST_MODE_EXT: DTM_PACKET_LENGTH (Bit 0)*/ +#define BLE_BLELL_LE_RF_TEST_MODE_EXT_DTM_PACKET_LENGTH_Msk (0xffUL) /*!< BLE_BLELL LE_RF_TEST_MODE_EXT: DTM_PACKET_LENGTH (Bitfield-Mask: 0xff)*/ +/* ================================================== BLE_BLELL.TXRX_HOP =================================================== */ +#define BLE_BLELL_TXRX_HOP_HOP_CH_TX_Pos (0UL) /*!< BLE_BLELL TXRX_HOP: HOP_CH_TX (Bit 0) */ +#define BLE_BLELL_TXRX_HOP_HOP_CH_TX_Msk (0x7fUL) /*!< BLE_BLELL TXRX_HOP: HOP_CH_TX (Bitfield-Mask: 0x7f) */ +#define BLE_BLELL_TXRX_HOP_HOP_CH_RX_Pos (8UL) /*!< BLE_BLELL TXRX_HOP: HOP_CH_RX (Bit 8) */ +#define BLE_BLELL_TXRX_HOP_HOP_CH_RX_Msk (0x7f00UL) /*!< BLE_BLELL TXRX_HOP: HOP_CH_RX (Bitfield-Mask: 0x7f) */ +/* =============================================== BLE_BLELL.TX_RX_ON_DELAY ================================================ */ +#define BLE_BLELL_TX_RX_ON_DELAY_RXON_DELAY_Pos (0UL) /*!< BLE_BLELL TX_RX_ON_DELAY: RXON_DELAY (Bit 0) */ +#define BLE_BLELL_TX_RX_ON_DELAY_RXON_DELAY_Msk (0xffUL) /*!< BLE_BLELL TX_RX_ON_DELAY: RXON_DELAY (Bitfield-Mask: 0xff)*/ +#define BLE_BLELL_TX_RX_ON_DELAY_TXON_DELAY_Pos (8UL) /*!< BLE_BLELL TX_RX_ON_DELAY: TXON_DELAY (Bit 8) */ +#define BLE_BLELL_TX_RX_ON_DELAY_TXON_DELAY_Msk (0xff00UL) /*!< BLE_BLELL TX_RX_ON_DELAY: TXON_DELAY (Bitfield-Mask: 0xff)*/ +/* ================================================ BLE_BLELL.ADV_ACCADDR_L ================================================ */ +#define BLE_BLELL_ADV_ACCADDR_L_ADV_ACCADDR_L_Pos (0UL) /*!< BLE_BLELL ADV_ACCADDR_L: ADV_ACCADDR_L (Bit 0) */ +#define BLE_BLELL_ADV_ACCADDR_L_ADV_ACCADDR_L_Msk (0xffffUL) /*!< BLE_BLELL ADV_ACCADDR_L: ADV_ACCADDR_L (Bitfield-Mask: 0xffff)*/ +/* ================================================ BLE_BLELL.ADV_ACCADDR_H ================================================ */ +#define BLE_BLELL_ADV_ACCADDR_H_ADV_ACCADDR_H_Pos (0UL) /*!< BLE_BLELL ADV_ACCADDR_H: ADV_ACCADDR_H (Bit 0) */ +#define BLE_BLELL_ADV_ACCADDR_H_ADV_ACCADDR_H_Msk (0xffffUL) /*!< BLE_BLELL ADV_ACCADDR_H: ADV_ACCADDR_H (Bitfield-Mask: 0xffff)*/ +/* =========================================== BLE_BLELL.ADV_CH_TX_POWER_LVL_LS ============================================ */ +#define BLE_BLELL_ADV_CH_TX_POWER_LVL_LS_ADV_TRANSMIT_POWER_LVL_LS_Pos (0UL) /*!< BLE_BLELL ADV_CH_TX_POWER_LVL_LS: ADV_TRANSMIT_POWER_LVL_LS (Bit 0)*/ +#define BLE_BLELL_ADV_CH_TX_POWER_LVL_LS_ADV_TRANSMIT_POWER_LVL_LS_Msk (0xffffUL) /*!< BLE_BLELL ADV_CH_TX_POWER_LVL_LS: ADV_TRANSMIT_POWER_LVL_LS (Bitfield-Mask: 0xffff)*/ +/* =========================================== BLE_BLELL.ADV_CH_TX_POWER_LVL_MS ============================================ */ +#define BLE_BLELL_ADV_CH_TX_POWER_LVL_MS_ADV_TRANSMIT_POWER_LVL_MS_Pos (0UL) /*!< BLE_BLELL ADV_CH_TX_POWER_LVL_MS: ADV_TRANSMIT_POWER_LVL_MS (Bit 0)*/ +#define BLE_BLELL_ADV_CH_TX_POWER_LVL_MS_ADV_TRANSMIT_POWER_LVL_MS_Msk (0x3UL) /*!< BLE_BLELL ADV_CH_TX_POWER_LVL_MS: ADV_TRANSMIT_POWER_LVL_MS (Bitfield-Mask: 0x03)*/ +/* =========================================== BLE_BLELL.CONN_CH_TX_POWER_LVL_LS =========================================== */ +#define BLE_BLELL_CONN_CH_TX_POWER_LVL_LS_CONNCH_TRANSMIT_POWER_LVL_LS_Pos (0UL) /*!< BLE_BLELL CONN_CH_TX_POWER_LVL_LS: CONNCH_TRANSMIT_POWER_LVL_LS (Bit 0)*/ +#define BLE_BLELL_CONN_CH_TX_POWER_LVL_LS_CONNCH_TRANSMIT_POWER_LVL_LS_Msk (0xffffUL) /*!< BLE_BLELL CONN_CH_TX_POWER_LVL_LS: CONNCH_TRANSMIT_POWER_LVL_LS (Bitfield-Mask: 0xffff)*/ +/* =========================================== BLE_BLELL.CONN_CH_TX_POWER_LVL_MS =========================================== */ +#define BLE_BLELL_CONN_CH_TX_POWER_LVL_MS_CONNCH_TRANSMIT_POWER_LVL_MS_Pos (0UL) /*!< BLE_BLELL CONN_CH_TX_POWER_LVL_MS: CONNCH_TRANSMIT_POWER_LVL_MS (Bit 0)*/ +#define BLE_BLELL_CONN_CH_TX_POWER_LVL_MS_CONNCH_TRANSMIT_POWER_LVL_MS_Msk (0x3UL) /*!< BLE_BLELL CONN_CH_TX_POWER_LVL_MS: CONNCH_TRANSMIT_POWER_LVL_MS (Bitfield-Mask: 0x03)*/ +/* =============================================== BLE_BLELL.DEV_PUB_ADDR_L ================================================ */ +#define BLE_BLELL_DEV_PUB_ADDR_L_DEV_PUB_ADDR_L_Pos (0UL) /*!< BLE_BLELL DEV_PUB_ADDR_L: DEV_PUB_ADDR_L (Bit 0) */ +#define BLE_BLELL_DEV_PUB_ADDR_L_DEV_PUB_ADDR_L_Msk (0xffffUL) /*!< BLE_BLELL DEV_PUB_ADDR_L: DEV_PUB_ADDR_L (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.DEV_PUB_ADDR_M ================================================ */ +#define BLE_BLELL_DEV_PUB_ADDR_M_DEV_PUB_ADDR_M_Pos (0UL) /*!< BLE_BLELL DEV_PUB_ADDR_M: DEV_PUB_ADDR_M (Bit 0) */ +#define BLE_BLELL_DEV_PUB_ADDR_M_DEV_PUB_ADDR_M_Msk (0xffffUL) /*!< BLE_BLELL DEV_PUB_ADDR_M: DEV_PUB_ADDR_M (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.DEV_PUB_ADDR_H ================================================ */ +#define BLE_BLELL_DEV_PUB_ADDR_H_DEV_PUB_ADDR_H_Pos (0UL) /*!< BLE_BLELL DEV_PUB_ADDR_H: DEV_PUB_ADDR_H (Bit 0) */ +#define BLE_BLELL_DEV_PUB_ADDR_H_DEV_PUB_ADDR_H_Msk (0xffffUL) /*!< BLE_BLELL DEV_PUB_ADDR_H: DEV_PUB_ADDR_H (Bitfield-Mask: 0xffff)*/ +/* =========================================== BLE_BLELL.OFFSET_TO_FIRST_INSTANT =========================================== */ +#define BLE_BLELL_OFFSET_TO_FIRST_INSTANT_OFFSET_TO_FIRST_EVENT_Pos (0UL) /*!< BLE_BLELL OFFSET_TO_FIRST_INSTANT: OFFSET_TO_FIRST_EVENT (Bit 0)*/ +#define BLE_BLELL_OFFSET_TO_FIRST_INSTANT_OFFSET_TO_FIRST_EVENT_Msk (0xffffUL) /*!< BLE_BLELL OFFSET_TO_FIRST_INSTANT: OFFSET_TO_FIRST_EVENT (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.ADV_CONFIG ================================================== */ +#define BLE_BLELL_ADV_CONFIG_ADV_STRT_EN_Pos (0UL) /*!< BLE_BLELL ADV_CONFIG: ADV_STRT_EN (Bit 0) */ +#define BLE_BLELL_ADV_CONFIG_ADV_STRT_EN_Msk (0x1UL) /*!< BLE_BLELL ADV_CONFIG: ADV_STRT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_CONFIG_ADV_CLS_EN_Pos (1UL) /*!< BLE_BLELL ADV_CONFIG: ADV_CLS_EN (Bit 1) */ +#define BLE_BLELL_ADV_CONFIG_ADV_CLS_EN_Msk (0x2UL) /*!< BLE_BLELL ADV_CONFIG: ADV_CLS_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_CONFIG_ADV_TX_EN_Pos (2UL) /*!< BLE_BLELL ADV_CONFIG: ADV_TX_EN (Bit 2) */ +#define BLE_BLELL_ADV_CONFIG_ADV_TX_EN_Msk (0x4UL) /*!< BLE_BLELL ADV_CONFIG: ADV_TX_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_CONFIG_SCN_RSP_TX_EN_Pos (3UL) /*!< BLE_BLELL ADV_CONFIG: SCN_RSP_TX_EN (Bit 3) */ +#define BLE_BLELL_ADV_CONFIG_SCN_RSP_TX_EN_Msk (0x8UL) /*!< BLE_BLELL ADV_CONFIG: SCN_RSP_TX_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_ADV_CONFIG_ADV_SCN_REQ_RX_EN_Pos (4UL) /*!< BLE_BLELL ADV_CONFIG: ADV_SCN_REQ_RX_EN (Bit 4) */ +#define BLE_BLELL_ADV_CONFIG_ADV_SCN_REQ_RX_EN_Msk (0x10UL) /*!< BLE_BLELL ADV_CONFIG: ADV_SCN_REQ_RX_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_CONFIG_ADV_CONN_REQ_RX_EN_Pos (5UL) /*!< BLE_BLELL ADV_CONFIG: ADV_CONN_REQ_RX_EN (Bit 5) */ +#define BLE_BLELL_ADV_CONFIG_ADV_CONN_REQ_RX_EN_Msk (0x20UL) /*!< BLE_BLELL ADV_CONFIG: ADV_CONN_REQ_RX_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_CONFIG_SLV_CONNECTED_EN_Pos (6UL) /*!< BLE_BLELL ADV_CONFIG: SLV_CONNECTED_EN (Bit 6) */ +#define BLE_BLELL_ADV_CONFIG_SLV_CONNECTED_EN_Msk (0x40UL) /*!< BLE_BLELL ADV_CONFIG: SLV_CONNECTED_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_CONFIG_ADV_TIMEOUT_EN_Pos (7UL) /*!< BLE_BLELL ADV_CONFIG: ADV_TIMEOUT_EN (Bit 7) */ +#define BLE_BLELL_ADV_CONFIG_ADV_TIMEOUT_EN_Msk (0x80UL) /*!< BLE_BLELL ADV_CONFIG: ADV_TIMEOUT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_CONFIG_ADV_RAND_DISABLE_Pos (8UL) /*!< BLE_BLELL ADV_CONFIG: ADV_RAND_DISABLE (Bit 8) */ +#define BLE_BLELL_ADV_CONFIG_ADV_RAND_DISABLE_Msk (0x100UL) /*!< BLE_BLELL ADV_CONFIG: ADV_RAND_DISABLE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_CONFIG_ADV_SCN_PEER_RPA_UNMCH_EN_Pos (9UL) /*!< BLE_BLELL ADV_CONFIG: ADV_SCN_PEER_RPA_UNMCH_EN (Bit 9) */ +#define BLE_BLELL_ADV_CONFIG_ADV_SCN_PEER_RPA_UNMCH_EN_Msk (0x200UL) /*!< BLE_BLELL ADV_CONFIG: ADV_SCN_PEER_RPA_UNMCH_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_CONFIG_ADV_CONN_PEER_RPA_UNMCH_EN_Pos (10UL) /*!< BLE_BLELL ADV_CONFIG: ADV_CONN_PEER_RPA_UNMCH_EN (Bit 10)*/ +#define BLE_BLELL_ADV_CONFIG_ADV_CONN_PEER_RPA_UNMCH_EN_Msk (0x400UL) /*!< BLE_BLELL ADV_CONFIG: ADV_CONN_PEER_RPA_UNMCH_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_ADV_CONFIG_ADV_PKT_INTERVAL_Pos (11UL) /*!< BLE_BLELL ADV_CONFIG: ADV_PKT_INTERVAL (Bit 11) */ +#define BLE_BLELL_ADV_CONFIG_ADV_PKT_INTERVAL_Msk (0xf800UL) /*!< BLE_BLELL ADV_CONFIG: ADV_PKT_INTERVAL (Bitfield-Mask: 0x1f)*/ +/* ================================================= BLE_BLELL.SCAN_CONFIG ================================================= */ +#define BLE_BLELL_SCAN_CONFIG_SCN_STRT_EN_Pos (0UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_STRT_EN (Bit 0) */ +#define BLE_BLELL_SCAN_CONFIG_SCN_STRT_EN_Msk (0x1UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_STRT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_SCAN_CONFIG_SCN_CLOSE_EN_Pos (1UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_CLOSE_EN (Bit 1) */ +#define BLE_BLELL_SCAN_CONFIG_SCN_CLOSE_EN_Msk (0x2UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_CLOSE_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_SCAN_CONFIG_SCN_TX_EN_Pos (2UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_TX_EN (Bit 2) */ +#define BLE_BLELL_SCAN_CONFIG_SCN_TX_EN_Msk (0x4UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_TX_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_SCAN_CONFIG_ADV_RX_EN_Pos (3UL) /*!< BLE_BLELL SCAN_CONFIG: ADV_RX_EN (Bit 3) */ +#define BLE_BLELL_SCAN_CONFIG_ADV_RX_EN_Msk (0x8UL) /*!< BLE_BLELL SCAN_CONFIG: ADV_RX_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_SCAN_CONFIG_SCN_RSP_RX_EN_Pos (4UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_RSP_RX_EN (Bit 4) */ +#define BLE_BLELL_SCAN_CONFIG_SCN_RSP_RX_EN_Msk (0x10UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_RSP_RX_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN_Pos (5UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN (Bit 5)*/ +#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN_Msk (0x20UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN_Pos (6UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN (Bit 6)*/ +#define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN_Msk (0x40UL) /*!< BLE_BLELL SCAN_CONFIG: SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_CONFIG_SCANA_TX_ADDR_NOT_SET_INTR_EN_Pos (7UL) /*!< BLE_BLELL SCAN_CONFIG: SCANA_TX_ADDR_NOT_SET_INTR_EN (Bit 7)*/ +#define BLE_BLELL_SCAN_CONFIG_SCANA_TX_ADDR_NOT_SET_INTR_EN_Msk (0x80UL) /*!< BLE_BLELL SCAN_CONFIG: SCANA_TX_ADDR_NOT_SET_INTR_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_CONFIG_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN_Pos (8UL) /*!< BLE_BLELL SCAN_CONFIG: RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN (Bit 8)*/ +#define BLE_BLELL_SCAN_CONFIG_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN_Msk (0x100UL) /*!< BLE_BLELL SCAN_CONFIG: RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_CONFIG_BACKOFF_ENABLE_Pos (11UL) /*!< BLE_BLELL SCAN_CONFIG: BACKOFF_ENABLE (Bit 11) */ +#define BLE_BLELL_SCAN_CONFIG_BACKOFF_ENABLE_Msk (0x800UL) /*!< BLE_BLELL SCAN_CONFIG: BACKOFF_ENABLE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_SCAN_CONFIG_SCAN_CHANNEL_MAP_Pos (13UL) /*!< BLE_BLELL SCAN_CONFIG: SCAN_CHANNEL_MAP (Bit 13) */ +#define BLE_BLELL_SCAN_CONFIG_SCAN_CHANNEL_MAP_Msk (0xe000UL) /*!< BLE_BLELL SCAN_CONFIG: SCAN_CHANNEL_MAP (Bitfield-Mask: 0x07)*/ +/* ================================================= BLE_BLELL.INIT_CONFIG ================================================= */ +#define BLE_BLELL_INIT_CONFIG_INIT_STRT_EN_Pos (0UL) /*!< BLE_BLELL INIT_CONFIG: INIT_STRT_EN (Bit 0) */ +#define BLE_BLELL_INIT_CONFIG_INIT_STRT_EN_Msk (0x1UL) /*!< BLE_BLELL INIT_CONFIG: INIT_STRT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_INIT_CONFIG_INIT_CLOSE_EN_Pos (1UL) /*!< BLE_BLELL INIT_CONFIG: INIT_CLOSE_EN (Bit 1) */ +#define BLE_BLELL_INIT_CONFIG_INIT_CLOSE_EN_Msk (0x2UL) /*!< BLE_BLELL INIT_CONFIG: INIT_CLOSE_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_CONFIG_CONN_REQ_TX_EN_Pos (2UL) /*!< BLE_BLELL INIT_CONFIG: CONN_REQ_TX_EN (Bit 2) */ +#define BLE_BLELL_INIT_CONFIG_CONN_REQ_TX_EN_Msk (0x4UL) /*!< BLE_BLELL INIT_CONFIG: CONN_REQ_TX_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_CONFIG_CONN_CREATED_Pos (4UL) /*!< BLE_BLELL INIT_CONFIG: CONN_CREATED (Bit 4) */ +#define BLE_BLELL_INIT_CONFIG_CONN_CREATED_Msk (0x10UL) /*!< BLE_BLELL INIT_CONFIG: CONN_CREATED (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN_Pos (5UL) /*!< BLE_BLELL INIT_CONFIG: INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN (Bit 5)*/ +#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN_Msk (0x20UL) /*!< BLE_BLELL INIT_CONFIG: INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN_Pos (6UL) /*!< BLE_BLELL INIT_CONFIG: INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN (Bit 6)*/ +#define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN_Msk (0x40UL) /*!< BLE_BLELL INIT_CONFIG: INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_CONFIG_INITA_TX_ADDR_NOT_SET_INTR_EN_Pos (7UL) /*!< BLE_BLELL INIT_CONFIG: INITA_TX_ADDR_NOT_SET_INTR_EN (Bit 7)*/ +#define BLE_BLELL_INIT_CONFIG_INITA_TX_ADDR_NOT_SET_INTR_EN_Msk (0x80UL) /*!< BLE_BLELL INIT_CONFIG: INITA_TX_ADDR_NOT_SET_INTR_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_INIT_CONFIG_INIT_CHANNEL_MAP_Pos (13UL) /*!< BLE_BLELL INIT_CONFIG: INIT_CHANNEL_MAP (Bit 13) */ +#define BLE_BLELL_INIT_CONFIG_INIT_CHANNEL_MAP_Msk (0xe000UL) /*!< BLE_BLELL INIT_CONFIG: INIT_CHANNEL_MAP (Bitfield-Mask: 0x07)*/ +/* ================================================= BLE_BLELL.CONN_CONFIG ================================================= */ +#define BLE_BLELL_CONN_CONFIG_RX_PKT_LIMIT_Pos (0UL) /*!< BLE_BLELL CONN_CONFIG: RX_PKT_LIMIT (Bit 0) */ +#define BLE_BLELL_CONN_CONFIG_RX_PKT_LIMIT_Msk (0xfUL) /*!< BLE_BLELL CONN_CONFIG: RX_PKT_LIMIT (Bitfield-Mask: 0x0f) */ +#define BLE_BLELL_CONN_CONFIG_RX_INTR_THRESHOLD_Pos (4UL) /*!< BLE_BLELL CONN_CONFIG: RX_INTR_THRESHOLD (Bit 4) */ +#define BLE_BLELL_CONN_CONFIG_RX_INTR_THRESHOLD_Msk (0xf0UL) /*!< BLE_BLELL CONN_CONFIG: RX_INTR_THRESHOLD (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_CONFIG_MD_BIT_CLEAR_Pos (8UL) /*!< BLE_BLELL CONN_CONFIG: MD_BIT_CLEAR (Bit 8) */ +#define BLE_BLELL_CONN_CONFIG_MD_BIT_CLEAR_Msk (0x100UL) /*!< BLE_BLELL CONN_CONFIG: MD_BIT_CLEAR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_CONN_CONFIG_DSM_SLOT_VARIANCE_Pos (11UL) /*!< BLE_BLELL CONN_CONFIG: DSM_SLOT_VARIANCE (Bit 11) */ +#define BLE_BLELL_CONN_CONFIG_DSM_SLOT_VARIANCE_Msk (0x800UL) /*!< BLE_BLELL CONN_CONFIG: DSM_SLOT_VARIANCE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_CONFIG_SLV_MD_CONFIG_Pos (12UL) /*!< BLE_BLELL CONN_CONFIG: SLV_MD_CONFIG (Bit 12) */ +#define BLE_BLELL_CONN_CONFIG_SLV_MD_CONFIG_Msk (0x1000UL) /*!< BLE_BLELL CONN_CONFIG: SLV_MD_CONFIG (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_CONFIG_EXTEND_CU_TX_WIN_Pos (13UL) /*!< BLE_BLELL CONN_CONFIG: EXTEND_CU_TX_WIN (Bit 13) */ +#define BLE_BLELL_CONN_CONFIG_EXTEND_CU_TX_WIN_Msk (0x2000UL) /*!< BLE_BLELL CONN_CONFIG: EXTEND_CU_TX_WIN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_CONFIG_MASK_SUTO_AT_UPDT_Pos (14UL) /*!< BLE_BLELL CONN_CONFIG: MASK_SUTO_AT_UPDT (Bit 14) */ +#define BLE_BLELL_CONN_CONFIG_MASK_SUTO_AT_UPDT_Msk (0x4000UL) /*!< BLE_BLELL CONN_CONFIG: MASK_SUTO_AT_UPDT (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_CONFIG_CONN_REQ_1SLOT_EARLY_Pos (15UL) /*!< BLE_BLELL CONN_CONFIG: CONN_REQ_1SLOT_EARLY (Bit 15) */ +#define BLE_BLELL_CONN_CONFIG_CONN_REQ_1SLOT_EARLY_Msk (0x8000UL) /*!< BLE_BLELL CONN_CONFIG: CONN_REQ_1SLOT_EARLY (Bitfield-Mask: 0x01)*/ +/* ================================================= BLE_BLELL.CONN_PARAM1 ================================================= */ +#define BLE_BLELL_CONN_PARAM1_SCA_PARAM_Pos (0UL) /*!< BLE_BLELL CONN_PARAM1: SCA_PARAM (Bit 0) */ +#define BLE_BLELL_CONN_PARAM1_SCA_PARAM_Msk (0x7UL) /*!< BLE_BLELL CONN_PARAM1: SCA_PARAM (Bitfield-Mask: 0x07) */ +#define BLE_BLELL_CONN_PARAM1_HOP_INCREMENT_PARAM_Pos (3UL) /*!< BLE_BLELL CONN_PARAM1: HOP_INCREMENT_PARAM (Bit 3) */ +#define BLE_BLELL_CONN_PARAM1_HOP_INCREMENT_PARAM_Msk (0xf8UL) /*!< BLE_BLELL CONN_PARAM1: HOP_INCREMENT_PARAM (Bitfield-Mask: 0x1f)*/ +#define BLE_BLELL_CONN_PARAM1_CRC_INIT_L_Pos (8UL) /*!< BLE_BLELL CONN_PARAM1: CRC_INIT_L (Bit 8) */ +#define BLE_BLELL_CONN_PARAM1_CRC_INIT_L_Msk (0xff00UL) /*!< BLE_BLELL CONN_PARAM1: CRC_INIT_L (Bitfield-Mask: 0xff) */ +/* ================================================= BLE_BLELL.CONN_PARAM2 ================================================= */ +#define BLE_BLELL_CONN_PARAM2_CRC_INIT_H_Pos (0UL) /*!< BLE_BLELL CONN_PARAM2: CRC_INIT_H (Bit 0) */ +#define BLE_BLELL_CONN_PARAM2_CRC_INIT_H_Msk (0xffffUL) /*!< BLE_BLELL CONN_PARAM2: CRC_INIT_H (Bitfield-Mask: 0xffff) */ +/* =============================================== BLE_BLELL.CONN_INTR_MASK ================================================ */ +#define BLE_BLELL_CONN_INTR_MASK_CONN_CL_INT_EN_Pos (0UL) /*!< BLE_BLELL CONN_INTR_MASK: CONN_CL_INT_EN (Bit 0) */ +#define BLE_BLELL_CONN_INTR_MASK_CONN_CL_INT_EN_Msk (0x1UL) /*!< BLE_BLELL CONN_INTR_MASK: CONN_CL_INT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_CONN_ESTB_INT_EN_Pos (1UL) /*!< BLE_BLELL CONN_INTR_MASK: CONN_ESTB_INT_EN (Bit 1) */ +#define BLE_BLELL_CONN_INTR_MASK_CONN_ESTB_INT_EN_Msk (0x2UL) /*!< BLE_BLELL CONN_INTR_MASK: CONN_ESTB_INT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_MAP_UPDT_INT_EN_Pos (2UL) /*!< BLE_BLELL CONN_INTR_MASK: MAP_UPDT_INT_EN (Bit 2) */ +#define BLE_BLELL_CONN_INTR_MASK_MAP_UPDT_INT_EN_Msk (0x4UL) /*!< BLE_BLELL CONN_INTR_MASK: MAP_UPDT_INT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_START_CE_INT_EN_Pos (3UL) /*!< BLE_BLELL CONN_INTR_MASK: START_CE_INT_EN (Bit 3) */ +#define BLE_BLELL_CONN_INTR_MASK_START_CE_INT_EN_Msk (0x8UL) /*!< BLE_BLELL CONN_INTR_MASK: START_CE_INT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_CLOSE_CE_INT_EN_Pos (4UL) /*!< BLE_BLELL CONN_INTR_MASK: CLOSE_CE_INT_EN (Bit 4) */ +#define BLE_BLELL_CONN_INTR_MASK_CLOSE_CE_INT_EN_Msk (0x10UL) /*!< BLE_BLELL CONN_INTR_MASK: CLOSE_CE_INT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_CE_TX_ACK_INT_EN_Pos (5UL) /*!< BLE_BLELL CONN_INTR_MASK: CE_TX_ACK_INT_EN (Bit 5) */ +#define BLE_BLELL_CONN_INTR_MASK_CE_TX_ACK_INT_EN_Msk (0x20UL) /*!< BLE_BLELL CONN_INTR_MASK: CE_TX_ACK_INT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_CE_RX_INT_EN_Pos (6UL) /*!< BLE_BLELL CONN_INTR_MASK: CE_RX_INT_EN (Bit 6) */ +#define BLE_BLELL_CONN_INTR_MASK_CE_RX_INT_EN_Msk (0x40UL) /*!< BLE_BLELL CONN_INTR_MASK: CE_RX_INT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_CONN_UPDATE_INTR_EN_Pos (7UL) /*!< BLE_BLELL CONN_INTR_MASK: CONN_UPDATE_INTR_EN (Bit 7) */ +#define BLE_BLELL_CONN_INTR_MASK_CONN_UPDATE_INTR_EN_Msk (0x80UL) /*!< BLE_BLELL CONN_INTR_MASK: CONN_UPDATE_INTR_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_RX_GOOD_PDU_INT_EN_Pos (8UL) /*!< BLE_BLELL CONN_INTR_MASK: RX_GOOD_PDU_INT_EN (Bit 8) */ +#define BLE_BLELL_CONN_INTR_MASK_RX_GOOD_PDU_INT_EN_Msk (0x100UL) /*!< BLE_BLELL CONN_INTR_MASK: RX_GOOD_PDU_INT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_RX_BAD_PDU_INT_EN_Pos (9UL) /*!< BLE_BLELL CONN_INTR_MASK: RX_BAD_PDU_INT_EN (Bit 9) */ +#define BLE_BLELL_CONN_INTR_MASK_RX_BAD_PDU_INT_EN_Msk (0x200UL) /*!< BLE_BLELL CONN_INTR_MASK: RX_BAD_PDU_INT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_PING_TIMER_EXPIRD_INTR_Pos (14UL) /*!< BLE_BLELL CONN_INTR_MASK: PING_TIMER_EXPIRD_INTR (Bit 14)*/ +#define BLE_BLELL_CONN_INTR_MASK_PING_TIMER_EXPIRD_INTR_Msk (0x4000UL) /*!< BLE_BLELL CONN_INTR_MASK: PING_TIMER_EXPIRD_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_INTR_MASK_PING_NEARLY_EXPIRD_INTR_Pos (15UL) /*!< BLE_BLELL CONN_INTR_MASK: PING_NEARLY_EXPIRD_INTR (Bit 15)*/ +#define BLE_BLELL_CONN_INTR_MASK_PING_NEARLY_EXPIRD_INTR_Msk (0x8000UL) /*!< BLE_BLELL CONN_INTR_MASK: PING_NEARLY_EXPIRD_INTR (Bitfield-Mask: 0x01)*/ +/* ============================================ BLE_BLELL.SLAVE_TIMING_CONTROL ============================================= */ +#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_SET_VAL_Pos (0UL) /*!< BLE_BLELL SLAVE_TIMING_CONTROL: SLAVE_TIME_SET_VAL (Bit 0)*/ +#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_SET_VAL_Msk (0xffUL) /*!< BLE_BLELL SLAVE_TIMING_CONTROL: SLAVE_TIME_SET_VAL (Bitfield-Mask: 0xff)*/ +#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_ADJ_VAL_Pos (8UL) /*!< BLE_BLELL SLAVE_TIMING_CONTROL: SLAVE_TIME_ADJ_VAL (Bit 8)*/ +#define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_ADJ_VAL_Msk (0xff00UL) /*!< BLE_BLELL SLAVE_TIMING_CONTROL: SLAVE_TIME_ADJ_VAL (Bitfield-Mask: 0xff)*/ +/* ============================================== BLE_BLELL.RECEIVE_TRIG_CTRL ============================================== */ +#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_THRESHOLD_Pos (0UL) /*!< BLE_BLELL RECEIVE_TRIG_CTRL: ACC_TRIGGER_THRESHOLD (Bit 0)*/ +#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_THRESHOLD_Msk (0x3fUL) /*!< BLE_BLELL RECEIVE_TRIG_CTRL: ACC_TRIGGER_THRESHOLD (Bitfield-Mask: 0x3f)*/ +#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_TIMEOUT_Pos (8UL) /*!< BLE_BLELL RECEIVE_TRIG_CTRL: ACC_TRIGGER_TIMEOUT (Bit 8)*/ +#define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_TIMEOUT_Msk (0xff00UL) /*!< BLE_BLELL RECEIVE_TRIG_CTRL: ACC_TRIGGER_TIMEOUT (Bitfield-Mask: 0xff)*/ +/* ================================================== BLE_BLELL.LL_DBG_1 =================================================== */ +#define BLE_BLELL_LL_DBG_1_CONN_RX_WR_PTR_Pos (0UL) /*!< BLE_BLELL LL_DBG_1: CONN_RX_WR_PTR (Bit 0) */ +#define BLE_BLELL_LL_DBG_1_CONN_RX_WR_PTR_Msk (0x3ffUL) /*!< BLE_BLELL LL_DBG_1: CONN_RX_WR_PTR (Bitfield-Mask: 0x3ff) */ +/* ================================================== BLE_BLELL.LL_DBG_2 =================================================== */ +#define BLE_BLELL_LL_DBG_2_CONN_RX_RD_PTR_Pos (0UL) /*!< BLE_BLELL LL_DBG_2: CONN_RX_RD_PTR (Bit 0) */ +#define BLE_BLELL_LL_DBG_2_CONN_RX_RD_PTR_Msk (0x3ffUL) /*!< BLE_BLELL LL_DBG_2: CONN_RX_RD_PTR (Bitfield-Mask: 0x3ff) */ +/* ================================================== BLE_BLELL.LL_DBG_3 =================================================== */ +#define BLE_BLELL_LL_DBG_3_CONN_RX_WR_PTR_STORE_Pos (0UL) /*!< BLE_BLELL LL_DBG_3: CONN_RX_WR_PTR_STORE (Bit 0) */ +#define BLE_BLELL_LL_DBG_3_CONN_RX_WR_PTR_STORE_Msk (0x3ffUL) /*!< BLE_BLELL LL_DBG_3: CONN_RX_WR_PTR_STORE (Bitfield-Mask: 0x3ff)*/ +/* ================================================== BLE_BLELL.LL_DBG_4 =================================================== */ +#define BLE_BLELL_LL_DBG_4_CONNECTION_FSM_STATE_Pos (0UL) /*!< BLE_BLELL LL_DBG_4: CONNECTION_FSM_STATE (Bit 0) */ +#define BLE_BLELL_LL_DBG_4_CONNECTION_FSM_STATE_Msk (0xfUL) /*!< BLE_BLELL LL_DBG_4: CONNECTION_FSM_STATE (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_LL_DBG_4_SLAVE_LATENCY_FSM_STATE_Pos (4UL) /*!< BLE_BLELL LL_DBG_4: SLAVE_LATENCY_FSM_STATE (Bit 4) */ +#define BLE_BLELL_LL_DBG_4_SLAVE_LATENCY_FSM_STATE_Msk (0x30UL) /*!< BLE_BLELL LL_DBG_4: SLAVE_LATENCY_FSM_STATE (Bitfield-Mask: 0x03)*/ +#define BLE_BLELL_LL_DBG_4_ADVERTISER_FSM_STATE_Pos (6UL) /*!< BLE_BLELL LL_DBG_4: ADVERTISER_FSM_STATE (Bit 6) */ +#define BLE_BLELL_LL_DBG_4_ADVERTISER_FSM_STATE_Msk (0x7c0UL) /*!< BLE_BLELL LL_DBG_4: ADVERTISER_FSM_STATE (Bitfield-Mask: 0x1f)*/ +/* ================================================== BLE_BLELL.LL_DBG_5 =================================================== */ +#define BLE_BLELL_LL_DBG_5_INIT_FSM_STATE_Pos (0UL) /*!< BLE_BLELL LL_DBG_5: INIT_FSM_STATE (Bit 0) */ +#define BLE_BLELL_LL_DBG_5_INIT_FSM_STATE_Msk (0x1fUL) /*!< BLE_BLELL LL_DBG_5: INIT_FSM_STATE (Bitfield-Mask: 0x1f) */ +#define BLE_BLELL_LL_DBG_5_SCAN_FSM_STATE_Pos (5UL) /*!< BLE_BLELL LL_DBG_5: SCAN_FSM_STATE (Bit 5) */ +#define BLE_BLELL_LL_DBG_5_SCAN_FSM_STATE_Msk (0x3e0UL) /*!< BLE_BLELL LL_DBG_5: SCAN_FSM_STATE (Bitfield-Mask: 0x1f) */ +/* ================================================== BLE_BLELL.LL_DBG_6 =================================================== */ +#define BLE_BLELL_LL_DBG_6_ADV_TX_WR_PTR_Pos (0UL) /*!< BLE_BLELL LL_DBG_6: ADV_TX_WR_PTR (Bit 0) */ +#define BLE_BLELL_LL_DBG_6_ADV_TX_WR_PTR_Msk (0xfUL) /*!< BLE_BLELL LL_DBG_6: ADV_TX_WR_PTR (Bitfield-Mask: 0x0f) */ +#define BLE_BLELL_LL_DBG_6_SCAN_RSP_TX_WR_PTR_Pos (4UL) /*!< BLE_BLELL LL_DBG_6: SCAN_RSP_TX_WR_PTR (Bit 4) */ +#define BLE_BLELL_LL_DBG_6_SCAN_RSP_TX_WR_PTR_Msk (0xf0UL) /*!< BLE_BLELL LL_DBG_6: SCAN_RSP_TX_WR_PTR (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_LL_DBG_6_ADV_TX_RD_PTR_Pos (8UL) /*!< BLE_BLELL LL_DBG_6: ADV_TX_RD_PTR (Bit 8) */ +#define BLE_BLELL_LL_DBG_6_ADV_TX_RD_PTR_Msk (0x3f00UL) /*!< BLE_BLELL LL_DBG_6: ADV_TX_RD_PTR (Bitfield-Mask: 0x3f) */ +/* ================================================== BLE_BLELL.LL_DBG_7 =================================================== */ +#define BLE_BLELL_LL_DBG_7_ADV_RX_WR_PTR_Pos (0UL) /*!< BLE_BLELL LL_DBG_7: ADV_RX_WR_PTR (Bit 0) */ +#define BLE_BLELL_LL_DBG_7_ADV_RX_WR_PTR_Msk (0x7fUL) /*!< BLE_BLELL LL_DBG_7: ADV_RX_WR_PTR (Bitfield-Mask: 0x7f) */ +#define BLE_BLELL_LL_DBG_7_ADV_RX_RD_PTR_Pos (7UL) /*!< BLE_BLELL LL_DBG_7: ADV_RX_RD_PTR (Bit 7) */ +#define BLE_BLELL_LL_DBG_7_ADV_RX_RD_PTR_Msk (0x3f80UL) /*!< BLE_BLELL LL_DBG_7: ADV_RX_RD_PTR (Bitfield-Mask: 0x7f) */ +/* ================================================== BLE_BLELL.LL_DBG_8 =================================================== */ +#define BLE_BLELL_LL_DBG_8_ADV_RX_WR_PTR_STORE_Pos (0UL) /*!< BLE_BLELL LL_DBG_8: ADV_RX_WR_PTR_STORE (Bit 0) */ +#define BLE_BLELL_LL_DBG_8_ADV_RX_WR_PTR_STORE_Msk (0x7fUL) /*!< BLE_BLELL LL_DBG_8: ADV_RX_WR_PTR_STORE (Bitfield-Mask: 0x7f)*/ +#define BLE_BLELL_LL_DBG_8_WLF_PTR_Pos (7UL) /*!< BLE_BLELL LL_DBG_8: WLF_PTR (Bit 7) */ +#define BLE_BLELL_LL_DBG_8_WLF_PTR_Msk (0x3f80UL) /*!< BLE_BLELL LL_DBG_8: WLF_PTR (Bitfield-Mask: 0x7f) */ +/* ================================================== BLE_BLELL.LL_DBG_9 =================================================== */ +#define BLE_BLELL_LL_DBG_9_WINDOW_WIDEN_Pos (0UL) /*!< BLE_BLELL LL_DBG_9: WINDOW_WIDEN (Bit 0) */ +#define BLE_BLELL_LL_DBG_9_WINDOW_WIDEN_Msk (0xffffUL) /*!< BLE_BLELL LL_DBG_9: WINDOW_WIDEN (Bitfield-Mask: 0xffff) */ +/* ================================================== BLE_BLELL.LL_DBG_10 ================================================== */ +#define BLE_BLELL_LL_DBG_10_RF_CHANNEL_NUM_Pos (0UL) /*!< BLE_BLELL LL_DBG_10: RF_CHANNEL_NUM (Bit 0) */ +#define BLE_BLELL_LL_DBG_10_RF_CHANNEL_NUM_Msk (0x3fUL) /*!< BLE_BLELL LL_DBG_10: RF_CHANNEL_NUM (Bitfield-Mask: 0x3f) */ +/* ============================================== BLE_BLELL.PEER_ADDR_INIT_L =============================================== */ +#define BLE_BLELL_PEER_ADDR_INIT_L_PEER_ADDR_L_Pos (0UL) /*!< BLE_BLELL PEER_ADDR_INIT_L: PEER_ADDR_L (Bit 0) */ +#define BLE_BLELL_PEER_ADDR_INIT_L_PEER_ADDR_L_Msk (0xffffUL) /*!< BLE_BLELL PEER_ADDR_INIT_L: PEER_ADDR_L (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_BLELL.PEER_ADDR_INIT_M =============================================== */ +#define BLE_BLELL_PEER_ADDR_INIT_M_PEER_ADDR_M_Pos (0UL) /*!< BLE_BLELL PEER_ADDR_INIT_M: PEER_ADDR_M (Bit 0) */ +#define BLE_BLELL_PEER_ADDR_INIT_M_PEER_ADDR_M_Msk (0xffffUL) /*!< BLE_BLELL PEER_ADDR_INIT_M: PEER_ADDR_M (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_BLELL.PEER_ADDR_INIT_H =============================================== */ +#define BLE_BLELL_PEER_ADDR_INIT_H_PEER_ADDR_H_Pos (0UL) /*!< BLE_BLELL PEER_ADDR_INIT_H: PEER_ADDR_H (Bit 0) */ +#define BLE_BLELL_PEER_ADDR_INIT_H_PEER_ADDR_H_Msk (0xffffUL) /*!< BLE_BLELL PEER_ADDR_INIT_H: PEER_ADDR_H (Bitfield-Mask: 0xffff)*/ +/* =========================================== BLE_BLELL.INIT_WINDOW_TIMER_CTRL ============================================ */ +#define BLE_BLELL_INIT_WINDOW_TIMER_CTRL_INIT_WINDOW_OFFSET_SEL_Pos (0UL) /*!< BLE_BLELL INIT_WINDOW_TIMER_CTRL: INIT_WINDOW_OFFSET_SEL (Bit 0)*/ +#define BLE_BLELL_INIT_WINDOW_TIMER_CTRL_INIT_WINDOW_OFFSET_SEL_Msk (0x1UL) /*!< BLE_BLELL INIT_WINDOW_TIMER_CTRL: INIT_WINDOW_OFFSET_SEL (Bitfield-Mask: 0x01)*/ +/* =============================================== BLE_BLELL.CONN_CONFIG_EXT =============================================== */ +#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_2SLOT_EARLY_Pos (0UL) /*!< BLE_BLELL CONN_CONFIG_EXT: CONN_REQ_2SLOT_EARLY (Bit 0) */ +#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_2SLOT_EARLY_Msk (0x1UL) /*!< BLE_BLELL CONN_CONFIG_EXT: CONN_REQ_2SLOT_EARLY (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_3SLOT_EARLY_Pos (1UL) /*!< BLE_BLELL CONN_CONFIG_EXT: CONN_REQ_3SLOT_EARLY (Bit 1) */ +#define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_3SLOT_EARLY_Msk (0x2UL) /*!< BLE_BLELL CONN_CONFIG_EXT: CONN_REQ_3SLOT_EARLY (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_CONFIG_EXT_FW_PKT_RCV_CONN_INDEX_Pos (2UL) /*!< BLE_BLELL CONN_CONFIG_EXT: FW_PKT_RCV_CONN_INDEX (Bit 2)*/ +#define BLE_BLELL_CONN_CONFIG_EXT_FW_PKT_RCV_CONN_INDEX_Msk (0x7cUL) /*!< BLE_BLELL CONN_CONFIG_EXT: FW_PKT_RCV_CONN_INDEX (Bitfield-Mask: 0x1f)*/ +#define BLE_BLELL_CONN_CONFIG_EXT_MMMS_RX_PKT_LIMIT_Pos (8UL) /*!< BLE_BLELL CONN_CONFIG_EXT: MMMS_RX_PKT_LIMIT (Bit 8) */ +#define BLE_BLELL_CONN_CONFIG_EXT_MMMS_RX_PKT_LIMIT_Msk (0x3f00UL) /*!< BLE_BLELL CONN_CONFIG_EXT: MMMS_RX_PKT_LIMIT (Bitfield-Mask: 0x3f)*/ +#define BLE_BLELL_CONN_CONFIG_EXT_DEBUG_CE_EXPIRE_Pos (14UL) /*!< BLE_BLELL CONN_CONFIG_EXT: DEBUG_CE_EXPIRE (Bit 14) */ +#define BLE_BLELL_CONN_CONFIG_EXT_DEBUG_CE_EXPIRE_Msk (0x4000UL) /*!< BLE_BLELL CONN_CONFIG_EXT: DEBUG_CE_EXPIRE (Bitfield-Mask: 0x01)*/ +/* ================================================= BLE_BLELL.DPLL_CONFIG ================================================= */ +#define BLE_BLELL_DPLL_CONFIG_DPLL_CORREL_CONFIG_Pos (0UL) /*!< BLE_BLELL DPLL_CONFIG: DPLL_CORREL_CONFIG (Bit 0) */ +#define BLE_BLELL_DPLL_CONFIG_DPLL_CORREL_CONFIG_Msk (0xffffUL) /*!< BLE_BLELL DPLL_CONFIG: DPLL_CORREL_CONFIG (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.INIT_NI_VAL ================================================= */ +#define BLE_BLELL_INIT_NI_VAL_INIT_NI_VAL_Pos (0UL) /*!< BLE_BLELL INIT_NI_VAL: INIT_NI_VAL (Bit 0) */ +#define BLE_BLELL_INIT_NI_VAL_INIT_NI_VAL_Msk (0xffffUL) /*!< BLE_BLELL INIT_NI_VAL: INIT_NI_VAL (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_BLELL.INIT_WINDOW_OFFSET ============================================== */ +#define BLE_BLELL_INIT_WINDOW_OFFSET_INIT_WINDOW_NI_Pos (0UL) /*!< BLE_BLELL INIT_WINDOW_OFFSET: INIT_WINDOW_NI (Bit 0) */ +#define BLE_BLELL_INIT_WINDOW_OFFSET_INIT_WINDOW_NI_Msk (0xffffUL) /*!< BLE_BLELL INIT_WINDOW_OFFSET: INIT_WINDOW_NI (Bitfield-Mask: 0xffff)*/ +/* ========================================== BLE_BLELL.INIT_WINDOW_NI_ANCHOR_PT =========================================== */ +#define BLE_BLELL_INIT_WINDOW_NI_ANCHOR_PT_INIT_INT_OFF_CAPT_Pos (0UL) /*!< BLE_BLELL INIT_WINDOW_NI_ANCHOR_PT: INIT_INT_OFF_CAPT (Bit 0)*/ +#define BLE_BLELL_INIT_WINDOW_NI_ANCHOR_PT_INIT_INT_OFF_CAPT_Msk (0xffffUL) /*!< BLE_BLELL INIT_WINDOW_NI_ANCHOR_PT: INIT_INT_OFF_CAPT (Bitfield-Mask: 0xffff)*/ +/* ========================================== BLE_BLELL.CONN_UPDATE_NEW_INTERVAL =========================================== */ +#define BLE_BLELL_CONN_UPDATE_NEW_INTERVAL_CONN_UPDT_INTERVAL_Pos (0UL) /*!< BLE_BLELL CONN_UPDATE_NEW_INTERVAL: CONN_UPDT_INTERVAL (Bit 0)*/ +#define BLE_BLELL_CONN_UPDATE_NEW_INTERVAL_CONN_UPDT_INTERVAL_Msk (0xffffUL) /*!< BLE_BLELL CONN_UPDATE_NEW_INTERVAL: CONN_UPDT_INTERVAL (Bitfield-Mask: 0xffff)*/ +/* =========================================== BLE_BLELL.CONN_UPDATE_NEW_LATENCY =========================================== */ +#define BLE_BLELL_CONN_UPDATE_NEW_LATENCY_CONN_UPDT_SLV_LATENCY_Pos (0UL) /*!< BLE_BLELL CONN_UPDATE_NEW_LATENCY: CONN_UPDT_SLV_LATENCY (Bit 0)*/ +#define BLE_BLELL_CONN_UPDATE_NEW_LATENCY_CONN_UPDT_SLV_LATENCY_Msk (0xffffUL) /*!< BLE_BLELL CONN_UPDATE_NEW_LATENCY: CONN_UPDT_SLV_LATENCY (Bitfield-Mask: 0xffff)*/ +/* =========================================== BLE_BLELL.CONN_UPDATE_NEW_SUP_TO ============================================ */ +#define BLE_BLELL_CONN_UPDATE_NEW_SUP_TO_CONN_UPDT_SUP_TO_Pos (0UL) /*!< BLE_BLELL CONN_UPDATE_NEW_SUP_TO: CONN_UPDT_SUP_TO (Bit 0)*/ +#define BLE_BLELL_CONN_UPDATE_NEW_SUP_TO_CONN_UPDT_SUP_TO_Msk (0xffffUL) /*!< BLE_BLELL CONN_UPDATE_NEW_SUP_TO: CONN_UPDT_SUP_TO (Bitfield-Mask: 0xffff)*/ +/* ========================================= BLE_BLELL.CONN_UPDATE_NEW_SL_INTERVAL ========================================= */ +#define BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL_SL_CONN_INTERVAL_VAL_Pos (0UL) /*!< BLE_BLELL CONN_UPDATE_NEW_SL_INTERVAL: SL_CONN_INTERVAL_VAL (Bit 0)*/ +#define BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL_SL_CONN_INTERVAL_VAL_Msk (0xffffUL) /*!< BLE_BLELL CONN_UPDATE_NEW_SL_INTERVAL: SL_CONN_INTERVAL_VAL (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD0 ================================================ */ +#define BLE_BLELL_CONN_REQ_WORD0_ACCESS_ADDR_LOWER_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD0: ACCESS_ADDR_LOWER (Bit 0) */ +#define BLE_BLELL_CONN_REQ_WORD0_ACCESS_ADDR_LOWER_Msk (0xffffUL) /*!< BLE_BLELL CONN_REQ_WORD0: ACCESS_ADDR_LOWER (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD1 ================================================ */ +#define BLE_BLELL_CONN_REQ_WORD1_ACCESS_ADDR_UPPER_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD1: ACCESS_ADDR_UPPER (Bit 0) */ +#define BLE_BLELL_CONN_REQ_WORD1_ACCESS_ADDR_UPPER_Msk (0xffffUL) /*!< BLE_BLELL CONN_REQ_WORD1: ACCESS_ADDR_UPPER (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD2 ================================================ */ +#define BLE_BLELL_CONN_REQ_WORD2_TX_WINDOW_SIZE_VAL_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD2: TX_WINDOW_SIZE_VAL (Bit 0) */ +#define BLE_BLELL_CONN_REQ_WORD2_TX_WINDOW_SIZE_VAL_Msk (0xffUL) /*!< BLE_BLELL CONN_REQ_WORD2: TX_WINDOW_SIZE_VAL (Bitfield-Mask: 0xff)*/ +#define BLE_BLELL_CONN_REQ_WORD2_CRC_INIT_LOWER_Pos (8UL) /*!< BLE_BLELL CONN_REQ_WORD2: CRC_INIT_LOWER (Bit 8) */ +#define BLE_BLELL_CONN_REQ_WORD2_CRC_INIT_LOWER_Msk (0xff00UL) /*!< BLE_BLELL CONN_REQ_WORD2: CRC_INIT_LOWER (Bitfield-Mask: 0xff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD3 ================================================ */ +#define BLE_BLELL_CONN_REQ_WORD3_CRC_INIT_UPPER_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD3: CRC_INIT_UPPER (Bit 0) */ +#define BLE_BLELL_CONN_REQ_WORD3_CRC_INIT_UPPER_Msk (0xffffUL) /*!< BLE_BLELL CONN_REQ_WORD3: CRC_INIT_UPPER (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD4 ================================================ */ +#define BLE_BLELL_CONN_REQ_WORD4_TX_WINDOW_OFFSET_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD4: TX_WINDOW_OFFSET (Bit 0) */ +#define BLE_BLELL_CONN_REQ_WORD4_TX_WINDOW_OFFSET_Msk (0xffffUL) /*!< BLE_BLELL CONN_REQ_WORD4: TX_WINDOW_OFFSET (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD5 ================================================ */ +#define BLE_BLELL_CONN_REQ_WORD5_CONNECTION_INTERVAL_VAL_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD5: CONNECTION_INTERVAL_VAL (Bit 0)*/ +#define BLE_BLELL_CONN_REQ_WORD5_CONNECTION_INTERVAL_VAL_Msk (0xffffUL) /*!< BLE_BLELL CONN_REQ_WORD5: CONNECTION_INTERVAL_VAL (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD6 ================================================ */ +#define BLE_BLELL_CONN_REQ_WORD6_SLAVE_LATENCY_VAL_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD6: SLAVE_LATENCY_VAL (Bit 0) */ +#define BLE_BLELL_CONN_REQ_WORD6_SLAVE_LATENCY_VAL_Msk (0xffffUL) /*!< BLE_BLELL CONN_REQ_WORD6: SLAVE_LATENCY_VAL (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD7 ================================================ */ +#define BLE_BLELL_CONN_REQ_WORD7_SUPERVISION_TIMEOUT_VAL_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD7: SUPERVISION_TIMEOUT_VAL (Bit 0)*/ +#define BLE_BLELL_CONN_REQ_WORD7_SUPERVISION_TIMEOUT_VAL_Msk (0xffffUL) /*!< BLE_BLELL CONN_REQ_WORD7: SUPERVISION_TIMEOUT_VAL (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD8 ================================================ */ +#define BLE_BLELL_CONN_REQ_WORD8_DATA_CHANNELS_LOWER_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD8: DATA_CHANNELS_LOWER (Bit 0) */ +#define BLE_BLELL_CONN_REQ_WORD8_DATA_CHANNELS_LOWER_Msk (0xffffUL) /*!< BLE_BLELL CONN_REQ_WORD8: DATA_CHANNELS_LOWER (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD9 ================================================ */ +#define BLE_BLELL_CONN_REQ_WORD9_DATA_CHANNELS_MID_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD9: DATA_CHANNELS_MID (Bit 0) */ +#define BLE_BLELL_CONN_REQ_WORD9_DATA_CHANNELS_MID_Msk (0xffffUL) /*!< BLE_BLELL CONN_REQ_WORD9: DATA_CHANNELS_MID (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD10 =============================================== */ +#define BLE_BLELL_CONN_REQ_WORD10_DATA_CHANNELS_UPPER_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD10: DATA_CHANNELS_UPPER (Bit 0) */ +#define BLE_BLELL_CONN_REQ_WORD10_DATA_CHANNELS_UPPER_Msk (0x1fUL) /*!< BLE_BLELL CONN_REQ_WORD10: DATA_CHANNELS_UPPER (Bitfield-Mask: 0x1f)*/ +/* =============================================== BLE_BLELL.CONN_REQ_WORD11 =============================================== */ +#define BLE_BLELL_CONN_REQ_WORD11_HOP_INCREMENT_2_Pos (0UL) /*!< BLE_BLELL CONN_REQ_WORD11: HOP_INCREMENT_2 (Bit 0) */ +#define BLE_BLELL_CONN_REQ_WORD11_HOP_INCREMENT_2_Msk (0x1fUL) /*!< BLE_BLELL CONN_REQ_WORD11: HOP_INCREMENT_2 (Bitfield-Mask: 0x1f)*/ +#define BLE_BLELL_CONN_REQ_WORD11_SCA_2_Pos (5UL) /*!< BLE_BLELL CONN_REQ_WORD11: SCA_2 (Bit 5) */ +#define BLE_BLELL_CONN_REQ_WORD11_SCA_2_Msk (0xe0UL) /*!< BLE_BLELL CONN_REQ_WORD11: SCA_2 (Bitfield-Mask: 0x07) */ +/* =============================================== BLE_BLELL.PDU_RESP_TIMER ================================================ */ +#define BLE_BLELL_PDU_RESP_TIMER_PDU_RESP_TIME_VAL_Pos (0UL) /*!< BLE_BLELL PDU_RESP_TIMER: PDU_RESP_TIME_VAL (Bit 0) */ +#define BLE_BLELL_PDU_RESP_TIMER_PDU_RESP_TIME_VAL_Msk (0xffffUL) /*!< BLE_BLELL PDU_RESP_TIMER: PDU_RESP_TIME_VAL (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_BLELL.NEXT_RESP_TIMER_EXP ============================================= */ +#define BLE_BLELL_NEXT_RESP_TIMER_EXP_NEXT_RESPONSE_INSTANT_Pos (0UL) /*!< BLE_BLELL NEXT_RESP_TIMER_EXP: NEXT_RESPONSE_INSTANT (Bit 0)*/ +#define BLE_BLELL_NEXT_RESP_TIMER_EXP_NEXT_RESPONSE_INSTANT_Msk (0xffffUL) /*!< BLE_BLELL NEXT_RESP_TIMER_EXP: NEXT_RESPONSE_INSTANT (Bitfield-Mask: 0xffff)*/ +/* ================================================= BLE_BLELL.NEXT_SUP_TO ================================================= */ +#define BLE_BLELL_NEXT_SUP_TO_NEXT_TIMEOUT_INSTANT_Pos (0UL) /*!< BLE_BLELL NEXT_SUP_TO: NEXT_TIMEOUT_INSTANT (Bit 0) */ +#define BLE_BLELL_NEXT_SUP_TO_NEXT_TIMEOUT_INSTANT_Msk (0xffffUL) /*!< BLE_BLELL NEXT_SUP_TO: NEXT_TIMEOUT_INSTANT (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_BLELL.LLH_FEATURE_CONFIG ============================================== */ +#define BLE_BLELL_LLH_FEATURE_CONFIG_QUICK_TRANSMIT_Pos (0UL) /*!< BLE_BLELL LLH_FEATURE_CONFIG: QUICK_TRANSMIT (Bit 0) */ +#define BLE_BLELL_LLH_FEATURE_CONFIG_QUICK_TRANSMIT_Msk (0x1UL) /*!< BLE_BLELL LLH_FEATURE_CONFIG: QUICK_TRANSMIT (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LLH_FEATURE_CONFIG_SL_DSM_EN_Pos (1UL) /*!< BLE_BLELL LLH_FEATURE_CONFIG: SL_DSM_EN (Bit 1) */ +#define BLE_BLELL_LLH_FEATURE_CONFIG_SL_DSM_EN_Msk (0x2UL) /*!< BLE_BLELL LLH_FEATURE_CONFIG: SL_DSM_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LLH_FEATURE_CONFIG_US_COUNTER_OFFSET_ADJ_Pos (2UL) /*!< BLE_BLELL LLH_FEATURE_CONFIG: US_COUNTER_OFFSET_ADJ (Bit 2)*/ +#define BLE_BLELL_LLH_FEATURE_CONFIG_US_COUNTER_OFFSET_ADJ_Msk (0x4UL) /*!< BLE_BLELL LLH_FEATURE_CONFIG: US_COUNTER_OFFSET_ADJ (Bitfield-Mask: 0x01)*/ +/* ============================================== BLE_BLELL.WIN_MIN_STEP_SIZE ============================================== */ +#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPDN_Pos (0UL) /*!< BLE_BLELL WIN_MIN_STEP_SIZE: STEPDN (Bit 0) */ +#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPDN_Msk (0xfUL) /*!< BLE_BLELL WIN_MIN_STEP_SIZE: STEPDN (Bitfield-Mask: 0x0f) */ +#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPUP_Pos (4UL) /*!< BLE_BLELL WIN_MIN_STEP_SIZE: STEPUP (Bit 4) */ +#define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPUP_Msk (0xf0UL) /*!< BLE_BLELL WIN_MIN_STEP_SIZE: STEPUP (Bitfield-Mask: 0x0f) */ +#define BLE_BLELL_WIN_MIN_STEP_SIZE_WINDOW_MIN_FW_Pos (8UL) /*!< BLE_BLELL WIN_MIN_STEP_SIZE: WINDOW_MIN_FW (Bit 8) */ +#define BLE_BLELL_WIN_MIN_STEP_SIZE_WINDOW_MIN_FW_Msk (0xff00UL) /*!< BLE_BLELL WIN_MIN_STEP_SIZE: WINDOW_MIN_FW (Bitfield-Mask: 0xff)*/ +/* ================================================= BLE_BLELL.SLV_WIN_ADJ ================================================= */ +#define BLE_BLELL_SLV_WIN_ADJ_SLV_WIN_ADJ_Pos (0UL) /*!< BLE_BLELL SLV_WIN_ADJ: SLV_WIN_ADJ (Bit 0) */ +#define BLE_BLELL_SLV_WIN_ADJ_SLV_WIN_ADJ_Msk (0x7ffUL) /*!< BLE_BLELL SLV_WIN_ADJ: SLV_WIN_ADJ (Bitfield-Mask: 0x7ff) */ +/* ============================================== BLE_BLELL.SL_CONN_INTERVAL =============================================== */ +#define BLE_BLELL_SL_CONN_INTERVAL_SL_CONN_INTERVAL_VAL_Pos (0UL) /*!< BLE_BLELL SL_CONN_INTERVAL: SL_CONN_INTERVAL_VAL (Bit 0)*/ +#define BLE_BLELL_SL_CONN_INTERVAL_SL_CONN_INTERVAL_VAL_Msk (0xffffUL) /*!< BLE_BLELL SL_CONN_INTERVAL: SL_CONN_INTERVAL_VAL (Bitfield-Mask: 0xffff)*/ +/* ============================================= BLE_BLELL.LE_PING_TIMER_ADDR ============================================== */ +#define BLE_BLELL_LE_PING_TIMER_ADDR_CONN_PING_TIMER_ADDR_Pos (0UL) /*!< BLE_BLELL LE_PING_TIMER_ADDR: CONN_PING_TIMER_ADDR (Bit 0)*/ +#define BLE_BLELL_LE_PING_TIMER_ADDR_CONN_PING_TIMER_ADDR_Msk (0xffffUL) /*!< BLE_BLELL LE_PING_TIMER_ADDR: CONN_PING_TIMER_ADDR (Bitfield-Mask: 0xffff)*/ +/* ============================================ BLE_BLELL.LE_PING_TIMER_OFFSET ============================================= */ +#define BLE_BLELL_LE_PING_TIMER_OFFSET_CONN_PING_TIMER_OFFSET_Pos (0UL) /*!< BLE_BLELL LE_PING_TIMER_OFFSET: CONN_PING_TIMER_OFFSET (Bit 0)*/ +#define BLE_BLELL_LE_PING_TIMER_OFFSET_CONN_PING_TIMER_OFFSET_Msk (0xffffUL) /*!< BLE_BLELL LE_PING_TIMER_OFFSET: CONN_PING_TIMER_OFFSET (Bitfield-Mask: 0xffff)*/ +/* =========================================== BLE_BLELL.LE_PING_TIMER_NEXT_EXP ============================================ */ +#define BLE_BLELL_LE_PING_TIMER_NEXT_EXP_CONN_PING_TIMER_NEXT_EXP_Pos (0UL) /*!< BLE_BLELL LE_PING_TIMER_NEXT_EXP: CONN_PING_TIMER_NEXT_EXP (Bit 0)*/ +#define BLE_BLELL_LE_PING_TIMER_NEXT_EXP_CONN_PING_TIMER_NEXT_EXP_Msk (0xffffUL) /*!< BLE_BLELL LE_PING_TIMER_NEXT_EXP: CONN_PING_TIMER_NEXT_EXP (Bitfield-Mask: 0xffff)*/ +/* ========================================== BLE_BLELL.LE_PING_TIMER_WRAP_COUNT =========================================== */ +#define BLE_BLELL_LE_PING_TIMER_WRAP_COUNT_CONN_SEC_CURRENT_WRAP_Pos (0UL) /*!< BLE_BLELL LE_PING_TIMER_WRAP_COUNT: CONN_SEC_CURRENT_WRAP (Bit 0)*/ +#define BLE_BLELL_LE_PING_TIMER_WRAP_COUNT_CONN_SEC_CURRENT_WRAP_Msk (0xffffUL) /*!< BLE_BLELL LE_PING_TIMER_WRAP_COUNT: CONN_SEC_CURRENT_WRAP (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.TX_EN_EXT_DELAY =============================================== */ +#define BLE_BLELL_TX_EN_EXT_DELAY_TXEN_EXT_DELAY_Pos (0UL) /*!< BLE_BLELL TX_EN_EXT_DELAY: TXEN_EXT_DELAY (Bit 0) */ +#define BLE_BLELL_TX_EN_EXT_DELAY_TXEN_EXT_DELAY_Msk (0xfUL) /*!< BLE_BLELL TX_EN_EXT_DELAY: TXEN_EXT_DELAY (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_TX_EN_EXT_DELAY_RXEN_EXT_DELAY_Pos (4UL) /*!< BLE_BLELL TX_EN_EXT_DELAY: RXEN_EXT_DELAY (Bit 4) */ +#define BLE_BLELL_TX_EN_EXT_DELAY_RXEN_EXT_DELAY_Msk (0xf0UL) /*!< BLE_BLELL TX_EN_EXT_DELAY: RXEN_EXT_DELAY (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_TX_EN_EXT_DELAY_DEMOD_2M_COMP_DLY_Pos (8UL) /*!< BLE_BLELL TX_EN_EXT_DELAY: DEMOD_2M_COMP_DLY (Bit 8) */ +#define BLE_BLELL_TX_EN_EXT_DELAY_DEMOD_2M_COMP_DLY_Msk (0xf00UL) /*!< BLE_BLELL TX_EN_EXT_DELAY: DEMOD_2M_COMP_DLY (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_TX_EN_EXT_DELAY_MOD_2M_COMP_DLY_Pos (12UL) /*!< BLE_BLELL TX_EN_EXT_DELAY: MOD_2M_COMP_DLY (Bit 12) */ +#define BLE_BLELL_TX_EN_EXT_DELAY_MOD_2M_COMP_DLY_Msk (0xf000UL) /*!< BLE_BLELL TX_EN_EXT_DELAY: MOD_2M_COMP_DLY (Bitfield-Mask: 0x0f)*/ +/* ============================================== BLE_BLELL.TX_RX_SYNTH_DELAY ============================================== */ +#define BLE_BLELL_TX_RX_SYNTH_DELAY_RX_EN_DELAY_Pos (0UL) /*!< BLE_BLELL TX_RX_SYNTH_DELAY: RX_EN_DELAY (Bit 0) */ +#define BLE_BLELL_TX_RX_SYNTH_DELAY_RX_EN_DELAY_Msk (0xffUL) /*!< BLE_BLELL TX_RX_SYNTH_DELAY: RX_EN_DELAY (Bitfield-Mask: 0xff)*/ +#define BLE_BLELL_TX_RX_SYNTH_DELAY_TX_EN_DELAY_Pos (8UL) /*!< BLE_BLELL TX_RX_SYNTH_DELAY: TX_EN_DELAY (Bit 8) */ +#define BLE_BLELL_TX_RX_SYNTH_DELAY_TX_EN_DELAY_Msk (0xff00UL) /*!< BLE_BLELL TX_RX_SYNTH_DELAY: TX_EN_DELAY (Bitfield-Mask: 0xff)*/ +/* ============================================= BLE_BLELL.EXT_PA_LNA_DLY_CNFG ============================================= */ +#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_LNA_CTL_DELAY_Pos (0UL) /*!< BLE_BLELL EXT_PA_LNA_DLY_CNFG: LNA_CTL_DELAY (Bit 0) */ +#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_LNA_CTL_DELAY_Msk (0xffUL) /*!< BLE_BLELL EXT_PA_LNA_DLY_CNFG: LNA_CTL_DELAY (Bitfield-Mask: 0xff)*/ +#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_PA_CTL_DELAY_Pos (8UL) /*!< BLE_BLELL EXT_PA_LNA_DLY_CNFG: PA_CTL_DELAY (Bit 8) */ +#define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_PA_CTL_DELAY_Msk (0xff00UL) /*!< BLE_BLELL EXT_PA_LNA_DLY_CNFG: PA_CTL_DELAY (Bitfield-Mask: 0xff)*/ +/* ================================================== BLE_BLELL.LL_CONFIG ================================================== */ +#define BLE_BLELL_LL_CONFIG_RSSI_SEL_Pos (0UL) /*!< BLE_BLELL LL_CONFIG: RSSI_SEL (Bit 0) */ +#define BLE_BLELL_LL_CONFIG_RSSI_SEL_Msk (0x1UL) /*!< BLE_BLELL LL_CONFIG: RSSI_SEL (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONFIG_TX_RX_CTRL_SEL_Pos (1UL) /*!< BLE_BLELL LL_CONFIG: TX_RX_CTRL_SEL (Bit 1) */ +#define BLE_BLELL_LL_CONFIG_TX_RX_CTRL_SEL_Msk (0x2UL) /*!< BLE_BLELL LL_CONFIG: TX_RX_CTRL_SEL (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONFIG_TIFS_ENABLE_Pos (2UL) /*!< BLE_BLELL LL_CONFIG: TIFS_ENABLE (Bit 2) */ +#define BLE_BLELL_LL_CONFIG_TIFS_ENABLE_Msk (0x4UL) /*!< BLE_BLELL LL_CONFIG: TIFS_ENABLE (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONFIG_TIMER_LF_SLOT_ENABLE_Pos (3UL) /*!< BLE_BLELL LL_CONFIG: TIMER_LF_SLOT_ENABLE (Bit 3) */ +#define BLE_BLELL_LL_CONFIG_TIMER_LF_SLOT_ENABLE_Msk (0x8UL) /*!< BLE_BLELL LL_CONFIG: TIMER_LF_SLOT_ENABLE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONFIG_RSSI_INTR_SEL_Pos (5UL) /*!< BLE_BLELL LL_CONFIG: RSSI_INTR_SEL (Bit 5) */ +#define BLE_BLELL_LL_CONFIG_RSSI_INTR_SEL_Msk (0x20UL) /*!< BLE_BLELL LL_CONFIG: RSSI_INTR_SEL (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONFIG_RSSI_EARLY_CNFG_Pos (6UL) /*!< BLE_BLELL LL_CONFIG: RSSI_EARLY_CNFG (Bit 6) */ +#define BLE_BLELL_LL_CONFIG_RSSI_EARLY_CNFG_Msk (0x40UL) /*!< BLE_BLELL LL_CONFIG: RSSI_EARLY_CNFG (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONFIG_TX_RX_PIN_DLY_Pos (7UL) /*!< BLE_BLELL LL_CONFIG: TX_RX_PIN_DLY (Bit 7) */ +#define BLE_BLELL_LL_CONFIG_TX_RX_PIN_DLY_Msk (0x80UL) /*!< BLE_BLELL LL_CONFIG: TX_RX_PIN_DLY (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONFIG_TX_PA_PWR_LVL_TYPE_Pos (8UL) /*!< BLE_BLELL LL_CONFIG: TX_PA_PWR_LVL_TYPE (Bit 8) */ +#define BLE_BLELL_LL_CONFIG_TX_PA_PWR_LVL_TYPE_Msk (0x100UL) /*!< BLE_BLELL LL_CONFIG: TX_PA_PWR_LVL_TYPE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONFIG_RSSI_ENERGY_RD_Pos (9UL) /*!< BLE_BLELL LL_CONFIG: RSSI_ENERGY_RD (Bit 9) */ +#define BLE_BLELL_LL_CONFIG_RSSI_ENERGY_RD_Msk (0x200UL) /*!< BLE_BLELL LL_CONFIG: RSSI_ENERGY_RD (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONFIG_RSSI_EACH_PKT_Pos (10UL) /*!< BLE_BLELL LL_CONFIG: RSSI_EACH_PKT (Bit 10) */ +#define BLE_BLELL_LL_CONFIG_RSSI_EACH_PKT_Msk (0x400UL) /*!< BLE_BLELL LL_CONFIG: RSSI_EACH_PKT (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONFIG_FORCE_TRIG_RCB_UPDATE_Pos (11UL) /*!< BLE_BLELL LL_CONFIG: FORCE_TRIG_RCB_UPDATE (Bit 11) */ +#define BLE_BLELL_LL_CONFIG_FORCE_TRIG_RCB_UPDATE_Msk (0x800UL) /*!< BLE_BLELL LL_CONFIG: FORCE_TRIG_RCB_UPDATE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONFIG_CHECK_DUP_CONN_Pos (12UL) /*!< BLE_BLELL LL_CONFIG: CHECK_DUP_CONN (Bit 12) */ +#define BLE_BLELL_LL_CONFIG_CHECK_DUP_CONN_Msk (0x1000UL) /*!< BLE_BLELL LL_CONFIG: CHECK_DUP_CONN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONFIG_MULTI_ENGINE_LPM_Pos (13UL) /*!< BLE_BLELL LL_CONFIG: MULTI_ENGINE_LPM (Bit 13) */ +#define BLE_BLELL_LL_CONFIG_MULTI_ENGINE_LPM_Msk (0x2000UL) /*!< BLE_BLELL LL_CONFIG: MULTI_ENGINE_LPM (Bitfield-Mask: 0x01)*/ +/* ================================================= BLE_BLELL.LL_CONTROL ================================================== */ +#define BLE_BLELL_LL_CONTROL_PRIV_1_2_Pos (0UL) /*!< BLE_BLELL LL_CONTROL: PRIV_1_2 (Bit 0) */ +#define BLE_BLELL_LL_CONTROL_PRIV_1_2_Msk (0x1UL) /*!< BLE_BLELL LL_CONTROL: PRIV_1_2 (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONTROL_DLE_Pos (1UL) /*!< BLE_BLELL LL_CONTROL: DLE (Bit 1) */ +#define BLE_BLELL_LL_CONTROL_DLE_Msk (0x2UL) /*!< BLE_BLELL LL_CONTROL: DLE (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONTROL_WL_READ_AS_MEM_Pos (2UL) /*!< BLE_BLELL LL_CONTROL: WL_READ_AS_MEM (Bit 2) */ +#define BLE_BLELL_LL_CONTROL_WL_READ_AS_MEM_Msk (0x4UL) /*!< BLE_BLELL LL_CONTROL: WL_READ_AS_MEM (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL_Pos (3UL) /*!< BLE_BLELL LL_CONTROL: ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL (Bit 3)*/ +#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL_Msk (0x8UL) /*!< BLE_BLELL LL_CONTROL: ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONTROL_HW_RSLV_LIST_FULL_Pos (4UL) /*!< BLE_BLELL LL_CONTROL: HW_RSLV_LIST_FULL (Bit 4) */ +#define BLE_BLELL_LL_CONTROL_HW_RSLV_LIST_FULL_Msk (0x10UL) /*!< BLE_BLELL LL_CONTROL: HW_RSLV_LIST_FULL (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONTROL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV_Pos (5UL) /*!< BLE_BLELL LL_CONTROL: RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV (Bit 5)*/ +#define BLE_BLELL_LL_CONTROL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV_Msk (0x20UL) /*!< BLE_BLELL LL_CONTROL: RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONTROL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV_Pos (6UL) /*!< BLE_BLELL LL_CONTROL: RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV (Bit 6)*/ +#define BLE_BLELL_LL_CONTROL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV_Msk (0x40UL) /*!< BLE_BLELL LL_CONTROL: RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN_Pos (7UL) /*!< BLE_BLELL LL_CONTROL: RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN (Bit 7)*/ +#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN_Msk (0x80UL) /*!< BLE_BLELL LL_CONTROL: RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI_Pos (8UL) /*!< BLE_BLELL LL_CONTROL: RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI (Bit 8)*/ +#define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI_Msk (0x100UL) /*!< BLE_BLELL LL_CONTROL: RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONTROL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI_Pos (9UL) /*!< BLE_BLELL LL_CONTROL: RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI (Bit 9)*/ +#define BLE_BLELL_LL_CONTROL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI_Msk (0x200UL) /*!< BLE_BLELL LL_CONTROL: RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONTROL_PRIV_1_2_ADV_Pos (10UL) /*!< BLE_BLELL LL_CONTROL: PRIV_1_2_ADV (Bit 10) */ +#define BLE_BLELL_LL_CONTROL_PRIV_1_2_ADV_Msk (0x400UL) /*!< BLE_BLELL LL_CONTROL: PRIV_1_2_ADV (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONTROL_PRIV_1_2_SCAN_Pos (11UL) /*!< BLE_BLELL LL_CONTROL: PRIV_1_2_SCAN (Bit 11) */ +#define BLE_BLELL_LL_CONTROL_PRIV_1_2_SCAN_Msk (0x800UL) /*!< BLE_BLELL LL_CONTROL: PRIV_1_2_SCAN (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONTROL_PRIV_1_2_INIT_Pos (12UL) /*!< BLE_BLELL LL_CONTROL: PRIV_1_2_INIT (Bit 12) */ +#define BLE_BLELL_LL_CONTROL_PRIV_1_2_INIT_Msk (0x1000UL) /*!< BLE_BLELL LL_CONTROL: PRIV_1_2_INIT (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_LL_CONTROL_EN_CONN_RX_EN_MOD_Pos (13UL) /*!< BLE_BLELL LL_CONTROL: EN_CONN_RX_EN_MOD (Bit 13) */ +#define BLE_BLELL_LL_CONTROL_EN_CONN_RX_EN_MOD_Msk (0x2000UL) /*!< BLE_BLELL LL_CONTROL: EN_CONN_RX_EN_MOD (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONTROL_SLV_CONN_PEER_RPA_NOT_RSLVD_Pos (14UL) /*!< BLE_BLELL LL_CONTROL: SLV_CONN_PEER_RPA_NOT_RSLVD (Bit 14)*/ +#define BLE_BLELL_LL_CONTROL_SLV_CONN_PEER_RPA_NOT_RSLVD_Msk (0x4000UL) /*!< BLE_BLELL LL_CONTROL: SLV_CONN_PEER_RPA_NOT_RSLVD (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_FLUSH_Pos (15UL) /*!< BLE_BLELL LL_CONTROL: ADVCH_FIFO_FLUSH (Bit 15) */ +#define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_FLUSH_Msk (0x8000UL) /*!< BLE_BLELL LL_CONTROL: ADVCH_FIFO_FLUSH (Bitfield-Mask: 0x01)*/ +/* ================================================ BLE_BLELL.DEV_PA_ADDR_L ================================================ */ +#define BLE_BLELL_DEV_PA_ADDR_L_DEV_PA_ADDR_L_Pos (0UL) /*!< BLE_BLELL DEV_PA_ADDR_L: DEV_PA_ADDR_L (Bit 0) */ +#define BLE_BLELL_DEV_PA_ADDR_L_DEV_PA_ADDR_L_Msk (0xffffUL) /*!< BLE_BLELL DEV_PA_ADDR_L: DEV_PA_ADDR_L (Bitfield-Mask: 0xffff)*/ +/* ================================================ BLE_BLELL.DEV_PA_ADDR_M ================================================ */ +#define BLE_BLELL_DEV_PA_ADDR_M_DEV_PA_ADDR_M_Pos (0UL) /*!< BLE_BLELL DEV_PA_ADDR_M: DEV_PA_ADDR_M (Bit 0) */ +#define BLE_BLELL_DEV_PA_ADDR_M_DEV_PA_ADDR_M_Msk (0xffffUL) /*!< BLE_BLELL DEV_PA_ADDR_M: DEV_PA_ADDR_M (Bitfield-Mask: 0xffff)*/ +/* ================================================ BLE_BLELL.DEV_PA_ADDR_H ================================================ */ +#define BLE_BLELL_DEV_PA_ADDR_H_DEV_PA_ADDR_H_Pos (0UL) /*!< BLE_BLELL DEV_PA_ADDR_H: DEV_PA_ADDR_H (Bit 0) */ +#define BLE_BLELL_DEV_PA_ADDR_H_DEV_PA_ADDR_H_Msk (0xffffUL) /*!< BLE_BLELL DEV_PA_ADDR_H: DEV_PA_ADDR_H (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_BLELL.RSLV_LIST_ENABLE =============================================== */ +#define BLE_BLELL_RSLV_LIST_ENABLE_VALID_ENTRY_Pos (0UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: VALID_ENTRY (Bit 0) */ +#define BLE_BLELL_RSLV_LIST_ENABLE_VALID_ENTRY_Msk (0x1UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: VALID_ENTRY (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_IRK_SET_Pos (1UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: PEER_ADDR_IRK_SET (Bit 1) */ +#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_IRK_SET_Msk (0x2UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: PEER_ADDR_IRK_SET (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_IRK_SET_RX_Pos (2UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: SELF_ADDR_IRK_SET_RX (Bit 2)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_IRK_SET_RX_Msk (0x4UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: SELF_ADDR_IRK_SET_RX (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_WHITELISTED_PEER_Pos (3UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: WHITELISTED_PEER (Bit 3) */ +#define BLE_BLELL_RSLV_LIST_ENABLE_WHITELISTED_PEER_Msk (0x8UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: WHITELISTED_PEER (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_TYPE_Pos (4UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: PEER_ADDR_TYPE (Bit 4) */ +#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_TYPE_Msk (0x10UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: PEER_ADDR_TYPE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_RPA_VAL_Pos (5UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: PEER_ADDR_RPA_VAL (Bit 5) */ +#define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_RPA_VAL_Msk (0x20UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: PEER_ADDR_RPA_VAL (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_RXD_RPA_VAL_Pos (6UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: SELF_ADDR_RXD_RPA_VAL (Bit 6)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_RXD_RPA_VAL_Msk (0x40UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: SELF_ADDR_RXD_RPA_VAL (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TX_RPA_VAL_Pos (7UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: SELF_ADDR_TX_RPA_VAL (Bit 7)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TX_RPA_VAL_Msk (0x80UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: SELF_ADDR_TX_RPA_VAL (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_INIT_RPA_SEL_Pos (8UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: SELF_ADDR_INIT_RPA_SEL (Bit 8)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_INIT_RPA_SEL_Msk (0x100UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: SELF_ADDR_INIT_RPA_SEL (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TYPE_TX_Pos (9UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: SELF_ADDR_TYPE_TX (Bit 9) */ +#define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TYPE_TX_Msk (0x200UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: SELF_ADDR_TYPE_TX (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_RSLV_LIST_ENABLE_ENTRY_CONNECTED_Pos (10UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: ENTRY_CONNECTED (Bit 10) */ +#define BLE_BLELL_RSLV_LIST_ENABLE_ENTRY_CONNECTED_Msk (0x400UL) /*!< BLE_BLELL RSLV_LIST_ENABLE: ENTRY_CONNECTED (Bitfield-Mask: 0x01)*/ +/* ============================================ BLE_BLELL.WL_CONNECTION_STATUS ============================================= */ +#define BLE_BLELL_WL_CONNECTION_STATUS_WL_ENTRY_CONNECTED_Pos (0UL) /*!< BLE_BLELL WL_CONNECTION_STATUS: WL_ENTRY_CONNECTED (Bit 0)*/ +#define BLE_BLELL_WL_CONNECTION_STATUS_WL_ENTRY_CONNECTED_Msk (0xffffUL) /*!< BLE_BLELL WL_CONNECTION_STATUS: WL_ENTRY_CONNECTED (Bitfield-Mask: 0xffff)*/ +/* ========================================== BLE_BLELL.CONN_RXMEM_BASE_ADDR_DLE =========================================== */ +#define BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE_CONN_RX_MEM_BASE_ADDR_DLE_Pos (0UL) /*!< BLE_BLELL CONN_RXMEM_BASE_ADDR_DLE: CONN_RX_MEM_BASE_ADDR_DLE (Bit 0)*/ +#define BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE_CONN_RX_MEM_BASE_ADDR_DLE_Msk (0xffffffffUL) /*!< BLE_BLELL CONN_RXMEM_BASE_ADDR_DLE: CONN_RX_MEM_BASE_ADDR_DLE (Bitfield-Mask: 0xffffffff)*/ +/* ========================================== BLE_BLELL.CONN_TXMEM_BASE_ADDR_DLE =========================================== */ +#define BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE_CONN_TX_MEM_BASE_ADDR_DLE_Pos (0UL) /*!< BLE_BLELL CONN_TXMEM_BASE_ADDR_DLE: CONN_TX_MEM_BASE_ADDR_DLE (Bit 0)*/ +#define BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE_CONN_TX_MEM_BASE_ADDR_DLE_Msk (0xffffffffUL) /*!< BLE_BLELL CONN_TXMEM_BASE_ADDR_DLE: CONN_TX_MEM_BASE_ADDR_DLE (Bitfield-Mask: 0xffffffff)*/ +/* ========================================= BLE_BLELL.CONN_1_PARAM_MEM_BASE_ADDR ========================================== */ +#define BLE_BLELL_CONN_1_PARAM_MEM_BASE_ADDR_CONN_1_PARAM_Pos (0UL) /*!< BLE_BLELL CONN_1_PARAM_MEM_BASE_ADDR: CONN_1_PARAM (Bit 0)*/ +#define BLE_BLELL_CONN_1_PARAM_MEM_BASE_ADDR_CONN_1_PARAM_Msk (0xffffUL) /*!< BLE_BLELL CONN_1_PARAM_MEM_BASE_ADDR: CONN_1_PARAM (Bitfield-Mask: 0xffff)*/ +/* ========================================= BLE_BLELL.CONN_2_PARAM_MEM_BASE_ADDR ========================================== */ +#define BLE_BLELL_CONN_2_PARAM_MEM_BASE_ADDR_CONN_2_PARAM_Pos (0UL) /*!< BLE_BLELL CONN_2_PARAM_MEM_BASE_ADDR: CONN_2_PARAM (Bit 0)*/ +#define BLE_BLELL_CONN_2_PARAM_MEM_BASE_ADDR_CONN_2_PARAM_Msk (0xffffUL) /*!< BLE_BLELL CONN_2_PARAM_MEM_BASE_ADDR: CONN_2_PARAM (Bitfield-Mask: 0xffff)*/ +/* ========================================= BLE_BLELL.CONN_3_PARAM_MEM_BASE_ADDR ========================================== */ +#define BLE_BLELL_CONN_3_PARAM_MEM_BASE_ADDR_CONN_3_PARAM_Pos (0UL) /*!< BLE_BLELL CONN_3_PARAM_MEM_BASE_ADDR: CONN_3_PARAM (Bit 0)*/ +#define BLE_BLELL_CONN_3_PARAM_MEM_BASE_ADDR_CONN_3_PARAM_Msk (0xffffUL) /*!< BLE_BLELL CONN_3_PARAM_MEM_BASE_ADDR: CONN_3_PARAM (Bitfield-Mask: 0xffff)*/ +/* ========================================= BLE_BLELL.CONN_4_PARAM_MEM_BASE_ADDR ========================================== */ +#define BLE_BLELL_CONN_4_PARAM_MEM_BASE_ADDR_CONN_4_PARAM_Pos (0UL) /*!< BLE_BLELL CONN_4_PARAM_MEM_BASE_ADDR: CONN_4_PARAM (Bit 0)*/ +#define BLE_BLELL_CONN_4_PARAM_MEM_BASE_ADDR_CONN_4_PARAM_Msk (0xffffUL) /*!< BLE_BLELL CONN_4_PARAM_MEM_BASE_ADDR: CONN_4_PARAM (Bitfield-Mask: 0xffff)*/ +/* ================================================== BLE_BLELL.NI_TIMER =================================================== */ +#define BLE_BLELL_NI_TIMER_NI_TIMER_Pos (0UL) /*!< BLE_BLELL NI_TIMER: NI_TIMER (Bit 0) */ +#define BLE_BLELL_NI_TIMER_NI_TIMER_Msk (0xffffUL) /*!< BLE_BLELL NI_TIMER: NI_TIMER (Bitfield-Mask: 0xffff) */ +/* ================================================== BLE_BLELL.US_OFFSET ================================================== */ +#define BLE_BLELL_US_OFFSET_US_OFFSET_SLOT_BOUNDARY_Pos (0UL) /*!< BLE_BLELL US_OFFSET: US_OFFSET_SLOT_BOUNDARY (Bit 0) */ +#define BLE_BLELL_US_OFFSET_US_OFFSET_SLOT_BOUNDARY_Msk (0x3ffUL) /*!< BLE_BLELL US_OFFSET: US_OFFSET_SLOT_BOUNDARY (Bitfield-Mask: 0x3ff)*/ +/* ================================================== BLE_BLELL.NEXT_CONN ================================================== */ +#define BLE_BLELL_NEXT_CONN_NEXT_CONN_INDEX_Pos (0UL) /*!< BLE_BLELL NEXT_CONN: NEXT_CONN_INDEX (Bit 0) */ +#define BLE_BLELL_NEXT_CONN_NEXT_CONN_INDEX_Msk (0x1fUL) /*!< BLE_BLELL NEXT_CONN: NEXT_CONN_INDEX (Bitfield-Mask: 0x1f)*/ +#define BLE_BLELL_NEXT_CONN_NEXT_CONN_TYPE_Pos (5UL) /*!< BLE_BLELL NEXT_CONN: NEXT_CONN_TYPE (Bit 5) */ +#define BLE_BLELL_NEXT_CONN_NEXT_CONN_TYPE_Msk (0x20UL) /*!< BLE_BLELL NEXT_CONN: NEXT_CONN_TYPE (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_NEXT_CONN_NI_VALID_Pos (6UL) /*!< BLE_BLELL NEXT_CONN: NI_VALID (Bit 6) */ +#define BLE_BLELL_NEXT_CONN_NI_VALID_Msk (0x40UL) /*!< BLE_BLELL NEXT_CONN: NI_VALID (Bitfield-Mask: 0x01) */ +/* ================================================== BLE_BLELL.NI_ABORT =================================================== */ +#define BLE_BLELL_NI_ABORT_NI_ABORT_Pos (0UL) /*!< BLE_BLELL NI_ABORT: NI_ABORT (Bit 0) */ +#define BLE_BLELL_NI_ABORT_NI_ABORT_Msk (0x1UL) /*!< BLE_BLELL NI_ABORT: NI_ABORT (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_NI_ABORT_ABORT_ACK_Pos (1UL) /*!< BLE_BLELL NI_ABORT: ABORT_ACK (Bit 1) */ +#define BLE_BLELL_NI_ABORT_ABORT_ACK_Msk (0x2UL) /*!< BLE_BLELL NI_ABORT: ABORT_ACK (Bitfield-Mask: 0x01) */ +/* =============================================== BLE_BLELL.CONN_NI_STATUS ================================================ */ +#define BLE_BLELL_CONN_NI_STATUS_CONN_NI_Pos (0UL) /*!< BLE_BLELL CONN_NI_STATUS: CONN_NI (Bit 0) */ +#define BLE_BLELL_CONN_NI_STATUS_CONN_NI_Msk (0xffffUL) /*!< BLE_BLELL CONN_NI_STATUS: CONN_NI (Bitfield-Mask: 0xffff) */ +/* ============================================= BLE_BLELL.NEXT_SUP_TO_STATUS ============================================== */ +#define BLE_BLELL_NEXT_SUP_TO_STATUS_NEXT_SUP_TO_Pos (0UL) /*!< BLE_BLELL NEXT_SUP_TO_STATUS: NEXT_SUP_TO (Bit 0) */ +#define BLE_BLELL_NEXT_SUP_TO_STATUS_NEXT_SUP_TO_Msk (0xffffUL) /*!< BLE_BLELL NEXT_SUP_TO_STATUS: NEXT_SUP_TO (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_BLELL.MMMS_CONN_STATUS =============================================== */ +#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_INDEX_Pos (0UL) /*!< BLE_BLELL MMMS_CONN_STATUS: CURR_CONN_INDEX (Bit 0) */ +#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_INDEX_Msk (0x1fUL) /*!< BLE_BLELL MMMS_CONN_STATUS: CURR_CONN_INDEX (Bitfield-Mask: 0x1f)*/ +#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_TYPE_Pos (5UL) /*!< BLE_BLELL MMMS_CONN_STATUS: CURR_CONN_TYPE (Bit 5) */ +#define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_TYPE_Msk (0x20UL) /*!< BLE_BLELL MMMS_CONN_STATUS: CURR_CONN_TYPE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_CONN_STATUS_SN_CURR_Pos (6UL) /*!< BLE_BLELL MMMS_CONN_STATUS: SN_CURR (Bit 6) */ +#define BLE_BLELL_MMMS_CONN_STATUS_SN_CURR_Msk (0x40UL) /*!< BLE_BLELL MMMS_CONN_STATUS: SN_CURR (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_MMMS_CONN_STATUS_NESN_CURR_Pos (7UL) /*!< BLE_BLELL MMMS_CONN_STATUS: NESN_CURR (Bit 7) */ +#define BLE_BLELL_MMMS_CONN_STATUS_NESN_CURR_Msk (0x80UL) /*!< BLE_BLELL MMMS_CONN_STATUS: NESN_CURR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_CONN_STATUS_LAST_UNMAPPED_CHANNEL_Pos (8UL) /*!< BLE_BLELL MMMS_CONN_STATUS: LAST_UNMAPPED_CHANNEL (Bit 8)*/ +#define BLE_BLELL_MMMS_CONN_STATUS_LAST_UNMAPPED_CHANNEL_Msk (0x3f00UL) /*!< BLE_BLELL MMMS_CONN_STATUS: LAST_UNMAPPED_CHANNEL (Bitfield-Mask: 0x3f)*/ +#define BLE_BLELL_MMMS_CONN_STATUS_PKT_MISS_Pos (14UL) /*!< BLE_BLELL MMMS_CONN_STATUS: PKT_MISS (Bit 14) */ +#define BLE_BLELL_MMMS_CONN_STATUS_PKT_MISS_Msk (0x4000UL) /*!< BLE_BLELL MMMS_CONN_STATUS: PKT_MISS (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_CONN_STATUS_ANCHOR_PT_STATE_Pos (15UL) /*!< BLE_BLELL MMMS_CONN_STATUS: ANCHOR_PT_STATE (Bit 15) */ +#define BLE_BLELL_MMMS_CONN_STATUS_ANCHOR_PT_STATE_Msk (0x8000UL) /*!< BLE_BLELL MMMS_CONN_STATUS: ANCHOR_PT_STATE (Bitfield-Mask: 0x01)*/ +/* ============================================= BLE_BLELL.BT_SLOT_CAPT_STATUS ============================================= */ +#define BLE_BLELL_BT_SLOT_CAPT_STATUS_BT_SLOT_Pos (0UL) /*!< BLE_BLELL BT_SLOT_CAPT_STATUS: BT_SLOT (Bit 0) */ +#define BLE_BLELL_BT_SLOT_CAPT_STATUS_BT_SLOT_Msk (0xffffUL) /*!< BLE_BLELL BT_SLOT_CAPT_STATUS: BT_SLOT (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLELL.US_CAPT_STATUS ================================================ */ +#define BLE_BLELL_US_CAPT_STATUS_US_CAPT_Pos (0UL) /*!< BLE_BLELL US_CAPT_STATUS: US_CAPT (Bit 0) */ +#define BLE_BLELL_US_CAPT_STATUS_US_CAPT_Msk (0x3ffUL) /*!< BLE_BLELL US_CAPT_STATUS: US_CAPT (Bitfield-Mask: 0x3ff) */ +/* ============================================== BLE_BLELL.US_OFFSET_STATUS =============================================== */ +#define BLE_BLELL_US_OFFSET_STATUS_US_OFFSET_Pos (0UL) /*!< BLE_BLELL US_OFFSET_STATUS: US_OFFSET (Bit 0) */ +#define BLE_BLELL_US_OFFSET_STATUS_US_OFFSET_Msk (0xffffUL) /*!< BLE_BLELL US_OFFSET_STATUS: US_OFFSET (Bitfield-Mask: 0xffff)*/ +/* ========================================== BLE_BLELL.ACCU_WINDOW_WIDEN_STATUS =========================================== */ +#define BLE_BLELL_ACCU_WINDOW_WIDEN_STATUS_ACCU_WINDOW_WIDEN_Pos (0UL) /*!< BLE_BLELL ACCU_WINDOW_WIDEN_STATUS: ACCU_WINDOW_WIDEN (Bit 0)*/ +#define BLE_BLELL_ACCU_WINDOW_WIDEN_STATUS_ACCU_WINDOW_WIDEN_Msk (0xffffUL) /*!< BLE_BLELL ACCU_WINDOW_WIDEN_STATUS: ACCU_WINDOW_WIDEN (Bitfield-Mask: 0xffff)*/ +/* ============================================== BLE_BLELL.EARLY_INTR_STATUS ============================================== */ +#define BLE_BLELL_EARLY_INTR_STATUS_CONN_INDEX_FOR_EARLY_INTR_Pos (0UL) /*!< BLE_BLELL EARLY_INTR_STATUS: CONN_INDEX_FOR_EARLY_INTR (Bit 0)*/ +#define BLE_BLELL_EARLY_INTR_STATUS_CONN_INDEX_FOR_EARLY_INTR_Msk (0x1fUL) /*!< BLE_BLELL EARLY_INTR_STATUS: CONN_INDEX_FOR_EARLY_INTR (Bitfield-Mask: 0x1f)*/ +#define BLE_BLELL_EARLY_INTR_STATUS_CONN_TYPE_FOR_EARLY_INTR_Pos (5UL) /*!< BLE_BLELL EARLY_INTR_STATUS: CONN_TYPE_FOR_EARLY_INTR (Bit 5)*/ +#define BLE_BLELL_EARLY_INTR_STATUS_CONN_TYPE_FOR_EARLY_INTR_Msk (0x20UL) /*!< BLE_BLELL EARLY_INTR_STATUS: CONN_TYPE_FOR_EARLY_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_EARLY_INTR_STATUS_US_FOR_EARLY_INTR_Pos (6UL) /*!< BLE_BLELL EARLY_INTR_STATUS: US_FOR_EARLY_INTR (Bit 6) */ +#define BLE_BLELL_EARLY_INTR_STATUS_US_FOR_EARLY_INTR_Msk (0xffc0UL) /*!< BLE_BLELL EARLY_INTR_STATUS: US_FOR_EARLY_INTR (Bitfield-Mask: 0x3ff)*/ +/* ================================================= BLE_BLELL.MMMS_CONFIG ================================================= */ +#define BLE_BLELL_MMMS_CONFIG_MMMS_ENABLE_Pos (0UL) /*!< BLE_BLELL MMMS_CONFIG: MMMS_ENABLE (Bit 0) */ +#define BLE_BLELL_MMMS_CONFIG_MMMS_ENABLE_Msk (0x1UL) /*!< BLE_BLELL MMMS_CONFIG: MMMS_ENABLE (Bitfield-Mask: 0x01) */ +#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_REQ_PARAM_IN_MEM_Pos (1UL) /*!< BLE_BLELL MMMS_CONFIG: DISABLE_CONN_REQ_PARAM_IN_MEM (Bit 1)*/ +#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_REQ_PARAM_IN_MEM_Msk (0x2UL) /*!< BLE_BLELL MMMS_CONFIG: DISABLE_CONN_REQ_PARAM_IN_MEM (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_PARAM_MEM_WR_Pos (2UL) /*!< BLE_BLELL MMMS_CONFIG: DISABLE_CONN_PARAM_MEM_WR (Bit 2)*/ +#define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_PARAM_MEM_WR_Msk (0x4UL) /*!< BLE_BLELL MMMS_CONFIG: DISABLE_CONN_PARAM_MEM_WR (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_CONFIG_CONN_PARAM_FROM_REG_Pos (3UL) /*!< BLE_BLELL MMMS_CONFIG: CONN_PARAM_FROM_REG (Bit 3) */ +#define BLE_BLELL_MMMS_CONFIG_CONN_PARAM_FROM_REG_Msk (0x8UL) /*!< BLE_BLELL MMMS_CONFIG: CONN_PARAM_FROM_REG (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_CONFIG_ADV_CONN_INDEX_Pos (4UL) /*!< BLE_BLELL MMMS_CONFIG: ADV_CONN_INDEX (Bit 4) */ +#define BLE_BLELL_MMMS_CONFIG_ADV_CONN_INDEX_Msk (0x1f0UL) /*!< BLE_BLELL MMMS_CONFIG: ADV_CONN_INDEX (Bitfield-Mask: 0x1f)*/ +#define BLE_BLELL_MMMS_CONFIG_CE_LEN_IMMEDIATE_EXPIRE_Pos (9UL) /*!< BLE_BLELL MMMS_CONFIG: CE_LEN_IMMEDIATE_EXPIRE (Bit 9) */ +#define BLE_BLELL_MMMS_CONFIG_CE_LEN_IMMEDIATE_EXPIRE_Msk (0x200UL) /*!< BLE_BLELL MMMS_CONFIG: CE_LEN_IMMEDIATE_EXPIRE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_CONFIG_RESET_RX_FIFO_PTR_Pos (10UL) /*!< BLE_BLELL MMMS_CONFIG: RESET_RX_FIFO_PTR (Bit 10) */ +#define BLE_BLELL_MMMS_CONFIG_RESET_RX_FIFO_PTR_Msk (0x400UL) /*!< BLE_BLELL MMMS_CONFIG: RESET_RX_FIFO_PTR (Bitfield-Mask: 0x01)*/ +/* ================================================= BLE_BLELL.US_COUNTER ================================================== */ +#define BLE_BLELL_US_COUNTER_US_COUNTER_Pos (0UL) /*!< BLE_BLELL US_COUNTER: US_COUNTER (Bit 0) */ +#define BLE_BLELL_US_COUNTER_US_COUNTER_Msk (0x3ffUL) /*!< BLE_BLELL US_COUNTER: US_COUNTER (Bitfield-Mask: 0x3ff) */ +/* ================================================ BLE_BLELL.US_CAPT_PREV ================================================= */ +#define BLE_BLELL_US_CAPT_PREV_US_CAPT_LOAD_Pos (0UL) /*!< BLE_BLELL US_CAPT_PREV: US_CAPT_LOAD (Bit 0) */ +#define BLE_BLELL_US_CAPT_PREV_US_CAPT_LOAD_Msk (0x3ffUL) /*!< BLE_BLELL US_CAPT_PREV: US_CAPT_LOAD (Bitfield-Mask: 0x3ff)*/ +/* ================================================ BLE_BLELL.EARLY_INTR_NI ================================================ */ +#define BLE_BLELL_EARLY_INTR_NI_EARLY_INTR_NI_Pos (0UL) /*!< BLE_BLELL EARLY_INTR_NI: EARLY_INTR_NI (Bit 0) */ +#define BLE_BLELL_EARLY_INTR_NI_EARLY_INTR_NI_Msk (0xffffUL) /*!< BLE_BLELL EARLY_INTR_NI: EARLY_INTR_NI (Bitfield-Mask: 0xffff)*/ +/* ========================================= BLE_BLELL.MMMS_MASTER_CREATE_BT_CAPT ========================================== */ +#define BLE_BLELL_MMMS_MASTER_CREATE_BT_CAPT_BT_SLOT_Pos (0UL) /*!< BLE_BLELL MMMS_MASTER_CREATE_BT_CAPT: BT_SLOT (Bit 0) */ +#define BLE_BLELL_MMMS_MASTER_CREATE_BT_CAPT_BT_SLOT_Msk (0xffffUL) /*!< BLE_BLELL MMMS_MASTER_CREATE_BT_CAPT: BT_SLOT (Bitfield-Mask: 0xffff)*/ +/* ========================================== BLE_BLELL.MMMS_SLAVE_CREATE_BT_CAPT ========================================== */ +#define BLE_BLELL_MMMS_SLAVE_CREATE_BT_CAPT_US_CAPT_Pos (0UL) /*!< BLE_BLELL MMMS_SLAVE_CREATE_BT_CAPT: US_CAPT (Bit 0) */ +#define BLE_BLELL_MMMS_SLAVE_CREATE_BT_CAPT_US_CAPT_Msk (0x3ffUL) /*!< BLE_BLELL MMMS_SLAVE_CREATE_BT_CAPT: US_CAPT (Bitfield-Mask: 0x3ff)*/ +/* ========================================== BLE_BLELL.MMMS_SLAVE_CREATE_US_CAPT ========================================== */ +#define BLE_BLELL_MMMS_SLAVE_CREATE_US_CAPT_US_OFFSET_SLAVE_CREATED_Pos (0UL) /*!< BLE_BLELL MMMS_SLAVE_CREATE_US_CAPT: US_OFFSET_SLAVE_CREATED (Bit 0)*/ +#define BLE_BLELL_MMMS_SLAVE_CREATE_US_CAPT_US_OFFSET_SLAVE_CREATED_Msk (0xffffUL) /*!< BLE_BLELL MMMS_SLAVE_CREATE_US_CAPT: US_OFFSET_SLAVE_CREATED (Bitfield-Mask: 0xffff)*/ +/* ========================================== BLE_BLELL.MMMS_DATA_MEM_DESCRIPTOR =========================================== */ +#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_LLID_C1_Pos (0UL) /*!< BLE_BLELL MMMS_DATA_MEM_DESCRIPTOR: LLID_C1 (Bit 0) */ +#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_LLID_C1_Msk (0x3UL) /*!< BLE_BLELL MMMS_DATA_MEM_DESCRIPTOR: LLID_C1 (Bitfield-Mask: 0x03)*/ +#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_DATA_LENGTH_C1_Pos (2UL) /*!< BLE_BLELL MMMS_DATA_MEM_DESCRIPTOR: DATA_LENGTH_C1 (Bit 2)*/ +#define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_DATA_LENGTH_C1_Msk (0x3fcUL) /*!< BLE_BLELL MMMS_DATA_MEM_DESCRIPTOR: DATA_LENGTH_C1 (Bitfield-Mask: 0xff)*/ +/* ============================================ BLE_BLELL.CONN_1_DATA_LIST_SENT ============================================ */ +#define BLE_BLELL_CONN_1_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos (0UL) /*!< BLE_BLELL CONN_1_DATA_LIST_SENT: LIST_INDEX__TX_SENT_3_0_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_1_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_1_DATA_LIST_SENT: LIST_INDEX__TX_SENT_3_0_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_1_DATA_LIST_SENT_SET_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_1_DATA_LIST_SENT: SET_CLEAR_C1 (Bit 7) */ +#define BLE_BLELL_CONN_1_DATA_LIST_SENT_SET_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_1_DATA_LIST_SENT: SET_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_1_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos (8UL) /*!< BLE_BLELL CONN_1_DATA_LIST_SENT: BUFFER_NUM_TX_SENT_3_0_C1 (Bit 8)*/ +#define BLE_BLELL_CONN_1_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk (0xf00UL) /*!< BLE_BLELL CONN_1_DATA_LIST_SENT: BUFFER_NUM_TX_SENT_3_0_C1 (Bitfield-Mask: 0x0f)*/ +/* ============================================ BLE_BLELL.CONN_1_DATA_LIST_ACK ============================================= */ +#define BLE_BLELL_CONN_1_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos (0UL) /*!< BLE_BLELL CONN_1_DATA_LIST_ACK: LIST_INDEX__TX_ACK_3_0_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_1_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_1_DATA_LIST_ACK: LIST_INDEX__TX_ACK_3_0_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_1_DATA_LIST_ACK_SET_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_1_DATA_LIST_ACK: SET_CLEAR_C1 (Bit 7) */ +#define BLE_BLELL_CONN_1_DATA_LIST_ACK_SET_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_1_DATA_LIST_ACK: SET_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +/* =========================================== BLE_BLELL.CONN_1_CE_DATA_LIST_CFG =========================================== */ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos (0UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: DATA_LIST_INDEX_LAST_ACK_INDEX_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: DATA_LIST_INDEX_LAST_ACK_INDEX_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos (4UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: DATA_LIST_HEAD_UP_C1 (Bit 4)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk (0x10UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: DATA_LIST_HEAD_UP_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos (5UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: SLV_MD_CONFIG_C1 (Bit 5)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk (0x20UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: SLV_MD_CONFIG_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_C1_Pos (6UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: MD_C1 (Bit 6) */ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_C1_Msk (0x40UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: MD_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: MD_BIT_CLEAR_C1 (Bit 7)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: MD_BIT_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos (8UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: PAUSE_DATA_C1 (Bit 8)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk (0x100UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: PAUSE_DATA_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_Pos (9UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: KILL_CONN (Bit 9) */ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_Msk (0x200UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: KILL_CONN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos (10UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: KILL_CONN_AFTER_TX (Bit 10)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk (0x400UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: KILL_CONN_AFTER_TX (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos (11UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: EMPTYPDU_SENT (Bit 11)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk (0x800UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: EMPTYPDU_SENT (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos (12UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: CURRENT_PDU_INDEX_C1 (Bit 12)*/ +#define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk (0xf000UL) /*!< BLE_BLELL CONN_1_CE_DATA_LIST_CFG: CURRENT_PDU_INDEX_C1 (Bitfield-Mask: 0x0f)*/ +/* ============================================ BLE_BLELL.CONN_2_DATA_LIST_SENT ============================================ */ +#define BLE_BLELL_CONN_2_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos (0UL) /*!< BLE_BLELL CONN_2_DATA_LIST_SENT: LIST_INDEX__TX_SENT_3_0_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_2_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_2_DATA_LIST_SENT: LIST_INDEX__TX_SENT_3_0_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_2_DATA_LIST_SENT_SET_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_2_DATA_LIST_SENT: SET_CLEAR_C1 (Bit 7) */ +#define BLE_BLELL_CONN_2_DATA_LIST_SENT_SET_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_2_DATA_LIST_SENT: SET_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_2_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos (8UL) /*!< BLE_BLELL CONN_2_DATA_LIST_SENT: BUFFER_NUM_TX_SENT_3_0_C1 (Bit 8)*/ +#define BLE_BLELL_CONN_2_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk (0xf00UL) /*!< BLE_BLELL CONN_2_DATA_LIST_SENT: BUFFER_NUM_TX_SENT_3_0_C1 (Bitfield-Mask: 0x0f)*/ +/* ============================================ BLE_BLELL.CONN_2_DATA_LIST_ACK ============================================= */ +#define BLE_BLELL_CONN_2_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos (0UL) /*!< BLE_BLELL CONN_2_DATA_LIST_ACK: LIST_INDEX__TX_ACK_3_0_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_2_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_2_DATA_LIST_ACK: LIST_INDEX__TX_ACK_3_0_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_2_DATA_LIST_ACK_SET_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_2_DATA_LIST_ACK: SET_CLEAR_C1 (Bit 7) */ +#define BLE_BLELL_CONN_2_DATA_LIST_ACK_SET_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_2_DATA_LIST_ACK: SET_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +/* =========================================== BLE_BLELL.CONN_2_CE_DATA_LIST_CFG =========================================== */ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos (0UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: DATA_LIST_INDEX_LAST_ACK_INDEX_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: DATA_LIST_INDEX_LAST_ACK_INDEX_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos (4UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: DATA_LIST_HEAD_UP_C1 (Bit 4)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk (0x10UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: DATA_LIST_HEAD_UP_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos (5UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: SLV_MD_CONFIG_C1 (Bit 5)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk (0x20UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: SLV_MD_CONFIG_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_C1_Pos (6UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: MD_C1 (Bit 6) */ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_C1_Msk (0x40UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: MD_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: MD_BIT_CLEAR_C1 (Bit 7)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: MD_BIT_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos (8UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: PAUSE_DATA_C1 (Bit 8)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk (0x100UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: PAUSE_DATA_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_Pos (9UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: KILL_CONN (Bit 9) */ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_Msk (0x200UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: KILL_CONN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos (10UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: KILL_CONN_AFTER_TX (Bit 10)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk (0x400UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: KILL_CONN_AFTER_TX (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos (11UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: EMPTYPDU_SENT (Bit 11)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk (0x800UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: EMPTYPDU_SENT (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos (12UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: CURRENT_PDU_INDEX_C1 (Bit 12)*/ +#define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk (0xf000UL) /*!< BLE_BLELL CONN_2_CE_DATA_LIST_CFG: CURRENT_PDU_INDEX_C1 (Bitfield-Mask: 0x0f)*/ +/* ============================================ BLE_BLELL.CONN_3_DATA_LIST_SENT ============================================ */ +#define BLE_BLELL_CONN_3_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos (0UL) /*!< BLE_BLELL CONN_3_DATA_LIST_SENT: LIST_INDEX__TX_SENT_3_0_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_3_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_3_DATA_LIST_SENT: LIST_INDEX__TX_SENT_3_0_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_3_DATA_LIST_SENT_SET_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_3_DATA_LIST_SENT: SET_CLEAR_C1 (Bit 7) */ +#define BLE_BLELL_CONN_3_DATA_LIST_SENT_SET_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_3_DATA_LIST_SENT: SET_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_3_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos (8UL) /*!< BLE_BLELL CONN_3_DATA_LIST_SENT: BUFFER_NUM_TX_SENT_3_0_C1 (Bit 8)*/ +#define BLE_BLELL_CONN_3_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk (0xf00UL) /*!< BLE_BLELL CONN_3_DATA_LIST_SENT: BUFFER_NUM_TX_SENT_3_0_C1 (Bitfield-Mask: 0x0f)*/ +/* ============================================ BLE_BLELL.CONN_3_DATA_LIST_ACK ============================================= */ +#define BLE_BLELL_CONN_3_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos (0UL) /*!< BLE_BLELL CONN_3_DATA_LIST_ACK: LIST_INDEX__TX_ACK_3_0_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_3_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_3_DATA_LIST_ACK: LIST_INDEX__TX_ACK_3_0_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_3_DATA_LIST_ACK_SET_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_3_DATA_LIST_ACK: SET_CLEAR_C1 (Bit 7) */ +#define BLE_BLELL_CONN_3_DATA_LIST_ACK_SET_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_3_DATA_LIST_ACK: SET_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +/* =========================================== BLE_BLELL.CONN_3_CE_DATA_LIST_CFG =========================================== */ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos (0UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: DATA_LIST_INDEX_LAST_ACK_INDEX_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: DATA_LIST_INDEX_LAST_ACK_INDEX_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos (4UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: DATA_LIST_HEAD_UP_C1 (Bit 4)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk (0x10UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: DATA_LIST_HEAD_UP_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos (5UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: SLV_MD_CONFIG_C1 (Bit 5)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk (0x20UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: SLV_MD_CONFIG_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_C1_Pos (6UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: MD_C1 (Bit 6) */ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_C1_Msk (0x40UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: MD_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: MD_BIT_CLEAR_C1 (Bit 7)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: MD_BIT_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos (8UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: PAUSE_DATA_C1 (Bit 8)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk (0x100UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: PAUSE_DATA_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_Pos (9UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: KILL_CONN (Bit 9) */ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_Msk (0x200UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: KILL_CONN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos (10UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: KILL_CONN_AFTER_TX (Bit 10)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk (0x400UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: KILL_CONN_AFTER_TX (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos (11UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: EMPTYPDU_SENT (Bit 11)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk (0x800UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: EMPTYPDU_SENT (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos (12UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: CURRENT_PDU_INDEX_C1 (Bit 12)*/ +#define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk (0xf000UL) /*!< BLE_BLELL CONN_3_CE_DATA_LIST_CFG: CURRENT_PDU_INDEX_C1 (Bitfield-Mask: 0x0f)*/ +/* ============================================ BLE_BLELL.CONN_4_DATA_LIST_SENT ============================================ */ +#define BLE_BLELL_CONN_4_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos (0UL) /*!< BLE_BLELL CONN_4_DATA_LIST_SENT: LIST_INDEX__TX_SENT_3_0_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_4_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_4_DATA_LIST_SENT: LIST_INDEX__TX_SENT_3_0_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_4_DATA_LIST_SENT_SET_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_4_DATA_LIST_SENT: SET_CLEAR_C1 (Bit 7) */ +#define BLE_BLELL_CONN_4_DATA_LIST_SENT_SET_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_4_DATA_LIST_SENT: SET_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_4_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos (8UL) /*!< BLE_BLELL CONN_4_DATA_LIST_SENT: BUFFER_NUM_TX_SENT_3_0_C1 (Bit 8)*/ +#define BLE_BLELL_CONN_4_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk (0xf00UL) /*!< BLE_BLELL CONN_4_DATA_LIST_SENT: BUFFER_NUM_TX_SENT_3_0_C1 (Bitfield-Mask: 0x0f)*/ +/* ============================================ BLE_BLELL.CONN_4_DATA_LIST_ACK ============================================= */ +#define BLE_BLELL_CONN_4_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos (0UL) /*!< BLE_BLELL CONN_4_DATA_LIST_ACK: LIST_INDEX__TX_ACK_3_0_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_4_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_4_DATA_LIST_ACK: LIST_INDEX__TX_ACK_3_0_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_4_DATA_LIST_ACK_SET_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_4_DATA_LIST_ACK: SET_CLEAR_C1 (Bit 7) */ +#define BLE_BLELL_CONN_4_DATA_LIST_ACK_SET_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_4_DATA_LIST_ACK: SET_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +/* =========================================== BLE_BLELL.CONN_4_CE_DATA_LIST_CFG =========================================== */ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos (0UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: DATA_LIST_INDEX_LAST_ACK_INDEX_C1 (Bit 0)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk (0xfUL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: DATA_LIST_INDEX_LAST_ACK_INDEX_C1 (Bitfield-Mask: 0x0f)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos (4UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: DATA_LIST_HEAD_UP_C1 (Bit 4)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk (0x10UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: DATA_LIST_HEAD_UP_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos (5UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: SLV_MD_CONFIG_C1 (Bit 5)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk (0x20UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: SLV_MD_CONFIG_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_C1_Pos (6UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: MD_C1 (Bit 6) */ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_C1_Msk (0x40UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: MD_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos (7UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: MD_BIT_CLEAR_C1 (Bit 7)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk (0x80UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: MD_BIT_CLEAR_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos (8UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: PAUSE_DATA_C1 (Bit 8)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk (0x100UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: PAUSE_DATA_C1 (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_Pos (9UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: KILL_CONN (Bit 9) */ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_Msk (0x200UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: KILL_CONN (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos (10UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: KILL_CONN_AFTER_TX (Bit 10)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk (0x400UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: KILL_CONN_AFTER_TX (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos (11UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: EMPTYPDU_SENT (Bit 11)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk (0x800UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: EMPTYPDU_SENT (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos (12UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: CURRENT_PDU_INDEX_C1 (Bit 12)*/ +#define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk (0xf000UL) /*!< BLE_BLELL CONN_4_CE_DATA_LIST_CFG: CURRENT_PDU_INDEX_C1 (Bitfield-Mask: 0x0f)*/ +/* ============================================ BLE_BLELL.MMMS_ADVCH_NI_ENABLE ============================================= */ +#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_ADV_NI_ENABLE_Pos (0UL) /*!< BLE_BLELL MMMS_ADVCH_NI_ENABLE: ADV_NI_ENABLE (Bit 0) */ +#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_ADV_NI_ENABLE_Msk (0x1UL) /*!< BLE_BLELL MMMS_ADVCH_NI_ENABLE: ADV_NI_ENABLE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_SCAN_NI_ENABLE_Pos (1UL) /*!< BLE_BLELL MMMS_ADVCH_NI_ENABLE: SCAN_NI_ENABLE (Bit 1) */ +#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_SCAN_NI_ENABLE_Msk (0x2UL) /*!< BLE_BLELL MMMS_ADVCH_NI_ENABLE: SCAN_NI_ENABLE (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_INIT_NI_ENABLE_Pos (2UL) /*!< BLE_BLELL MMMS_ADVCH_NI_ENABLE: INIT_NI_ENABLE (Bit 2) */ +#define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_INIT_NI_ENABLE_Msk (0x4UL) /*!< BLE_BLELL MMMS_ADVCH_NI_ENABLE: INIT_NI_ENABLE (Bitfield-Mask: 0x01)*/ +/* ============================================= BLE_BLELL.MMMS_ADVCH_NI_VALID ============================================= */ +#define BLE_BLELL_MMMS_ADVCH_NI_VALID_ADV_NI_VALID_Pos (0UL) /*!< BLE_BLELL MMMS_ADVCH_NI_VALID: ADV_NI_VALID (Bit 0) */ +#define BLE_BLELL_MMMS_ADVCH_NI_VALID_ADV_NI_VALID_Msk (0x1UL) /*!< BLE_BLELL MMMS_ADVCH_NI_VALID: ADV_NI_VALID (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_ADVCH_NI_VALID_SCAN_NI_VALID_Pos (1UL) /*!< BLE_BLELL MMMS_ADVCH_NI_VALID: SCAN_NI_VALID (Bit 1) */ +#define BLE_BLELL_MMMS_ADVCH_NI_VALID_SCAN_NI_VALID_Msk (0x2UL) /*!< BLE_BLELL MMMS_ADVCH_NI_VALID: SCAN_NI_VALID (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_ADVCH_NI_VALID_INIT_NI_VALID_Pos (2UL) /*!< BLE_BLELL MMMS_ADVCH_NI_VALID: INIT_NI_VALID (Bit 2) */ +#define BLE_BLELL_MMMS_ADVCH_NI_VALID_INIT_NI_VALID_Msk (0x4UL) /*!< BLE_BLELL MMMS_ADVCH_NI_VALID: INIT_NI_VALID (Bitfield-Mask: 0x01)*/ +/* ============================================= BLE_BLELL.MMMS_ADVCH_NI_ABORT ============================================= */ +#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_NI_ABORT_Pos (0UL) /*!< BLE_BLELL MMMS_ADVCH_NI_ABORT: ADVCH_NI_ABORT (Bit 0) */ +#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_NI_ABORT_Msk (0x1UL) /*!< BLE_BLELL MMMS_ADVCH_NI_ABORT: ADVCH_NI_ABORT (Bitfield-Mask: 0x01)*/ +#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_ABORT_STATUS_Pos (1UL) /*!< BLE_BLELL MMMS_ADVCH_NI_ABORT: ADVCH_ABORT_STATUS (Bit 1)*/ +#define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_ABORT_STATUS_Msk (0x2UL) /*!< BLE_BLELL MMMS_ADVCH_NI_ABORT: ADVCH_ABORT_STATUS (Bitfield-Mask: 0x01)*/ +/* =========================================== BLE_BLELL.CONN_PARAM_NEXT_SUP_TO ============================================ */ +#define BLE_BLELL_CONN_PARAM_NEXT_SUP_TO_NEXT_SUP_TO_LOAD_Pos (0UL) /*!< BLE_BLELL CONN_PARAM_NEXT_SUP_TO: NEXT_SUP_TO_LOAD (Bit 0)*/ +#define BLE_BLELL_CONN_PARAM_NEXT_SUP_TO_NEXT_SUP_TO_LOAD_Msk (0xffffUL) /*!< BLE_BLELL CONN_PARAM_NEXT_SUP_TO: NEXT_SUP_TO_LOAD (Bitfield-Mask: 0xffff)*/ +/* ========================================== BLE_BLELL.CONN_PARAM_ACC_WIN_WIDEN =========================================== */ +#define BLE_BLELL_CONN_PARAM_ACC_WIN_WIDEN_ACC_WINDOW_WIDEN_Pos (0UL) /*!< BLE_BLELL CONN_PARAM_ACC_WIN_WIDEN: ACC_WINDOW_WIDEN (Bit 0)*/ +#define BLE_BLELL_CONN_PARAM_ACC_WIN_WIDEN_ACC_WINDOW_WIDEN_Msk (0x3ffUL) /*!< BLE_BLELL CONN_PARAM_ACC_WIN_WIDEN: ACC_WINDOW_WIDEN (Bitfield-Mask: 0x3ff)*/ +/* =============================================== BLE_BLELL.HW_LOAD_OFFSET ================================================ */ +#define BLE_BLELL_HW_LOAD_OFFSET_LOAD_OFFSET_Pos (0UL) /*!< BLE_BLELL HW_LOAD_OFFSET: LOAD_OFFSET (Bit 0) */ +#define BLE_BLELL_HW_LOAD_OFFSET_LOAD_OFFSET_Msk (0x1fUL) /*!< BLE_BLELL HW_LOAD_OFFSET: LOAD_OFFSET (Bitfield-Mask: 0x1f)*/ +/* ================================================== BLE_BLELL.ADV_RAND =================================================== */ +#define BLE_BLELL_ADV_RAND_ADV_RAND_Pos (0UL) /*!< BLE_BLELL ADV_RAND: ADV_RAND (Bit 0) */ +#define BLE_BLELL_ADV_RAND_ADV_RAND_Msk (0xfUL) /*!< BLE_BLELL ADV_RAND: ADV_RAND (Bitfield-Mask: 0x0f) */ +/* ============================================== BLE_BLELL.MMMS_RX_PKT_CNTR =============================================== */ +#define BLE_BLELL_MMMS_RX_PKT_CNTR_MMMS_RX_PKT_CNT_Pos (0UL) /*!< BLE_BLELL MMMS_RX_PKT_CNTR: MMMS_RX_PKT_CNT (Bit 0) */ +#define BLE_BLELL_MMMS_RX_PKT_CNTR_MMMS_RX_PKT_CNT_Msk (0x3fUL) /*!< BLE_BLELL MMMS_RX_PKT_CNTR: MMMS_RX_PKT_CNT (Bitfield-Mask: 0x3f)*/ +/* ============================================== BLE_BLELL.CONN_RX_PKT_CNTR =============================================== */ +#define BLE_BLELL_CONN_RX_PKT_CNTR_RX_PKT_CNT_Pos (0UL) /*!< BLE_BLELL CONN_RX_PKT_CNTR: RX_PKT_CNT (Bit 0) */ +#define BLE_BLELL_CONN_RX_PKT_CNTR_RX_PKT_CNT_Msk (0x3fUL) /*!< BLE_BLELL CONN_RX_PKT_CNTR: RX_PKT_CNT (Bitfield-Mask: 0x3f)*/ +/* ============================================= BLE_BLELL.WHITELIST_BASE_ADDR ============================================= */ +#define BLE_BLELL_WHITELIST_BASE_ADDR_WL_BASE_ADDR_Pos (0UL) /*!< BLE_BLELL WHITELIST_BASE_ADDR: WL_BASE_ADDR (Bit 0) */ +#define BLE_BLELL_WHITELIST_BASE_ADDR_WL_BASE_ADDR_Msk (0xffffUL) /*!< BLE_BLELL WHITELIST_BASE_ADDR: WL_BASE_ADDR (Bitfield-Mask: 0xffff)*/ +/* ======================================= BLE_BLELL.RSLV_LIST_PEER_IDNTT_BASE_ADDR ======================================== */ +#define BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR_RSLV_LIST_PEER_IDNTT_BASE_ADDR_Pos (0UL) /*!< BLE_BLELL RSLV_LIST_PEER_IDNTT_BASE_ADDR: RSLV_LIST_PEER_IDNTT_BASE_ADDR (Bit 0)*/ +#define BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR_RSLV_LIST_PEER_IDNTT_BASE_ADDR_Msk (0xffffUL) /*!< BLE_BLELL RSLV_LIST_PEER_IDNTT_BASE_ADDR: RSLV_LIST_PEER_IDNTT_BASE_ADDR (Bitfield-Mask: 0xffff)*/ +/* ======================================== BLE_BLELL.RSLV_LIST_PEER_RPA_BASE_ADDR ========================================= */ +#define BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR_RSLV_LIST_PEER_RPA_BASE_ADDR_Pos (0UL) /*!< BLE_BLELL RSLV_LIST_PEER_RPA_BASE_ADDR: RSLV_LIST_PEER_RPA_BASE_ADDR (Bit 0)*/ +#define BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR_RSLV_LIST_PEER_RPA_BASE_ADDR_Msk (0xffffUL) /*!< BLE_BLELL RSLV_LIST_PEER_RPA_BASE_ADDR: RSLV_LIST_PEER_RPA_BASE_ADDR (Bitfield-Mask: 0xffff)*/ +/* ====================================== BLE_BLELL.RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR ====================================== */ +#define BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_Pos (0UL) /*!< BLE_BLELL RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR: RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR (Bit 0)*/ +#define BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_Msk (0xffffUL) /*!< BLE_BLELL RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR: RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR (Bitfield-Mask: 0xffff)*/ +/* ======================================= BLE_BLELL.RSLV_LIST_TX_INIT_RPA_BASE_ADDR ======================================= */ +#define BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_Pos (0UL) /*!< BLE_BLELL RSLV_LIST_TX_INIT_RPA_BASE_ADDR: RSLV_LIST_TX_INIT_RPA_BASE_ADDR (Bit 0)*/ +#define BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_Msk (0xffffUL) /*!< BLE_BLELL RSLV_LIST_TX_INIT_RPA_BASE_ADDR: RSLV_LIST_TX_INIT_RPA_BASE_ADDR (Bitfield-Mask: 0xffff)*/ + + +/* ================================================= BLE_BLESS.DDFT_CONFIG ================================================= */ +#define BLE_BLESS_DDFT_CONFIG_DDFT_ENABLE_Pos (0UL) /*!< BLE_BLESS DDFT_CONFIG: DDFT_ENABLE (Bit 0) */ +#define BLE_BLESS_DDFT_CONFIG_DDFT_ENABLE_Msk (0x1UL) /*!< BLE_BLESS DDFT_CONFIG: DDFT_ENABLE (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_DDFT_CONFIG_BLERD_DDFT_EN_Pos (1UL) /*!< BLE_BLESS DDFT_CONFIG: BLERD_DDFT_EN (Bit 1) */ +#define BLE_BLESS_DDFT_CONFIG_BLERD_DDFT_EN_Msk (0x2UL) /*!< BLE_BLESS DDFT_CONFIG: BLERD_DDFT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG1_Pos (8UL) /*!< BLE_BLESS DDFT_CONFIG: DDFT_MUX_CFG1 (Bit 8) */ +#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG1_Msk (0x1f00UL) /*!< BLE_BLESS DDFT_CONFIG: DDFT_MUX_CFG1 (Bitfield-Mask: 0x1f)*/ +#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG2_Pos (16UL) /*!< BLE_BLESS DDFT_CONFIG: DDFT_MUX_CFG2 (Bit 16) */ +#define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG2_Msk (0x1f0000UL) /*!< BLE_BLESS DDFT_CONFIG: DDFT_MUX_CFG2 (Bitfield-Mask: 0x1f)*/ +/* ============================================= BLE_BLESS.XTAL_CLK_DIV_CONFIG ============================================= */ +#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Pos (0UL) /*!< BLE_BLESS XTAL_CLK_DIV_CONFIG: SYSCLK_DIV (Bit 0) */ +#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Msk (0x3UL) /*!< BLE_BLESS XTAL_CLK_DIV_CONFIG: SYSCLK_DIV (Bitfield-Mask: 0x03)*/ +#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Pos (2UL) /*!< BLE_BLESS XTAL_CLK_DIV_CONFIG: LLCLK_DIV (Bit 2) */ +#define BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Msk (0xcUL) /*!< BLE_BLESS XTAL_CLK_DIV_CONFIG: LLCLK_DIV (Bitfield-Mask: 0x03)*/ +/* ================================================== BLE_BLESS.INTR_STAT ================================================== */ +#define BLE_BLESS_INTR_STAT_DSM_ENTERED_INTR_Pos (0UL) /*!< BLE_BLESS INTR_STAT: DSM_ENTERED_INTR (Bit 0) */ +#define BLE_BLESS_INTR_STAT_DSM_ENTERED_INTR_Msk (0x1UL) /*!< BLE_BLESS INTR_STAT: DSM_ENTERED_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_STAT_DSM_EXITED_INTR_Pos (1UL) /*!< BLE_BLESS INTR_STAT: DSM_EXITED_INTR (Bit 1) */ +#define BLE_BLESS_INTR_STAT_DSM_EXITED_INTR_Msk (0x2UL) /*!< BLE_BLESS INTR_STAT: DSM_EXITED_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_STAT_RCBLL_DONE_INTR_Pos (2UL) /*!< BLE_BLESS INTR_STAT: RCBLL_DONE_INTR (Bit 2) */ +#define BLE_BLESS_INTR_STAT_RCBLL_DONE_INTR_Msk (0x4UL) /*!< BLE_BLESS INTR_STAT: RCBLL_DONE_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Pos (3UL) /*!< BLE_BLESS INTR_STAT: BLERD_ACTIVE_INTR (Bit 3) */ +#define BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Msk (0x8UL) /*!< BLE_BLESS INTR_STAT: BLERD_ACTIVE_INTR (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_STAT_RCB_INTR_Pos (4UL) /*!< BLE_BLESS INTR_STAT: RCB_INTR (Bit 4) */ +#define BLE_BLESS_INTR_STAT_RCB_INTR_Msk (0x10UL) /*!< BLE_BLESS INTR_STAT: RCB_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_STAT_LL_INTR_Pos (5UL) /*!< BLE_BLESS INTR_STAT: LL_INTR (Bit 5) */ +#define BLE_BLESS_INTR_STAT_LL_INTR_Msk (0x20UL) /*!< BLE_BLESS INTR_STAT: LL_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_STAT_GPIO_INTR_Pos (6UL) /*!< BLE_BLESS INTR_STAT: GPIO_INTR (Bit 6) */ +#define BLE_BLESS_INTR_STAT_GPIO_INTR_Msk (0x40UL) /*!< BLE_BLESS INTR_STAT: GPIO_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_STAT_EFUSE_INTR_Pos (7UL) /*!< BLE_BLESS INTR_STAT: EFUSE_INTR (Bit 7) */ +#define BLE_BLESS_INTR_STAT_EFUSE_INTR_Msk (0x80UL) /*!< BLE_BLESS INTR_STAT: EFUSE_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_STAT_XTAL_ON_INTR_Pos (8UL) /*!< BLE_BLESS INTR_STAT: XTAL_ON_INTR (Bit 8) */ +#define BLE_BLESS_INTR_STAT_XTAL_ON_INTR_Msk (0x100UL) /*!< BLE_BLESS INTR_STAT: XTAL_ON_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_STAT_ENC_INTR_Pos (9UL) /*!< BLE_BLESS INTR_STAT: ENC_INTR (Bit 9) */ +#define BLE_BLESS_INTR_STAT_ENC_INTR_Msk (0x200UL) /*!< BLE_BLESS INTR_STAT: ENC_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_POS_Pos (10UL) /*!< BLE_BLESS INTR_STAT: HVLDO_LV_DETECT_POS (Bit 10) */ +#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_POS_Msk (0x400UL) /*!< BLE_BLESS INTR_STAT: HVLDO_LV_DETECT_POS (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_NEG_Pos (11UL) /*!< BLE_BLESS INTR_STAT: HVLDO_LV_DETECT_NEG (Bit 11) */ +#define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_NEG_Msk (0x800UL) /*!< BLE_BLESS INTR_STAT: HVLDO_LV_DETECT_NEG (Bitfield-Mask: 0x01)*/ +/* ================================================== BLE_BLESS.INTR_MASK ================================================== */ +#define BLE_BLESS_INTR_MASK_DSM_EXIT_Pos (0UL) /*!< BLE_BLESS INTR_MASK: DSM_EXIT (Bit 0) */ +#define BLE_BLESS_INTR_MASK_DSM_EXIT_Msk (0x1UL) /*!< BLE_BLESS INTR_MASK: DSM_EXIT (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_MASK_DSM_ENTERED_INTR_MASK_Pos (1UL) /*!< BLE_BLESS INTR_MASK: DSM_ENTERED_INTR_MASK (Bit 1) */ +#define BLE_BLESS_INTR_MASK_DSM_ENTERED_INTR_MASK_Msk (0x2UL) /*!< BLE_BLESS INTR_MASK: DSM_ENTERED_INTR_MASK (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_MASK_DSM_EXITED_INTR_MASK_Pos (2UL) /*!< BLE_BLESS INTR_MASK: DSM_EXITED_INTR_MASK (Bit 2) */ +#define BLE_BLESS_INTR_MASK_DSM_EXITED_INTR_MASK_Msk (0x4UL) /*!< BLE_BLESS INTR_MASK: DSM_EXITED_INTR_MASK (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_MASK_XTAL_ON_INTR_MASK_Pos (3UL) /*!< BLE_BLESS INTR_MASK: XTAL_ON_INTR_MASK (Bit 3) */ +#define BLE_BLESS_INTR_MASK_XTAL_ON_INTR_MASK_Msk (0x8UL) /*!< BLE_BLESS INTR_MASK: XTAL_ON_INTR_MASK (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_MASK_RCBLL_INTR_MASK_Pos (4UL) /*!< BLE_BLESS INTR_MASK: RCBLL_INTR_MASK (Bit 4) */ +#define BLE_BLESS_INTR_MASK_RCBLL_INTR_MASK_Msk (0x10UL) /*!< BLE_BLESS INTR_MASK: RCBLL_INTR_MASK (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_MASK_BLERD_ACTIVE_INTR_MASK_Pos (5UL) /*!< BLE_BLESS INTR_MASK: BLERD_ACTIVE_INTR_MASK (Bit 5) */ +#define BLE_BLESS_INTR_MASK_BLERD_ACTIVE_INTR_MASK_Msk (0x20UL) /*!< BLE_BLESS INTR_MASK: BLERD_ACTIVE_INTR_MASK (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_MASK_RCB_INTR_MASK_Pos (6UL) /*!< BLE_BLESS INTR_MASK: RCB_INTR_MASK (Bit 6) */ +#define BLE_BLESS_INTR_MASK_RCB_INTR_MASK_Msk (0x40UL) /*!< BLE_BLESS INTR_MASK: RCB_INTR_MASK (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_MASK_LL_INTR_MASK_Pos (7UL) /*!< BLE_BLESS INTR_MASK: LL_INTR_MASK (Bit 7) */ +#define BLE_BLESS_INTR_MASK_LL_INTR_MASK_Msk (0x80UL) /*!< BLE_BLESS INTR_MASK: LL_INTR_MASK (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_MASK_GPIO_INTR_MASK_Pos (8UL) /*!< BLE_BLESS INTR_MASK: GPIO_INTR_MASK (Bit 8) */ +#define BLE_BLESS_INTR_MASK_GPIO_INTR_MASK_Msk (0x100UL) /*!< BLE_BLESS INTR_MASK: GPIO_INTR_MASK (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_MASK_EFUSE_INTR_MASK_Pos (9UL) /*!< BLE_BLESS INTR_MASK: EFUSE_INTR_MASK (Bit 9) */ +#define BLE_BLESS_INTR_MASK_EFUSE_INTR_MASK_Msk (0x200UL) /*!< BLE_BLESS INTR_MASK: EFUSE_INTR_MASK (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_MASK_ENC_INTR_MASK_Pos (10UL) /*!< BLE_BLESS INTR_MASK: ENC_INTR_MASK (Bit 10) */ +#define BLE_BLESS_INTR_MASK_ENC_INTR_MASK_Msk (0x400UL) /*!< BLE_BLESS INTR_MASK: ENC_INTR_MASK (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_POS_MASK_Pos (11UL) /*!< BLE_BLESS INTR_MASK: HVLDO_LV_DETECT_POS_MASK (Bit 11) */ +#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_POS_MASK_Msk (0x800UL) /*!< BLE_BLESS INTR_MASK: HVLDO_LV_DETECT_POS_MASK (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_NEG_MASK_Pos (12UL) /*!< BLE_BLESS INTR_MASK: HVLDO_LV_DETECT_NEG_MASK (Bit 12) */ +#define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_NEG_MASK_Msk (0x1000UL) /*!< BLE_BLESS INTR_MASK: HVLDO_LV_DETECT_NEG_MASK (Bitfield-Mask: 0x01)*/ +/* ================================================== BLE_BLESS.LL_CLK_EN ================================================== */ +#define BLE_BLESS_LL_CLK_EN_CLK_EN_Pos (0UL) /*!< BLE_BLESS LL_CLK_EN: CLK_EN (Bit 0) */ +#define BLE_BLESS_LL_CLK_EN_CLK_EN_Msk (0x1UL) /*!< BLE_BLESS LL_CLK_EN: CLK_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_LL_CLK_EN_CY_CORREL_EN_Pos (1UL) /*!< BLE_BLESS LL_CLK_EN: CY_CORREL_EN (Bit 1) */ +#define BLE_BLESS_LL_CLK_EN_CY_CORREL_EN_Msk (0x2UL) /*!< BLE_BLESS LL_CLK_EN: CY_CORREL_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_LL_CLK_EN_MXD_IF_OPTION_Pos (2UL) /*!< BLE_BLESS LL_CLK_EN: MXD_IF_OPTION (Bit 2) */ +#define BLE_BLESS_LL_CLK_EN_MXD_IF_OPTION_Msk (0x4UL) /*!< BLE_BLESS LL_CLK_EN: MXD_IF_OPTION (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Pos (3UL) /*!< BLE_BLESS LL_CLK_EN: SEL_RCB_CLK (Bit 3) */ +#define BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Msk (0x8UL) /*!< BLE_BLESS LL_CLK_EN: SEL_RCB_CLK (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_LL_CLK_EN_BLESS_RESET_Pos (4UL) /*!< BLE_BLESS LL_CLK_EN: BLESS_RESET (Bit 4) */ +#define BLE_BLESS_LL_CLK_EN_BLESS_RESET_Msk (0x10UL) /*!< BLE_BLESS LL_CLK_EN: BLESS_RESET (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_LL_CLK_EN_DPSLP_HWRCB_EN_Pos (5UL) /*!< BLE_BLESS LL_CLK_EN: DPSLP_HWRCB_EN (Bit 5) */ +#define BLE_BLESS_LL_CLK_EN_DPSLP_HWRCB_EN_Msk (0x20UL) /*!< BLE_BLESS LL_CLK_EN: DPSLP_HWRCB_EN (Bitfield-Mask: 0x01) */ +/* ================================================= BLE_BLESS.LF_CLK_CTRL ================================================= */ +#define BLE_BLESS_LF_CLK_CTRL_DISABLE_LF_CLK_Pos (0UL) /*!< BLE_BLESS LF_CLK_CTRL: DISABLE_LF_CLK (Bit 0) */ +#define BLE_BLESS_LF_CLK_CTRL_DISABLE_LF_CLK_Msk (0x1UL) /*!< BLE_BLESS LF_CLK_CTRL: DISABLE_LF_CLK (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_LF_CLK_CTRL_ENABLE_ENC_CLK_Pos (1UL) /*!< BLE_BLESS LF_CLK_CTRL: ENABLE_ENC_CLK (Bit 1) */ +#define BLE_BLESS_LF_CLK_CTRL_ENABLE_ENC_CLK_Msk (0x2UL) /*!< BLE_BLESS LF_CLK_CTRL: ENABLE_ENC_CLK (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_LF_CLK_CTRL_M0S8BLESS_REV_ID_Pos (29UL) /*!< BLE_BLESS LF_CLK_CTRL: M0S8BLESS_REV_ID (Bit 29) */ +#define BLE_BLESS_LF_CLK_CTRL_M0S8BLESS_REV_ID_Msk (0xe0000000UL) /*!< BLE_BLESS LF_CLK_CTRL: M0S8BLESS_REV_ID (Bitfield-Mask: 0x07)*/ +/* =============================================== BLE_BLESS.EXT_PA_LNA_CTRL =============================================== */ +#define BLE_BLESS_EXT_PA_LNA_CTRL_ENABLE_EXT_PA_LNA_Pos (1UL) /*!< BLE_BLESS EXT_PA_LNA_CTRL: ENABLE_EXT_PA_LNA (Bit 1) */ +#define BLE_BLESS_EXT_PA_LNA_CTRL_ENABLE_EXT_PA_LNA_Msk (0x2UL) /*!< BLE_BLESS EXT_PA_LNA_CTRL: ENABLE_EXT_PA_LNA (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_EXT_PA_LNA_CTRL_CHIP_EN_POL_Pos (2UL) /*!< BLE_BLESS EXT_PA_LNA_CTRL: CHIP_EN_POL (Bit 2) */ +#define BLE_BLESS_EXT_PA_LNA_CTRL_CHIP_EN_POL_Msk (0x4UL) /*!< BLE_BLESS EXT_PA_LNA_CTRL: CHIP_EN_POL (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_EXT_PA_LNA_CTRL_PA_CTRL_POL_Pos (3UL) /*!< BLE_BLESS EXT_PA_LNA_CTRL: PA_CTRL_POL (Bit 3) */ +#define BLE_BLESS_EXT_PA_LNA_CTRL_PA_CTRL_POL_Msk (0x8UL) /*!< BLE_BLESS EXT_PA_LNA_CTRL: PA_CTRL_POL (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_EXT_PA_LNA_CTRL_LNA_CTRL_POL_Pos (4UL) /*!< BLE_BLESS EXT_PA_LNA_CTRL: LNA_CTRL_POL (Bit 4) */ +#define BLE_BLESS_EXT_PA_LNA_CTRL_LNA_CTRL_POL_Msk (0x10UL) /*!< BLE_BLESS EXT_PA_LNA_CTRL: LNA_CTRL_POL (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_EXT_PA_LNA_CTRL_OUT_EN_DRIVE_VAL_Pos (5UL) /*!< BLE_BLESS EXT_PA_LNA_CTRL: OUT_EN_DRIVE_VAL (Bit 5) */ +#define BLE_BLESS_EXT_PA_LNA_CTRL_OUT_EN_DRIVE_VAL_Msk (0x20UL) /*!< BLE_BLESS EXT_PA_LNA_CTRL: OUT_EN_DRIVE_VAL (Bitfield-Mask: 0x01)*/ +/* ============================================ BLE_BLESS.LL_PKT_RSSI_CH_ENERGY ============================================ */ +#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RSSI_Pos (0UL) /*!< BLE_BLESS LL_PKT_RSSI_CH_ENERGY: RSSI (Bit 0) */ +#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RSSI_Msk (0xffffUL) /*!< BLE_BLESS LL_PKT_RSSI_CH_ENERGY: RSSI (Bitfield-Mask: 0xffff)*/ +#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RX_CHANNEL_Pos (16UL) /*!< BLE_BLESS LL_PKT_RSSI_CH_ENERGY: RX_CHANNEL (Bit 16) */ +#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RX_CHANNEL_Msk (0x3f0000UL) /*!< BLE_BLESS LL_PKT_RSSI_CH_ENERGY: RX_CHANNEL (Bitfield-Mask: 0x3f)*/ +#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_PKT_RSSI_OR_CH_ENERGY_Pos (22UL) /*!< BLE_BLESS LL_PKT_RSSI_CH_ENERGY: PKT_RSSI_OR_CH_ENERGY (Bit 22)*/ +#define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_PKT_RSSI_OR_CH_ENERGY_Msk (0x400000UL) /*!< BLE_BLESS LL_PKT_RSSI_CH_ENERGY: PKT_RSSI_OR_CH_ENERGY (Bitfield-Mask: 0x01)*/ +/* =================================================== BLE_BLESS.MT_CFG ==================================================== */ +#define BLE_BLESS_MT_CFG_ENABLE_BLERD_Pos (0UL) /*!< BLE_BLESS MT_CFG: ENABLE_BLERD (Bit 0) */ +#define BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk (0x1UL) /*!< BLE_BLESS MT_CFG: ENABLE_BLERD (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXIT_CFG_Pos (1UL) /*!< BLE_BLESS MT_CFG: DEEPSLEEP_EXIT_CFG (Bit 1) */ +#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXIT_CFG_Msk (0x2UL) /*!< BLE_BLESS MT_CFG: DEEPSLEEP_EXIT_CFG (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXITED_Pos (2UL) /*!< BLE_BLESS MT_CFG: DEEPSLEEP_EXITED (Bit 2) */ +#define BLE_BLESS_MT_CFG_DEEPSLEEP_EXITED_Msk (0x4UL) /*!< BLE_BLESS MT_CFG: DEEPSLEEP_EXITED (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Pos (3UL) /*!< BLE_BLESS MT_CFG: ACT_LDO_NOT_BUCK (Bit 3) */ +#define BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Msk (0x8UL) /*!< BLE_BLESS MT_CFG: ACT_LDO_NOT_BUCK (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Pos (4UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_HVLDO_BYPASS (Bit 4) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Msk (0x10UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_HVLDO_BYPASS (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MT_CFG_HVLDO_BYPASS_Pos (5UL) /*!< BLE_BLESS MT_CFG: HVLDO_BYPASS (Bit 5) */ +#define BLE_BLESS_MT_CFG_HVLDO_BYPASS_Msk (0x20UL) /*!< BLE_BLESS MT_CFG: HVLDO_BYPASS (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_ACT_REGULATOR_Pos (6UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_ACT_REGULATOR (Bit 6) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_ACT_REGULATOR_Msk (0x40UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_ACT_REGULATOR (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MT_CFG_ACT_REGULATOR_EN_Pos (7UL) /*!< BLE_BLESS MT_CFG: ACT_REGULATOR_EN (Bit 7) */ +#define BLE_BLESS_MT_CFG_ACT_REGULATOR_EN_Msk (0x80UL) /*!< BLE_BLESS MT_CFG: ACT_REGULATOR_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_DIG_REGULATOR_Pos (8UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_DIG_REGULATOR (Bit 8) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_DIG_REGULATOR_Msk (0x100UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_DIG_REGULATOR (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MT_CFG_DIG_REGULATOR_EN_Pos (9UL) /*!< BLE_BLESS MT_CFG: DIG_REGULATOR_EN (Bit 9) */ +#define BLE_BLESS_MT_CFG_DIG_REGULATOR_EN_Msk (0x200UL) /*!< BLE_BLESS MT_CFG: DIG_REGULATOR_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_RET_SWITCH_Pos (10UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_RET_SWITCH (Bit 10) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_RET_SWITCH_Msk (0x400UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_RET_SWITCH (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MT_CFG_RET_SWITCH_Pos (11UL) /*!< BLE_BLESS MT_CFG: RET_SWITCH (Bit 11) */ +#define BLE_BLESS_MT_CFG_RET_SWITCH_Msk (0x800UL) /*!< BLE_BLESS MT_CFG: RET_SWITCH (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_ISOLATE_Pos (12UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_ISOLATE (Bit 12) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_ISOLATE_Msk (0x1000UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_ISOLATE (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_ISOLATE_N_Pos (13UL) /*!< BLE_BLESS MT_CFG: ISOLATE_N (Bit 13) */ +#define BLE_BLESS_MT_CFG_ISOLATE_N_Msk (0x2000UL) /*!< BLE_BLESS MT_CFG: ISOLATE_N (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_LL_CLK_EN_Pos (14UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_LL_CLK_EN (Bit 14) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_LL_CLK_EN_Msk (0x4000UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_LL_CLK_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MT_CFG_LL_CLK_EN_Pos (15UL) /*!< BLE_BLESS MT_CFG: LL_CLK_EN (Bit 15) */ +#define BLE_BLESS_MT_CFG_LL_CLK_EN_Msk (0x8000UL) /*!< BLE_BLESS MT_CFG: LL_CLK_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Pos (16UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_HVLDO_EN (Bit 16) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Msk (0x10000UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_HVLDO_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_HVLDO_EN_Pos (17UL) /*!< BLE_BLESS MT_CFG: HVLDO_EN (Bit 17) */ +#define BLE_BLESS_MT_CFG_HVLDO_EN_Msk (0x20000UL) /*!< BLE_BLESS MT_CFG: HVLDO_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Pos (18UL) /*!< BLE_BLESS MT_CFG: DPSLP_ECO_ON (Bit 18) */ +#define BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Msk (0x40000UL) /*!< BLE_BLESS MT_CFG: DPSLP_ECO_ON (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_RESET_N_Pos (19UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_RESET_N (Bit 19) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_RESET_N_Msk (0x80000UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_RESET_N (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_RESET_N_Pos (20UL) /*!< BLE_BLESS MT_CFG: RESET_N (Bit 20) */ +#define BLE_BLESS_MT_CFG_RESET_N_Msk (0x100000UL) /*!< BLE_BLESS MT_CFG: RESET_N (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_XTAL_EN_Pos (21UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_XTAL_EN (Bit 21) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_XTAL_EN_Msk (0x200000UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_XTAL_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_XTAL_EN_Pos (22UL) /*!< BLE_BLESS MT_CFG: XTAL_EN (Bit 22) */ +#define BLE_BLESS_MT_CFG_XTAL_EN_Msk (0x400000UL) /*!< BLE_BLESS MT_CFG: XTAL_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_CLK_EN_Pos (23UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_CLK_EN (Bit 23) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_CLK_EN_Msk (0x800000UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_CLK_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_BLERD_CLK_EN_Pos (24UL) /*!< BLE_BLESS MT_CFG: BLERD_CLK_EN (Bit 24) */ +#define BLE_BLESS_MT_CFG_BLERD_CLK_EN_Msk (0x1000000UL) /*!< BLE_BLESS MT_CFG: BLERD_CLK_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_RET_LDO_OL_Pos (25UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_RET_LDO_OL (Bit 25) */ +#define BLE_BLESS_MT_CFG_OVERRIDE_RET_LDO_OL_Msk (0x2000000UL) /*!< BLE_BLESS MT_CFG: OVERRIDE_RET_LDO_OL (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MT_CFG_RET_LDO_OL_Pos (26UL) /*!< BLE_BLESS MT_CFG: RET_LDO_OL (Bit 26) */ +#define BLE_BLESS_MT_CFG_RET_LDO_OL_Msk (0x4000000UL) /*!< BLE_BLESS MT_CFG: RET_LDO_OL (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_CFG_HVLDO_POR_HV_Pos (27UL) /*!< BLE_BLESS MT_CFG: HVLDO_POR_HV (Bit 27) */ +#define BLE_BLESS_MT_CFG_HVLDO_POR_HV_Msk (0x8000000UL) /*!< BLE_BLESS MT_CFG: HVLDO_POR_HV (Bitfield-Mask: 0x01) */ +/* ================================================ BLE_BLESS.MT_DELAY_CFG ================================================= */ +#define BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Pos (0UL) /*!< BLE_BLESS MT_DELAY_CFG: HVLDO_STARTUP_DELAY (Bit 0) */ +#define BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Msk (0xffUL) /*!< BLE_BLESS MT_DELAY_CFG: HVLDO_STARTUP_DELAY (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Pos (8UL) /*!< BLE_BLESS MT_DELAY_CFG: ISOLATE_DEASSERT_DELAY (Bit 8) */ +#define BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Msk (0xff00UL) /*!< BLE_BLESS MT_DELAY_CFG: ISOLATE_DEASSERT_DELAY (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Pos (16UL) /*!< BLE_BLESS MT_DELAY_CFG: ACT_TO_SWITCH_DELAY (Bit 16) */ +#define BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Msk (0xff0000UL) /*!< BLE_BLESS MT_DELAY_CFG: ACT_TO_SWITCH_DELAY (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Pos (24UL) /*!< BLE_BLESS MT_DELAY_CFG: HVLDO_DISABLE_DELAY (Bit 24) */ +#define BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Msk (0xff000000UL) /*!< BLE_BLESS MT_DELAY_CFG: HVLDO_DISABLE_DELAY (Bitfield-Mask: 0xff)*/ +/* ================================================ BLE_BLESS.MT_DELAY_CFG2 ================================================ */ +#define BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Pos (0UL) /*!< BLE_BLESS MT_DELAY_CFG2: OSC_STARTUP_DELAY_LF (Bit 0) */ +#define BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Msk (0xffUL) /*!< BLE_BLESS MT_DELAY_CFG2: OSC_STARTUP_DELAY_LF (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_MT_DELAY_CFG2_DSM_OFFSET_TO_WAKEUP_INSTANT_LF_Pos (8UL) /*!< BLE_BLESS MT_DELAY_CFG2: DSM_OFFSET_TO_WAKEUP_INSTANT_LF (Bit 8)*/ +#define BLE_BLESS_MT_DELAY_CFG2_DSM_OFFSET_TO_WAKEUP_INSTANT_LF_Msk (0xff00UL) /*!< BLE_BLESS MT_DELAY_CFG2: DSM_OFFSET_TO_WAKEUP_INSTANT_LF (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Pos (16UL) /*!< BLE_BLESS MT_DELAY_CFG2: ACT_STARTUP_DELAY (Bit 16) */ +#define BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Msk (0xff0000UL) /*!< BLE_BLESS MT_DELAY_CFG2: ACT_STARTUP_DELAY (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Pos (24UL) /*!< BLE_BLESS MT_DELAY_CFG2: DIG_LDO_STARTUP_DELAY (Bit 24) */ +#define BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Msk (0xff000000UL) /*!< BLE_BLESS MT_DELAY_CFG2: DIG_LDO_STARTUP_DELAY (Bitfield-Mask: 0xff)*/ +/* ================================================ BLE_BLESS.MT_DELAY_CFG3 ================================================ */ +#define BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Pos (0UL) /*!< BLE_BLESS MT_DELAY_CFG3: XTAL_DISABLE_DELAY (Bit 0) */ +#define BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Msk (0xffUL) /*!< BLE_BLESS MT_DELAY_CFG3: XTAL_DISABLE_DELAY (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Pos (8UL) /*!< BLE_BLESS MT_DELAY_CFG3: DIG_LDO_DISABLE_DELAY (Bit 8) */ +#define BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Msk (0xff00UL) /*!< BLE_BLESS MT_DELAY_CFG3: DIG_LDO_DISABLE_DELAY (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Pos (16UL) /*!< BLE_BLESS MT_DELAY_CFG3: VDDR_STABLE_DELAY (Bit 16) */ +#define BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Msk (0xff0000UL) /*!< BLE_BLESS MT_DELAY_CFG3: VDDR_STABLE_DELAY (Bitfield-Mask: 0xff)*/ +/* ================================================= BLE_BLESS.MT_VIO_CTRL ================================================= */ +#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Pos (0UL) /*!< BLE_BLESS MT_VIO_CTRL: SRSS_SWITCH_EN (Bit 0) */ +#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk (0x1UL) /*!< BLE_BLESS MT_VIO_CTRL: SRSS_SWITCH_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Pos (1UL) /*!< BLE_BLESS MT_VIO_CTRL: SRSS_SWITCH_EN_DLY (Bit 1) */ +#define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Msk (0x2UL) /*!< BLE_BLESS MT_VIO_CTRL: SRSS_SWITCH_EN_DLY (Bitfield-Mask: 0x01)*/ +/* ================================================== BLE_BLESS.MT_STATUS ================================================== */ +#define BLE_BLESS_MT_STATUS_BLESS_STATE_Pos (0UL) /*!< BLE_BLESS MT_STATUS: BLESS_STATE (Bit 0) */ +#define BLE_BLESS_MT_STATUS_BLESS_STATE_Msk (0x1UL) /*!< BLE_BLESS MT_STATUS: BLESS_STATE (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_MT_STATUS_MT_CURR_STATE_Pos (1UL) /*!< BLE_BLESS MT_STATUS: MT_CURR_STATE (Bit 1) */ +#define BLE_BLESS_MT_STATUS_MT_CURR_STATE_Msk (0x1eUL) /*!< BLE_BLESS MT_STATUS: MT_CURR_STATE (Bitfield-Mask: 0x0f) */ +#define BLE_BLESS_MT_STATUS_HVLDO_STARTUP_CURR_STATE_Pos (5UL) /*!< BLE_BLESS MT_STATUS: HVLDO_STARTUP_CURR_STATE (Bit 5) */ +#define BLE_BLESS_MT_STATUS_HVLDO_STARTUP_CURR_STATE_Msk (0xe0UL) /*!< BLE_BLESS MT_STATUS: HVLDO_STARTUP_CURR_STATE (Bitfield-Mask: 0x07)*/ +/* =============================================== BLE_BLESS.PWR_CTRL_SM_ST ================================================ */ +#define BLE_BLESS_PWR_CTRL_SM_ST_PWR_CTRL_SM_CURR_STATE_Pos (0UL) /*!< BLE_BLESS PWR_CTRL_SM_ST: PWR_CTRL_SM_CURR_STATE (Bit 0)*/ +#define BLE_BLESS_PWR_CTRL_SM_ST_PWR_CTRL_SM_CURR_STATE_Msk (0xfUL) /*!< BLE_BLESS PWR_CTRL_SM_ST: PWR_CTRL_SM_CURR_STATE (Bitfield-Mask: 0x0f)*/ +/* ================================================= BLE_BLESS.HVLDO_CTRL ================================================== */ +#define BLE_BLESS_HVLDO_CTRL_ADFT_EN_Pos (0UL) /*!< BLE_BLESS HVLDO_CTRL: ADFT_EN (Bit 0) */ +#define BLE_BLESS_HVLDO_CTRL_ADFT_EN_Msk (0x1UL) /*!< BLE_BLESS HVLDO_CTRL: ADFT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_HVLDO_CTRL_ADFT_CTRL_Pos (1UL) /*!< BLE_BLESS HVLDO_CTRL: ADFT_CTRL (Bit 1) */ +#define BLE_BLESS_HVLDO_CTRL_ADFT_CTRL_Msk (0x1eUL) /*!< BLE_BLESS HVLDO_CTRL: ADFT_CTRL (Bitfield-Mask: 0x0f) */ +#define BLE_BLESS_HVLDO_CTRL_VREF_EXT_EN_Pos (6UL) /*!< BLE_BLESS HVLDO_CTRL: VREF_EXT_EN (Bit 6) */ +#define BLE_BLESS_HVLDO_CTRL_VREF_EXT_EN_Msk (0x40UL) /*!< BLE_BLESS HVLDO_CTRL: VREF_EXT_EN (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_HVLDO_CTRL_STATUS_Pos (31UL) /*!< BLE_BLESS HVLDO_CTRL: STATUS (Bit 31) */ +#define BLE_BLESS_HVLDO_CTRL_STATUS_Msk (0x80000000UL) /*!< BLE_BLESS HVLDO_CTRL: STATUS (Bitfield-Mask: 0x01) */ +/* ================================================ BLE_BLESS.MISC_EN_CTRL ================================================= */ +#define BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Pos (0UL) /*!< BLE_BLESS MISC_EN_CTRL: BUCK_EN_CTRL (Bit 0) */ +#define BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Msk (0x1UL) /*!< BLE_BLESS MISC_EN_CTRL: BUCK_EN_CTRL (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Pos (1UL) /*!< BLE_BLESS MISC_EN_CTRL: ACT_REG_EN_CTRL (Bit 1) */ +#define BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Msk (0x2UL) /*!< BLE_BLESS MISC_EN_CTRL: ACT_REG_EN_CTRL (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_EN_Pos (2UL) /*!< BLE_BLESS MISC_EN_CTRL: LPM_DRIFT_EN (Bit 2) */ +#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_EN_Msk (0x4UL) /*!< BLE_BLESS MISC_EN_CTRL: LPM_DRIFT_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_MULTI_Pos (3UL) /*!< BLE_BLESS MISC_EN_CTRL: LPM_DRIFT_MULTI (Bit 3) */ +#define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_MULTI_Msk (0x8UL) /*!< BLE_BLESS MISC_EN_CTRL: LPM_DRIFT_MULTI (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_MISC_EN_CTRL_LPM_ENTRY_CTRL_MODE_Pos (4UL) /*!< BLE_BLESS MISC_EN_CTRL: LPM_ENTRY_CTRL_MODE (Bit 4) */ +#define BLE_BLESS_MISC_EN_CTRL_LPM_ENTRY_CTRL_MODE_Msk (0x10UL) /*!< BLE_BLESS MISC_EN_CTRL: LPM_ENTRY_CTRL_MODE (Bitfield-Mask: 0x01)*/ +/* ================================================ BLE_BLESS.EFUSE_CONFIG ================================================= */ +#define BLE_BLESS_EFUSE_CONFIG_EFUSE_MODE_Pos (0UL) /*!< BLE_BLESS EFUSE_CONFIG: EFUSE_MODE (Bit 0) */ +#define BLE_BLESS_EFUSE_CONFIG_EFUSE_MODE_Msk (0x1UL) /*!< BLE_BLESS EFUSE_CONFIG: EFUSE_MODE (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_EFUSE_CONFIG_EFUSE_READ_Pos (1UL) /*!< BLE_BLESS EFUSE_CONFIG: EFUSE_READ (Bit 1) */ +#define BLE_BLESS_EFUSE_CONFIG_EFUSE_READ_Msk (0x2UL) /*!< BLE_BLESS EFUSE_CONFIG: EFUSE_READ (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_EFUSE_CONFIG_EFUSE_WRITE_Pos (2UL) /*!< BLE_BLESS EFUSE_CONFIG: EFUSE_WRITE (Bit 2) */ +#define BLE_BLESS_EFUSE_CONFIG_EFUSE_WRITE_Msk (0x4UL) /*!< BLE_BLESS EFUSE_CONFIG: EFUSE_WRITE (Bitfield-Mask: 0x01) */ +/* =============================================== BLE_BLESS.EFUSE_TIM_CTRL1 =============================================== */ +#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_HIGH_Pos (0UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: SCLK_HIGH (Bit 0) */ +#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_HIGH_Msk (0xffUL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: SCLK_HIGH (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_LOW_Pos (8UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: SCLK_LOW (Bit 8) */ +#define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_LOW_Msk (0xff00UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: SCLK_LOW (Bitfield-Mask: 0xff) */ +#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_SETUP_TIME_Pos (16UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: CS_SCLK_SETUP_TIME (Bit 16) */ +#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_SETUP_TIME_Msk (0xf0000UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: CS_SCLK_SETUP_TIME (Bitfield-Mask: 0x0f)*/ +#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_HOLD_TIME_Pos (20UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: CS_SCLK_HOLD_TIME (Bit 20) */ +#define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_HOLD_TIME_Msk (0xf00000UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: CS_SCLK_HOLD_TIME (Bitfield-Mask: 0x0f)*/ +#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_SETUP_TIME_Pos (24UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: RW_CS_SETUP_TIME (Bit 24) */ +#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_SETUP_TIME_Msk (0xf000000UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: RW_CS_SETUP_TIME (Bitfield-Mask: 0x0f)*/ +#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_HOLD_TIME_Pos (28UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: RW_CS_HOLD_TIME (Bit 28) */ +#define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_HOLD_TIME_Msk (0xf0000000UL) /*!< BLE_BLESS EFUSE_TIM_CTRL1: RW_CS_HOLD_TIME (Bitfield-Mask: 0x0f)*/ +/* =============================================== BLE_BLESS.EFUSE_TIM_CTRL2 =============================================== */ +#define BLE_BLESS_EFUSE_TIM_CTRL2_DATA_SAMPLE_TIME_Pos (0UL) /*!< BLE_BLESS EFUSE_TIM_CTRL2: DATA_SAMPLE_TIME (Bit 0) */ +#define BLE_BLESS_EFUSE_TIM_CTRL2_DATA_SAMPLE_TIME_Msk (0xffUL) /*!< BLE_BLESS EFUSE_TIM_CTRL2: DATA_SAMPLE_TIME (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_EFUSE_TIM_CTRL2_DOUT_CS_HOLD_TIME_Pos (8UL) /*!< BLE_BLESS EFUSE_TIM_CTRL2: DOUT_CS_HOLD_TIME (Bit 8) */ +#define BLE_BLESS_EFUSE_TIM_CTRL2_DOUT_CS_HOLD_TIME_Msk (0xf00UL) /*!< BLE_BLESS EFUSE_TIM_CTRL2: DOUT_CS_HOLD_TIME (Bitfield-Mask: 0x0f)*/ +/* =============================================== BLE_BLESS.EFUSE_TIM_CTRL3 =============================================== */ +#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_SETUP_TIME_Pos (0UL) /*!< BLE_BLESS EFUSE_TIM_CTRL3: PGM_SCLK_SETUP_TIME (Bit 0) */ +#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_SETUP_TIME_Msk (0xfUL) /*!< BLE_BLESS EFUSE_TIM_CTRL3: PGM_SCLK_SETUP_TIME (Bitfield-Mask: 0x0f)*/ +#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_HOLD_TIME_Pos (4UL) /*!< BLE_BLESS EFUSE_TIM_CTRL3: PGM_SCLK_HOLD_TIME (Bit 4) */ +#define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_HOLD_TIME_Msk (0xf0UL) /*!< BLE_BLESS EFUSE_TIM_CTRL3: PGM_SCLK_HOLD_TIME (Bitfield-Mask: 0x0f)*/ +#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_SETUP_TIME_Pos (8UL) /*!< BLE_BLESS EFUSE_TIM_CTRL3: AVDD_CS_SETUP_TIME (Bit 8) */ +#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_SETUP_TIME_Msk (0xff00UL) /*!< BLE_BLESS EFUSE_TIM_CTRL3: AVDD_CS_SETUP_TIME (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_HOLD_TIME_Pos (16UL) /*!< BLE_BLESS EFUSE_TIM_CTRL3: AVDD_CS_HOLD_TIME (Bit 16) */ +#define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_HOLD_TIME_Msk (0xff0000UL) /*!< BLE_BLESS EFUSE_TIM_CTRL3: AVDD_CS_HOLD_TIME (Bitfield-Mask: 0xff)*/ +/* ================================================ BLE_BLESS.EFUSE_RDATA_L ================================================ */ +#define BLE_BLESS_EFUSE_RDATA_L_DATA_Pos (0UL) /*!< BLE_BLESS EFUSE_RDATA_L: DATA (Bit 0) */ +#define BLE_BLESS_EFUSE_RDATA_L_DATA_Msk (0xffffffffUL) /*!< BLE_BLESS EFUSE_RDATA_L: DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================ BLE_BLESS.EFUSE_RDATA_H ================================================ */ +#define BLE_BLESS_EFUSE_RDATA_H_DATA_Pos (0UL) /*!< BLE_BLESS EFUSE_RDATA_H: DATA (Bit 0) */ +#define BLE_BLESS_EFUSE_RDATA_H_DATA_Msk (0xffffffffUL) /*!< BLE_BLESS EFUSE_RDATA_H: DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================ BLE_BLESS.EFUSE_WDATA_L ================================================ */ +#define BLE_BLESS_EFUSE_WDATA_L_DATA_Pos (0UL) /*!< BLE_BLESS EFUSE_WDATA_L: DATA (Bit 0) */ +#define BLE_BLESS_EFUSE_WDATA_L_DATA_Msk (0xffffffffUL) /*!< BLE_BLESS EFUSE_WDATA_L: DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================ BLE_BLESS.EFUSE_WDATA_H ================================================ */ +#define BLE_BLESS_EFUSE_WDATA_H_DATA_Pos (0UL) /*!< BLE_BLESS EFUSE_WDATA_H: DATA (Bit 0) */ +#define BLE_BLESS_EFUSE_WDATA_H_DATA_Msk (0xffffffffUL) /*!< BLE_BLESS EFUSE_WDATA_H: DATA (Bitfield-Mask: 0xffffffff) */ +/* =============================================== BLE_BLESS.DIV_BY_625_CFG ================================================ */ +#define BLE_BLESS_DIV_BY_625_CFG_ENABLE_Pos (1UL) /*!< BLE_BLESS DIV_BY_625_CFG: ENABLE (Bit 1) */ +#define BLE_BLESS_DIV_BY_625_CFG_ENABLE_Msk (0x2UL) /*!< BLE_BLESS DIV_BY_625_CFG: ENABLE (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_DIV_BY_625_CFG_DIVIDEND_Pos (8UL) /*!< BLE_BLESS DIV_BY_625_CFG: DIVIDEND (Bit 8) */ +#define BLE_BLESS_DIV_BY_625_CFG_DIVIDEND_Msk (0xffff00UL) /*!< BLE_BLESS DIV_BY_625_CFG: DIVIDEND (Bitfield-Mask: 0xffff)*/ +/* =============================================== BLE_BLESS.DIV_BY_625_STS ================================================ */ +#define BLE_BLESS_DIV_BY_625_STS_QUOTIENT_Pos (0UL) /*!< BLE_BLESS DIV_BY_625_STS: QUOTIENT (Bit 0) */ +#define BLE_BLESS_DIV_BY_625_STS_QUOTIENT_Msk (0x3fUL) /*!< BLE_BLESS DIV_BY_625_STS: QUOTIENT (Bitfield-Mask: 0x3f) */ +#define BLE_BLESS_DIV_BY_625_STS_REMAINDER_Pos (8UL) /*!< BLE_BLESS DIV_BY_625_STS: REMAINDER (Bit 8) */ +#define BLE_BLESS_DIV_BY_625_STS_REMAINDER_Msk (0x3ff00UL) /*!< BLE_BLESS DIV_BY_625_STS: REMAINDER (Bitfield-Mask: 0x3ff)*/ +/* =============================================== BLE_BLESS.PACKET_COUNTER0 =============================================== */ +#define BLE_BLESS_PACKET_COUNTER0_PACKET_COUNTER_LOWER_Pos (0UL) /*!< BLE_BLESS PACKET_COUNTER0: PACKET_COUNTER_LOWER (Bit 0) */ +#define BLE_BLESS_PACKET_COUNTER0_PACKET_COUNTER_LOWER_Msk (0xffffffffUL) /*!< BLE_BLESS PACKET_COUNTER0: PACKET_COUNTER_LOWER (Bitfield-Mask: 0xffffffff)*/ +/* =============================================== BLE_BLESS.PACKET_COUNTER2 =============================================== */ +#define BLE_BLESS_PACKET_COUNTER2_PACKET_COUNTER_UPPER_Pos (0UL) /*!< BLE_BLESS PACKET_COUNTER2: PACKET_COUNTER_UPPER (Bit 0) */ +#define BLE_BLESS_PACKET_COUNTER2_PACKET_COUNTER_UPPER_Msk (0xffUL) /*!< BLE_BLESS PACKET_COUNTER2: PACKET_COUNTER_UPPER (Bitfield-Mask: 0xff)*/ +/* ================================================= BLE_BLESS.IV_MASTER0 ================================================== */ +#define BLE_BLESS_IV_MASTER0_IV_MASTER_Pos (0UL) /*!< BLE_BLESS IV_MASTER0: IV_MASTER (Bit 0) */ +#define BLE_BLESS_IV_MASTER0_IV_MASTER_Msk (0xffffffffUL) /*!< BLE_BLESS IV_MASTER0: IV_MASTER (Bitfield-Mask: 0xffffffff)*/ +/* ================================================== BLE_BLESS.IV_SLAVE0 ================================================== */ +#define BLE_BLESS_IV_SLAVE0_IV_SLAVE_Pos (0UL) /*!< BLE_BLESS IV_SLAVE0: IV_SLAVE (Bit 0) */ +#define BLE_BLESS_IV_SLAVE0_IV_SLAVE_Msk (0xffffffffUL) /*!< BLE_BLESS IV_SLAVE0: IV_SLAVE (Bitfield-Mask: 0xffffffff) */ +/* =================================================== BLE_BLESS.ENC_KEY =================================================== */ +#define BLE_BLESS_ENC_KEY_ENC_KEY_Pos (0UL) /*!< BLE_BLESS ENC_KEY: ENC_KEY (Bit 0) */ +#define BLE_BLESS_ENC_KEY_ENC_KEY_Msk (0xffffffffUL) /*!< BLE_BLESS ENC_KEY: ENC_KEY (Bitfield-Mask: 0xffffffff) */ +/* =================================================== BLE_BLESS.MIC_IN0 =================================================== */ +#define BLE_BLESS_MIC_IN0_MIC_IN_Pos (0UL) /*!< BLE_BLESS MIC_IN0: MIC_IN (Bit 0) */ +#define BLE_BLESS_MIC_IN0_MIC_IN_Msk (0xffffffffUL) /*!< BLE_BLESS MIC_IN0: MIC_IN (Bitfield-Mask: 0xffffffff) */ +/* ================================================== BLE_BLESS.MIC_OUT0 =================================================== */ +#define BLE_BLESS_MIC_OUT0_MIC_OUT_Pos (0UL) /*!< BLE_BLESS MIC_OUT0: MIC_OUT (Bit 0) */ +#define BLE_BLESS_MIC_OUT0_MIC_OUT_Msk (0xffffffffUL) /*!< BLE_BLESS MIC_OUT0: MIC_OUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= BLE_BLESS.ENC_PARAMS ================================================== */ +#define BLE_BLESS_ENC_PARAMS_DATA_PDU_HEADER_Pos (0UL) /*!< BLE_BLESS ENC_PARAMS: DATA_PDU_HEADER (Bit 0) */ +#define BLE_BLESS_ENC_PARAMS_DATA_PDU_HEADER_Msk (0x3UL) /*!< BLE_BLESS ENC_PARAMS: DATA_PDU_HEADER (Bitfield-Mask: 0x03)*/ +#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_Pos (2UL) /*!< BLE_BLESS ENC_PARAMS: PAYLOAD_LENGTH_LSB (Bit 2) */ +#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_Msk (0x7cUL) /*!< BLE_BLESS ENC_PARAMS: PAYLOAD_LENGTH_LSB (Bitfield-Mask: 0x1f)*/ +#define BLE_BLESS_ENC_PARAMS_DIRECTION_Pos (7UL) /*!< BLE_BLESS ENC_PARAMS: DIRECTION (Bit 7) */ +#define BLE_BLESS_ENC_PARAMS_DIRECTION_Msk (0x80UL) /*!< BLE_BLESS ENC_PARAMS: DIRECTION (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_EXT_Pos (8UL) /*!< BLE_BLESS ENC_PARAMS: PAYLOAD_LENGTH_LSB_EXT (Bit 8) */ +#define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_EXT_Msk (0x700UL) /*!< BLE_BLESS ENC_PARAMS: PAYLOAD_LENGTH_LSB_EXT (Bitfield-Mask: 0x07)*/ +#define BLE_BLESS_ENC_PARAMS_MEM_LATENCY_HIDE_Pos (11UL) /*!< BLE_BLESS ENC_PARAMS: MEM_LATENCY_HIDE (Bit 11) */ +#define BLE_BLESS_ENC_PARAMS_MEM_LATENCY_HIDE_Msk (0x800UL) /*!< BLE_BLESS ENC_PARAMS: MEM_LATENCY_HIDE (Bitfield-Mask: 0x01)*/ +/* ================================================= BLE_BLESS.ENC_CONFIG ================================================== */ +#define BLE_BLESS_ENC_CONFIG_START_PROC_Pos (0UL) /*!< BLE_BLESS ENC_CONFIG: START_PROC (Bit 0) */ +#define BLE_BLESS_ENC_CONFIG_START_PROC_Msk (0x1UL) /*!< BLE_BLESS ENC_CONFIG: START_PROC (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_ENC_CONFIG_ECB_CCM_Pos (1UL) /*!< BLE_BLESS ENC_CONFIG: ECB_CCM (Bit 1) */ +#define BLE_BLESS_ENC_CONFIG_ECB_CCM_Msk (0x2UL) /*!< BLE_BLESS ENC_CONFIG: ECB_CCM (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_ENC_CONFIG_DEC_ENC_Pos (2UL) /*!< BLE_BLESS ENC_CONFIG: DEC_ENC (Bit 2) */ +#define BLE_BLESS_ENC_CONFIG_DEC_ENC_Msk (0x4UL) /*!< BLE_BLESS ENC_CONFIG: DEC_ENC (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_ENC_CONFIG_PAYLOAD_LENGTH_MSB_Pos (8UL) /*!< BLE_BLESS ENC_CONFIG: PAYLOAD_LENGTH_MSB (Bit 8) */ +#define BLE_BLESS_ENC_CONFIG_PAYLOAD_LENGTH_MSB_Msk (0xff00UL) /*!< BLE_BLESS ENC_CONFIG: PAYLOAD_LENGTH_MSB (Bitfield-Mask: 0xff)*/ +#define BLE_BLESS_ENC_CONFIG_B0_FLAGS_Pos (16UL) /*!< BLE_BLESS ENC_CONFIG: B0_FLAGS (Bit 16) */ +#define BLE_BLESS_ENC_CONFIG_B0_FLAGS_Msk (0xff0000UL) /*!< BLE_BLESS ENC_CONFIG: B0_FLAGS (Bitfield-Mask: 0xff) */ +#define BLE_BLESS_ENC_CONFIG_AES_B0_DATA_OVERRIDE_Pos (24UL) /*!< BLE_BLESS ENC_CONFIG: AES_B0_DATA_OVERRIDE (Bit 24) */ +#define BLE_BLESS_ENC_CONFIG_AES_B0_DATA_OVERRIDE_Msk (0x1000000UL) /*!< BLE_BLESS ENC_CONFIG: AES_B0_DATA_OVERRIDE (Bitfield-Mask: 0x01)*/ +/* ================================================= BLE_BLESS.ENC_INTR_EN ================================================= */ +#define BLE_BLESS_ENC_INTR_EN_AUTH_PASS_INTR_EN_Pos (0UL) /*!< BLE_BLESS ENC_INTR_EN: AUTH_PASS_INTR_EN (Bit 0) */ +#define BLE_BLESS_ENC_INTR_EN_AUTH_PASS_INTR_EN_Msk (0x1UL) /*!< BLE_BLESS ENC_INTR_EN: AUTH_PASS_INTR_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_ENC_INTR_EN_ECB_PROC_INTR_EN_Pos (1UL) /*!< BLE_BLESS ENC_INTR_EN: ECB_PROC_INTR_EN (Bit 1) */ +#define BLE_BLESS_ENC_INTR_EN_ECB_PROC_INTR_EN_Msk (0x2UL) /*!< BLE_BLESS ENC_INTR_EN: ECB_PROC_INTR_EN (Bitfield-Mask: 0x01)*/ +#define BLE_BLESS_ENC_INTR_EN_CCM_PROC_INTR_EN_Pos (2UL) /*!< BLE_BLESS ENC_INTR_EN: CCM_PROC_INTR_EN (Bit 2) */ +#define BLE_BLESS_ENC_INTR_EN_CCM_PROC_INTR_EN_Msk (0x4UL) /*!< BLE_BLESS ENC_INTR_EN: CCM_PROC_INTR_EN (Bitfield-Mask: 0x01)*/ +/* ================================================== BLE_BLESS.ENC_INTR =================================================== */ +#define BLE_BLESS_ENC_INTR_AUTH_PASS_INTR_Pos (0UL) /*!< BLE_BLESS ENC_INTR: AUTH_PASS_INTR (Bit 0) */ +#define BLE_BLESS_ENC_INTR_AUTH_PASS_INTR_Msk (0x1UL) /*!< BLE_BLESS ENC_INTR: AUTH_PASS_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_ENC_INTR_ECB_PROC_INTR_Pos (1UL) /*!< BLE_BLESS ENC_INTR: ECB_PROC_INTR (Bit 1) */ +#define BLE_BLESS_ENC_INTR_ECB_PROC_INTR_Msk (0x2UL) /*!< BLE_BLESS ENC_INTR: ECB_PROC_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_ENC_INTR_CCM_PROC_INTR_Pos (2UL) /*!< BLE_BLESS ENC_INTR: CCM_PROC_INTR (Bit 2) */ +#define BLE_BLESS_ENC_INTR_CCM_PROC_INTR_Msk (0x4UL) /*!< BLE_BLESS ENC_INTR: CCM_PROC_INTR (Bitfield-Mask: 0x01) */ +#define BLE_BLESS_ENC_INTR_IN_DATA_CLEAR_Pos (3UL) /*!< BLE_BLESS ENC_INTR: IN_DATA_CLEAR (Bit 3) */ +#define BLE_BLESS_ENC_INTR_IN_DATA_CLEAR_Msk (0x8UL) /*!< BLE_BLESS ENC_INTR: IN_DATA_CLEAR (Bitfield-Mask: 0x01) */ +/* ================================================= BLE_BLESS.B1_DATA_REG ================================================= */ +#define BLE_BLESS_B1_DATA_REG_B1_DATA_Pos (0UL) /*!< BLE_BLESS B1_DATA_REG: B1_DATA (Bit 0) */ +#define BLE_BLESS_B1_DATA_REG_B1_DATA_Msk (0xffffffffUL) /*!< BLE_BLESS B1_DATA_REG: B1_DATA (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== BLE_BLESS.ENC_MEM_BASE_ADDR ============================================== */ +#define BLE_BLESS_ENC_MEM_BASE_ADDR_ENC_MEM_Pos (0UL) /*!< BLE_BLESS ENC_MEM_BASE_ADDR: ENC_MEM (Bit 0) */ +#define BLE_BLESS_ENC_MEM_BASE_ADDR_ENC_MEM_Msk (0xffffffffUL) /*!< BLE_BLESS ENC_MEM_BASE_ADDR: ENC_MEM (Bitfield-Mask: 0xffffffff)*/ +/* ================================================= BLE_BLESS.TRIM_LDO_0 ================================================== */ +#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_VREG_Pos (0UL) /*!< BLE_BLESS TRIM_LDO_0: ACT_LDO_VREG (Bit 0) */ +#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_VREG_Msk (0xfUL) /*!< BLE_BLESS TRIM_LDO_0: ACT_LDO_VREG (Bitfield-Mask: 0x0f) */ +#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_ITAIL_Pos (4UL) /*!< BLE_BLESS TRIM_LDO_0: ACT_LDO_ITAIL (Bit 4) */ +#define BLE_BLESS_TRIM_LDO_0_ACT_LDO_ITAIL_Msk (0xf0UL) /*!< BLE_BLESS TRIM_LDO_0: ACT_LDO_ITAIL (Bitfield-Mask: 0x0f) */ +/* ================================================= BLE_BLESS.TRIM_LDO_1 ================================================== */ +#define BLE_BLESS_TRIM_LDO_1_ACT_REF_BGR_Pos (0UL) /*!< BLE_BLESS TRIM_LDO_1: ACT_REF_BGR (Bit 0) */ +#define BLE_BLESS_TRIM_LDO_1_ACT_REF_BGR_Msk (0xfUL) /*!< BLE_BLESS TRIM_LDO_1: ACT_REF_BGR (Bitfield-Mask: 0x0f) */ +#define BLE_BLESS_TRIM_LDO_1_SB_BGRES_Pos (4UL) /*!< BLE_BLESS TRIM_LDO_1: SB_BGRES (Bit 4) */ +#define BLE_BLESS_TRIM_LDO_1_SB_BGRES_Msk (0xf0UL) /*!< BLE_BLESS TRIM_LDO_1: SB_BGRES (Bitfield-Mask: 0x0f) */ +/* ================================================= BLE_BLESS.TRIM_LDO_2 ================================================== */ +#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_RES_Pos (0UL) /*!< BLE_BLESS TRIM_LDO_2: SB_BMULT_RES (Bit 0) */ +#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_RES_Msk (0x1fUL) /*!< BLE_BLESS TRIM_LDO_2: SB_BMULT_RES (Bitfield-Mask: 0x1f) */ +#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_NBIAS_Pos (5UL) /*!< BLE_BLESS TRIM_LDO_2: SB_BMULT_NBIAS (Bit 5) */ +#define BLE_BLESS_TRIM_LDO_2_SB_BMULT_NBIAS_Msk (0x60UL) /*!< BLE_BLESS TRIM_LDO_2: SB_BMULT_NBIAS (Bitfield-Mask: 0x03)*/ +/* ================================================= BLE_BLESS.TRIM_LDO_3 ================================================== */ +#define BLE_BLESS_TRIM_LDO_3_LVDET_Pos (0UL) /*!< BLE_BLESS TRIM_LDO_3: LVDET (Bit 0) */ +#define BLE_BLESS_TRIM_LDO_3_LVDET_Msk (0x1fUL) /*!< BLE_BLESS TRIM_LDO_3: LVDET (Bitfield-Mask: 0x1f) */ +#define BLE_BLESS_TRIM_LDO_3_SLOPE_SB_BMULT_Pos (5UL) /*!< BLE_BLESS TRIM_LDO_3: SLOPE_SB_BMULT (Bit 5) */ +#define BLE_BLESS_TRIM_LDO_3_SLOPE_SB_BMULT_Msk (0x60UL) /*!< BLE_BLESS TRIM_LDO_3: SLOPE_SB_BMULT (Bitfield-Mask: 0x03)*/ +/* ================================================== BLE_BLESS.TRIM_MXD =================================================== */ +#define BLE_BLESS_TRIM_MXD_MXD_TRIM_BITS_Pos (0UL) /*!< BLE_BLESS TRIM_MXD: MXD_TRIM_BITS (Bit 0) */ +#define BLE_BLESS_TRIM_MXD_MXD_TRIM_BITS_Msk (0xffUL) /*!< BLE_BLESS TRIM_MXD: MXD_TRIM_BITS (Bitfield-Mask: 0xff) */ +/* ================================================= BLE_BLESS.TRIM_LDO_4 ================================================== */ +#define BLE_BLESS_TRIM_LDO_4_T_LDO_Pos (0UL) /*!< BLE_BLESS TRIM_LDO_4: T_LDO (Bit 0) */ +#define BLE_BLESS_TRIM_LDO_4_T_LDO_Msk (0xffUL) /*!< BLE_BLESS TRIM_LDO_4: T_LDO (Bitfield-Mask: 0xff) */ +/* ================================================= BLE_BLESS.TRIM_LDO_5 ================================================== */ +#define BLE_BLESS_TRIM_LDO_5_RESERVED_Pos (0UL) /*!< BLE_BLESS TRIM_LDO_5: RESERVED (Bit 0) */ +#define BLE_BLESS_TRIM_LDO_5_RESERVED_Msk (0xffUL) /*!< BLE_BLESS TRIM_LDO_5: RESERVED (Bitfield-Mask: 0xff) */ + + +#endif /* _CYIP_BLE_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_cpuss.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_cpuss.h new file mode 100644 index 0000000000..a2320dfa79 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_cpuss.h @@ -0,0 +1,346 @@ +/***************************************************************************//** +* \file cyip_cpuss.h +* +* \brief +* CPUSS IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_CPUSS_H_ +#define _CYIP_CPUSS_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ CPUSS ================ */ +/* =========================================================================================================================== */ + +#define CPUSS_SECTION_SIZE 0x00010000UL + +/** + * \brief CPU subsystem (CPUSS) (CPUSS) + */ +typedef struct { /*!< CPUSS Structure */ + __IOM uint32_t CM0_CTL; /*!< 0x00000000 CM0+ control */ + __IM uint32_t RESERVED; + __IM uint32_t CM0_STATUS; /*!< 0x00000008 CM0+ status */ + __IM uint32_t RESERVED1; + __IOM uint32_t CM0_CLOCK_CTL; /*!< 0x00000010 CM0+ clock control */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t CM0_NMI_CTL; /*!< 0x0000001C CM0+ NMI control */ + __IOM uint32_t CM0_INT_CTL0; /*!< 0x00000020 CM0+ interrupt control 0 */ + __IOM uint32_t CM0_INT_CTL1; /*!< 0x00000024 CM0+ interrupt control 1 */ + __IOM uint32_t CM0_INT_CTL2; /*!< 0x00000028 CM0+ interrupt control 2 */ + __IOM uint32_t CM0_INT_CTL3; /*!< 0x0000002C CM0+ interrupt control 3 */ + __IOM uint32_t CM0_INT_CTL4; /*!< 0x00000030 CM0+ interrupt control 4 */ + __IOM uint32_t CM0_INT_CTL5; /*!< 0x00000034 CM0+ interrupt control 5 */ + __IOM uint32_t CM0_INT_CTL6; /*!< 0x00000038 CM0+ interrupt control 6 */ + __IOM uint32_t CM0_INT_CTL7; /*!< 0x0000003C CM0+ interrupt control 7 */ + __IM uint32_t RESERVED3[16]; + __IOM uint32_t CM4_PWR_CTL; /*!< 0x00000080 CM4 power control */ + __IM uint32_t RESERVED4; + __IM uint32_t CM4_STATUS; /*!< 0x00000088 CM4 status */ + __IM uint32_t RESERVED5; + __IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000090 CM4 clock control */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t CM4_NMI_CTL; /*!< 0x000000A0 CM4 NMI control */ + __IM uint32_t RESERVED7[7]; + __IOM uint32_t UDB_PWR_CTL; /*!< 0x000000C0 UDB power control */ + __IM uint32_t RESERVED8[15]; + __IOM uint32_t RAM0_CTL0; /*!< 0x00000100 RAM 0 control 0 */ + __IM uint32_t RESERVED9[15]; + __IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00000140 RAM 0 power control */ + __IOM uint32_t RAM1_CTL0; /*!< 0x00000180 RAM 1 control 0 */ + __IM uint32_t RESERVED10[3]; + __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00000190 RAM1 power control */ + __IM uint32_t RESERVED11[3]; + __IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000001B0 RAM2 power control */ + __IM uint32_t RESERVED13[3]; + __IOM uint32_t ROM_CTL; /*!< 0x000001C0 ROM control */ + __IM uint32_t RESERVED14[7]; + __IOM uint32_t ETB_PWR_CTL; /*!< 0x000001E0 ETB power control */ + __IM uint32_t RESERVED15[9]; + __IM uint32_t DP_STATUS; /*!< 0x00000208 Debug port status */ + __IM uint32_t RESERVED16[5]; + __IOM uint32_t BUFF_CTL; /*!< 0x00000220 Buffer control */ + __IM uint32_t RESERVED17[7]; + __IOM uint32_t SYSTICK_CTL; /*!< 0x00000240 SysTick timer control */ + __IM uint32_t RESERVED18[12]; + __IM uint32_t MBIST_STAT; /*!< 0x00000274 Memory BIST status */ + __IM uint32_t RESERVED19[2]; + __IOM uint32_t WOUNDING; /*!< 0x00000280 Wounding */ + __IM uint32_t RESERVED20[3]; + __IOM uint32_t PROTECTION; /*!< 0x00000290 Protection status */ + __IM uint32_t RESERVED21[3]; + __IOM uint32_t CM0_PC0_HANDLER; /*!< 0x000002A0 CM0+ protection context 0 handler */ + __IM uint32_t RESERVED22[3]; + __IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x000002B0 CM0+ vector table base */ + __IM uint32_t RESERVED23[3]; + __IOM uint32_t CM4_VECTOR_TABLE_BASE; /*!< 0x000002C0 CM4 vector table base */ + __IM uint32_t RESERVED24[79]; + __IM uint32_t IDENTITY; /*!< 0x00000400 Identity */ + __IM uint32_t RESERVED25[15103]; + __IOM uint32_t TRIM_ROM_CTL; /*!< 0x0000F000 ROM trim control */ + __IOM uint32_t TRIM_RAM_CTL; /*!< 0x0000F004 RAM trim control */ +} CPUSS_Type; /*!< Size = 61448 (0xF008) */ + + +/* ===================================================== CPUSS.CM0_CTL ===================================================== */ +#define CPUSS_CM0_CTL_SLV_STALL_Pos (28UL) /*!< CPUSS CM0_CTL: SLV_STALL (Bit 28) */ +#define CPUSS_CM0_CTL_SLV_STALL_Msk (0x10000000UL) /*!< CPUSS CM0_CTL: SLV_STALL (Bitfield-Mask: 0x01) */ +#define CPUSS_CM0_CTL_ENABLED_Pos (31UL) /*!< CPUSS CM0_CTL: ENABLED (Bit 31) */ +#define CPUSS_CM0_CTL_ENABLED_Msk (0x80000000UL) /*!< CPUSS CM0_CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* =================================================== CPUSS.CM0_STATUS ==================================================== */ +#define CPUSS_CM0_STATUS_SLEEPING_Pos (0UL) /*!< CPUSS CM0_STATUS: SLEEPING (Bit 0) */ +#define CPUSS_CM0_STATUS_SLEEPING_Msk (0x1UL) /*!< CPUSS CM0_STATUS: SLEEPING (Bitfield-Mask: 0x01) */ +#define CPUSS_CM0_STATUS_SLEEPDEEP_Pos (1UL) /*!< CPUSS CM0_STATUS: SLEEPDEEP (Bit 1) */ +#define CPUSS_CM0_STATUS_SLEEPDEEP_Msk (0x2UL) /*!< CPUSS CM0_STATUS: SLEEPDEEP (Bitfield-Mask: 0x01) */ +/* ================================================== CPUSS.CM0_CLOCK_CTL ================================================== */ +#define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos (8UL) /*!< CPUSS CM0_CLOCK_CTL: SLOW_INT_DIV (Bit 8) */ +#define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk (0xff00UL) /*!< CPUSS CM0_CLOCK_CTL: SLOW_INT_DIV (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Pos (24UL) /*!< CPUSS CM0_CLOCK_CTL: PERI_INT_DIV (Bit 24) */ +#define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Msk (0xff000000UL) /*!< CPUSS CM0_CLOCK_CTL: PERI_INT_DIV (Bitfield-Mask: 0xff) */ +/* =================================================== CPUSS.CM0_NMI_CTL =================================================== */ +#define CPUSS_CM0_NMI_CTL_MUX0_SEL_Pos (0UL) /*!< CPUSS CM0_NMI_CTL: MUX0_SEL (Bit 0) */ +#define CPUSS_CM0_NMI_CTL_MUX0_SEL_Msk (0xffUL) /*!< CPUSS CM0_NMI_CTL: MUX0_SEL (Bitfield-Mask: 0xff) */ +/* ================================================== CPUSS.CM0_INT_CTL0 =================================================== */ +#define CPUSS_CM0_INT_CTL0_MUX0_SEL_Pos (0UL) /*!< CPUSS CM0_INT_CTL0: MUX0_SEL (Bit 0) */ +#define CPUSS_CM0_INT_CTL0_MUX0_SEL_Msk (0xffUL) /*!< CPUSS CM0_INT_CTL0: MUX0_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL0_MUX1_SEL_Pos (8UL) /*!< CPUSS CM0_INT_CTL0: MUX1_SEL (Bit 8) */ +#define CPUSS_CM0_INT_CTL0_MUX1_SEL_Msk (0xff00UL) /*!< CPUSS CM0_INT_CTL0: MUX1_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL0_MUX2_SEL_Pos (16UL) /*!< CPUSS CM0_INT_CTL0: MUX2_SEL (Bit 16) */ +#define CPUSS_CM0_INT_CTL0_MUX2_SEL_Msk (0xff0000UL) /*!< CPUSS CM0_INT_CTL0: MUX2_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL0_MUX3_SEL_Pos (24UL) /*!< CPUSS CM0_INT_CTL0: MUX3_SEL (Bit 24) */ +#define CPUSS_CM0_INT_CTL0_MUX3_SEL_Msk (0xff000000UL) /*!< CPUSS CM0_INT_CTL0: MUX3_SEL (Bitfield-Mask: 0xff) */ +/* ================================================== CPUSS.CM0_INT_CTL1 =================================================== */ +#define CPUSS_CM0_INT_CTL1_MUX0_SEL_Pos (0UL) /*!< CPUSS CM0_INT_CTL1: MUX0_SEL (Bit 0) */ +#define CPUSS_CM0_INT_CTL1_MUX0_SEL_Msk (0xffUL) /*!< CPUSS CM0_INT_CTL1: MUX0_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL1_MUX1_SEL_Pos (8UL) /*!< CPUSS CM0_INT_CTL1: MUX1_SEL (Bit 8) */ +#define CPUSS_CM0_INT_CTL1_MUX1_SEL_Msk (0xff00UL) /*!< CPUSS CM0_INT_CTL1: MUX1_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL1_MUX2_SEL_Pos (16UL) /*!< CPUSS CM0_INT_CTL1: MUX2_SEL (Bit 16) */ +#define CPUSS_CM0_INT_CTL1_MUX2_SEL_Msk (0xff0000UL) /*!< CPUSS CM0_INT_CTL1: MUX2_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL1_MUX3_SEL_Pos (24UL) /*!< CPUSS CM0_INT_CTL1: MUX3_SEL (Bit 24) */ +#define CPUSS_CM0_INT_CTL1_MUX3_SEL_Msk (0xff000000UL) /*!< CPUSS CM0_INT_CTL1: MUX3_SEL (Bitfield-Mask: 0xff) */ +/* ================================================== CPUSS.CM0_INT_CTL2 =================================================== */ +#define CPUSS_CM0_INT_CTL2_MUX0_SEL_Pos (0UL) /*!< CPUSS CM0_INT_CTL2: MUX0_SEL (Bit 0) */ +#define CPUSS_CM0_INT_CTL2_MUX0_SEL_Msk (0xffUL) /*!< CPUSS CM0_INT_CTL2: MUX0_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL2_MUX1_SEL_Pos (8UL) /*!< CPUSS CM0_INT_CTL2: MUX1_SEL (Bit 8) */ +#define CPUSS_CM0_INT_CTL2_MUX1_SEL_Msk (0xff00UL) /*!< CPUSS CM0_INT_CTL2: MUX1_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL2_MUX2_SEL_Pos (16UL) /*!< CPUSS CM0_INT_CTL2: MUX2_SEL (Bit 16) */ +#define CPUSS_CM0_INT_CTL2_MUX2_SEL_Msk (0xff0000UL) /*!< CPUSS CM0_INT_CTL2: MUX2_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL2_MUX3_SEL_Pos (24UL) /*!< CPUSS CM0_INT_CTL2: MUX3_SEL (Bit 24) */ +#define CPUSS_CM0_INT_CTL2_MUX3_SEL_Msk (0xff000000UL) /*!< CPUSS CM0_INT_CTL2: MUX3_SEL (Bitfield-Mask: 0xff) */ +/* ================================================== CPUSS.CM0_INT_CTL3 =================================================== */ +#define CPUSS_CM0_INT_CTL3_MUX0_SEL_Pos (0UL) /*!< CPUSS CM0_INT_CTL3: MUX0_SEL (Bit 0) */ +#define CPUSS_CM0_INT_CTL3_MUX0_SEL_Msk (0xffUL) /*!< CPUSS CM0_INT_CTL3: MUX0_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL3_MUX1_SEL_Pos (8UL) /*!< CPUSS CM0_INT_CTL3: MUX1_SEL (Bit 8) */ +#define CPUSS_CM0_INT_CTL3_MUX1_SEL_Msk (0xff00UL) /*!< CPUSS CM0_INT_CTL3: MUX1_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL3_MUX2_SEL_Pos (16UL) /*!< CPUSS CM0_INT_CTL3: MUX2_SEL (Bit 16) */ +#define CPUSS_CM0_INT_CTL3_MUX2_SEL_Msk (0xff0000UL) /*!< CPUSS CM0_INT_CTL3: MUX2_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL3_MUX3_SEL_Pos (24UL) /*!< CPUSS CM0_INT_CTL3: MUX3_SEL (Bit 24) */ +#define CPUSS_CM0_INT_CTL3_MUX3_SEL_Msk (0xff000000UL) /*!< CPUSS CM0_INT_CTL3: MUX3_SEL (Bitfield-Mask: 0xff) */ +/* ================================================== CPUSS.CM0_INT_CTL4 =================================================== */ +#define CPUSS_CM0_INT_CTL4_MUX0_SEL_Pos (0UL) /*!< CPUSS CM0_INT_CTL4: MUX0_SEL (Bit 0) */ +#define CPUSS_CM0_INT_CTL4_MUX0_SEL_Msk (0xffUL) /*!< CPUSS CM0_INT_CTL4: MUX0_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL4_MUX1_SEL_Pos (8UL) /*!< CPUSS CM0_INT_CTL4: MUX1_SEL (Bit 8) */ +#define CPUSS_CM0_INT_CTL4_MUX1_SEL_Msk (0xff00UL) /*!< CPUSS CM0_INT_CTL4: MUX1_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL4_MUX2_SEL_Pos (16UL) /*!< CPUSS CM0_INT_CTL4: MUX2_SEL (Bit 16) */ +#define CPUSS_CM0_INT_CTL4_MUX2_SEL_Msk (0xff0000UL) /*!< CPUSS CM0_INT_CTL4: MUX2_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL4_MUX3_SEL_Pos (24UL) /*!< CPUSS CM0_INT_CTL4: MUX3_SEL (Bit 24) */ +#define CPUSS_CM0_INT_CTL4_MUX3_SEL_Msk (0xff000000UL) /*!< CPUSS CM0_INT_CTL4: MUX3_SEL (Bitfield-Mask: 0xff) */ +/* ================================================== CPUSS.CM0_INT_CTL5 =================================================== */ +#define CPUSS_CM0_INT_CTL5_MUX0_SEL_Pos (0UL) /*!< CPUSS CM0_INT_CTL5: MUX0_SEL (Bit 0) */ +#define CPUSS_CM0_INT_CTL5_MUX0_SEL_Msk (0xffUL) /*!< CPUSS CM0_INT_CTL5: MUX0_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL5_MUX1_SEL_Pos (8UL) /*!< CPUSS CM0_INT_CTL5: MUX1_SEL (Bit 8) */ +#define CPUSS_CM0_INT_CTL5_MUX1_SEL_Msk (0xff00UL) /*!< CPUSS CM0_INT_CTL5: MUX1_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL5_MUX2_SEL_Pos (16UL) /*!< CPUSS CM0_INT_CTL5: MUX2_SEL (Bit 16) */ +#define CPUSS_CM0_INT_CTL5_MUX2_SEL_Msk (0xff0000UL) /*!< CPUSS CM0_INT_CTL5: MUX2_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL5_MUX3_SEL_Pos (24UL) /*!< CPUSS CM0_INT_CTL5: MUX3_SEL (Bit 24) */ +#define CPUSS_CM0_INT_CTL5_MUX3_SEL_Msk (0xff000000UL) /*!< CPUSS CM0_INT_CTL5: MUX3_SEL (Bitfield-Mask: 0xff) */ +/* ================================================== CPUSS.CM0_INT_CTL6 =================================================== */ +#define CPUSS_CM0_INT_CTL6_MUX0_SEL_Pos (0UL) /*!< CPUSS CM0_INT_CTL6: MUX0_SEL (Bit 0) */ +#define CPUSS_CM0_INT_CTL6_MUX0_SEL_Msk (0xffUL) /*!< CPUSS CM0_INT_CTL6: MUX0_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL6_MUX1_SEL_Pos (8UL) /*!< CPUSS CM0_INT_CTL6: MUX1_SEL (Bit 8) */ +#define CPUSS_CM0_INT_CTL6_MUX1_SEL_Msk (0xff00UL) /*!< CPUSS CM0_INT_CTL6: MUX1_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL6_MUX2_SEL_Pos (16UL) /*!< CPUSS CM0_INT_CTL6: MUX2_SEL (Bit 16) */ +#define CPUSS_CM0_INT_CTL6_MUX2_SEL_Msk (0xff0000UL) /*!< CPUSS CM0_INT_CTL6: MUX2_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL6_MUX3_SEL_Pos (24UL) /*!< CPUSS CM0_INT_CTL6: MUX3_SEL (Bit 24) */ +#define CPUSS_CM0_INT_CTL6_MUX3_SEL_Msk (0xff000000UL) /*!< CPUSS CM0_INT_CTL6: MUX3_SEL (Bitfield-Mask: 0xff) */ +/* ================================================== CPUSS.CM0_INT_CTL7 =================================================== */ +#define CPUSS_CM0_INT_CTL7_MUX0_SEL_Pos (0UL) /*!< CPUSS CM0_INT_CTL7: MUX0_SEL (Bit 0) */ +#define CPUSS_CM0_INT_CTL7_MUX0_SEL_Msk (0xffUL) /*!< CPUSS CM0_INT_CTL7: MUX0_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL7_MUX1_SEL_Pos (8UL) /*!< CPUSS CM0_INT_CTL7: MUX1_SEL (Bit 8) */ +#define CPUSS_CM0_INT_CTL7_MUX1_SEL_Msk (0xff00UL) /*!< CPUSS CM0_INT_CTL7: MUX1_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL7_MUX2_SEL_Pos (16UL) /*!< CPUSS CM0_INT_CTL7: MUX2_SEL (Bit 16) */ +#define CPUSS_CM0_INT_CTL7_MUX2_SEL_Msk (0xff0000UL) /*!< CPUSS CM0_INT_CTL7: MUX2_SEL (Bitfield-Mask: 0xff) */ +#define CPUSS_CM0_INT_CTL7_MUX3_SEL_Pos (24UL) /*!< CPUSS CM0_INT_CTL7: MUX3_SEL (Bit 24) */ +#define CPUSS_CM0_INT_CTL7_MUX3_SEL_Msk (0xff000000UL) /*!< CPUSS CM0_INT_CTL7: MUX3_SEL (Bitfield-Mask: 0xff) */ +/* =================================================== CPUSS.CM4_PWR_CTL =================================================== */ +#define CPUSS_CM4_PWR_CTL_ISOLATE_Pos (0UL) /*!< CPUSS CM4_PWR_CTL: ISOLATE (Bit 0) */ +#define CPUSS_CM4_PWR_CTL_ISOLATE_Msk (0x1UL) /*!< CPUSS CM4_PWR_CTL: ISOLATE (Bitfield-Mask: 0x01) */ +#define CPUSS_CM4_PWR_CTL_RETAIN_Pos (1UL) /*!< CPUSS CM4_PWR_CTL: RETAIN (Bit 1) */ +#define CPUSS_CM4_PWR_CTL_RETAIN_Msk (0x2UL) /*!< CPUSS CM4_PWR_CTL: RETAIN (Bitfield-Mask: 0x01) */ +#define CPUSS_CM4_PWR_CTL_POWER_Pos (2UL) /*!< CPUSS CM4_PWR_CTL: POWER (Bit 2) */ +#define CPUSS_CM4_PWR_CTL_POWER_Msk (0x4UL) /*!< CPUSS CM4_PWR_CTL: POWER (Bitfield-Mask: 0x01) */ +#define CPUSS_CM4_PWR_CTL_RESET_Pos (3UL) /*!< CPUSS CM4_PWR_CTL: RESET (Bit 3) */ +#define CPUSS_CM4_PWR_CTL_RESET_Msk (0x8UL) /*!< CPUSS CM4_PWR_CTL: RESET (Bitfield-Mask: 0x01) */ +#define CPUSS_CM4_PWR_CTL_CLOCK_Pos (4UL) /*!< CPUSS CM4_PWR_CTL: CLOCK (Bit 4) */ +#define CPUSS_CM4_PWR_CTL_CLOCK_Msk (0x10UL) /*!< CPUSS CM4_PWR_CTL: CLOCK (Bitfield-Mask: 0x01) */ +/* =================================================== CPUSS.CM4_STATUS ==================================================== */ +#define CPUSS_CM4_STATUS_SLEEPING_Pos (0UL) /*!< CPUSS CM4_STATUS: SLEEPING (Bit 0) */ +#define CPUSS_CM4_STATUS_SLEEPING_Msk (0x1UL) /*!< CPUSS CM4_STATUS: SLEEPING (Bitfield-Mask: 0x01) */ +#define CPUSS_CM4_STATUS_SLEEPDEEP_Pos (1UL) /*!< CPUSS CM4_STATUS: SLEEPDEEP (Bit 1) */ +#define CPUSS_CM4_STATUS_SLEEPDEEP_Msk (0x2UL) /*!< CPUSS CM4_STATUS: SLEEPDEEP (Bitfield-Mask: 0x01) */ +/* ================================================== CPUSS.CM4_CLOCK_CTL ================================================== */ +#define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Pos (8UL) /*!< CPUSS CM4_CLOCK_CTL: FAST_INT_DIV (Bit 8) */ +#define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Msk (0xff00UL) /*!< CPUSS CM4_CLOCK_CTL: FAST_INT_DIV (Bitfield-Mask: 0xff) */ +/* =================================================== CPUSS.CM4_NMI_CTL =================================================== */ +#define CPUSS_CM4_NMI_CTL_MUX0_SEL_Pos (0UL) /*!< CPUSS CM4_NMI_CTL: MUX0_SEL (Bit 0) */ +#define CPUSS_CM4_NMI_CTL_MUX0_SEL_Msk (0xffUL) /*!< CPUSS CM4_NMI_CTL: MUX0_SEL (Bitfield-Mask: 0xff) */ +/* =================================================== CPUSS.UDB_PWR_CTL =================================================== */ +#define CPUSS_UDB_PWR_CTL_ISOLATE_Pos (0UL) /*!< CPUSS UDB_PWR_CTL: ISOLATE (Bit 0) */ +#define CPUSS_UDB_PWR_CTL_ISOLATE_Msk (0x1UL) /*!< CPUSS UDB_PWR_CTL: ISOLATE (Bitfield-Mask: 0x01) */ +#define CPUSS_UDB_PWR_CTL_RETAIN_Pos (1UL) /*!< CPUSS UDB_PWR_CTL: RETAIN (Bit 1) */ +#define CPUSS_UDB_PWR_CTL_RETAIN_Msk (0x2UL) /*!< CPUSS UDB_PWR_CTL: RETAIN (Bitfield-Mask: 0x01) */ +#define CPUSS_UDB_PWR_CTL_POWER_Pos (2UL) /*!< CPUSS UDB_PWR_CTL: POWER (Bit 2) */ +#define CPUSS_UDB_PWR_CTL_POWER_Msk (0x4UL) /*!< CPUSS UDB_PWR_CTL: POWER (Bitfield-Mask: 0x01) */ +#define CPUSS_UDB_PWR_CTL_RESET_Pos (3UL) /*!< CPUSS UDB_PWR_CTL: RESET (Bit 3) */ +#define CPUSS_UDB_PWR_CTL_RESET_Msk (0x8UL) /*!< CPUSS UDB_PWR_CTL: RESET (Bitfield-Mask: 0x01) */ +#define CPUSS_UDB_PWR_CTL_CLOCK_Pos (4UL) /*!< CPUSS UDB_PWR_CTL: CLOCK (Bit 4) */ +#define CPUSS_UDB_PWR_CTL_CLOCK_Msk (0x10UL) /*!< CPUSS UDB_PWR_CTL: CLOCK (Bitfield-Mask: 0x01) */ +/* ==================================================== CPUSS.RAM0_CTL0 ==================================================== */ +#define CPUSS_RAM0_CTL0_SLOW_WS_Pos (0UL) /*!< CPUSS RAM0_CTL0: SLOW_WS (Bit 0) */ +#define CPUSS_RAM0_CTL0_SLOW_WS_Msk (0x3UL) /*!< CPUSS RAM0_CTL0: SLOW_WS (Bitfield-Mask: 0x03) */ +#define CPUSS_RAM0_CTL0_FAST_WS_Pos (8UL) /*!< CPUSS RAM0_CTL0: FAST_WS (Bit 8) */ +#define CPUSS_RAM0_CTL0_FAST_WS_Msk (0x300UL) /*!< CPUSS RAM0_CTL0: FAST_WS (Bitfield-Mask: 0x03) */ +/* =============================================== CPUSS.RAM0_PWR_MACRO_CTL ================================================ */ +#define CPUSS_RAM0_PWR_MACRO_CTL_ISOLATE_Pos (0UL) /*!< CPUSS RAM0_PWR_MACRO_CTL: ISOLATE (Bit 0) */ +#define CPUSS_RAM0_PWR_MACRO_CTL_ISOLATE_Msk (0x1UL) /*!< CPUSS RAM0_PWR_MACRO_CTL: ISOLATE (Bitfield-Mask: 0x01) */ +#define CPUSS_RAM0_PWR_MACRO_CTL_RETAIN_Pos (1UL) /*!< CPUSS RAM0_PWR_MACRO_CTL: RETAIN (Bit 1) */ +#define CPUSS_RAM0_PWR_MACRO_CTL_RETAIN_Msk (0x2UL) /*!< CPUSS RAM0_PWR_MACRO_CTL: RETAIN (Bitfield-Mask: 0x01) */ +#define CPUSS_RAM0_PWR_MACRO_CTL_POWER_Pos (2UL) /*!< CPUSS RAM0_PWR_MACRO_CTL: POWER (Bit 2) */ +#define CPUSS_RAM0_PWR_MACRO_CTL_POWER_Msk (0x4UL) /*!< CPUSS RAM0_PWR_MACRO_CTL: POWER (Bitfield-Mask: 0x01) */ +/* ==================================================== CPUSS.RAM1_CTL0 ==================================================== */ +#define CPUSS_RAM1_CTL0_SLOW_WS_Pos (0UL) /*!< CPUSS RAM1_CTL0: SLOW_WS (Bit 0) */ +#define CPUSS_RAM1_CTL0_SLOW_WS_Msk (0x3UL) /*!< CPUSS RAM1_CTL0: SLOW_WS (Bitfield-Mask: 0x03) */ +#define CPUSS_RAM1_CTL0_FAST_WS_Pos (8UL) /*!< CPUSS RAM1_CTL0: FAST_WS (Bit 8) */ +#define CPUSS_RAM1_CTL0_FAST_WS_Msk (0x300UL) /*!< CPUSS RAM1_CTL0: FAST_WS (Bitfield-Mask: 0x03) */ +/* ================================================== CPUSS.RAM1_PWR_CTL =================================================== */ +#define CPUSS_RAM1_PWR_CTL_ISOLATE_Pos (0UL) /*!< CPUSS RAM1_PWR_CTL: ISOLATE (Bit 0) */ +#define CPUSS_RAM1_PWR_CTL_ISOLATE_Msk (0x1UL) /*!< CPUSS RAM1_PWR_CTL: ISOLATE (Bitfield-Mask: 0x01) */ +#define CPUSS_RAM1_PWR_CTL_RETAIN_Pos (1UL) /*!< CPUSS RAM1_PWR_CTL: RETAIN (Bit 1) */ +#define CPUSS_RAM1_PWR_CTL_RETAIN_Msk (0x2UL) /*!< CPUSS RAM1_PWR_CTL: RETAIN (Bitfield-Mask: 0x01) */ +#define CPUSS_RAM1_PWR_CTL_POWER_Pos (2UL) /*!< CPUSS RAM1_PWR_CTL: POWER (Bit 2) */ +#define CPUSS_RAM1_PWR_CTL_POWER_Msk (0x4UL) /*!< CPUSS RAM1_PWR_CTL: POWER (Bitfield-Mask: 0x01) */ +/* ==================================================== CPUSS.RAM2_CTL0 ==================================================== */ +#define CPUSS_RAM2_CTL0_SLOW_WS_Pos (0UL) /*!< CPUSS RAM2_CTL0: SLOW_WS (Bit 0) */ +#define CPUSS_RAM2_CTL0_SLOW_WS_Msk (0x3UL) /*!< CPUSS RAM2_CTL0: SLOW_WS (Bitfield-Mask: 0x03) */ +#define CPUSS_RAM2_CTL0_FAST_WS_Pos (8UL) /*!< CPUSS RAM2_CTL0: FAST_WS (Bit 8) */ +#define CPUSS_RAM2_CTL0_FAST_WS_Msk (0x300UL) /*!< CPUSS RAM2_CTL0: FAST_WS (Bitfield-Mask: 0x03) */ +/* ================================================== CPUSS.RAM2_PWR_CTL =================================================== */ +#define CPUSS_RAM2_PWR_CTL_ISOLATE_Pos (0UL) /*!< CPUSS RAM2_PWR_CTL: ISOLATE (Bit 0) */ +#define CPUSS_RAM2_PWR_CTL_ISOLATE_Msk (0x1UL) /*!< CPUSS RAM2_PWR_CTL: ISOLATE (Bitfield-Mask: 0x01) */ +#define CPUSS_RAM2_PWR_CTL_RETAIN_Pos (1UL) /*!< CPUSS RAM2_PWR_CTL: RETAIN (Bit 1) */ +#define CPUSS_RAM2_PWR_CTL_RETAIN_Msk (0x2UL) /*!< CPUSS RAM2_PWR_CTL: RETAIN (Bitfield-Mask: 0x01) */ +#define CPUSS_RAM2_PWR_CTL_POWER_Pos (2UL) /*!< CPUSS RAM2_PWR_CTL: POWER (Bit 2) */ +#define CPUSS_RAM2_PWR_CTL_POWER_Msk (0x4UL) /*!< CPUSS RAM2_PWR_CTL: POWER (Bitfield-Mask: 0x01) */ +/* ===================================================== CPUSS.ROM_CTL ===================================================== */ +#define CPUSS_ROM_CTL_SLOW_WS_Pos (0UL) /*!< CPUSS ROM_CTL: SLOW_WS (Bit 0) */ +#define CPUSS_ROM_CTL_SLOW_WS_Msk (0x3UL) /*!< CPUSS ROM_CTL: SLOW_WS (Bitfield-Mask: 0x03) */ +#define CPUSS_ROM_CTL_FAST_WS_Pos (8UL) /*!< CPUSS ROM_CTL: FAST_WS (Bit 8) */ +#define CPUSS_ROM_CTL_FAST_WS_Msk (0x300UL) /*!< CPUSS ROM_CTL: FAST_WS (Bitfield-Mask: 0x03) */ +/* =================================================== CPUSS.ETB_PWR_CTL =================================================== */ +#define CPUSS_ETB_PWR_CTL_ISOLATE_Pos (0UL) /*!< CPUSS ETB_PWR_CTL: ISOLATE (Bit 0) */ +#define CPUSS_ETB_PWR_CTL_ISOLATE_Msk (0x1UL) /*!< CPUSS ETB_PWR_CTL: ISOLATE (Bitfield-Mask: 0x01) */ +#define CPUSS_ETB_PWR_CTL_RETAIN_Pos (1UL) /*!< CPUSS ETB_PWR_CTL: RETAIN (Bit 1) */ +#define CPUSS_ETB_PWR_CTL_RETAIN_Msk (0x2UL) /*!< CPUSS ETB_PWR_CTL: RETAIN (Bitfield-Mask: 0x01) */ +#define CPUSS_ETB_PWR_CTL_POWER_Pos (2UL) /*!< CPUSS ETB_PWR_CTL: POWER (Bit 2) */ +#define CPUSS_ETB_PWR_CTL_POWER_Msk (0x4UL) /*!< CPUSS ETB_PWR_CTL: POWER (Bitfield-Mask: 0x01) */ +/* ==================================================== CPUSS.DP_STATUS ==================================================== */ +#define CPUSS_DP_STATUS_SWJ_CONNECTED_Pos (0UL) /*!< CPUSS DP_STATUS: SWJ_CONNECTED (Bit 0) */ +#define CPUSS_DP_STATUS_SWJ_CONNECTED_Msk (0x1UL) /*!< CPUSS DP_STATUS: SWJ_CONNECTED (Bitfield-Mask: 0x01) */ +#define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Pos (1UL) /*!< CPUSS DP_STATUS: SWJ_DEBUG_EN (Bit 1) */ +#define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Msk (0x2UL) /*!< CPUSS DP_STATUS: SWJ_DEBUG_EN (Bitfield-Mask: 0x01) */ +#define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Pos (2UL) /*!< CPUSS DP_STATUS: SWJ_JTAG_SEL (Bit 2) */ +#define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Msk (0x4UL) /*!< CPUSS DP_STATUS: SWJ_JTAG_SEL (Bitfield-Mask: 0x01) */ +/* ==================================================== CPUSS.BUFF_CTL ===================================================== */ +#define CPUSS_BUFF_CTL_WRITE_BUFF_Pos (0UL) /*!< CPUSS BUFF_CTL: WRITE_BUFF (Bit 0) */ +#define CPUSS_BUFF_CTL_WRITE_BUFF_Msk (0x1UL) /*!< CPUSS BUFF_CTL: WRITE_BUFF (Bitfield-Mask: 0x01) */ +/* =================================================== CPUSS.SYSTICK_CTL =================================================== */ +#define CPUSS_SYSTICK_CTL_TENMS_Pos (0UL) /*!< CPUSS SYSTICK_CTL: TENMS (Bit 0) */ +#define CPUSS_SYSTICK_CTL_TENMS_Msk (0xffffffUL) /*!< CPUSS SYSTICK_CTL: TENMS (Bitfield-Mask: 0xffffff) */ +#define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos (24UL) /*!< CPUSS SYSTICK_CTL: CLOCK_SOURCE (Bit 24) */ +#define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Msk (0x3000000UL) /*!< CPUSS SYSTICK_CTL: CLOCK_SOURCE (Bitfield-Mask: 0x03) */ +#define CPUSS_SYSTICK_CTL_SKEW_Pos (30UL) /*!< CPUSS SYSTICK_CTL: SKEW (Bit 30) */ +#define CPUSS_SYSTICK_CTL_SKEW_Msk (0x40000000UL) /*!< CPUSS SYSTICK_CTL: SKEW (Bitfield-Mask: 0x01) */ +#define CPUSS_SYSTICK_CTL_NOREF_Pos (31UL) /*!< CPUSS SYSTICK_CTL: NOREF (Bit 31) */ +#define CPUSS_SYSTICK_CTL_NOREF_Msk (0x80000000UL) /*!< CPUSS SYSTICK_CTL: NOREF (Bitfield-Mask: 0x01) */ +/* =================================================== CPUSS.MBIST_STAT ==================================================== */ +#define CPUSS_MBIST_STAT_SFP_READY_Pos (0UL) /*!< CPUSS MBIST_STAT: SFP_READY (Bit 0) */ +#define CPUSS_MBIST_STAT_SFP_READY_Msk (0x1UL) /*!< CPUSS MBIST_STAT: SFP_READY (Bitfield-Mask: 0x01) */ +#define CPUSS_MBIST_STAT_SFP_FAIL_Pos (1UL) /*!< CPUSS MBIST_STAT: SFP_FAIL (Bit 1) */ +#define CPUSS_MBIST_STAT_SFP_FAIL_Msk (0x2UL) /*!< CPUSS MBIST_STAT: SFP_FAIL (Bitfield-Mask: 0x01) */ +/* ==================================================== CPUSS.WOUNDING ===================================================== */ +#define CPUSS_WOUNDING_RAM0_WOUND_Pos (0UL) /*!< CPUSS WOUNDING: RAM0_WOUND (Bit 0) */ +#define CPUSS_WOUNDING_RAM0_WOUND_Msk (0x7UL) /*!< CPUSS WOUNDING: RAM0_WOUND (Bitfield-Mask: 0x07) */ +#define CPUSS_WOUNDING_RAM1_WOUND_Pos (4UL) /*!< CPUSS WOUNDING: RAM1_WOUND (Bit 4) */ +#define CPUSS_WOUNDING_RAM1_WOUND_Msk (0x70UL) /*!< CPUSS WOUNDING: RAM1_WOUND (Bitfield-Mask: 0x07) */ +#define CPUSS_WOUNDING_RAM2_WOUND_Pos (8UL) /*!< CPUSS WOUNDING: RAM2_WOUND (Bit 8) */ +#define CPUSS_WOUNDING_RAM2_WOUND_Msk (0x700UL) /*!< CPUSS WOUNDING: RAM2_WOUND (Bitfield-Mask: 0x07) */ +#define CPUSS_WOUNDING_FLASH_WOUND_Pos (12UL) /*!< CPUSS WOUNDING: FLASH_WOUND (Bit 12) */ +#define CPUSS_WOUNDING_FLASH_WOUND_Msk (0x7000UL) /*!< CPUSS WOUNDING: FLASH_WOUND (Bitfield-Mask: 0x07) */ +/* =================================================== CPUSS.PROTECTION ==================================================== */ +#define CPUSS_PROTECTION_STATE_Pos (0UL) /*!< CPUSS PROTECTION: STATE (Bit 0) */ +#define CPUSS_PROTECTION_STATE_Msk (0x7UL) /*!< CPUSS PROTECTION: STATE (Bitfield-Mask: 0x07) */ +/* ================================================= CPUSS.CM0_PC0_HANDLER ================================================= */ +#define CPUSS_CM0_PC0_HANDLER_ADDR_Pos (0UL) /*!< CPUSS CM0_PC0_HANDLER: ADDR (Bit 0) */ +#define CPUSS_CM0_PC0_HANDLER_ADDR_Msk (0xffffffffUL) /*!< CPUSS CM0_PC0_HANDLER: ADDR (Bitfield-Mask: 0xffffffff) */ +/* ============================================== CPUSS.CM0_VECTOR_TABLE_BASE ============================================== */ +#define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Pos (8UL) /*!< CPUSS CM0_VECTOR_TABLE_BASE: ADDR24 (Bit 8) */ +#define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Msk (0xffffff00UL) /*!< CPUSS CM0_VECTOR_TABLE_BASE: ADDR24 (Bitfield-Mask: 0xffffff)*/ +/* ============================================== CPUSS.CM4_VECTOR_TABLE_BASE ============================================== */ +#define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Pos (10UL) /*!< CPUSS CM4_VECTOR_TABLE_BASE: ADDR22 (Bit 10) */ +#define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Msk (0xfffffc00UL) /*!< CPUSS CM4_VECTOR_TABLE_BASE: ADDR22 (Bitfield-Mask: 0x3fffff)*/ +/* ==================================================== CPUSS.IDENTITY ===================================================== */ +#define CPUSS_IDENTITY_P_Pos (0UL) /*!< CPUSS IDENTITY: P (Bit 0) */ +#define CPUSS_IDENTITY_P_Msk (0x1UL) /*!< CPUSS IDENTITY: P (Bitfield-Mask: 0x01) */ +#define CPUSS_IDENTITY_NS_Pos (1UL) /*!< CPUSS IDENTITY: NS (Bit 1) */ +#define CPUSS_IDENTITY_NS_Msk (0x2UL) /*!< CPUSS IDENTITY: NS (Bitfield-Mask: 0x01) */ +#define CPUSS_IDENTITY_PC_Pos (4UL) /*!< CPUSS IDENTITY: PC (Bit 4) */ +#define CPUSS_IDENTITY_PC_Msk (0xf0UL) /*!< CPUSS IDENTITY: PC (Bitfield-Mask: 0x0f) */ +#define CPUSS_IDENTITY_MS_Pos (8UL) /*!< CPUSS IDENTITY: MS (Bit 8) */ +#define CPUSS_IDENTITY_MS_Msk (0xf00UL) /*!< CPUSS IDENTITY: MS (Bitfield-Mask: 0x0f) */ +/* ================================================== CPUSS.TRIM_ROM_CTL =================================================== */ +#define CPUSS_TRIM_ROM_CTL_RM_Pos (0UL) /*!< CPUSS TRIM_ROM_CTL: RM (Bit 0) */ +#define CPUSS_TRIM_ROM_CTL_RM_Msk (0xfUL) /*!< CPUSS TRIM_ROM_CTL: RM (Bitfield-Mask: 0x0f) */ +#define CPUSS_TRIM_ROM_CTL_RME_Pos (4UL) /*!< CPUSS TRIM_ROM_CTL: RME (Bit 4) */ +#define CPUSS_TRIM_ROM_CTL_RME_Msk (0x10UL) /*!< CPUSS TRIM_ROM_CTL: RME (Bitfield-Mask: 0x01) */ +/* ================================================== CPUSS.TRIM_RAM_CTL =================================================== */ +#define CPUSS_TRIM_RAM_CTL_RM_Pos (0UL) /*!< CPUSS TRIM_RAM_CTL: RM (Bit 0) */ +#define CPUSS_TRIM_RAM_CTL_RM_Msk (0xfUL) /*!< CPUSS TRIM_RAM_CTL: RM (Bitfield-Mask: 0x0f) */ +#define CPUSS_TRIM_RAM_CTL_RME_Pos (4UL) /*!< CPUSS TRIM_RAM_CTL: RME (Bit 4) */ +#define CPUSS_TRIM_RAM_CTL_RME_Msk (0x10UL) /*!< CPUSS TRIM_RAM_CTL: RME (Bitfield-Mask: 0x01) */ +#define CPUSS_TRIM_RAM_CTL_WPULSE_Pos (5UL) /*!< CPUSS TRIM_RAM_CTL: WPULSE (Bit 5) */ +#define CPUSS_TRIM_RAM_CTL_WPULSE_Msk (0xe0UL) /*!< CPUSS TRIM_RAM_CTL: WPULSE (Bitfield-Mask: 0x07) */ +#define CPUSS_TRIM_RAM_CTL_RA_Pos (8UL) /*!< CPUSS TRIM_RAM_CTL: RA (Bit 8) */ +#define CPUSS_TRIM_RAM_CTL_RA_Msk (0x300UL) /*!< CPUSS TRIM_RAM_CTL: RA (Bitfield-Mask: 0x03) */ +#define CPUSS_TRIM_RAM_CTL_WA_Pos (12UL) /*!< CPUSS TRIM_RAM_CTL: WA (Bit 12) */ +#define CPUSS_TRIM_RAM_CTL_WA_Msk (0x7000UL) /*!< CPUSS TRIM_RAM_CTL: WA (Bitfield-Mask: 0x07) */ + + +#endif /* _CYIP_CPUSS_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_crypto.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_crypto.h new file mode 100644 index 0000000000..d32888bb00 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_crypto.h @@ -0,0 +1,375 @@ +/***************************************************************************//** +* \file cyip_crypto.h +* +* \brief +* CRYPTO IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_CRYPTO_H_ +#define _CYIP_CRYPTO_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ CRYPTO ================ */ +/* =========================================================================================================================== */ + +#define CRYPTO_SECTION_SIZE 0x00010000UL + +/** + * \brief Cryptography component (CRYPTO) + */ +typedef struct { /*!< CRYPTO Structure */ + __IOM uint32_t CTL; /*!< 0x00000000 Control */ + __IM uint32_t STATUS; /*!< 0x00000004 Status */ + __IM uint32_t RESERVED[6]; + __IM uint32_t ERROR_STATUS0; /*!< 0x00000020 Error status 0 */ + __IOM uint32_t ERROR_STATUS1; /*!< 0x00000024 Error status 1 */ + __IM uint32_t RESERVED1[6]; + __IOM uint32_t INSTR_FF_CTL; /*!< 0x00000040 Instruction FIFO control */ + __IM uint32_t INSTR_FF_STATUS; /*!< 0x00000044 Instruction FIFO status */ + __OM uint32_t INSTR_FF_WR; /*!< 0x00000048 Instruction FIFO write */ + __IM uint32_t RESERVED2[13]; + __IM uint32_t RF_DATA[16]; /*!< 0x00000080 Register-file */ + __IM uint32_t RESERVED3[16]; + __IOM uint32_t AES_CTL; /*!< 0x00000100 AES control */ + __IM uint32_t RESERVED4[31]; + __IM uint32_t STR_RESULT; /*!< 0x00000180 String result */ + __IM uint32_t RESERVED5[31]; + __IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */ + __IOM uint32_t PR_LFSR_CTL1; /*!< 0x00000204 Pseudo random LFSR control 1 */ + __IOM uint32_t PR_LFSR_CTL2; /*!< 0x00000208 Pseudo random LFSR control 2 */ + __IM uint32_t RESERVED6; + __IOM uint32_t PR_RESULT; /*!< 0x00000210 Pseudo random result */ + __IM uint32_t RESERVED7[27]; + __IOM uint32_t TR_CTL0; /*!< 0x00000280 True random control 0 */ + __IOM uint32_t TR_CTL1; /*!< 0x00000284 True random control 1 */ + __IOM uint32_t TR_RESULT; /*!< 0x00000288 True random result */ + __IM uint32_t RESERVED8[5]; + __IOM uint32_t TR_GARO_CTL; /*!< 0x000002A0 True random GARO control */ + __IOM uint32_t TR_FIRO_CTL; /*!< 0x000002A4 True random FIRO control */ + __IM uint32_t RESERVED9[6]; + __IOM uint32_t TR_MON_CTL; /*!< 0x000002C0 True random monitor control */ + __IM uint32_t RESERVED10; + __IOM uint32_t TR_MON_CMD; /*!< 0x000002C8 True random monitor command */ + __IM uint32_t RESERVED11; + __IOM uint32_t TR_MON_RC_CTL; /*!< 0x000002D0 True random monitor RC control */ + __IM uint32_t RESERVED12; + __IM uint32_t TR_MON_RC_STATUS0; /*!< 0x000002D8 True random monitor RC status 0 */ + __IM uint32_t TR_MON_RC_STATUS1; /*!< 0x000002DC True random monitor RC status 1 */ + __IOM uint32_t TR_MON_AP_CTL; /*!< 0x000002E0 True random monitor AP control */ + __IM uint32_t RESERVED13; + __IM uint32_t TR_MON_AP_STATUS0; /*!< 0x000002E8 True random monitor AP status 0 */ + __IM uint32_t TR_MON_AP_STATUS1; /*!< 0x000002EC True random monitor AP status 1 */ + __IM uint32_t RESERVED14[4]; + __IOM uint32_t SHA_CTL; /*!< 0x00000300 SHA control */ + __IM uint32_t RESERVED15[63]; + __IOM uint32_t CRC_CTL; /*!< 0x00000400 CRC control */ + __IM uint32_t RESERVED16[3]; + __IOM uint32_t CRC_DATA_CTL; /*!< 0x00000410 CRC data control */ + __IM uint32_t RESERVED17[3]; + __IOM uint32_t CRC_POL_CTL; /*!< 0x00000420 CRC polynomial control */ + __IM uint32_t RESERVED18[3]; + __IOM uint32_t CRC_LFSR_CTL; /*!< 0x00000430 CRC LFSR control */ + __IM uint32_t RESERVED19[3]; + __IOM uint32_t CRC_REM_CTL; /*!< 0x00000440 CRC remainder control */ + __IM uint32_t RESERVED20; + __IM uint32_t CRC_REM_RESULT; /*!< 0x00000448 CRC remainder result */ + __IM uint32_t RESERVED21[13]; + __IOM uint32_t VU_CTL0; /*!< 0x00000480 Vector unit control 0 */ + __IOM uint32_t VU_CTL1; /*!< 0x00000484 Vector unit control 1 */ + __IM uint32_t RESERVED22[2]; + __IM uint32_t VU_STATUS; /*!< 0x00000490 Vector unit status */ + __IM uint32_t RESERVED23[203]; + __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */ + __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */ + __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */ + __IM uint32_t RESERVED24[3596]; + __IOM uint32_t MEM_BUFF[4096]; /*!< 0x00004000 Memory buffer */ +} CRYPTO_Type; /*!< Size = 32768 (0x8000) */ + + +/* ====================================================== CRYPTO.CTL ======================================================= */ +#define CRYPTO_CTL_ISOLATE_Pos (0UL) /*!< CRYPTO CTL: ISOLATE (Bit 0) */ +#define CRYPTO_CTL_ISOLATE_Msk (0x1UL) /*!< CRYPTO CTL: ISOLATE (Bitfield-Mask: 0x01) */ +#define CRYPTO_CTL_RETAIN_Pos (1UL) /*!< CRYPTO CTL: RETAIN (Bit 1) */ +#define CRYPTO_CTL_RETAIN_Msk (0x2UL) /*!< CRYPTO CTL: RETAIN (Bitfield-Mask: 0x01) */ +#define CRYPTO_CTL_POWER_Pos (2UL) /*!< CRYPTO CTL: POWER (Bit 2) */ +#define CRYPTO_CTL_POWER_Msk (0x4UL) /*!< CRYPTO CTL: POWER (Bitfield-Mask: 0x01) */ +#define CRYPTO_CTL_ENABLED_Pos (31UL) /*!< CRYPTO CTL: ENABLED (Bit 31) */ +#define CRYPTO_CTL_ENABLED_Msk (0x80000000UL) /*!< CRYPTO CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ===================================================== CRYPTO.STATUS ===================================================== */ +#define CRYPTO_STATUS_AES_BUSY_Pos (0UL) /*!< CRYPTO STATUS: AES_BUSY (Bit 0) */ +#define CRYPTO_STATUS_AES_BUSY_Msk (0x1UL) /*!< CRYPTO STATUS: AES_BUSY (Bitfield-Mask: 0x01) */ +#define CRYPTO_STATUS_DES_BUSY_Pos (1UL) /*!< CRYPTO STATUS: DES_BUSY (Bit 1) */ +#define CRYPTO_STATUS_DES_BUSY_Msk (0x2UL) /*!< CRYPTO STATUS: DES_BUSY (Bitfield-Mask: 0x01) */ +#define CRYPTO_STATUS_SHA_BUSY_Pos (2UL) /*!< CRYPTO STATUS: SHA_BUSY (Bit 2) */ +#define CRYPTO_STATUS_SHA_BUSY_Msk (0x4UL) /*!< CRYPTO STATUS: SHA_BUSY (Bitfield-Mask: 0x01) */ +#define CRYPTO_STATUS_CRC_BUSY_Pos (3UL) /*!< CRYPTO STATUS: CRC_BUSY (Bit 3) */ +#define CRYPTO_STATUS_CRC_BUSY_Msk (0x8UL) /*!< CRYPTO STATUS: CRC_BUSY (Bitfield-Mask: 0x01) */ +#define CRYPTO_STATUS_STR_BUSY_Pos (4UL) /*!< CRYPTO STATUS: STR_BUSY (Bit 4) */ +#define CRYPTO_STATUS_STR_BUSY_Msk (0x10UL) /*!< CRYPTO STATUS: STR_BUSY (Bitfield-Mask: 0x01) */ +#define CRYPTO_STATUS_PR_BUSY_Pos (5UL) /*!< CRYPTO STATUS: PR_BUSY (Bit 5) */ +#define CRYPTO_STATUS_PR_BUSY_Msk (0x20UL) /*!< CRYPTO STATUS: PR_BUSY (Bitfield-Mask: 0x01) */ +#define CRYPTO_STATUS_TR_BUSY_Pos (6UL) /*!< CRYPTO STATUS: TR_BUSY (Bit 6) */ +#define CRYPTO_STATUS_TR_BUSY_Msk (0x40UL) /*!< CRYPTO STATUS: TR_BUSY (Bitfield-Mask: 0x01) */ +#define CRYPTO_STATUS_VU_BUSY_Pos (7UL) /*!< CRYPTO STATUS: VU_BUSY (Bit 7) */ +#define CRYPTO_STATUS_VU_BUSY_Msk (0x80UL) /*!< CRYPTO STATUS: VU_BUSY (Bitfield-Mask: 0x01) */ +#define CRYPTO_STATUS_CMD_FF_BUSY_Pos (31UL) /*!< CRYPTO STATUS: CMD_FF_BUSY (Bit 31) */ +#define CRYPTO_STATUS_CMD_FF_BUSY_Msk (0x80000000UL) /*!< CRYPTO STATUS: CMD_FF_BUSY (Bitfield-Mask: 0x01) */ +/* ================================================= CRYPTO.ERROR_STATUS0 ================================================== */ +#define CRYPTO_ERROR_STATUS0_DATA32_Pos (0UL) /*!< CRYPTO ERROR_STATUS0: DATA32 (Bit 0) */ +#define CRYPTO_ERROR_STATUS0_DATA32_Msk (0xffffffffUL) /*!< CRYPTO ERROR_STATUS0: DATA32 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CRYPTO.ERROR_STATUS1 ================================================== */ +#define CRYPTO_ERROR_STATUS1_DATA23_Pos (0UL) /*!< CRYPTO ERROR_STATUS1: DATA23 (Bit 0) */ +#define CRYPTO_ERROR_STATUS1_DATA23_Msk (0xffffffUL) /*!< CRYPTO ERROR_STATUS1: DATA23 (Bitfield-Mask: 0xffffff) */ +#define CRYPTO_ERROR_STATUS1_IDX_Pos (24UL) /*!< CRYPTO ERROR_STATUS1: IDX (Bit 24) */ +#define CRYPTO_ERROR_STATUS1_IDX_Msk (0x7000000UL) /*!< CRYPTO ERROR_STATUS1: IDX (Bitfield-Mask: 0x07) */ +#define CRYPTO_ERROR_STATUS1_VALID_Pos (31UL) /*!< CRYPTO ERROR_STATUS1: VALID (Bit 31) */ +#define CRYPTO_ERROR_STATUS1_VALID_Msk (0x80000000UL) /*!< CRYPTO ERROR_STATUS1: VALID (Bitfield-Mask: 0x01) */ +/* ================================================== CRYPTO.INSTR_FF_CTL ================================================== */ +#define CRYPTO_INSTR_FF_CTL_EVENT_LEVEL_Pos (0UL) /*!< CRYPTO INSTR_FF_CTL: EVENT_LEVEL (Bit 0) */ +#define CRYPTO_INSTR_FF_CTL_EVENT_LEVEL_Msk (0x7UL) /*!< CRYPTO INSTR_FF_CTL: EVENT_LEVEL (Bitfield-Mask: 0x07) */ +#define CRYPTO_INSTR_FF_CTL_CLEAR_Pos (16UL) /*!< CRYPTO INSTR_FF_CTL: CLEAR (Bit 16) */ +#define CRYPTO_INSTR_FF_CTL_CLEAR_Msk (0x10000UL) /*!< CRYPTO INSTR_FF_CTL: CLEAR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INSTR_FF_CTL_BLOCK_Pos (17UL) /*!< CRYPTO INSTR_FF_CTL: BLOCK (Bit 17) */ +#define CRYPTO_INSTR_FF_CTL_BLOCK_Msk (0x20000UL) /*!< CRYPTO INSTR_FF_CTL: BLOCK (Bitfield-Mask: 0x01) */ +/* ================================================ CRYPTO.INSTR_FF_STATUS ================================================= */ +#define CRYPTO_INSTR_FF_STATUS_USED_Pos (0UL) /*!< CRYPTO INSTR_FF_STATUS: USED (Bit 0) */ +#define CRYPTO_INSTR_FF_STATUS_USED_Msk (0xfUL) /*!< CRYPTO INSTR_FF_STATUS: USED (Bitfield-Mask: 0x0f) */ +#define CRYPTO_INSTR_FF_STATUS_EVENT_Pos (16UL) /*!< CRYPTO INSTR_FF_STATUS: EVENT (Bit 16) */ +#define CRYPTO_INSTR_FF_STATUS_EVENT_Msk (0x10000UL) /*!< CRYPTO INSTR_FF_STATUS: EVENT (Bitfield-Mask: 0x01) */ +#define CRYPTO_INSTR_FF_STATUS_BUSY_Pos (31UL) /*!< CRYPTO INSTR_FF_STATUS: BUSY (Bit 31) */ +#define CRYPTO_INSTR_FF_STATUS_BUSY_Msk (0x80000000UL) /*!< CRYPTO INSTR_FF_STATUS: BUSY (Bitfield-Mask: 0x01) */ +/* ================================================== CRYPTO.INSTR_FF_WR =================================================== */ +#define CRYPTO_INSTR_FF_WR_DATA32_Pos (0UL) /*!< CRYPTO INSTR_FF_WR: DATA32 (Bit 0) */ +#define CRYPTO_INSTR_FF_WR_DATA32_Msk (0xffffffffUL) /*!< CRYPTO INSTR_FF_WR: DATA32 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CRYPTO.RF_DATA ===================================================== */ +#define CRYPTO_RF_DATA_DATA32_Pos (0UL) /*!< CRYPTO RF_DATA: DATA32 (Bit 0) */ +#define CRYPTO_RF_DATA_DATA32_Msk (0xffffffffUL) /*!< CRYPTO RF_DATA: DATA32 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CRYPTO.AES_CTL ===================================================== */ +#define CRYPTO_AES_CTL_KEY_SIZE_Pos (0UL) /*!< CRYPTO AES_CTL: KEY_SIZE (Bit 0) */ +#define CRYPTO_AES_CTL_KEY_SIZE_Msk (0x3UL) /*!< CRYPTO AES_CTL: KEY_SIZE (Bitfield-Mask: 0x03) */ +/* =================================================== CRYPTO.STR_RESULT =================================================== */ +#define CRYPTO_STR_RESULT_MEMCMP_Pos (0UL) /*!< CRYPTO STR_RESULT: MEMCMP (Bit 0) */ +#define CRYPTO_STR_RESULT_MEMCMP_Msk (0x1UL) /*!< CRYPTO STR_RESULT: MEMCMP (Bitfield-Mask: 0x01) */ +/* ================================================== CRYPTO.PR_LFSR_CTL0 ================================================== */ +#define CRYPTO_PR_LFSR_CTL0_LFSR32_Pos (0UL) /*!< CRYPTO PR_LFSR_CTL0: LFSR32 (Bit 0) */ +#define CRYPTO_PR_LFSR_CTL0_LFSR32_Msk (0xffffffffUL) /*!< CRYPTO PR_LFSR_CTL0: LFSR32 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CRYPTO.PR_LFSR_CTL1 ================================================== */ +#define CRYPTO_PR_LFSR_CTL1_LFSR31_Pos (0UL) /*!< CRYPTO PR_LFSR_CTL1: LFSR31 (Bit 0) */ +#define CRYPTO_PR_LFSR_CTL1_LFSR31_Msk (0x7fffffffUL) /*!< CRYPTO PR_LFSR_CTL1: LFSR31 (Bitfield-Mask: 0x7fffffff) */ +/* ================================================== CRYPTO.PR_LFSR_CTL2 ================================================== */ +#define CRYPTO_PR_LFSR_CTL2_LFSR29_Pos (0UL) /*!< CRYPTO PR_LFSR_CTL2: LFSR29 (Bit 0) */ +#define CRYPTO_PR_LFSR_CTL2_LFSR29_Msk (0x1fffffffUL) /*!< CRYPTO PR_LFSR_CTL2: LFSR29 (Bitfield-Mask: 0x1fffffff) */ +/* =================================================== CRYPTO.PR_RESULT ==================================================== */ +#define CRYPTO_PR_RESULT_DATA32_Pos (0UL) /*!< CRYPTO PR_RESULT: DATA32 (Bit 0) */ +#define CRYPTO_PR_RESULT_DATA32_Msk (0xffffffffUL) /*!< CRYPTO PR_RESULT: DATA32 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CRYPTO.TR_CTL0 ===================================================== */ +#define CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV_Pos (0UL) /*!< CRYPTO TR_CTL0: SAMPLE_CLOCK_DIV (Bit 0) */ +#define CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV_Msk (0xffUL) /*!< CRYPTO TR_CTL0: SAMPLE_CLOCK_DIV (Bitfield-Mask: 0xff) */ +#define CRYPTO_TR_CTL0_RED_CLOCK_DIV_Pos (8UL) /*!< CRYPTO TR_CTL0: RED_CLOCK_DIV (Bit 8) */ +#define CRYPTO_TR_CTL0_RED_CLOCK_DIV_Msk (0xff00UL) /*!< CRYPTO TR_CTL0: RED_CLOCK_DIV (Bitfield-Mask: 0xff) */ +#define CRYPTO_TR_CTL0_INIT_DELAY_Pos (16UL) /*!< CRYPTO TR_CTL0: INIT_DELAY (Bit 16) */ +#define CRYPTO_TR_CTL0_INIT_DELAY_Msk (0xff0000UL) /*!< CRYPTO TR_CTL0: INIT_DELAY (Bitfield-Mask: 0xff) */ +#define CRYPTO_TR_CTL0_VON_NEUMANN_CORR_Pos (24UL) /*!< CRYPTO TR_CTL0: VON_NEUMANN_CORR (Bit 24) */ +#define CRYPTO_TR_CTL0_VON_NEUMANN_CORR_Msk (0x1000000UL) /*!< CRYPTO TR_CTL0: VON_NEUMANN_CORR (Bitfield-Mask: 0x01) */ +#define CRYPTO_TR_CTL0_STOP_ON_AP_DETECT_Pos (28UL) /*!< CRYPTO TR_CTL0: STOP_ON_AP_DETECT (Bit 28) */ +#define CRYPTO_TR_CTL0_STOP_ON_AP_DETECT_Msk (0x10000000UL) /*!< CRYPTO TR_CTL0: STOP_ON_AP_DETECT (Bitfield-Mask: 0x01) */ +#define CRYPTO_TR_CTL0_STOP_ON_RC_DETECT_Pos (29UL) /*!< CRYPTO TR_CTL0: STOP_ON_RC_DETECT (Bit 29) */ +#define CRYPTO_TR_CTL0_STOP_ON_RC_DETECT_Msk (0x20000000UL) /*!< CRYPTO TR_CTL0: STOP_ON_RC_DETECT (Bitfield-Mask: 0x01) */ +/* ==================================================== CRYPTO.TR_CTL1 ===================================================== */ +#define CRYPTO_TR_CTL1_RO11_EN_Pos (0UL) /*!< CRYPTO TR_CTL1: RO11_EN (Bit 0) */ +#define CRYPTO_TR_CTL1_RO11_EN_Msk (0x1UL) /*!< CRYPTO TR_CTL1: RO11_EN (Bitfield-Mask: 0x01) */ +#define CRYPTO_TR_CTL1_RO15_EN_Pos (1UL) /*!< CRYPTO TR_CTL1: RO15_EN (Bit 1) */ +#define CRYPTO_TR_CTL1_RO15_EN_Msk (0x2UL) /*!< CRYPTO TR_CTL1: RO15_EN (Bitfield-Mask: 0x01) */ +#define CRYPTO_TR_CTL1_GARO15_EN_Pos (2UL) /*!< CRYPTO TR_CTL1: GARO15_EN (Bit 2) */ +#define CRYPTO_TR_CTL1_GARO15_EN_Msk (0x4UL) /*!< CRYPTO TR_CTL1: GARO15_EN (Bitfield-Mask: 0x01) */ +#define CRYPTO_TR_CTL1_GARO31_EN_Pos (3UL) /*!< CRYPTO TR_CTL1: GARO31_EN (Bit 3) */ +#define CRYPTO_TR_CTL1_GARO31_EN_Msk (0x8UL) /*!< CRYPTO TR_CTL1: GARO31_EN (Bitfield-Mask: 0x01) */ +#define CRYPTO_TR_CTL1_FIRO15_EN_Pos (4UL) /*!< CRYPTO TR_CTL1: FIRO15_EN (Bit 4) */ +#define CRYPTO_TR_CTL1_FIRO15_EN_Msk (0x10UL) /*!< CRYPTO TR_CTL1: FIRO15_EN (Bitfield-Mask: 0x01) */ +#define CRYPTO_TR_CTL1_FIRO31_EN_Pos (5UL) /*!< CRYPTO TR_CTL1: FIRO31_EN (Bit 5) */ +#define CRYPTO_TR_CTL1_FIRO31_EN_Msk (0x20UL) /*!< CRYPTO TR_CTL1: FIRO31_EN (Bitfield-Mask: 0x01) */ +/* =================================================== CRYPTO.TR_RESULT ==================================================== */ +#define CRYPTO_TR_RESULT_DATA32_Pos (0UL) /*!< CRYPTO TR_RESULT: DATA32 (Bit 0) */ +#define CRYPTO_TR_RESULT_DATA32_Msk (0xffffffffUL) /*!< CRYPTO TR_RESULT: DATA32 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CRYPTO.TR_GARO_CTL =================================================== */ +#define CRYPTO_TR_GARO_CTL_POLYNOMIAL31_Pos (0UL) /*!< CRYPTO TR_GARO_CTL: POLYNOMIAL31 (Bit 0) */ +#define CRYPTO_TR_GARO_CTL_POLYNOMIAL31_Msk (0x7fffffffUL) /*!< CRYPTO TR_GARO_CTL: POLYNOMIAL31 (Bitfield-Mask: 0x7fffffff)*/ +/* ================================================== CRYPTO.TR_FIRO_CTL =================================================== */ +#define CRYPTO_TR_FIRO_CTL_POLYNOMIAL31_Pos (0UL) /*!< CRYPTO TR_FIRO_CTL: POLYNOMIAL31 (Bit 0) */ +#define CRYPTO_TR_FIRO_CTL_POLYNOMIAL31_Msk (0x7fffffffUL) /*!< CRYPTO TR_FIRO_CTL: POLYNOMIAL31 (Bitfield-Mask: 0x7fffffff)*/ +/* =================================================== CRYPTO.TR_MON_CTL =================================================== */ +#define CRYPTO_TR_MON_CTL_BITSTREAM_SEL_Pos (0UL) /*!< CRYPTO TR_MON_CTL: BITSTREAM_SEL (Bit 0) */ +#define CRYPTO_TR_MON_CTL_BITSTREAM_SEL_Msk (0x3UL) /*!< CRYPTO TR_MON_CTL: BITSTREAM_SEL (Bitfield-Mask: 0x03) */ +/* =================================================== CRYPTO.TR_MON_CMD =================================================== */ +#define CRYPTO_TR_MON_CMD_START_AP_Pos (0UL) /*!< CRYPTO TR_MON_CMD: START_AP (Bit 0) */ +#define CRYPTO_TR_MON_CMD_START_AP_Msk (0x1UL) /*!< CRYPTO TR_MON_CMD: START_AP (Bitfield-Mask: 0x01) */ +#define CRYPTO_TR_MON_CMD_START_RC_Pos (1UL) /*!< CRYPTO TR_MON_CMD: START_RC (Bit 1) */ +#define CRYPTO_TR_MON_CMD_START_RC_Msk (0x2UL) /*!< CRYPTO TR_MON_CMD: START_RC (Bitfield-Mask: 0x01) */ +/* ================================================= CRYPTO.TR_MON_RC_CTL ================================================== */ +#define CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8_Pos (0UL) /*!< CRYPTO TR_MON_RC_CTL: CUTOFF_COUNT8 (Bit 0) */ +#define CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8_Msk (0xffUL) /*!< CRYPTO TR_MON_RC_CTL: CUTOFF_COUNT8 (Bitfield-Mask: 0xff) */ +/* =============================================== CRYPTO.TR_MON_RC_STATUS0 ================================================ */ +#define CRYPTO_TR_MON_RC_STATUS0_BIT_Pos (0UL) /*!< CRYPTO TR_MON_RC_STATUS0: BIT (Bit 0) */ +#define CRYPTO_TR_MON_RC_STATUS0_BIT_Msk (0x1UL) /*!< CRYPTO TR_MON_RC_STATUS0: BIT (Bitfield-Mask: 0x01) */ +/* =============================================== CRYPTO.TR_MON_RC_STATUS1 ================================================ */ +#define CRYPTO_TR_MON_RC_STATUS1_REP_COUNT_Pos (0UL) /*!< CRYPTO TR_MON_RC_STATUS1: REP_COUNT (Bit 0) */ +#define CRYPTO_TR_MON_RC_STATUS1_REP_COUNT_Msk (0xffUL) /*!< CRYPTO TR_MON_RC_STATUS1: REP_COUNT (Bitfield-Mask: 0xff) */ +/* ================================================= CRYPTO.TR_MON_AP_CTL ================================================== */ +#define CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16_Pos (0UL) /*!< CRYPTO TR_MON_AP_CTL: CUTOFF_COUNT16 (Bit 0) */ +#define CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16_Msk (0xffffUL) /*!< CRYPTO TR_MON_AP_CTL: CUTOFF_COUNT16 (Bitfield-Mask: 0xffff)*/ +#define CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE_Pos (16UL) /*!< CRYPTO TR_MON_AP_CTL: WINDOW_SIZE (Bit 16) */ +#define CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE_Msk (0xffff0000UL) /*!< CRYPTO TR_MON_AP_CTL: WINDOW_SIZE (Bitfield-Mask: 0xffff) */ +/* =============================================== CRYPTO.TR_MON_AP_STATUS0 ================================================ */ +#define CRYPTO_TR_MON_AP_STATUS0_BIT_Pos (0UL) /*!< CRYPTO TR_MON_AP_STATUS0: BIT (Bit 0) */ +#define CRYPTO_TR_MON_AP_STATUS0_BIT_Msk (0x1UL) /*!< CRYPTO TR_MON_AP_STATUS0: BIT (Bitfield-Mask: 0x01) */ +/* =============================================== CRYPTO.TR_MON_AP_STATUS1 ================================================ */ +#define CRYPTO_TR_MON_AP_STATUS1_OCC_COUNT_Pos (0UL) /*!< CRYPTO TR_MON_AP_STATUS1: OCC_COUNT (Bit 0) */ +#define CRYPTO_TR_MON_AP_STATUS1_OCC_COUNT_Msk (0xffffUL) /*!< CRYPTO TR_MON_AP_STATUS1: OCC_COUNT (Bitfield-Mask: 0xffff)*/ +#define CRYPTO_TR_MON_AP_STATUS1_WINDOW_INDEX_Pos (16UL) /*!< CRYPTO TR_MON_AP_STATUS1: WINDOW_INDEX (Bit 16) */ +#define CRYPTO_TR_MON_AP_STATUS1_WINDOW_INDEX_Msk (0xffff0000UL) /*!< CRYPTO TR_MON_AP_STATUS1: WINDOW_INDEX (Bitfield-Mask: 0xffff)*/ +/* ==================================================== CRYPTO.SHA_CTL ===================================================== */ +#define CRYPTO_SHA_CTL_MODE_Pos (0UL) /*!< CRYPTO SHA_CTL: MODE (Bit 0) */ +#define CRYPTO_SHA_CTL_MODE_Msk (0x7UL) /*!< CRYPTO SHA_CTL: MODE (Bitfield-Mask: 0x07) */ +/* ==================================================== CRYPTO.CRC_CTL ===================================================== */ +#define CRYPTO_CRC_CTL_DATA_REVERSE_Pos (0UL) /*!< CRYPTO CRC_CTL: DATA_REVERSE (Bit 0) */ +#define CRYPTO_CRC_CTL_DATA_REVERSE_Msk (0x1UL) /*!< CRYPTO CRC_CTL: DATA_REVERSE (Bitfield-Mask: 0x01) */ +#define CRYPTO_CRC_CTL_REM_REVERSE_Pos (8UL) /*!< CRYPTO CRC_CTL: REM_REVERSE (Bit 8) */ +#define CRYPTO_CRC_CTL_REM_REVERSE_Msk (0x100UL) /*!< CRYPTO CRC_CTL: REM_REVERSE (Bitfield-Mask: 0x01) */ +/* ================================================== CRYPTO.CRC_DATA_CTL ================================================== */ +#define CRYPTO_CRC_DATA_CTL_DATA_XOR_Pos (0UL) /*!< CRYPTO CRC_DATA_CTL: DATA_XOR (Bit 0) */ +#define CRYPTO_CRC_DATA_CTL_DATA_XOR_Msk (0xffUL) /*!< CRYPTO CRC_DATA_CTL: DATA_XOR (Bitfield-Mask: 0xff) */ +/* ================================================== CRYPTO.CRC_POL_CTL =================================================== */ +#define CRYPTO_CRC_POL_CTL_POLYNOMIAL_Pos (0UL) /*!< CRYPTO CRC_POL_CTL: POLYNOMIAL (Bit 0) */ +#define CRYPTO_CRC_POL_CTL_POLYNOMIAL_Msk (0xffffffffUL) /*!< CRYPTO CRC_POL_CTL: POLYNOMIAL (Bitfield-Mask: 0xffffffff)*/ +/* ================================================== CRYPTO.CRC_LFSR_CTL ================================================== */ +#define CRYPTO_CRC_LFSR_CTL_LFSR32_Pos (0UL) /*!< CRYPTO CRC_LFSR_CTL: LFSR32 (Bit 0) */ +#define CRYPTO_CRC_LFSR_CTL_LFSR32_Msk (0xffffffffUL) /*!< CRYPTO CRC_LFSR_CTL: LFSR32 (Bitfield-Mask: 0xffffffff) */ +/* ================================================== CRYPTO.CRC_REM_CTL =================================================== */ +#define CRYPTO_CRC_REM_CTL_REM_XOR_Pos (0UL) /*!< CRYPTO CRC_REM_CTL: REM_XOR (Bit 0) */ +#define CRYPTO_CRC_REM_CTL_REM_XOR_Msk (0xffffffffUL) /*!< CRYPTO CRC_REM_CTL: REM_XOR (Bitfield-Mask: 0xffffffff) */ +/* ================================================= CRYPTO.CRC_REM_RESULT ================================================= */ +#define CRYPTO_CRC_REM_RESULT_REM_Pos (0UL) /*!< CRYPTO CRC_REM_RESULT: REM (Bit 0) */ +#define CRYPTO_CRC_REM_RESULT_REM_Msk (0xffffffffUL) /*!< CRYPTO CRC_REM_RESULT: REM (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CRYPTO.VU_CTL0 ===================================================== */ +#define CRYPTO_VU_CTL0_ALWAYS_EXECUTE_Pos (0UL) /*!< CRYPTO VU_CTL0: ALWAYS_EXECUTE (Bit 0) */ +#define CRYPTO_VU_CTL0_ALWAYS_EXECUTE_Msk (0x1UL) /*!< CRYPTO VU_CTL0: ALWAYS_EXECUTE (Bitfield-Mask: 0x01) */ +/* ==================================================== CRYPTO.VU_CTL1 ===================================================== */ +#define CRYPTO_VU_CTL1_ADDR_Pos (14UL) /*!< CRYPTO VU_CTL1: ADDR (Bit 14) */ +#define CRYPTO_VU_CTL1_ADDR_Msk (0xffffc000UL) /*!< CRYPTO VU_CTL1: ADDR (Bitfield-Mask: 0x3ffff) */ +/* =================================================== CRYPTO.VU_STATUS ==================================================== */ +#define CRYPTO_VU_STATUS_CARRY_Pos (0UL) /*!< CRYPTO VU_STATUS: CARRY (Bit 0) */ +#define CRYPTO_VU_STATUS_CARRY_Msk (0x1UL) /*!< CRYPTO VU_STATUS: CARRY (Bitfield-Mask: 0x01) */ +#define CRYPTO_VU_STATUS_EVEN_Pos (1UL) /*!< CRYPTO VU_STATUS: EVEN (Bit 1) */ +#define CRYPTO_VU_STATUS_EVEN_Msk (0x2UL) /*!< CRYPTO VU_STATUS: EVEN (Bitfield-Mask: 0x01) */ +#define CRYPTO_VU_STATUS_ZERO_Pos (2UL) /*!< CRYPTO VU_STATUS: ZERO (Bit 2) */ +#define CRYPTO_VU_STATUS_ZERO_Msk (0x4UL) /*!< CRYPTO VU_STATUS: ZERO (Bitfield-Mask: 0x01) */ +#define CRYPTO_VU_STATUS_ONE_Pos (3UL) /*!< CRYPTO VU_STATUS: ONE (Bit 3) */ +#define CRYPTO_VU_STATUS_ONE_Msk (0x8UL) /*!< CRYPTO VU_STATUS: ONE (Bitfield-Mask: 0x01) */ +/* ====================================================== CRYPTO.INTR ====================================================== */ +#define CRYPTO_INTR_INSTR_FF_LEVEL_Pos (0UL) /*!< CRYPTO INTR: INSTR_FF_LEVEL (Bit 0) */ +#define CRYPTO_INTR_INSTR_FF_LEVEL_Msk (0x1UL) /*!< CRYPTO INTR: INSTR_FF_LEVEL (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_INSTR_FF_OVERFLOW_Pos (1UL) /*!< CRYPTO INTR: INSTR_FF_OVERFLOW (Bit 1) */ +#define CRYPTO_INTR_INSTR_FF_OVERFLOW_Msk (0x2UL) /*!< CRYPTO INTR: INSTR_FF_OVERFLOW (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_TR_INITIALIZED_Pos (2UL) /*!< CRYPTO INTR: TR_INITIALIZED (Bit 2) */ +#define CRYPTO_INTR_TR_INITIALIZED_Msk (0x4UL) /*!< CRYPTO INTR: TR_INITIALIZED (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_TR_DATA_AVAILABLE_Pos (3UL) /*!< CRYPTO INTR: TR_DATA_AVAILABLE (Bit 3) */ +#define CRYPTO_INTR_TR_DATA_AVAILABLE_Msk (0x8UL) /*!< CRYPTO INTR: TR_DATA_AVAILABLE (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_PR_DATA_AVAILABLE_Pos (4UL) /*!< CRYPTO INTR: PR_DATA_AVAILABLE (Bit 4) */ +#define CRYPTO_INTR_PR_DATA_AVAILABLE_Msk (0x10UL) /*!< CRYPTO INTR: PR_DATA_AVAILABLE (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_INSTR_OPC_ERROR_Pos (16UL) /*!< CRYPTO INTR: INSTR_OPC_ERROR (Bit 16) */ +#define CRYPTO_INTR_INSTR_OPC_ERROR_Msk (0x10000UL) /*!< CRYPTO INTR: INSTR_OPC_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_INSTR_CC_ERROR_Pos (17UL) /*!< CRYPTO INTR: INSTR_CC_ERROR (Bit 17) */ +#define CRYPTO_INTR_INSTR_CC_ERROR_Msk (0x20000UL) /*!< CRYPTO INTR: INSTR_CC_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_BUS_ERROR_Pos (18UL) /*!< CRYPTO INTR: BUS_ERROR (Bit 18) */ +#define CRYPTO_INTR_BUS_ERROR_Msk (0x40000UL) /*!< CRYPTO INTR: BUS_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_TR_AP_DETECT_ERROR_Pos (19UL) /*!< CRYPTO INTR: TR_AP_DETECT_ERROR (Bit 19) */ +#define CRYPTO_INTR_TR_AP_DETECT_ERROR_Msk (0x80000UL) /*!< CRYPTO INTR: TR_AP_DETECT_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_TR_RC_DETECT_ERROR_Pos (20UL) /*!< CRYPTO INTR: TR_RC_DETECT_ERROR (Bit 20) */ +#define CRYPTO_INTR_TR_RC_DETECT_ERROR_Msk (0x100000UL) /*!< CRYPTO INTR: TR_RC_DETECT_ERROR (Bitfield-Mask: 0x01) */ +/* ==================================================== CRYPTO.INTR_SET ==================================================== */ +#define CRYPTO_INTR_SET_INSTR_FF_LEVEL_Pos (0UL) /*!< CRYPTO INTR_SET: INSTR_FF_LEVEL (Bit 0) */ +#define CRYPTO_INTR_SET_INSTR_FF_LEVEL_Msk (0x1UL) /*!< CRYPTO INTR_SET: INSTR_FF_LEVEL (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_SET_INSTR_FF_OVERFLOW_Pos (1UL) /*!< CRYPTO INTR_SET: INSTR_FF_OVERFLOW (Bit 1) */ +#define CRYPTO_INTR_SET_INSTR_FF_OVERFLOW_Msk (0x2UL) /*!< CRYPTO INTR_SET: INSTR_FF_OVERFLOW (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_SET_TR_INITIALIZED_Pos (2UL) /*!< CRYPTO INTR_SET: TR_INITIALIZED (Bit 2) */ +#define CRYPTO_INTR_SET_TR_INITIALIZED_Msk (0x4UL) /*!< CRYPTO INTR_SET: TR_INITIALIZED (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_SET_TR_DATA_AVAILABLE_Pos (3UL) /*!< CRYPTO INTR_SET: TR_DATA_AVAILABLE (Bit 3) */ +#define CRYPTO_INTR_SET_TR_DATA_AVAILABLE_Msk (0x8UL) /*!< CRYPTO INTR_SET: TR_DATA_AVAILABLE (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_SET_PR_DATA_AVAILABLE_Pos (4UL) /*!< CRYPTO INTR_SET: PR_DATA_AVAILABLE (Bit 4) */ +#define CRYPTO_INTR_SET_PR_DATA_AVAILABLE_Msk (0x10UL) /*!< CRYPTO INTR_SET: PR_DATA_AVAILABLE (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_SET_INSTR_OPC_ERROR_Pos (16UL) /*!< CRYPTO INTR_SET: INSTR_OPC_ERROR (Bit 16) */ +#define CRYPTO_INTR_SET_INSTR_OPC_ERROR_Msk (0x10000UL) /*!< CRYPTO INTR_SET: INSTR_OPC_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_SET_INSTR_CC_ERROR_Pos (17UL) /*!< CRYPTO INTR_SET: INSTR_CC_ERROR (Bit 17) */ +#define CRYPTO_INTR_SET_INSTR_CC_ERROR_Msk (0x20000UL) /*!< CRYPTO INTR_SET: INSTR_CC_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_SET_BUS_ERROR_Pos (18UL) /*!< CRYPTO INTR_SET: BUS_ERROR (Bit 18) */ +#define CRYPTO_INTR_SET_BUS_ERROR_Msk (0x40000UL) /*!< CRYPTO INTR_SET: BUS_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_SET_TR_AP_DETECT_ERROR_Pos (19UL) /*!< CRYPTO INTR_SET: TR_AP_DETECT_ERROR (Bit 19) */ +#define CRYPTO_INTR_SET_TR_AP_DETECT_ERROR_Msk (0x80000UL) /*!< CRYPTO INTR_SET: TR_AP_DETECT_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_SET_TR_RC_DETECT_ERROR_Pos (20UL) /*!< CRYPTO INTR_SET: TR_RC_DETECT_ERROR (Bit 20) */ +#define CRYPTO_INTR_SET_TR_RC_DETECT_ERROR_Msk (0x100000UL) /*!< CRYPTO INTR_SET: TR_RC_DETECT_ERROR (Bitfield-Mask: 0x01) */ +/* =================================================== CRYPTO.INTR_MASK ==================================================== */ +#define CRYPTO_INTR_MASK_INSTR_FF_LEVEL_Pos (0UL) /*!< CRYPTO INTR_MASK: INSTR_FF_LEVEL (Bit 0) */ +#define CRYPTO_INTR_MASK_INSTR_FF_LEVEL_Msk (0x1UL) /*!< CRYPTO INTR_MASK: INSTR_FF_LEVEL (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASK_INSTR_FF_OVERFLOW_Pos (1UL) /*!< CRYPTO INTR_MASK: INSTR_FF_OVERFLOW (Bit 1) */ +#define CRYPTO_INTR_MASK_INSTR_FF_OVERFLOW_Msk (0x2UL) /*!< CRYPTO INTR_MASK: INSTR_FF_OVERFLOW (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASK_TR_INITIALIZED_Pos (2UL) /*!< CRYPTO INTR_MASK: TR_INITIALIZED (Bit 2) */ +#define CRYPTO_INTR_MASK_TR_INITIALIZED_Msk (0x4UL) /*!< CRYPTO INTR_MASK: TR_INITIALIZED (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASK_TR_DATA_AVAILABLE_Pos (3UL) /*!< CRYPTO INTR_MASK: TR_DATA_AVAILABLE (Bit 3) */ +#define CRYPTO_INTR_MASK_TR_DATA_AVAILABLE_Msk (0x8UL) /*!< CRYPTO INTR_MASK: TR_DATA_AVAILABLE (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASK_PR_DATA_AVAILABLE_Pos (4UL) /*!< CRYPTO INTR_MASK: PR_DATA_AVAILABLE (Bit 4) */ +#define CRYPTO_INTR_MASK_PR_DATA_AVAILABLE_Msk (0x10UL) /*!< CRYPTO INTR_MASK: PR_DATA_AVAILABLE (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASK_INSTR_OPC_ERROR_Pos (16UL) /*!< CRYPTO INTR_MASK: INSTR_OPC_ERROR (Bit 16) */ +#define CRYPTO_INTR_MASK_INSTR_OPC_ERROR_Msk (0x10000UL) /*!< CRYPTO INTR_MASK: INSTR_OPC_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASK_INSTR_CC_ERROR_Pos (17UL) /*!< CRYPTO INTR_MASK: INSTR_CC_ERROR (Bit 17) */ +#define CRYPTO_INTR_MASK_INSTR_CC_ERROR_Msk (0x20000UL) /*!< CRYPTO INTR_MASK: INSTR_CC_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASK_BUS_ERROR_Pos (18UL) /*!< CRYPTO INTR_MASK: BUS_ERROR (Bit 18) */ +#define CRYPTO_INTR_MASK_BUS_ERROR_Msk (0x40000UL) /*!< CRYPTO INTR_MASK: BUS_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASK_TR_AP_DETECT_ERROR_Pos (19UL) /*!< CRYPTO INTR_MASK: TR_AP_DETECT_ERROR (Bit 19) */ +#define CRYPTO_INTR_MASK_TR_AP_DETECT_ERROR_Msk (0x80000UL) /*!< CRYPTO INTR_MASK: TR_AP_DETECT_ERROR (Bitfield-Mask: 0x01)*/ +#define CRYPTO_INTR_MASK_TR_RC_DETECT_ERROR_Pos (20UL) /*!< CRYPTO INTR_MASK: TR_RC_DETECT_ERROR (Bit 20) */ +#define CRYPTO_INTR_MASK_TR_RC_DETECT_ERROR_Msk (0x100000UL) /*!< CRYPTO INTR_MASK: TR_RC_DETECT_ERROR (Bitfield-Mask: 0x01)*/ +/* ================================================== CRYPTO.INTR_MASKED =================================================== */ +#define CRYPTO_INTR_MASKED_INSTR_FF_LEVEL_Pos (0UL) /*!< CRYPTO INTR_MASKED: INSTR_FF_LEVEL (Bit 0) */ +#define CRYPTO_INTR_MASKED_INSTR_FF_LEVEL_Msk (0x1UL) /*!< CRYPTO INTR_MASKED: INSTR_FF_LEVEL (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASKED_INSTR_FF_OVERFLOW_Pos (1UL) /*!< CRYPTO INTR_MASKED: INSTR_FF_OVERFLOW (Bit 1) */ +#define CRYPTO_INTR_MASKED_INSTR_FF_OVERFLOW_Msk (0x2UL) /*!< CRYPTO INTR_MASKED: INSTR_FF_OVERFLOW (Bitfield-Mask: 0x01)*/ +#define CRYPTO_INTR_MASKED_TR_INITIALIZED_Pos (2UL) /*!< CRYPTO INTR_MASKED: TR_INITIALIZED (Bit 2) */ +#define CRYPTO_INTR_MASKED_TR_INITIALIZED_Msk (0x4UL) /*!< CRYPTO INTR_MASKED: TR_INITIALIZED (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASKED_TR_DATA_AVAILABLE_Pos (3UL) /*!< CRYPTO INTR_MASKED: TR_DATA_AVAILABLE (Bit 3) */ +#define CRYPTO_INTR_MASKED_TR_DATA_AVAILABLE_Msk (0x8UL) /*!< CRYPTO INTR_MASKED: TR_DATA_AVAILABLE (Bitfield-Mask: 0x01)*/ +#define CRYPTO_INTR_MASKED_PR_DATA_AVAILABLE_Pos (4UL) /*!< CRYPTO INTR_MASKED: PR_DATA_AVAILABLE (Bit 4) */ +#define CRYPTO_INTR_MASKED_PR_DATA_AVAILABLE_Msk (0x10UL) /*!< CRYPTO INTR_MASKED: PR_DATA_AVAILABLE (Bitfield-Mask: 0x01)*/ +#define CRYPTO_INTR_MASKED_INSTR_OPC_ERROR_Pos (16UL) /*!< CRYPTO INTR_MASKED: INSTR_OPC_ERROR (Bit 16) */ +#define CRYPTO_INTR_MASKED_INSTR_OPC_ERROR_Msk (0x10000UL) /*!< CRYPTO INTR_MASKED: INSTR_OPC_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASKED_INSTR_CC_ERROR_Pos (17UL) /*!< CRYPTO INTR_MASKED: INSTR_CC_ERROR (Bit 17) */ +#define CRYPTO_INTR_MASKED_INSTR_CC_ERROR_Msk (0x20000UL) /*!< CRYPTO INTR_MASKED: INSTR_CC_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASKED_BUS_ERROR_Pos (18UL) /*!< CRYPTO INTR_MASKED: BUS_ERROR (Bit 18) */ +#define CRYPTO_INTR_MASKED_BUS_ERROR_Msk (0x40000UL) /*!< CRYPTO INTR_MASKED: BUS_ERROR (Bitfield-Mask: 0x01) */ +#define CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Pos (19UL) /*!< CRYPTO INTR_MASKED: TR_AP_DETECT_ERROR (Bit 19) */ +#define CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Msk (0x80000UL) /*!< CRYPTO INTR_MASKED: TR_AP_DETECT_ERROR (Bitfield-Mask: 0x01)*/ +#define CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Pos (20UL) /*!< CRYPTO INTR_MASKED: TR_RC_DETECT_ERROR (Bit 20) */ +#define CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Msk (0x100000UL) /*!< CRYPTO INTR_MASKED: TR_RC_DETECT_ERROR (Bitfield-Mask: 0x01)*/ +/* ==================================================== CRYPTO.MEM_BUFF ==================================================== */ +#define CRYPTO_MEM_BUFF_DATA32_Pos (0UL) /*!< CRYPTO MEM_BUFF: DATA32 (Bit 0) */ +#define CRYPTO_MEM_BUFF_DATA32_Msk (0xffffffffUL) /*!< CRYPTO MEM_BUFF: DATA32 (Bitfield-Mask: 0xffffffff) */ + + +#endif /* _CYIP_CRYPTO_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_csd.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_csd.h new file mode 100644 index 0000000000..f939ab9e29 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_csd.h @@ -0,0 +1,473 @@ +/***************************************************************************//** +* \file cyip_csd.h +* +* \brief +* CSD IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_CSD_H_ +#define _CYIP_CSD_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ CSD ================ */ +/* =========================================================================================================================== */ + +#define CSD_SECTION_SIZE 0x00001000UL + +/** + * \brief Capsense Controller (CSD) + */ +typedef struct { /*!< CSD Structure */ + __IOM uint32_t CONFIG; /*!< 0x00000000 Configuration and Control */ + __IOM uint32_t SPARE; /*!< 0x00000004 Spare MMIO */ + __IM uint32_t RESERVED[30]; + __IM uint32_t STATUS; /*!< 0x00000080 Status Register */ + __IM uint32_t STAT_SEQ; /*!< 0x00000084 Current Sequencer status */ + __IM uint32_t STAT_CNTS; /*!< 0x00000088 Current status counts */ + __IM uint32_t RESERVED1[17]; + __IM uint32_t RESULT_VAL1; /*!< 0x000000D0 Result CSD/CSX accumulation counter value 1 */ + __IM uint32_t RESULT_VAL2; /*!< 0x000000D4 Result CSX accumulation counter value 2 */ + __IM uint32_t RESERVED2[2]; + __IM uint32_t ADC_RES; /*!< 0x000000E0 ADC measurement */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t INTR; /*!< 0x000000F0 CSD Interrupt Request Register */ + __IOM uint32_t INTR_SET; /*!< 0x000000F4 CSD Interrupt set register */ + __IOM uint32_t INTR_MASK; /*!< 0x000000F8 CSD Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x000000FC CSD Interrupt masked register */ + __IM uint32_t RESERVED4[32]; + __IOM uint32_t HSCMP; /*!< 0x00000180 High Speed Comparator configuration */ + __IOM uint32_t AMBUF; /*!< 0x00000184 Reference Generator configuration */ + __IOM uint32_t REFGEN; /*!< 0x00000188 Reference Generator configuration */ + __IOM uint32_t CSDCMP; /*!< 0x0000018C CSD Comparator configuration */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t SW_RES; /*!< 0x000001F0 Switch Resistance configuration */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t SENSE_PERIOD; /*!< 0x00000200 Sense clock period */ + __IOM uint32_t SENSE_DUTY; /*!< 0x00000204 Sense clock duty cycle */ + __IM uint32_t RESERVED7[30]; + __IOM uint32_t SW_HS_P_SEL; /*!< 0x00000280 HSCMP Pos input switch Waveform selection */ + __IOM uint32_t SW_HS_N_SEL; /*!< 0x00000284 HSCMP Neg input switch Waveform selection */ + __IOM uint32_t SW_SHIELD_SEL; /*!< 0x00000288 Shielding switches Waveform selection */ + __IM uint32_t RESERVED8; + __IOM uint32_t SW_AMUXBUF_SEL; /*!< 0x00000290 Amuxbuffer switches Waveform selection */ + __IOM uint32_t SW_BYP_SEL; /*!< 0x00000294 AMUXBUS bypass switches Waveform selection */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t SW_CMP_P_SEL; /*!< 0x000002A0 CSDCMP Pos Switch Waveform selection */ + __IOM uint32_t SW_CMP_N_SEL; /*!< 0x000002A4 CSDCMP Neg Switch Waveform selection */ + __IOM uint32_t SW_REFGEN_SEL; /*!< 0x000002A8 Reference Generator Switch Waveform selection */ + __IM uint32_t RESERVED10; + __IOM uint32_t SW_FW_MOD_SEL; /*!< 0x000002B0 Full Wave Cmod Switch Waveform selection */ + __IOM uint32_t SW_FW_TANK_SEL; /*!< 0x000002B4 Full Wave Csh_tank Switch Waveform selection */ + __IM uint32_t RESERVED11[2]; + __IOM uint32_t SW_DSI_SEL; /*!< 0x000002C0 DSI output switch control Waveform selection */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t IO_SEL; /*!< 0x000002D0 IO output control Waveform selection */ + __IM uint32_t RESERVED13[11]; + __IOM uint32_t SEQ_TIME; /*!< 0x00000300 Sequencer Timing */ + __IM uint32_t RESERVED14[3]; + __IOM uint32_t SEQ_INIT_CNT; /*!< 0x00000310 Sequencer Initial conversion and sample counts */ + __IOM uint32_t SEQ_NORM_CNT; /*!< 0x00000314 Sequencer Normal conversion and sample counts */ + __IM uint32_t RESERVED15[2]; + __IOM uint32_t ADC_CTL; /*!< 0x00000320 ADC Control */ + __IM uint32_t RESERVED16[7]; + __IOM uint32_t SEQ_START; /*!< 0x00000340 Sequencer start */ + __IM uint32_t RESERVED17[47]; + __IOM uint32_t IDACA; /*!< 0x00000400 IDACA Configuration */ + __IM uint32_t RESERVED18[63]; + __IOM uint32_t IDACB; /*!< 0x00000500 IDACB Configuration */ +} CSD_Type; /*!< Size = 1284 (0x504) */ + + +/* ====================================================== CSD.CONFIG ======================================================= */ +#define CSD_CONFIG_IREF_SEL_Pos (0UL) /*!< CSD CONFIG: IREF_SEL (Bit 0) */ +#define CSD_CONFIG_IREF_SEL_Msk (0x1UL) /*!< CSD CONFIG: IREF_SEL (Bitfield-Mask: 0x01) */ +#define CSD_CONFIG_FILTER_DELAY_Pos (4UL) /*!< CSD CONFIG: FILTER_DELAY (Bit 4) */ +#define CSD_CONFIG_FILTER_DELAY_Msk (0x1f0UL) /*!< CSD CONFIG: FILTER_DELAY (Bitfield-Mask: 0x1f) */ +#define CSD_CONFIG_SHIELD_DELAY_Pos (10UL) /*!< CSD CONFIG: SHIELD_DELAY (Bit 10) */ +#define CSD_CONFIG_SHIELD_DELAY_Msk (0xc00UL) /*!< CSD CONFIG: SHIELD_DELAY (Bitfield-Mask: 0x03) */ +#define CSD_CONFIG_SENSE_EN_Pos (12UL) /*!< CSD CONFIG: SENSE_EN (Bit 12) */ +#define CSD_CONFIG_SENSE_EN_Msk (0x1000UL) /*!< CSD CONFIG: SENSE_EN (Bitfield-Mask: 0x01) */ +#define CSD_CONFIG_FULL_WAVE_Pos (17UL) /*!< CSD CONFIG: FULL_WAVE (Bit 17) */ +#define CSD_CONFIG_FULL_WAVE_Msk (0x20000UL) /*!< CSD CONFIG: FULL_WAVE (Bitfield-Mask: 0x01) */ +#define CSD_CONFIG_MUTUAL_CAP_Pos (18UL) /*!< CSD CONFIG: MUTUAL_CAP (Bit 18) */ +#define CSD_CONFIG_MUTUAL_CAP_Msk (0x40000UL) /*!< CSD CONFIG: MUTUAL_CAP (Bitfield-Mask: 0x01) */ +#define CSD_CONFIG_CSX_DUAL_CNT_Pos (19UL) /*!< CSD CONFIG: CSX_DUAL_CNT (Bit 19) */ +#define CSD_CONFIG_CSX_DUAL_CNT_Msk (0x80000UL) /*!< CSD CONFIG: CSX_DUAL_CNT (Bitfield-Mask: 0x01) */ +#define CSD_CONFIG_DSI_COUNT_SEL_Pos (24UL) /*!< CSD CONFIG: DSI_COUNT_SEL (Bit 24) */ +#define CSD_CONFIG_DSI_COUNT_SEL_Msk (0x1000000UL) /*!< CSD CONFIG: DSI_COUNT_SEL (Bitfield-Mask: 0x01) */ +#define CSD_CONFIG_DSI_SAMPLE_EN_Pos (25UL) /*!< CSD CONFIG: DSI_SAMPLE_EN (Bit 25) */ +#define CSD_CONFIG_DSI_SAMPLE_EN_Msk (0x2000000UL) /*!< CSD CONFIG: DSI_SAMPLE_EN (Bitfield-Mask: 0x01) */ +#define CSD_CONFIG_SAMPLE_SYNC_Pos (26UL) /*!< CSD CONFIG: SAMPLE_SYNC (Bit 26) */ +#define CSD_CONFIG_SAMPLE_SYNC_Msk (0x4000000UL) /*!< CSD CONFIG: SAMPLE_SYNC (Bitfield-Mask: 0x01) */ +#define CSD_CONFIG_DSI_SENSE_EN_Pos (27UL) /*!< CSD CONFIG: DSI_SENSE_EN (Bit 27) */ +#define CSD_CONFIG_DSI_SENSE_EN_Msk (0x8000000UL) /*!< CSD CONFIG: DSI_SENSE_EN (Bitfield-Mask: 0x01) */ +#define CSD_CONFIG_LP_MODE_Pos (30UL) /*!< CSD CONFIG: LP_MODE (Bit 30) */ +#define CSD_CONFIG_LP_MODE_Msk (0x40000000UL) /*!< CSD CONFIG: LP_MODE (Bitfield-Mask: 0x01) */ +#define CSD_CONFIG_ENABLE_Pos (31UL) /*!< CSD CONFIG: ENABLE (Bit 31) */ +#define CSD_CONFIG_ENABLE_Msk (0x80000000UL) /*!< CSD CONFIG: ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CSD.SPARE ======================================================= */ +#define CSD_SPARE_SPARE_Pos (0UL) /*!< CSD SPARE: SPARE (Bit 0) */ +#define CSD_SPARE_SPARE_Msk (0xfUL) /*!< CSD SPARE: SPARE (Bitfield-Mask: 0x0f) */ +/* ====================================================== CSD.STATUS ======================================================= */ +#define CSD_STATUS_CSD_SENSE_Pos (1UL) /*!< CSD STATUS: CSD_SENSE (Bit 1) */ +#define CSD_STATUS_CSD_SENSE_Msk (0x2UL) /*!< CSD STATUS: CSD_SENSE (Bitfield-Mask: 0x01) */ +#define CSD_STATUS_HSCMP_OUT_Pos (2UL) /*!< CSD STATUS: HSCMP_OUT (Bit 2) */ +#define CSD_STATUS_HSCMP_OUT_Msk (0x4UL) /*!< CSD STATUS: HSCMP_OUT (Bitfield-Mask: 0x01) */ +#define CSD_STATUS_CSDCMP_OUT_Pos (3UL) /*!< CSD STATUS: CSDCMP_OUT (Bit 3) */ +#define CSD_STATUS_CSDCMP_OUT_Msk (0x8UL) /*!< CSD STATUS: CSDCMP_OUT (Bitfield-Mask: 0x01) */ +/* ===================================================== CSD.STAT_SEQ ====================================================== */ +#define CSD_STAT_SEQ_SEQ_STATE_Pos (0UL) /*!< CSD STAT_SEQ: SEQ_STATE (Bit 0) */ +#define CSD_STAT_SEQ_SEQ_STATE_Msk (0x7UL) /*!< CSD STAT_SEQ: SEQ_STATE (Bitfield-Mask: 0x07) */ +#define CSD_STAT_SEQ_ADC_STATE_Pos (16UL) /*!< CSD STAT_SEQ: ADC_STATE (Bit 16) */ +#define CSD_STAT_SEQ_ADC_STATE_Msk (0x70000UL) /*!< CSD STAT_SEQ: ADC_STATE (Bitfield-Mask: 0x07) */ +/* ===================================================== CSD.STAT_CNTS ===================================================== */ +#define CSD_STAT_CNTS_NUM_CONV_Pos (0UL) /*!< CSD STAT_CNTS: NUM_CONV (Bit 0) */ +#define CSD_STAT_CNTS_NUM_CONV_Msk (0xffffUL) /*!< CSD STAT_CNTS: NUM_CONV (Bitfield-Mask: 0xffff) */ +/* ==================================================== CSD.RESULT_VAL1 ==================================================== */ +#define CSD_RESULT_VAL1_VALUE_Pos (0UL) /*!< CSD RESULT_VAL1: VALUE (Bit 0) */ +#define CSD_RESULT_VAL1_VALUE_Msk (0xffffUL) /*!< CSD RESULT_VAL1: VALUE (Bitfield-Mask: 0xffff) */ +#define CSD_RESULT_VAL1_BAD_CONVS_Pos (16UL) /*!< CSD RESULT_VAL1: BAD_CONVS (Bit 16) */ +#define CSD_RESULT_VAL1_BAD_CONVS_Msk (0xff0000UL) /*!< CSD RESULT_VAL1: BAD_CONVS (Bitfield-Mask: 0xff) */ +/* ==================================================== CSD.RESULT_VAL2 ==================================================== */ +#define CSD_RESULT_VAL2_VALUE_Pos (0UL) /*!< CSD RESULT_VAL2: VALUE (Bit 0) */ +#define CSD_RESULT_VAL2_VALUE_Msk (0xffffUL) /*!< CSD RESULT_VAL2: VALUE (Bitfield-Mask: 0xffff) */ +/* ====================================================== CSD.ADC_RES ====================================================== */ +#define CSD_ADC_RES_VIN_CNT_Pos (0UL) /*!< CSD ADC_RES: VIN_CNT (Bit 0) */ +#define CSD_ADC_RES_VIN_CNT_Msk (0xffffUL) /*!< CSD ADC_RES: VIN_CNT (Bitfield-Mask: 0xffff) */ +#define CSD_ADC_RES_HSCMP_POL_Pos (16UL) /*!< CSD ADC_RES: HSCMP_POL (Bit 16) */ +#define CSD_ADC_RES_HSCMP_POL_Msk (0x10000UL) /*!< CSD ADC_RES: HSCMP_POL (Bitfield-Mask: 0x01) */ +#define CSD_ADC_RES_ADC_OVERFLOW_Pos (30UL) /*!< CSD ADC_RES: ADC_OVERFLOW (Bit 30) */ +#define CSD_ADC_RES_ADC_OVERFLOW_Msk (0x40000000UL) /*!< CSD ADC_RES: ADC_OVERFLOW (Bitfield-Mask: 0x01) */ +#define CSD_ADC_RES_ADC_ABORT_Pos (31UL) /*!< CSD ADC_RES: ADC_ABORT (Bit 31) */ +#define CSD_ADC_RES_ADC_ABORT_Msk (0x80000000UL) /*!< CSD ADC_RES: ADC_ABORT (Bitfield-Mask: 0x01) */ +/* ======================================================= CSD.INTR ======================================================== */ +#define CSD_INTR_SAMPLE_Pos (1UL) /*!< CSD INTR: SAMPLE (Bit 1) */ +#define CSD_INTR_SAMPLE_Msk (0x2UL) /*!< CSD INTR: SAMPLE (Bitfield-Mask: 0x01) */ +#define CSD_INTR_INIT_Pos (2UL) /*!< CSD INTR: INIT (Bit 2) */ +#define CSD_INTR_INIT_Msk (0x4UL) /*!< CSD INTR: INIT (Bitfield-Mask: 0x01) */ +#define CSD_INTR_ADC_RES_Pos (8UL) /*!< CSD INTR: ADC_RES (Bit 8) */ +#define CSD_INTR_ADC_RES_Msk (0x100UL) /*!< CSD INTR: ADC_RES (Bitfield-Mask: 0x01) */ +/* ===================================================== CSD.INTR_SET ====================================================== */ +#define CSD_INTR_SET_SAMPLE_Pos (1UL) /*!< CSD INTR_SET: SAMPLE (Bit 1) */ +#define CSD_INTR_SET_SAMPLE_Msk (0x2UL) /*!< CSD INTR_SET: SAMPLE (Bitfield-Mask: 0x01) */ +#define CSD_INTR_SET_INIT_Pos (2UL) /*!< CSD INTR_SET: INIT (Bit 2) */ +#define CSD_INTR_SET_INIT_Msk (0x4UL) /*!< CSD INTR_SET: INIT (Bitfield-Mask: 0x01) */ +#define CSD_INTR_SET_ADC_RES_Pos (8UL) /*!< CSD INTR_SET: ADC_RES (Bit 8) */ +#define CSD_INTR_SET_ADC_RES_Msk (0x100UL) /*!< CSD INTR_SET: ADC_RES (Bitfield-Mask: 0x01) */ +/* ===================================================== CSD.INTR_MASK ===================================================== */ +#define CSD_INTR_MASK_SAMPLE_Pos (1UL) /*!< CSD INTR_MASK: SAMPLE (Bit 1) */ +#define CSD_INTR_MASK_SAMPLE_Msk (0x2UL) /*!< CSD INTR_MASK: SAMPLE (Bitfield-Mask: 0x01) */ +#define CSD_INTR_MASK_INIT_Pos (2UL) /*!< CSD INTR_MASK: INIT (Bit 2) */ +#define CSD_INTR_MASK_INIT_Msk (0x4UL) /*!< CSD INTR_MASK: INIT (Bitfield-Mask: 0x01) */ +#define CSD_INTR_MASK_ADC_RES_Pos (8UL) /*!< CSD INTR_MASK: ADC_RES (Bit 8) */ +#define CSD_INTR_MASK_ADC_RES_Msk (0x100UL) /*!< CSD INTR_MASK: ADC_RES (Bitfield-Mask: 0x01) */ +/* ==================================================== CSD.INTR_MASKED ==================================================== */ +#define CSD_INTR_MASKED_SAMPLE_Pos (1UL) /*!< CSD INTR_MASKED: SAMPLE (Bit 1) */ +#define CSD_INTR_MASKED_SAMPLE_Msk (0x2UL) /*!< CSD INTR_MASKED: SAMPLE (Bitfield-Mask: 0x01) */ +#define CSD_INTR_MASKED_INIT_Pos (2UL) /*!< CSD INTR_MASKED: INIT (Bit 2) */ +#define CSD_INTR_MASKED_INIT_Msk (0x4UL) /*!< CSD INTR_MASKED: INIT (Bitfield-Mask: 0x01) */ +#define CSD_INTR_MASKED_ADC_RES_Pos (8UL) /*!< CSD INTR_MASKED: ADC_RES (Bit 8) */ +#define CSD_INTR_MASKED_ADC_RES_Msk (0x100UL) /*!< CSD INTR_MASKED: ADC_RES (Bitfield-Mask: 0x01) */ +/* ======================================================= CSD.HSCMP ======================================================= */ +#define CSD_HSCMP_HSCMP_EN_Pos (0UL) /*!< CSD HSCMP: HSCMP_EN (Bit 0) */ +#define CSD_HSCMP_HSCMP_EN_Msk (0x1UL) /*!< CSD HSCMP: HSCMP_EN (Bitfield-Mask: 0x01) */ +#define CSD_HSCMP_HSCMP_INVERT_Pos (4UL) /*!< CSD HSCMP: HSCMP_INVERT (Bit 4) */ +#define CSD_HSCMP_HSCMP_INVERT_Msk (0x10UL) /*!< CSD HSCMP: HSCMP_INVERT (Bitfield-Mask: 0x01) */ +#define CSD_HSCMP_AZ_EN_Pos (31UL) /*!< CSD HSCMP: AZ_EN (Bit 31) */ +#define CSD_HSCMP_AZ_EN_Msk (0x80000000UL) /*!< CSD HSCMP: AZ_EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CSD.AMBUF ======================================================= */ +#define CSD_AMBUF_PWR_MODE_Pos (0UL) /*!< CSD AMBUF: PWR_MODE (Bit 0) */ +#define CSD_AMBUF_PWR_MODE_Msk (0x3UL) /*!< CSD AMBUF: PWR_MODE (Bitfield-Mask: 0x03) */ +/* ====================================================== CSD.REFGEN ======================================================= */ +#define CSD_REFGEN_REFGEN_EN_Pos (0UL) /*!< CSD REFGEN: REFGEN_EN (Bit 0) */ +#define CSD_REFGEN_REFGEN_EN_Msk (0x1UL) /*!< CSD REFGEN: REFGEN_EN (Bitfield-Mask: 0x01) */ +#define CSD_REFGEN_BYPASS_Pos (4UL) /*!< CSD REFGEN: BYPASS (Bit 4) */ +#define CSD_REFGEN_BYPASS_Msk (0x10UL) /*!< CSD REFGEN: BYPASS (Bitfield-Mask: 0x01) */ +#define CSD_REFGEN_VDDA_EN_Pos (5UL) /*!< CSD REFGEN: VDDA_EN (Bit 5) */ +#define CSD_REFGEN_VDDA_EN_Msk (0x20UL) /*!< CSD REFGEN: VDDA_EN (Bitfield-Mask: 0x01) */ +#define CSD_REFGEN_RES_EN_Pos (6UL) /*!< CSD REFGEN: RES_EN (Bit 6) */ +#define CSD_REFGEN_RES_EN_Msk (0x40UL) /*!< CSD REFGEN: RES_EN (Bitfield-Mask: 0x01) */ +#define CSD_REFGEN_GAIN_Pos (8UL) /*!< CSD REFGEN: GAIN (Bit 8) */ +#define CSD_REFGEN_GAIN_Msk (0x1f00UL) /*!< CSD REFGEN: GAIN (Bitfield-Mask: 0x1f) */ +#define CSD_REFGEN_VREFLO_SEL_Pos (16UL) /*!< CSD REFGEN: VREFLO_SEL (Bit 16) */ +#define CSD_REFGEN_VREFLO_SEL_Msk (0x1f0000UL) /*!< CSD REFGEN: VREFLO_SEL (Bitfield-Mask: 0x1f) */ +#define CSD_REFGEN_VREFLO_INT_Pos (23UL) /*!< CSD REFGEN: VREFLO_INT (Bit 23) */ +#define CSD_REFGEN_VREFLO_INT_Msk (0x800000UL) /*!< CSD REFGEN: VREFLO_INT (Bitfield-Mask: 0x01) */ +/* ====================================================== CSD.CSDCMP ======================================================= */ +#define CSD_CSDCMP_CSDCMP_EN_Pos (0UL) /*!< CSD CSDCMP: CSDCMP_EN (Bit 0) */ +#define CSD_CSDCMP_CSDCMP_EN_Msk (0x1UL) /*!< CSD CSDCMP: CSDCMP_EN (Bitfield-Mask: 0x01) */ +#define CSD_CSDCMP_POLARITY_SEL_Pos (4UL) /*!< CSD CSDCMP: POLARITY_SEL (Bit 4) */ +#define CSD_CSDCMP_POLARITY_SEL_Msk (0x30UL) /*!< CSD CSDCMP: POLARITY_SEL (Bitfield-Mask: 0x03) */ +#define CSD_CSDCMP_CMP_PHASE_Pos (8UL) /*!< CSD CSDCMP: CMP_PHASE (Bit 8) */ +#define CSD_CSDCMP_CMP_PHASE_Msk (0x300UL) /*!< CSD CSDCMP: CMP_PHASE (Bitfield-Mask: 0x03) */ +#define CSD_CSDCMP_CMP_MODE_Pos (28UL) /*!< CSD CSDCMP: CMP_MODE (Bit 28) */ +#define CSD_CSDCMP_CMP_MODE_Msk (0x10000000UL) /*!< CSD CSDCMP: CMP_MODE (Bitfield-Mask: 0x01) */ +#define CSD_CSDCMP_FEEDBACK_MODE_Pos (29UL) /*!< CSD CSDCMP: FEEDBACK_MODE (Bit 29) */ +#define CSD_CSDCMP_FEEDBACK_MODE_Msk (0x20000000UL) /*!< CSD CSDCMP: FEEDBACK_MODE (Bitfield-Mask: 0x01) */ +#define CSD_CSDCMP_AZ_EN_Pos (31UL) /*!< CSD CSDCMP: AZ_EN (Bit 31) */ +#define CSD_CSDCMP_AZ_EN_Msk (0x80000000UL) /*!< CSD CSDCMP: AZ_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== CSD.SW_RES ======================================================= */ +#define CSD_SW_RES_RES_HCAV_Pos (0UL) /*!< CSD SW_RES: RES_HCAV (Bit 0) */ +#define CSD_SW_RES_RES_HCAV_Msk (0x3UL) /*!< CSD SW_RES: RES_HCAV (Bitfield-Mask: 0x03) */ +#define CSD_SW_RES_RES_HCAG_Pos (2UL) /*!< CSD SW_RES: RES_HCAG (Bit 2) */ +#define CSD_SW_RES_RES_HCAG_Msk (0xcUL) /*!< CSD SW_RES: RES_HCAG (Bitfield-Mask: 0x03) */ +#define CSD_SW_RES_RES_HCBV_Pos (4UL) /*!< CSD SW_RES: RES_HCBV (Bit 4) */ +#define CSD_SW_RES_RES_HCBV_Msk (0x30UL) /*!< CSD SW_RES: RES_HCBV (Bitfield-Mask: 0x03) */ +#define CSD_SW_RES_RES_HCBG_Pos (6UL) /*!< CSD SW_RES: RES_HCBG (Bit 6) */ +#define CSD_SW_RES_RES_HCBG_Msk (0xc0UL) /*!< CSD SW_RES: RES_HCBG (Bitfield-Mask: 0x03) */ +#define CSD_SW_RES_RES_F1PM_Pos (16UL) /*!< CSD SW_RES: RES_F1PM (Bit 16) */ +#define CSD_SW_RES_RES_F1PM_Msk (0x30000UL) /*!< CSD SW_RES: RES_F1PM (Bitfield-Mask: 0x03) */ +#define CSD_SW_RES_RES_F2PT_Pos (18UL) /*!< CSD SW_RES: RES_F2PT (Bit 18) */ +#define CSD_SW_RES_RES_F2PT_Msk (0xc0000UL) /*!< CSD SW_RES: RES_F2PT (Bitfield-Mask: 0x03) */ +/* =================================================== CSD.SENSE_PERIOD ==================================================== */ +#define CSD_SENSE_PERIOD_SENSE_DIV_Pos (0UL) /*!< CSD SENSE_PERIOD: SENSE_DIV (Bit 0) */ +#define CSD_SENSE_PERIOD_SENSE_DIV_Msk (0xfffUL) /*!< CSD SENSE_PERIOD: SENSE_DIV (Bitfield-Mask: 0xfff) */ +#define CSD_SENSE_PERIOD_LFSR_SIZE_Pos (16UL) /*!< CSD SENSE_PERIOD: LFSR_SIZE (Bit 16) */ +#define CSD_SENSE_PERIOD_LFSR_SIZE_Msk (0x70000UL) /*!< CSD SENSE_PERIOD: LFSR_SIZE (Bitfield-Mask: 0x07) */ +#define CSD_SENSE_PERIOD_LFSR_SCALE_Pos (20UL) /*!< CSD SENSE_PERIOD: LFSR_SCALE (Bit 20) */ +#define CSD_SENSE_PERIOD_LFSR_SCALE_Msk (0xf00000UL) /*!< CSD SENSE_PERIOD: LFSR_SCALE (Bitfield-Mask: 0x0f) */ +#define CSD_SENSE_PERIOD_LFSR_CLEAR_Pos (24UL) /*!< CSD SENSE_PERIOD: LFSR_CLEAR (Bit 24) */ +#define CSD_SENSE_PERIOD_LFSR_CLEAR_Msk (0x1000000UL) /*!< CSD SENSE_PERIOD: LFSR_CLEAR (Bitfield-Mask: 0x01) */ +#define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Pos (25UL) /*!< CSD SENSE_PERIOD: SEL_LFSR_MSB (Bit 25) */ +#define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Msk (0x2000000UL) /*!< CSD SENSE_PERIOD: SEL_LFSR_MSB (Bitfield-Mask: 0x01) */ +#define CSD_SENSE_PERIOD_LFSR_BITS_Pos (26UL) /*!< CSD SENSE_PERIOD: LFSR_BITS (Bit 26) */ +#define CSD_SENSE_PERIOD_LFSR_BITS_Msk (0xc000000UL) /*!< CSD SENSE_PERIOD: LFSR_BITS (Bitfield-Mask: 0x03) */ +/* ==================================================== CSD.SENSE_DUTY ===================================================== */ +#define CSD_SENSE_DUTY_SENSE_WIDTH_Pos (0UL) /*!< CSD SENSE_DUTY: SENSE_WIDTH (Bit 0) */ +#define CSD_SENSE_DUTY_SENSE_WIDTH_Msk (0xfffUL) /*!< CSD SENSE_DUTY: SENSE_WIDTH (Bitfield-Mask: 0xfff) */ +#define CSD_SENSE_DUTY_SENSE_POL_Pos (16UL) /*!< CSD SENSE_DUTY: SENSE_POL (Bit 16) */ +#define CSD_SENSE_DUTY_SENSE_POL_Msk (0x10000UL) /*!< CSD SENSE_DUTY: SENSE_POL (Bitfield-Mask: 0x01) */ +#define CSD_SENSE_DUTY_OVERLAP_PHI1_Pos (18UL) /*!< CSD SENSE_DUTY: OVERLAP_PHI1 (Bit 18) */ +#define CSD_SENSE_DUTY_OVERLAP_PHI1_Msk (0x40000UL) /*!< CSD SENSE_DUTY: OVERLAP_PHI1 (Bitfield-Mask: 0x01) */ +#define CSD_SENSE_DUTY_OVERLAP_PHI2_Pos (19UL) /*!< CSD SENSE_DUTY: OVERLAP_PHI2 (Bit 19) */ +#define CSD_SENSE_DUTY_OVERLAP_PHI2_Msk (0x80000UL) /*!< CSD SENSE_DUTY: OVERLAP_PHI2 (Bitfield-Mask: 0x01) */ +/* ==================================================== CSD.SW_HS_P_SEL ==================================================== */ +#define CSD_SW_HS_P_SEL_SW_HMPM_Pos (0UL) /*!< CSD SW_HS_P_SEL: SW_HMPM (Bit 0) */ +#define CSD_SW_HS_P_SEL_SW_HMPM_Msk (0x1UL) /*!< CSD SW_HS_P_SEL: SW_HMPM (Bitfield-Mask: 0x01) */ +#define CSD_SW_HS_P_SEL_SW_HMPT_Pos (4UL) /*!< CSD SW_HS_P_SEL: SW_HMPT (Bit 4) */ +#define CSD_SW_HS_P_SEL_SW_HMPT_Msk (0x10UL) /*!< CSD SW_HS_P_SEL: SW_HMPT (Bitfield-Mask: 0x01) */ +#define CSD_SW_HS_P_SEL_SW_HMPS_Pos (8UL) /*!< CSD SW_HS_P_SEL: SW_HMPS (Bit 8) */ +#define CSD_SW_HS_P_SEL_SW_HMPS_Msk (0x100UL) /*!< CSD SW_HS_P_SEL: SW_HMPS (Bitfield-Mask: 0x01) */ +#define CSD_SW_HS_P_SEL_SW_HMMA_Pos (12UL) /*!< CSD SW_HS_P_SEL: SW_HMMA (Bit 12) */ +#define CSD_SW_HS_P_SEL_SW_HMMA_Msk (0x1000UL) /*!< CSD SW_HS_P_SEL: SW_HMMA (Bitfield-Mask: 0x01) */ +#define CSD_SW_HS_P_SEL_SW_HMMB_Pos (16UL) /*!< CSD SW_HS_P_SEL: SW_HMMB (Bit 16) */ +#define CSD_SW_HS_P_SEL_SW_HMMB_Msk (0x10000UL) /*!< CSD SW_HS_P_SEL: SW_HMMB (Bitfield-Mask: 0x01) */ +#define CSD_SW_HS_P_SEL_SW_HMCA_Pos (20UL) /*!< CSD SW_HS_P_SEL: SW_HMCA (Bit 20) */ +#define CSD_SW_HS_P_SEL_SW_HMCA_Msk (0x100000UL) /*!< CSD SW_HS_P_SEL: SW_HMCA (Bitfield-Mask: 0x01) */ +#define CSD_SW_HS_P_SEL_SW_HMCB_Pos (24UL) /*!< CSD SW_HS_P_SEL: SW_HMCB (Bit 24) */ +#define CSD_SW_HS_P_SEL_SW_HMCB_Msk (0x1000000UL) /*!< CSD SW_HS_P_SEL: SW_HMCB (Bitfield-Mask: 0x01) */ +#define CSD_SW_HS_P_SEL_SW_HMRH_Pos (28UL) /*!< CSD SW_HS_P_SEL: SW_HMRH (Bit 28) */ +#define CSD_SW_HS_P_SEL_SW_HMRH_Msk (0x10000000UL) /*!< CSD SW_HS_P_SEL: SW_HMRH (Bitfield-Mask: 0x01) */ +/* ==================================================== CSD.SW_HS_N_SEL ==================================================== */ +#define CSD_SW_HS_N_SEL_SW_HCCC_Pos (16UL) /*!< CSD SW_HS_N_SEL: SW_HCCC (Bit 16) */ +#define CSD_SW_HS_N_SEL_SW_HCCC_Msk (0x10000UL) /*!< CSD SW_HS_N_SEL: SW_HCCC (Bitfield-Mask: 0x01) */ +#define CSD_SW_HS_N_SEL_SW_HCCD_Pos (20UL) /*!< CSD SW_HS_N_SEL: SW_HCCD (Bit 20) */ +#define CSD_SW_HS_N_SEL_SW_HCCD_Msk (0x100000UL) /*!< CSD SW_HS_N_SEL: SW_HCCD (Bitfield-Mask: 0x01) */ +#define CSD_SW_HS_N_SEL_SW_HCRH_Pos (24UL) /*!< CSD SW_HS_N_SEL: SW_HCRH (Bit 24) */ +#define CSD_SW_HS_N_SEL_SW_HCRH_Msk (0x7000000UL) /*!< CSD SW_HS_N_SEL: SW_HCRH (Bitfield-Mask: 0x07) */ +#define CSD_SW_HS_N_SEL_SW_HCRL_Pos (28UL) /*!< CSD SW_HS_N_SEL: SW_HCRL (Bit 28) */ +#define CSD_SW_HS_N_SEL_SW_HCRL_Msk (0x70000000UL) /*!< CSD SW_HS_N_SEL: SW_HCRL (Bitfield-Mask: 0x07) */ +/* =================================================== CSD.SW_SHIELD_SEL =================================================== */ +#define CSD_SW_SHIELD_SEL_SW_HCAV_Pos (0UL) /*!< CSD SW_SHIELD_SEL: SW_HCAV (Bit 0) */ +#define CSD_SW_SHIELD_SEL_SW_HCAV_Msk (0x7UL) /*!< CSD SW_SHIELD_SEL: SW_HCAV (Bitfield-Mask: 0x07) */ +#define CSD_SW_SHIELD_SEL_SW_HCAG_Pos (4UL) /*!< CSD SW_SHIELD_SEL: SW_HCAG (Bit 4) */ +#define CSD_SW_SHIELD_SEL_SW_HCAG_Msk (0x70UL) /*!< CSD SW_SHIELD_SEL: SW_HCAG (Bitfield-Mask: 0x07) */ +#define CSD_SW_SHIELD_SEL_SW_HCBV_Pos (8UL) /*!< CSD SW_SHIELD_SEL: SW_HCBV (Bit 8) */ +#define CSD_SW_SHIELD_SEL_SW_HCBV_Msk (0x700UL) /*!< CSD SW_SHIELD_SEL: SW_HCBV (Bitfield-Mask: 0x07) */ +#define CSD_SW_SHIELD_SEL_SW_HCBG_Pos (12UL) /*!< CSD SW_SHIELD_SEL: SW_HCBG (Bit 12) */ +#define CSD_SW_SHIELD_SEL_SW_HCBG_Msk (0x7000UL) /*!< CSD SW_SHIELD_SEL: SW_HCBG (Bitfield-Mask: 0x07) */ +#define CSD_SW_SHIELD_SEL_SW_HCCV_Pos (16UL) /*!< CSD SW_SHIELD_SEL: SW_HCCV (Bit 16) */ +#define CSD_SW_SHIELD_SEL_SW_HCCV_Msk (0x10000UL) /*!< CSD SW_SHIELD_SEL: SW_HCCV (Bitfield-Mask: 0x01) */ +#define CSD_SW_SHIELD_SEL_SW_HCCG_Pos (20UL) /*!< CSD SW_SHIELD_SEL: SW_HCCG (Bit 20) */ +#define CSD_SW_SHIELD_SEL_SW_HCCG_Msk (0x100000UL) /*!< CSD SW_SHIELD_SEL: SW_HCCG (Bitfield-Mask: 0x01) */ +/* ================================================== CSD.SW_AMUXBUF_SEL =================================================== */ +#define CSD_SW_AMUXBUF_SEL_SW_IRBY_Pos (4UL) /*!< CSD SW_AMUXBUF_SEL: SW_IRBY (Bit 4) */ +#define CSD_SW_AMUXBUF_SEL_SW_IRBY_Msk (0x10UL) /*!< CSD SW_AMUXBUF_SEL: SW_IRBY (Bitfield-Mask: 0x01) */ +#define CSD_SW_AMUXBUF_SEL_SW_IRLB_Pos (8UL) /*!< CSD SW_AMUXBUF_SEL: SW_IRLB (Bit 8) */ +#define CSD_SW_AMUXBUF_SEL_SW_IRLB_Msk (0x100UL) /*!< CSD SW_AMUXBUF_SEL: SW_IRLB (Bitfield-Mask: 0x01) */ +#define CSD_SW_AMUXBUF_SEL_SW_ICA_Pos (12UL) /*!< CSD SW_AMUXBUF_SEL: SW_ICA (Bit 12) */ +#define CSD_SW_AMUXBUF_SEL_SW_ICA_Msk (0x1000UL) /*!< CSD SW_AMUXBUF_SEL: SW_ICA (Bitfield-Mask: 0x01) */ +#define CSD_SW_AMUXBUF_SEL_SW_ICB_Pos (16UL) /*!< CSD SW_AMUXBUF_SEL: SW_ICB (Bit 16) */ +#define CSD_SW_AMUXBUF_SEL_SW_ICB_Msk (0x70000UL) /*!< CSD SW_AMUXBUF_SEL: SW_ICB (Bitfield-Mask: 0x07) */ +#define CSD_SW_AMUXBUF_SEL_SW_IRLI_Pos (20UL) /*!< CSD SW_AMUXBUF_SEL: SW_IRLI (Bit 20) */ +#define CSD_SW_AMUXBUF_SEL_SW_IRLI_Msk (0x100000UL) /*!< CSD SW_AMUXBUF_SEL: SW_IRLI (Bitfield-Mask: 0x01) */ +#define CSD_SW_AMUXBUF_SEL_SW_IRH_Pos (24UL) /*!< CSD SW_AMUXBUF_SEL: SW_IRH (Bit 24) */ +#define CSD_SW_AMUXBUF_SEL_SW_IRH_Msk (0x1000000UL) /*!< CSD SW_AMUXBUF_SEL: SW_IRH (Bitfield-Mask: 0x01) */ +#define CSD_SW_AMUXBUF_SEL_SW_IRL_Pos (28UL) /*!< CSD SW_AMUXBUF_SEL: SW_IRL (Bit 28) */ +#define CSD_SW_AMUXBUF_SEL_SW_IRL_Msk (0x10000000UL) /*!< CSD SW_AMUXBUF_SEL: SW_IRL (Bitfield-Mask: 0x01) */ +/* ==================================================== CSD.SW_BYP_SEL ===================================================== */ +#define CSD_SW_BYP_SEL_SW_BYA_Pos (12UL) /*!< CSD SW_BYP_SEL: SW_BYA (Bit 12) */ +#define CSD_SW_BYP_SEL_SW_BYA_Msk (0x1000UL) /*!< CSD SW_BYP_SEL: SW_BYA (Bitfield-Mask: 0x01) */ +#define CSD_SW_BYP_SEL_SW_BYB_Pos (16UL) /*!< CSD SW_BYP_SEL: SW_BYB (Bit 16) */ +#define CSD_SW_BYP_SEL_SW_BYB_Msk (0x10000UL) /*!< CSD SW_BYP_SEL: SW_BYB (Bitfield-Mask: 0x01) */ +#define CSD_SW_BYP_SEL_SW_CBCC_Pos (20UL) /*!< CSD SW_BYP_SEL: SW_CBCC (Bit 20) */ +#define CSD_SW_BYP_SEL_SW_CBCC_Msk (0x100000UL) /*!< CSD SW_BYP_SEL: SW_CBCC (Bitfield-Mask: 0x01) */ +/* =================================================== CSD.SW_CMP_P_SEL ==================================================== */ +#define CSD_SW_CMP_P_SEL_SW_SFPM_Pos (0UL) /*!< CSD SW_CMP_P_SEL: SW_SFPM (Bit 0) */ +#define CSD_SW_CMP_P_SEL_SW_SFPM_Msk (0x7UL) /*!< CSD SW_CMP_P_SEL: SW_SFPM (Bitfield-Mask: 0x07) */ +#define CSD_SW_CMP_P_SEL_SW_SFPT_Pos (4UL) /*!< CSD SW_CMP_P_SEL: SW_SFPT (Bit 4) */ +#define CSD_SW_CMP_P_SEL_SW_SFPT_Msk (0x70UL) /*!< CSD SW_CMP_P_SEL: SW_SFPT (Bitfield-Mask: 0x07) */ +#define CSD_SW_CMP_P_SEL_SW_SFPS_Pos (8UL) /*!< CSD SW_CMP_P_SEL: SW_SFPS (Bit 8) */ +#define CSD_SW_CMP_P_SEL_SW_SFPS_Msk (0x700UL) /*!< CSD SW_CMP_P_SEL: SW_SFPS (Bitfield-Mask: 0x07) */ +#define CSD_SW_CMP_P_SEL_SW_SFMA_Pos (12UL) /*!< CSD SW_CMP_P_SEL: SW_SFMA (Bit 12) */ +#define CSD_SW_CMP_P_SEL_SW_SFMA_Msk (0x1000UL) /*!< CSD SW_CMP_P_SEL: SW_SFMA (Bitfield-Mask: 0x01) */ +#define CSD_SW_CMP_P_SEL_SW_SFMB_Pos (16UL) /*!< CSD SW_CMP_P_SEL: SW_SFMB (Bit 16) */ +#define CSD_SW_CMP_P_SEL_SW_SFMB_Msk (0x10000UL) /*!< CSD SW_CMP_P_SEL: SW_SFMB (Bitfield-Mask: 0x01) */ +#define CSD_SW_CMP_P_SEL_SW_SFCA_Pos (20UL) /*!< CSD SW_CMP_P_SEL: SW_SFCA (Bit 20) */ +#define CSD_SW_CMP_P_SEL_SW_SFCA_Msk (0x100000UL) /*!< CSD SW_CMP_P_SEL: SW_SFCA (Bitfield-Mask: 0x01) */ +#define CSD_SW_CMP_P_SEL_SW_SFCB_Pos (24UL) /*!< CSD SW_CMP_P_SEL: SW_SFCB (Bit 24) */ +#define CSD_SW_CMP_P_SEL_SW_SFCB_Msk (0x1000000UL) /*!< CSD SW_CMP_P_SEL: SW_SFCB (Bitfield-Mask: 0x01) */ +/* =================================================== CSD.SW_CMP_N_SEL ==================================================== */ +#define CSD_SW_CMP_N_SEL_SW_SCRH_Pos (24UL) /*!< CSD SW_CMP_N_SEL: SW_SCRH (Bit 24) */ +#define CSD_SW_CMP_N_SEL_SW_SCRH_Msk (0x7000000UL) /*!< CSD SW_CMP_N_SEL: SW_SCRH (Bitfield-Mask: 0x07) */ +#define CSD_SW_CMP_N_SEL_SW_SCRL_Pos (28UL) /*!< CSD SW_CMP_N_SEL: SW_SCRL (Bit 28) */ +#define CSD_SW_CMP_N_SEL_SW_SCRL_Msk (0x70000000UL) /*!< CSD SW_CMP_N_SEL: SW_SCRL (Bitfield-Mask: 0x07) */ +/* =================================================== CSD.SW_REFGEN_SEL =================================================== */ +#define CSD_SW_REFGEN_SEL_SW_IAIB_Pos (0UL) /*!< CSD SW_REFGEN_SEL: SW_IAIB (Bit 0) */ +#define CSD_SW_REFGEN_SEL_SW_IAIB_Msk (0x1UL) /*!< CSD SW_REFGEN_SEL: SW_IAIB (Bitfield-Mask: 0x01) */ +#define CSD_SW_REFGEN_SEL_SW_IBCB_Pos (4UL) /*!< CSD SW_REFGEN_SEL: SW_IBCB (Bit 4) */ +#define CSD_SW_REFGEN_SEL_SW_IBCB_Msk (0x10UL) /*!< CSD SW_REFGEN_SEL: SW_IBCB (Bitfield-Mask: 0x01) */ +#define CSD_SW_REFGEN_SEL_SW_SGMB_Pos (16UL) /*!< CSD SW_REFGEN_SEL: SW_SGMB (Bit 16) */ +#define CSD_SW_REFGEN_SEL_SW_SGMB_Msk (0x10000UL) /*!< CSD SW_REFGEN_SEL: SW_SGMB (Bitfield-Mask: 0x01) */ +#define CSD_SW_REFGEN_SEL_SW_SGRP_Pos (20UL) /*!< CSD SW_REFGEN_SEL: SW_SGRP (Bit 20) */ +#define CSD_SW_REFGEN_SEL_SW_SGRP_Msk (0x100000UL) /*!< CSD SW_REFGEN_SEL: SW_SGRP (Bitfield-Mask: 0x01) */ +#define CSD_SW_REFGEN_SEL_SW_SGRE_Pos (24UL) /*!< CSD SW_REFGEN_SEL: SW_SGRE (Bit 24) */ +#define CSD_SW_REFGEN_SEL_SW_SGRE_Msk (0x1000000UL) /*!< CSD SW_REFGEN_SEL: SW_SGRE (Bitfield-Mask: 0x01) */ +#define CSD_SW_REFGEN_SEL_SW_SGR_Pos (28UL) /*!< CSD SW_REFGEN_SEL: SW_SGR (Bit 28) */ +#define CSD_SW_REFGEN_SEL_SW_SGR_Msk (0x10000000UL) /*!< CSD SW_REFGEN_SEL: SW_SGR (Bitfield-Mask: 0x01) */ +/* =================================================== CSD.SW_FW_MOD_SEL =================================================== */ +#define CSD_SW_FW_MOD_SEL_SW_F1PM_Pos (0UL) /*!< CSD SW_FW_MOD_SEL: SW_F1PM (Bit 0) */ +#define CSD_SW_FW_MOD_SEL_SW_F1PM_Msk (0x1UL) /*!< CSD SW_FW_MOD_SEL: SW_F1PM (Bitfield-Mask: 0x01) */ +#define CSD_SW_FW_MOD_SEL_SW_F1MA_Pos (8UL) /*!< CSD SW_FW_MOD_SEL: SW_F1MA (Bit 8) */ +#define CSD_SW_FW_MOD_SEL_SW_F1MA_Msk (0x700UL) /*!< CSD SW_FW_MOD_SEL: SW_F1MA (Bitfield-Mask: 0x07) */ +#define CSD_SW_FW_MOD_SEL_SW_F1CA_Pos (16UL) /*!< CSD SW_FW_MOD_SEL: SW_F1CA (Bit 16) */ +#define CSD_SW_FW_MOD_SEL_SW_F1CA_Msk (0x70000UL) /*!< CSD SW_FW_MOD_SEL: SW_F1CA (Bitfield-Mask: 0x07) */ +#define CSD_SW_FW_MOD_SEL_SW_C1CC_Pos (20UL) /*!< CSD SW_FW_MOD_SEL: SW_C1CC (Bit 20) */ +#define CSD_SW_FW_MOD_SEL_SW_C1CC_Msk (0x100000UL) /*!< CSD SW_FW_MOD_SEL: SW_C1CC (Bitfield-Mask: 0x01) */ +#define CSD_SW_FW_MOD_SEL_SW_C1CD_Pos (24UL) /*!< CSD SW_FW_MOD_SEL: SW_C1CD (Bit 24) */ +#define CSD_SW_FW_MOD_SEL_SW_C1CD_Msk (0x1000000UL) /*!< CSD SW_FW_MOD_SEL: SW_C1CD (Bitfield-Mask: 0x01) */ +#define CSD_SW_FW_MOD_SEL_SW_C1F1_Pos (28UL) /*!< CSD SW_FW_MOD_SEL: SW_C1F1 (Bit 28) */ +#define CSD_SW_FW_MOD_SEL_SW_C1F1_Msk (0x10000000UL) /*!< CSD SW_FW_MOD_SEL: SW_C1F1 (Bitfield-Mask: 0x01) */ +/* ================================================== CSD.SW_FW_TANK_SEL =================================================== */ +#define CSD_SW_FW_TANK_SEL_SW_F2PT_Pos (4UL) /*!< CSD SW_FW_TANK_SEL: SW_F2PT (Bit 4) */ +#define CSD_SW_FW_TANK_SEL_SW_F2PT_Msk (0x10UL) /*!< CSD SW_FW_TANK_SEL: SW_F2PT (Bitfield-Mask: 0x01) */ +#define CSD_SW_FW_TANK_SEL_SW_F2MA_Pos (8UL) /*!< CSD SW_FW_TANK_SEL: SW_F2MA (Bit 8) */ +#define CSD_SW_FW_TANK_SEL_SW_F2MA_Msk (0x700UL) /*!< CSD SW_FW_TANK_SEL: SW_F2MA (Bitfield-Mask: 0x07) */ +#define CSD_SW_FW_TANK_SEL_SW_F2CA_Pos (12UL) /*!< CSD SW_FW_TANK_SEL: SW_F2CA (Bit 12) */ +#define CSD_SW_FW_TANK_SEL_SW_F2CA_Msk (0x7000UL) /*!< CSD SW_FW_TANK_SEL: SW_F2CA (Bitfield-Mask: 0x07) */ +#define CSD_SW_FW_TANK_SEL_SW_F2CB_Pos (16UL) /*!< CSD SW_FW_TANK_SEL: SW_F2CB (Bit 16) */ +#define CSD_SW_FW_TANK_SEL_SW_F2CB_Msk (0x70000UL) /*!< CSD SW_FW_TANK_SEL: SW_F2CB (Bitfield-Mask: 0x07) */ +#define CSD_SW_FW_TANK_SEL_SW_C2CC_Pos (20UL) /*!< CSD SW_FW_TANK_SEL: SW_C2CC (Bit 20) */ +#define CSD_SW_FW_TANK_SEL_SW_C2CC_Msk (0x100000UL) /*!< CSD SW_FW_TANK_SEL: SW_C2CC (Bitfield-Mask: 0x01) */ +#define CSD_SW_FW_TANK_SEL_SW_C2CD_Pos (24UL) /*!< CSD SW_FW_TANK_SEL: SW_C2CD (Bit 24) */ +#define CSD_SW_FW_TANK_SEL_SW_C2CD_Msk (0x1000000UL) /*!< CSD SW_FW_TANK_SEL: SW_C2CD (Bitfield-Mask: 0x01) */ +#define CSD_SW_FW_TANK_SEL_SW_C2F2_Pos (28UL) /*!< CSD SW_FW_TANK_SEL: SW_C2F2 (Bit 28) */ +#define CSD_SW_FW_TANK_SEL_SW_C2F2_Msk (0x10000000UL) /*!< CSD SW_FW_TANK_SEL: SW_C2F2 (Bitfield-Mask: 0x01) */ +/* ==================================================== CSD.SW_DSI_SEL ===================================================== */ +#define CSD_SW_DSI_SEL_DSI_CSH_TANK_Pos (0UL) /*!< CSD SW_DSI_SEL: DSI_CSH_TANK (Bit 0) */ +#define CSD_SW_DSI_SEL_DSI_CSH_TANK_Msk (0xfUL) /*!< CSD SW_DSI_SEL: DSI_CSH_TANK (Bitfield-Mask: 0x0f) */ +#define CSD_SW_DSI_SEL_DSI_CMOD_Pos (4UL) /*!< CSD SW_DSI_SEL: DSI_CMOD (Bit 4) */ +#define CSD_SW_DSI_SEL_DSI_CMOD_Msk (0xf0UL) /*!< CSD SW_DSI_SEL: DSI_CMOD (Bitfield-Mask: 0x0f) */ +/* ====================================================== CSD.IO_SEL ======================================================= */ +#define CSD_IO_SEL_CSD_TX_OUT_Pos (0UL) /*!< CSD IO_SEL: CSD_TX_OUT (Bit 0) */ +#define CSD_IO_SEL_CSD_TX_OUT_Msk (0xfUL) /*!< CSD IO_SEL: CSD_TX_OUT (Bitfield-Mask: 0x0f) */ +#define CSD_IO_SEL_CSD_TX_OUT_EN_Pos (4UL) /*!< CSD IO_SEL: CSD_TX_OUT_EN (Bit 4) */ +#define CSD_IO_SEL_CSD_TX_OUT_EN_Msk (0xf0UL) /*!< CSD IO_SEL: CSD_TX_OUT_EN (Bitfield-Mask: 0x0f) */ +#define CSD_IO_SEL_CSD_TX_AMUXB_EN_Pos (12UL) /*!< CSD IO_SEL: CSD_TX_AMUXB_EN (Bit 12) */ +#define CSD_IO_SEL_CSD_TX_AMUXB_EN_Msk (0xf000UL) /*!< CSD IO_SEL: CSD_TX_AMUXB_EN (Bitfield-Mask: 0x0f) */ +#define CSD_IO_SEL_CSD_TX_N_OUT_Pos (16UL) /*!< CSD IO_SEL: CSD_TX_N_OUT (Bit 16) */ +#define CSD_IO_SEL_CSD_TX_N_OUT_Msk (0xf0000UL) /*!< CSD IO_SEL: CSD_TX_N_OUT (Bitfield-Mask: 0x0f) */ +#define CSD_IO_SEL_CSD_TX_N_OUT_EN_Pos (20UL) /*!< CSD IO_SEL: CSD_TX_N_OUT_EN (Bit 20) */ +#define CSD_IO_SEL_CSD_TX_N_OUT_EN_Msk (0xf00000UL) /*!< CSD IO_SEL: CSD_TX_N_OUT_EN (Bitfield-Mask: 0x0f) */ +#define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Pos (24UL) /*!< CSD IO_SEL: CSD_TX_N_AMUXA_EN (Bit 24) */ +#define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Msk (0xf000000UL) /*!< CSD IO_SEL: CSD_TX_N_AMUXA_EN (Bitfield-Mask: 0x0f) */ +/* ===================================================== CSD.SEQ_TIME ====================================================== */ +#define CSD_SEQ_TIME_AZ_TIME_Pos (0UL) /*!< CSD SEQ_TIME: AZ_TIME (Bit 0) */ +#define CSD_SEQ_TIME_AZ_TIME_Msk (0xffUL) /*!< CSD SEQ_TIME: AZ_TIME (Bitfield-Mask: 0xff) */ +/* =================================================== CSD.SEQ_INIT_CNT ==================================================== */ +#define CSD_SEQ_INIT_CNT_CONV_CNT_Pos (0UL) /*!< CSD SEQ_INIT_CNT: CONV_CNT (Bit 0) */ +#define CSD_SEQ_INIT_CNT_CONV_CNT_Msk (0xffffUL) /*!< CSD SEQ_INIT_CNT: CONV_CNT (Bitfield-Mask: 0xffff) */ +/* =================================================== CSD.SEQ_NORM_CNT ==================================================== */ +#define CSD_SEQ_NORM_CNT_CONV_CNT_Pos (0UL) /*!< CSD SEQ_NORM_CNT: CONV_CNT (Bit 0) */ +#define CSD_SEQ_NORM_CNT_CONV_CNT_Msk (0xffffUL) /*!< CSD SEQ_NORM_CNT: CONV_CNT (Bitfield-Mask: 0xffff) */ +/* ====================================================== CSD.ADC_CTL ====================================================== */ +#define CSD_ADC_CTL_ADC_TIME_Pos (0UL) /*!< CSD ADC_CTL: ADC_TIME (Bit 0) */ +#define CSD_ADC_CTL_ADC_TIME_Msk (0xffUL) /*!< CSD ADC_CTL: ADC_TIME (Bitfield-Mask: 0xff) */ +#define CSD_ADC_CTL_ADC_MODE_Pos (16UL) /*!< CSD ADC_CTL: ADC_MODE (Bit 16) */ +#define CSD_ADC_CTL_ADC_MODE_Msk (0x30000UL) /*!< CSD ADC_CTL: ADC_MODE (Bitfield-Mask: 0x03) */ +/* ===================================================== CSD.SEQ_START ===================================================== */ +#define CSD_SEQ_START_START_Pos (0UL) /*!< CSD SEQ_START: START (Bit 0) */ +#define CSD_SEQ_START_START_Msk (0x1UL) /*!< CSD SEQ_START: START (Bitfield-Mask: 0x01) */ +#define CSD_SEQ_START_SEQ_MODE_Pos (1UL) /*!< CSD SEQ_START: SEQ_MODE (Bit 1) */ +#define CSD_SEQ_START_SEQ_MODE_Msk (0x2UL) /*!< CSD SEQ_START: SEQ_MODE (Bitfield-Mask: 0x01) */ +#define CSD_SEQ_START_ABORT_Pos (3UL) /*!< CSD SEQ_START: ABORT (Bit 3) */ +#define CSD_SEQ_START_ABORT_Msk (0x8UL) /*!< CSD SEQ_START: ABORT (Bitfield-Mask: 0x01) */ +#define CSD_SEQ_START_DSI_START_EN_Pos (4UL) /*!< CSD SEQ_START: DSI_START_EN (Bit 4) */ +#define CSD_SEQ_START_DSI_START_EN_Msk (0x10UL) /*!< CSD SEQ_START: DSI_START_EN (Bitfield-Mask: 0x01) */ +#define CSD_SEQ_START_AZ0_SKIP_Pos (8UL) /*!< CSD SEQ_START: AZ0_SKIP (Bit 8) */ +#define CSD_SEQ_START_AZ0_SKIP_Msk (0x100UL) /*!< CSD SEQ_START: AZ0_SKIP (Bitfield-Mask: 0x01) */ +#define CSD_SEQ_START_AZ1_SKIP_Pos (9UL) /*!< CSD SEQ_START: AZ1_SKIP (Bit 9) */ +#define CSD_SEQ_START_AZ1_SKIP_Msk (0x200UL) /*!< CSD SEQ_START: AZ1_SKIP (Bitfield-Mask: 0x01) */ +/* ======================================================= CSD.IDACA ======================================================= */ +#define CSD_IDACA_VAL_Pos (0UL) /*!< CSD IDACA: VAL (Bit 0) */ +#define CSD_IDACA_VAL_Msk (0x7fUL) /*!< CSD IDACA: VAL (Bitfield-Mask: 0x7f) */ +#define CSD_IDACA_POL_DYN_Pos (7UL) /*!< CSD IDACA: POL_DYN (Bit 7) */ +#define CSD_IDACA_POL_DYN_Msk (0x80UL) /*!< CSD IDACA: POL_DYN (Bitfield-Mask: 0x01) */ +#define CSD_IDACA_POLARITY_Pos (8UL) /*!< CSD IDACA: POLARITY (Bit 8) */ +#define CSD_IDACA_POLARITY_Msk (0x300UL) /*!< CSD IDACA: POLARITY (Bitfield-Mask: 0x03) */ +#define CSD_IDACA_BAL_MODE_Pos (10UL) /*!< CSD IDACA: BAL_MODE (Bit 10) */ +#define CSD_IDACA_BAL_MODE_Msk (0xc00UL) /*!< CSD IDACA: BAL_MODE (Bitfield-Mask: 0x03) */ +#define CSD_IDACA_LEG1_MODE_Pos (16UL) /*!< CSD IDACA: LEG1_MODE (Bit 16) */ +#define CSD_IDACA_LEG1_MODE_Msk (0x30000UL) /*!< CSD IDACA: LEG1_MODE (Bitfield-Mask: 0x03) */ +#define CSD_IDACA_LEG2_MODE_Pos (18UL) /*!< CSD IDACA: LEG2_MODE (Bit 18) */ +#define CSD_IDACA_LEG2_MODE_Msk (0xc0000UL) /*!< CSD IDACA: LEG2_MODE (Bitfield-Mask: 0x03) */ +#define CSD_IDACA_DSI_CTRL_EN_Pos (21UL) /*!< CSD IDACA: DSI_CTRL_EN (Bit 21) */ +#define CSD_IDACA_DSI_CTRL_EN_Msk (0x200000UL) /*!< CSD IDACA: DSI_CTRL_EN (Bitfield-Mask: 0x01) */ +#define CSD_IDACA_RANGE_Pos (22UL) /*!< CSD IDACA: RANGE (Bit 22) */ +#define CSD_IDACA_RANGE_Msk (0xc00000UL) /*!< CSD IDACA: RANGE (Bitfield-Mask: 0x03) */ +#define CSD_IDACA_LEG1_EN_Pos (24UL) /*!< CSD IDACA: LEG1_EN (Bit 24) */ +#define CSD_IDACA_LEG1_EN_Msk (0x1000000UL) /*!< CSD IDACA: LEG1_EN (Bitfield-Mask: 0x01) */ +#define CSD_IDACA_LEG2_EN_Pos (25UL) /*!< CSD IDACA: LEG2_EN (Bit 25) */ +#define CSD_IDACA_LEG2_EN_Msk (0x2000000UL) /*!< CSD IDACA: LEG2_EN (Bitfield-Mask: 0x01) */ +/* ======================================================= CSD.IDACB ======================================================= */ +#define CSD_IDACB_VAL_Pos (0UL) /*!< CSD IDACB: VAL (Bit 0) */ +#define CSD_IDACB_VAL_Msk (0x7fUL) /*!< CSD IDACB: VAL (Bitfield-Mask: 0x7f) */ +#define CSD_IDACB_POL_DYN_Pos (7UL) /*!< CSD IDACB: POL_DYN (Bit 7) */ +#define CSD_IDACB_POL_DYN_Msk (0x80UL) /*!< CSD IDACB: POL_DYN (Bitfield-Mask: 0x01) */ +#define CSD_IDACB_POLARITY_Pos (8UL) /*!< CSD IDACB: POLARITY (Bit 8) */ +#define CSD_IDACB_POLARITY_Msk (0x300UL) /*!< CSD IDACB: POLARITY (Bitfield-Mask: 0x03) */ +#define CSD_IDACB_BAL_MODE_Pos (10UL) /*!< CSD IDACB: BAL_MODE (Bit 10) */ +#define CSD_IDACB_BAL_MODE_Msk (0xc00UL) /*!< CSD IDACB: BAL_MODE (Bitfield-Mask: 0x03) */ +#define CSD_IDACB_LEG1_MODE_Pos (16UL) /*!< CSD IDACB: LEG1_MODE (Bit 16) */ +#define CSD_IDACB_LEG1_MODE_Msk (0x30000UL) /*!< CSD IDACB: LEG1_MODE (Bitfield-Mask: 0x03) */ +#define CSD_IDACB_LEG2_MODE_Pos (18UL) /*!< CSD IDACB: LEG2_MODE (Bit 18) */ +#define CSD_IDACB_LEG2_MODE_Msk (0xc0000UL) /*!< CSD IDACB: LEG2_MODE (Bitfield-Mask: 0x03) */ +#define CSD_IDACB_DSI_CTRL_EN_Pos (21UL) /*!< CSD IDACB: DSI_CTRL_EN (Bit 21) */ +#define CSD_IDACB_DSI_CTRL_EN_Msk (0x200000UL) /*!< CSD IDACB: DSI_CTRL_EN (Bitfield-Mask: 0x01) */ +#define CSD_IDACB_RANGE_Pos (22UL) /*!< CSD IDACB: RANGE (Bit 22) */ +#define CSD_IDACB_RANGE_Msk (0xc00000UL) /*!< CSD IDACB: RANGE (Bitfield-Mask: 0x03) */ +#define CSD_IDACB_LEG1_EN_Pos (24UL) /*!< CSD IDACB: LEG1_EN (Bit 24) */ +#define CSD_IDACB_LEG1_EN_Msk (0x1000000UL) /*!< CSD IDACB: LEG1_EN (Bitfield-Mask: 0x01) */ +#define CSD_IDACB_LEG2_EN_Pos (25UL) /*!< CSD IDACB: LEG2_EN (Bit 25) */ +#define CSD_IDACB_LEG2_EN_Msk (0x2000000UL) /*!< CSD IDACB: LEG2_EN (Bitfield-Mask: 0x01) */ +#define CSD_IDACB_LEG3_EN_Pos (26UL) /*!< CSD IDACB: LEG3_EN (Bit 26) */ +#define CSD_IDACB_LEG3_EN_Msk (0x4000000UL) /*!< CSD IDACB: LEG3_EN (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_CSD_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ctbm.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ctbm.h new file mode 100644 index 0000000000..cca584cc15 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ctbm.h @@ -0,0 +1,287 @@ +/***************************************************************************//** +* \file cyip_ctbm.h +* +* \brief +* CTBM IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_CTBM_H_ +#define _CYIP_CTBM_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ CTBM ================ */ +/* =========================================================================================================================== */ + +#define CTBM_SECTION_SIZE 0x00010000UL + +/** + * \brief Continuous Time Block Mini (CTBM) + */ +typedef struct { /*!< CTBM Structure */ + __IOM uint32_t CTB_CTRL; /*!< 0x00000000 global CTB and power control */ + __IOM uint32_t OA_RES0_CTRL; /*!< 0x00000004 Opamp0 and resistor0 control */ + __IOM uint32_t OA_RES1_CTRL; /*!< 0x00000008 Opamp1 and resistor1 control */ + __IM uint32_t COMP_STAT; /*!< 0x0000000C Comparator status */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */ + __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */ + __IM uint32_t RESERVED1[20]; + __IOM uint32_t OA0_SW; /*!< 0x00000080 Opamp0 switch control */ + __IOM uint32_t OA0_SW_CLEAR; /*!< 0x00000084 Opamp0 switch control clear */ + __IOM uint32_t OA1_SW; /*!< 0x00000088 Opamp1 switch control */ + __IOM uint32_t OA1_SW_CLEAR; /*!< 0x0000008C Opamp1 switch control clear */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t CTD_SW; /*!< 0x000000A0 CTDAC connection switch control */ + __IOM uint32_t CTD_SW_CLEAR; /*!< 0x000000A4 CTDAC connection switch control clear */ + __IM uint32_t RESERVED3[6]; + __IOM uint32_t CTB_SW_DS_CTRL; /*!< 0x000000C0 CTB bus switch control */ + __IOM uint32_t CTB_SW_SQ_CTRL; /*!< 0x000000C4 CTB bus switch Sar Sequencer control */ + __IM uint32_t CTB_SW_STATUS; /*!< 0x000000C8 CTB bus switch control status */ + __IM uint32_t RESERVED4[909]; + __IOM uint32_t OA0_OFFSET_TRIM; /*!< 0x00000F00 Opamp0 trim control */ + __IOM uint32_t OA0_SLOPE_OFFSET_TRIM; /*!< 0x00000F04 Opamp0 trim control */ + __IOM uint32_t OA0_COMP_TRIM; /*!< 0x00000F08 Opamp0 trim control */ + __IOM uint32_t OA1_OFFSET_TRIM; /*!< 0x00000F0C Opamp1 trim control */ + __IOM uint32_t OA1_SLOPE_OFFSET_TRIM; /*!< 0x00000F10 Opamp1 trim control */ + __IOM uint32_t OA1_COMP_TRIM; /*!< 0x00000F14 Opamp1 trim control */ +} CTBM_Type; /*!< Size = 3864 (0xF18) */ + + +/* ===================================================== CTBM.CTB_CTRL ===================================================== */ +#define CTBM_CTB_CTRL_DEEPSLEEP_ON_Pos (30UL) /*!< CTBM CTB_CTRL: DEEPSLEEP_ON (Bit 30) */ +#define CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk (0x40000000UL) /*!< CTBM CTB_CTRL: DEEPSLEEP_ON (Bitfield-Mask: 0x01) */ +#define CTBM_CTB_CTRL_ENABLED_Pos (31UL) /*!< CTBM CTB_CTRL: ENABLED (Bit 31) */ +#define CTBM_CTB_CTRL_ENABLED_Msk (0x80000000UL) /*!< CTBM CTB_CTRL: ENABLED (Bitfield-Mask: 0x01) */ +/* =================================================== CTBM.OA_RES0_CTRL =================================================== */ +#define CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Pos (0UL) /*!< CTBM OA_RES0_CTRL: OA0_PWR_MODE (Bit 0) */ +#define CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Msk (0x7UL) /*!< CTBM OA_RES0_CTRL: OA0_PWR_MODE (Bitfield-Mask: 0x07) */ +#define CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos (3UL) /*!< CTBM OA_RES0_CTRL: OA0_DRIVE_STR_SEL (Bit 3) */ +#define CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk (0x8UL) /*!< CTBM OA_RES0_CTRL: OA0_DRIVE_STR_SEL (Bitfield-Mask: 0x01)*/ +#define CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos (4UL) /*!< CTBM OA_RES0_CTRL: OA0_COMP_EN (Bit 4) */ +#define CTBM_OA_RES0_CTRL_OA0_COMP_EN_Msk (0x10UL) /*!< CTBM OA_RES0_CTRL: OA0_COMP_EN (Bitfield-Mask: 0x01) */ +#define CTBM_OA_RES0_CTRL_OA0_HYST_EN_Pos (5UL) /*!< CTBM OA_RES0_CTRL: OA0_HYST_EN (Bit 5) */ +#define CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk (0x20UL) /*!< CTBM OA_RES0_CTRL: OA0_HYST_EN (Bitfield-Mask: 0x01) */ +#define CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Pos (6UL) /*!< CTBM OA_RES0_CTRL: OA0_BYPASS_DSI_SYNC (Bit 6) */ +#define CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk (0x40UL) /*!< CTBM OA_RES0_CTRL: OA0_BYPASS_DSI_SYNC (Bitfield-Mask: 0x01)*/ +#define CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Pos (7UL) /*!< CTBM OA_RES0_CTRL: OA0_DSI_LEVEL (Bit 7) */ +#define CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk (0x80UL) /*!< CTBM OA_RES0_CTRL: OA0_DSI_LEVEL (Bitfield-Mask: 0x01) */ +#define CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos (8UL) /*!< CTBM OA_RES0_CTRL: OA0_COMPINT (Bit 8) */ +#define CTBM_OA_RES0_CTRL_OA0_COMPINT_Msk (0x300UL) /*!< CTBM OA_RES0_CTRL: OA0_COMPINT (Bitfield-Mask: 0x03) */ +#define CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Pos (11UL) /*!< CTBM OA_RES0_CTRL: OA0_PUMP_EN (Bit 11) */ +#define CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk (0x800UL) /*!< CTBM OA_RES0_CTRL: OA0_PUMP_EN (Bitfield-Mask: 0x01) */ +#define CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Pos (12UL) /*!< CTBM OA_RES0_CTRL: OA0_BOOST_EN (Bit 12) */ +#define CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk (0x1000UL) /*!< CTBM OA_RES0_CTRL: OA0_BOOST_EN (Bitfield-Mask: 0x01) */ +/* =================================================== CTBM.OA_RES1_CTRL =================================================== */ +#define CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Pos (0UL) /*!< CTBM OA_RES1_CTRL: OA1_PWR_MODE (Bit 0) */ +#define CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Msk (0x7UL) /*!< CTBM OA_RES1_CTRL: OA1_PWR_MODE (Bitfield-Mask: 0x07) */ +#define CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Pos (3UL) /*!< CTBM OA_RES1_CTRL: OA1_DRIVE_STR_SEL (Bit 3) */ +#define CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk (0x8UL) /*!< CTBM OA_RES1_CTRL: OA1_DRIVE_STR_SEL (Bitfield-Mask: 0x01)*/ +#define CTBM_OA_RES1_CTRL_OA1_COMP_EN_Pos (4UL) /*!< CTBM OA_RES1_CTRL: OA1_COMP_EN (Bit 4) */ +#define CTBM_OA_RES1_CTRL_OA1_COMP_EN_Msk (0x10UL) /*!< CTBM OA_RES1_CTRL: OA1_COMP_EN (Bitfield-Mask: 0x01) */ +#define CTBM_OA_RES1_CTRL_OA1_HYST_EN_Pos (5UL) /*!< CTBM OA_RES1_CTRL: OA1_HYST_EN (Bit 5) */ +#define CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk (0x20UL) /*!< CTBM OA_RES1_CTRL: OA1_HYST_EN (Bitfield-Mask: 0x01) */ +#define CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Pos (6UL) /*!< CTBM OA_RES1_CTRL: OA1_BYPASS_DSI_SYNC (Bit 6) */ +#define CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk (0x40UL) /*!< CTBM OA_RES1_CTRL: OA1_BYPASS_DSI_SYNC (Bitfield-Mask: 0x01)*/ +#define CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Pos (7UL) /*!< CTBM OA_RES1_CTRL: OA1_DSI_LEVEL (Bit 7) */ +#define CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk (0x80UL) /*!< CTBM OA_RES1_CTRL: OA1_DSI_LEVEL (Bitfield-Mask: 0x01) */ +#define CTBM_OA_RES1_CTRL_OA1_COMPINT_Pos (8UL) /*!< CTBM OA_RES1_CTRL: OA1_COMPINT (Bit 8) */ +#define CTBM_OA_RES1_CTRL_OA1_COMPINT_Msk (0x300UL) /*!< CTBM OA_RES1_CTRL: OA1_COMPINT (Bitfield-Mask: 0x03) */ +#define CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Pos (11UL) /*!< CTBM OA_RES1_CTRL: OA1_PUMP_EN (Bit 11) */ +#define CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk (0x800UL) /*!< CTBM OA_RES1_CTRL: OA1_PUMP_EN (Bitfield-Mask: 0x01) */ +#define CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Pos (12UL) /*!< CTBM OA_RES1_CTRL: OA1_BOOST_EN (Bit 12) */ +#define CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Msk (0x1000UL) /*!< CTBM OA_RES1_CTRL: OA1_BOOST_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== CTBM.COMP_STAT ===================================================== */ +#define CTBM_COMP_STAT_OA0_COMP_Pos (0UL) /*!< CTBM COMP_STAT: OA0_COMP (Bit 0) */ +#define CTBM_COMP_STAT_OA0_COMP_Msk (0x1UL) /*!< CTBM COMP_STAT: OA0_COMP (Bitfield-Mask: 0x01) */ +#define CTBM_COMP_STAT_OA1_COMP_Pos (16UL) /*!< CTBM COMP_STAT: OA1_COMP (Bit 16) */ +#define CTBM_COMP_STAT_OA1_COMP_Msk (0x10000UL) /*!< CTBM COMP_STAT: OA1_COMP (Bitfield-Mask: 0x01) */ +/* ======================================================= CTBM.INTR ======================================================= */ +#define CTBM_INTR_COMP0_Pos (0UL) /*!< CTBM INTR: COMP0 (Bit 0) */ +#define CTBM_INTR_COMP0_Msk (0x1UL) /*!< CTBM INTR: COMP0 (Bitfield-Mask: 0x01) */ +#define CTBM_INTR_COMP1_Pos (1UL) /*!< CTBM INTR: COMP1 (Bit 1) */ +#define CTBM_INTR_COMP1_Msk (0x2UL) /*!< CTBM INTR: COMP1 (Bitfield-Mask: 0x01) */ +/* ===================================================== CTBM.INTR_SET ===================================================== */ +#define CTBM_INTR_SET_COMP0_SET_Pos (0UL) /*!< CTBM INTR_SET: COMP0_SET (Bit 0) */ +#define CTBM_INTR_SET_COMP0_SET_Msk (0x1UL) /*!< CTBM INTR_SET: COMP0_SET (Bitfield-Mask: 0x01) */ +#define CTBM_INTR_SET_COMP1_SET_Pos (1UL) /*!< CTBM INTR_SET: COMP1_SET (Bit 1) */ +#define CTBM_INTR_SET_COMP1_SET_Msk (0x2UL) /*!< CTBM INTR_SET: COMP1_SET (Bitfield-Mask: 0x01) */ +/* ==================================================== CTBM.INTR_MASK ===================================================== */ +#define CTBM_INTR_MASK_COMP0_MASK_Pos (0UL) /*!< CTBM INTR_MASK: COMP0_MASK (Bit 0) */ +#define CTBM_INTR_MASK_COMP0_MASK_Msk (0x1UL) /*!< CTBM INTR_MASK: COMP0_MASK (Bitfield-Mask: 0x01) */ +#define CTBM_INTR_MASK_COMP1_MASK_Pos (1UL) /*!< CTBM INTR_MASK: COMP1_MASK (Bit 1) */ +#define CTBM_INTR_MASK_COMP1_MASK_Msk (0x2UL) /*!< CTBM INTR_MASK: COMP1_MASK (Bitfield-Mask: 0x01) */ +/* =================================================== CTBM.INTR_MASKED ==================================================== */ +#define CTBM_INTR_MASKED_COMP0_MASKED_Pos (0UL) /*!< CTBM INTR_MASKED: COMP0_MASKED (Bit 0) */ +#define CTBM_INTR_MASKED_COMP0_MASKED_Msk (0x1UL) /*!< CTBM INTR_MASKED: COMP0_MASKED (Bitfield-Mask: 0x01) */ +#define CTBM_INTR_MASKED_COMP1_MASKED_Pos (1UL) /*!< CTBM INTR_MASKED: COMP1_MASKED (Bit 1) */ +#define CTBM_INTR_MASKED_COMP1_MASKED_Msk (0x2UL) /*!< CTBM INTR_MASKED: COMP1_MASKED (Bitfield-Mask: 0x01) */ +/* ====================================================== CTBM.OA0_SW ====================================================== */ +#define CTBM_OA0_SW_OA0P_A00_Pos (0UL) /*!< CTBM OA0_SW: OA0P_A00 (Bit 0) */ +#define CTBM_OA0_SW_OA0P_A00_Msk (0x1UL) /*!< CTBM OA0_SW: OA0P_A00 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_OA0P_A20_Pos (2UL) /*!< CTBM OA0_SW: OA0P_A20 (Bit 2) */ +#define CTBM_OA0_SW_OA0P_A20_Msk (0x4UL) /*!< CTBM OA0_SW: OA0P_A20 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_OA0P_A30_Pos (3UL) /*!< CTBM OA0_SW: OA0P_A30 (Bit 3) */ +#define CTBM_OA0_SW_OA0P_A30_Msk (0x8UL) /*!< CTBM OA0_SW: OA0P_A30 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_OA0M_A11_Pos (8UL) /*!< CTBM OA0_SW: OA0M_A11 (Bit 8) */ +#define CTBM_OA0_SW_OA0M_A11_Msk (0x100UL) /*!< CTBM OA0_SW: OA0M_A11 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_OA0M_A81_Pos (14UL) /*!< CTBM OA0_SW: OA0M_A81 (Bit 14) */ +#define CTBM_OA0_SW_OA0M_A81_Msk (0x4000UL) /*!< CTBM OA0_SW: OA0M_A81 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_OA0O_D51_Pos (18UL) /*!< CTBM OA0_SW: OA0O_D51 (Bit 18) */ +#define CTBM_OA0_SW_OA0O_D51_Msk (0x40000UL) /*!< CTBM OA0_SW: OA0O_D51 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_OA0O_D81_Pos (21UL) /*!< CTBM OA0_SW: OA0O_D81 (Bit 21) */ +#define CTBM_OA0_SW_OA0O_D81_Msk (0x200000UL) /*!< CTBM OA0_SW: OA0O_D81 (Bitfield-Mask: 0x01) */ +/* =================================================== CTBM.OA0_SW_CLEAR =================================================== */ +#define CTBM_OA0_SW_CLEAR_OA0P_A00_Pos (0UL) /*!< CTBM OA0_SW_CLEAR: OA0P_A00 (Bit 0) */ +#define CTBM_OA0_SW_CLEAR_OA0P_A00_Msk (0x1UL) /*!< CTBM OA0_SW_CLEAR: OA0P_A00 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_CLEAR_OA0P_A20_Pos (2UL) /*!< CTBM OA0_SW_CLEAR: OA0P_A20 (Bit 2) */ +#define CTBM_OA0_SW_CLEAR_OA0P_A20_Msk (0x4UL) /*!< CTBM OA0_SW_CLEAR: OA0P_A20 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_CLEAR_OA0P_A30_Pos (3UL) /*!< CTBM OA0_SW_CLEAR: OA0P_A30 (Bit 3) */ +#define CTBM_OA0_SW_CLEAR_OA0P_A30_Msk (0x8UL) /*!< CTBM OA0_SW_CLEAR: OA0P_A30 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_CLEAR_OA0M_A11_Pos (8UL) /*!< CTBM OA0_SW_CLEAR: OA0M_A11 (Bit 8) */ +#define CTBM_OA0_SW_CLEAR_OA0M_A11_Msk (0x100UL) /*!< CTBM OA0_SW_CLEAR: OA0M_A11 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_CLEAR_OA0M_A81_Pos (14UL) /*!< CTBM OA0_SW_CLEAR: OA0M_A81 (Bit 14) */ +#define CTBM_OA0_SW_CLEAR_OA0M_A81_Msk (0x4000UL) /*!< CTBM OA0_SW_CLEAR: OA0M_A81 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_CLEAR_OA0O_D51_Pos (18UL) /*!< CTBM OA0_SW_CLEAR: OA0O_D51 (Bit 18) */ +#define CTBM_OA0_SW_CLEAR_OA0O_D51_Msk (0x40000UL) /*!< CTBM OA0_SW_CLEAR: OA0O_D51 (Bitfield-Mask: 0x01) */ +#define CTBM_OA0_SW_CLEAR_OA0O_D81_Pos (21UL) /*!< CTBM OA0_SW_CLEAR: OA0O_D81 (Bit 21) */ +#define CTBM_OA0_SW_CLEAR_OA0O_D81_Msk (0x200000UL) /*!< CTBM OA0_SW_CLEAR: OA0O_D81 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTBM.OA1_SW ====================================================== */ +#define CTBM_OA1_SW_OA1P_A03_Pos (0UL) /*!< CTBM OA1_SW: OA1P_A03 (Bit 0) */ +#define CTBM_OA1_SW_OA1P_A03_Msk (0x1UL) /*!< CTBM OA1_SW: OA1P_A03 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_OA1P_A13_Pos (1UL) /*!< CTBM OA1_SW: OA1P_A13 (Bit 1) */ +#define CTBM_OA1_SW_OA1P_A13_Msk (0x2UL) /*!< CTBM OA1_SW: OA1P_A13 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_OA1P_A43_Pos (4UL) /*!< CTBM OA1_SW: OA1P_A43 (Bit 4) */ +#define CTBM_OA1_SW_OA1P_A43_Msk (0x10UL) /*!< CTBM OA1_SW: OA1P_A43 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_OA1P_A73_Pos (7UL) /*!< CTBM OA1_SW: OA1P_A73 (Bit 7) */ +#define CTBM_OA1_SW_OA1P_A73_Msk (0x80UL) /*!< CTBM OA1_SW: OA1P_A73 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_OA1M_A22_Pos (8UL) /*!< CTBM OA1_SW: OA1M_A22 (Bit 8) */ +#define CTBM_OA1_SW_OA1M_A22_Msk (0x100UL) /*!< CTBM OA1_SW: OA1M_A22 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_OA1M_A82_Pos (14UL) /*!< CTBM OA1_SW: OA1M_A82 (Bit 14) */ +#define CTBM_OA1_SW_OA1M_A82_Msk (0x4000UL) /*!< CTBM OA1_SW: OA1M_A82 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_OA1O_D52_Pos (18UL) /*!< CTBM OA1_SW: OA1O_D52 (Bit 18) */ +#define CTBM_OA1_SW_OA1O_D52_Msk (0x40000UL) /*!< CTBM OA1_SW: OA1O_D52 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_OA1O_D62_Pos (19UL) /*!< CTBM OA1_SW: OA1O_D62 (Bit 19) */ +#define CTBM_OA1_SW_OA1O_D62_Msk (0x80000UL) /*!< CTBM OA1_SW: OA1O_D62 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_OA1O_D82_Pos (21UL) /*!< CTBM OA1_SW: OA1O_D82 (Bit 21) */ +#define CTBM_OA1_SW_OA1O_D82_Msk (0x200000UL) /*!< CTBM OA1_SW: OA1O_D82 (Bitfield-Mask: 0x01) */ +/* =================================================== CTBM.OA1_SW_CLEAR =================================================== */ +#define CTBM_OA1_SW_CLEAR_OA1P_A03_Pos (0UL) /*!< CTBM OA1_SW_CLEAR: OA1P_A03 (Bit 0) */ +#define CTBM_OA1_SW_CLEAR_OA1P_A03_Msk (0x1UL) /*!< CTBM OA1_SW_CLEAR: OA1P_A03 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_CLEAR_OA1P_A13_Pos (1UL) /*!< CTBM OA1_SW_CLEAR: OA1P_A13 (Bit 1) */ +#define CTBM_OA1_SW_CLEAR_OA1P_A13_Msk (0x2UL) /*!< CTBM OA1_SW_CLEAR: OA1P_A13 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_CLEAR_OA1P_A43_Pos (4UL) /*!< CTBM OA1_SW_CLEAR: OA1P_A43 (Bit 4) */ +#define CTBM_OA1_SW_CLEAR_OA1P_A43_Msk (0x10UL) /*!< CTBM OA1_SW_CLEAR: OA1P_A43 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_CLEAR_OA1P_A73_Pos (7UL) /*!< CTBM OA1_SW_CLEAR: OA1P_A73 (Bit 7) */ +#define CTBM_OA1_SW_CLEAR_OA1P_A73_Msk (0x80UL) /*!< CTBM OA1_SW_CLEAR: OA1P_A73 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_CLEAR_OA1M_A22_Pos (8UL) /*!< CTBM OA1_SW_CLEAR: OA1M_A22 (Bit 8) */ +#define CTBM_OA1_SW_CLEAR_OA1M_A22_Msk (0x100UL) /*!< CTBM OA1_SW_CLEAR: OA1M_A22 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_CLEAR_OA1M_A82_Pos (14UL) /*!< CTBM OA1_SW_CLEAR: OA1M_A82 (Bit 14) */ +#define CTBM_OA1_SW_CLEAR_OA1M_A82_Msk (0x4000UL) /*!< CTBM OA1_SW_CLEAR: OA1M_A82 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_CLEAR_OA1O_D52_Pos (18UL) /*!< CTBM OA1_SW_CLEAR: OA1O_D52 (Bit 18) */ +#define CTBM_OA1_SW_CLEAR_OA1O_D52_Msk (0x40000UL) /*!< CTBM OA1_SW_CLEAR: OA1O_D52 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_CLEAR_OA1O_D62_Pos (19UL) /*!< CTBM OA1_SW_CLEAR: OA1O_D62 (Bit 19) */ +#define CTBM_OA1_SW_CLEAR_OA1O_D62_Msk (0x80000UL) /*!< CTBM OA1_SW_CLEAR: OA1O_D62 (Bitfield-Mask: 0x01) */ +#define CTBM_OA1_SW_CLEAR_OA1O_D82_Pos (21UL) /*!< CTBM OA1_SW_CLEAR: OA1O_D82 (Bit 21) */ +#define CTBM_OA1_SW_CLEAR_OA1O_D82_Msk (0x200000UL) /*!< CTBM OA1_SW_CLEAR: OA1O_D82 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTBM.CTD_SW ====================================================== */ +#define CTBM_CTD_SW_CTDD_CRD_Pos (1UL) /*!< CTBM CTD_SW: CTDD_CRD (Bit 1) */ +#define CTBM_CTD_SW_CTDD_CRD_Msk (0x2UL) /*!< CTBM CTD_SW: CTDD_CRD (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CTDS_CRS_Pos (4UL) /*!< CTBM CTD_SW: CTDS_CRS (Bit 4) */ +#define CTBM_CTD_SW_CTDS_CRS_Msk (0x10UL) /*!< CTBM CTD_SW: CTDS_CRS (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CTDS_COR_Pos (5UL) /*!< CTBM CTD_SW: CTDS_COR (Bit 5) */ +#define CTBM_CTD_SW_CTDS_COR_Msk (0x20UL) /*!< CTBM CTD_SW: CTDS_COR (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CTDO_C6H_Pos (8UL) /*!< CTBM CTD_SW: CTDO_C6H (Bit 8) */ +#define CTBM_CTD_SW_CTDO_C6H_Msk (0x100UL) /*!< CTBM CTD_SW: CTDO_C6H (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CTDO_COS_Pos (9UL) /*!< CTBM CTD_SW: CTDO_COS (Bit 9) */ +#define CTBM_CTD_SW_CTDO_COS_Msk (0x200UL) /*!< CTBM CTD_SW: CTDO_COS (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CTDH_COB_Pos (10UL) /*!< CTBM CTD_SW: CTDH_COB (Bit 10) */ +#define CTBM_CTD_SW_CTDH_COB_Msk (0x400UL) /*!< CTBM CTD_SW: CTDH_COB (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CTDH_CHD_Pos (12UL) /*!< CTBM CTD_SW: CTDH_CHD (Bit 12) */ +#define CTBM_CTD_SW_CTDH_CHD_Msk (0x1000UL) /*!< CTBM CTD_SW: CTDH_CHD (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CTDH_CA0_Pos (13UL) /*!< CTBM CTD_SW: CTDH_CA0 (Bit 13) */ +#define CTBM_CTD_SW_CTDH_CA0_Msk (0x2000UL) /*!< CTBM CTD_SW: CTDH_CA0 (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CTDH_CIS_Pos (14UL) /*!< CTBM CTD_SW: CTDH_CIS (Bit 14) */ +#define CTBM_CTD_SW_CTDH_CIS_Msk (0x4000UL) /*!< CTBM CTD_SW: CTDH_CIS (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CTDH_ILR_Pos (15UL) /*!< CTBM CTD_SW: CTDH_ILR (Bit 15) */ +#define CTBM_CTD_SW_CTDH_ILR_Msk (0x8000UL) /*!< CTBM CTD_SW: CTDH_ILR (Bitfield-Mask: 0x01) */ +/* =================================================== CTBM.CTD_SW_CLEAR =================================================== */ +#define CTBM_CTD_SW_CLEAR_CTDD_CRD_Pos (1UL) /*!< CTBM CTD_SW_CLEAR: CTDD_CRD (Bit 1) */ +#define CTBM_CTD_SW_CLEAR_CTDD_CRD_Msk (0x2UL) /*!< CTBM CTD_SW_CLEAR: CTDD_CRD (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CLEAR_CTDS_CRS_Pos (4UL) /*!< CTBM CTD_SW_CLEAR: CTDS_CRS (Bit 4) */ +#define CTBM_CTD_SW_CLEAR_CTDS_CRS_Msk (0x10UL) /*!< CTBM CTD_SW_CLEAR: CTDS_CRS (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CLEAR_CTDS_COR_Pos (5UL) /*!< CTBM CTD_SW_CLEAR: CTDS_COR (Bit 5) */ +#define CTBM_CTD_SW_CLEAR_CTDS_COR_Msk (0x20UL) /*!< CTBM CTD_SW_CLEAR: CTDS_COR (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CLEAR_CTDO_C6H_Pos (8UL) /*!< CTBM CTD_SW_CLEAR: CTDO_C6H (Bit 8) */ +#define CTBM_CTD_SW_CLEAR_CTDO_C6H_Msk (0x100UL) /*!< CTBM CTD_SW_CLEAR: CTDO_C6H (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CLEAR_CTDO_COS_Pos (9UL) /*!< CTBM CTD_SW_CLEAR: CTDO_COS (Bit 9) */ +#define CTBM_CTD_SW_CLEAR_CTDO_COS_Msk (0x200UL) /*!< CTBM CTD_SW_CLEAR: CTDO_COS (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CLEAR_CTDH_COB_Pos (10UL) /*!< CTBM CTD_SW_CLEAR: CTDH_COB (Bit 10) */ +#define CTBM_CTD_SW_CLEAR_CTDH_COB_Msk (0x400UL) /*!< CTBM CTD_SW_CLEAR: CTDH_COB (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CLEAR_CTDH_CHD_Pos (12UL) /*!< CTBM CTD_SW_CLEAR: CTDH_CHD (Bit 12) */ +#define CTBM_CTD_SW_CLEAR_CTDH_CHD_Msk (0x1000UL) /*!< CTBM CTD_SW_CLEAR: CTDH_CHD (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CLEAR_CTDH_CA0_Pos (13UL) /*!< CTBM CTD_SW_CLEAR: CTDH_CA0 (Bit 13) */ +#define CTBM_CTD_SW_CLEAR_CTDH_CA0_Msk (0x2000UL) /*!< CTBM CTD_SW_CLEAR: CTDH_CA0 (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CLEAR_CTDH_CIS_Pos (14UL) /*!< CTBM CTD_SW_CLEAR: CTDH_CIS (Bit 14) */ +#define CTBM_CTD_SW_CLEAR_CTDH_CIS_Msk (0x4000UL) /*!< CTBM CTD_SW_CLEAR: CTDH_CIS (Bitfield-Mask: 0x01) */ +#define CTBM_CTD_SW_CLEAR_CTDH_ILR_Pos (15UL) /*!< CTBM CTD_SW_CLEAR: CTDH_ILR (Bit 15) */ +#define CTBM_CTD_SW_CLEAR_CTDH_ILR_Msk (0x8000UL) /*!< CTBM CTD_SW_CLEAR: CTDH_ILR (Bitfield-Mask: 0x01) */ +/* ================================================== CTBM.CTB_SW_DS_CTRL ================================================== */ +#define CTBM_CTB_SW_DS_CTRL_P2_DS_CTRL23_Pos (10UL) /*!< CTBM CTB_SW_DS_CTRL: P2_DS_CTRL23 (Bit 10) */ +#define CTBM_CTB_SW_DS_CTRL_P2_DS_CTRL23_Msk (0x400UL) /*!< CTBM CTB_SW_DS_CTRL: P2_DS_CTRL23 (Bitfield-Mask: 0x01) */ +#define CTBM_CTB_SW_DS_CTRL_P3_DS_CTRL23_Pos (11UL) /*!< CTBM CTB_SW_DS_CTRL: P3_DS_CTRL23 (Bit 11) */ +#define CTBM_CTB_SW_DS_CTRL_P3_DS_CTRL23_Msk (0x800UL) /*!< CTBM CTB_SW_DS_CTRL: P3_DS_CTRL23 (Bitfield-Mask: 0x01) */ +#define CTBM_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Pos (31UL) /*!< CTBM CTB_SW_DS_CTRL: CTD_COS_DS_CTRL (Bit 31) */ +#define CTBM_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Msk (0x80000000UL) /*!< CTBM CTB_SW_DS_CTRL: CTD_COS_DS_CTRL (Bitfield-Mask: 0x01)*/ +/* ================================================== CTBM.CTB_SW_SQ_CTRL ================================================== */ +#define CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Pos (10UL) /*!< CTBM CTB_SW_SQ_CTRL: P2_SQ_CTRL23 (Bit 10) */ +#define CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk (0x400UL) /*!< CTBM CTB_SW_SQ_CTRL: P2_SQ_CTRL23 (Bitfield-Mask: 0x01) */ +#define CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Pos (11UL) /*!< CTBM CTB_SW_SQ_CTRL: P3_SQ_CTRL23 (Bit 11) */ +#define CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk (0x800UL) /*!< CTBM CTB_SW_SQ_CTRL: P3_SQ_CTRL23 (Bitfield-Mask: 0x01) */ +/* ================================================== CTBM.CTB_SW_STATUS =================================================== */ +#define CTBM_CTB_SW_STATUS_OA0O_D51_STAT_Pos (28UL) /*!< CTBM CTB_SW_STATUS: OA0O_D51_STAT (Bit 28) */ +#define CTBM_CTB_SW_STATUS_OA0O_D51_STAT_Msk (0x10000000UL) /*!< CTBM CTB_SW_STATUS: OA0O_D51_STAT (Bitfield-Mask: 0x01) */ +#define CTBM_CTB_SW_STATUS_OA1O_D52_STAT_Pos (29UL) /*!< CTBM CTB_SW_STATUS: OA1O_D52_STAT (Bit 29) */ +#define CTBM_CTB_SW_STATUS_OA1O_D52_STAT_Msk (0x20000000UL) /*!< CTBM CTB_SW_STATUS: OA1O_D52_STAT (Bitfield-Mask: 0x01) */ +#define CTBM_CTB_SW_STATUS_OA1O_D62_STAT_Pos (30UL) /*!< CTBM CTB_SW_STATUS: OA1O_D62_STAT (Bit 30) */ +#define CTBM_CTB_SW_STATUS_OA1O_D62_STAT_Msk (0x40000000UL) /*!< CTBM CTB_SW_STATUS: OA1O_D62_STAT (Bitfield-Mask: 0x01) */ +#define CTBM_CTB_SW_STATUS_CTD_COS_STAT_Pos (31UL) /*!< CTBM CTB_SW_STATUS: CTD_COS_STAT (Bit 31) */ +#define CTBM_CTB_SW_STATUS_CTD_COS_STAT_Msk (0x80000000UL) /*!< CTBM CTB_SW_STATUS: CTD_COS_STAT (Bitfield-Mask: 0x01) */ +/* ================================================= CTBM.OA0_OFFSET_TRIM ================================================== */ +#define CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos (0UL) /*!< CTBM OA0_OFFSET_TRIM: OA0_OFFSET_TRIM (Bit 0) */ +#define CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk (0x3fUL) /*!< CTBM OA0_OFFSET_TRIM: OA0_OFFSET_TRIM (Bitfield-Mask: 0x3f)*/ +/* ============================================== CTBM.OA0_SLOPE_OFFSET_TRIM =============================================== */ +#define CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos (0UL) /*!< CTBM OA0_SLOPE_OFFSET_TRIM: OA0_SLOPE_OFFSET_TRIM (Bit 0)*/ +#define CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk (0x3fUL) /*!< CTBM OA0_SLOPE_OFFSET_TRIM: OA0_SLOPE_OFFSET_TRIM (Bitfield-Mask: 0x3f)*/ +/* ================================================== CTBM.OA0_COMP_TRIM =================================================== */ +#define CTBM_OA0_COMP_TRIM_OA0_COMP_TRIM_Pos (0UL) /*!< CTBM OA0_COMP_TRIM: OA0_COMP_TRIM (Bit 0) */ +#define CTBM_OA0_COMP_TRIM_OA0_COMP_TRIM_Msk (0x3UL) /*!< CTBM OA0_COMP_TRIM: OA0_COMP_TRIM (Bitfield-Mask: 0x03) */ +/* ================================================= CTBM.OA1_OFFSET_TRIM ================================================== */ +#define CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos (0UL) /*!< CTBM OA1_OFFSET_TRIM: OA1_OFFSET_TRIM (Bit 0) */ +#define CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk (0x3fUL) /*!< CTBM OA1_OFFSET_TRIM: OA1_OFFSET_TRIM (Bitfield-Mask: 0x3f)*/ +/* ============================================== CTBM.OA1_SLOPE_OFFSET_TRIM =============================================== */ +#define CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos (0UL) /*!< CTBM OA1_SLOPE_OFFSET_TRIM: OA1_SLOPE_OFFSET_TRIM (Bit 0)*/ +#define CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk (0x3fUL) /*!< CTBM OA1_SLOPE_OFFSET_TRIM: OA1_SLOPE_OFFSET_TRIM (Bitfield-Mask: 0x3f)*/ +/* ================================================== CTBM.OA1_COMP_TRIM =================================================== */ +#define CTBM_OA1_COMP_TRIM_OA1_COMP_TRIM_Pos (0UL) /*!< CTBM OA1_COMP_TRIM: OA1_COMP_TRIM (Bit 0) */ +#define CTBM_OA1_COMP_TRIM_OA1_COMP_TRIM_Msk (0x3UL) /*!< CTBM OA1_COMP_TRIM: OA1_COMP_TRIM (Bitfield-Mask: 0x03) */ + + +#endif /* _CYIP_CTBM_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ctdac.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ctdac.h new file mode 100644 index 0000000000..79832bfb3b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ctdac.h @@ -0,0 +1,110 @@ +/***************************************************************************//** +* \file cyip_ctdac.h +* +* \brief +* CTDAC IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_CTDAC_H_ +#define _CYIP_CTDAC_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ CTDAC ================ */ +/* =========================================================================================================================== */ + +#define CTDAC_SECTION_SIZE 0x00010000UL + +/** + * \brief Continuous Time DAC (CTDAC) + */ +typedef struct { /*!< CTDAC Structure */ + __IOM uint32_t CTDAC_CTRL; /*!< 0x00000000 Global CTDAC control */ + __IM uint32_t RESERVED[7]; + __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */ + __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */ + __IM uint32_t RESERVED1[32]; + __IOM uint32_t CTDAC_SW; /*!< 0x000000B0 CTDAC switch control */ + __IOM uint32_t CTDAC_SW_CLEAR; /*!< 0x000000B4 CTDAC switch control clear */ + __IM uint32_t RESERVED2[18]; + __IOM uint32_t CTDAC_VAL; /*!< 0x00000100 DAC Value */ + __IOM uint32_t CTDAC_VAL_NXT; /*!< 0x00000104 Next DAC value (double buffering) */ + __IM uint32_t RESERVED3[894]; + __IOM uint32_t TRIM; /*!< 0x00000F00 Trim */ +} CTDAC_Type; /*!< Size = 3844 (0xF04) */ + + +/* =================================================== CTDAC.CTDAC_CTRL ==================================================== */ +#define CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos (0UL) /*!< CTDAC CTDAC_CTRL: DEGLITCH_CNT (Bit 0) */ +#define CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk (0x3fUL) /*!< CTDAC CTDAC_CTRL: DEGLITCH_CNT (Bitfield-Mask: 0x3f) */ +#define CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Pos (8UL) /*!< CTDAC CTDAC_CTRL: DEGLITCH_CO6 (Bit 8) */ +#define CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk (0x100UL) /*!< CTDAC CTDAC_CTRL: DEGLITCH_CO6 (Bitfield-Mask: 0x01) */ +#define CTDAC_CTDAC_CTRL_DEGLITCH_COS_Pos (9UL) /*!< CTDAC CTDAC_CTRL: DEGLITCH_COS (Bit 9) */ +#define CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk (0x200UL) /*!< CTDAC CTDAC_CTRL: DEGLITCH_COS (Bitfield-Mask: 0x01) */ +#define CTDAC_CTDAC_CTRL_OUT_EN_Pos (22UL) /*!< CTDAC CTDAC_CTRL: OUT_EN (Bit 22) */ +#define CTDAC_CTDAC_CTRL_OUT_EN_Msk (0x400000UL) /*!< CTDAC CTDAC_CTRL: OUT_EN (Bitfield-Mask: 0x01) */ +#define CTDAC_CTDAC_CTRL_CTDAC_RANGE_Pos (23UL) /*!< CTDAC CTDAC_CTRL: CTDAC_RANGE (Bit 23) */ +#define CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk (0x800000UL) /*!< CTDAC CTDAC_CTRL: CTDAC_RANGE (Bitfield-Mask: 0x01) */ +#define CTDAC_CTDAC_CTRL_CTDAC_MODE_Pos (24UL) /*!< CTDAC CTDAC_CTRL: CTDAC_MODE (Bit 24) */ +#define CTDAC_CTDAC_CTRL_CTDAC_MODE_Msk (0x3000000UL) /*!< CTDAC CTDAC_CTRL: CTDAC_MODE (Bitfield-Mask: 0x03) */ +#define CTDAC_CTDAC_CTRL_DISABLED_MODE_Pos (27UL) /*!< CTDAC CTDAC_CTRL: DISABLED_MODE (Bit 27) */ +#define CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk (0x8000000UL) /*!< CTDAC CTDAC_CTRL: DISABLED_MODE (Bitfield-Mask: 0x01) */ +#define CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Pos (28UL) /*!< CTDAC CTDAC_CTRL: DSI_STROBE_EN (Bit 28) */ +#define CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Msk (0x10000000UL) /*!< CTDAC CTDAC_CTRL: DSI_STROBE_EN (Bitfield-Mask: 0x01) */ +#define CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Pos (29UL) /*!< CTDAC CTDAC_CTRL: DSI_STROBE_LEVEL (Bit 29) */ +#define CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Msk (0x20000000UL) /*!< CTDAC CTDAC_CTRL: DSI_STROBE_LEVEL (Bitfield-Mask: 0x01) */ +#define CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Pos (30UL) /*!< CTDAC CTDAC_CTRL: DEEPSLEEP_ON (Bit 30) */ +#define CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk (0x40000000UL) /*!< CTDAC CTDAC_CTRL: DEEPSLEEP_ON (Bitfield-Mask: 0x01) */ +#define CTDAC_CTDAC_CTRL_ENABLED_Pos (31UL) /*!< CTDAC CTDAC_CTRL: ENABLED (Bit 31) */ +#define CTDAC_CTDAC_CTRL_ENABLED_Msk (0x80000000UL) /*!< CTDAC CTDAC_CTRL: ENABLED (Bitfield-Mask: 0x01) */ +/* ====================================================== CTDAC.INTR ======================================================= */ +#define CTDAC_INTR_VDAC_EMPTY_Pos (0UL) /*!< CTDAC INTR: VDAC_EMPTY (Bit 0) */ +#define CTDAC_INTR_VDAC_EMPTY_Msk (0x1UL) /*!< CTDAC INTR: VDAC_EMPTY (Bitfield-Mask: 0x01) */ +/* ==================================================== CTDAC.INTR_SET ===================================================== */ +#define CTDAC_INTR_SET_VDAC_EMPTY_SET_Pos (0UL) /*!< CTDAC INTR_SET: VDAC_EMPTY_SET (Bit 0) */ +#define CTDAC_INTR_SET_VDAC_EMPTY_SET_Msk (0x1UL) /*!< CTDAC INTR_SET: VDAC_EMPTY_SET (Bitfield-Mask: 0x01) */ +/* ==================================================== CTDAC.INTR_MASK ==================================================== */ +#define CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Pos (0UL) /*!< CTDAC INTR_MASK: VDAC_EMPTY_MASK (Bit 0) */ +#define CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk (0x1UL) /*!< CTDAC INTR_MASK: VDAC_EMPTY_MASK (Bitfield-Mask: 0x01) */ +/* =================================================== CTDAC.INTR_MASKED =================================================== */ +#define CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Pos (0UL) /*!< CTDAC INTR_MASKED: VDAC_EMPTY_MASKED (Bit 0) */ +#define CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Msk (0x1UL) /*!< CTDAC INTR_MASKED: VDAC_EMPTY_MASKED (Bitfield-Mask: 0x01)*/ +/* ==================================================== CTDAC.CTDAC_SW ===================================================== */ +#define CTDAC_CTDAC_SW_CTDD_CVD_Pos (0UL) /*!< CTDAC CTDAC_SW: CTDD_CVD (Bit 0) */ +#define CTDAC_CTDAC_SW_CTDD_CVD_Msk (0x1UL) /*!< CTDAC CTDAC_SW: CTDD_CVD (Bitfield-Mask: 0x01) */ +#define CTDAC_CTDAC_SW_CTDO_CO6_Pos (8UL) /*!< CTDAC CTDAC_SW: CTDO_CO6 (Bit 8) */ +#define CTDAC_CTDAC_SW_CTDO_CO6_Msk (0x100UL) /*!< CTDAC CTDAC_SW: CTDO_CO6 (Bitfield-Mask: 0x01) */ +/* ================================================= CTDAC.CTDAC_SW_CLEAR ================================================== */ +#define CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Pos (0UL) /*!< CTDAC CTDAC_SW_CLEAR: CTDD_CVD (Bit 0) */ +#define CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk (0x1UL) /*!< CTDAC CTDAC_SW_CLEAR: CTDD_CVD (Bitfield-Mask: 0x01) */ +#define CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Pos (8UL) /*!< CTDAC CTDAC_SW_CLEAR: CTDO_CO6 (Bit 8) */ +#define CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Msk (0x100UL) /*!< CTDAC CTDAC_SW_CLEAR: CTDO_CO6 (Bitfield-Mask: 0x01) */ +/* ==================================================== CTDAC.CTDAC_VAL ==================================================== */ +#define CTDAC_CTDAC_VAL_VALUE_Pos (0UL) /*!< CTDAC CTDAC_VAL: VALUE (Bit 0) */ +#define CTDAC_CTDAC_VAL_VALUE_Msk (0xfffUL) /*!< CTDAC CTDAC_VAL: VALUE (Bitfield-Mask: 0xfff) */ +/* ================================================== CTDAC.CTDAC_VAL_NXT ================================================== */ +#define CTDAC_CTDAC_VAL_NXT_VALUE_Pos (0UL) /*!< CTDAC CTDAC_VAL_NXT: VALUE (Bit 0) */ +#define CTDAC_CTDAC_VAL_NXT_VALUE_Msk (0xfffUL) /*!< CTDAC CTDAC_VAL_NXT: VALUE (Bitfield-Mask: 0xfff) */ +/* ====================================================== CTDAC.TRIM ======================================================= */ +#define CTDAC_TRIM_TRIM_VAL_Pos (0UL) /*!< CTDAC TRIM: TRIM_VAL (Bit 0) */ +#define CTDAC_TRIM_TRIM_VAL_Msk (0xfUL) /*!< CTDAC TRIM: TRIM_VAL (Bitfield-Mask: 0x0f) */ + + +#endif /* _CYIP_CTDAC_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_dw.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_dw.h new file mode 100644 index 0000000000..7d723f89c0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_dw.h @@ -0,0 +1,230 @@ +/***************************************************************************//** +* \file cyip_dw.h +* +* \brief +* DW IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_DW_H_ +#define _CYIP_DW_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ DW ================ */ +/* =========================================================================================================================== */ + +#define DW_CH_STRUCT_SECTION_SIZE 0x00000020UL +#define DW_DESCR_STRUCT_SECTION_SIZE 0x00000020UL +#define DW_SECTION_SIZE 0x00001000UL + +/** + * \brief DW channel structure (DW_CH_STRUCT) + */ +typedef struct { + __IOM uint32_t CH_CTL; /*!< 0x00000000 Channel control */ + __IM uint32_t CH_STATUS; /*!< 0x00000004 Channel status */ + __IOM uint32_t CH_IDX; /*!< 0x00000008 Channel current indices */ + __IOM uint32_t CH_CURR_PTR; /*!< 0x0000000C Channel current descriptor pointer */ + __IOM uint32_t INTR; /*!< 0x00000010 Interrupt */ + __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */ + __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */ + __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */ +} DW_CH_STRUCT_Type; /*!< Size = 32 (0x20) */ + +/** + * \brief DW descriptor structure (DW_DESCR_STRUCT) + */ +typedef struct { + __IOM uint32_t DESCR_CTL; /*!< 0x00000000 Descriptor control */ + __IOM uint32_t DESCR_SRC; /*!< 0x00000004 Descriptor source */ + __IOM uint32_t DESCR_DST; /*!< 0x00000008 Descriptor destination */ + __IOM uint32_t DESCR_X_CTL; /*!< 0x0000000C Descriptor X loop control */ + __IOM uint32_t DESCR_Y_CTL; /*!< 0x00000010 Descriptor Y loop control */ + __IOM uint32_t DESCR_NEXT_PTR; /*!< 0x00000014 Descriptor next pointer */ + __IM uint32_t RESERVED[2]; +} DW_DESCR_STRUCT_Type; /*!< Size = 24 (0x18) */ + +/** + * \brief Datawire Controller (DW) + */ +typedef struct { /*!< DW Structure */ + __IOM uint32_t CTL; /*!< 0x00000000 Control */ + __IM uint32_t STATUS; /*!< 0x00000004 Status */ + __IM uint32_t PENDING; /*!< 0x00000008 Pending channels */ + __IM uint32_t RESERVED; + __IM uint32_t STATUS_INTR; /*!< 0x00000010 System interrupt control */ + __IM uint32_t STATUS_INTR_MASKED; /*!< 0x00000014 Status of interrupts masked */ + __IM uint32_t RESERVED1[2]; + __IM uint32_t ACT_DESCR_CTL; /*!< 0x00000020 Active descriptor control */ + __IM uint32_t ACT_DESCR_SRC; /*!< 0x00000024 Active descriptor source */ + __IM uint32_t ACT_DESCR_DST; /*!< 0x00000028 Active descriptor destination */ + __IM uint32_t RESERVED2; + __IM uint32_t ACT_DESCR_X_CTL; /*!< 0x00000030 Active descriptor X loop control */ + __IM uint32_t ACT_DESCR_Y_CTL; /*!< 0x00000034 Active descriptor Y loop control */ + __IM uint32_t ACT_DESCR_NEXT_PTR; /*!< 0x00000038 Active descriptor next pointer */ + __IM uint32_t RESERVED3; + __IM uint32_t ACT_SRC; /*!< 0x00000040 Active source */ + __IM uint32_t ACT_DST; /*!< 0x00000044 Active destination */ + __IM uint32_t RESERVED4[494]; + DW_CH_STRUCT_Type CH_STRUCT[32]; /*!< 0x00000800 DW channel structure */ + DW_DESCR_STRUCT_Type DESCR_STRUCT; /*!< 0x00000C00 DW descriptor structure */ +} DW_Type; /*!< Size = 3104 (0xC20) */ + + +/* ================================================== DW_CH_STRUCT.CH_CTL ================================================== */ +#define DW_CH_STRUCT_CH_CTL_P_Pos (0UL) /*!< DW_CH_STRUCT CH_CTL: P (Bit 0) */ +#define DW_CH_STRUCT_CH_CTL_P_Msk (0x1UL) /*!< DW_CH_STRUCT CH_CTL: P (Bitfield-Mask: 0x01) */ +#define DW_CH_STRUCT_CH_CTL_NS_Pos (1UL) /*!< DW_CH_STRUCT CH_CTL: NS (Bit 1) */ +#define DW_CH_STRUCT_CH_CTL_NS_Msk (0x2UL) /*!< DW_CH_STRUCT CH_CTL: NS (Bitfield-Mask: 0x01) */ +#define DW_CH_STRUCT_CH_CTL_B_Pos (2UL) /*!< DW_CH_STRUCT CH_CTL: B (Bit 2) */ +#define DW_CH_STRUCT_CH_CTL_B_Msk (0x4UL) /*!< DW_CH_STRUCT CH_CTL: B (Bitfield-Mask: 0x01) */ +#define DW_CH_STRUCT_CH_CTL_PC_Pos (4UL) /*!< DW_CH_STRUCT CH_CTL: PC (Bit 4) */ +#define DW_CH_STRUCT_CH_CTL_PC_Msk (0xf0UL) /*!< DW_CH_STRUCT CH_CTL: PC (Bitfield-Mask: 0x0f) */ +#define DW_CH_STRUCT_CH_CTL_PRIO_Pos (16UL) /*!< DW_CH_STRUCT CH_CTL: PRIO (Bit 16) */ +#define DW_CH_STRUCT_CH_CTL_PRIO_Msk (0x30000UL) /*!< DW_CH_STRUCT CH_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos (18UL) /*!< DW_CH_STRUCT CH_CTL: PREEMPTABLE (Bit 18) */ +#define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk (0x40000UL) /*!< DW_CH_STRUCT CH_CTL: PREEMPTABLE (Bitfield-Mask: 0x01) */ +#define DW_CH_STRUCT_CH_CTL_ENABLED_Pos (31UL) /*!< DW_CH_STRUCT CH_CTL: ENABLED (Bit 31) */ +#define DW_CH_STRUCT_CH_CTL_ENABLED_Msk (0x80000000UL) /*!< DW_CH_STRUCT CH_CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================ DW_CH_STRUCT.CH_STATUS ================================================= */ +#define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Pos (0UL) /*!< DW_CH_STRUCT CH_STATUS: INTR_CAUSE (Bit 0) */ +#define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Msk (0xfUL) /*!< DW_CH_STRUCT CH_STATUS: INTR_CAUSE (Bitfield-Mask: 0x0f) */ +/* ================================================== DW_CH_STRUCT.CH_IDX ================================================== */ +#define DW_CH_STRUCT_CH_IDX_X_IDX_Pos (0UL) /*!< DW_CH_STRUCT CH_IDX: X_IDX (Bit 0) */ +#define DW_CH_STRUCT_CH_IDX_X_IDX_Msk (0xffUL) /*!< DW_CH_STRUCT CH_IDX: X_IDX (Bitfield-Mask: 0xff) */ +#define DW_CH_STRUCT_CH_IDX_Y_IDX_Pos (8UL) /*!< DW_CH_STRUCT CH_IDX: Y_IDX (Bit 8) */ +#define DW_CH_STRUCT_CH_IDX_Y_IDX_Msk (0xff00UL) /*!< DW_CH_STRUCT CH_IDX: Y_IDX (Bitfield-Mask: 0xff) */ +/* =============================================== DW_CH_STRUCT.CH_CURR_PTR ================================================ */ +#define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Pos (2UL) /*!< DW_CH_STRUCT CH_CURR_PTR: ADDR (Bit 2) */ +#define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Msk (0xfffffffcUL) /*!< DW_CH_STRUCT CH_CURR_PTR: ADDR (Bitfield-Mask: 0x3fffffff)*/ +/* =================================================== DW_CH_STRUCT.INTR =================================================== */ +#define DW_CH_STRUCT_INTR_CH_Pos (0UL) /*!< DW_CH_STRUCT INTR: CH (Bit 0) */ +#define DW_CH_STRUCT_INTR_CH_Msk (0x1UL) /*!< DW_CH_STRUCT INTR: CH (Bitfield-Mask: 0x01) */ +/* ================================================= DW_CH_STRUCT.INTR_SET ================================================= */ +#define DW_CH_STRUCT_INTR_SET_CH_Pos (0UL) /*!< DW_CH_STRUCT INTR_SET: CH (Bit 0) */ +#define DW_CH_STRUCT_INTR_SET_CH_Msk (0x1UL) /*!< DW_CH_STRUCT INTR_SET: CH (Bitfield-Mask: 0x01) */ +/* ================================================ DW_CH_STRUCT.INTR_MASK ================================================= */ +#define DW_CH_STRUCT_INTR_MASK_CH_Pos (0UL) /*!< DW_CH_STRUCT INTR_MASK: CH (Bit 0) */ +#define DW_CH_STRUCT_INTR_MASK_CH_Msk (0x1UL) /*!< DW_CH_STRUCT INTR_MASK: CH (Bitfield-Mask: 0x01) */ +/* =============================================== DW_CH_STRUCT.INTR_MASKED ================================================ */ +#define DW_CH_STRUCT_INTR_MASKED_CH_Pos (0UL) /*!< DW_CH_STRUCT INTR_MASKED: CH (Bit 0) */ +#define DW_CH_STRUCT_INTR_MASKED_CH_Msk (0x1UL) /*!< DW_CH_STRUCT INTR_MASKED: CH (Bitfield-Mask: 0x01) */ + + +/* =============================================== DW_DESCR_STRUCT.DESCR_CTL =============================================== */ +#define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Pos (0UL) /*!< DW_DESCR_STRUCT DESCR_CTL: WAIT_FOR_DEACT (Bit 0) */ +#define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Msk (0x3UL) /*!< DW_DESCR_STRUCT DESCR_CTL: WAIT_FOR_DEACT (Bitfield-Mask: 0x03)*/ +#define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Pos (2UL) /*!< DW_DESCR_STRUCT DESCR_CTL: INTR_TYPE (Bit 2) */ +#define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Msk (0xcUL) /*!< DW_DESCR_STRUCT DESCR_CTL: INTR_TYPE (Bitfield-Mask: 0x03)*/ +#define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Pos (4UL) /*!< DW_DESCR_STRUCT DESCR_CTL: TR_OUT_TYPE (Bit 4) */ +#define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Msk (0x30UL) /*!< DW_DESCR_STRUCT DESCR_CTL: TR_OUT_TYPE (Bitfield-Mask: 0x03)*/ +#define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Pos (6UL) /*!< DW_DESCR_STRUCT DESCR_CTL: TR_IN_TYPE (Bit 6) */ +#define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Msk (0xc0UL) /*!< DW_DESCR_STRUCT DESCR_CTL: TR_IN_TYPE (Bitfield-Mask: 0x03)*/ +#define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Pos (24UL) /*!< DW_DESCR_STRUCT DESCR_CTL: CH_DISABLE (Bit 24) */ +#define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Msk (0x1000000UL) /*!< DW_DESCR_STRUCT DESCR_CTL: CH_DISABLE (Bitfield-Mask: 0x01)*/ +#define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Pos (26UL) /*!< DW_DESCR_STRUCT DESCR_CTL: SRC_TRANSFER_SIZE (Bit 26) */ +#define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk (0x4000000UL) /*!< DW_DESCR_STRUCT DESCR_CTL: SRC_TRANSFER_SIZE (Bitfield-Mask: 0x01)*/ +#define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Pos (27UL) /*!< DW_DESCR_STRUCT DESCR_CTL: DST_TRANSFER_SIZE (Bit 27) */ +#define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk (0x8000000UL) /*!< DW_DESCR_STRUCT DESCR_CTL: DST_TRANSFER_SIZE (Bitfield-Mask: 0x01)*/ +#define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Pos (28UL) /*!< DW_DESCR_STRUCT DESCR_CTL: DATA_SIZE (Bit 28) */ +#define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk (0x30000000UL) /*!< DW_DESCR_STRUCT DESCR_CTL: DATA_SIZE (Bitfield-Mask: 0x03)*/ +#define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Pos (30UL) /*!< DW_DESCR_STRUCT DESCR_CTL: DESCR_TYPE (Bit 30) */ +#define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Msk (0xc0000000UL) /*!< DW_DESCR_STRUCT DESCR_CTL: DESCR_TYPE (Bitfield-Mask: 0x03)*/ +/* =============================================== DW_DESCR_STRUCT.DESCR_SRC =============================================== */ +#define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Pos (0UL) /*!< DW_DESCR_STRUCT DESCR_SRC: SRC_ADDR (Bit 0) */ +#define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Msk (0xffffffffUL) /*!< DW_DESCR_STRUCT DESCR_SRC: SRC_ADDR (Bitfield-Mask: 0xffffffff)*/ +/* =============================================== DW_DESCR_STRUCT.DESCR_DST =============================================== */ +#define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Pos (0UL) /*!< DW_DESCR_STRUCT DESCR_DST: DST_ADDR (Bit 0) */ +#define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Msk (0xffffffffUL) /*!< DW_DESCR_STRUCT DESCR_DST: DST_ADDR (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== DW_DESCR_STRUCT.DESCR_X_CTL ============================================== */ +#define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Pos (0UL) /*!< DW_DESCR_STRUCT DESCR_X_CTL: SRC_X_INCR (Bit 0) */ +#define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Msk (0xfffUL) /*!< DW_DESCR_STRUCT DESCR_X_CTL: SRC_X_INCR (Bitfield-Mask: 0xfff)*/ +#define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Pos (12UL) /*!< DW_DESCR_STRUCT DESCR_X_CTL: DST_X_INCR (Bit 12) */ +#define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Msk (0xfff000UL) /*!< DW_DESCR_STRUCT DESCR_X_CTL: DST_X_INCR (Bitfield-Mask: 0xfff)*/ +#define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Pos (24UL) /*!< DW_DESCR_STRUCT DESCR_X_CTL: X_COUNT (Bit 24) */ +#define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Msk (0xff000000UL) /*!< DW_DESCR_STRUCT DESCR_X_CTL: X_COUNT (Bitfield-Mask: 0xff)*/ +/* ============================================== DW_DESCR_STRUCT.DESCR_Y_CTL ============================================== */ +#define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Pos (0UL) /*!< DW_DESCR_STRUCT DESCR_Y_CTL: SRC_Y_INCR (Bit 0) */ +#define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Msk (0xfffUL) /*!< DW_DESCR_STRUCT DESCR_Y_CTL: SRC_Y_INCR (Bitfield-Mask: 0xfff)*/ +#define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Pos (12UL) /*!< DW_DESCR_STRUCT DESCR_Y_CTL: DST_Y_INCR (Bit 12) */ +#define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Msk (0xfff000UL) /*!< DW_DESCR_STRUCT DESCR_Y_CTL: DST_Y_INCR (Bitfield-Mask: 0xfff)*/ +#define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Pos (24UL) /*!< DW_DESCR_STRUCT DESCR_Y_CTL: Y_COUNT (Bit 24) */ +#define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Msk (0xff000000UL) /*!< DW_DESCR_STRUCT DESCR_Y_CTL: Y_COUNT (Bitfield-Mask: 0xff)*/ +/* ============================================ DW_DESCR_STRUCT.DESCR_NEXT_PTR ============================================= */ +#define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Pos (2UL) /*!< DW_DESCR_STRUCT DESCR_NEXT_PTR: ADDR (Bit 2) */ +#define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Msk (0xfffffffcUL) /*!< DW_DESCR_STRUCT DESCR_NEXT_PTR: ADDR (Bitfield-Mask: 0x3fffffff)*/ + + +/* ======================================================== DW.CTL ========================================================= */ +#define DW_CTL_ENABLED_Pos (31UL) /*!< DW CTL: ENABLED (Bit 31) */ +#define DW_CTL_ENABLED_Msk (0x80000000UL) /*!< DW CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ======================================================= DW.STATUS ======================================================= */ +#define DW_STATUS_P_Pos (0UL) /*!< DW STATUS: P (Bit 0) */ +#define DW_STATUS_P_Msk (0x1UL) /*!< DW STATUS: P (Bitfield-Mask: 0x01) */ +#define DW_STATUS_NS_Pos (1UL) /*!< DW STATUS: NS (Bit 1) */ +#define DW_STATUS_NS_Msk (0x2UL) /*!< DW STATUS: NS (Bitfield-Mask: 0x01) */ +#define DW_STATUS_B_Pos (2UL) /*!< DW STATUS: B (Bit 2) */ +#define DW_STATUS_B_Msk (0x4UL) /*!< DW STATUS: B (Bitfield-Mask: 0x01) */ +#define DW_STATUS_PC_Pos (4UL) /*!< DW STATUS: PC (Bit 4) */ +#define DW_STATUS_PC_Msk (0xf0UL) /*!< DW STATUS: PC (Bitfield-Mask: 0x0f) */ +#define DW_STATUS_CH_IDX_Pos (8UL) /*!< DW STATUS: CH_IDX (Bit 8) */ +#define DW_STATUS_CH_IDX_Msk (0x1f00UL) /*!< DW STATUS: CH_IDX (Bitfield-Mask: 0x1f) */ +#define DW_STATUS_PRIO_Pos (16UL) /*!< DW STATUS: PRIO (Bit 16) */ +#define DW_STATUS_PRIO_Msk (0x30000UL) /*!< DW STATUS: PRIO (Bitfield-Mask: 0x03) */ +#define DW_STATUS_PREEMPTABLE_Pos (18UL) /*!< DW STATUS: PREEMPTABLE (Bit 18) */ +#define DW_STATUS_PREEMPTABLE_Msk (0x40000UL) /*!< DW STATUS: PREEMPTABLE (Bitfield-Mask: 0x01) */ +#define DW_STATUS_STATE_Pos (20UL) /*!< DW STATUS: STATE (Bit 20) */ +#define DW_STATUS_STATE_Msk (0x700000UL) /*!< DW STATUS: STATE (Bitfield-Mask: 0x07) */ +#define DW_STATUS_ACTIVE_Pos (31UL) /*!< DW STATUS: ACTIVE (Bit 31) */ +#define DW_STATUS_ACTIVE_Msk (0x80000000UL) /*!< DW STATUS: ACTIVE (Bitfield-Mask: 0x01) */ +/* ====================================================== DW.PENDING ======================================================= */ +#define DW_PENDING_CH_PENDING_Pos (0UL) /*!< DW PENDING: CH_PENDING (Bit 0) */ +#define DW_PENDING_CH_PENDING_Msk (0xffffffffUL) /*!< DW PENDING: CH_PENDING (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DW.STATUS_INTR ===================================================== */ +#define DW_STATUS_INTR_CH_Pos (0UL) /*!< DW STATUS_INTR: CH (Bit 0) */ +#define DW_STATUS_INTR_CH_Msk (0xffffffffUL) /*!< DW STATUS_INTR: CH (Bitfield-Mask: 0xffffffff) */ +/* ================================================= DW.STATUS_INTR_MASKED ================================================= */ +#define DW_STATUS_INTR_MASKED_CH_Pos (0UL) /*!< DW STATUS_INTR_MASKED: CH (Bit 0) */ +#define DW_STATUS_INTR_MASKED_CH_Msk (0xffffffffUL) /*!< DW STATUS_INTR_MASKED: CH (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DW.ACT_DESCR_CTL ==================================================== */ +#define DW_ACT_DESCR_CTL_DATA_Pos (0UL) /*!< DW ACT_DESCR_CTL: DATA (Bit 0) */ +#define DW_ACT_DESCR_CTL_DATA_Msk (0xffffffffUL) /*!< DW ACT_DESCR_CTL: DATA (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DW.ACT_DESCR_SRC ==================================================== */ +#define DW_ACT_DESCR_SRC_DATA_Pos (0UL) /*!< DW ACT_DESCR_SRC: DATA (Bit 0) */ +#define DW_ACT_DESCR_SRC_DATA_Msk (0xffffffffUL) /*!< DW ACT_DESCR_SRC: DATA (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DW.ACT_DESCR_DST ==================================================== */ +#define DW_ACT_DESCR_DST_DATA_Pos (0UL) /*!< DW ACT_DESCR_DST: DATA (Bit 0) */ +#define DW_ACT_DESCR_DST_DATA_Msk (0xffffffffUL) /*!< DW ACT_DESCR_DST: DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== DW.ACT_DESCR_X_CTL =================================================== */ +#define DW_ACT_DESCR_X_CTL_DATA_Pos (0UL) /*!< DW ACT_DESCR_X_CTL: DATA (Bit 0) */ +#define DW_ACT_DESCR_X_CTL_DATA_Msk (0xffffffffUL) /*!< DW ACT_DESCR_X_CTL: DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================== DW.ACT_DESCR_Y_CTL =================================================== */ +#define DW_ACT_DESCR_Y_CTL_DATA_Pos (0UL) /*!< DW ACT_DESCR_Y_CTL: DATA (Bit 0) */ +#define DW_ACT_DESCR_Y_CTL_DATA_Msk (0xffffffffUL) /*!< DW ACT_DESCR_Y_CTL: DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================= DW.ACT_DESCR_NEXT_PTR ================================================= */ +#define DW_ACT_DESCR_NEXT_PTR_ADDR_Pos (2UL) /*!< DW ACT_DESCR_NEXT_PTR: ADDR (Bit 2) */ +#define DW_ACT_DESCR_NEXT_PTR_ADDR_Msk (0xfffffffcUL) /*!< DW ACT_DESCR_NEXT_PTR: ADDR (Bitfield-Mask: 0x3fffffff) */ +/* ====================================================== DW.ACT_SRC ======================================================= */ +#define DW_ACT_SRC_SRC_ADDR_Pos (0UL) /*!< DW ACT_SRC: SRC_ADDR (Bit 0) */ +#define DW_ACT_SRC_SRC_ADDR_Msk (0xffffffffUL) /*!< DW ACT_SRC: SRC_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DW.ACT_DST ======================================================= */ +#define DW_ACT_DST_DST_ADDR_Pos (0UL) /*!< DW ACT_DST: DST_ADDR (Bit 0) */ +#define DW_ACT_DST_DST_ADDR_Msk (0xffffffffUL) /*!< DW ACT_DST: DST_ADDR (Bitfield-Mask: 0xffffffff) */ + + +#endif /* _CYIP_DW_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_efuse.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_efuse.h new file mode 100644 index 0000000000..e03d5e6d35 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_efuse.h @@ -0,0 +1,318 @@ +/***************************************************************************//** +* \file cyip_efuse.h +* +* \brief +* EFUSE IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_EFUSE_H_ +#define _CYIP_EFUSE_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ EFUSE ================ */ +/* =========================================================================================================================== */ + +#define EFUSE_SECTION_SIZE 0x00000080UL + +/** + * \brief EFUSE MXS40 registers (EFUSE) + */ +typedef struct { /*!< EFUSE Structure */ + __IOM uint32_t CTL; /*!< 0x00000000 Control */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t CMD; /*!< 0x00000010 Command */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t SEQ_DEFAULT; /*!< 0x00000020 Sequencer Default value */ + __IM uint32_t RESERVED2[7]; + __IOM uint32_t SEQ_READ_CTL_0; /*!< 0x00000040 Sequencer read control 0 */ + __IOM uint32_t SEQ_READ_CTL_1; /*!< 0x00000044 Sequencer read control 1 */ + __IOM uint32_t SEQ_READ_CTL_2; /*!< 0x00000048 Sequencer read control 2 */ + __IOM uint32_t SEQ_READ_CTL_3; /*!< 0x0000004C Sequencer read control 3 */ + __IOM uint32_t SEQ_READ_CTL_4; /*!< 0x00000050 Sequencer read control 4 */ + __IOM uint32_t SEQ_READ_CTL_5; /*!< 0x00000054 Sequencer read control 5 */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t SEQ_PROGRAM_CTL_0; /*!< 0x00000060 Sequencer program control 0 */ + __IOM uint32_t SEQ_PROGRAM_CTL_1; /*!< 0x00000064 Sequencer program control 1 */ + __IOM uint32_t SEQ_PROGRAM_CTL_2; /*!< 0x00000068 Sequencer program control 2 */ + __IOM uint32_t SEQ_PROGRAM_CTL_3; /*!< 0x0000006C Sequencer program control 3 */ + __IOM uint32_t SEQ_PROGRAM_CTL_4; /*!< 0x00000070 Sequencer program control 4 */ + __IOM uint32_t SEQ_PROGRAM_CTL_5; /*!< 0x00000074 Sequencer program control 5 */ +} EFUSE_Type; /*!< Size = 120 (0x78) */ + + +/* ======================================================= EFUSE.CTL ======================================================= */ +#define EFUSE_CTL_ENABLED_Pos (31UL) /*!< EFUSE CTL: ENABLED (Bit 31) */ +#define EFUSE_CTL_ENABLED_Msk (0x80000000UL) /*!< EFUSE CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ======================================================= EFUSE.CMD ======================================================= */ +#define EFUSE_CMD_BIT_DATA_Pos (0UL) /*!< EFUSE CMD: BIT_DATA (Bit 0) */ +#define EFUSE_CMD_BIT_DATA_Msk (0x1UL) /*!< EFUSE CMD: BIT_DATA (Bitfield-Mask: 0x01) */ +#define EFUSE_CMD_BIT_ADDR_Pos (4UL) /*!< EFUSE CMD: BIT_ADDR (Bit 4) */ +#define EFUSE_CMD_BIT_ADDR_Msk (0x70UL) /*!< EFUSE CMD: BIT_ADDR (Bitfield-Mask: 0x07) */ +#define EFUSE_CMD_BYTE_ADDR_Pos (8UL) /*!< EFUSE CMD: BYTE_ADDR (Bit 8) */ +#define EFUSE_CMD_BYTE_ADDR_Msk (0x1f00UL) /*!< EFUSE CMD: BYTE_ADDR (Bitfield-Mask: 0x1f) */ +#define EFUSE_CMD_MACRO_ADDR_Pos (16UL) /*!< EFUSE CMD: MACRO_ADDR (Bit 16) */ +#define EFUSE_CMD_MACRO_ADDR_Msk (0xf0000UL) /*!< EFUSE CMD: MACRO_ADDR (Bitfield-Mask: 0x0f) */ +#define EFUSE_CMD_START_Pos (31UL) /*!< EFUSE CMD: START (Bit 31) */ +#define EFUSE_CMD_START_Msk (0x80000000UL) /*!< EFUSE CMD: START (Bitfield-Mask: 0x01) */ +/* =================================================== EFUSE.SEQ_DEFAULT =================================================== */ +#define EFUSE_SEQ_DEFAULT_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_DEFAULT: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_DEFAULT_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_DEFAULT: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_DEFAULT_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_DEFAULT: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_DEFAULT_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_DEFAULT: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_DEFAULT_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_DEFAULT: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_DEFAULT_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_DEFAULT: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_DEFAULT_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_DEFAULT: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_DEFAULT_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_DEFAULT: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_DEFAULT_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_DEFAULT: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_DEFAULT_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_DEFAULT: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_DEFAULT_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_DEFAULT: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_DEFAULT_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_DEFAULT: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_DEFAULT_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_DEFAULT: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_DEFAULT_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_DEFAULT: STROBE_G (Bitfield-Mask: 0x01) */ +/* ================================================= EFUSE.SEQ_READ_CTL_0 ================================================== */ +#define EFUSE_SEQ_READ_CTL_0_CYCLES_Pos (0UL) /*!< EFUSE SEQ_READ_CTL_0: CYCLES (Bit 0) */ +#define EFUSE_SEQ_READ_CTL_0_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_READ_CTL_0: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_READ_CTL_0_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_READ_CTL_0: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_0_DONE_Pos (31UL) /*!< EFUSE SEQ_READ_CTL_0: DONE (Bit 31) */ +#define EFUSE_SEQ_READ_CTL_0_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_READ_CTL_0: DONE (Bitfield-Mask: 0x01) */ +/* ================================================= EFUSE.SEQ_READ_CTL_1 ================================================== */ +#define EFUSE_SEQ_READ_CTL_1_CYCLES_Pos (0UL) /*!< EFUSE SEQ_READ_CTL_1: CYCLES (Bit 0) */ +#define EFUSE_SEQ_READ_CTL_1_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_READ_CTL_1: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_READ_CTL_1_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_READ_CTL_1: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_1_DONE_Pos (31UL) /*!< EFUSE SEQ_READ_CTL_1: DONE (Bit 31) */ +#define EFUSE_SEQ_READ_CTL_1_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_READ_CTL_1: DONE (Bitfield-Mask: 0x01) */ +/* ================================================= EFUSE.SEQ_READ_CTL_2 ================================================== */ +#define EFUSE_SEQ_READ_CTL_2_CYCLES_Pos (0UL) /*!< EFUSE SEQ_READ_CTL_2: CYCLES (Bit 0) */ +#define EFUSE_SEQ_READ_CTL_2_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_READ_CTL_2: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_READ_CTL_2_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_READ_CTL_2: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_2_DONE_Pos (31UL) /*!< EFUSE SEQ_READ_CTL_2: DONE (Bit 31) */ +#define EFUSE_SEQ_READ_CTL_2_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_READ_CTL_2: DONE (Bitfield-Mask: 0x01) */ +/* ================================================= EFUSE.SEQ_READ_CTL_3 ================================================== */ +#define EFUSE_SEQ_READ_CTL_3_CYCLES_Pos (0UL) /*!< EFUSE SEQ_READ_CTL_3: CYCLES (Bit 0) */ +#define EFUSE_SEQ_READ_CTL_3_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_READ_CTL_3: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_READ_CTL_3_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_READ_CTL_3: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_3_DONE_Pos (31UL) /*!< EFUSE SEQ_READ_CTL_3: DONE (Bit 31) */ +#define EFUSE_SEQ_READ_CTL_3_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_READ_CTL_3: DONE (Bitfield-Mask: 0x01) */ +/* ================================================= EFUSE.SEQ_READ_CTL_4 ================================================== */ +#define EFUSE_SEQ_READ_CTL_4_CYCLES_Pos (0UL) /*!< EFUSE SEQ_READ_CTL_4: CYCLES (Bit 0) */ +#define EFUSE_SEQ_READ_CTL_4_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_READ_CTL_4: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_READ_CTL_4_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_READ_CTL_4: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_4_DONE_Pos (31UL) /*!< EFUSE SEQ_READ_CTL_4: DONE (Bit 31) */ +#define EFUSE_SEQ_READ_CTL_4_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_READ_CTL_4: DONE (Bitfield-Mask: 0x01) */ +/* ================================================= EFUSE.SEQ_READ_CTL_5 ================================================== */ +#define EFUSE_SEQ_READ_CTL_5_CYCLES_Pos (0UL) /*!< EFUSE SEQ_READ_CTL_5: CYCLES (Bit 0) */ +#define EFUSE_SEQ_READ_CTL_5_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_READ_CTL_5: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_READ_CTL_5_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_READ_CTL_5: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_READ_CTL_5_DONE_Pos (31UL) /*!< EFUSE SEQ_READ_CTL_5: DONE (Bit 31) */ +#define EFUSE_SEQ_READ_CTL_5_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_READ_CTL_5: DONE (Bitfield-Mask: 0x01) */ +/* ================================================ EFUSE.SEQ_PROGRAM_CTL_0 ================================================ */ +#define EFUSE_SEQ_PROGRAM_CTL_0_CYCLES_Pos (0UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: CYCLES (Bit 0) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_PROGRAM_CTL_0: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_DONE_Pos (31UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: DONE (Bit 31) */ +#define EFUSE_SEQ_PROGRAM_CTL_0_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_PROGRAM_CTL_0: DONE (Bitfield-Mask: 0x01) */ +/* ================================================ EFUSE.SEQ_PROGRAM_CTL_1 ================================================ */ +#define EFUSE_SEQ_PROGRAM_CTL_1_CYCLES_Pos (0UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: CYCLES (Bit 0) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_PROGRAM_CTL_1: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_DONE_Pos (31UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: DONE (Bit 31) */ +#define EFUSE_SEQ_PROGRAM_CTL_1_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_PROGRAM_CTL_1: DONE (Bitfield-Mask: 0x01) */ +/* ================================================ EFUSE.SEQ_PROGRAM_CTL_2 ================================================ */ +#define EFUSE_SEQ_PROGRAM_CTL_2_CYCLES_Pos (0UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: CYCLES (Bit 0) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_PROGRAM_CTL_2: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_DONE_Pos (31UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: DONE (Bit 31) */ +#define EFUSE_SEQ_PROGRAM_CTL_2_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_PROGRAM_CTL_2: DONE (Bitfield-Mask: 0x01) */ +/* ================================================ EFUSE.SEQ_PROGRAM_CTL_3 ================================================ */ +#define EFUSE_SEQ_PROGRAM_CTL_3_CYCLES_Pos (0UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: CYCLES (Bit 0) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_PROGRAM_CTL_3: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_DONE_Pos (31UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: DONE (Bit 31) */ +#define EFUSE_SEQ_PROGRAM_CTL_3_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_PROGRAM_CTL_3: DONE (Bitfield-Mask: 0x01) */ +/* ================================================ EFUSE.SEQ_PROGRAM_CTL_4 ================================================ */ +#define EFUSE_SEQ_PROGRAM_CTL_4_CYCLES_Pos (0UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: CYCLES (Bit 0) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_PROGRAM_CTL_4: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_DONE_Pos (31UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: DONE (Bit 31) */ +#define EFUSE_SEQ_PROGRAM_CTL_4_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_PROGRAM_CTL_4: DONE (Bitfield-Mask: 0x01) */ +/* ================================================ EFUSE.SEQ_PROGRAM_CTL_5 ================================================ */ +#define EFUSE_SEQ_PROGRAM_CTL_5_CYCLES_Pos (0UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: CYCLES (Bit 0) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_CYCLES_Msk (0x3ffUL) /*!< EFUSE SEQ_PROGRAM_CTL_5: CYCLES (Bitfield-Mask: 0x3ff) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_A_Pos (16UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_A (Bit 16) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_A_Msk (0x10000UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_A (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_B_Pos (17UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_B (Bit 17) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_B_Msk (0x20000UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_B (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_C_Pos (18UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_C (Bit 18) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_C_Msk (0x40000UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_C (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_D_Pos (19UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_D (Bit 19) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_D_Msk (0x80000UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_D (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_E_Pos (20UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_E (Bit 20) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_E_Msk (0x100000UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_E (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_F_Pos (21UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_F (Bit 21) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_F_Msk (0x200000UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_F (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_G_Pos (22UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_G (Bit 22) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_G_Msk (0x400000UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: STROBE_G (Bitfield-Mask: 0x01) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_DONE_Pos (31UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: DONE (Bit 31) */ +#define EFUSE_SEQ_PROGRAM_CTL_5_DONE_Msk (0x80000000UL) /*!< EFUSE SEQ_PROGRAM_CTL_5: DONE (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_EFUSE_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_fault.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_fault.h new file mode 100644 index 0000000000..cd5922f014 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_fault.h @@ -0,0 +1,113 @@ +/***************************************************************************//** +* \file cyip_fault.h +* +* \brief +* FAULT IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_FAULT_H_ +#define _CYIP_FAULT_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ FAULT ================ */ +/* =========================================================================================================================== */ + +#define FAULT_STRUCT_SECTION_SIZE 0x00000100UL +#define FAULT_SECTION_SIZE 0x00010000UL + +/** + * \brief Fault structure (FAULT_STRUCT) + */ +typedef struct { + __IOM uint32_t CTL; /*!< 0x00000000 Fault control */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t STATUS; /*!< 0x0000000C Fault status */ + __IM uint32_t DATA[4]; /*!< 0x00000010 Fault data */ + __IM uint32_t RESERVED1[8]; + __IM uint32_t PENDING0; /*!< 0x00000040 Fault pending 0 */ + __IM uint32_t PENDING1; /*!< 0x00000044 Fault pending 1 */ + __IM uint32_t PENDING2; /*!< 0x00000048 Fault pending 2 */ + __IM uint32_t RESERVED2; + __IOM uint32_t MASK0; /*!< 0x00000050 Fault mask 0 */ + __IOM uint32_t MASK1; /*!< 0x00000054 Fault mask 1 */ + __IOM uint32_t MASK2; /*!< 0x00000058 Fault mask 2 */ + __IM uint32_t RESERVED3[25]; + __IOM uint32_t INTR; /*!< 0x000000C0 Interrupt */ + __IOM uint32_t INTR_SET; /*!< 0x000000C4 Interrupt set */ + __IOM uint32_t INTR_MASK; /*!< 0x000000C8 Interrupt mask */ + __IM uint32_t INTR_MASKED; /*!< 0x000000CC Interrupt masked */ + __IM uint32_t RESERVED4[12]; +} FAULT_STRUCT_Type; /*!< Size = 208 (0xD0) */ + +/** + * \brief Fault structures (FAULT) + */ +typedef struct { /*!< FAULT Structure */ + FAULT_STRUCT_Type STRUCT[4]; /*!< 0x00000000 Fault structure */ +} FAULT_Type; /*!< Size = 1024 (0x400) */ + + +/* =================================================== FAULT_STRUCT.CTL ==================================================== */ +#define FAULT_STRUCT_CTL_TR_EN_Pos (0UL) /*!< FAULT_STRUCT CTL: TR_EN (Bit 0) */ +#define FAULT_STRUCT_CTL_TR_EN_Msk (0x1UL) /*!< FAULT_STRUCT CTL: TR_EN (Bitfield-Mask: 0x01) */ +#define FAULT_STRUCT_CTL_OUT_EN_Pos (1UL) /*!< FAULT_STRUCT CTL: OUT_EN (Bit 1) */ +#define FAULT_STRUCT_CTL_OUT_EN_Msk (0x2UL) /*!< FAULT_STRUCT CTL: OUT_EN (Bitfield-Mask: 0x01) */ +#define FAULT_STRUCT_CTL_RESET_REQ_EN_Pos (2UL) /*!< FAULT_STRUCT CTL: RESET_REQ_EN (Bit 2) */ +#define FAULT_STRUCT_CTL_RESET_REQ_EN_Msk (0x4UL) /*!< FAULT_STRUCT CTL: RESET_REQ_EN (Bitfield-Mask: 0x01) */ +/* ================================================== FAULT_STRUCT.STATUS ================================================== */ +#define FAULT_STRUCT_STATUS_IDX_Pos (0UL) /*!< FAULT_STRUCT STATUS: IDX (Bit 0) */ +#define FAULT_STRUCT_STATUS_IDX_Msk (0x7fUL) /*!< FAULT_STRUCT STATUS: IDX (Bitfield-Mask: 0x7f) */ +#define FAULT_STRUCT_STATUS_VALID_Pos (31UL) /*!< FAULT_STRUCT STATUS: VALID (Bit 31) */ +#define FAULT_STRUCT_STATUS_VALID_Msk (0x80000000UL) /*!< FAULT_STRUCT STATUS: VALID (Bitfield-Mask: 0x01) */ +/* =================================================== FAULT_STRUCT.DATA =================================================== */ +#define FAULT_STRUCT_DATA_DATA_Pos (0UL) /*!< FAULT_STRUCT DATA: DATA (Bit 0) */ +#define FAULT_STRUCT_DATA_DATA_Msk (0xffffffffUL) /*!< FAULT_STRUCT DATA: DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================= FAULT_STRUCT.PENDING0 ================================================= */ +#define FAULT_STRUCT_PENDING0_SOURCE_Pos (0UL) /*!< FAULT_STRUCT PENDING0: SOURCE (Bit 0) */ +#define FAULT_STRUCT_PENDING0_SOURCE_Msk (0xffffffffUL) /*!< FAULT_STRUCT PENDING0: SOURCE (Bitfield-Mask: 0xffffffff) */ +/* ================================================= FAULT_STRUCT.PENDING1 ================================================= */ +#define FAULT_STRUCT_PENDING1_SOURCE_Pos (0UL) /*!< FAULT_STRUCT PENDING1: SOURCE (Bit 0) */ +#define FAULT_STRUCT_PENDING1_SOURCE_Msk (0xffffffffUL) /*!< FAULT_STRUCT PENDING1: SOURCE (Bitfield-Mask: 0xffffffff) */ +/* ================================================= FAULT_STRUCT.PENDING2 ================================================= */ +#define FAULT_STRUCT_PENDING2_SOURCE_Pos (0UL) /*!< FAULT_STRUCT PENDING2: SOURCE (Bit 0) */ +#define FAULT_STRUCT_PENDING2_SOURCE_Msk (0xffffffffUL) /*!< FAULT_STRUCT PENDING2: SOURCE (Bitfield-Mask: 0xffffffff) */ +/* ================================================== FAULT_STRUCT.MASK0 =================================================== */ +#define FAULT_STRUCT_MASK0_SOURCE_Pos (0UL) /*!< FAULT_STRUCT MASK0: SOURCE (Bit 0) */ +#define FAULT_STRUCT_MASK0_SOURCE_Msk (0xffffffffUL) /*!< FAULT_STRUCT MASK0: SOURCE (Bitfield-Mask: 0xffffffff) */ +/* ================================================== FAULT_STRUCT.MASK1 =================================================== */ +#define FAULT_STRUCT_MASK1_SOURCE_Pos (0UL) /*!< FAULT_STRUCT MASK1: SOURCE (Bit 0) */ +#define FAULT_STRUCT_MASK1_SOURCE_Msk (0xffffffffUL) /*!< FAULT_STRUCT MASK1: SOURCE (Bitfield-Mask: 0xffffffff) */ +/* ================================================== FAULT_STRUCT.MASK2 =================================================== */ +#define FAULT_STRUCT_MASK2_SOURCE_Pos (0UL) /*!< FAULT_STRUCT MASK2: SOURCE (Bit 0) */ +#define FAULT_STRUCT_MASK2_SOURCE_Msk (0xffffffffUL) /*!< FAULT_STRUCT MASK2: SOURCE (Bitfield-Mask: 0xffffffff) */ +/* =================================================== FAULT_STRUCT.INTR =================================================== */ +#define FAULT_STRUCT_INTR_FAULT_Pos (0UL) /*!< FAULT_STRUCT INTR: FAULT (Bit 0) */ +#define FAULT_STRUCT_INTR_FAULT_Msk (0x1UL) /*!< FAULT_STRUCT INTR: FAULT (Bitfield-Mask: 0x01) */ +/* ================================================= FAULT_STRUCT.INTR_SET ================================================= */ +#define FAULT_STRUCT_INTR_SET_FAULT_Pos (0UL) /*!< FAULT_STRUCT INTR_SET: FAULT (Bit 0) */ +#define FAULT_STRUCT_INTR_SET_FAULT_Msk (0x1UL) /*!< FAULT_STRUCT INTR_SET: FAULT (Bitfield-Mask: 0x01) */ +/* ================================================ FAULT_STRUCT.INTR_MASK ================================================= */ +#define FAULT_STRUCT_INTR_MASK_FAULT_Pos (0UL) /*!< FAULT_STRUCT INTR_MASK: FAULT (Bit 0) */ +#define FAULT_STRUCT_INTR_MASK_FAULT_Msk (0x1UL) /*!< FAULT_STRUCT INTR_MASK: FAULT (Bitfield-Mask: 0x01) */ +/* =============================================== FAULT_STRUCT.INTR_MASKED ================================================ */ +#define FAULT_STRUCT_INTR_MASKED_FAULT_Pos (0UL) /*!< FAULT_STRUCT INTR_MASKED: FAULT (Bit 0) */ +#define FAULT_STRUCT_INTR_MASKED_FAULT_Msk (0x1UL) /*!< FAULT_STRUCT INTR_MASKED: FAULT (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_FAULT_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_flashc.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_flashc.h new file mode 100644 index 0000000000..6243a8e5d6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_flashc.h @@ -0,0 +1,518 @@ +/***************************************************************************//** +* \file cyip_flashc.h +* +* \brief +* FLASHC IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_FLASHC_H_ +#define _CYIP_FLASHC_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ FLASHC ================ */ +/* =========================================================================================================================== */ + +#define FLASHC_FM_CTL_SECTION_SIZE 0x00001000UL +#define FLASHC_SECTION_SIZE 0x00010000UL + +/** + * \brief Flash Macro Registers (FLASHC_FM_CTL) + */ +typedef struct { + __IOM uint32_t FM_CTL; /*!< 0x00000000 Flash macro control */ + __IM uint32_t STATUS; /*!< 0x00000004 Status */ + __IOM uint32_t FM_ADDR; /*!< 0x00000008 Flash macro address */ + __IM uint32_t GEOMETRY; /*!< 0x0000000C Regular flash geometry */ + __IM uint32_t GEOMETRY_SUPERVISORY; /*!< 0x00000010 Supervisory flash geometry */ + __IOM uint32_t TIMER_CTL; /*!< 0x00000014 Timer control */ + __IOM uint32_t ANA_CTL0; /*!< 0x00000018 Analog control 0 */ + __IOM uint32_t ANA_CTL1; /*!< 0x0000001C Analog control 1 */ + __IM uint32_t GEOMETRY_GEN; /*!< 0x00000020 General FM Geometry Info */ + __IOM uint32_t TEST_CTL; /*!< 0x00000024 Test mode control */ + __IOM uint32_t WAIT_CTL; /*!< 0x00000028 Wiat State control */ + __IM uint32_t MONITOR_STATUS; /*!< 0x0000002C Monitor Status */ + __IOM uint32_t SCRATCH_CTL; /*!< 0x00000030 Scratch Control */ + __IOM uint32_t HV_CTL; /*!< 0x00000034 High voltage control */ + __OM uint32_t ACLK_CTL; /*!< 0x00000038 Aclk control */ + __IOM uint32_t INTR; /*!< 0x0000003C Interrupt */ + __IOM uint32_t INTR_SET; /*!< 0x00000040 Interrupt set */ + __IOM uint32_t INTR_MASK; /*!< 0x00000044 Interrupt mask */ + __IM uint32_t INTR_MASKED; /*!< 0x00000048 Interrupt masked */ + __OM uint32_t FM_HV_DATA_ALL; /*!< 0x0000004C Flash macro high Voltage page latches data (for all page + latches) */ + __IOM uint32_t CAL_CTL0; /*!< 0x00000050 Cal control BG LO trim bits */ + __IOM uint32_t CAL_CTL1; /*!< 0x00000054 Cal control BG HI trim bits */ + __IOM uint32_t CAL_CTL2; /*!< 0x00000058 Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext */ + __IOM uint32_t CAL_CTL3; /*!< 0x0000005C Cal control osc trim bits, idac, sdac, itim, bdac. */ + __OM uint32_t BOOKMARK; /*!< 0x00000060 Bookmark register - keeps the current FW HV seq */ + __IM uint32_t RESERVED[7]; + __IOM uint32_t RED_CTL01; /*!< 0x00000080 Redundancy Control normal sectors 0,1 */ + __IOM uint32_t RED_CTL23; /*!< 0x00000084 Redundancy Controll normal sectors 2,3 */ + __IOM uint32_t RED_CTL45; /*!< 0x00000088 Redundancy Controll normal sectors 4,5 */ + __IOM uint32_t RED_CTL67; /*!< 0x0000008C Redundancy Controll normal sectors 6,7 */ + __IOM uint32_t RED_CTL_SM01; /*!< 0x00000090 Redundancy Controll special sectors 0,1 */ + __IM uint32_t RESERVED1[27]; + __IM uint32_t TM_CMPR[32]; /*!< 0x00000100 Comparison between FM data out and Page Latches on each + column. */ + __IM uint32_t RESERVED2[416]; + __IOM uint32_t FM_HV_DATA[256]; /*!< 0x00000800 Flash macro high Voltage page latches data */ + __IM uint32_t FM_MEM_DATA[256]; /*!< 0x00000C00 Flash macro memory sense amplifier and column decoder data */ +} FLASHC_FM_CTL_Type; /*!< Size = 4096 (0x1000) */ + +/** + * \brief Flash controller (FLASHC) + */ +typedef struct { /*!< FLASHC Structure */ + __IOM uint32_t FLASH_CTL; /*!< 0x00000000 Control */ + __IOM uint32_t FLASH_PWR_CTL; /*!< 0x00000004 Flash power control */ + __IOM uint32_t FLASH_CMD; /*!< 0x00000008 Command */ + __IM uint32_t RESERVED[253]; + __IOM uint32_t CM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */ + __IOM uint32_t CM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */ + __IOM uint32_t CM0_CA_CMD; /*!< 0x00000408 CM0+ cache command */ + __IM uint32_t RESERVED1[13]; + __IM uint32_t CM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */ + __IM uint32_t CM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */ + __IM uint32_t CM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */ + __IM uint32_t RESERVED2[13]; + __IOM uint32_t CM4_CA_CTL0; /*!< 0x00000480 CM4 cache control */ + __IOM uint32_t CM4_CA_CTL1; /*!< 0x00000484 CM0+ cache control */ + __IOM uint32_t CM4_CA_CMD; /*!< 0x00000488 CM4 cache command */ + __IM uint32_t RESERVED3[13]; + __IM uint32_t CM4_CA_STATUS0; /*!< 0x000004C0 CM4 cache status 0 */ + __IM uint32_t CM4_CA_STATUS1; /*!< 0x000004C4 CM4 cache status 1 */ + __IM uint32_t CM4_CA_STATUS2; /*!< 0x000004C8 CM4 cache status 2 */ + __IM uint32_t RESERVED4[13]; + __IOM uint32_t CRYPTO_BUFF_CTL; /*!< 0x00000500 Cryptography buffer control */ + __IM uint32_t RESERVED5; + __IOM uint32_t CRYPTO_BUFF_CMD; /*!< 0x00000508 Cryptography buffer command */ + __IM uint32_t RESERVED6[29]; + __IOM uint32_t DW0_BUFF_CTL; /*!< 0x00000580 Datawire 0 buffer control */ + __IM uint32_t RESERVED7; + __IOM uint32_t DW0_BUFF_CMD; /*!< 0x00000588 Datawire 0 buffer command */ + __IM uint32_t RESERVED8[29]; + __IOM uint32_t DW1_BUFF_CTL; /*!< 0x00000600 Datawire 1 buffer control */ + __IM uint32_t RESERVED9; + __IOM uint32_t DW1_BUFF_CMD; /*!< 0x00000608 Datawire 1 buffer command */ + __IM uint32_t RESERVED10[29]; + __IOM uint32_t DAP_BUFF_CTL; /*!< 0x00000680 Debug access port buffer control */ + __IM uint32_t RESERVED11; + __IOM uint32_t DAP_BUFF_CMD; /*!< 0x00000688 Debug access port buffer command */ + __IM uint32_t RESERVED12[29]; + __IOM uint32_t EXT_MS0_BUFF_CTL; /*!< 0x00000700 External master 0 buffer control */ + __IM uint32_t RESERVED13; + __IOM uint32_t EXT_MS0_BUFF_CMD; /*!< 0x00000708 External master 0 buffer command */ + __IM uint32_t RESERVED14[29]; + __IOM uint32_t EXT_MS1_BUFF_CTL; /*!< 0x00000780 External master 1 buffer control */ + __IM uint32_t RESERVED15; + __IOM uint32_t EXT_MS1_BUFF_CMD; /*!< 0x00000788 External master 1 buffer command */ + __IM uint32_t RESERVED16[14877]; + FLASHC_FM_CTL_Type FM_CTL; /*!< 0x0000F000 Flash Macro Registers */ +} FLASHC_Type; /*!< Size = 65536 (0x10000) */ + + +/* ================================================= FLASHC_FM_CTL.FM_CTL ================================================== */ +#define FLASHC_FM_CTL_FM_CTL_FM_MODE_Pos (0UL) /*!< FLASHC_FM_CTL FM_CTL: FM_MODE (Bit 0) */ +#define FLASHC_FM_CTL_FM_CTL_FM_MODE_Msk (0xfUL) /*!< FLASHC_FM_CTL FM_CTL: FM_MODE (Bitfield-Mask: 0x0f) */ +#define FLASHC_FM_CTL_FM_CTL_FM_SEQ_Pos (8UL) /*!< FLASHC_FM_CTL FM_CTL: FM_SEQ (Bit 8) */ +#define FLASHC_FM_CTL_FM_CTL_FM_SEQ_Msk (0x300UL) /*!< FLASHC_FM_CTL FM_CTL: FM_SEQ (Bitfield-Mask: 0x03) */ +#define FLASHC_FM_CTL_FM_CTL_DAA_MUX_SEL_Pos (16UL) /*!< FLASHC_FM_CTL FM_CTL: DAA_MUX_SEL (Bit 16) */ +#define FLASHC_FM_CTL_FM_CTL_DAA_MUX_SEL_Msk (0x7f0000UL) /*!< FLASHC_FM_CTL FM_CTL: DAA_MUX_SEL (Bitfield-Mask: 0x7f) */ +#define FLASHC_FM_CTL_FM_CTL_IF_SEL_Pos (24UL) /*!< FLASHC_FM_CTL FM_CTL: IF_SEL (Bit 24) */ +#define FLASHC_FM_CTL_FM_CTL_IF_SEL_Msk (0x1000000UL) /*!< FLASHC_FM_CTL FM_CTL: IF_SEL (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_FM_CTL_WR_EN_Pos (25UL) /*!< FLASHC_FM_CTL FM_CTL: WR_EN (Bit 25) */ +#define FLASHC_FM_CTL_FM_CTL_WR_EN_Msk (0x2000000UL) /*!< FLASHC_FM_CTL FM_CTL: WR_EN (Bitfield-Mask: 0x01) */ +/* ================================================= FLASHC_FM_CTL.STATUS ================================================== */ +#define FLASHC_FM_CTL_STATUS_HV_TIMER_RUNNING_Pos (0UL) /*!< FLASHC_FM_CTL STATUS: HV_TIMER_RUNNING (Bit 0) */ +#define FLASHC_FM_CTL_STATUS_HV_TIMER_RUNNING_Msk (0x1UL) /*!< FLASHC_FM_CTL STATUS: HV_TIMER_RUNNING (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Pos (1UL) /*!< FLASHC_FM_CTL STATUS: HV_REGS_ISOLATED (Bit 1) */ +#define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Msk (0x2UL) /*!< FLASHC_FM_CTL STATUS: HV_REGS_ISOLATED (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Pos (2UL) /*!< FLASHC_FM_CTL STATUS: ILLEGAL_HVOP (Bit 2) */ +#define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Msk (0x4UL) /*!< FLASHC_FM_CTL STATUS: ILLEGAL_HVOP (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_STATUS_TURBO_N_Pos (3UL) /*!< FLASHC_FM_CTL STATUS: TURBO_N (Bit 3) */ +#define FLASHC_FM_CTL_STATUS_TURBO_N_Msk (0x8UL) /*!< FLASHC_FM_CTL STATUS: TURBO_N (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_STATUS_WR_EN_MON_Pos (4UL) /*!< FLASHC_FM_CTL STATUS: WR_EN_MON (Bit 4) */ +#define FLASHC_FM_CTL_STATUS_WR_EN_MON_Msk (0x10UL) /*!< FLASHC_FM_CTL STATUS: WR_EN_MON (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Pos (5UL) /*!< FLASHC_FM_CTL STATUS: IF_SEL_MON (Bit 5) */ +#define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Msk (0x20UL) /*!< FLASHC_FM_CTL STATUS: IF_SEL_MON (Bitfield-Mask: 0x01) */ +/* ================================================= FLASHC_FM_CTL.FM_ADDR ================================================= */ +#define FLASHC_FM_CTL_FM_ADDR_RA_Pos (0UL) /*!< FLASHC_FM_CTL FM_ADDR: RA (Bit 0) */ +#define FLASHC_FM_CTL_FM_ADDR_RA_Msk (0xffffUL) /*!< FLASHC_FM_CTL FM_ADDR: RA (Bitfield-Mask: 0xffff) */ +#define FLASHC_FM_CTL_FM_ADDR_BA_Pos (16UL) /*!< FLASHC_FM_CTL FM_ADDR: BA (Bit 16) */ +#define FLASHC_FM_CTL_FM_ADDR_BA_Msk (0xff0000UL) /*!< FLASHC_FM_CTL FM_ADDR: BA (Bitfield-Mask: 0xff) */ +#define FLASHC_FM_CTL_FM_ADDR_AXA_Pos (24UL) /*!< FLASHC_FM_CTL FM_ADDR: AXA (Bit 24) */ +#define FLASHC_FM_CTL_FM_ADDR_AXA_Msk (0x1000000UL) /*!< FLASHC_FM_CTL FM_ADDR: AXA (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC_FM_CTL.GEOMETRY ================================================= */ +#define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Pos (0UL) /*!< FLASHC_FM_CTL GEOMETRY: WORD_SIZE_LOG2 (Bit 0) */ +#define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Msk (0xfUL) /*!< FLASHC_FM_CTL GEOMETRY: WORD_SIZE_LOG2 (Bitfield-Mask: 0x0f)*/ +#define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Pos (4UL) /*!< FLASHC_FM_CTL GEOMETRY: PAGE_SIZE_LOG2 (Bit 4) */ +#define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Msk (0xf0UL) /*!< FLASHC_FM_CTL GEOMETRY: PAGE_SIZE_LOG2 (Bitfield-Mask: 0x0f)*/ +#define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Pos (8UL) /*!< FLASHC_FM_CTL GEOMETRY: ROW_COUNT (Bit 8) */ +#define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Msk (0xffff00UL) /*!< FLASHC_FM_CTL GEOMETRY: ROW_COUNT (Bitfield-Mask: 0xffff) */ +#define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Pos (24UL) /*!< FLASHC_FM_CTL GEOMETRY: BANK_COUNT (Bit 24) */ +#define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Msk (0xff000000UL) /*!< FLASHC_FM_CTL GEOMETRY: BANK_COUNT (Bitfield-Mask: 0xff) */ +/* ========================================== FLASHC_FM_CTL.GEOMETRY_SUPERVISORY =========================================== */ +#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Pos (0UL) /*!< FLASHC_FM_CTL GEOMETRY_SUPERVISORY: WORD_SIZE_LOG2 (Bit 0)*/ +#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Msk (0xfUL) /*!< FLASHC_FM_CTL GEOMETRY_SUPERVISORY: WORD_SIZE_LOG2 (Bitfield-Mask: 0x0f)*/ +#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Pos (4UL) /*!< FLASHC_FM_CTL GEOMETRY_SUPERVISORY: PAGE_SIZE_LOG2 (Bit 4)*/ +#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Msk (0xf0UL) /*!< FLASHC_FM_CTL GEOMETRY_SUPERVISORY: PAGE_SIZE_LOG2 (Bitfield-Mask: 0x0f)*/ +#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Pos (8UL) /*!< FLASHC_FM_CTL GEOMETRY_SUPERVISORY: ROW_COUNT (Bit 8) */ +#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Msk (0xffff00UL) /*!< FLASHC_FM_CTL GEOMETRY_SUPERVISORY: ROW_COUNT (Bitfield-Mask: 0xffff)*/ +#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Pos (24UL) /*!< FLASHC_FM_CTL GEOMETRY_SUPERVISORY: BANK_COUNT (Bit 24) */ +#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Msk (0xff000000UL) /*!< FLASHC_FM_CTL GEOMETRY_SUPERVISORY: BANK_COUNT (Bitfield-Mask: 0xff)*/ +/* ================================================ FLASHC_FM_CTL.TIMER_CTL ================================================ */ +#define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Pos (0UL) /*!< FLASHC_FM_CTL TIMER_CTL: PERIOD (Bit 0) */ +#define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Msk (0xffffUL) /*!< FLASHC_FM_CTL TIMER_CTL: PERIOD (Bitfield-Mask: 0xffff) */ +#define FLASHC_FM_CTL_TIMER_CTL_SCALE_Pos (16UL) /*!< FLASHC_FM_CTL TIMER_CTL: SCALE (Bit 16) */ +#define FLASHC_FM_CTL_TIMER_CTL_SCALE_Msk (0x10000UL) /*!< FLASHC_FM_CTL TIMER_CTL: SCALE (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TIMER_CTL_PUMP_CLOCK_SEL_Pos (24UL) /*!< FLASHC_FM_CTL TIMER_CTL: PUMP_CLOCK_SEL (Bit 24) */ +#define FLASHC_FM_CTL_TIMER_CTL_PUMP_CLOCK_SEL_Msk (0x1000000UL) /*!< FLASHC_FM_CTL TIMER_CTL: PUMP_CLOCK_SEL (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Pos (25UL) /*!< FLASHC_FM_CTL TIMER_CTL: PRE_PROG (Bit 25) */ +#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Msk (0x2000000UL) /*!< FLASHC_FM_CTL TIMER_CTL: PRE_PROG (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Pos (26UL) /*!< FLASHC_FM_CTL TIMER_CTL: PRE_PROG_CSL (Bit 26) */ +#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Msk (0x4000000UL) /*!< FLASHC_FM_CTL TIMER_CTL: PRE_PROG_CSL (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Pos (29UL) /*!< FLASHC_FM_CTL TIMER_CTL: PUMP_EN (Bit 29) */ +#define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Msk (0x20000000UL) /*!< FLASHC_FM_CTL TIMER_CTL: PUMP_EN (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Pos (30UL) /*!< FLASHC_FM_CTL TIMER_CTL: ACLK_EN (Bit 30) */ +#define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Msk (0x40000000UL) /*!< FLASHC_FM_CTL TIMER_CTL: ACLK_EN (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Pos (31UL) /*!< FLASHC_FM_CTL TIMER_CTL: TIMER_EN (Bit 31) */ +#define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Msk (0x80000000UL) /*!< FLASHC_FM_CTL TIMER_CTL: TIMER_EN (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC_FM_CTL.ANA_CTL0 ================================================= */ +#define FLASHC_FM_CTL_ANA_CTL0_CSLDAC_Pos (8UL) /*!< FLASHC_FM_CTL ANA_CTL0: CSLDAC (Bit 8) */ +#define FLASHC_FM_CTL_ANA_CTL0_CSLDAC_Msk (0x700UL) /*!< FLASHC_FM_CTL ANA_CTL0: CSLDAC (Bitfield-Mask: 0x07) */ +#define FLASHC_FM_CTL_ANA_CTL0_VCC_SEL_Pos (24UL) /*!< FLASHC_FM_CTL ANA_CTL0: VCC_SEL (Bit 24) */ +#define FLASHC_FM_CTL_ANA_CTL0_VCC_SEL_Msk (0x1000000UL) /*!< FLASHC_FM_CTL ANA_CTL0: VCC_SEL (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Pos (27UL) /*!< FLASHC_FM_CTL ANA_CTL0: FLIP_AMUXBUS_AB (Bit 27) */ +#define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Msk (0x8000000UL) /*!< FLASHC_FM_CTL ANA_CTL0: FLIP_AMUXBUS_AB (Bitfield-Mask: 0x01)*/ +/* ================================================ FLASHC_FM_CTL.ANA_CTL1 ================================================= */ +#define FLASHC_FM_CTL_ANA_CTL1_MDAC_Pos (0UL) /*!< FLASHC_FM_CTL ANA_CTL1: MDAC (Bit 0) */ +#define FLASHC_FM_CTL_ANA_CTL1_MDAC_Msk (0xffUL) /*!< FLASHC_FM_CTL ANA_CTL1: MDAC (Bitfield-Mask: 0xff) */ +#define FLASHC_FM_CTL_ANA_CTL1_PDAC_Pos (16UL) /*!< FLASHC_FM_CTL ANA_CTL1: PDAC (Bit 16) */ +#define FLASHC_FM_CTL_ANA_CTL1_PDAC_Msk (0xf0000UL) /*!< FLASHC_FM_CTL ANA_CTL1: PDAC (Bitfield-Mask: 0x0f) */ +#define FLASHC_FM_CTL_ANA_CTL1_NDAC_Pos (24UL) /*!< FLASHC_FM_CTL ANA_CTL1: NDAC (Bit 24) */ +#define FLASHC_FM_CTL_ANA_CTL1_NDAC_Msk (0xf000000UL) /*!< FLASHC_FM_CTL ANA_CTL1: NDAC (Bitfield-Mask: 0x0f) */ +#define FLASHC_FM_CTL_ANA_CTL1_VPROT_OVERRIDE_Pos (28UL) /*!< FLASHC_FM_CTL ANA_CTL1: VPROT_OVERRIDE (Bit 28) */ +#define FLASHC_FM_CTL_ANA_CTL1_VPROT_OVERRIDE_Msk (0x10000000UL) /*!< FLASHC_FM_CTL ANA_CTL1: VPROT_OVERRIDE (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_ANA_CTL1_SPARE2_Pos (29UL) /*!< FLASHC_FM_CTL ANA_CTL1: SPARE2 (Bit 29) */ +#define FLASHC_FM_CTL_ANA_CTL1_SPARE2_Msk (0x20000000UL) /*!< FLASHC_FM_CTL ANA_CTL1: SPARE2 (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_ANA_CTL1_RST_SFT_HVPL_Pos (30UL) /*!< FLASHC_FM_CTL ANA_CTL1: RST_SFT_HVPL (Bit 30) */ +#define FLASHC_FM_CTL_ANA_CTL1_RST_SFT_HVPL_Msk (0x40000000UL) /*!< FLASHC_FM_CTL ANA_CTL1: RST_SFT_HVPL (Bitfield-Mask: 0x01)*/ +/* ============================================== FLASHC_FM_CTL.GEOMETRY_GEN =============================================== */ +#define FLASHC_FM_CTL_GEOMETRY_GEN_RWW_Pos (1UL) /*!< FLASHC_FM_CTL GEOMETRY_GEN: RWW (Bit 1) */ +#define FLASHC_FM_CTL_GEOMETRY_GEN_RWW_Msk (0x2UL) /*!< FLASHC_FM_CTL GEOMETRY_GEN: RWW (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_GEOMETRY_GEN_MAX_DOUT_WIDTH_Pos (2UL) /*!< FLASHC_FM_CTL GEOMETRY_GEN: MAX_DOUT_WIDTH (Bit 2) */ +#define FLASHC_FM_CTL_GEOMETRY_GEN_MAX_DOUT_WIDTH_Msk (0x4UL) /*!< FLASHC_FM_CTL GEOMETRY_GEN: MAX_DOUT_WIDTH (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_GEOMETRY_GEN_SECTOR0_SR_Pos (3UL) /*!< FLASHC_FM_CTL GEOMETRY_GEN: SECTOR0_SR (Bit 3) */ +#define FLASHC_FM_CTL_GEOMETRY_GEN_SECTOR0_SR_Msk (0x8UL) /*!< FLASHC_FM_CTL GEOMETRY_GEN: SECTOR0_SR (Bitfield-Mask: 0x01)*/ +/* ================================================ FLASHC_FM_CTL.TEST_CTL ================================================= */ +#define FLASHC_FM_CTL_TEST_CTL_TEST_MODE_Pos (0UL) /*!< FLASHC_FM_CTL TEST_CTL: TEST_MODE (Bit 0) */ +#define FLASHC_FM_CTL_TEST_CTL_TEST_MODE_Msk (0x1fUL) /*!< FLASHC_FM_CTL TEST_CTL: TEST_MODE (Bitfield-Mask: 0x1f) */ +#define FLASHC_FM_CTL_TEST_CTL_PN_CTL_Pos (8UL) /*!< FLASHC_FM_CTL TEST_CTL: PN_CTL (Bit 8) */ +#define FLASHC_FM_CTL_TEST_CTL_PN_CTL_Msk (0x100UL) /*!< FLASHC_FM_CTL TEST_CTL: PN_CTL (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TEST_CTL_TM_PE_Pos (9UL) /*!< FLASHC_FM_CTL TEST_CTL: TM_PE (Bit 9) */ +#define FLASHC_FM_CTL_TEST_CTL_TM_PE_Msk (0x200UL) /*!< FLASHC_FM_CTL TEST_CTL: TM_PE (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TEST_CTL_TM_DISPOS_Pos (10UL) /*!< FLASHC_FM_CTL TEST_CTL: TM_DISPOS (Bit 10) */ +#define FLASHC_FM_CTL_TEST_CTL_TM_DISPOS_Msk (0x400UL) /*!< FLASHC_FM_CTL TEST_CTL: TM_DISPOS (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TEST_CTL_TM_DISNEG_Pos (11UL) /*!< FLASHC_FM_CTL TEST_CTL: TM_DISNEG (Bit 11) */ +#define FLASHC_FM_CTL_TEST_CTL_TM_DISNEG_Msk (0x800UL) /*!< FLASHC_FM_CTL TEST_CTL: TM_DISNEG (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TEST_CTL_EN_CLK_MON_Pos (16UL) /*!< FLASHC_FM_CTL TEST_CTL: EN_CLK_MON (Bit 16) */ +#define FLASHC_FM_CTL_TEST_CTL_EN_CLK_MON_Msk (0x10000UL) /*!< FLASHC_FM_CTL TEST_CTL: EN_CLK_MON (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TEST_CTL_CSL_DEBUG_Pos (17UL) /*!< FLASHC_FM_CTL TEST_CTL: CSL_DEBUG (Bit 17) */ +#define FLASHC_FM_CTL_TEST_CTL_CSL_DEBUG_Msk (0x20000UL) /*!< FLASHC_FM_CTL TEST_CTL: CSL_DEBUG (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TEST_CTL_ENABLE_OSC_Pos (18UL) /*!< FLASHC_FM_CTL TEST_CTL: ENABLE_OSC (Bit 18) */ +#define FLASHC_FM_CTL_TEST_CTL_ENABLE_OSC_Msk (0x40000UL) /*!< FLASHC_FM_CTL TEST_CTL: ENABLE_OSC (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_TEST_CTL_UNSCRAMBLE_WA_Pos (31UL) /*!< FLASHC_FM_CTL TEST_CTL: UNSCRAMBLE_WA (Bit 31) */ +#define FLASHC_FM_CTL_TEST_CTL_UNSCRAMBLE_WA_Msk (0x80000000UL) /*!< FLASHC_FM_CTL TEST_CTL: UNSCRAMBLE_WA (Bitfield-Mask: 0x01)*/ +/* ================================================ FLASHC_FM_CTL.WAIT_CTL ================================================= */ +#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Pos (0UL) /*!< FLASHC_FM_CTL WAIT_CTL: WAIT_FM_MEM_RD (Bit 0) */ +#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Msk (0xfUL) /*!< FLASHC_FM_CTL WAIT_CTL: WAIT_FM_MEM_RD (Bitfield-Mask: 0x0f)*/ +#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Pos (8UL) /*!< FLASHC_FM_CTL WAIT_CTL: WAIT_FM_HV_RD (Bit 8) */ +#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Msk (0xf00UL) /*!< FLASHC_FM_CTL WAIT_CTL: WAIT_FM_HV_RD (Bitfield-Mask: 0x0f)*/ +#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Pos (16UL) /*!< FLASHC_FM_CTL WAIT_CTL: WAIT_FM_HV_WR (Bit 16) */ +#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Msk (0x70000UL) /*!< FLASHC_FM_CTL WAIT_CTL: WAIT_FM_HV_WR (Bitfield-Mask: 0x07)*/ +/* ============================================= FLASHC_FM_CTL.MONITOR_STATUS ============================================== */ +#define FLASHC_FM_CTL_MONITOR_STATUS_NEG_PUMP_VLO_Pos (1UL) /*!< FLASHC_FM_CTL MONITOR_STATUS: NEG_PUMP_VLO (Bit 1) */ +#define FLASHC_FM_CTL_MONITOR_STATUS_NEG_PUMP_VLO_Msk (0x2UL) /*!< FLASHC_FM_CTL MONITOR_STATUS: NEG_PUMP_VLO (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_MONITOR_STATUS_POS_PUMP_VHI_Pos (2UL) /*!< FLASHC_FM_CTL MONITOR_STATUS: POS_PUMP_VHI (Bit 2) */ +#define FLASHC_FM_CTL_MONITOR_STATUS_POS_PUMP_VHI_Msk (0x4UL) /*!< FLASHC_FM_CTL MONITOR_STATUS: POS_PUMP_VHI (Bitfield-Mask: 0x01)*/ +/* =============================================== FLASHC_FM_CTL.SCRATCH_CTL =============================================== */ +#define FLASHC_FM_CTL_SCRATCH_CTL_DUMMY32_Pos (0UL) /*!< FLASHC_FM_CTL SCRATCH_CTL: DUMMY32 (Bit 0) */ +#define FLASHC_FM_CTL_SCRATCH_CTL_DUMMY32_Msk (0xffffffffUL) /*!< FLASHC_FM_CTL SCRATCH_CTL: DUMMY32 (Bitfield-Mask: 0xffffffff)*/ +/* ================================================= FLASHC_FM_CTL.HV_CTL ================================================== */ +#define FLASHC_FM_CTL_HV_CTL_TIMER_CLOCK_FREQ_Pos (0UL) /*!< FLASHC_FM_CTL HV_CTL: TIMER_CLOCK_FREQ (Bit 0) */ +#define FLASHC_FM_CTL_HV_CTL_TIMER_CLOCK_FREQ_Msk (0xffUL) /*!< FLASHC_FM_CTL HV_CTL: TIMER_CLOCK_FREQ (Bitfield-Mask: 0xff)*/ +/* ================================================ FLASHC_FM_CTL.ACLK_CTL ================================================= */ +#define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Pos (0UL) /*!< FLASHC_FM_CTL ACLK_CTL: ACLK_GEN (Bit 0) */ +#define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Msk (0x1UL) /*!< FLASHC_FM_CTL ACLK_CTL: ACLK_GEN (Bitfield-Mask: 0x01) */ +/* ================================================== FLASHC_FM_CTL.INTR =================================================== */ +#define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Pos (0UL) /*!< FLASHC_FM_CTL INTR: TIMER_EXPIRED (Bit 0) */ +#define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Msk (0x1UL) /*!< FLASHC_FM_CTL INTR: TIMER_EXPIRED (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC_FM_CTL.INTR_SET ================================================= */ +#define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Pos (0UL) /*!< FLASHC_FM_CTL INTR_SET: TIMER_EXPIRED (Bit 0) */ +#define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Msk (0x1UL) /*!< FLASHC_FM_CTL INTR_SET: TIMER_EXPIRED (Bitfield-Mask: 0x01)*/ +/* ================================================ FLASHC_FM_CTL.INTR_MASK ================================================ */ +#define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Pos (0UL) /*!< FLASHC_FM_CTL INTR_MASK: TIMER_EXPIRED (Bit 0) */ +#define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Msk (0x1UL) /*!< FLASHC_FM_CTL INTR_MASK: TIMER_EXPIRED (Bitfield-Mask: 0x01)*/ +/* =============================================== FLASHC_FM_CTL.INTR_MASKED =============================================== */ +#define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Pos (0UL) /*!< FLASHC_FM_CTL INTR_MASKED: TIMER_EXPIRED (Bit 0) */ +#define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Msk (0x1UL) /*!< FLASHC_FM_CTL INTR_MASKED: TIMER_EXPIRED (Bitfield-Mask: 0x01)*/ +/* ============================================= FLASHC_FM_CTL.FM_HV_DATA_ALL ============================================== */ +#define FLASHC_FM_CTL_FM_HV_DATA_ALL_DATA32_Pos (0UL) /*!< FLASHC_FM_CTL FM_HV_DATA_ALL: DATA32 (Bit 0) */ +#define FLASHC_FM_CTL_FM_HV_DATA_ALL_DATA32_Msk (0xffffffffUL) /*!< FLASHC_FM_CTL FM_HV_DATA_ALL: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ================================================ FLASHC_FM_CTL.CAL_CTL0 ================================================= */ +#define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_LO_HV_Pos (0UL) /*!< FLASHC_FM_CTL CAL_CTL0: VCT_TRIM_LO_HV (Bit 0) */ +#define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_LO_HV_Msk (0x1fUL) /*!< FLASHC_FM_CTL CAL_CTL0: VCT_TRIM_LO_HV (Bitfield-Mask: 0x1f)*/ +#define FLASHC_FM_CTL_CAL_CTL0_CDAC_LO_HV_Pos (5UL) /*!< FLASHC_FM_CTL CAL_CTL0: CDAC_LO_HV (Bit 5) */ +#define FLASHC_FM_CTL_CAL_CTL0_CDAC_LO_HV_Msk (0xe0UL) /*!< FLASHC_FM_CTL CAL_CTL0: CDAC_LO_HV (Bitfield-Mask: 0x07) */ +#define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_LO_HV_Pos (8UL) /*!< FLASHC_FM_CTL CAL_CTL0: VBG_TRIM_LO_HV (Bit 8) */ +#define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_LO_HV_Msk (0x1f00UL) /*!< FLASHC_FM_CTL CAL_CTL0: VBG_TRIM_LO_HV (Bitfield-Mask: 0x1f)*/ +#define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_LO_HV_Pos (13UL) /*!< FLASHC_FM_CTL CAL_CTL0: VBG_TC_TRIM_LO_HV (Bit 13) */ +#define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_LO_HV_Msk (0xe000UL) /*!< FLASHC_FM_CTL CAL_CTL0: VBG_TC_TRIM_LO_HV (Bitfield-Mask: 0x07)*/ +#define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIM_LO_HV_Pos (16UL) /*!< FLASHC_FM_CTL CAL_CTL0: IPREF_TRIM_LO_HV (Bit 16) */ +#define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIM_LO_HV_Msk (0xf0000UL) /*!< FLASHC_FM_CTL CAL_CTL0: IPREF_TRIM_LO_HV (Bitfield-Mask: 0x0f)*/ +/* ================================================ FLASHC_FM_CTL.CAL_CTL1 ================================================= */ +#define FLASHC_FM_CTL_CAL_CTL1_VCT_TRIM_HI_HV_Pos (0UL) /*!< FLASHC_FM_CTL CAL_CTL1: VCT_TRIM_HI_HV (Bit 0) */ +#define FLASHC_FM_CTL_CAL_CTL1_VCT_TRIM_HI_HV_Msk (0x1fUL) /*!< FLASHC_FM_CTL CAL_CTL1: VCT_TRIM_HI_HV (Bitfield-Mask: 0x1f)*/ +#define FLASHC_FM_CTL_CAL_CTL1_CDAC_HI_HV_Pos (5UL) /*!< FLASHC_FM_CTL CAL_CTL1: CDAC_HI_HV (Bit 5) */ +#define FLASHC_FM_CTL_CAL_CTL1_CDAC_HI_HV_Msk (0xe0UL) /*!< FLASHC_FM_CTL CAL_CTL1: CDAC_HI_HV (Bitfield-Mask: 0x07) */ +#define FLASHC_FM_CTL_CAL_CTL1_VBG_TRIM_HI_HV_Pos (8UL) /*!< FLASHC_FM_CTL CAL_CTL1: VBG_TRIM_HI_HV (Bit 8) */ +#define FLASHC_FM_CTL_CAL_CTL1_VBG_TRIM_HI_HV_Msk (0x1f00UL) /*!< FLASHC_FM_CTL CAL_CTL1: VBG_TRIM_HI_HV (Bitfield-Mask: 0x1f)*/ +#define FLASHC_FM_CTL_CAL_CTL1_VBG_TC_TRIM_HI_HV_Pos (13UL) /*!< FLASHC_FM_CTL CAL_CTL1: VBG_TC_TRIM_HI_HV (Bit 13) */ +#define FLASHC_FM_CTL_CAL_CTL1_VBG_TC_TRIM_HI_HV_Msk (0xe000UL) /*!< FLASHC_FM_CTL CAL_CTL1: VBG_TC_TRIM_HI_HV (Bitfield-Mask: 0x07)*/ +#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HI_HV_Pos (16UL) /*!< FLASHC_FM_CTL CAL_CTL1: IPREF_TRIM_HI_HV (Bit 16) */ +#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HI_HV_Msk (0xf0000UL) /*!< FLASHC_FM_CTL CAL_CTL1: IPREF_TRIM_HI_HV (Bitfield-Mask: 0x0f)*/ +/* ================================================ FLASHC_FM_CTL.CAL_CTL2 ================================================= */ +#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_LO_HV_Pos (0UL) /*!< FLASHC_FM_CTL CAL_CTL2: ICREF_TRIM_LO_HV (Bit 0) */ +#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_LO_HV_Msk (0x1fUL) /*!< FLASHC_FM_CTL CAL_CTL2: ICREF_TRIM_LO_HV (Bitfield-Mask: 0x1f)*/ +#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_LO_HV_Pos (5UL) /*!< FLASHC_FM_CTL CAL_CTL2: ICREF_TC_TRIM_LO_HV (Bit 5) */ +#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_LO_HV_Msk (0xe0UL) /*!< FLASHC_FM_CTL CAL_CTL2: ICREF_TC_TRIM_LO_HV (Bitfield-Mask: 0x07)*/ +#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_HI_HV_Pos (8UL) /*!< FLASHC_FM_CTL CAL_CTL2: ICREF_TRIM_HI_HV (Bit 8) */ +#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_HI_HV_Msk (0x1f00UL) /*!< FLASHC_FM_CTL CAL_CTL2: ICREF_TRIM_HI_HV (Bitfield-Mask: 0x1f)*/ +#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_HI_HV_Pos (13UL) /*!< FLASHC_FM_CTL CAL_CTL2: ICREF_TC_TRIM_HI_HV (Bit 13) */ +#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_HI_HV_Msk (0xe000UL) /*!< FLASHC_FM_CTL CAL_CTL2: ICREF_TC_TRIM_HI_HV (Bitfield-Mask: 0x07)*/ +#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_HV_Pos (16UL) /*!< FLASHC_FM_CTL CAL_CTL2: VREF_SEL_HV (Bit 16) */ +#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_HV_Msk (0x10000UL) /*!< FLASHC_FM_CTL CAL_CTL2: VREF_SEL_HV (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_CAL_CTL2_IREF_SEL_HV_Pos (17UL) /*!< FLASHC_FM_CTL CAL_CTL2: IREF_SEL_HV (Bit 17) */ +#define FLASHC_FM_CTL_CAL_CTL2_IREF_SEL_HV_Msk (0x20000UL) /*!< FLASHC_FM_CTL CAL_CTL2: IREF_SEL_HV (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_CAL_CTL2_FM_ACTIVE_HV_Pos (18UL) /*!< FLASHC_FM_CTL CAL_CTL2: FM_ACTIVE_HV (Bit 18) */ +#define FLASHC_FM_CTL_CAL_CTL2_FM_ACTIVE_HV_Msk (0x40000UL) /*!< FLASHC_FM_CTL CAL_CTL2: FM_ACTIVE_HV (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_CAL_CTL2_TURBO_EXT_HV_Pos (19UL) /*!< FLASHC_FM_CTL CAL_CTL2: TURBO_EXT_HV (Bit 19) */ +#define FLASHC_FM_CTL_CAL_CTL2_TURBO_EXT_HV_Msk (0x80000UL) /*!< FLASHC_FM_CTL CAL_CTL2: TURBO_EXT_HV (Bitfield-Mask: 0x01)*/ +/* ================================================ FLASHC_FM_CTL.CAL_CTL3 ================================================= */ +#define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Pos (0UL) /*!< FLASHC_FM_CTL CAL_CTL3: OSC_TRIM_HV (Bit 0) */ +#define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Msk (0xfUL) /*!< FLASHC_FM_CTL CAL_CTL3: OSC_TRIM_HV (Bitfield-Mask: 0x0f) */ +#define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Pos (4UL) /*!< FLASHC_FM_CTL CAL_CTL3: OSC_RANGE_TRIM_HV (Bit 4) */ +#define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Msk (0x10UL) /*!< FLASHC_FM_CTL CAL_CTL3: OSC_RANGE_TRIM_HV (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_CAL_CTL3_IDAC_HV_Pos (5UL) /*!< FLASHC_FM_CTL CAL_CTL3: IDAC_HV (Bit 5) */ +#define FLASHC_FM_CTL_CAL_CTL3_IDAC_HV_Msk (0x1e0UL) /*!< FLASHC_FM_CTL CAL_CTL3: IDAC_HV (Bitfield-Mask: 0x0f) */ +#define FLASHC_FM_CTL_CAL_CTL3_SDAC_HV_Pos (9UL) /*!< FLASHC_FM_CTL CAL_CTL3: SDAC_HV (Bit 9) */ +#define FLASHC_FM_CTL_CAL_CTL3_SDAC_HV_Msk (0x600UL) /*!< FLASHC_FM_CTL CAL_CTL3: SDAC_HV (Bitfield-Mask: 0x03) */ +#define FLASHC_FM_CTL_CAL_CTL3_ITIM_HV_Pos (11UL) /*!< FLASHC_FM_CTL CAL_CTL3: ITIM_HV (Bit 11) */ +#define FLASHC_FM_CTL_CAL_CTL3_ITIM_HV_Msk (0x7800UL) /*!< FLASHC_FM_CTL CAL_CTL3: ITIM_HV (Bitfield-Mask: 0x0f) */ +#define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Pos (15UL) /*!< FLASHC_FM_CTL CAL_CTL3: VDDHI_HV (Bit 15) */ +#define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Msk (0x8000UL) /*!< FLASHC_FM_CTL CAL_CTL3: VDDHI_HV (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Pos (16UL) /*!< FLASHC_FM_CTL CAL_CTL3: TURBO_PULSEW_HV (Bit 16) */ +#define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Msk (0x30000UL) /*!< FLASHC_FM_CTL CAL_CTL3: TURBO_PULSEW_HV (Bitfield-Mask: 0x03)*/ +#define FLASHC_FM_CTL_CAL_CTL3_BGLO_EN_HV_Pos (18UL) /*!< FLASHC_FM_CTL CAL_CTL3: BGLO_EN_HV (Bit 18) */ +#define FLASHC_FM_CTL_CAL_CTL3_BGLO_EN_HV_Msk (0x40000UL) /*!< FLASHC_FM_CTL CAL_CTL3: BGLO_EN_HV (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_CAL_CTL3_BGHI_EN_HV_Pos (19UL) /*!< FLASHC_FM_CTL CAL_CTL3: BGHI_EN_HV (Bit 19) */ +#define FLASHC_FM_CTL_CAL_CTL3_BGHI_EN_HV_Msk (0x80000UL) /*!< FLASHC_FM_CTL CAL_CTL3: BGHI_EN_HV (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC_FM_CTL.BOOKMARK ================================================= */ +#define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Pos (0UL) /*!< FLASHC_FM_CTL BOOKMARK: BOOKMARK (Bit 0) */ +#define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Msk (0xffffffffUL) /*!< FLASHC_FM_CTL BOOKMARK: BOOKMARK (Bitfield-Mask: 0xffffffff)*/ +/* ================================================ FLASHC_FM_CTL.RED_CTL01 ================================================ */ +#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Pos (0UL) /*!< FLASHC_FM_CTL RED_CTL01: RED_ADDR_0 (Bit 0) */ +#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Msk (0xffUL) /*!< FLASHC_FM_CTL RED_CTL01: RED_ADDR_0 (Bitfield-Mask: 0xff) */ +#define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Pos (8UL) /*!< FLASHC_FM_CTL RED_CTL01: RED_EN_0 (Bit 8) */ +#define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Msk (0x100UL) /*!< FLASHC_FM_CTL RED_CTL01: RED_EN_0 (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Pos (16UL) /*!< FLASHC_FM_CTL RED_CTL01: RED_ADDR_1 (Bit 16) */ +#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Msk (0xff0000UL) /*!< FLASHC_FM_CTL RED_CTL01: RED_ADDR_1 (Bitfield-Mask: 0xff) */ +#define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Pos (24UL) /*!< FLASHC_FM_CTL RED_CTL01: RED_EN_1 (Bit 24) */ +#define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Msk (0x1000000UL) /*!< FLASHC_FM_CTL RED_CTL01: RED_EN_1 (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC_FM_CTL.RED_CTL23 ================================================ */ +#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Pos (0UL) /*!< FLASHC_FM_CTL RED_CTL23: RED_ADDR_2 (Bit 0) */ +#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Msk (0xffUL) /*!< FLASHC_FM_CTL RED_CTL23: RED_ADDR_2 (Bitfield-Mask: 0xff) */ +#define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Pos (8UL) /*!< FLASHC_FM_CTL RED_CTL23: RED_EN_2 (Bit 8) */ +#define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Msk (0x100UL) /*!< FLASHC_FM_CTL RED_CTL23: RED_EN_2 (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Pos (16UL) /*!< FLASHC_FM_CTL RED_CTL23: RED_ADDR_3 (Bit 16) */ +#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Msk (0xff0000UL) /*!< FLASHC_FM_CTL RED_CTL23: RED_ADDR_3 (Bitfield-Mask: 0xff) */ +#define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Pos (24UL) /*!< FLASHC_FM_CTL RED_CTL23: RED_EN_3 (Bit 24) */ +#define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Msk (0x1000000UL) /*!< FLASHC_FM_CTL RED_CTL23: RED_EN_3 (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC_FM_CTL.RED_CTL45 ================================================ */ +#define FLASHC_FM_CTL_RED_CTL45_RED_ADDR_4_Pos (0UL) /*!< FLASHC_FM_CTL RED_CTL45: RED_ADDR_4 (Bit 0) */ +#define FLASHC_FM_CTL_RED_CTL45_RED_ADDR_4_Msk (0xffUL) /*!< FLASHC_FM_CTL RED_CTL45: RED_ADDR_4 (Bitfield-Mask: 0xff) */ +#define FLASHC_FM_CTL_RED_CTL45_RED_EN_4_Pos (8UL) /*!< FLASHC_FM_CTL RED_CTL45: RED_EN_4 (Bit 8) */ +#define FLASHC_FM_CTL_RED_CTL45_RED_EN_4_Msk (0x100UL) /*!< FLASHC_FM_CTL RED_CTL45: RED_EN_4 (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_RED_CTL45_RED_ADDR_5_Pos (16UL) /*!< FLASHC_FM_CTL RED_CTL45: RED_ADDR_5 (Bit 16) */ +#define FLASHC_FM_CTL_RED_CTL45_RED_ADDR_5_Msk (0xff0000UL) /*!< FLASHC_FM_CTL RED_CTL45: RED_ADDR_5 (Bitfield-Mask: 0xff) */ +#define FLASHC_FM_CTL_RED_CTL45_RED_EN_5_Pos (24UL) /*!< FLASHC_FM_CTL RED_CTL45: RED_EN_5 (Bit 24) */ +#define FLASHC_FM_CTL_RED_CTL45_RED_EN_5_Msk (0x1000000UL) /*!< FLASHC_FM_CTL RED_CTL45: RED_EN_5 (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC_FM_CTL.RED_CTL67 ================================================ */ +#define FLASHC_FM_CTL_RED_CTL67_RED_ADDR_6_Pos (0UL) /*!< FLASHC_FM_CTL RED_CTL67: RED_ADDR_6 (Bit 0) */ +#define FLASHC_FM_CTL_RED_CTL67_RED_ADDR_6_Msk (0xffUL) /*!< FLASHC_FM_CTL RED_CTL67: RED_ADDR_6 (Bitfield-Mask: 0xff) */ +#define FLASHC_FM_CTL_RED_CTL67_RED_EN_6_Pos (8UL) /*!< FLASHC_FM_CTL RED_CTL67: RED_EN_6 (Bit 8) */ +#define FLASHC_FM_CTL_RED_CTL67_RED_EN_6_Msk (0x100UL) /*!< FLASHC_FM_CTL RED_CTL67: RED_EN_6 (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_RED_CTL67_RED_ADDR_7_Pos (16UL) /*!< FLASHC_FM_CTL RED_CTL67: RED_ADDR_7 (Bit 16) */ +#define FLASHC_FM_CTL_RED_CTL67_RED_ADDR_7_Msk (0xff0000UL) /*!< FLASHC_FM_CTL RED_CTL67: RED_ADDR_7 (Bitfield-Mask: 0xff) */ +#define FLASHC_FM_CTL_RED_CTL67_RED_EN_7_Pos (24UL) /*!< FLASHC_FM_CTL RED_CTL67: RED_EN_7 (Bit 24) */ +#define FLASHC_FM_CTL_RED_CTL67_RED_EN_7_Msk (0x1000000UL) /*!< FLASHC_FM_CTL RED_CTL67: RED_EN_7 (Bitfield-Mask: 0x01) */ +/* ============================================== FLASHC_FM_CTL.RED_CTL_SM01 =============================================== */ +#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM0_Pos (0UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: RED_ADDR_SM0 (Bit 0) */ +#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM0_Msk (0xffUL) /*!< FLASHC_FM_CTL RED_CTL_SM01: RED_ADDR_SM0 (Bitfield-Mask: 0xff)*/ +#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM0_Pos (8UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: RED_EN_SM0 (Bit 8) */ +#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM0_Msk (0x100UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: RED_EN_SM0 (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM1_Pos (16UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: RED_ADDR_SM1 (Bit 16) */ +#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM1_Msk (0xff0000UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: RED_ADDR_SM1 (Bitfield-Mask: 0xff)*/ +#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM1_Pos (24UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: RED_EN_SM1 (Bit 24) */ +#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM1_Msk (0x1000000UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: RED_EN_SM1 (Bitfield-Mask: 0x01)*/ +#define FLASHC_FM_CTL_RED_CTL_SM01_TRKD_Pos (30UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: TRKD (Bit 30) */ +#define FLASHC_FM_CTL_RED_CTL_SM01_TRKD_Msk (0x40000000UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: TRKD (Bitfield-Mask: 0x01) */ +#define FLASHC_FM_CTL_RED_CTL_SM01_R_GRANT_EN_Pos (31UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: R_GRANT_EN (Bit 31) */ +#define FLASHC_FM_CTL_RED_CTL_SM01_R_GRANT_EN_Msk (0x80000000UL) /*!< FLASHC_FM_CTL RED_CTL_SM01: R_GRANT_EN (Bitfield-Mask: 0x01)*/ +/* ================================================= FLASHC_FM_CTL.TM_CMPR ================================================= */ +#define FLASHC_FM_CTL_TM_CMPR_DATA_COMP_RESULT_Pos (0UL) /*!< FLASHC_FM_CTL TM_CMPR: DATA_COMP_RESULT (Bit 0) */ +#define FLASHC_FM_CTL_TM_CMPR_DATA_COMP_RESULT_Msk (0x1UL) /*!< FLASHC_FM_CTL TM_CMPR: DATA_COMP_RESULT (Bitfield-Mask: 0x01)*/ +/* =============================================== FLASHC_FM_CTL.FM_HV_DATA ================================================ */ +#define FLASHC_FM_CTL_FM_HV_DATA_DATA32_Pos (0UL) /*!< FLASHC_FM_CTL FM_HV_DATA: DATA32 (Bit 0) */ +#define FLASHC_FM_CTL_FM_HV_DATA_DATA32_Msk (0xffffffffUL) /*!< FLASHC_FM_CTL FM_HV_DATA: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* =============================================== FLASHC_FM_CTL.FM_MEM_DATA =============================================== */ +#define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Pos (0UL) /*!< FLASHC_FM_CTL FM_MEM_DATA: DATA32 (Bit 0) */ +#define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Msk (0xffffffffUL) /*!< FLASHC_FM_CTL FM_MEM_DATA: DATA32 (Bitfield-Mask: 0xffffffff)*/ + + +/* =================================================== FLASHC.FLASH_CTL ==================================================== */ +#define FLASHC_FLASH_CTL_MAIN_WS_Pos (0UL) /*!< FLASHC FLASH_CTL: MAIN_WS (Bit 0) */ +#define FLASHC_FLASH_CTL_MAIN_WS_Msk (0xfUL) /*!< FLASHC FLASH_CTL: MAIN_WS (Bitfield-Mask: 0x0f) */ +#define FLASHC_FLASH_CTL_REMAP_Pos (8UL) /*!< FLASHC FLASH_CTL: REMAP (Bit 8) */ +#define FLASHC_FLASH_CTL_REMAP_Msk (0x100UL) /*!< FLASHC FLASH_CTL: REMAP (Bitfield-Mask: 0x01) */ +/* ================================================= FLASHC.FLASH_PWR_CTL ================================================== */ +#define FLASHC_FLASH_PWR_CTL_ENABLE_Pos (0UL) /*!< FLASHC FLASH_PWR_CTL: ENABLE (Bit 0) */ +#define FLASHC_FLASH_PWR_CTL_ENABLE_Msk (0x1UL) /*!< FLASHC FLASH_PWR_CTL: ENABLE (Bitfield-Mask: 0x01) */ +#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Pos (1UL) /*!< FLASHC FLASH_PWR_CTL: ENABLE_HV (Bit 1) */ +#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Msk (0x2UL) /*!< FLASHC FLASH_PWR_CTL: ENABLE_HV (Bitfield-Mask: 0x01) */ +/* =================================================== FLASHC.FLASH_CMD ==================================================== */ +#define FLASHC_FLASH_CMD_INV_Pos (0UL) /*!< FLASHC FLASH_CMD: INV (Bit 0) */ +#define FLASHC_FLASH_CMD_INV_Msk (0x1UL) /*!< FLASHC FLASH_CMD: INV (Bitfield-Mask: 0x01) */ +/* ================================================== FLASHC.CM0_CA_CTL0 =================================================== */ +#define FLASHC_CM0_CA_CTL0_WAY_Pos (16UL) /*!< FLASHC CM0_CA_CTL0: WAY (Bit 16) */ +#define FLASHC_CM0_CA_CTL0_WAY_Msk (0x30000UL) /*!< FLASHC CM0_CA_CTL0: WAY (Bitfield-Mask: 0x03) */ +#define FLASHC_CM0_CA_CTL0_SET_ADDR_Pos (24UL) /*!< FLASHC CM0_CA_CTL0: SET_ADDR (Bit 24) */ +#define FLASHC_CM0_CA_CTL0_SET_ADDR_Msk (0x7000000UL) /*!< FLASHC CM0_CA_CTL0: SET_ADDR (Bitfield-Mask: 0x07) */ +#define FLASHC_CM0_CA_CTL0_PREF_EN_Pos (30UL) /*!< FLASHC CM0_CA_CTL0: PREF_EN (Bit 30) */ +#define FLASHC_CM0_CA_CTL0_PREF_EN_Msk (0x40000000UL) /*!< FLASHC CM0_CA_CTL0: PREF_EN (Bitfield-Mask: 0x01) */ +#define FLASHC_CM0_CA_CTL0_ENABLED_Pos (31UL) /*!< FLASHC CM0_CA_CTL0: ENABLED (Bit 31) */ +#define FLASHC_CM0_CA_CTL0_ENABLED_Msk (0x80000000UL) /*!< FLASHC CM0_CA_CTL0: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================== FLASHC.CM0_CA_CTL1 =================================================== */ +#define FLASHC_CM0_CA_CTL1_ISOLATE_Pos (0UL) /*!< FLASHC CM0_CA_CTL1: ISOLATE (Bit 0) */ +#define FLASHC_CM0_CA_CTL1_ISOLATE_Msk (0x1UL) /*!< FLASHC CM0_CA_CTL1: ISOLATE (Bitfield-Mask: 0x01) */ +#define FLASHC_CM0_CA_CTL1_RETAIN_Pos (1UL) /*!< FLASHC CM0_CA_CTL1: RETAIN (Bit 1) */ +#define FLASHC_CM0_CA_CTL1_RETAIN_Msk (0x2UL) /*!< FLASHC CM0_CA_CTL1: RETAIN (Bitfield-Mask: 0x01) */ +#define FLASHC_CM0_CA_CTL1_POWER_Pos (2UL) /*!< FLASHC CM0_CA_CTL1: POWER (Bit 2) */ +#define FLASHC_CM0_CA_CTL1_POWER_Msk (0x4UL) /*!< FLASHC CM0_CA_CTL1: POWER (Bitfield-Mask: 0x01) */ +/* =================================================== FLASHC.CM0_CA_CMD =================================================== */ +#define FLASHC_CM0_CA_CMD_INV_Pos (0UL) /*!< FLASHC CM0_CA_CMD: INV (Bit 0) */ +#define FLASHC_CM0_CA_CMD_INV_Msk (0x1UL) /*!< FLASHC CM0_CA_CMD: INV (Bitfield-Mask: 0x01) */ +/* ================================================= FLASHC.CM0_CA_STATUS0 ================================================= */ +#define FLASHC_CM0_CA_STATUS0_VALID16_Pos (0UL) /*!< FLASHC CM0_CA_STATUS0: VALID16 (Bit 0) */ +#define FLASHC_CM0_CA_STATUS0_VALID16_Msk (0xffffUL) /*!< FLASHC CM0_CA_STATUS0: VALID16 (Bitfield-Mask: 0xffff) */ +/* ================================================= FLASHC.CM0_CA_STATUS1 ================================================= */ +#define FLASHC_CM0_CA_STATUS1_TAG_Pos (0UL) /*!< FLASHC CM0_CA_STATUS1: TAG (Bit 0) */ +#define FLASHC_CM0_CA_STATUS1_TAG_Msk (0xffffffffUL) /*!< FLASHC CM0_CA_STATUS1: TAG (Bitfield-Mask: 0xffffffff) */ +/* ================================================= FLASHC.CM0_CA_STATUS2 ================================================= */ +#define FLASHC_CM0_CA_STATUS2_LRU_Pos (0UL) /*!< FLASHC CM0_CA_STATUS2: LRU (Bit 0) */ +#define FLASHC_CM0_CA_STATUS2_LRU_Msk (0x3fUL) /*!< FLASHC CM0_CA_STATUS2: LRU (Bitfield-Mask: 0x3f) */ +/* ================================================== FLASHC.CM4_CA_CTL0 =================================================== */ +#define FLASHC_CM4_CA_CTL0_WAY_Pos (16UL) /*!< FLASHC CM4_CA_CTL0: WAY (Bit 16) */ +#define FLASHC_CM4_CA_CTL0_WAY_Msk (0x30000UL) /*!< FLASHC CM4_CA_CTL0: WAY (Bitfield-Mask: 0x03) */ +#define FLASHC_CM4_CA_CTL0_SET_ADDR_Pos (24UL) /*!< FLASHC CM4_CA_CTL0: SET_ADDR (Bit 24) */ +#define FLASHC_CM4_CA_CTL0_SET_ADDR_Msk (0x7000000UL) /*!< FLASHC CM4_CA_CTL0: SET_ADDR (Bitfield-Mask: 0x07) */ +#define FLASHC_CM4_CA_CTL0_PREF_EN_Pos (30UL) /*!< FLASHC CM4_CA_CTL0: PREF_EN (Bit 30) */ +#define FLASHC_CM4_CA_CTL0_PREF_EN_Msk (0x40000000UL) /*!< FLASHC CM4_CA_CTL0: PREF_EN (Bitfield-Mask: 0x01) */ +#define FLASHC_CM4_CA_CTL0_ENABLED_Pos (31UL) /*!< FLASHC CM4_CA_CTL0: ENABLED (Bit 31) */ +#define FLASHC_CM4_CA_CTL0_ENABLED_Msk (0x80000000UL) /*!< FLASHC CM4_CA_CTL0: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================== FLASHC.CM4_CA_CTL1 =================================================== */ +#define FLASHC_CM4_CA_CTL1_ISOLATE_Pos (0UL) /*!< FLASHC CM4_CA_CTL1: ISOLATE (Bit 0) */ +#define FLASHC_CM4_CA_CTL1_ISOLATE_Msk (0x1UL) /*!< FLASHC CM4_CA_CTL1: ISOLATE (Bitfield-Mask: 0x01) */ +#define FLASHC_CM4_CA_CTL1_RETAIN_Pos (1UL) /*!< FLASHC CM4_CA_CTL1: RETAIN (Bit 1) */ +#define FLASHC_CM4_CA_CTL1_RETAIN_Msk (0x2UL) /*!< FLASHC CM4_CA_CTL1: RETAIN (Bitfield-Mask: 0x01) */ +#define FLASHC_CM4_CA_CTL1_POWER_Pos (2UL) /*!< FLASHC CM4_CA_CTL1: POWER (Bit 2) */ +#define FLASHC_CM4_CA_CTL1_POWER_Msk (0x4UL) /*!< FLASHC CM4_CA_CTL1: POWER (Bitfield-Mask: 0x01) */ +/* =================================================== FLASHC.CM4_CA_CMD =================================================== */ +#define FLASHC_CM4_CA_CMD_INV_Pos (0UL) /*!< FLASHC CM4_CA_CMD: INV (Bit 0) */ +#define FLASHC_CM4_CA_CMD_INV_Msk (0x1UL) /*!< FLASHC CM4_CA_CMD: INV (Bitfield-Mask: 0x01) */ +/* ================================================= FLASHC.CM4_CA_STATUS0 ================================================= */ +#define FLASHC_CM4_CA_STATUS0_VALID16_Pos (0UL) /*!< FLASHC CM4_CA_STATUS0: VALID16 (Bit 0) */ +#define FLASHC_CM4_CA_STATUS0_VALID16_Msk (0xffffUL) /*!< FLASHC CM4_CA_STATUS0: VALID16 (Bitfield-Mask: 0xffff) */ +/* ================================================= FLASHC.CM4_CA_STATUS1 ================================================= */ +#define FLASHC_CM4_CA_STATUS1_TAG_Pos (0UL) /*!< FLASHC CM4_CA_STATUS1: TAG (Bit 0) */ +#define FLASHC_CM4_CA_STATUS1_TAG_Msk (0xffffffffUL) /*!< FLASHC CM4_CA_STATUS1: TAG (Bitfield-Mask: 0xffffffff) */ +/* ================================================= FLASHC.CM4_CA_STATUS2 ================================================= */ +#define FLASHC_CM4_CA_STATUS2_LRU_Pos (0UL) /*!< FLASHC CM4_CA_STATUS2: LRU (Bit 0) */ +#define FLASHC_CM4_CA_STATUS2_LRU_Msk (0x3fUL) /*!< FLASHC CM4_CA_STATUS2: LRU (Bitfield-Mask: 0x3f) */ +/* ================================================ FLASHC.CRYPTO_BUFF_CTL ================================================= */ +#define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Pos (30UL) /*!< FLASHC CRYPTO_BUFF_CTL: PREF_EN (Bit 30) */ +#define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Msk (0x40000000UL) /*!< FLASHC CRYPTO_BUFF_CTL: PREF_EN (Bitfield-Mask: 0x01) */ +#define FLASHC_CRYPTO_BUFF_CTL_ENABLED_Pos (31UL) /*!< FLASHC CRYPTO_BUFF_CTL: ENABLED (Bit 31) */ +#define FLASHC_CRYPTO_BUFF_CTL_ENABLED_Msk (0x80000000UL) /*!< FLASHC CRYPTO_BUFF_CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC.CRYPTO_BUFF_CMD ================================================= */ +#define FLASHC_CRYPTO_BUFF_CMD_INV_Pos (0UL) /*!< FLASHC CRYPTO_BUFF_CMD: INV (Bit 0) */ +#define FLASHC_CRYPTO_BUFF_CMD_INV_Msk (0x1UL) /*!< FLASHC CRYPTO_BUFF_CMD: INV (Bitfield-Mask: 0x01) */ +/* ================================================== FLASHC.DW0_BUFF_CTL ================================================== */ +#define FLASHC_DW0_BUFF_CTL_PREF_EN_Pos (30UL) /*!< FLASHC DW0_BUFF_CTL: PREF_EN (Bit 30) */ +#define FLASHC_DW0_BUFF_CTL_PREF_EN_Msk (0x40000000UL) /*!< FLASHC DW0_BUFF_CTL: PREF_EN (Bitfield-Mask: 0x01) */ +#define FLASHC_DW0_BUFF_CTL_ENABLED_Pos (31UL) /*!< FLASHC DW0_BUFF_CTL: ENABLED (Bit 31) */ +#define FLASHC_DW0_BUFF_CTL_ENABLED_Msk (0x80000000UL) /*!< FLASHC DW0_BUFF_CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================== FLASHC.DW0_BUFF_CMD ================================================== */ +#define FLASHC_DW0_BUFF_CMD_INV_Pos (0UL) /*!< FLASHC DW0_BUFF_CMD: INV (Bit 0) */ +#define FLASHC_DW0_BUFF_CMD_INV_Msk (0x1UL) /*!< FLASHC DW0_BUFF_CMD: INV (Bitfield-Mask: 0x01) */ +/* ================================================== FLASHC.DW1_BUFF_CTL ================================================== */ +#define FLASHC_DW1_BUFF_CTL_PREF_EN_Pos (30UL) /*!< FLASHC DW1_BUFF_CTL: PREF_EN (Bit 30) */ +#define FLASHC_DW1_BUFF_CTL_PREF_EN_Msk (0x40000000UL) /*!< FLASHC DW1_BUFF_CTL: PREF_EN (Bitfield-Mask: 0x01) */ +#define FLASHC_DW1_BUFF_CTL_ENABLED_Pos (31UL) /*!< FLASHC DW1_BUFF_CTL: ENABLED (Bit 31) */ +#define FLASHC_DW1_BUFF_CTL_ENABLED_Msk (0x80000000UL) /*!< FLASHC DW1_BUFF_CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================== FLASHC.DW1_BUFF_CMD ================================================== */ +#define FLASHC_DW1_BUFF_CMD_INV_Pos (0UL) /*!< FLASHC DW1_BUFF_CMD: INV (Bit 0) */ +#define FLASHC_DW1_BUFF_CMD_INV_Msk (0x1UL) /*!< FLASHC DW1_BUFF_CMD: INV (Bitfield-Mask: 0x01) */ +/* ================================================== FLASHC.DAP_BUFF_CTL ================================================== */ +#define FLASHC_DAP_BUFF_CTL_PREF_EN_Pos (30UL) /*!< FLASHC DAP_BUFF_CTL: PREF_EN (Bit 30) */ +#define FLASHC_DAP_BUFF_CTL_PREF_EN_Msk (0x40000000UL) /*!< FLASHC DAP_BUFF_CTL: PREF_EN (Bitfield-Mask: 0x01) */ +#define FLASHC_DAP_BUFF_CTL_ENABLED_Pos (31UL) /*!< FLASHC DAP_BUFF_CTL: ENABLED (Bit 31) */ +#define FLASHC_DAP_BUFF_CTL_ENABLED_Msk (0x80000000UL) /*!< FLASHC DAP_BUFF_CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================== FLASHC.DAP_BUFF_CMD ================================================== */ +#define FLASHC_DAP_BUFF_CMD_INV_Pos (0UL) /*!< FLASHC DAP_BUFF_CMD: INV (Bit 0) */ +#define FLASHC_DAP_BUFF_CMD_INV_Msk (0x1UL) /*!< FLASHC DAP_BUFF_CMD: INV (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC.EXT_MS0_BUFF_CTL ================================================ */ +#define FLASHC_EXT_MS0_BUFF_CTL_PREF_EN_Pos (30UL) /*!< FLASHC EXT_MS0_BUFF_CTL: PREF_EN (Bit 30) */ +#define FLASHC_EXT_MS0_BUFF_CTL_PREF_EN_Msk (0x40000000UL) /*!< FLASHC EXT_MS0_BUFF_CTL: PREF_EN (Bitfield-Mask: 0x01) */ +#define FLASHC_EXT_MS0_BUFF_CTL_ENABLED_Pos (31UL) /*!< FLASHC EXT_MS0_BUFF_CTL: ENABLED (Bit 31) */ +#define FLASHC_EXT_MS0_BUFF_CTL_ENABLED_Msk (0x80000000UL) /*!< FLASHC EXT_MS0_BUFF_CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC.EXT_MS0_BUFF_CMD ================================================ */ +#define FLASHC_EXT_MS0_BUFF_CMD_INV_Pos (0UL) /*!< FLASHC EXT_MS0_BUFF_CMD: INV (Bit 0) */ +#define FLASHC_EXT_MS0_BUFF_CMD_INV_Msk (0x1UL) /*!< FLASHC EXT_MS0_BUFF_CMD: INV (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC.EXT_MS1_BUFF_CTL ================================================ */ +#define FLASHC_EXT_MS1_BUFF_CTL_PREF_EN_Pos (30UL) /*!< FLASHC EXT_MS1_BUFF_CTL: PREF_EN (Bit 30) */ +#define FLASHC_EXT_MS1_BUFF_CTL_PREF_EN_Msk (0x40000000UL) /*!< FLASHC EXT_MS1_BUFF_CTL: PREF_EN (Bitfield-Mask: 0x01) */ +#define FLASHC_EXT_MS1_BUFF_CTL_ENABLED_Pos (31UL) /*!< FLASHC EXT_MS1_BUFF_CTL: ENABLED (Bit 31) */ +#define FLASHC_EXT_MS1_BUFF_CTL_ENABLED_Msk (0x80000000UL) /*!< FLASHC EXT_MS1_BUFF_CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================ FLASHC.EXT_MS1_BUFF_CMD ================================================ */ +#define FLASHC_EXT_MS1_BUFF_CMD_INV_Pos (0UL) /*!< FLASHC EXT_MS1_BUFF_CMD: INV (Bit 0) */ +#define FLASHC_EXT_MS1_BUFF_CMD_INV_Msk (0x1UL) /*!< FLASHC EXT_MS1_BUFF_CMD: INV (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_FLASHC_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_gpio.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_gpio.h new file mode 100644 index 0000000000..02ef325503 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_gpio.h @@ -0,0 +1,468 @@ +/***************************************************************************//** +* \file cyip_gpio.h +* +* \brief +* GPIO IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_GPIO_H_ +#define _CYIP_GPIO_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +#define GPIO_PRT_SECTION_SIZE 0x00000080UL +#define GPIO_SECTION_SIZE 0x00010000UL + +/** + * \brief GPIO port registers (GPIO_PRT) + */ +typedef struct { + __IOM uint32_t OUT; /*!< 0x00000000 Port output data register */ + __IOM uint32_t OUT_CLR; /*!< 0x00000004 Port output data set register */ + __IOM uint32_t OUT_SET; /*!< 0x00000008 Port output data clear register */ + __IOM uint32_t OUT_INV; /*!< 0x0000000C Port output data invert register */ + __IM uint32_t IN; /*!< 0x00000010 Port input state register */ + __IOM uint32_t INTR; /*!< 0x00000014 Port interrupt status register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000018 Port interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x0000001C Port interrupt masked status register */ + __IOM uint32_t INTR_SET; /*!< 0x00000020 Port interrupt set register */ + __IOM uint32_t INTR_CFG; /*!< 0x00000024 Port interrupt configuration register */ + __IOM uint32_t CFG; /*!< 0x00000028 Port configuration register */ + __IOM uint32_t CFG_IN; /*!< 0x0000002C Port input buffer configuration register */ + __IOM uint32_t CFG_OUT; /*!< 0x00000030 Port output buffer configuration register */ + __IOM uint32_t CFG_SIO; /*!< 0x00000034 Port SIO configuration register */ + __IM uint32_t RESERVED; + __IOM uint32_t CFG_IN_GPIO5V; /*!< 0x0000003C Port GPIO5V input buffer configuration register */ + __IM uint32_t RESERVED1[16]; +} GPIO_PRT_Type; /*!< Size = 64 (0x40) */ + +/** + * \brief GPIO port control/configuration (GPIO) + */ +typedef struct { /*!< GPIO Structure */ + GPIO_PRT_Type PRT[128]; /*!< 0x00000000 GPIO port registers */ + __IM uint32_t INTR_CAUSE0; /*!< 0x00004000 Interrupt port cause register 0 */ + __IM uint32_t INTR_CAUSE1; /*!< 0x00004004 Interrupt port cause register 1 */ + __IM uint32_t INTR_CAUSE2; /*!< 0x00004008 Interrupt port cause register 2 */ + __IM uint32_t INTR_CAUSE3; /*!< 0x0000400C Interrupt port cause register 3 */ + __IM uint32_t VDD_ACTIVE; /*!< 0x00004010 Extern power supply detection register */ + __IOM uint32_t VDD_INTR; /*!< 0x00004014 Supply detection interrupt register */ + __IOM uint32_t VDD_INTR_MASK; /*!< 0x00004018 Supply detection interrupt mask register */ + __IM uint32_t VDD_INTR_MASKED; /*!< 0x0000401C Supply detection interrupt masked register */ + __IOM uint32_t VDD_INTR_SET; /*!< 0x00004020 Supply detection interrupt set register */ +} GPIO_Type; /*!< Size = 16420 (0x4024) */ + + +/* ===================================================== GPIO_PRT.OUT ====================================================== */ +#define GPIO_PRT_OUT_OUT0_Pos (0UL) /*!< GPIO_PRT OUT: OUT0 (Bit 0) */ +#define GPIO_PRT_OUT_OUT0_Msk (0x1UL) /*!< GPIO_PRT OUT: OUT0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_OUT1_Pos (1UL) /*!< GPIO_PRT OUT: OUT1 (Bit 1) */ +#define GPIO_PRT_OUT_OUT1_Msk (0x2UL) /*!< GPIO_PRT OUT: OUT1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_OUT2_Pos (2UL) /*!< GPIO_PRT OUT: OUT2 (Bit 2) */ +#define GPIO_PRT_OUT_OUT2_Msk (0x4UL) /*!< GPIO_PRT OUT: OUT2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_OUT3_Pos (3UL) /*!< GPIO_PRT OUT: OUT3 (Bit 3) */ +#define GPIO_PRT_OUT_OUT3_Msk (0x8UL) /*!< GPIO_PRT OUT: OUT3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_OUT4_Pos (4UL) /*!< GPIO_PRT OUT: OUT4 (Bit 4) */ +#define GPIO_PRT_OUT_OUT4_Msk (0x10UL) /*!< GPIO_PRT OUT: OUT4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_OUT5_Pos (5UL) /*!< GPIO_PRT OUT: OUT5 (Bit 5) */ +#define GPIO_PRT_OUT_OUT5_Msk (0x20UL) /*!< GPIO_PRT OUT: OUT5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_OUT6_Pos (6UL) /*!< GPIO_PRT OUT: OUT6 (Bit 6) */ +#define GPIO_PRT_OUT_OUT6_Msk (0x40UL) /*!< GPIO_PRT OUT: OUT6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_OUT7_Pos (7UL) /*!< GPIO_PRT OUT: OUT7 (Bit 7) */ +#define GPIO_PRT_OUT_OUT7_Msk (0x80UL) /*!< GPIO_PRT OUT: OUT7 (Bitfield-Mask: 0x01) */ +/* =================================================== GPIO_PRT.OUT_CLR ==================================================== */ +#define GPIO_PRT_OUT_CLR_OUT0_Pos (0UL) /*!< GPIO_PRT OUT_CLR: OUT0 (Bit 0) */ +#define GPIO_PRT_OUT_CLR_OUT0_Msk (0x1UL) /*!< GPIO_PRT OUT_CLR: OUT0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_CLR_OUT1_Pos (1UL) /*!< GPIO_PRT OUT_CLR: OUT1 (Bit 1) */ +#define GPIO_PRT_OUT_CLR_OUT1_Msk (0x2UL) /*!< GPIO_PRT OUT_CLR: OUT1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_CLR_OUT2_Pos (2UL) /*!< GPIO_PRT OUT_CLR: OUT2 (Bit 2) */ +#define GPIO_PRT_OUT_CLR_OUT2_Msk (0x4UL) /*!< GPIO_PRT OUT_CLR: OUT2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_CLR_OUT3_Pos (3UL) /*!< GPIO_PRT OUT_CLR: OUT3 (Bit 3) */ +#define GPIO_PRT_OUT_CLR_OUT3_Msk (0x8UL) /*!< GPIO_PRT OUT_CLR: OUT3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_CLR_OUT4_Pos (4UL) /*!< GPIO_PRT OUT_CLR: OUT4 (Bit 4) */ +#define GPIO_PRT_OUT_CLR_OUT4_Msk (0x10UL) /*!< GPIO_PRT OUT_CLR: OUT4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_CLR_OUT5_Pos (5UL) /*!< GPIO_PRT OUT_CLR: OUT5 (Bit 5) */ +#define GPIO_PRT_OUT_CLR_OUT5_Msk (0x20UL) /*!< GPIO_PRT OUT_CLR: OUT5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_CLR_OUT6_Pos (6UL) /*!< GPIO_PRT OUT_CLR: OUT6 (Bit 6) */ +#define GPIO_PRT_OUT_CLR_OUT6_Msk (0x40UL) /*!< GPIO_PRT OUT_CLR: OUT6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_CLR_OUT7_Pos (7UL) /*!< GPIO_PRT OUT_CLR: OUT7 (Bit 7) */ +#define GPIO_PRT_OUT_CLR_OUT7_Msk (0x80UL) /*!< GPIO_PRT OUT_CLR: OUT7 (Bitfield-Mask: 0x01) */ +/* =================================================== GPIO_PRT.OUT_SET ==================================================== */ +#define GPIO_PRT_OUT_SET_OUT0_Pos (0UL) /*!< GPIO_PRT OUT_SET: OUT0 (Bit 0) */ +#define GPIO_PRT_OUT_SET_OUT0_Msk (0x1UL) /*!< GPIO_PRT OUT_SET: OUT0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_SET_OUT1_Pos (1UL) /*!< GPIO_PRT OUT_SET: OUT1 (Bit 1) */ +#define GPIO_PRT_OUT_SET_OUT1_Msk (0x2UL) /*!< GPIO_PRT OUT_SET: OUT1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_SET_OUT2_Pos (2UL) /*!< GPIO_PRT OUT_SET: OUT2 (Bit 2) */ +#define GPIO_PRT_OUT_SET_OUT2_Msk (0x4UL) /*!< GPIO_PRT OUT_SET: OUT2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_SET_OUT3_Pos (3UL) /*!< GPIO_PRT OUT_SET: OUT3 (Bit 3) */ +#define GPIO_PRT_OUT_SET_OUT3_Msk (0x8UL) /*!< GPIO_PRT OUT_SET: OUT3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_SET_OUT4_Pos (4UL) /*!< GPIO_PRT OUT_SET: OUT4 (Bit 4) */ +#define GPIO_PRT_OUT_SET_OUT4_Msk (0x10UL) /*!< GPIO_PRT OUT_SET: OUT4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_SET_OUT5_Pos (5UL) /*!< GPIO_PRT OUT_SET: OUT5 (Bit 5) */ +#define GPIO_PRT_OUT_SET_OUT5_Msk (0x20UL) /*!< GPIO_PRT OUT_SET: OUT5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_SET_OUT6_Pos (6UL) /*!< GPIO_PRT OUT_SET: OUT6 (Bit 6) */ +#define GPIO_PRT_OUT_SET_OUT6_Msk (0x40UL) /*!< GPIO_PRT OUT_SET: OUT6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_SET_OUT7_Pos (7UL) /*!< GPIO_PRT OUT_SET: OUT7 (Bit 7) */ +#define GPIO_PRT_OUT_SET_OUT7_Msk (0x80UL) /*!< GPIO_PRT OUT_SET: OUT7 (Bitfield-Mask: 0x01) */ +/* =================================================== GPIO_PRT.OUT_INV ==================================================== */ +#define GPIO_PRT_OUT_INV_OUT0_Pos (0UL) /*!< GPIO_PRT OUT_INV: OUT0 (Bit 0) */ +#define GPIO_PRT_OUT_INV_OUT0_Msk (0x1UL) /*!< GPIO_PRT OUT_INV: OUT0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_INV_OUT1_Pos (1UL) /*!< GPIO_PRT OUT_INV: OUT1 (Bit 1) */ +#define GPIO_PRT_OUT_INV_OUT1_Msk (0x2UL) /*!< GPIO_PRT OUT_INV: OUT1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_INV_OUT2_Pos (2UL) /*!< GPIO_PRT OUT_INV: OUT2 (Bit 2) */ +#define GPIO_PRT_OUT_INV_OUT2_Msk (0x4UL) /*!< GPIO_PRT OUT_INV: OUT2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_INV_OUT3_Pos (3UL) /*!< GPIO_PRT OUT_INV: OUT3 (Bit 3) */ +#define GPIO_PRT_OUT_INV_OUT3_Msk (0x8UL) /*!< GPIO_PRT OUT_INV: OUT3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_INV_OUT4_Pos (4UL) /*!< GPIO_PRT OUT_INV: OUT4 (Bit 4) */ +#define GPIO_PRT_OUT_INV_OUT4_Msk (0x10UL) /*!< GPIO_PRT OUT_INV: OUT4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_INV_OUT5_Pos (5UL) /*!< GPIO_PRT OUT_INV: OUT5 (Bit 5) */ +#define GPIO_PRT_OUT_INV_OUT5_Msk (0x20UL) /*!< GPIO_PRT OUT_INV: OUT5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_INV_OUT6_Pos (6UL) /*!< GPIO_PRT OUT_INV: OUT6 (Bit 6) */ +#define GPIO_PRT_OUT_INV_OUT6_Msk (0x40UL) /*!< GPIO_PRT OUT_INV: OUT6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_OUT_INV_OUT7_Pos (7UL) /*!< GPIO_PRT OUT_INV: OUT7 (Bit 7) */ +#define GPIO_PRT_OUT_INV_OUT7_Msk (0x80UL) /*!< GPIO_PRT OUT_INV: OUT7 (Bitfield-Mask: 0x01) */ +/* ====================================================== GPIO_PRT.IN ====================================================== */ +#define GPIO_PRT_IN_IN0_Pos (0UL) /*!< GPIO_PRT IN: IN0 (Bit 0) */ +#define GPIO_PRT_IN_IN0_Msk (0x1UL) /*!< GPIO_PRT IN: IN0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_IN_IN1_Pos (1UL) /*!< GPIO_PRT IN: IN1 (Bit 1) */ +#define GPIO_PRT_IN_IN1_Msk (0x2UL) /*!< GPIO_PRT IN: IN1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_IN_IN2_Pos (2UL) /*!< GPIO_PRT IN: IN2 (Bit 2) */ +#define GPIO_PRT_IN_IN2_Msk (0x4UL) /*!< GPIO_PRT IN: IN2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_IN_IN3_Pos (3UL) /*!< GPIO_PRT IN: IN3 (Bit 3) */ +#define GPIO_PRT_IN_IN3_Msk (0x8UL) /*!< GPIO_PRT IN: IN3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_IN_IN4_Pos (4UL) /*!< GPIO_PRT IN: IN4 (Bit 4) */ +#define GPIO_PRT_IN_IN4_Msk (0x10UL) /*!< GPIO_PRT IN: IN4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_IN_IN5_Pos (5UL) /*!< GPIO_PRT IN: IN5 (Bit 5) */ +#define GPIO_PRT_IN_IN5_Msk (0x20UL) /*!< GPIO_PRT IN: IN5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_IN_IN6_Pos (6UL) /*!< GPIO_PRT IN: IN6 (Bit 6) */ +#define GPIO_PRT_IN_IN6_Msk (0x40UL) /*!< GPIO_PRT IN: IN6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_IN_IN7_Pos (7UL) /*!< GPIO_PRT IN: IN7 (Bit 7) */ +#define GPIO_PRT_IN_IN7_Msk (0x80UL) /*!< GPIO_PRT IN: IN7 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_IN_FLT_IN_Pos (8UL) /*!< GPIO_PRT IN: FLT_IN (Bit 8) */ +#define GPIO_PRT_IN_FLT_IN_Msk (0x100UL) /*!< GPIO_PRT IN: FLT_IN (Bitfield-Mask: 0x01) */ +/* ===================================================== GPIO_PRT.INTR ===================================================== */ +#define GPIO_PRT_INTR_EDGE0_Pos (0UL) /*!< GPIO_PRT INTR: EDGE0 (Bit 0) */ +#define GPIO_PRT_INTR_EDGE0_Msk (0x1UL) /*!< GPIO_PRT INTR: EDGE0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_EDGE1_Pos (1UL) /*!< GPIO_PRT INTR: EDGE1 (Bit 1) */ +#define GPIO_PRT_INTR_EDGE1_Msk (0x2UL) /*!< GPIO_PRT INTR: EDGE1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_EDGE2_Pos (2UL) /*!< GPIO_PRT INTR: EDGE2 (Bit 2) */ +#define GPIO_PRT_INTR_EDGE2_Msk (0x4UL) /*!< GPIO_PRT INTR: EDGE2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_EDGE3_Pos (3UL) /*!< GPIO_PRT INTR: EDGE3 (Bit 3) */ +#define GPIO_PRT_INTR_EDGE3_Msk (0x8UL) /*!< GPIO_PRT INTR: EDGE3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_EDGE4_Pos (4UL) /*!< GPIO_PRT INTR: EDGE4 (Bit 4) */ +#define GPIO_PRT_INTR_EDGE4_Msk (0x10UL) /*!< GPIO_PRT INTR: EDGE4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_EDGE5_Pos (5UL) /*!< GPIO_PRT INTR: EDGE5 (Bit 5) */ +#define GPIO_PRT_INTR_EDGE5_Msk (0x20UL) /*!< GPIO_PRT INTR: EDGE5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_EDGE6_Pos (6UL) /*!< GPIO_PRT INTR: EDGE6 (Bit 6) */ +#define GPIO_PRT_INTR_EDGE6_Msk (0x40UL) /*!< GPIO_PRT INTR: EDGE6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_EDGE7_Pos (7UL) /*!< GPIO_PRT INTR: EDGE7 (Bit 7) */ +#define GPIO_PRT_INTR_EDGE7_Msk (0x80UL) /*!< GPIO_PRT INTR: EDGE7 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_FLT_EDGE_Pos (8UL) /*!< GPIO_PRT INTR: FLT_EDGE (Bit 8) */ +#define GPIO_PRT_INTR_FLT_EDGE_Msk (0x100UL) /*!< GPIO_PRT INTR: FLT_EDGE (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_IN_IN0_Pos (16UL) /*!< GPIO_PRT INTR: IN_IN0 (Bit 16) */ +#define GPIO_PRT_INTR_IN_IN0_Msk (0x10000UL) /*!< GPIO_PRT INTR: IN_IN0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_IN_IN1_Pos (17UL) /*!< GPIO_PRT INTR: IN_IN1 (Bit 17) */ +#define GPIO_PRT_INTR_IN_IN1_Msk (0x20000UL) /*!< GPIO_PRT INTR: IN_IN1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_IN_IN2_Pos (18UL) /*!< GPIO_PRT INTR: IN_IN2 (Bit 18) */ +#define GPIO_PRT_INTR_IN_IN2_Msk (0x40000UL) /*!< GPIO_PRT INTR: IN_IN2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_IN_IN3_Pos (19UL) /*!< GPIO_PRT INTR: IN_IN3 (Bit 19) */ +#define GPIO_PRT_INTR_IN_IN3_Msk (0x80000UL) /*!< GPIO_PRT INTR: IN_IN3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_IN_IN4_Pos (20UL) /*!< GPIO_PRT INTR: IN_IN4 (Bit 20) */ +#define GPIO_PRT_INTR_IN_IN4_Msk (0x100000UL) /*!< GPIO_PRT INTR: IN_IN4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_IN_IN5_Pos (21UL) /*!< GPIO_PRT INTR: IN_IN5 (Bit 21) */ +#define GPIO_PRT_INTR_IN_IN5_Msk (0x200000UL) /*!< GPIO_PRT INTR: IN_IN5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_IN_IN6_Pos (22UL) /*!< GPIO_PRT INTR: IN_IN6 (Bit 22) */ +#define GPIO_PRT_INTR_IN_IN6_Msk (0x400000UL) /*!< GPIO_PRT INTR: IN_IN6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_IN_IN7_Pos (23UL) /*!< GPIO_PRT INTR: IN_IN7 (Bit 23) */ +#define GPIO_PRT_INTR_IN_IN7_Msk (0x800000UL) /*!< GPIO_PRT INTR: IN_IN7 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_FLT_IN_IN_Pos (24UL) /*!< GPIO_PRT INTR: FLT_IN_IN (Bit 24) */ +#define GPIO_PRT_INTR_FLT_IN_IN_Msk (0x1000000UL) /*!< GPIO_PRT INTR: FLT_IN_IN (Bitfield-Mask: 0x01) */ +/* ================================================== GPIO_PRT.INTR_MASK =================================================== */ +#define GPIO_PRT_INTR_MASK_EDGE0_Pos (0UL) /*!< GPIO_PRT INTR_MASK: EDGE0 (Bit 0) */ +#define GPIO_PRT_INTR_MASK_EDGE0_Msk (0x1UL) /*!< GPIO_PRT INTR_MASK: EDGE0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASK_EDGE1_Pos (1UL) /*!< GPIO_PRT INTR_MASK: EDGE1 (Bit 1) */ +#define GPIO_PRT_INTR_MASK_EDGE1_Msk (0x2UL) /*!< GPIO_PRT INTR_MASK: EDGE1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASK_EDGE2_Pos (2UL) /*!< GPIO_PRT INTR_MASK: EDGE2 (Bit 2) */ +#define GPIO_PRT_INTR_MASK_EDGE2_Msk (0x4UL) /*!< GPIO_PRT INTR_MASK: EDGE2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASK_EDGE3_Pos (3UL) /*!< GPIO_PRT INTR_MASK: EDGE3 (Bit 3) */ +#define GPIO_PRT_INTR_MASK_EDGE3_Msk (0x8UL) /*!< GPIO_PRT INTR_MASK: EDGE3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASK_EDGE4_Pos (4UL) /*!< GPIO_PRT INTR_MASK: EDGE4 (Bit 4) */ +#define GPIO_PRT_INTR_MASK_EDGE4_Msk (0x10UL) /*!< GPIO_PRT INTR_MASK: EDGE4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASK_EDGE5_Pos (5UL) /*!< GPIO_PRT INTR_MASK: EDGE5 (Bit 5) */ +#define GPIO_PRT_INTR_MASK_EDGE5_Msk (0x20UL) /*!< GPIO_PRT INTR_MASK: EDGE5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASK_EDGE6_Pos (6UL) /*!< GPIO_PRT INTR_MASK: EDGE6 (Bit 6) */ +#define GPIO_PRT_INTR_MASK_EDGE6_Msk (0x40UL) /*!< GPIO_PRT INTR_MASK: EDGE6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASK_EDGE7_Pos (7UL) /*!< GPIO_PRT INTR_MASK: EDGE7 (Bit 7) */ +#define GPIO_PRT_INTR_MASK_EDGE7_Msk (0x80UL) /*!< GPIO_PRT INTR_MASK: EDGE7 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASK_FLT_EDGE_Pos (8UL) /*!< GPIO_PRT INTR_MASK: FLT_EDGE (Bit 8) */ +#define GPIO_PRT_INTR_MASK_FLT_EDGE_Msk (0x100UL) /*!< GPIO_PRT INTR_MASK: FLT_EDGE (Bitfield-Mask: 0x01) */ +/* ================================================= GPIO_PRT.INTR_MASKED ================================================== */ +#define GPIO_PRT_INTR_MASKED_EDGE0_Pos (0UL) /*!< GPIO_PRT INTR_MASKED: EDGE0 (Bit 0) */ +#define GPIO_PRT_INTR_MASKED_EDGE0_Msk (0x1UL) /*!< GPIO_PRT INTR_MASKED: EDGE0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASKED_EDGE1_Pos (1UL) /*!< GPIO_PRT INTR_MASKED: EDGE1 (Bit 1) */ +#define GPIO_PRT_INTR_MASKED_EDGE1_Msk (0x2UL) /*!< GPIO_PRT INTR_MASKED: EDGE1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASKED_EDGE2_Pos (2UL) /*!< GPIO_PRT INTR_MASKED: EDGE2 (Bit 2) */ +#define GPIO_PRT_INTR_MASKED_EDGE2_Msk (0x4UL) /*!< GPIO_PRT INTR_MASKED: EDGE2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASKED_EDGE3_Pos (3UL) /*!< GPIO_PRT INTR_MASKED: EDGE3 (Bit 3) */ +#define GPIO_PRT_INTR_MASKED_EDGE3_Msk (0x8UL) /*!< GPIO_PRT INTR_MASKED: EDGE3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASKED_EDGE4_Pos (4UL) /*!< GPIO_PRT INTR_MASKED: EDGE4 (Bit 4) */ +#define GPIO_PRT_INTR_MASKED_EDGE4_Msk (0x10UL) /*!< GPIO_PRT INTR_MASKED: EDGE4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASKED_EDGE5_Pos (5UL) /*!< GPIO_PRT INTR_MASKED: EDGE5 (Bit 5) */ +#define GPIO_PRT_INTR_MASKED_EDGE5_Msk (0x20UL) /*!< GPIO_PRT INTR_MASKED: EDGE5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASKED_EDGE6_Pos (6UL) /*!< GPIO_PRT INTR_MASKED: EDGE6 (Bit 6) */ +#define GPIO_PRT_INTR_MASKED_EDGE6_Msk (0x40UL) /*!< GPIO_PRT INTR_MASKED: EDGE6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASKED_EDGE7_Pos (7UL) /*!< GPIO_PRT INTR_MASKED: EDGE7 (Bit 7) */ +#define GPIO_PRT_INTR_MASKED_EDGE7_Msk (0x80UL) /*!< GPIO_PRT INTR_MASKED: EDGE7 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_MASKED_FLT_EDGE_Pos (8UL) /*!< GPIO_PRT INTR_MASKED: FLT_EDGE (Bit 8) */ +#define GPIO_PRT_INTR_MASKED_FLT_EDGE_Msk (0x100UL) /*!< GPIO_PRT INTR_MASKED: FLT_EDGE (Bitfield-Mask: 0x01) */ +/* =================================================== GPIO_PRT.INTR_SET =================================================== */ +#define GPIO_PRT_INTR_SET_EDGE0_Pos (0UL) /*!< GPIO_PRT INTR_SET: EDGE0 (Bit 0) */ +#define GPIO_PRT_INTR_SET_EDGE0_Msk (0x1UL) /*!< GPIO_PRT INTR_SET: EDGE0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_SET_EDGE1_Pos (1UL) /*!< GPIO_PRT INTR_SET: EDGE1 (Bit 1) */ +#define GPIO_PRT_INTR_SET_EDGE1_Msk (0x2UL) /*!< GPIO_PRT INTR_SET: EDGE1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_SET_EDGE2_Pos (2UL) /*!< GPIO_PRT INTR_SET: EDGE2 (Bit 2) */ +#define GPIO_PRT_INTR_SET_EDGE2_Msk (0x4UL) /*!< GPIO_PRT INTR_SET: EDGE2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_SET_EDGE3_Pos (3UL) /*!< GPIO_PRT INTR_SET: EDGE3 (Bit 3) */ +#define GPIO_PRT_INTR_SET_EDGE3_Msk (0x8UL) /*!< GPIO_PRT INTR_SET: EDGE3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_SET_EDGE4_Pos (4UL) /*!< GPIO_PRT INTR_SET: EDGE4 (Bit 4) */ +#define GPIO_PRT_INTR_SET_EDGE4_Msk (0x10UL) /*!< GPIO_PRT INTR_SET: EDGE4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_SET_EDGE5_Pos (5UL) /*!< GPIO_PRT INTR_SET: EDGE5 (Bit 5) */ +#define GPIO_PRT_INTR_SET_EDGE5_Msk (0x20UL) /*!< GPIO_PRT INTR_SET: EDGE5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_SET_EDGE6_Pos (6UL) /*!< GPIO_PRT INTR_SET: EDGE6 (Bit 6) */ +#define GPIO_PRT_INTR_SET_EDGE6_Msk (0x40UL) /*!< GPIO_PRT INTR_SET: EDGE6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_SET_EDGE7_Pos (7UL) /*!< GPIO_PRT INTR_SET: EDGE7 (Bit 7) */ +#define GPIO_PRT_INTR_SET_EDGE7_Msk (0x80UL) /*!< GPIO_PRT INTR_SET: EDGE7 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_INTR_SET_FLT_EDGE_Pos (8UL) /*!< GPIO_PRT INTR_SET: FLT_EDGE (Bit 8) */ +#define GPIO_PRT_INTR_SET_FLT_EDGE_Msk (0x100UL) /*!< GPIO_PRT INTR_SET: FLT_EDGE (Bitfield-Mask: 0x01) */ +/* =================================================== GPIO_PRT.INTR_CFG =================================================== */ +#define GPIO_PRT_INTR_CFG_EDGE0_SEL_Pos (0UL) /*!< GPIO_PRT INTR_CFG: EDGE0_SEL (Bit 0) */ +#define GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk (0x3UL) /*!< GPIO_PRT INTR_CFG: EDGE0_SEL (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_INTR_CFG_EDGE1_SEL_Pos (2UL) /*!< GPIO_PRT INTR_CFG: EDGE1_SEL (Bit 2) */ +#define GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk (0xcUL) /*!< GPIO_PRT INTR_CFG: EDGE1_SEL (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_INTR_CFG_EDGE2_SEL_Pos (4UL) /*!< GPIO_PRT INTR_CFG: EDGE2_SEL (Bit 4) */ +#define GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk (0x30UL) /*!< GPIO_PRT INTR_CFG: EDGE2_SEL (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_INTR_CFG_EDGE3_SEL_Pos (6UL) /*!< GPIO_PRT INTR_CFG: EDGE3_SEL (Bit 6) */ +#define GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk (0xc0UL) /*!< GPIO_PRT INTR_CFG: EDGE3_SEL (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_INTR_CFG_EDGE4_SEL_Pos (8UL) /*!< GPIO_PRT INTR_CFG: EDGE4_SEL (Bit 8) */ +#define GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk (0x300UL) /*!< GPIO_PRT INTR_CFG: EDGE4_SEL (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_INTR_CFG_EDGE5_SEL_Pos (10UL) /*!< GPIO_PRT INTR_CFG: EDGE5_SEL (Bit 10) */ +#define GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk (0xc00UL) /*!< GPIO_PRT INTR_CFG: EDGE5_SEL (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_INTR_CFG_EDGE6_SEL_Pos (12UL) /*!< GPIO_PRT INTR_CFG: EDGE6_SEL (Bit 12) */ +#define GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk (0x3000UL) /*!< GPIO_PRT INTR_CFG: EDGE6_SEL (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_INTR_CFG_EDGE7_SEL_Pos (14UL) /*!< GPIO_PRT INTR_CFG: EDGE7_SEL (Bit 14) */ +#define GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk (0xc000UL) /*!< GPIO_PRT INTR_CFG: EDGE7_SEL (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Pos (16UL) /*!< GPIO_PRT INTR_CFG: FLT_EDGE_SEL (Bit 16) */ +#define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk (0x30000UL) /*!< GPIO_PRT INTR_CFG: FLT_EDGE_SEL (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_INTR_CFG_FLT_SEL_Pos (18UL) /*!< GPIO_PRT INTR_CFG: FLT_SEL (Bit 18) */ +#define GPIO_PRT_INTR_CFG_FLT_SEL_Msk (0x1c0000UL) /*!< GPIO_PRT INTR_CFG: FLT_SEL (Bitfield-Mask: 0x07) */ +/* ===================================================== GPIO_PRT.CFG ====================================================== */ +#define GPIO_PRT_CFG_DRIVE_MODE0_Pos (0UL) /*!< GPIO_PRT CFG: DRIVE_MODE0 (Bit 0) */ +#define GPIO_PRT_CFG_DRIVE_MODE0_Msk (0x7UL) /*!< GPIO_PRT CFG: DRIVE_MODE0 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_IN_EN0_Pos (3UL) /*!< GPIO_PRT CFG: IN_EN0 (Bit 3) */ +#define GPIO_PRT_CFG_IN_EN0_Msk (0x8UL) /*!< GPIO_PRT CFG: IN_EN0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_DRIVE_MODE1_Pos (4UL) /*!< GPIO_PRT CFG: DRIVE_MODE1 (Bit 4) */ +#define GPIO_PRT_CFG_DRIVE_MODE1_Msk (0x70UL) /*!< GPIO_PRT CFG: DRIVE_MODE1 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_IN_EN1_Pos (7UL) /*!< GPIO_PRT CFG: IN_EN1 (Bit 7) */ +#define GPIO_PRT_CFG_IN_EN1_Msk (0x80UL) /*!< GPIO_PRT CFG: IN_EN1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_DRIVE_MODE2_Pos (8UL) /*!< GPIO_PRT CFG: DRIVE_MODE2 (Bit 8) */ +#define GPIO_PRT_CFG_DRIVE_MODE2_Msk (0x700UL) /*!< GPIO_PRT CFG: DRIVE_MODE2 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_IN_EN2_Pos (11UL) /*!< GPIO_PRT CFG: IN_EN2 (Bit 11) */ +#define GPIO_PRT_CFG_IN_EN2_Msk (0x800UL) /*!< GPIO_PRT CFG: IN_EN2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_DRIVE_MODE3_Pos (12UL) /*!< GPIO_PRT CFG: DRIVE_MODE3 (Bit 12) */ +#define GPIO_PRT_CFG_DRIVE_MODE3_Msk (0x7000UL) /*!< GPIO_PRT CFG: DRIVE_MODE3 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_IN_EN3_Pos (15UL) /*!< GPIO_PRT CFG: IN_EN3 (Bit 15) */ +#define GPIO_PRT_CFG_IN_EN3_Msk (0x8000UL) /*!< GPIO_PRT CFG: IN_EN3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_DRIVE_MODE4_Pos (16UL) /*!< GPIO_PRT CFG: DRIVE_MODE4 (Bit 16) */ +#define GPIO_PRT_CFG_DRIVE_MODE4_Msk (0x70000UL) /*!< GPIO_PRT CFG: DRIVE_MODE4 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_IN_EN4_Pos (19UL) /*!< GPIO_PRT CFG: IN_EN4 (Bit 19) */ +#define GPIO_PRT_CFG_IN_EN4_Msk (0x80000UL) /*!< GPIO_PRT CFG: IN_EN4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_DRIVE_MODE5_Pos (20UL) /*!< GPIO_PRT CFG: DRIVE_MODE5 (Bit 20) */ +#define GPIO_PRT_CFG_DRIVE_MODE5_Msk (0x700000UL) /*!< GPIO_PRT CFG: DRIVE_MODE5 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_IN_EN5_Pos (23UL) /*!< GPIO_PRT CFG: IN_EN5 (Bit 23) */ +#define GPIO_PRT_CFG_IN_EN5_Msk (0x800000UL) /*!< GPIO_PRT CFG: IN_EN5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_DRIVE_MODE6_Pos (24UL) /*!< GPIO_PRT CFG: DRIVE_MODE6 (Bit 24) */ +#define GPIO_PRT_CFG_DRIVE_MODE6_Msk (0x7000000UL) /*!< GPIO_PRT CFG: DRIVE_MODE6 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_IN_EN6_Pos (27UL) /*!< GPIO_PRT CFG: IN_EN6 (Bit 27) */ +#define GPIO_PRT_CFG_IN_EN6_Msk (0x8000000UL) /*!< GPIO_PRT CFG: IN_EN6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_DRIVE_MODE7_Pos (28UL) /*!< GPIO_PRT CFG: DRIVE_MODE7 (Bit 28) */ +#define GPIO_PRT_CFG_DRIVE_MODE7_Msk (0x70000000UL) /*!< GPIO_PRT CFG: DRIVE_MODE7 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_IN_EN7_Pos (31UL) /*!< GPIO_PRT CFG: IN_EN7 (Bit 31) */ +#define GPIO_PRT_CFG_IN_EN7_Msk (0x80000000UL) /*!< GPIO_PRT CFG: IN_EN7 (Bitfield-Mask: 0x01) */ +/* ==================================================== GPIO_PRT.CFG_IN ==================================================== */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Pos (0UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL0_0 (Bit 0) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Msk (0x1UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL0_0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Pos (1UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL1_0 (Bit 1) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Msk (0x2UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL1_0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Pos (2UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL2_0 (Bit 2) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Msk (0x4UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL2_0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Pos (3UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL3_0 (Bit 3) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Msk (0x8UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL3_0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Pos (4UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL4_0 (Bit 4) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Msk (0x10UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL4_0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Pos (5UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL5_0 (Bit 5) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Msk (0x20UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL5_0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Pos (6UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL6_0 (Bit 6) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Msk (0x40UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL6_0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Pos (7UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL7_0 (Bit 7) */ +#define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Msk (0x80UL) /*!< GPIO_PRT CFG_IN: VTRIP_SEL7_0 (Bitfield-Mask: 0x01) */ +/* =================================================== GPIO_PRT.CFG_OUT ==================================================== */ +#define GPIO_PRT_CFG_OUT_SLOW0_Pos (0UL) /*!< GPIO_PRT CFG_OUT: SLOW0 (Bit 0) */ +#define GPIO_PRT_CFG_OUT_SLOW0_Msk (0x1UL) /*!< GPIO_PRT CFG_OUT: SLOW0 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_OUT_SLOW1_Pos (1UL) /*!< GPIO_PRT CFG_OUT: SLOW1 (Bit 1) */ +#define GPIO_PRT_CFG_OUT_SLOW1_Msk (0x2UL) /*!< GPIO_PRT CFG_OUT: SLOW1 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_OUT_SLOW2_Pos (2UL) /*!< GPIO_PRT CFG_OUT: SLOW2 (Bit 2) */ +#define GPIO_PRT_CFG_OUT_SLOW2_Msk (0x4UL) /*!< GPIO_PRT CFG_OUT: SLOW2 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_OUT_SLOW3_Pos (3UL) /*!< GPIO_PRT CFG_OUT: SLOW3 (Bit 3) */ +#define GPIO_PRT_CFG_OUT_SLOW3_Msk (0x8UL) /*!< GPIO_PRT CFG_OUT: SLOW3 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_OUT_SLOW4_Pos (4UL) /*!< GPIO_PRT CFG_OUT: SLOW4 (Bit 4) */ +#define GPIO_PRT_CFG_OUT_SLOW4_Msk (0x10UL) /*!< GPIO_PRT CFG_OUT: SLOW4 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_OUT_SLOW5_Pos (5UL) /*!< GPIO_PRT CFG_OUT: SLOW5 (Bit 5) */ +#define GPIO_PRT_CFG_OUT_SLOW5_Msk (0x20UL) /*!< GPIO_PRT CFG_OUT: SLOW5 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_OUT_SLOW6_Pos (6UL) /*!< GPIO_PRT CFG_OUT: SLOW6 (Bit 6) */ +#define GPIO_PRT_CFG_OUT_SLOW6_Msk (0x40UL) /*!< GPIO_PRT CFG_OUT: SLOW6 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_OUT_SLOW7_Pos (7UL) /*!< GPIO_PRT CFG_OUT: SLOW7 (Bit 7) */ +#define GPIO_PRT_CFG_OUT_SLOW7_Msk (0x80UL) /*!< GPIO_PRT CFG_OUT: SLOW7 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Pos (16UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL0 (Bit 16) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Msk (0x30000UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL0 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Pos (18UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL1 (Bit 18) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Msk (0xc0000UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL1 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Pos (20UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL2 (Bit 20) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Msk (0x300000UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL2 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Pos (22UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL3 (Bit 22) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Msk (0xc00000UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL3 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Pos (24UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL4 (Bit 24) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Msk (0x3000000UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL4 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Pos (26UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL5 (Bit 26) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Msk (0xc000000UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL5 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Pos (28UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL6 (Bit 28) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Msk (0x30000000UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL6 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Pos (30UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL7 (Bit 30) */ +#define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Msk (0xc0000000UL) /*!< GPIO_PRT CFG_OUT: DRIVE_SEL7 (Bitfield-Mask: 0x03) */ +/* =================================================== GPIO_PRT.CFG_SIO ==================================================== */ +#define GPIO_PRT_CFG_SIO_VREG_EN01_Pos (0UL) /*!< GPIO_PRT CFG_SIO: VREG_EN01 (Bit 0) */ +#define GPIO_PRT_CFG_SIO_VREG_EN01_Msk (0x1UL) /*!< GPIO_PRT CFG_SIO: VREG_EN01 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_IBUF_SEL01_Pos (1UL) /*!< GPIO_PRT CFG_SIO: IBUF_SEL01 (Bit 1) */ +#define GPIO_PRT_CFG_SIO_IBUF_SEL01_Msk (0x2UL) /*!< GPIO_PRT CFG_SIO: IBUF_SEL01 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Pos (2UL) /*!< GPIO_PRT CFG_SIO: VTRIP_SEL01 (Bit 2) */ +#define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Msk (0x4UL) /*!< GPIO_PRT CFG_SIO: VTRIP_SEL01 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_VREF_SEL01_Pos (3UL) /*!< GPIO_PRT CFG_SIO: VREF_SEL01 (Bit 3) */ +#define GPIO_PRT_CFG_SIO_VREF_SEL01_Msk (0x18UL) /*!< GPIO_PRT CFG_SIO: VREF_SEL01 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_SIO_VOH_SEL01_Pos (5UL) /*!< GPIO_PRT CFG_SIO: VOH_SEL01 (Bit 5) */ +#define GPIO_PRT_CFG_SIO_VOH_SEL01_Msk (0xe0UL) /*!< GPIO_PRT CFG_SIO: VOH_SEL01 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_SIO_VREG_EN23_Pos (8UL) /*!< GPIO_PRT CFG_SIO: VREG_EN23 (Bit 8) */ +#define GPIO_PRT_CFG_SIO_VREG_EN23_Msk (0x100UL) /*!< GPIO_PRT CFG_SIO: VREG_EN23 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_IBUF_SEL23_Pos (9UL) /*!< GPIO_PRT CFG_SIO: IBUF_SEL23 (Bit 9) */ +#define GPIO_PRT_CFG_SIO_IBUF_SEL23_Msk (0x200UL) /*!< GPIO_PRT CFG_SIO: IBUF_SEL23 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Pos (10UL) /*!< GPIO_PRT CFG_SIO: VTRIP_SEL23 (Bit 10) */ +#define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Msk (0x400UL) /*!< GPIO_PRT CFG_SIO: VTRIP_SEL23 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_VREF_SEL23_Pos (11UL) /*!< GPIO_PRT CFG_SIO: VREF_SEL23 (Bit 11) */ +#define GPIO_PRT_CFG_SIO_VREF_SEL23_Msk (0x1800UL) /*!< GPIO_PRT CFG_SIO: VREF_SEL23 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_SIO_VOH_SEL23_Pos (13UL) /*!< GPIO_PRT CFG_SIO: VOH_SEL23 (Bit 13) */ +#define GPIO_PRT_CFG_SIO_VOH_SEL23_Msk (0xe000UL) /*!< GPIO_PRT CFG_SIO: VOH_SEL23 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_SIO_VREG_EN45_Pos (16UL) /*!< GPIO_PRT CFG_SIO: VREG_EN45 (Bit 16) */ +#define GPIO_PRT_CFG_SIO_VREG_EN45_Msk (0x10000UL) /*!< GPIO_PRT CFG_SIO: VREG_EN45 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_IBUF_SEL45_Pos (17UL) /*!< GPIO_PRT CFG_SIO: IBUF_SEL45 (Bit 17) */ +#define GPIO_PRT_CFG_SIO_IBUF_SEL45_Msk (0x20000UL) /*!< GPIO_PRT CFG_SIO: IBUF_SEL45 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Pos (18UL) /*!< GPIO_PRT CFG_SIO: VTRIP_SEL45 (Bit 18) */ +#define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Msk (0x40000UL) /*!< GPIO_PRT CFG_SIO: VTRIP_SEL45 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_VREF_SEL45_Pos (19UL) /*!< GPIO_PRT CFG_SIO: VREF_SEL45 (Bit 19) */ +#define GPIO_PRT_CFG_SIO_VREF_SEL45_Msk (0x180000UL) /*!< GPIO_PRT CFG_SIO: VREF_SEL45 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_SIO_VOH_SEL45_Pos (21UL) /*!< GPIO_PRT CFG_SIO: VOH_SEL45 (Bit 21) */ +#define GPIO_PRT_CFG_SIO_VOH_SEL45_Msk (0xe00000UL) /*!< GPIO_PRT CFG_SIO: VOH_SEL45 (Bitfield-Mask: 0x07) */ +#define GPIO_PRT_CFG_SIO_VREG_EN67_Pos (24UL) /*!< GPIO_PRT CFG_SIO: VREG_EN67 (Bit 24) */ +#define GPIO_PRT_CFG_SIO_VREG_EN67_Msk (0x1000000UL) /*!< GPIO_PRT CFG_SIO: VREG_EN67 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_IBUF_SEL67_Pos (25UL) /*!< GPIO_PRT CFG_SIO: IBUF_SEL67 (Bit 25) */ +#define GPIO_PRT_CFG_SIO_IBUF_SEL67_Msk (0x2000000UL) /*!< GPIO_PRT CFG_SIO: IBUF_SEL67 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Pos (26UL) /*!< GPIO_PRT CFG_SIO: VTRIP_SEL67 (Bit 26) */ +#define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Msk (0x4000000UL) /*!< GPIO_PRT CFG_SIO: VTRIP_SEL67 (Bitfield-Mask: 0x01) */ +#define GPIO_PRT_CFG_SIO_VREF_SEL67_Pos (27UL) /*!< GPIO_PRT CFG_SIO: VREF_SEL67 (Bit 27) */ +#define GPIO_PRT_CFG_SIO_VREF_SEL67_Msk (0x18000000UL) /*!< GPIO_PRT CFG_SIO: VREF_SEL67 (Bitfield-Mask: 0x03) */ +#define GPIO_PRT_CFG_SIO_VOH_SEL67_Pos (29UL) /*!< GPIO_PRT CFG_SIO: VOH_SEL67 (Bit 29) */ +#define GPIO_PRT_CFG_SIO_VOH_SEL67_Msk (0xe0000000UL) /*!< GPIO_PRT CFG_SIO: VOH_SEL67 (Bitfield-Mask: 0x07) */ +/* ================================================ GPIO_PRT.CFG_IN_GPIO5V ================================================= */ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL0_1_Pos (0UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL0_1 (Bit 0) */ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL0_1_Msk (0x1UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL0_1 (Bitfield-Mask: 0x01)*/ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL1_1_Pos (1UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL1_1 (Bit 1) */ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL1_1_Msk (0x2UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL1_1 (Bitfield-Mask: 0x01)*/ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL2_1_Pos (2UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL2_1 (Bit 2) */ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL2_1_Msk (0x4UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL2_1 (Bitfield-Mask: 0x01)*/ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL3_1_Pos (3UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL3_1 (Bit 3) */ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL3_1_Msk (0x8UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL3_1 (Bitfield-Mask: 0x01)*/ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL4_1_Pos (4UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL4_1 (Bit 4) */ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL4_1_Msk (0x10UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL4_1 (Bitfield-Mask: 0x01)*/ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL5_1_Pos (5UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL5_1 (Bit 5) */ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL5_1_Msk (0x20UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL5_1 (Bitfield-Mask: 0x01)*/ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL6_1_Pos (6UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL6_1 (Bit 6) */ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL6_1_Msk (0x40UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL6_1 (Bitfield-Mask: 0x01)*/ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL7_1_Pos (7UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL7_1 (Bit 7) */ +#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL7_1_Msk (0x80UL) /*!< GPIO_PRT CFG_IN_GPIO5V: VTRIP_SEL7_1 (Bitfield-Mask: 0x01)*/ + + +/* =================================================== GPIO.INTR_CAUSE0 ==================================================== */ +#define GPIO_INTR_CAUSE0_PORT_INT_Pos (0UL) /*!< GPIO INTR_CAUSE0: PORT_INT (Bit 0) */ +#define GPIO_INTR_CAUSE0_PORT_INT_Msk (0xffffffffUL) /*!< GPIO INTR_CAUSE0: PORT_INT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== GPIO.INTR_CAUSE1 ==================================================== */ +#define GPIO_INTR_CAUSE1_PORT_INT_Pos (0UL) /*!< GPIO INTR_CAUSE1: PORT_INT (Bit 0) */ +#define GPIO_INTR_CAUSE1_PORT_INT_Msk (0xffffffffUL) /*!< GPIO INTR_CAUSE1: PORT_INT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== GPIO.INTR_CAUSE2 ==================================================== */ +#define GPIO_INTR_CAUSE2_PORT_INT_Pos (0UL) /*!< GPIO INTR_CAUSE2: PORT_INT (Bit 0) */ +#define GPIO_INTR_CAUSE2_PORT_INT_Msk (0xffffffffUL) /*!< GPIO INTR_CAUSE2: PORT_INT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== GPIO.INTR_CAUSE3 ==================================================== */ +#define GPIO_INTR_CAUSE3_PORT_INT_Pos (0UL) /*!< GPIO INTR_CAUSE3: PORT_INT (Bit 0) */ +#define GPIO_INTR_CAUSE3_PORT_INT_Msk (0xffffffffUL) /*!< GPIO INTR_CAUSE3: PORT_INT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== GPIO.VDD_ACTIVE ==================================================== */ +#define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Pos (0UL) /*!< GPIO VDD_ACTIVE: VDDIO_ACTIVE (Bit 0) */ +#define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Msk (0xffffUL) /*!< GPIO VDD_ACTIVE: VDDIO_ACTIVE (Bitfield-Mask: 0xffff) */ +#define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Pos (30UL) /*!< GPIO VDD_ACTIVE: VDDA_ACTIVE (Bit 30) */ +#define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Msk (0x40000000UL) /*!< GPIO VDD_ACTIVE: VDDA_ACTIVE (Bitfield-Mask: 0x01) */ +#define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Pos (31UL) /*!< GPIO VDD_ACTIVE: VDDD_ACTIVE (Bit 31) */ +#define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Msk (0x80000000UL) /*!< GPIO VDD_ACTIVE: VDDD_ACTIVE (Bitfield-Mask: 0x01) */ +/* ===================================================== GPIO.VDD_INTR ===================================================== */ +#define GPIO_VDD_INTR_VDDIO_ACTIVE_Pos (0UL) /*!< GPIO VDD_INTR: VDDIO_ACTIVE (Bit 0) */ +#define GPIO_VDD_INTR_VDDIO_ACTIVE_Msk (0xffffUL) /*!< GPIO VDD_INTR: VDDIO_ACTIVE (Bitfield-Mask: 0xffff) */ +#define GPIO_VDD_INTR_VDDA_ACTIVE_Pos (30UL) /*!< GPIO VDD_INTR: VDDA_ACTIVE (Bit 30) */ +#define GPIO_VDD_INTR_VDDA_ACTIVE_Msk (0x40000000UL) /*!< GPIO VDD_INTR: VDDA_ACTIVE (Bitfield-Mask: 0x01) */ +#define GPIO_VDD_INTR_VDDD_ACTIVE_Pos (31UL) /*!< GPIO VDD_INTR: VDDD_ACTIVE (Bit 31) */ +#define GPIO_VDD_INTR_VDDD_ACTIVE_Msk (0x80000000UL) /*!< GPIO VDD_INTR: VDDD_ACTIVE (Bitfield-Mask: 0x01) */ +/* ================================================== GPIO.VDD_INTR_MASK =================================================== */ +#define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Pos (0UL) /*!< GPIO VDD_INTR_MASK: VDDIO_ACTIVE (Bit 0) */ +#define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Msk (0xffffUL) /*!< GPIO VDD_INTR_MASK: VDDIO_ACTIVE (Bitfield-Mask: 0xffff) */ +#define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Pos (30UL) /*!< GPIO VDD_INTR_MASK: VDDA_ACTIVE (Bit 30) */ +#define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Msk (0x40000000UL) /*!< GPIO VDD_INTR_MASK: VDDA_ACTIVE (Bitfield-Mask: 0x01) */ +#define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Pos (31UL) /*!< GPIO VDD_INTR_MASK: VDDD_ACTIVE (Bit 31) */ +#define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Msk (0x80000000UL) /*!< GPIO VDD_INTR_MASK: VDDD_ACTIVE (Bitfield-Mask: 0x01) */ +/* ================================================= GPIO.VDD_INTR_MASKED ================================================== */ +#define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos (0UL) /*!< GPIO VDD_INTR_MASKED: VDDIO_ACTIVE (Bit 0) */ +#define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk (0xffffUL) /*!< GPIO VDD_INTR_MASKED: VDDIO_ACTIVE (Bitfield-Mask: 0xffff)*/ +#define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Pos (30UL) /*!< GPIO VDD_INTR_MASKED: VDDA_ACTIVE (Bit 30) */ +#define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Msk (0x40000000UL) /*!< GPIO VDD_INTR_MASKED: VDDA_ACTIVE (Bitfield-Mask: 0x01) */ +#define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Pos (31UL) /*!< GPIO VDD_INTR_MASKED: VDDD_ACTIVE (Bit 31) */ +#define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Msk (0x80000000UL) /*!< GPIO VDD_INTR_MASKED: VDDD_ACTIVE (Bitfield-Mask: 0x01) */ +/* =================================================== GPIO.VDD_INTR_SET =================================================== */ +#define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Pos (0UL) /*!< GPIO VDD_INTR_SET: VDDIO_ACTIVE (Bit 0) */ +#define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Msk (0xffffUL) /*!< GPIO VDD_INTR_SET: VDDIO_ACTIVE (Bitfield-Mask: 0xffff) */ +#define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Pos (30UL) /*!< GPIO VDD_INTR_SET: VDDA_ACTIVE (Bit 30) */ +#define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Msk (0x40000000UL) /*!< GPIO VDD_INTR_SET: VDDA_ACTIVE (Bitfield-Mask: 0x01) */ +#define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Pos (31UL) /*!< GPIO VDD_INTR_SET: VDDD_ACTIVE (Bit 31) */ +#define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Msk (0x80000000UL) /*!< GPIO VDD_INTR_SET: VDDD_ACTIVE (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_GPIO_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_headers.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_headers.h new file mode 100644 index 0000000000..36458cc81b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_headers.h @@ -0,0 +1,31 @@ +/***************************************************************************//** +* \file cyip_headers.h +* +* \brief +* Common header file to be included by all IP definition headers +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_HEADERS_H_ +#define _CYIP_HEADERS_H_ + +#include + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) +#include "core_cm0plus.h" +#else +#include "core_cm4.h" +#endif + +#endif /* _CYIP_HEADERS_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_hsiom.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_hsiom.h new file mode 100644 index 0000000000..aae2c67796 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_hsiom.h @@ -0,0 +1,88 @@ +/***************************************************************************//** +* \file cyip_hsiom.h +* +* \brief +* HSIOM IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_HSIOM_H_ +#define _CYIP_HSIOM_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ HSIOM ================ */ +/* =========================================================================================================================== */ + +#define HSIOM_PRT_SECTION_SIZE 0x00000010UL +#define HSIOM_SECTION_SIZE 0x00004000UL + +/** + * \brief HSIOM port registers (HSIOM_PRT) + */ +typedef struct { + __IOM uint32_t PORT_SEL0; /*!< 0x00000000 Port selection 0 */ + __IOM uint32_t PORT_SEL1; /*!< 0x00000004 Port selection 1 */ + __IM uint32_t RESERVED[2]; +} HSIOM_PRT_Type; /*!< Size = 8 (0x8) */ + +/** + * \brief High Speed IO Matrix (HSIOM) (HSIOM) + */ +typedef struct { /*!< HSIOM Structure */ + HSIOM_PRT_Type PRT[128]; /*!< 0x00000000 HSIOM port registers */ + __IM uint32_t RESERVED[1536]; + __IOM uint32_t AMUX_SPLIT_CTL[64]; /*!< 0x00002000 AMUX splitter cell control */ +} HSIOM_Type; /*!< Size = 8448 (0x2100) */ + + +/* ================================================== HSIOM_PRT.PORT_SEL0 ================================================== */ +#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Pos (0UL) /*!< HSIOM_PRT PORT_SEL0: IO0_SEL (Bit 0) */ +#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Msk (0x1fUL) /*!< HSIOM_PRT PORT_SEL0: IO0_SEL (Bitfield-Mask: 0x1f) */ +#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Pos (8UL) /*!< HSIOM_PRT PORT_SEL0: IO1_SEL (Bit 8) */ +#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Msk (0x1f00UL) /*!< HSIOM_PRT PORT_SEL0: IO1_SEL (Bitfield-Mask: 0x1f) */ +#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Pos (16UL) /*!< HSIOM_PRT PORT_SEL0: IO2_SEL (Bit 16) */ +#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Msk (0x1f0000UL) /*!< HSIOM_PRT PORT_SEL0: IO2_SEL (Bitfield-Mask: 0x1f) */ +#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Pos (24UL) /*!< HSIOM_PRT PORT_SEL0: IO3_SEL (Bit 24) */ +#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Msk (0x1f000000UL) /*!< HSIOM_PRT PORT_SEL0: IO3_SEL (Bitfield-Mask: 0x1f) */ +/* ================================================== HSIOM_PRT.PORT_SEL1 ================================================== */ +#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Pos (0UL) /*!< HSIOM_PRT PORT_SEL1: IO4_SEL (Bit 0) */ +#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Msk (0x1fUL) /*!< HSIOM_PRT PORT_SEL1: IO4_SEL (Bitfield-Mask: 0x1f) */ +#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Pos (8UL) /*!< HSIOM_PRT PORT_SEL1: IO5_SEL (Bit 8) */ +#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Msk (0x1f00UL) /*!< HSIOM_PRT PORT_SEL1: IO5_SEL (Bitfield-Mask: 0x1f) */ +#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Pos (16UL) /*!< HSIOM_PRT PORT_SEL1: IO6_SEL (Bit 16) */ +#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Msk (0x1f0000UL) /*!< HSIOM_PRT PORT_SEL1: IO6_SEL (Bitfield-Mask: 0x1f) */ +#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Pos (24UL) /*!< HSIOM_PRT PORT_SEL1: IO7_SEL (Bit 24) */ +#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Msk (0x1f000000UL) /*!< HSIOM_PRT PORT_SEL1: IO7_SEL (Bitfield-Mask: 0x1f) */ + + +/* ================================================= HSIOM.AMUX_SPLIT_CTL ================================================== */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos (0UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_AA_SL (Bit 0) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk (0x1UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_AA_SL (Bitfield-Mask: 0x01) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos (1UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_AA_SR (Bit 1) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk (0x2UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_AA_SR (Bitfield-Mask: 0x01) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos (2UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_AA_S0 (Bit 2) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk (0x4UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_AA_S0 (Bitfield-Mask: 0x01) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos (4UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_BB_SL (Bit 4) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk (0x10UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_BB_SL (Bitfield-Mask: 0x01) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos (5UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_BB_SR (Bit 5) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk (0x20UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_BB_SR (Bitfield-Mask: 0x01) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos (6UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_BB_S0 (Bit 6) */ +#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk (0x40UL) /*!< HSIOM AMUX_SPLIT_CTL: SWITCH_BB_S0 (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_HSIOM_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_i2s.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_i2s.h new file mode 100644 index 0000000000..9228a2fcc4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_i2s.h @@ -0,0 +1,280 @@ +/***************************************************************************//** +* \file cyip_i2s.h +* +* \brief +* I2S IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_I2S_H_ +#define _CYIP_I2S_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ + +#define I2S_SECTION_SIZE 0x00001000UL + +/** + * \brief I2S registers (I2S) + */ +typedef struct { /*!< I2S Structure */ + __IOM uint32_t CTL; /*!< 0x00000000 Control */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */ + __IOM uint32_t COMMON_CTL; /*!< 0x00000014 Common control */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t CMD; /*!< 0x00000020 Command */ + __IM uint32_t RESERVED2[7]; + __IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */ + __IM uint32_t RESERVED3[15]; + __IOM uint32_t TX_CTL; /*!< 0x00000080 Transmitter control */ + __IOM uint32_t TX_WATCHDOG; /*!< 0x00000084 Transmitter watchdog */ + __IM uint32_t RESERVED4[6]; + __IOM uint32_t RX_CTL; /*!< 0x000000A0 Receiver control */ + __IOM uint32_t RX_WATCHDOG; /*!< 0x000000A4 Receiver watchdog */ + __IM uint32_t RESERVED5[86]; + __IOM uint32_t TX_FIFO_CTL; /*!< 0x00000200 TX FIFO control */ + __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000204 TX FIFO status */ + __OM uint32_t TX_FIFO_WR; /*!< 0x00000208 TX FIFO write */ + __IM uint32_t RESERVED6[61]; + __IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */ + __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */ + __IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */ + __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */ + __IM uint32_t RESERVED7[764]; + __IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */ + __IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */ +} I2S_Type; /*!< Size = 3856 (0xF10) */ + + +/* ======================================================== I2S.CTL ======================================================== */ +#define I2S_CTL_TX_ENABLED_Pos (30UL) /*!< I2S CTL: TX_ENABLED (Bit 30) */ +#define I2S_CTL_TX_ENABLED_Msk (0x40000000UL) /*!< I2S CTL: TX_ENABLED (Bitfield-Mask: 0x01) */ +#define I2S_CTL_RX_ENABLED_Pos (31UL) /*!< I2S CTL: RX_ENABLED (Bit 31) */ +#define I2S_CTL_RX_ENABLED_Msk (0x80000000UL) /*!< I2S CTL: RX_ENABLED (Bitfield-Mask: 0x01) */ +/* ===================================================== I2S.CLOCK_CTL ===================================================== */ +#define I2S_CLOCK_CTL_CLOCK_DIV_Pos (0UL) /*!< I2S CLOCK_CTL: CLOCK_DIV (Bit 0) */ +#define I2S_CLOCK_CTL_CLOCK_DIV_Msk (0x3fUL) /*!< I2S CLOCK_CTL: CLOCK_DIV (Bitfield-Mask: 0x3f) */ +#define I2S_CLOCK_CTL_CLOCK_SEL_Pos (8UL) /*!< I2S CLOCK_CTL: CLOCK_SEL (Bit 8) */ +#define I2S_CLOCK_CTL_CLOCK_SEL_Msk (0x100UL) /*!< I2S CLOCK_CTL: CLOCK_SEL (Bitfield-Mask: 0x01) */ +/* ==================================================== I2S.COMMON_CTL ===================================================== */ +#define I2S_COMMON_CTL_LOOPBACK_Pos (0UL) /*!< I2S COMMON_CTL: LOOPBACK (Bit 0) */ +#define I2S_COMMON_CTL_LOOPBACK_Msk (0x1UL) /*!< I2S COMMON_CTL: LOOPBACK (Bitfield-Mask: 0x01) */ +/* ======================================================== I2S.CMD ======================================================== */ +#define I2S_CMD_TX_START_Pos (0UL) /*!< I2S CMD: TX_START (Bit 0) */ +#define I2S_CMD_TX_START_Msk (0x1UL) /*!< I2S CMD: TX_START (Bitfield-Mask: 0x01) */ +#define I2S_CMD_TX_PAUSE_Pos (8UL) /*!< I2S CMD: TX_PAUSE (Bit 8) */ +#define I2S_CMD_TX_PAUSE_Msk (0x100UL) /*!< I2S CMD: TX_PAUSE (Bitfield-Mask: 0x01) */ +#define I2S_CMD_RX_START_Pos (16UL) /*!< I2S CMD: RX_START (Bit 16) */ +#define I2S_CMD_RX_START_Msk (0x10000UL) /*!< I2S CMD: RX_START (Bitfield-Mask: 0x01) */ +/* ====================================================== I2S.TR_CTL ======================================================= */ +#define I2S_TR_CTL_TX_REQ_EN_Pos (0UL) /*!< I2S TR_CTL: TX_REQ_EN (Bit 0) */ +#define I2S_TR_CTL_TX_REQ_EN_Msk (0x1UL) /*!< I2S TR_CTL: TX_REQ_EN (Bitfield-Mask: 0x01) */ +#define I2S_TR_CTL_RX_REQ_EN_Pos (16UL) /*!< I2S TR_CTL: RX_REQ_EN (Bit 16) */ +#define I2S_TR_CTL_RX_REQ_EN_Msk (0x10000UL) /*!< I2S TR_CTL: RX_REQ_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== I2S.TX_CTL ======================================================= */ +#define I2S_TX_CTL_M_CLOCK_DIV_Pos (0UL) /*!< I2S TX_CTL: M_CLOCK_DIV (Bit 0) */ +#define I2S_TX_CTL_M_CLOCK_DIV_Msk (0x7UL) /*!< I2S TX_CTL: M_CLOCK_DIV (Bitfield-Mask: 0x07) */ +#define I2S_TX_CTL_B_CLOCK_INV_Pos (3UL) /*!< I2S TX_CTL: B_CLOCK_INV (Bit 3) */ +#define I2S_TX_CTL_B_CLOCK_INV_Msk (0x8UL) /*!< I2S TX_CTL: B_CLOCK_INV (Bitfield-Mask: 0x01) */ +#define I2S_TX_CTL_CH_NR_Pos (4UL) /*!< I2S TX_CTL: CH_NR (Bit 4) */ +#define I2S_TX_CTL_CH_NR_Msk (0x70UL) /*!< I2S TX_CTL: CH_NR (Bitfield-Mask: 0x07) */ +#define I2S_TX_CTL_MS_Pos (7UL) /*!< I2S TX_CTL: MS (Bit 7) */ +#define I2S_TX_CTL_MS_Msk (0x80UL) /*!< I2S TX_CTL: MS (Bitfield-Mask: 0x01) */ +#define I2S_TX_CTL_I2S_MODE_Pos (8UL) /*!< I2S TX_CTL: I2S_MODE (Bit 8) */ +#define I2S_TX_CTL_I2S_MODE_Msk (0x300UL) /*!< I2S TX_CTL: I2S_MODE (Bitfield-Mask: 0x03) */ +#define I2S_TX_CTL_WS_PULSE_Pos (10UL) /*!< I2S TX_CTL: WS_PULSE (Bit 10) */ +#define I2S_TX_CTL_WS_PULSE_Msk (0x400UL) /*!< I2S TX_CTL: WS_PULSE (Bitfield-Mask: 0x01) */ +#define I2S_TX_CTL_OVHDATA_Pos (12UL) /*!< I2S TX_CTL: OVHDATA (Bit 12) */ +#define I2S_TX_CTL_OVHDATA_Msk (0x1000UL) /*!< I2S TX_CTL: OVHDATA (Bitfield-Mask: 0x01) */ +#define I2S_TX_CTL_WD_EN_Pos (13UL) /*!< I2S TX_CTL: WD_EN (Bit 13) */ +#define I2S_TX_CTL_WD_EN_Msk (0x2000UL) /*!< I2S TX_CTL: WD_EN (Bitfield-Mask: 0x01) */ +#define I2S_TX_CTL_CH_LEN_Pos (16UL) /*!< I2S TX_CTL: CH_LEN (Bit 16) */ +#define I2S_TX_CTL_CH_LEN_Msk (0x70000UL) /*!< I2S TX_CTL: CH_LEN (Bitfield-Mask: 0x07) */ +#define I2S_TX_CTL_WORD_LEN_Pos (20UL) /*!< I2S TX_CTL: WORD_LEN (Bit 20) */ +#define I2S_TX_CTL_WORD_LEN_Msk (0x700000UL) /*!< I2S TX_CTL: WORD_LEN (Bitfield-Mask: 0x07) */ +/* ==================================================== I2S.TX_WATCHDOG ==================================================== */ +#define I2S_TX_WATCHDOG_WD_COUNTER_Pos (0UL) /*!< I2S TX_WATCHDOG: WD_COUNTER (Bit 0) */ +#define I2S_TX_WATCHDOG_WD_COUNTER_Msk (0xffffffffUL) /*!< I2S TX_WATCHDOG: WD_COUNTER (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== I2S.RX_CTL ======================================================= */ +#define I2S_RX_CTL_M_CLOCK_DIV_Pos (0UL) /*!< I2S RX_CTL: M_CLOCK_DIV (Bit 0) */ +#define I2S_RX_CTL_M_CLOCK_DIV_Msk (0x7UL) /*!< I2S RX_CTL: M_CLOCK_DIV (Bitfield-Mask: 0x07) */ +#define I2S_RX_CTL_B_CLOCK_INV_Pos (3UL) /*!< I2S RX_CTL: B_CLOCK_INV (Bit 3) */ +#define I2S_RX_CTL_B_CLOCK_INV_Msk (0x8UL) /*!< I2S RX_CTL: B_CLOCK_INV (Bitfield-Mask: 0x01) */ +#define I2S_RX_CTL_CH_NR_Pos (4UL) /*!< I2S RX_CTL: CH_NR (Bit 4) */ +#define I2S_RX_CTL_CH_NR_Msk (0x70UL) /*!< I2S RX_CTL: CH_NR (Bitfield-Mask: 0x07) */ +#define I2S_RX_CTL_MS_Pos (7UL) /*!< I2S RX_CTL: MS (Bit 7) */ +#define I2S_RX_CTL_MS_Msk (0x80UL) /*!< I2S RX_CTL: MS (Bitfield-Mask: 0x01) */ +#define I2S_RX_CTL_I2S_MODE_Pos (8UL) /*!< I2S RX_CTL: I2S_MODE (Bit 8) */ +#define I2S_RX_CTL_I2S_MODE_Msk (0x300UL) /*!< I2S RX_CTL: I2S_MODE (Bitfield-Mask: 0x03) */ +#define I2S_RX_CTL_WS_PULSE_Pos (10UL) /*!< I2S RX_CTL: WS_PULSE (Bit 10) */ +#define I2S_RX_CTL_WS_PULSE_Msk (0x400UL) /*!< I2S RX_CTL: WS_PULSE (Bitfield-Mask: 0x01) */ +#define I2S_RX_CTL_WD_EN_Pos (13UL) /*!< I2S RX_CTL: WD_EN (Bit 13) */ +#define I2S_RX_CTL_WD_EN_Msk (0x2000UL) /*!< I2S RX_CTL: WD_EN (Bitfield-Mask: 0x01) */ +#define I2S_RX_CTL_CH_LEN_Pos (16UL) /*!< I2S RX_CTL: CH_LEN (Bit 16) */ +#define I2S_RX_CTL_CH_LEN_Msk (0x70000UL) /*!< I2S RX_CTL: CH_LEN (Bitfield-Mask: 0x07) */ +#define I2S_RX_CTL_WORD_LEN_Pos (20UL) /*!< I2S RX_CTL: WORD_LEN (Bit 20) */ +#define I2S_RX_CTL_WORD_LEN_Msk (0x700000UL) /*!< I2S RX_CTL: WORD_LEN (Bitfield-Mask: 0x07) */ +#define I2S_RX_CTL_BIT_EXTENSION_Pos (23UL) /*!< I2S RX_CTL: BIT_EXTENSION (Bit 23) */ +#define I2S_RX_CTL_BIT_EXTENSION_Msk (0x800000UL) /*!< I2S RX_CTL: BIT_EXTENSION (Bitfield-Mask: 0x01) */ +/* ==================================================== I2S.RX_WATCHDOG ==================================================== */ +#define I2S_RX_WATCHDOG_WD_COUNTER_Pos (0UL) /*!< I2S RX_WATCHDOG: WD_COUNTER (Bit 0) */ +#define I2S_RX_WATCHDOG_WD_COUNTER_Msk (0xffffffffUL) /*!< I2S RX_WATCHDOG: WD_COUNTER (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== I2S.TX_FIFO_CTL ==================================================== */ +#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Pos (0UL) /*!< I2S TX_FIFO_CTL: TRIGGER_LEVEL (Bit 0) */ +#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Msk (0xffUL) /*!< I2S TX_FIFO_CTL: TRIGGER_LEVEL (Bitfield-Mask: 0xff) */ +#define I2S_TX_FIFO_CTL_CLEAR_Pos (16UL) /*!< I2S TX_FIFO_CTL: CLEAR (Bit 16) */ +#define I2S_TX_FIFO_CTL_CLEAR_Msk (0x10000UL) /*!< I2S TX_FIFO_CTL: CLEAR (Bitfield-Mask: 0x01) */ +#define I2S_TX_FIFO_CTL_FREEZE_Pos (17UL) /*!< I2S TX_FIFO_CTL: FREEZE (Bit 17) */ +#define I2S_TX_FIFO_CTL_FREEZE_Msk (0x20000UL) /*!< I2S TX_FIFO_CTL: FREEZE (Bitfield-Mask: 0x01) */ +/* ================================================== I2S.TX_FIFO_STATUS =================================================== */ +#define I2S_TX_FIFO_STATUS_USED_Pos (0UL) /*!< I2S TX_FIFO_STATUS: USED (Bit 0) */ +#define I2S_TX_FIFO_STATUS_USED_Msk (0x1ffUL) /*!< I2S TX_FIFO_STATUS: USED (Bitfield-Mask: 0x1ff) */ +#define I2S_TX_FIFO_STATUS_RD_PTR_Pos (16UL) /*!< I2S TX_FIFO_STATUS: RD_PTR (Bit 16) */ +#define I2S_TX_FIFO_STATUS_RD_PTR_Msk (0xff0000UL) /*!< I2S TX_FIFO_STATUS: RD_PTR (Bitfield-Mask: 0xff) */ +#define I2S_TX_FIFO_STATUS_WR_PTR_Pos (24UL) /*!< I2S TX_FIFO_STATUS: WR_PTR (Bit 24) */ +#define I2S_TX_FIFO_STATUS_WR_PTR_Msk (0xff000000UL) /*!< I2S TX_FIFO_STATUS: WR_PTR (Bitfield-Mask: 0xff) */ +/* ==================================================== I2S.TX_FIFO_WR ===================================================== */ +#define I2S_TX_FIFO_WR_DATA_Pos (0UL) /*!< I2S TX_FIFO_WR: DATA (Bit 0) */ +#define I2S_TX_FIFO_WR_DATA_Msk (0xffffffffUL) /*!< I2S TX_FIFO_WR: DATA (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== I2S.RX_FIFO_CTL ==================================================== */ +#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Pos (0UL) /*!< I2S RX_FIFO_CTL: TRIGGER_LEVEL (Bit 0) */ +#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Msk (0xffUL) /*!< I2S RX_FIFO_CTL: TRIGGER_LEVEL (Bitfield-Mask: 0xff) */ +#define I2S_RX_FIFO_CTL_CLEAR_Pos (16UL) /*!< I2S RX_FIFO_CTL: CLEAR (Bit 16) */ +#define I2S_RX_FIFO_CTL_CLEAR_Msk (0x10000UL) /*!< I2S RX_FIFO_CTL: CLEAR (Bitfield-Mask: 0x01) */ +#define I2S_RX_FIFO_CTL_FREEZE_Pos (17UL) /*!< I2S RX_FIFO_CTL: FREEZE (Bit 17) */ +#define I2S_RX_FIFO_CTL_FREEZE_Msk (0x20000UL) /*!< I2S RX_FIFO_CTL: FREEZE (Bitfield-Mask: 0x01) */ +/* ================================================== I2S.RX_FIFO_STATUS =================================================== */ +#define I2S_RX_FIFO_STATUS_USED_Pos (0UL) /*!< I2S RX_FIFO_STATUS: USED (Bit 0) */ +#define I2S_RX_FIFO_STATUS_USED_Msk (0x1ffUL) /*!< I2S RX_FIFO_STATUS: USED (Bitfield-Mask: 0x1ff) */ +#define I2S_RX_FIFO_STATUS_RD_PTR_Pos (16UL) /*!< I2S RX_FIFO_STATUS: RD_PTR (Bit 16) */ +#define I2S_RX_FIFO_STATUS_RD_PTR_Msk (0xff0000UL) /*!< I2S RX_FIFO_STATUS: RD_PTR (Bitfield-Mask: 0xff) */ +#define I2S_RX_FIFO_STATUS_WR_PTR_Pos (24UL) /*!< I2S RX_FIFO_STATUS: WR_PTR (Bit 24) */ +#define I2S_RX_FIFO_STATUS_WR_PTR_Msk (0xff000000UL) /*!< I2S RX_FIFO_STATUS: WR_PTR (Bitfield-Mask: 0xff) */ +/* ==================================================== I2S.RX_FIFO_RD ===================================================== */ +#define I2S_RX_FIFO_RD_DATA_Pos (0UL) /*!< I2S RX_FIFO_RD: DATA (Bit 0) */ +#define I2S_RX_FIFO_RD_DATA_Msk (0xffffffffUL) /*!< I2S RX_FIFO_RD: DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================= I2S.RX_FIFO_RD_SILENT ================================================= */ +#define I2S_RX_FIFO_RD_SILENT_DATA_Pos (0UL) /*!< I2S RX_FIFO_RD_SILENT: DATA (Bit 0) */ +#define I2S_RX_FIFO_RD_SILENT_DATA_Msk (0xffffffffUL) /*!< I2S RX_FIFO_RD_SILENT: DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= I2S.INTR ======================================================== */ +#define I2S_INTR_TX_TRIGGER_Pos (0UL) /*!< I2S INTR: TX_TRIGGER (Bit 0) */ +#define I2S_INTR_TX_TRIGGER_Msk (0x1UL) /*!< I2S INTR: TX_TRIGGER (Bitfield-Mask: 0x01) */ +#define I2S_INTR_TX_NOT_FULL_Pos (1UL) /*!< I2S INTR: TX_NOT_FULL (Bit 1) */ +#define I2S_INTR_TX_NOT_FULL_Msk (0x2UL) /*!< I2S INTR: TX_NOT_FULL (Bitfield-Mask: 0x01) */ +#define I2S_INTR_TX_EMPTY_Pos (4UL) /*!< I2S INTR: TX_EMPTY (Bit 4) */ +#define I2S_INTR_TX_EMPTY_Msk (0x10UL) /*!< I2S INTR: TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2S_INTR_TX_OVERFLOW_Pos (5UL) /*!< I2S INTR: TX_OVERFLOW (Bit 5) */ +#define I2S_INTR_TX_OVERFLOW_Msk (0x20UL) /*!< I2S INTR: TX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_TX_UNDERFLOW_Pos (6UL) /*!< I2S INTR: TX_UNDERFLOW (Bit 6) */ +#define I2S_INTR_TX_UNDERFLOW_Msk (0x40UL) /*!< I2S INTR: TX_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_TX_WD_Pos (8UL) /*!< I2S INTR: TX_WD (Bit 8) */ +#define I2S_INTR_TX_WD_Msk (0x100UL) /*!< I2S INTR: TX_WD (Bitfield-Mask: 0x01) */ +#define I2S_INTR_RX_TRIGGER_Pos (16UL) /*!< I2S INTR: RX_TRIGGER (Bit 16) */ +#define I2S_INTR_RX_TRIGGER_Msk (0x10000UL) /*!< I2S INTR: RX_TRIGGER (Bitfield-Mask: 0x01) */ +#define I2S_INTR_RX_NOT_EMPTY_Pos (18UL) /*!< I2S INTR: RX_NOT_EMPTY (Bit 18) */ +#define I2S_INTR_RX_NOT_EMPTY_Msk (0x40000UL) /*!< I2S INTR: RX_NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define I2S_INTR_RX_FULL_Pos (19UL) /*!< I2S INTR: RX_FULL (Bit 19) */ +#define I2S_INTR_RX_FULL_Msk (0x80000UL) /*!< I2S INTR: RX_FULL (Bitfield-Mask: 0x01) */ +#define I2S_INTR_RX_OVERFLOW_Pos (21UL) /*!< I2S INTR: RX_OVERFLOW (Bit 21) */ +#define I2S_INTR_RX_OVERFLOW_Msk (0x200000UL) /*!< I2S INTR: RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_RX_UNDERFLOW_Pos (22UL) /*!< I2S INTR: RX_UNDERFLOW (Bit 22) */ +#define I2S_INTR_RX_UNDERFLOW_Msk (0x400000UL) /*!< I2S INTR: RX_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_RX_WD_Pos (24UL) /*!< I2S INTR: RX_WD (Bit 24) */ +#define I2S_INTR_RX_WD_Msk (0x1000000UL) /*!< I2S INTR: RX_WD (Bitfield-Mask: 0x01) */ +/* ===================================================== I2S.INTR_SET ====================================================== */ +#define I2S_INTR_SET_TX_TRIGGER_Pos (0UL) /*!< I2S INTR_SET: TX_TRIGGER (Bit 0) */ +#define I2S_INTR_SET_TX_TRIGGER_Msk (0x1UL) /*!< I2S INTR_SET: TX_TRIGGER (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_TX_NOT_FULL_Pos (1UL) /*!< I2S INTR_SET: TX_NOT_FULL (Bit 1) */ +#define I2S_INTR_SET_TX_NOT_FULL_Msk (0x2UL) /*!< I2S INTR_SET: TX_NOT_FULL (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_TX_EMPTY_Pos (4UL) /*!< I2S INTR_SET: TX_EMPTY (Bit 4) */ +#define I2S_INTR_SET_TX_EMPTY_Msk (0x10UL) /*!< I2S INTR_SET: TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_TX_OVERFLOW_Pos (5UL) /*!< I2S INTR_SET: TX_OVERFLOW (Bit 5) */ +#define I2S_INTR_SET_TX_OVERFLOW_Msk (0x20UL) /*!< I2S INTR_SET: TX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_TX_UNDERFLOW_Pos (6UL) /*!< I2S INTR_SET: TX_UNDERFLOW (Bit 6) */ +#define I2S_INTR_SET_TX_UNDERFLOW_Msk (0x40UL) /*!< I2S INTR_SET: TX_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_TX_WD_Pos (8UL) /*!< I2S INTR_SET: TX_WD (Bit 8) */ +#define I2S_INTR_SET_TX_WD_Msk (0x100UL) /*!< I2S INTR_SET: TX_WD (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_RX_TRIGGER_Pos (16UL) /*!< I2S INTR_SET: RX_TRIGGER (Bit 16) */ +#define I2S_INTR_SET_RX_TRIGGER_Msk (0x10000UL) /*!< I2S INTR_SET: RX_TRIGGER (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_RX_NOT_EMPTY_Pos (18UL) /*!< I2S INTR_SET: RX_NOT_EMPTY (Bit 18) */ +#define I2S_INTR_SET_RX_NOT_EMPTY_Msk (0x40000UL) /*!< I2S INTR_SET: RX_NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_RX_FULL_Pos (19UL) /*!< I2S INTR_SET: RX_FULL (Bit 19) */ +#define I2S_INTR_SET_RX_FULL_Msk (0x80000UL) /*!< I2S INTR_SET: RX_FULL (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_RX_OVERFLOW_Pos (21UL) /*!< I2S INTR_SET: RX_OVERFLOW (Bit 21) */ +#define I2S_INTR_SET_RX_OVERFLOW_Msk (0x200000UL) /*!< I2S INTR_SET: RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_RX_UNDERFLOW_Pos (22UL) /*!< I2S INTR_SET: RX_UNDERFLOW (Bit 22) */ +#define I2S_INTR_SET_RX_UNDERFLOW_Msk (0x400000UL) /*!< I2S INTR_SET: RX_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_SET_RX_WD_Pos (24UL) /*!< I2S INTR_SET: RX_WD (Bit 24) */ +#define I2S_INTR_SET_RX_WD_Msk (0x1000000UL) /*!< I2S INTR_SET: RX_WD (Bitfield-Mask: 0x01) */ +/* ===================================================== I2S.INTR_MASK ===================================================== */ +#define I2S_INTR_MASK_TX_TRIGGER_Pos (0UL) /*!< I2S INTR_MASK: TX_TRIGGER (Bit 0) */ +#define I2S_INTR_MASK_TX_TRIGGER_Msk (0x1UL) /*!< I2S INTR_MASK: TX_TRIGGER (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_TX_NOT_FULL_Pos (1UL) /*!< I2S INTR_MASK: TX_NOT_FULL (Bit 1) */ +#define I2S_INTR_MASK_TX_NOT_FULL_Msk (0x2UL) /*!< I2S INTR_MASK: TX_NOT_FULL (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_TX_EMPTY_Pos (4UL) /*!< I2S INTR_MASK: TX_EMPTY (Bit 4) */ +#define I2S_INTR_MASK_TX_EMPTY_Msk (0x10UL) /*!< I2S INTR_MASK: TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_TX_OVERFLOW_Pos (5UL) /*!< I2S INTR_MASK: TX_OVERFLOW (Bit 5) */ +#define I2S_INTR_MASK_TX_OVERFLOW_Msk (0x20UL) /*!< I2S INTR_MASK: TX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_TX_UNDERFLOW_Pos (6UL) /*!< I2S INTR_MASK: TX_UNDERFLOW (Bit 6) */ +#define I2S_INTR_MASK_TX_UNDERFLOW_Msk (0x40UL) /*!< I2S INTR_MASK: TX_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_TX_WD_Pos (8UL) /*!< I2S INTR_MASK: TX_WD (Bit 8) */ +#define I2S_INTR_MASK_TX_WD_Msk (0x100UL) /*!< I2S INTR_MASK: TX_WD (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_RX_TRIGGER_Pos (16UL) /*!< I2S INTR_MASK: RX_TRIGGER (Bit 16) */ +#define I2S_INTR_MASK_RX_TRIGGER_Msk (0x10000UL) /*!< I2S INTR_MASK: RX_TRIGGER (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_RX_NOT_EMPTY_Pos (18UL) /*!< I2S INTR_MASK: RX_NOT_EMPTY (Bit 18) */ +#define I2S_INTR_MASK_RX_NOT_EMPTY_Msk (0x40000UL) /*!< I2S INTR_MASK: RX_NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_RX_FULL_Pos (19UL) /*!< I2S INTR_MASK: RX_FULL (Bit 19) */ +#define I2S_INTR_MASK_RX_FULL_Msk (0x80000UL) /*!< I2S INTR_MASK: RX_FULL (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_RX_OVERFLOW_Pos (21UL) /*!< I2S INTR_MASK: RX_OVERFLOW (Bit 21) */ +#define I2S_INTR_MASK_RX_OVERFLOW_Msk (0x200000UL) /*!< I2S INTR_MASK: RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_RX_UNDERFLOW_Pos (22UL) /*!< I2S INTR_MASK: RX_UNDERFLOW (Bit 22) */ +#define I2S_INTR_MASK_RX_UNDERFLOW_Msk (0x400000UL) /*!< I2S INTR_MASK: RX_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASK_RX_WD_Pos (24UL) /*!< I2S INTR_MASK: RX_WD (Bit 24) */ +#define I2S_INTR_MASK_RX_WD_Msk (0x1000000UL) /*!< I2S INTR_MASK: RX_WD (Bitfield-Mask: 0x01) */ +/* ==================================================== I2S.INTR_MASKED ==================================================== */ +#define I2S_INTR_MASKED_TX_TRIGGER_Pos (0UL) /*!< I2S INTR_MASKED: TX_TRIGGER (Bit 0) */ +#define I2S_INTR_MASKED_TX_TRIGGER_Msk (0x1UL) /*!< I2S INTR_MASKED: TX_TRIGGER (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_TX_NOT_FULL_Pos (1UL) /*!< I2S INTR_MASKED: TX_NOT_FULL (Bit 1) */ +#define I2S_INTR_MASKED_TX_NOT_FULL_Msk (0x2UL) /*!< I2S INTR_MASKED: TX_NOT_FULL (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_TX_EMPTY_Pos (4UL) /*!< I2S INTR_MASKED: TX_EMPTY (Bit 4) */ +#define I2S_INTR_MASKED_TX_EMPTY_Msk (0x10UL) /*!< I2S INTR_MASKED: TX_EMPTY (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_TX_OVERFLOW_Pos (5UL) /*!< I2S INTR_MASKED: TX_OVERFLOW (Bit 5) */ +#define I2S_INTR_MASKED_TX_OVERFLOW_Msk (0x20UL) /*!< I2S INTR_MASKED: TX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_TX_UNDERFLOW_Pos (6UL) /*!< I2S INTR_MASKED: TX_UNDERFLOW (Bit 6) */ +#define I2S_INTR_MASKED_TX_UNDERFLOW_Msk (0x40UL) /*!< I2S INTR_MASKED: TX_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_TX_WD_Pos (8UL) /*!< I2S INTR_MASKED: TX_WD (Bit 8) */ +#define I2S_INTR_MASKED_TX_WD_Msk (0x100UL) /*!< I2S INTR_MASKED: TX_WD (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_RX_TRIGGER_Pos (16UL) /*!< I2S INTR_MASKED: RX_TRIGGER (Bit 16) */ +#define I2S_INTR_MASKED_RX_TRIGGER_Msk (0x10000UL) /*!< I2S INTR_MASKED: RX_TRIGGER (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_RX_NOT_EMPTY_Pos (18UL) /*!< I2S INTR_MASKED: RX_NOT_EMPTY (Bit 18) */ +#define I2S_INTR_MASKED_RX_NOT_EMPTY_Msk (0x40000UL) /*!< I2S INTR_MASKED: RX_NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_RX_FULL_Pos (19UL) /*!< I2S INTR_MASKED: RX_FULL (Bit 19) */ +#define I2S_INTR_MASKED_RX_FULL_Msk (0x80000UL) /*!< I2S INTR_MASKED: RX_FULL (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_RX_OVERFLOW_Pos (21UL) /*!< I2S INTR_MASKED: RX_OVERFLOW (Bit 21) */ +#define I2S_INTR_MASKED_RX_OVERFLOW_Msk (0x200000UL) /*!< I2S INTR_MASKED: RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_RX_UNDERFLOW_Pos (22UL) /*!< I2S INTR_MASKED: RX_UNDERFLOW (Bit 22) */ +#define I2S_INTR_MASKED_RX_UNDERFLOW_Msk (0x400000UL) /*!< I2S INTR_MASKED: RX_UNDERFLOW (Bitfield-Mask: 0x01) */ +#define I2S_INTR_MASKED_RX_WD_Pos (24UL) /*!< I2S INTR_MASKED: RX_WD (Bit 24) */ +#define I2S_INTR_MASKED_RX_WD_Msk (0x1000000UL) /*!< I2S INTR_MASKED: RX_WD (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_I2S_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ipc.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ipc.h new file mode 100644 index 0000000000..7b77442ab6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_ipc.h @@ -0,0 +1,123 @@ +/***************************************************************************//** +* \file cyip_ipc.h +* +* \brief +* IPC IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_IPC_H_ +#define _CYIP_IPC_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ IPC ================ */ +/* =========================================================================================================================== */ + +#define IPC_STRUCT_SECTION_SIZE 0x00000020UL +#define IPC_INTR_STRUCT_SECTION_SIZE 0x00000020UL +#define IPC_SECTION_SIZE 0x00010000UL + +/** + * \brief IPC structure (IPC_STRUCT) + */ +typedef struct { + __IM uint32_t ACQUIRE; /*!< 0x00000000 IPC acquire */ + __OM uint32_t RELEASE; /*!< 0x00000004 IPC release */ + __OM uint32_t NOTIFY; /*!< 0x00000008 IPC notification */ + __IOM uint32_t DATA; /*!< 0x0000000C IPC data */ + __IM uint32_t LOCK_STATUS; /*!< 0x00000010 IPC lock status */ + __IM uint32_t RESERVED[3]; +} IPC_STRUCT_Type; /*!< Size = 20 (0x14) */ + +/** + * \brief IPC interrupt structure (IPC_INTR_STRUCT) + */ +typedef struct { + __IOM uint32_t INTR; /*!< 0x00000000 Interrupt */ + __IOM uint32_t INTR_SET; /*!< 0x00000004 Interrupt set */ + __IOM uint32_t INTR_MASK; /*!< 0x00000008 Interrupt mask */ + __IM uint32_t INTR_MASKED; /*!< 0x0000000C Interrupt masked */ + __IM uint32_t RESERVED[4]; +} IPC_INTR_STRUCT_Type; /*!< Size = 16 (0x10) */ + +/** + * \brief IPC (IPC) + */ +typedef struct { /*!< IPC Structure */ + IPC_STRUCT_Type STRUCT[16]; /*!< 0x00000000 IPC structure */ + __IM uint32_t RESERVED[896]; + IPC_INTR_STRUCT_Type INTR_STRUCT[16]; /*!< 0x00001000 IPC interrupt structure */ +} IPC_Type; /*!< Size = 4608 (0x1200) */ + + +/* ================================================== IPC_STRUCT.ACQUIRE =================================================== */ +#define IPC_STRUCT_ACQUIRE_P_Pos (0UL) /*!< IPC_STRUCT ACQUIRE: P (Bit 0) */ +#define IPC_STRUCT_ACQUIRE_P_Msk (0x1UL) /*!< IPC_STRUCT ACQUIRE: P (Bitfield-Mask: 0x01) */ +#define IPC_STRUCT_ACQUIRE_NS_Pos (1UL) /*!< IPC_STRUCT ACQUIRE: NS (Bit 1) */ +#define IPC_STRUCT_ACQUIRE_NS_Msk (0x2UL) /*!< IPC_STRUCT ACQUIRE: NS (Bitfield-Mask: 0x01) */ +#define IPC_STRUCT_ACQUIRE_PC_Pos (4UL) /*!< IPC_STRUCT ACQUIRE: PC (Bit 4) */ +#define IPC_STRUCT_ACQUIRE_PC_Msk (0xf0UL) /*!< IPC_STRUCT ACQUIRE: PC (Bitfield-Mask: 0x0f) */ +#define IPC_STRUCT_ACQUIRE_MS_Pos (8UL) /*!< IPC_STRUCT ACQUIRE: MS (Bit 8) */ +#define IPC_STRUCT_ACQUIRE_MS_Msk (0xf00UL) /*!< IPC_STRUCT ACQUIRE: MS (Bitfield-Mask: 0x0f) */ +#define IPC_STRUCT_ACQUIRE_SUCCESS_Pos (31UL) /*!< IPC_STRUCT ACQUIRE: SUCCESS (Bit 31) */ +#define IPC_STRUCT_ACQUIRE_SUCCESS_Msk (0x80000000UL) /*!< IPC_STRUCT ACQUIRE: SUCCESS (Bitfield-Mask: 0x01) */ +/* ================================================== IPC_STRUCT.RELEASE =================================================== */ +#define IPC_STRUCT_RELEASE_INTR_RELEASE_Pos (0UL) /*!< IPC_STRUCT RELEASE: INTR_RELEASE (Bit 0) */ +#define IPC_STRUCT_RELEASE_INTR_RELEASE_Msk (0xffffUL) /*!< IPC_STRUCT RELEASE: INTR_RELEASE (Bitfield-Mask: 0xffff) */ +/* =================================================== IPC_STRUCT.NOTIFY =================================================== */ +#define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Pos (0UL) /*!< IPC_STRUCT NOTIFY: INTR_NOTIFY (Bit 0) */ +#define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk (0xffffUL) /*!< IPC_STRUCT NOTIFY: INTR_NOTIFY (Bitfield-Mask: 0xffff) */ +/* ==================================================== IPC_STRUCT.DATA ==================================================== */ +#define IPC_STRUCT_DATA_DATA_Pos (0UL) /*!< IPC_STRUCT DATA: DATA (Bit 0) */ +#define IPC_STRUCT_DATA_DATA_Msk (0xffffffffUL) /*!< IPC_STRUCT DATA: DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================ IPC_STRUCT.LOCK_STATUS ================================================= */ +#define IPC_STRUCT_LOCK_STATUS_P_Pos (0UL) /*!< IPC_STRUCT LOCK_STATUS: P (Bit 0) */ +#define IPC_STRUCT_LOCK_STATUS_P_Msk (0x1UL) /*!< IPC_STRUCT LOCK_STATUS: P (Bitfield-Mask: 0x01) */ +#define IPC_STRUCT_LOCK_STATUS_NS_Pos (1UL) /*!< IPC_STRUCT LOCK_STATUS: NS (Bit 1) */ +#define IPC_STRUCT_LOCK_STATUS_NS_Msk (0x2UL) /*!< IPC_STRUCT LOCK_STATUS: NS (Bitfield-Mask: 0x01) */ +#define IPC_STRUCT_LOCK_STATUS_PC_Pos (4UL) /*!< IPC_STRUCT LOCK_STATUS: PC (Bit 4) */ +#define IPC_STRUCT_LOCK_STATUS_PC_Msk (0xf0UL) /*!< IPC_STRUCT LOCK_STATUS: PC (Bitfield-Mask: 0x0f) */ +#define IPC_STRUCT_LOCK_STATUS_MS_Pos (8UL) /*!< IPC_STRUCT LOCK_STATUS: MS (Bit 8) */ +#define IPC_STRUCT_LOCK_STATUS_MS_Msk (0xf00UL) /*!< IPC_STRUCT LOCK_STATUS: MS (Bitfield-Mask: 0x0f) */ +#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Pos (31UL) /*!< IPC_STRUCT LOCK_STATUS: ACQUIRED (Bit 31) */ +#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Msk (0x80000000UL) /*!< IPC_STRUCT LOCK_STATUS: ACQUIRED (Bitfield-Mask: 0x01) */ + + +/* ================================================= IPC_INTR_STRUCT.INTR ================================================== */ +#define IPC_INTR_STRUCT_INTR_RELEASE_Pos (0UL) /*!< IPC_INTR_STRUCT INTR: RELEASE (Bit 0) */ +#define IPC_INTR_STRUCT_INTR_RELEASE_Msk (0xffffUL) /*!< IPC_INTR_STRUCT INTR: RELEASE (Bitfield-Mask: 0xffff) */ +#define IPC_INTR_STRUCT_INTR_NOTIFY_Pos (16UL) /*!< IPC_INTR_STRUCT INTR: NOTIFY (Bit 16) */ +#define IPC_INTR_STRUCT_INTR_NOTIFY_Msk (0xffff0000UL) /*!< IPC_INTR_STRUCT INTR: NOTIFY (Bitfield-Mask: 0xffff) */ +/* =============================================== IPC_INTR_STRUCT.INTR_SET ================================================ */ +#define IPC_INTR_STRUCT_INTR_SET_RELEASE_Pos (0UL) /*!< IPC_INTR_STRUCT INTR_SET: RELEASE (Bit 0) */ +#define IPC_INTR_STRUCT_INTR_SET_RELEASE_Msk (0xffffUL) /*!< IPC_INTR_STRUCT INTR_SET: RELEASE (Bitfield-Mask: 0xffff) */ +#define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Pos (16UL) /*!< IPC_INTR_STRUCT INTR_SET: NOTIFY (Bit 16) */ +#define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Msk (0xffff0000UL) /*!< IPC_INTR_STRUCT INTR_SET: NOTIFY (Bitfield-Mask: 0xffff) */ +/* =============================================== IPC_INTR_STRUCT.INTR_MASK =============================================== */ +#define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Pos (0UL) /*!< IPC_INTR_STRUCT INTR_MASK: RELEASE (Bit 0) */ +#define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk (0xffffUL) /*!< IPC_INTR_STRUCT INTR_MASK: RELEASE (Bitfield-Mask: 0xffff)*/ +#define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Pos (16UL) /*!< IPC_INTR_STRUCT INTR_MASK: NOTIFY (Bit 16) */ +#define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk (0xffff0000UL) /*!< IPC_INTR_STRUCT INTR_MASK: NOTIFY (Bitfield-Mask: 0xffff) */ +/* ============================================== IPC_INTR_STRUCT.INTR_MASKED ============================================== */ +#define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Pos (0UL) /*!< IPC_INTR_STRUCT INTR_MASKED: RELEASE (Bit 0) */ +#define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Msk (0xffffUL) /*!< IPC_INTR_STRUCT INTR_MASKED: RELEASE (Bitfield-Mask: 0xffff)*/ +#define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Pos (16UL) /*!< IPC_INTR_STRUCT INTR_MASKED: NOTIFY (Bit 16) */ +#define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Msk (0xffff0000UL) /*!< IPC_INTR_STRUCT INTR_MASKED: NOTIFY (Bitfield-Mask: 0xffff)*/ + + +#endif /* _CYIP_IPC_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_lcd.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_lcd.h new file mode 100644 index 0000000000..d0b63983bb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_lcd.h @@ -0,0 +1,92 @@ +/***************************************************************************//** +* \file cyip_lcd.h +* +* \brief +* LCD IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_LCD_H_ +#define _CYIP_LCD_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ LCD ================ */ +/* =========================================================================================================================== */ + +#define LCD_SECTION_SIZE 0x00010000UL + +/** + * \brief LCD Controller Block (LCD) + */ +typedef struct { /*!< LCD Structure */ + __IM uint32_t ID; /*!< 0x00000000 ID & Revision */ + __IOM uint32_t DIVIDER; /*!< 0x00000004 LCD Divider Register */ + __IOM uint32_t CONTROL; /*!< 0x00000008 LCD Configuration Register */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t DATA0[8]; /*!< 0x00000100 LCD Pin Data Registers */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t DATA1[8]; /*!< 0x00000200 LCD Pin Data Registers */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t DATA2[8]; /*!< 0x00000300 LCD Pin Data Registers */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t DATA3[8]; /*!< 0x00000400 LCD Pin Data Registers */ +} LCD_Type; /*!< Size = 1056 (0x420) */ + + +/* ======================================================== LCD.ID ========================================================= */ +#define LCD_ID_ID_Pos (0UL) /*!< LCD ID: ID (Bit 0) */ +#define LCD_ID_ID_Msk (0xffffUL) /*!< LCD ID: ID (Bitfield-Mask: 0xffff) */ +#define LCD_ID_REVISION_Pos (16UL) /*!< LCD ID: REVISION (Bit 16) */ +#define LCD_ID_REVISION_Msk (0xffff0000UL) /*!< LCD ID: REVISION (Bitfield-Mask: 0xffff) */ +/* ====================================================== LCD.DIVIDER ====================================================== */ +#define LCD_DIVIDER_SUBFR_DIV_Pos (0UL) /*!< LCD DIVIDER: SUBFR_DIV (Bit 0) */ +#define LCD_DIVIDER_SUBFR_DIV_Msk (0xffffUL) /*!< LCD DIVIDER: SUBFR_DIV (Bitfield-Mask: 0xffff) */ +#define LCD_DIVIDER_DEAD_DIV_Pos (16UL) /*!< LCD DIVIDER: DEAD_DIV (Bit 16) */ +#define LCD_DIVIDER_DEAD_DIV_Msk (0xffff0000UL) /*!< LCD DIVIDER: DEAD_DIV (Bitfield-Mask: 0xffff) */ +/* ====================================================== LCD.CONTROL ====================================================== */ +#define LCD_CONTROL_LS_EN_Pos (0UL) /*!< LCD CONTROL: LS_EN (Bit 0) */ +#define LCD_CONTROL_LS_EN_Msk (0x1UL) /*!< LCD CONTROL: LS_EN (Bitfield-Mask: 0x01) */ +#define LCD_CONTROL_HS_EN_Pos (1UL) /*!< LCD CONTROL: HS_EN (Bit 1) */ +#define LCD_CONTROL_HS_EN_Msk (0x2UL) /*!< LCD CONTROL: HS_EN (Bitfield-Mask: 0x01) */ +#define LCD_CONTROL_LCD_MODE_Pos (2UL) /*!< LCD CONTROL: LCD_MODE (Bit 2) */ +#define LCD_CONTROL_LCD_MODE_Msk (0x4UL) /*!< LCD CONTROL: LCD_MODE (Bitfield-Mask: 0x01) */ +#define LCD_CONTROL_TYPE_Pos (3UL) /*!< LCD CONTROL: TYPE (Bit 3) */ +#define LCD_CONTROL_TYPE_Msk (0x8UL) /*!< LCD CONTROL: TYPE (Bitfield-Mask: 0x01) */ +#define LCD_CONTROL_OP_MODE_Pos (4UL) /*!< LCD CONTROL: OP_MODE (Bit 4) */ +#define LCD_CONTROL_OP_MODE_Msk (0x10UL) /*!< LCD CONTROL: OP_MODE (Bitfield-Mask: 0x01) */ +#define LCD_CONTROL_BIAS_Pos (5UL) /*!< LCD CONTROL: BIAS (Bit 5) */ +#define LCD_CONTROL_BIAS_Msk (0x60UL) /*!< LCD CONTROL: BIAS (Bitfield-Mask: 0x03) */ +#define LCD_CONTROL_COM_NUM_Pos (8UL) /*!< LCD CONTROL: COM_NUM (Bit 8) */ +#define LCD_CONTROL_COM_NUM_Msk (0xf00UL) /*!< LCD CONTROL: COM_NUM (Bitfield-Mask: 0x0f) */ +#define LCD_CONTROL_LS_EN_STAT_Pos (31UL) /*!< LCD CONTROL: LS_EN_STAT (Bit 31) */ +#define LCD_CONTROL_LS_EN_STAT_Msk (0x80000000UL) /*!< LCD CONTROL: LS_EN_STAT (Bitfield-Mask: 0x01) */ +/* ======================================================= LCD.DATA0 ======================================================= */ +#define LCD_DATA0_DATA_Pos (0UL) /*!< LCD DATA0: DATA (Bit 0) */ +#define LCD_DATA0_DATA_Msk (0xffffffffUL) /*!< LCD DATA0: DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LCD.DATA1 ======================================================= */ +#define LCD_DATA1_DATA_Pos (0UL) /*!< LCD DATA1: DATA (Bit 0) */ +#define LCD_DATA1_DATA_Msk (0xffffffffUL) /*!< LCD DATA1: DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LCD.DATA2 ======================================================= */ +#define LCD_DATA2_DATA_Pos (0UL) /*!< LCD DATA2: DATA (Bit 0) */ +#define LCD_DATA2_DATA_Msk (0xffffffffUL) /*!< LCD DATA2: DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LCD.DATA3 ======================================================= */ +#define LCD_DATA3_DATA_Pos (0UL) /*!< LCD DATA3: DATA (Bit 0) */ +#define LCD_DATA3_DATA_Msk (0xffffffffUL) /*!< LCD DATA3: DATA (Bitfield-Mask: 0xffffffff) */ + + +#endif /* _CYIP_LCD_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_lpcomp.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_lpcomp.h new file mode 100644 index 0000000000..a34e5605dd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_lpcomp.h @@ -0,0 +1,171 @@ +/***************************************************************************//** +* \file cyip_lpcomp.h +* +* \brief +* LPCOMP IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_LPCOMP_H_ +#define _CYIP_LPCOMP_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + +#define LPCOMP_SECTION_SIZE 0x00010000UL + +/** + * \brief Low Power Comparators (LPCOMP) + */ +typedef struct { /*!< LPCOMP Structure */ + __IOM uint32_t CONFIG; /*!< 0x00000000 LPCOMP Configuration Register */ + __IM uint32_t STATUS; /*!< 0x00000004 LPCOMP Status Register */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t INTR; /*!< 0x00000010 LPCOMP Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000014 LPCOMP Interrupt set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000018 LPCOMP Interrupt request mask */ + __IM uint32_t INTR_MASKED; /*!< 0x0000001C LPCOMP Interrupt request masked */ + __IM uint32_t RESERVED1[8]; + __IOM uint32_t CMP0_CTRL; /*!< 0x00000040 Comparator 0 control Register */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t CMP0_SW; /*!< 0x00000050 Comparator 0 switch control */ + __IOM uint32_t CMP0_SW_CLEAR; /*!< 0x00000054 Comparator 0 switch control clear */ + __IM uint32_t RESERVED3[10]; + __IOM uint32_t CMP1_CTRL; /*!< 0x00000080 Comparator 1 control Register */ + __IM uint32_t RESERVED4[3]; + __IOM uint32_t CMP1_SW; /*!< 0x00000090 Comparator 1 switch control */ + __IOM uint32_t CMP1_SW_CLEAR; /*!< 0x00000094 Comparator 1 switch control clear */ +} LPCOMP_Type; /*!< Size = 152 (0x98) */ + + +/* ===================================================== LPCOMP.CONFIG ===================================================== */ +#define LPCOMP_CONFIG_LPREF_EN_Pos (30UL) /*!< LPCOMP CONFIG: LPREF_EN (Bit 30) */ +#define LPCOMP_CONFIG_LPREF_EN_Msk (0x40000000UL) /*!< LPCOMP CONFIG: LPREF_EN (Bitfield-Mask: 0x01) */ +#define LPCOMP_CONFIG_ENABLED_Pos (31UL) /*!< LPCOMP CONFIG: ENABLED (Bit 31) */ +#define LPCOMP_CONFIG_ENABLED_Msk (0x80000000UL) /*!< LPCOMP CONFIG: ENABLED (Bitfield-Mask: 0x01) */ +/* ===================================================== LPCOMP.STATUS ===================================================== */ +#define LPCOMP_STATUS_OUT0_Pos (0UL) /*!< LPCOMP STATUS: OUT0 (Bit 0) */ +#define LPCOMP_STATUS_OUT0_Msk (0x1UL) /*!< LPCOMP STATUS: OUT0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_STATUS_OUT1_Pos (16UL) /*!< LPCOMP STATUS: OUT1 (Bit 16) */ +#define LPCOMP_STATUS_OUT1_Msk (0x10000UL) /*!< LPCOMP STATUS: OUT1 (Bitfield-Mask: 0x01) */ +/* ====================================================== LPCOMP.INTR ====================================================== */ +#define LPCOMP_INTR_COMP0_Pos (0UL) /*!< LPCOMP INTR: COMP0 (Bit 0) */ +#define LPCOMP_INTR_COMP0_Msk (0x1UL) /*!< LPCOMP INTR: COMP0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_INTR_COMP1_Pos (1UL) /*!< LPCOMP INTR: COMP1 (Bit 1) */ +#define LPCOMP_INTR_COMP1_Msk (0x2UL) /*!< LPCOMP INTR: COMP1 (Bitfield-Mask: 0x01) */ +/* ==================================================== LPCOMP.INTR_SET ==================================================== */ +#define LPCOMP_INTR_SET_COMP0_Pos (0UL) /*!< LPCOMP INTR_SET: COMP0 (Bit 0) */ +#define LPCOMP_INTR_SET_COMP0_Msk (0x1UL) /*!< LPCOMP INTR_SET: COMP0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_INTR_SET_COMP1_Pos (1UL) /*!< LPCOMP INTR_SET: COMP1 (Bit 1) */ +#define LPCOMP_INTR_SET_COMP1_Msk (0x2UL) /*!< LPCOMP INTR_SET: COMP1 (Bitfield-Mask: 0x01) */ +/* =================================================== LPCOMP.INTR_MASK ==================================================== */ +#define LPCOMP_INTR_MASK_COMP0_MASK_Pos (0UL) /*!< LPCOMP INTR_MASK: COMP0_MASK (Bit 0) */ +#define LPCOMP_INTR_MASK_COMP0_MASK_Msk (0x1UL) /*!< LPCOMP INTR_MASK: COMP0_MASK (Bitfield-Mask: 0x01) */ +#define LPCOMP_INTR_MASK_COMP1_MASK_Pos (1UL) /*!< LPCOMP INTR_MASK: COMP1_MASK (Bit 1) */ +#define LPCOMP_INTR_MASK_COMP1_MASK_Msk (0x2UL) /*!< LPCOMP INTR_MASK: COMP1_MASK (Bitfield-Mask: 0x01) */ +/* ================================================== LPCOMP.INTR_MASKED =================================================== */ +#define LPCOMP_INTR_MASKED_COMP0_MASKED_Pos (0UL) /*!< LPCOMP INTR_MASKED: COMP0_MASKED (Bit 0) */ +#define LPCOMP_INTR_MASKED_COMP0_MASKED_Msk (0x1UL) /*!< LPCOMP INTR_MASKED: COMP0_MASKED (Bitfield-Mask: 0x01) */ +#define LPCOMP_INTR_MASKED_COMP1_MASKED_Pos (1UL) /*!< LPCOMP INTR_MASKED: COMP1_MASKED (Bit 1) */ +#define LPCOMP_INTR_MASKED_COMP1_MASKED_Msk (0x2UL) /*!< LPCOMP INTR_MASKED: COMP1_MASKED (Bitfield-Mask: 0x01) */ +/* =================================================== LPCOMP.CMP0_CTRL ==================================================== */ +#define LPCOMP_CMP0_CTRL_MODE0_Pos (0UL) /*!< LPCOMP CMP0_CTRL: MODE0 (Bit 0) */ +#define LPCOMP_CMP0_CTRL_MODE0_Msk (0x3UL) /*!< LPCOMP CMP0_CTRL: MODE0 (Bitfield-Mask: 0x03) */ +#define LPCOMP_CMP0_CTRL_HYST0_Pos (5UL) /*!< LPCOMP CMP0_CTRL: HYST0 (Bit 5) */ +#define LPCOMP_CMP0_CTRL_HYST0_Msk (0x20UL) /*!< LPCOMP CMP0_CTRL: HYST0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_CTRL_INTTYPE0_Pos (6UL) /*!< LPCOMP CMP0_CTRL: INTTYPE0 (Bit 6) */ +#define LPCOMP_CMP0_CTRL_INTTYPE0_Msk (0xc0UL) /*!< LPCOMP CMP0_CTRL: INTTYPE0 (Bitfield-Mask: 0x03) */ +#define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos (10UL) /*!< LPCOMP CMP0_CTRL: DSI_BYPASS0 (Bit 10) */ +#define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk (0x400UL) /*!< LPCOMP CMP0_CTRL: DSI_BYPASS0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Pos (11UL) /*!< LPCOMP CMP0_CTRL: DSI_LEVEL0 (Bit 11) */ +#define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk (0x800UL) /*!< LPCOMP CMP0_CTRL: DSI_LEVEL0 (Bitfield-Mask: 0x01) */ +/* ==================================================== LPCOMP.CMP0_SW ===================================================== */ +#define LPCOMP_CMP0_SW_CMP0_IP0_Pos (0UL) /*!< LPCOMP CMP0_SW: CMP0_IP0 (Bit 0) */ +#define LPCOMP_CMP0_SW_CMP0_IP0_Msk (0x1UL) /*!< LPCOMP CMP0_SW: CMP0_IP0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CMP0_AP0_Pos (1UL) /*!< LPCOMP CMP0_SW: CMP0_AP0 (Bit 1) */ +#define LPCOMP_CMP0_SW_CMP0_AP0_Msk (0x2UL) /*!< LPCOMP CMP0_SW: CMP0_AP0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CMP0_BP0_Pos (2UL) /*!< LPCOMP CMP0_SW: CMP0_BP0 (Bit 2) */ +#define LPCOMP_CMP0_SW_CMP0_BP0_Msk (0x4UL) /*!< LPCOMP CMP0_SW: CMP0_BP0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CMP0_IN0_Pos (4UL) /*!< LPCOMP CMP0_SW: CMP0_IN0 (Bit 4) */ +#define LPCOMP_CMP0_SW_CMP0_IN0_Msk (0x10UL) /*!< LPCOMP CMP0_SW: CMP0_IN0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CMP0_AN0_Pos (5UL) /*!< LPCOMP CMP0_SW: CMP0_AN0 (Bit 5) */ +#define LPCOMP_CMP0_SW_CMP0_AN0_Msk (0x20UL) /*!< LPCOMP CMP0_SW: CMP0_AN0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CMP0_BN0_Pos (6UL) /*!< LPCOMP CMP0_SW: CMP0_BN0 (Bit 6) */ +#define LPCOMP_CMP0_SW_CMP0_BN0_Msk (0x40UL) /*!< LPCOMP CMP0_SW: CMP0_BN0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CMP0_VN0_Pos (7UL) /*!< LPCOMP CMP0_SW: CMP0_VN0 (Bit 7) */ +#define LPCOMP_CMP0_SW_CMP0_VN0_Msk (0x80UL) /*!< LPCOMP CMP0_SW: CMP0_VN0 (Bitfield-Mask: 0x01) */ +/* ================================================= LPCOMP.CMP0_SW_CLEAR ================================================== */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Pos (0UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_IP0 (Bit 0) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Msk (0x1UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_IP0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Pos (1UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_AP0 (Bit 1) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Msk (0x2UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_AP0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Pos (2UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_BP0 (Bit 2) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Msk (0x4UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_BP0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Pos (4UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_IN0 (Bit 4) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Msk (0x10UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_IN0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Pos (5UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_AN0 (Bit 5) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Msk (0x20UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_AN0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Pos (6UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_BN0 (Bit 6) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Msk (0x40UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_BN0 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Pos (7UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_VN0 (Bit 7) */ +#define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Msk (0x80UL) /*!< LPCOMP CMP0_SW_CLEAR: CMP0_VN0 (Bitfield-Mask: 0x01) */ +/* =================================================== LPCOMP.CMP1_CTRL ==================================================== */ +#define LPCOMP_CMP1_CTRL_MODE1_Pos (0UL) /*!< LPCOMP CMP1_CTRL: MODE1 (Bit 0) */ +#define LPCOMP_CMP1_CTRL_MODE1_Msk (0x3UL) /*!< LPCOMP CMP1_CTRL: MODE1 (Bitfield-Mask: 0x03) */ +#define LPCOMP_CMP1_CTRL_HYST1_Pos (5UL) /*!< LPCOMP CMP1_CTRL: HYST1 (Bit 5) */ +#define LPCOMP_CMP1_CTRL_HYST1_Msk (0x20UL) /*!< LPCOMP CMP1_CTRL: HYST1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_CTRL_INTTYPE1_Pos (6UL) /*!< LPCOMP CMP1_CTRL: INTTYPE1 (Bit 6) */ +#define LPCOMP_CMP1_CTRL_INTTYPE1_Msk (0xc0UL) /*!< LPCOMP CMP1_CTRL: INTTYPE1 (Bitfield-Mask: 0x03) */ +#define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos (10UL) /*!< LPCOMP CMP1_CTRL: DSI_BYPASS1 (Bit 10) */ +#define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk (0x400UL) /*!< LPCOMP CMP1_CTRL: DSI_BYPASS1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Pos (11UL) /*!< LPCOMP CMP1_CTRL: DSI_LEVEL1 (Bit 11) */ +#define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk (0x800UL) /*!< LPCOMP CMP1_CTRL: DSI_LEVEL1 (Bitfield-Mask: 0x01) */ +/* ==================================================== LPCOMP.CMP1_SW ===================================================== */ +#define LPCOMP_CMP1_SW_CMP1_IP1_Pos (0UL) /*!< LPCOMP CMP1_SW: CMP1_IP1 (Bit 0) */ +#define LPCOMP_CMP1_SW_CMP1_IP1_Msk (0x1UL) /*!< LPCOMP CMP1_SW: CMP1_IP1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CMP1_AP1_Pos (1UL) /*!< LPCOMP CMP1_SW: CMP1_AP1 (Bit 1) */ +#define LPCOMP_CMP1_SW_CMP1_AP1_Msk (0x2UL) /*!< LPCOMP CMP1_SW: CMP1_AP1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CMP1_BP1_Pos (2UL) /*!< LPCOMP CMP1_SW: CMP1_BP1 (Bit 2) */ +#define LPCOMP_CMP1_SW_CMP1_BP1_Msk (0x4UL) /*!< LPCOMP CMP1_SW: CMP1_BP1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CMP1_IN1_Pos (4UL) /*!< LPCOMP CMP1_SW: CMP1_IN1 (Bit 4) */ +#define LPCOMP_CMP1_SW_CMP1_IN1_Msk (0x10UL) /*!< LPCOMP CMP1_SW: CMP1_IN1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CMP1_AN1_Pos (5UL) /*!< LPCOMP CMP1_SW: CMP1_AN1 (Bit 5) */ +#define LPCOMP_CMP1_SW_CMP1_AN1_Msk (0x20UL) /*!< LPCOMP CMP1_SW: CMP1_AN1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CMP1_BN1_Pos (6UL) /*!< LPCOMP CMP1_SW: CMP1_BN1 (Bit 6) */ +#define LPCOMP_CMP1_SW_CMP1_BN1_Msk (0x40UL) /*!< LPCOMP CMP1_SW: CMP1_BN1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CMP1_VN1_Pos (7UL) /*!< LPCOMP CMP1_SW: CMP1_VN1 (Bit 7) */ +#define LPCOMP_CMP1_SW_CMP1_VN1_Msk (0x80UL) /*!< LPCOMP CMP1_SW: CMP1_VN1 (Bitfield-Mask: 0x01) */ +/* ================================================= LPCOMP.CMP1_SW_CLEAR ================================================== */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Pos (0UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_IP1 (Bit 0) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Msk (0x1UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_IP1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Pos (1UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_AP1 (Bit 1) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Msk (0x2UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_AP1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Pos (2UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_BP1 (Bit 2) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Msk (0x4UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_BP1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Pos (4UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_IN1 (Bit 4) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Msk (0x10UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_IN1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Pos (5UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_AN1 (Bit 5) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Msk (0x20UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_AN1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Pos (6UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_BN1 (Bit 6) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Msk (0x40UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_BN1 (Bitfield-Mask: 0x01) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Pos (7UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_VN1 (Bit 7) */ +#define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Msk (0x80UL) /*!< LPCOMP CMP1_SW_CLEAR: CMP1_VN1 (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_LPCOMP_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_pass.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_pass.h new file mode 100644 index 0000000000..89082a4854 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_pass.h @@ -0,0 +1,130 @@ +/***************************************************************************//** +* \file cyip_pass.h +* +* \brief +* PASS IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_PASS_H_ +#define _CYIP_PASS_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ PASS ================ */ +/* =========================================================================================================================== */ + +#define PASS_AREF_SECTION_SIZE 0x00000100UL +#define PASS_SECTION_SIZE 0x00010000UL + +/** + * \brief AREF configuration (PASS_AREF) + */ +typedef struct { + __IOM uint32_t AREF_CTRL; /*!< 0x00000000 global AREF control */ + __IM uint32_t RESERVED[63]; +} PASS_AREF_Type; /*!< Size = 4 (0x4) */ + +/** + * \brief PASS top-level MMIO (DSABv2, INTR) (PASS) + */ +typedef struct { /*!< PASS Structure */ + __IM uint32_t INTR_CAUSE; /*!< 0x00000000 Interrupt cause register */ + __IM uint32_t RESERVED[895]; + PASS_AREF_Type AREF; /*!< 0x00000E00 AREF configuration */ + __IOM uint32_t VREF_TRIM0; /*!< 0x00000F00 VREF Trim bits */ + __IOM uint32_t VREF_TRIM1; /*!< 0x00000F04 VREF Trim bits */ + __IOM uint32_t VREF_TRIM2; /*!< 0x00000F08 VREF Trim bits */ + __IOM uint32_t VREF_TRIM3; /*!< 0x00000F0C VREF Trim bits */ + __IOM uint32_t IZTAT_TRIM0; /*!< 0x00000F10 IZTAT Trim bits */ + __IOM uint32_t IZTAT_TRIM1; /*!< 0x00000F14 IZTAT Trim bits */ + __IOM uint32_t IPTAT_TRIM0; /*!< 0x00000F18 IPTAT Trim bits */ + __IOM uint32_t ICTAT_TRIM0; /*!< 0x00000F1C ICTAT Trim bits */ +} PASS_Type; /*!< Size = 3872 (0xF20) */ + + +/* ================================================== PASS_AREF.AREF_CTRL ================================================== */ +#define PASS_AREF_AREF_CTRL_AREF_MODE_Pos (0UL) /*!< PASS_AREF AREF_CTRL: AREF_MODE (Bit 0) */ +#define PASS_AREF_AREF_CTRL_AREF_MODE_Msk (0x1UL) /*!< PASS_AREF AREF_CTRL: AREF_MODE (Bitfield-Mask: 0x01) */ +#define PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Pos (2UL) /*!< PASS_AREF AREF_CTRL: AREF_BIAS_SCALE (Bit 2) */ +#define PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Msk (0xcUL) /*!< PASS_AREF AREF_CTRL: AREF_BIAS_SCALE (Bitfield-Mask: 0x03)*/ +#define PASS_AREF_AREF_CTRL_AREF_RMB_Pos (4UL) /*!< PASS_AREF AREF_CTRL: AREF_RMB (Bit 4) */ +#define PASS_AREF_AREF_CTRL_AREF_RMB_Msk (0x70UL) /*!< PASS_AREF AREF_CTRL: AREF_RMB (Bitfield-Mask: 0x07) */ +#define PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Pos (7UL) /*!< PASS_AREF AREF_CTRL: CTB_IPTAT_SCALE (Bit 7) */ +#define PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Msk (0x80UL) /*!< PASS_AREF AREF_CTRL: CTB_IPTAT_SCALE (Bitfield-Mask: 0x01)*/ +#define PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Pos (8UL) /*!< PASS_AREF AREF_CTRL: CTB_IPTAT_REDIRECT (Bit 8) */ +#define PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk (0xff00UL) /*!< PASS_AREF AREF_CTRL: CTB_IPTAT_REDIRECT (Bitfield-Mask: 0xff)*/ +#define PASS_AREF_AREF_CTRL_IZTAT_SEL_Pos (16UL) /*!< PASS_AREF AREF_CTRL: IZTAT_SEL (Bit 16) */ +#define PASS_AREF_AREF_CTRL_IZTAT_SEL_Msk (0x10000UL) /*!< PASS_AREF AREF_CTRL: IZTAT_SEL (Bitfield-Mask: 0x01) */ +#define PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos (19UL) /*!< PASS_AREF AREF_CTRL: CLOCK_PUMP_PERI_SEL (Bit 19) */ +#define PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk (0x80000UL) /*!< PASS_AREF AREF_CTRL: CLOCK_PUMP_PERI_SEL (Bitfield-Mask: 0x01)*/ +#define PASS_AREF_AREF_CTRL_VREF_SEL_Pos (20UL) /*!< PASS_AREF AREF_CTRL: VREF_SEL (Bit 20) */ +#define PASS_AREF_AREF_CTRL_VREF_SEL_Msk (0x300000UL) /*!< PASS_AREF AREF_CTRL: VREF_SEL (Bitfield-Mask: 0x03) */ +#define PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Pos (28UL) /*!< PASS_AREF AREF_CTRL: DEEPSLEEP_MODE (Bit 28) */ +#define PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Msk (0x30000000UL) /*!< PASS_AREF AREF_CTRL: DEEPSLEEP_MODE (Bitfield-Mask: 0x03) */ +#define PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Pos (30UL) /*!< PASS_AREF AREF_CTRL: DEEPSLEEP_ON (Bit 30) */ +#define PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk (0x40000000UL) /*!< PASS_AREF AREF_CTRL: DEEPSLEEP_ON (Bitfield-Mask: 0x01) */ +#define PASS_AREF_AREF_CTRL_ENABLED_Pos (31UL) /*!< PASS_AREF AREF_CTRL: ENABLED (Bit 31) */ +#define PASS_AREF_AREF_CTRL_ENABLED_Msk (0x80000000UL) /*!< PASS_AREF AREF_CTRL: ENABLED (Bitfield-Mask: 0x01) */ + + +/* ==================================================== PASS.INTR_CAUSE ==================================================== */ +#define PASS_INTR_CAUSE_CTB0_INT_Pos (0UL) /*!< PASS INTR_CAUSE: CTB0_INT (Bit 0) */ +#define PASS_INTR_CAUSE_CTB0_INT_Msk (0x1UL) /*!< PASS INTR_CAUSE: CTB0_INT (Bitfield-Mask: 0x01) */ +#define PASS_INTR_CAUSE_CTB1_INT_Pos (1UL) /*!< PASS INTR_CAUSE: CTB1_INT (Bit 1) */ +#define PASS_INTR_CAUSE_CTB1_INT_Msk (0x2UL) /*!< PASS INTR_CAUSE: CTB1_INT (Bitfield-Mask: 0x01) */ +#define PASS_INTR_CAUSE_CTB2_INT_Pos (2UL) /*!< PASS INTR_CAUSE: CTB2_INT (Bit 2) */ +#define PASS_INTR_CAUSE_CTB2_INT_Msk (0x4UL) /*!< PASS INTR_CAUSE: CTB2_INT (Bitfield-Mask: 0x01) */ +#define PASS_INTR_CAUSE_CTB3_INT_Pos (3UL) /*!< PASS INTR_CAUSE: CTB3_INT (Bit 3) */ +#define PASS_INTR_CAUSE_CTB3_INT_Msk (0x8UL) /*!< PASS INTR_CAUSE: CTB3_INT (Bitfield-Mask: 0x01) */ +#define PASS_INTR_CAUSE_CTDAC0_INT_Pos (4UL) /*!< PASS INTR_CAUSE: CTDAC0_INT (Bit 4) */ +#define PASS_INTR_CAUSE_CTDAC0_INT_Msk (0x10UL) /*!< PASS INTR_CAUSE: CTDAC0_INT (Bitfield-Mask: 0x01) */ +#define PASS_INTR_CAUSE_CTDAC1_INT_Pos (5UL) /*!< PASS INTR_CAUSE: CTDAC1_INT (Bit 5) */ +#define PASS_INTR_CAUSE_CTDAC1_INT_Msk (0x20UL) /*!< PASS INTR_CAUSE: CTDAC1_INT (Bitfield-Mask: 0x01) */ +#define PASS_INTR_CAUSE_CTDAC2_INT_Pos (6UL) /*!< PASS INTR_CAUSE: CTDAC2_INT (Bit 6) */ +#define PASS_INTR_CAUSE_CTDAC2_INT_Msk (0x40UL) /*!< PASS INTR_CAUSE: CTDAC2_INT (Bitfield-Mask: 0x01) */ +#define PASS_INTR_CAUSE_CTDAC3_INT_Pos (7UL) /*!< PASS INTR_CAUSE: CTDAC3_INT (Bit 7) */ +#define PASS_INTR_CAUSE_CTDAC3_INT_Msk (0x80UL) /*!< PASS INTR_CAUSE: CTDAC3_INT (Bitfield-Mask: 0x01) */ +/* ==================================================== PASS.VREF_TRIM0 ==================================================== */ +#define PASS_VREF_TRIM0_VREF_ABS_TRIM_Pos (0UL) /*!< PASS VREF_TRIM0: VREF_ABS_TRIM (Bit 0) */ +#define PASS_VREF_TRIM0_VREF_ABS_TRIM_Msk (0xffUL) /*!< PASS VREF_TRIM0: VREF_ABS_TRIM (Bitfield-Mask: 0xff) */ +/* ==================================================== PASS.VREF_TRIM1 ==================================================== */ +#define PASS_VREF_TRIM1_VREF_TEMPCO_TRIM_Pos (0UL) /*!< PASS VREF_TRIM1: VREF_TEMPCO_TRIM (Bit 0) */ +#define PASS_VREF_TRIM1_VREF_TEMPCO_TRIM_Msk (0xffUL) /*!< PASS VREF_TRIM1: VREF_TEMPCO_TRIM (Bitfield-Mask: 0xff) */ +/* ==================================================== PASS.VREF_TRIM2 ==================================================== */ +#define PASS_VREF_TRIM2_VREF_CURV_TRIM_Pos (0UL) /*!< PASS VREF_TRIM2: VREF_CURV_TRIM (Bit 0) */ +#define PASS_VREF_TRIM2_VREF_CURV_TRIM_Msk (0xffUL) /*!< PASS VREF_TRIM2: VREF_CURV_TRIM (Bitfield-Mask: 0xff) */ +/* ==================================================== PASS.VREF_TRIM3 ==================================================== */ +#define PASS_VREF_TRIM3_VREF_ATTEN_TRIM_Pos (0UL) /*!< PASS VREF_TRIM3: VREF_ATTEN_TRIM (Bit 0) */ +#define PASS_VREF_TRIM3_VREF_ATTEN_TRIM_Msk (0xfUL) /*!< PASS VREF_TRIM3: VREF_ATTEN_TRIM (Bitfield-Mask: 0x0f) */ +/* =================================================== PASS.IZTAT_TRIM0 ==================================================== */ +#define PASS_IZTAT_TRIM0_IZTAT_ABS_TRIM_Pos (0UL) /*!< PASS IZTAT_TRIM0: IZTAT_ABS_TRIM (Bit 0) */ +#define PASS_IZTAT_TRIM0_IZTAT_ABS_TRIM_Msk (0xffUL) /*!< PASS IZTAT_TRIM0: IZTAT_ABS_TRIM (Bitfield-Mask: 0xff) */ +/* =================================================== PASS.IZTAT_TRIM1 ==================================================== */ +#define PASS_IZTAT_TRIM1_IZTAT_TC_TRIM_Pos (0UL) /*!< PASS IZTAT_TRIM1: IZTAT_TC_TRIM (Bit 0) */ +#define PASS_IZTAT_TRIM1_IZTAT_TC_TRIM_Msk (0xffUL) /*!< PASS IZTAT_TRIM1: IZTAT_TC_TRIM (Bitfield-Mask: 0xff) */ +/* =================================================== PASS.IPTAT_TRIM0 ==================================================== */ +#define PASS_IPTAT_TRIM0_IPTAT_CORE_TRIM_Pos (0UL) /*!< PASS IPTAT_TRIM0: IPTAT_CORE_TRIM (Bit 0) */ +#define PASS_IPTAT_TRIM0_IPTAT_CORE_TRIM_Msk (0xfUL) /*!< PASS IPTAT_TRIM0: IPTAT_CORE_TRIM (Bitfield-Mask: 0x0f) */ +#define PASS_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Pos (4UL) /*!< PASS IPTAT_TRIM0: IPTAT_CTBM_TRIM (Bit 4) */ +#define PASS_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Msk (0xf0UL) /*!< PASS IPTAT_TRIM0: IPTAT_CTBM_TRIM (Bitfield-Mask: 0x0f) */ +/* =================================================== PASS.ICTAT_TRIM0 ==================================================== */ +#define PASS_ICTAT_TRIM0_ICTAT_TRIM_Pos (0UL) /*!< PASS ICTAT_TRIM0: ICTAT_TRIM (Bit 0) */ +#define PASS_ICTAT_TRIM0_ICTAT_TRIM_Msk (0xfUL) /*!< PASS ICTAT_TRIM0: ICTAT_TRIM (Bitfield-Mask: 0x0f) */ + + +#endif /* _CYIP_PASS_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_pdm.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_pdm.h new file mode 100644 index 0000000000..0bff6de5ca --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_pdm.h @@ -0,0 +1,169 @@ +/***************************************************************************//** +* \file cyip_pdm.h +* +* \brief +* PDM IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_PDM_H_ +#define _CYIP_PDM_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + +#define PDM_SECTION_SIZE 0x00001000UL + +/** + * \brief PDM registers (PDM) + */ +typedef struct { /*!< PDM Structure */ + __IOM uint32_t CTL; /*!< 0x00000000 Control */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */ + __IOM uint32_t MODE_CTL; /*!< 0x00000014 Mode control */ + __IOM uint32_t DATA_CTL; /*!< 0x00000018 Data control */ + __IM uint32_t RESERVED1; + __IOM uint32_t CMD; /*!< 0x00000020 Command */ + __IM uint32_t RESERVED2[7]; + __IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */ + __IM uint32_t RESERVED3[175]; + __IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */ + __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */ + __IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */ + __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */ + __IM uint32_t RESERVED4[764]; + __IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */ + __IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */ +} PDM_Type; /*!< Size = 3856 (0xF10) */ + + +/* ======================================================== PDM.CTL ======================================================== */ +#define PDM_CTL_PGA_R_Pos (0UL) /*!< PDM CTL: PGA_R (Bit 0) */ +#define PDM_CTL_PGA_R_Msk (0xfUL) /*!< PDM CTL: PGA_R (Bitfield-Mask: 0x0f) */ +#define PDM_CTL_PGA_L_Pos (8UL) /*!< PDM CTL: PGA_L (Bit 8) */ +#define PDM_CTL_PGA_L_Msk (0xf00UL) /*!< PDM CTL: PGA_L (Bitfield-Mask: 0x0f) */ +#define PDM_CTL_SOFT_MUTE_Pos (16UL) /*!< PDM CTL: SOFT_MUTE (Bit 16) */ +#define PDM_CTL_SOFT_MUTE_Msk (0x10000UL) /*!< PDM CTL: SOFT_MUTE (Bitfield-Mask: 0x01) */ +#define PDM_CTL_STEP_SEL_Pos (17UL) /*!< PDM CTL: STEP_SEL (Bit 17) */ +#define PDM_CTL_STEP_SEL_Msk (0x20000UL) /*!< PDM CTL: STEP_SEL (Bitfield-Mask: 0x01) */ +#define PDM_CTL_ENABLED_Pos (31UL) /*!< PDM CTL: ENABLED (Bit 31) */ +#define PDM_CTL_ENABLED_Msk (0x80000000UL) /*!< PDM CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ===================================================== PDM.CLOCK_CTL ===================================================== */ +#define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Pos (0UL) /*!< PDM CLOCK_CTL: CLK_CLOCK_DIV (Bit 0) */ +#define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Msk (0x3UL) /*!< PDM CLOCK_CTL: CLK_CLOCK_DIV (Bitfield-Mask: 0x03) */ +#define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Pos (4UL) /*!< PDM CLOCK_CTL: MCLKQ_CLOCK_DIV (Bit 4) */ +#define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Msk (0x30UL) /*!< PDM CLOCK_CTL: MCLKQ_CLOCK_DIV (Bitfield-Mask: 0x03) */ +#define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Pos (8UL) /*!< PDM CLOCK_CTL: CKO_CLOCK_DIV (Bit 8) */ +#define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Msk (0xf00UL) /*!< PDM CLOCK_CTL: CKO_CLOCK_DIV (Bitfield-Mask: 0x0f) */ +#define PDM_CLOCK_CTL_SINC_RATE_Pos (16UL) /*!< PDM CLOCK_CTL: SINC_RATE (Bit 16) */ +#define PDM_CLOCK_CTL_SINC_RATE_Msk (0x7f0000UL) /*!< PDM CLOCK_CTL: SINC_RATE (Bitfield-Mask: 0x7f) */ +/* ===================================================== PDM.MODE_CTL ====================================================== */ +#define PDM_MODE_CTL_PCM_CH_SET_Pos (0UL) /*!< PDM MODE_CTL: PCM_CH_SET (Bit 0) */ +#define PDM_MODE_CTL_PCM_CH_SET_Msk (0x3UL) /*!< PDM MODE_CTL: PCM_CH_SET (Bitfield-Mask: 0x03) */ +#define PDM_MODE_CTL_SWAP_LR_Pos (2UL) /*!< PDM MODE_CTL: SWAP_LR (Bit 2) */ +#define PDM_MODE_CTL_SWAP_LR_Msk (0x4UL) /*!< PDM MODE_CTL: SWAP_LR (Bitfield-Mask: 0x01) */ +#define PDM_MODE_CTL_S_CYCLES_Pos (8UL) /*!< PDM MODE_CTL: S_CYCLES (Bit 8) */ +#define PDM_MODE_CTL_S_CYCLES_Msk (0x700UL) /*!< PDM MODE_CTL: S_CYCLES (Bitfield-Mask: 0x07) */ +#define PDM_MODE_CTL_CKO_DELAY_Pos (16UL) /*!< PDM MODE_CTL: CKO_DELAY (Bit 16) */ +#define PDM_MODE_CTL_CKO_DELAY_Msk (0x70000UL) /*!< PDM MODE_CTL: CKO_DELAY (Bitfield-Mask: 0x07) */ +#define PDM_MODE_CTL_HPF_GAIN_Pos (24UL) /*!< PDM MODE_CTL: HPF_GAIN (Bit 24) */ +#define PDM_MODE_CTL_HPF_GAIN_Msk (0xf000000UL) /*!< PDM MODE_CTL: HPF_GAIN (Bitfield-Mask: 0x0f) */ +#define PDM_MODE_CTL_HPF_EN_N_Pos (28UL) /*!< PDM MODE_CTL: HPF_EN_N (Bit 28) */ +#define PDM_MODE_CTL_HPF_EN_N_Msk (0x10000000UL) /*!< PDM MODE_CTL: HPF_EN_N (Bitfield-Mask: 0x01) */ +/* ===================================================== PDM.DATA_CTL ====================================================== */ +#define PDM_DATA_CTL_WORD_LEN_Pos (0UL) /*!< PDM DATA_CTL: WORD_LEN (Bit 0) */ +#define PDM_DATA_CTL_WORD_LEN_Msk (0x3UL) /*!< PDM DATA_CTL: WORD_LEN (Bitfield-Mask: 0x03) */ +#define PDM_DATA_CTL_BIT_EXTENSION_Pos (8UL) /*!< PDM DATA_CTL: BIT_EXTENSION (Bit 8) */ +#define PDM_DATA_CTL_BIT_EXTENSION_Msk (0x100UL) /*!< PDM DATA_CTL: BIT_EXTENSION (Bitfield-Mask: 0x01) */ +/* ======================================================== PDM.CMD ======================================================== */ +#define PDM_CMD_STREAM_EN_Pos (0UL) /*!< PDM CMD: STREAM_EN (Bit 0) */ +#define PDM_CMD_STREAM_EN_Msk (0x1UL) /*!< PDM CMD: STREAM_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== PDM.TR_CTL ======================================================= */ +#define PDM_TR_CTL_RX_REQ_EN_Pos (16UL) /*!< PDM TR_CTL: RX_REQ_EN (Bit 16) */ +#define PDM_TR_CTL_RX_REQ_EN_Msk (0x10000UL) /*!< PDM TR_CTL: RX_REQ_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== PDM.RX_FIFO_CTL ==================================================== */ +#define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Pos (0UL) /*!< PDM RX_FIFO_CTL: TRIGGER_LEVEL (Bit 0) */ +#define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Msk (0xffUL) /*!< PDM RX_FIFO_CTL: TRIGGER_LEVEL (Bitfield-Mask: 0xff) */ +#define PDM_RX_FIFO_CTL_CLEAR_Pos (16UL) /*!< PDM RX_FIFO_CTL: CLEAR (Bit 16) */ +#define PDM_RX_FIFO_CTL_CLEAR_Msk (0x10000UL) /*!< PDM RX_FIFO_CTL: CLEAR (Bitfield-Mask: 0x01) */ +#define PDM_RX_FIFO_CTL_FREEZE_Pos (17UL) /*!< PDM RX_FIFO_CTL: FREEZE (Bit 17) */ +#define PDM_RX_FIFO_CTL_FREEZE_Msk (0x20000UL) /*!< PDM RX_FIFO_CTL: FREEZE (Bitfield-Mask: 0x01) */ +/* ================================================== PDM.RX_FIFO_STATUS =================================================== */ +#define PDM_RX_FIFO_STATUS_USED_Pos (0UL) /*!< PDM RX_FIFO_STATUS: USED (Bit 0) */ +#define PDM_RX_FIFO_STATUS_USED_Msk (0x1ffUL) /*!< PDM RX_FIFO_STATUS: USED (Bitfield-Mask: 0x1ff) */ +#define PDM_RX_FIFO_STATUS_RD_PTR_Pos (16UL) /*!< PDM RX_FIFO_STATUS: RD_PTR (Bit 16) */ +#define PDM_RX_FIFO_STATUS_RD_PTR_Msk (0xff0000UL) /*!< PDM RX_FIFO_STATUS: RD_PTR (Bitfield-Mask: 0xff) */ +#define PDM_RX_FIFO_STATUS_WR_PTR_Pos (24UL) /*!< PDM RX_FIFO_STATUS: WR_PTR (Bit 24) */ +#define PDM_RX_FIFO_STATUS_WR_PTR_Msk (0xff000000UL) /*!< PDM RX_FIFO_STATUS: WR_PTR (Bitfield-Mask: 0xff) */ +/* ==================================================== PDM.RX_FIFO_RD ===================================================== */ +#define PDM_RX_FIFO_RD_DATA_Pos (0UL) /*!< PDM RX_FIFO_RD: DATA (Bit 0) */ +#define PDM_RX_FIFO_RD_DATA_Msk (0xffffffffUL) /*!< PDM RX_FIFO_RD: DATA (Bitfield-Mask: 0xffffffff) */ +/* ================================================= PDM.RX_FIFO_RD_SILENT ================================================= */ +#define PDM_RX_FIFO_RD_SILENT_DATA_Pos (0UL) /*!< PDM RX_FIFO_RD_SILENT: DATA (Bit 0) */ +#define PDM_RX_FIFO_RD_SILENT_DATA_Msk (0xffffffffUL) /*!< PDM RX_FIFO_RD_SILENT: DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PDM.INTR ======================================================== */ +#define PDM_INTR_RX_TRIGGER_Pos (16UL) /*!< PDM INTR: RX_TRIGGER (Bit 16) */ +#define PDM_INTR_RX_TRIGGER_Msk (0x10000UL) /*!< PDM INTR: RX_TRIGGER (Bitfield-Mask: 0x01) */ +#define PDM_INTR_RX_NOT_EMPTY_Pos (18UL) /*!< PDM INTR: RX_NOT_EMPTY (Bit 18) */ +#define PDM_INTR_RX_NOT_EMPTY_Msk (0x40000UL) /*!< PDM INTR: RX_NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define PDM_INTR_RX_FULL_Pos (19UL) /*!< PDM INTR: RX_FULL (Bit 19) */ +#define PDM_INTR_RX_FULL_Msk (0x80000UL) /*!< PDM INTR: RX_FULL (Bitfield-Mask: 0x01) */ +#define PDM_INTR_RX_OVERFLOW_Pos (21UL) /*!< PDM INTR: RX_OVERFLOW (Bit 21) */ +#define PDM_INTR_RX_OVERFLOW_Msk (0x200000UL) /*!< PDM INTR: RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define PDM_INTR_RX_UNDERFLOW_Pos (22UL) /*!< PDM INTR: RX_UNDERFLOW (Bit 22) */ +#define PDM_INTR_RX_UNDERFLOW_Msk (0x400000UL) /*!< PDM INTR: RX_UNDERFLOW (Bitfield-Mask: 0x01) */ +/* ===================================================== PDM.INTR_SET ====================================================== */ +#define PDM_INTR_SET_RX_TRIGGER_Pos (16UL) /*!< PDM INTR_SET: RX_TRIGGER (Bit 16) */ +#define PDM_INTR_SET_RX_TRIGGER_Msk (0x10000UL) /*!< PDM INTR_SET: RX_TRIGGER (Bitfield-Mask: 0x01) */ +#define PDM_INTR_SET_RX_NOT_EMPTY_Pos (18UL) /*!< PDM INTR_SET: RX_NOT_EMPTY (Bit 18) */ +#define PDM_INTR_SET_RX_NOT_EMPTY_Msk (0x40000UL) /*!< PDM INTR_SET: RX_NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define PDM_INTR_SET_RX_FULL_Pos (19UL) /*!< PDM INTR_SET: RX_FULL (Bit 19) */ +#define PDM_INTR_SET_RX_FULL_Msk (0x80000UL) /*!< PDM INTR_SET: RX_FULL (Bitfield-Mask: 0x01) */ +#define PDM_INTR_SET_RX_OVERFLOW_Pos (21UL) /*!< PDM INTR_SET: RX_OVERFLOW (Bit 21) */ +#define PDM_INTR_SET_RX_OVERFLOW_Msk (0x200000UL) /*!< PDM INTR_SET: RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define PDM_INTR_SET_RX_UNDERFLOW_Pos (22UL) /*!< PDM INTR_SET: RX_UNDERFLOW (Bit 22) */ +#define PDM_INTR_SET_RX_UNDERFLOW_Msk (0x400000UL) /*!< PDM INTR_SET: RX_UNDERFLOW (Bitfield-Mask: 0x01) */ +/* ===================================================== PDM.INTR_MASK ===================================================== */ +#define PDM_INTR_MASK_RX_TRIGGER_Pos (16UL) /*!< PDM INTR_MASK: RX_TRIGGER (Bit 16) */ +#define PDM_INTR_MASK_RX_TRIGGER_Msk (0x10000UL) /*!< PDM INTR_MASK: RX_TRIGGER (Bitfield-Mask: 0x01) */ +#define PDM_INTR_MASK_RX_NOT_EMPTY_Pos (18UL) /*!< PDM INTR_MASK: RX_NOT_EMPTY (Bit 18) */ +#define PDM_INTR_MASK_RX_NOT_EMPTY_Msk (0x40000UL) /*!< PDM INTR_MASK: RX_NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define PDM_INTR_MASK_RX_FULL_Pos (19UL) /*!< PDM INTR_MASK: RX_FULL (Bit 19) */ +#define PDM_INTR_MASK_RX_FULL_Msk (0x80000UL) /*!< PDM INTR_MASK: RX_FULL (Bitfield-Mask: 0x01) */ +#define PDM_INTR_MASK_RX_OVERFLOW_Pos (21UL) /*!< PDM INTR_MASK: RX_OVERFLOW (Bit 21) */ +#define PDM_INTR_MASK_RX_OVERFLOW_Msk (0x200000UL) /*!< PDM INTR_MASK: RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define PDM_INTR_MASK_RX_UNDERFLOW_Pos (22UL) /*!< PDM INTR_MASK: RX_UNDERFLOW (Bit 22) */ +#define PDM_INTR_MASK_RX_UNDERFLOW_Msk (0x400000UL) /*!< PDM INTR_MASK: RX_UNDERFLOW (Bitfield-Mask: 0x01) */ +/* ==================================================== PDM.INTR_MASKED ==================================================== */ +#define PDM_INTR_MASKED_RX_TRIGGER_Pos (16UL) /*!< PDM INTR_MASKED: RX_TRIGGER (Bit 16) */ +#define PDM_INTR_MASKED_RX_TRIGGER_Msk (0x10000UL) /*!< PDM INTR_MASKED: RX_TRIGGER (Bitfield-Mask: 0x01) */ +#define PDM_INTR_MASKED_RX_NOT_EMPTY_Pos (18UL) /*!< PDM INTR_MASKED: RX_NOT_EMPTY (Bit 18) */ +#define PDM_INTR_MASKED_RX_NOT_EMPTY_Msk (0x40000UL) /*!< PDM INTR_MASKED: RX_NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define PDM_INTR_MASKED_RX_FULL_Pos (19UL) /*!< PDM INTR_MASKED: RX_FULL (Bit 19) */ +#define PDM_INTR_MASKED_RX_FULL_Msk (0x80000UL) /*!< PDM INTR_MASKED: RX_FULL (Bitfield-Mask: 0x01) */ +#define PDM_INTR_MASKED_RX_OVERFLOW_Pos (21UL) /*!< PDM INTR_MASKED: RX_OVERFLOW (Bit 21) */ +#define PDM_INTR_MASKED_RX_OVERFLOW_Msk (0x200000UL) /*!< PDM INTR_MASKED: RX_OVERFLOW (Bitfield-Mask: 0x01) */ +#define PDM_INTR_MASKED_RX_UNDERFLOW_Pos (22UL) /*!< PDM INTR_MASKED: RX_UNDERFLOW (Bit 22) */ +#define PDM_INTR_MASKED_RX_UNDERFLOW_Msk (0x400000UL) /*!< PDM INTR_MASKED: RX_UNDERFLOW (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_PDM_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_peri.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_peri.h new file mode 100644 index 0000000000..67ac5c35eb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_peri.h @@ -0,0 +1,482 @@ +/***************************************************************************//** +* \file cyip_peri.h +* +* \brief +* PERI IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_PERI_H_ +#define _CYIP_PERI_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ PERI ================ */ +/* =========================================================================================================================== */ + +#define PERI_GR_SECTION_SIZE 0x00000040UL +#define PERI_TR_GR_SECTION_SIZE 0x00000200UL +#define PERI_PPU_PR_SECTION_SIZE 0x00000040UL +#define PERI_PPU_GR_SECTION_SIZE 0x00000040UL +#define PERI_GR_PPU_SL_SECTION_SIZE 0x00000040UL +#define PERI_GR_PPU_RG_SECTION_SIZE 0x00000040UL +#define PERI_SECTION_SIZE 0x00010000UL + +/** + * \brief Peripheral group structure (PERI_GR) + */ +typedef struct { + __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */ + __IM uint32_t RESERVED[7]; + __IOM uint32_t SL_CTL; /*!< 0x00000020 Slave control */ + __IOM uint32_t TIMEOUT_CTL; /*!< 0x00000024 Timeout control */ + __IM uint32_t RESERVED1[6]; +} PERI_GR_Type; /*!< Size = 40 (0x28) */ + +/** + * \brief Trigger group (PERI_TR_GR) + */ +typedef struct { + __IOM uint32_t TR_OUT_CTL[128]; /*!< 0x00000000 Trigger control register */ +} PERI_TR_GR_Type; /*!< Size = 512 (0x200) */ + +/** + * \brief PPU structure with programmable address (PERI_PPU_PR) + */ +typedef struct { + __IOM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ + __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ + __IM uint32_t RESERVED[6]; + __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ + __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ + __IM uint32_t RESERVED1[6]; +} PERI_PPU_PR_Type; /*!< Size = 40 (0x28) */ + +/** + * \brief PPU structure with fixed/constant address for a peripheral group (PERI_PPU_GR) + */ +typedef struct { + __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ + __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ + __IM uint32_t RESERVED[6]; + __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ + __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ + __IM uint32_t RESERVED1[6]; +} PERI_PPU_GR_Type; /*!< Size = 40 (0x28) */ + +/** + * \brief PPU structure with fixed/constant address for a specific slave (PERI_GR_PPU_SL) + */ +typedef struct { + __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ + __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ + __IM uint32_t RESERVED[6]; + __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ + __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ + __IM uint32_t RESERVED1[6]; +} PERI_GR_PPU_SL_Type; /*!< Size = 40 (0x28) */ + +/** + * \brief PPU structure with fixed/constant address for a specific region (PERI_GR_PPU_RG) + */ +typedef struct { + __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ + __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ + __IM uint32_t RESERVED[6]; + __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ + __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ + __IM uint32_t RESERVED1[6]; +} PERI_GR_PPU_RG_Type; /*!< Size = 40 (0x28) */ + +/** + * \brief Peripheral interconnect (PERI) + */ +typedef struct { /*!< PERI Structure */ + PERI_GR_Type GR[16]; /*!< 0x00000000 Peripheral group structure */ + __IOM uint32_t DIV_CMD; /*!< 0x00000400 Divider command register */ + __IM uint32_t RESERVED[255]; + __IOM uint32_t DIV_8_CTL[64]; /*!< 0x00000800 Divider control register (for 8.0 divider) */ + __IOM uint32_t DIV_16_CTL[64]; /*!< 0x00000900 Divider control register (for 16.0 divider) */ + __IOM uint32_t DIV_16_5_CTL[64]; /*!< 0x00000A00 Divider control register (for 16.5 divider) */ + __IOM uint32_t DIV_24_5_CTL[63]; /*!< 0x00000B00 Divider control register (for 24.5 divider) */ + __IM uint32_t RESERVED1; + __IOM uint32_t CLOCK_CTL[128]; /*!< 0x00000C00 Clock control register */ + __IM uint32_t RESERVED2[128]; + __IOM uint32_t TR_CMD; /*!< 0x00001000 Trigger command register */ + __IM uint32_t RESERVED3[1023]; + PERI_TR_GR_Type TR_GR[16]; /*!< 0x00002000 Trigger group */ + PERI_PPU_PR_Type PPU_PR[32]; /*!< 0x00004000 PPU structure with programmable address */ + __IM uint32_t RESERVED4[512]; + PERI_PPU_GR_Type PPU_GR[16]; /*!< 0x00005000 PPU structure with fixed/constant address for a peripheral + group */ +} PERI_Type; /*!< Size = 21504 (0x5400) */ + + +/* =================================================== PERI_GR.CLOCK_CTL =================================================== */ +#define PERI_GR_CLOCK_CTL_INT8_DIV_Pos (8UL) /*!< PERI_GR CLOCK_CTL: INT8_DIV (Bit 8) */ +#define PERI_GR_CLOCK_CTL_INT8_DIV_Msk (0xff00UL) /*!< PERI_GR CLOCK_CTL: INT8_DIV (Bitfield-Mask: 0xff) */ +/* ==================================================== PERI_GR.SL_CTL ===================================================== */ +#define PERI_GR_SL_CTL_ENABLED_0_Pos (0UL) /*!< PERI_GR SL_CTL: ENABLED_0 (Bit 0) */ +#define PERI_GR_SL_CTL_ENABLED_0_Msk (0x1UL) /*!< PERI_GR SL_CTL: ENABLED_0 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_1_Pos (1UL) /*!< PERI_GR SL_CTL: ENABLED_1 (Bit 1) */ +#define PERI_GR_SL_CTL_ENABLED_1_Msk (0x2UL) /*!< PERI_GR SL_CTL: ENABLED_1 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_2_Pos (2UL) /*!< PERI_GR SL_CTL: ENABLED_2 (Bit 2) */ +#define PERI_GR_SL_CTL_ENABLED_2_Msk (0x4UL) /*!< PERI_GR SL_CTL: ENABLED_2 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_3_Pos (3UL) /*!< PERI_GR SL_CTL: ENABLED_3 (Bit 3) */ +#define PERI_GR_SL_CTL_ENABLED_3_Msk (0x8UL) /*!< PERI_GR SL_CTL: ENABLED_3 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_4_Pos (4UL) /*!< PERI_GR SL_CTL: ENABLED_4 (Bit 4) */ +#define PERI_GR_SL_CTL_ENABLED_4_Msk (0x10UL) /*!< PERI_GR SL_CTL: ENABLED_4 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_5_Pos (5UL) /*!< PERI_GR SL_CTL: ENABLED_5 (Bit 5) */ +#define PERI_GR_SL_CTL_ENABLED_5_Msk (0x20UL) /*!< PERI_GR SL_CTL: ENABLED_5 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_6_Pos (6UL) /*!< PERI_GR SL_CTL: ENABLED_6 (Bit 6) */ +#define PERI_GR_SL_CTL_ENABLED_6_Msk (0x40UL) /*!< PERI_GR SL_CTL: ENABLED_6 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_7_Pos (7UL) /*!< PERI_GR SL_CTL: ENABLED_7 (Bit 7) */ +#define PERI_GR_SL_CTL_ENABLED_7_Msk (0x80UL) /*!< PERI_GR SL_CTL: ENABLED_7 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_8_Pos (8UL) /*!< PERI_GR SL_CTL: ENABLED_8 (Bit 8) */ +#define PERI_GR_SL_CTL_ENABLED_8_Msk (0x100UL) /*!< PERI_GR SL_CTL: ENABLED_8 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_9_Pos (9UL) /*!< PERI_GR SL_CTL: ENABLED_9 (Bit 9) */ +#define PERI_GR_SL_CTL_ENABLED_9_Msk (0x200UL) /*!< PERI_GR SL_CTL: ENABLED_9 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_10_Pos (10UL) /*!< PERI_GR SL_CTL: ENABLED_10 (Bit 10) */ +#define PERI_GR_SL_CTL_ENABLED_10_Msk (0x400UL) /*!< PERI_GR SL_CTL: ENABLED_10 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_11_Pos (11UL) /*!< PERI_GR SL_CTL: ENABLED_11 (Bit 11) */ +#define PERI_GR_SL_CTL_ENABLED_11_Msk (0x800UL) /*!< PERI_GR SL_CTL: ENABLED_11 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_12_Pos (12UL) /*!< PERI_GR SL_CTL: ENABLED_12 (Bit 12) */ +#define PERI_GR_SL_CTL_ENABLED_12_Msk (0x1000UL) /*!< PERI_GR SL_CTL: ENABLED_12 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_13_Pos (13UL) /*!< PERI_GR SL_CTL: ENABLED_13 (Bit 13) */ +#define PERI_GR_SL_CTL_ENABLED_13_Msk (0x2000UL) /*!< PERI_GR SL_CTL: ENABLED_13 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_14_Pos (14UL) /*!< PERI_GR SL_CTL: ENABLED_14 (Bit 14) */ +#define PERI_GR_SL_CTL_ENABLED_14_Msk (0x4000UL) /*!< PERI_GR SL_CTL: ENABLED_14 (Bitfield-Mask: 0x01) */ +#define PERI_GR_SL_CTL_ENABLED_15_Pos (15UL) /*!< PERI_GR SL_CTL: ENABLED_15 (Bit 15) */ +#define PERI_GR_SL_CTL_ENABLED_15_Msk (0x8000UL) /*!< PERI_GR SL_CTL: ENABLED_15 (Bitfield-Mask: 0x01) */ +/* ================================================== PERI_GR.TIMEOUT_CTL ================================================== */ +#define PERI_GR_TIMEOUT_CTL_TIMEOUT_Pos (0UL) /*!< PERI_GR TIMEOUT_CTL: TIMEOUT (Bit 0) */ +#define PERI_GR_TIMEOUT_CTL_TIMEOUT_Msk (0xffffUL) /*!< PERI_GR TIMEOUT_CTL: TIMEOUT (Bitfield-Mask: 0xffff) */ + + +/* ================================================= PERI_TR_GR.TR_OUT_CTL ================================================= */ +#define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos (0UL) /*!< PERI_TR_GR TR_OUT_CTL: TR_SEL (Bit 0) */ +#define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk (0x7fUL) /*!< PERI_TR_GR TR_OUT_CTL: TR_SEL (Bitfield-Mask: 0x7f) */ +#define PERI_TR_GR_TR_OUT_CTL_TR_INV_Pos (8UL) /*!< PERI_TR_GR TR_OUT_CTL: TR_INV (Bit 8) */ +#define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk (0x100UL) /*!< PERI_TR_GR TR_OUT_CTL: TR_INV (Bitfield-Mask: 0x01) */ +#define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos (9UL) /*!< PERI_TR_GR TR_OUT_CTL: TR_EDGE (Bit 9) */ +#define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk (0x200UL) /*!< PERI_TR_GR TR_OUT_CTL: TR_EDGE (Bitfield-Mask: 0x01) */ + + +/* =================================================== PERI_PPU_PR.ADDR0 =================================================== */ +#define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Pos (0UL) /*!< PERI_PPU_PR ADDR0: SUBREGION_DISABLE (Bit 0) */ +#define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Msk (0xffUL) /*!< PERI_PPU_PR ADDR0: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PERI_PPU_PR_ADDR0_ADDR24_Pos (8UL) /*!< PERI_PPU_PR ADDR0: ADDR24 (Bit 8) */ +#define PERI_PPU_PR_ADDR0_ADDR24_Msk (0xffffff00UL) /*!< PERI_PPU_PR ADDR0: ADDR24 (Bitfield-Mask: 0xffffff) */ +/* =================================================== PERI_PPU_PR.ATT0 ==================================================== */ +#define PERI_PPU_PR_ATT0_UR_Pos (0UL) /*!< PERI_PPU_PR ATT0: UR (Bit 0) */ +#define PERI_PPU_PR_ATT0_UR_Msk (0x1UL) /*!< PERI_PPU_PR ATT0: UR (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT0_UW_Pos (1UL) /*!< PERI_PPU_PR ATT0: UW (Bit 1) */ +#define PERI_PPU_PR_ATT0_UW_Msk (0x2UL) /*!< PERI_PPU_PR ATT0: UW (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT0_UX_Pos (2UL) /*!< PERI_PPU_PR ATT0: UX (Bit 2) */ +#define PERI_PPU_PR_ATT0_UX_Msk (0x4UL) /*!< PERI_PPU_PR ATT0: UX (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT0_PR_Pos (3UL) /*!< PERI_PPU_PR ATT0: PR (Bit 3) */ +#define PERI_PPU_PR_ATT0_PR_Msk (0x8UL) /*!< PERI_PPU_PR ATT0: PR (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT0_PW_Pos (4UL) /*!< PERI_PPU_PR ATT0: PW (Bit 4) */ +#define PERI_PPU_PR_ATT0_PW_Msk (0x10UL) /*!< PERI_PPU_PR ATT0: PW (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT0_PX_Pos (5UL) /*!< PERI_PPU_PR ATT0: PX (Bit 5) */ +#define PERI_PPU_PR_ATT0_PX_Msk (0x20UL) /*!< PERI_PPU_PR ATT0: PX (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT0_NS_Pos (6UL) /*!< PERI_PPU_PR ATT0: NS (Bit 6) */ +#define PERI_PPU_PR_ATT0_NS_Msk (0x40UL) /*!< PERI_PPU_PR ATT0: NS (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT0_PC_MASK_0_Pos (8UL) /*!< PERI_PPU_PR ATT0: PC_MASK_0 (Bit 8) */ +#define PERI_PPU_PR_ATT0_PC_MASK_0_Msk (0x100UL) /*!< PERI_PPU_PR ATT0: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Pos (9UL) /*!< PERI_PPU_PR ATT0: PC_MASK_15_TO_1 (Bit 9) */ +#define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Msk (0xfffe00UL) /*!< PERI_PPU_PR ATT0: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff) */ +#define PERI_PPU_PR_ATT0_REGION_SIZE_Pos (24UL) /*!< PERI_PPU_PR ATT0: REGION_SIZE (Bit 24) */ +#define PERI_PPU_PR_ATT0_REGION_SIZE_Msk (0x1f000000UL) /*!< PERI_PPU_PR ATT0: REGION_SIZE (Bitfield-Mask: 0x1f) */ +#define PERI_PPU_PR_ATT0_PC_MATCH_Pos (30UL) /*!< PERI_PPU_PR ATT0: PC_MATCH (Bit 30) */ +#define PERI_PPU_PR_ATT0_PC_MATCH_Msk (0x40000000UL) /*!< PERI_PPU_PR ATT0: PC_MATCH (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT0_ENABLED_Pos (31UL) /*!< PERI_PPU_PR ATT0: ENABLED (Bit 31) */ +#define PERI_PPU_PR_ATT0_ENABLED_Msk (0x80000000UL) /*!< PERI_PPU_PR ATT0: ENABLED (Bitfield-Mask: 0x01) */ +/* =================================================== PERI_PPU_PR.ADDR1 =================================================== */ +#define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Pos (0UL) /*!< PERI_PPU_PR ADDR1: SUBREGION_DISABLE (Bit 0) */ +#define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Msk (0xffUL) /*!< PERI_PPU_PR ADDR1: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PERI_PPU_PR_ADDR1_ADDR24_Pos (8UL) /*!< PERI_PPU_PR ADDR1: ADDR24 (Bit 8) */ +#define PERI_PPU_PR_ADDR1_ADDR24_Msk (0xffffff00UL) /*!< PERI_PPU_PR ADDR1: ADDR24 (Bitfield-Mask: 0xffffff) */ +/* =================================================== PERI_PPU_PR.ATT1 ==================================================== */ +#define PERI_PPU_PR_ATT1_UR_Pos (0UL) /*!< PERI_PPU_PR ATT1: UR (Bit 0) */ +#define PERI_PPU_PR_ATT1_UR_Msk (0x1UL) /*!< PERI_PPU_PR ATT1: UR (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT1_UW_Pos (1UL) /*!< PERI_PPU_PR ATT1: UW (Bit 1) */ +#define PERI_PPU_PR_ATT1_UW_Msk (0x2UL) /*!< PERI_PPU_PR ATT1: UW (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT1_UX_Pos (2UL) /*!< PERI_PPU_PR ATT1: UX (Bit 2) */ +#define PERI_PPU_PR_ATT1_UX_Msk (0x4UL) /*!< PERI_PPU_PR ATT1: UX (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT1_PR_Pos (3UL) /*!< PERI_PPU_PR ATT1: PR (Bit 3) */ +#define PERI_PPU_PR_ATT1_PR_Msk (0x8UL) /*!< PERI_PPU_PR ATT1: PR (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT1_PW_Pos (4UL) /*!< PERI_PPU_PR ATT1: PW (Bit 4) */ +#define PERI_PPU_PR_ATT1_PW_Msk (0x10UL) /*!< PERI_PPU_PR ATT1: PW (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT1_PX_Pos (5UL) /*!< PERI_PPU_PR ATT1: PX (Bit 5) */ +#define PERI_PPU_PR_ATT1_PX_Msk (0x20UL) /*!< PERI_PPU_PR ATT1: PX (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT1_NS_Pos (6UL) /*!< PERI_PPU_PR ATT1: NS (Bit 6) */ +#define PERI_PPU_PR_ATT1_NS_Msk (0x40UL) /*!< PERI_PPU_PR ATT1: NS (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT1_PC_MASK_0_Pos (8UL) /*!< PERI_PPU_PR ATT1: PC_MASK_0 (Bit 8) */ +#define PERI_PPU_PR_ATT1_PC_MASK_0_Msk (0x100UL) /*!< PERI_PPU_PR ATT1: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Pos (9UL) /*!< PERI_PPU_PR ATT1: PC_MASK_15_TO_1 (Bit 9) */ +#define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Msk (0xfffe00UL) /*!< PERI_PPU_PR ATT1: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff) */ +#define PERI_PPU_PR_ATT1_REGION_SIZE_Pos (24UL) /*!< PERI_PPU_PR ATT1: REGION_SIZE (Bit 24) */ +#define PERI_PPU_PR_ATT1_REGION_SIZE_Msk (0x1f000000UL) /*!< PERI_PPU_PR ATT1: REGION_SIZE (Bitfield-Mask: 0x1f) */ +#define PERI_PPU_PR_ATT1_PC_MATCH_Pos (30UL) /*!< PERI_PPU_PR ATT1: PC_MATCH (Bit 30) */ +#define PERI_PPU_PR_ATT1_PC_MATCH_Msk (0x40000000UL) /*!< PERI_PPU_PR ATT1: PC_MATCH (Bitfield-Mask: 0x01) */ +#define PERI_PPU_PR_ATT1_ENABLED_Pos (31UL) /*!< PERI_PPU_PR ATT1: ENABLED (Bit 31) */ +#define PERI_PPU_PR_ATT1_ENABLED_Msk (0x80000000UL) /*!< PERI_PPU_PR ATT1: ENABLED (Bitfield-Mask: 0x01) */ + + +/* =================================================== PERI_PPU_GR.ADDR0 =================================================== */ +#define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Pos (0UL) /*!< PERI_PPU_GR ADDR0: SUBREGION_DISABLE (Bit 0) */ +#define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Msk (0xffUL) /*!< PERI_PPU_GR ADDR0: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PERI_PPU_GR_ADDR0_ADDR24_Pos (8UL) /*!< PERI_PPU_GR ADDR0: ADDR24 (Bit 8) */ +#define PERI_PPU_GR_ADDR0_ADDR24_Msk (0xffffff00UL) /*!< PERI_PPU_GR ADDR0: ADDR24 (Bitfield-Mask: 0xffffff) */ +/* =================================================== PERI_PPU_GR.ATT0 ==================================================== */ +#define PERI_PPU_GR_ATT0_UR_Pos (0UL) /*!< PERI_PPU_GR ATT0: UR (Bit 0) */ +#define PERI_PPU_GR_ATT0_UR_Msk (0x1UL) /*!< PERI_PPU_GR ATT0: UR (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT0_UW_Pos (1UL) /*!< PERI_PPU_GR ATT0: UW (Bit 1) */ +#define PERI_PPU_GR_ATT0_UW_Msk (0x2UL) /*!< PERI_PPU_GR ATT0: UW (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT0_UX_Pos (2UL) /*!< PERI_PPU_GR ATT0: UX (Bit 2) */ +#define PERI_PPU_GR_ATT0_UX_Msk (0x4UL) /*!< PERI_PPU_GR ATT0: UX (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT0_PR_Pos (3UL) /*!< PERI_PPU_GR ATT0: PR (Bit 3) */ +#define PERI_PPU_GR_ATT0_PR_Msk (0x8UL) /*!< PERI_PPU_GR ATT0: PR (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT0_PW_Pos (4UL) /*!< PERI_PPU_GR ATT0: PW (Bit 4) */ +#define PERI_PPU_GR_ATT0_PW_Msk (0x10UL) /*!< PERI_PPU_GR ATT0: PW (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT0_PX_Pos (5UL) /*!< PERI_PPU_GR ATT0: PX (Bit 5) */ +#define PERI_PPU_GR_ATT0_PX_Msk (0x20UL) /*!< PERI_PPU_GR ATT0: PX (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT0_NS_Pos (6UL) /*!< PERI_PPU_GR ATT0: NS (Bit 6) */ +#define PERI_PPU_GR_ATT0_NS_Msk (0x40UL) /*!< PERI_PPU_GR ATT0: NS (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT0_PC_MASK_0_Pos (8UL) /*!< PERI_PPU_GR ATT0: PC_MASK_0 (Bit 8) */ +#define PERI_PPU_GR_ATT0_PC_MASK_0_Msk (0x100UL) /*!< PERI_PPU_GR ATT0: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Pos (9UL) /*!< PERI_PPU_GR ATT0: PC_MASK_15_TO_1 (Bit 9) */ +#define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Msk (0xfffe00UL) /*!< PERI_PPU_GR ATT0: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff) */ +#define PERI_PPU_GR_ATT0_REGION_SIZE_Pos (24UL) /*!< PERI_PPU_GR ATT0: REGION_SIZE (Bit 24) */ +#define PERI_PPU_GR_ATT0_REGION_SIZE_Msk (0x1f000000UL) /*!< PERI_PPU_GR ATT0: REGION_SIZE (Bitfield-Mask: 0x1f) */ +#define PERI_PPU_GR_ATT0_PC_MATCH_Pos (30UL) /*!< PERI_PPU_GR ATT0: PC_MATCH (Bit 30) */ +#define PERI_PPU_GR_ATT0_PC_MATCH_Msk (0x40000000UL) /*!< PERI_PPU_GR ATT0: PC_MATCH (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT0_ENABLED_Pos (31UL) /*!< PERI_PPU_GR ATT0: ENABLED (Bit 31) */ +#define PERI_PPU_GR_ATT0_ENABLED_Msk (0x80000000UL) /*!< PERI_PPU_GR ATT0: ENABLED (Bitfield-Mask: 0x01) */ +/* =================================================== PERI_PPU_GR.ADDR1 =================================================== */ +#define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Pos (0UL) /*!< PERI_PPU_GR ADDR1: SUBREGION_DISABLE (Bit 0) */ +#define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Msk (0xffUL) /*!< PERI_PPU_GR ADDR1: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PERI_PPU_GR_ADDR1_ADDR24_Pos (8UL) /*!< PERI_PPU_GR ADDR1: ADDR24 (Bit 8) */ +#define PERI_PPU_GR_ADDR1_ADDR24_Msk (0xffffff00UL) /*!< PERI_PPU_GR ADDR1: ADDR24 (Bitfield-Mask: 0xffffff) */ +/* =================================================== PERI_PPU_GR.ATT1 ==================================================== */ +#define PERI_PPU_GR_ATT1_UR_Pos (0UL) /*!< PERI_PPU_GR ATT1: UR (Bit 0) */ +#define PERI_PPU_GR_ATT1_UR_Msk (0x1UL) /*!< PERI_PPU_GR ATT1: UR (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT1_UW_Pos (1UL) /*!< PERI_PPU_GR ATT1: UW (Bit 1) */ +#define PERI_PPU_GR_ATT1_UW_Msk (0x2UL) /*!< PERI_PPU_GR ATT1: UW (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT1_UX_Pos (2UL) /*!< PERI_PPU_GR ATT1: UX (Bit 2) */ +#define PERI_PPU_GR_ATT1_UX_Msk (0x4UL) /*!< PERI_PPU_GR ATT1: UX (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT1_PR_Pos (3UL) /*!< PERI_PPU_GR ATT1: PR (Bit 3) */ +#define PERI_PPU_GR_ATT1_PR_Msk (0x8UL) /*!< PERI_PPU_GR ATT1: PR (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT1_PW_Pos (4UL) /*!< PERI_PPU_GR ATT1: PW (Bit 4) */ +#define PERI_PPU_GR_ATT1_PW_Msk (0x10UL) /*!< PERI_PPU_GR ATT1: PW (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT1_PX_Pos (5UL) /*!< PERI_PPU_GR ATT1: PX (Bit 5) */ +#define PERI_PPU_GR_ATT1_PX_Msk (0x20UL) /*!< PERI_PPU_GR ATT1: PX (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT1_NS_Pos (6UL) /*!< PERI_PPU_GR ATT1: NS (Bit 6) */ +#define PERI_PPU_GR_ATT1_NS_Msk (0x40UL) /*!< PERI_PPU_GR ATT1: NS (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT1_PC_MASK_0_Pos (8UL) /*!< PERI_PPU_GR ATT1: PC_MASK_0 (Bit 8) */ +#define PERI_PPU_GR_ATT1_PC_MASK_0_Msk (0x100UL) /*!< PERI_PPU_GR ATT1: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Pos (9UL) /*!< PERI_PPU_GR ATT1: PC_MASK_15_TO_1 (Bit 9) */ +#define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Msk (0xfffe00UL) /*!< PERI_PPU_GR ATT1: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff) */ +#define PERI_PPU_GR_ATT1_REGION_SIZE_Pos (24UL) /*!< PERI_PPU_GR ATT1: REGION_SIZE (Bit 24) */ +#define PERI_PPU_GR_ATT1_REGION_SIZE_Msk (0x1f000000UL) /*!< PERI_PPU_GR ATT1: REGION_SIZE (Bitfield-Mask: 0x1f) */ +#define PERI_PPU_GR_ATT1_PC_MATCH_Pos (30UL) /*!< PERI_PPU_GR ATT1: PC_MATCH (Bit 30) */ +#define PERI_PPU_GR_ATT1_PC_MATCH_Msk (0x40000000UL) /*!< PERI_PPU_GR ATT1: PC_MATCH (Bitfield-Mask: 0x01) */ +#define PERI_PPU_GR_ATT1_ENABLED_Pos (31UL) /*!< PERI_PPU_GR ATT1: ENABLED (Bit 31) */ +#define PERI_PPU_GR_ATT1_ENABLED_Msk (0x80000000UL) /*!< PERI_PPU_GR ATT1: ENABLED (Bitfield-Mask: 0x01) */ + + +/* ================================================= PERI_GR_PPU_SL.ADDR0 ================================================== */ +#define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Pos (0UL) /*!< PERI_GR_PPU_SL ADDR0: SUBREGION_DISABLE (Bit 0) */ +#define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Msk (0xffUL) /*!< PERI_GR_PPU_SL ADDR0: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PERI_GR_PPU_SL_ADDR0_ADDR24_Pos (8UL) /*!< PERI_GR_PPU_SL ADDR0: ADDR24 (Bit 8) */ +#define PERI_GR_PPU_SL_ADDR0_ADDR24_Msk (0xffffff00UL) /*!< PERI_GR_PPU_SL ADDR0: ADDR24 (Bitfield-Mask: 0xffffff) */ +/* ================================================== PERI_GR_PPU_SL.ATT0 ================================================== */ +#define PERI_GR_PPU_SL_ATT0_UR_Pos (0UL) /*!< PERI_GR_PPU_SL ATT0: UR (Bit 0) */ +#define PERI_GR_PPU_SL_ATT0_UR_Msk (0x1UL) /*!< PERI_GR_PPU_SL ATT0: UR (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT0_UW_Pos (1UL) /*!< PERI_GR_PPU_SL ATT0: UW (Bit 1) */ +#define PERI_GR_PPU_SL_ATT0_UW_Msk (0x2UL) /*!< PERI_GR_PPU_SL ATT0: UW (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT0_UX_Pos (2UL) /*!< PERI_GR_PPU_SL ATT0: UX (Bit 2) */ +#define PERI_GR_PPU_SL_ATT0_UX_Msk (0x4UL) /*!< PERI_GR_PPU_SL ATT0: UX (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT0_PR_Pos (3UL) /*!< PERI_GR_PPU_SL ATT0: PR (Bit 3) */ +#define PERI_GR_PPU_SL_ATT0_PR_Msk (0x8UL) /*!< PERI_GR_PPU_SL ATT0: PR (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT0_PW_Pos (4UL) /*!< PERI_GR_PPU_SL ATT0: PW (Bit 4) */ +#define PERI_GR_PPU_SL_ATT0_PW_Msk (0x10UL) /*!< PERI_GR_PPU_SL ATT0: PW (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT0_PX_Pos (5UL) /*!< PERI_GR_PPU_SL ATT0: PX (Bit 5) */ +#define PERI_GR_PPU_SL_ATT0_PX_Msk (0x20UL) /*!< PERI_GR_PPU_SL ATT0: PX (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT0_NS_Pos (6UL) /*!< PERI_GR_PPU_SL ATT0: NS (Bit 6) */ +#define PERI_GR_PPU_SL_ATT0_NS_Msk (0x40UL) /*!< PERI_GR_PPU_SL ATT0: NS (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Pos (8UL) /*!< PERI_GR_PPU_SL ATT0: PC_MASK_0 (Bit 8) */ +#define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Msk (0x100UL) /*!< PERI_GR_PPU_SL ATT0: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Pos (9UL) /*!< PERI_GR_PPU_SL ATT0: PC_MASK_15_TO_1 (Bit 9) */ +#define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Msk (0xfffe00UL) /*!< PERI_GR_PPU_SL ATT0: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +#define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Pos (24UL) /*!< PERI_GR_PPU_SL ATT0: REGION_SIZE (Bit 24) */ +#define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Msk (0x1f000000UL) /*!< PERI_GR_PPU_SL ATT0: REGION_SIZE (Bitfield-Mask: 0x1f) */ +#define PERI_GR_PPU_SL_ATT0_PC_MATCH_Pos (30UL) /*!< PERI_GR_PPU_SL ATT0: PC_MATCH (Bit 30) */ +#define PERI_GR_PPU_SL_ATT0_PC_MATCH_Msk (0x40000000UL) /*!< PERI_GR_PPU_SL ATT0: PC_MATCH (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT0_ENABLED_Pos (31UL) /*!< PERI_GR_PPU_SL ATT0: ENABLED (Bit 31) */ +#define PERI_GR_PPU_SL_ATT0_ENABLED_Msk (0x80000000UL) /*!< PERI_GR_PPU_SL ATT0: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================= PERI_GR_PPU_SL.ADDR1 ================================================== */ +#define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Pos (0UL) /*!< PERI_GR_PPU_SL ADDR1: SUBREGION_DISABLE (Bit 0) */ +#define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Msk (0xffUL) /*!< PERI_GR_PPU_SL ADDR1: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PERI_GR_PPU_SL_ADDR1_ADDR24_Pos (8UL) /*!< PERI_GR_PPU_SL ADDR1: ADDR24 (Bit 8) */ +#define PERI_GR_PPU_SL_ADDR1_ADDR24_Msk (0xffffff00UL) /*!< PERI_GR_PPU_SL ADDR1: ADDR24 (Bitfield-Mask: 0xffffff) */ +/* ================================================== PERI_GR_PPU_SL.ATT1 ================================================== */ +#define PERI_GR_PPU_SL_ATT1_UR_Pos (0UL) /*!< PERI_GR_PPU_SL ATT1: UR (Bit 0) */ +#define PERI_GR_PPU_SL_ATT1_UR_Msk (0x1UL) /*!< PERI_GR_PPU_SL ATT1: UR (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT1_UW_Pos (1UL) /*!< PERI_GR_PPU_SL ATT1: UW (Bit 1) */ +#define PERI_GR_PPU_SL_ATT1_UW_Msk (0x2UL) /*!< PERI_GR_PPU_SL ATT1: UW (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT1_UX_Pos (2UL) /*!< PERI_GR_PPU_SL ATT1: UX (Bit 2) */ +#define PERI_GR_PPU_SL_ATT1_UX_Msk (0x4UL) /*!< PERI_GR_PPU_SL ATT1: UX (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT1_PR_Pos (3UL) /*!< PERI_GR_PPU_SL ATT1: PR (Bit 3) */ +#define PERI_GR_PPU_SL_ATT1_PR_Msk (0x8UL) /*!< PERI_GR_PPU_SL ATT1: PR (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT1_PW_Pos (4UL) /*!< PERI_GR_PPU_SL ATT1: PW (Bit 4) */ +#define PERI_GR_PPU_SL_ATT1_PW_Msk (0x10UL) /*!< PERI_GR_PPU_SL ATT1: PW (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT1_PX_Pos (5UL) /*!< PERI_GR_PPU_SL ATT1: PX (Bit 5) */ +#define PERI_GR_PPU_SL_ATT1_PX_Msk (0x20UL) /*!< PERI_GR_PPU_SL ATT1: PX (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT1_NS_Pos (6UL) /*!< PERI_GR_PPU_SL ATT1: NS (Bit 6) */ +#define PERI_GR_PPU_SL_ATT1_NS_Msk (0x40UL) /*!< PERI_GR_PPU_SL ATT1: NS (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Pos (8UL) /*!< PERI_GR_PPU_SL ATT1: PC_MASK_0 (Bit 8) */ +#define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Msk (0x100UL) /*!< PERI_GR_PPU_SL ATT1: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Pos (9UL) /*!< PERI_GR_PPU_SL ATT1: PC_MASK_15_TO_1 (Bit 9) */ +#define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Msk (0xfffe00UL) /*!< PERI_GR_PPU_SL ATT1: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +#define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Pos (24UL) /*!< PERI_GR_PPU_SL ATT1: REGION_SIZE (Bit 24) */ +#define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Msk (0x1f000000UL) /*!< PERI_GR_PPU_SL ATT1: REGION_SIZE (Bitfield-Mask: 0x1f) */ +#define PERI_GR_PPU_SL_ATT1_PC_MATCH_Pos (30UL) /*!< PERI_GR_PPU_SL ATT1: PC_MATCH (Bit 30) */ +#define PERI_GR_PPU_SL_ATT1_PC_MATCH_Msk (0x40000000UL) /*!< PERI_GR_PPU_SL ATT1: PC_MATCH (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_SL_ATT1_ENABLED_Pos (31UL) /*!< PERI_GR_PPU_SL ATT1: ENABLED (Bit 31) */ +#define PERI_GR_PPU_SL_ATT1_ENABLED_Msk (0x80000000UL) /*!< PERI_GR_PPU_SL ATT1: ENABLED (Bitfield-Mask: 0x01) */ + + +/* ================================================= PERI_GR_PPU_RG.ADDR0 ================================================== */ +#define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Pos (0UL) /*!< PERI_GR_PPU_RG ADDR0: SUBREGION_DISABLE (Bit 0) */ +#define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Msk (0xffUL) /*!< PERI_GR_PPU_RG ADDR0: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PERI_GR_PPU_RG_ADDR0_ADDR24_Pos (8UL) /*!< PERI_GR_PPU_RG ADDR0: ADDR24 (Bit 8) */ +#define PERI_GR_PPU_RG_ADDR0_ADDR24_Msk (0xffffff00UL) /*!< PERI_GR_PPU_RG ADDR0: ADDR24 (Bitfield-Mask: 0xffffff) */ +/* ================================================== PERI_GR_PPU_RG.ATT0 ================================================== */ +#define PERI_GR_PPU_RG_ATT0_UR_Pos (0UL) /*!< PERI_GR_PPU_RG ATT0: UR (Bit 0) */ +#define PERI_GR_PPU_RG_ATT0_UR_Msk (0x1UL) /*!< PERI_GR_PPU_RG ATT0: UR (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT0_UW_Pos (1UL) /*!< PERI_GR_PPU_RG ATT0: UW (Bit 1) */ +#define PERI_GR_PPU_RG_ATT0_UW_Msk (0x2UL) /*!< PERI_GR_PPU_RG ATT0: UW (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT0_UX_Pos (2UL) /*!< PERI_GR_PPU_RG ATT0: UX (Bit 2) */ +#define PERI_GR_PPU_RG_ATT0_UX_Msk (0x4UL) /*!< PERI_GR_PPU_RG ATT0: UX (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT0_PR_Pos (3UL) /*!< PERI_GR_PPU_RG ATT0: PR (Bit 3) */ +#define PERI_GR_PPU_RG_ATT0_PR_Msk (0x8UL) /*!< PERI_GR_PPU_RG ATT0: PR (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT0_PW_Pos (4UL) /*!< PERI_GR_PPU_RG ATT0: PW (Bit 4) */ +#define PERI_GR_PPU_RG_ATT0_PW_Msk (0x10UL) /*!< PERI_GR_PPU_RG ATT0: PW (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT0_PX_Pos (5UL) /*!< PERI_GR_PPU_RG ATT0: PX (Bit 5) */ +#define PERI_GR_PPU_RG_ATT0_PX_Msk (0x20UL) /*!< PERI_GR_PPU_RG ATT0: PX (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT0_NS_Pos (6UL) /*!< PERI_GR_PPU_RG ATT0: NS (Bit 6) */ +#define PERI_GR_PPU_RG_ATT0_NS_Msk (0x40UL) /*!< PERI_GR_PPU_RG ATT0: NS (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Pos (8UL) /*!< PERI_GR_PPU_RG ATT0: PC_MASK_0 (Bit 8) */ +#define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Msk (0x100UL) /*!< PERI_GR_PPU_RG ATT0: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Pos (9UL) /*!< PERI_GR_PPU_RG ATT0: PC_MASK_15_TO_1 (Bit 9) */ +#define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Msk (0xfffe00UL) /*!< PERI_GR_PPU_RG ATT0: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +#define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Pos (24UL) /*!< PERI_GR_PPU_RG ATT0: REGION_SIZE (Bit 24) */ +#define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Msk (0x1f000000UL) /*!< PERI_GR_PPU_RG ATT0: REGION_SIZE (Bitfield-Mask: 0x1f) */ +#define PERI_GR_PPU_RG_ATT0_PC_MATCH_Pos (30UL) /*!< PERI_GR_PPU_RG ATT0: PC_MATCH (Bit 30) */ +#define PERI_GR_PPU_RG_ATT0_PC_MATCH_Msk (0x40000000UL) /*!< PERI_GR_PPU_RG ATT0: PC_MATCH (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT0_ENABLED_Pos (31UL) /*!< PERI_GR_PPU_RG ATT0: ENABLED (Bit 31) */ +#define PERI_GR_PPU_RG_ATT0_ENABLED_Msk (0x80000000UL) /*!< PERI_GR_PPU_RG ATT0: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================= PERI_GR_PPU_RG.ADDR1 ================================================== */ +#define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Pos (0UL) /*!< PERI_GR_PPU_RG ADDR1: SUBREGION_DISABLE (Bit 0) */ +#define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Msk (0xffUL) /*!< PERI_GR_PPU_RG ADDR1: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PERI_GR_PPU_RG_ADDR1_ADDR24_Pos (8UL) /*!< PERI_GR_PPU_RG ADDR1: ADDR24 (Bit 8) */ +#define PERI_GR_PPU_RG_ADDR1_ADDR24_Msk (0xffffff00UL) /*!< PERI_GR_PPU_RG ADDR1: ADDR24 (Bitfield-Mask: 0xffffff) */ +/* ================================================== PERI_GR_PPU_RG.ATT1 ================================================== */ +#define PERI_GR_PPU_RG_ATT1_UR_Pos (0UL) /*!< PERI_GR_PPU_RG ATT1: UR (Bit 0) */ +#define PERI_GR_PPU_RG_ATT1_UR_Msk (0x1UL) /*!< PERI_GR_PPU_RG ATT1: UR (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT1_UW_Pos (1UL) /*!< PERI_GR_PPU_RG ATT1: UW (Bit 1) */ +#define PERI_GR_PPU_RG_ATT1_UW_Msk (0x2UL) /*!< PERI_GR_PPU_RG ATT1: UW (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT1_UX_Pos (2UL) /*!< PERI_GR_PPU_RG ATT1: UX (Bit 2) */ +#define PERI_GR_PPU_RG_ATT1_UX_Msk (0x4UL) /*!< PERI_GR_PPU_RG ATT1: UX (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT1_PR_Pos (3UL) /*!< PERI_GR_PPU_RG ATT1: PR (Bit 3) */ +#define PERI_GR_PPU_RG_ATT1_PR_Msk (0x8UL) /*!< PERI_GR_PPU_RG ATT1: PR (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT1_PW_Pos (4UL) /*!< PERI_GR_PPU_RG ATT1: PW (Bit 4) */ +#define PERI_GR_PPU_RG_ATT1_PW_Msk (0x10UL) /*!< PERI_GR_PPU_RG ATT1: PW (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT1_PX_Pos (5UL) /*!< PERI_GR_PPU_RG ATT1: PX (Bit 5) */ +#define PERI_GR_PPU_RG_ATT1_PX_Msk (0x20UL) /*!< PERI_GR_PPU_RG ATT1: PX (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT1_NS_Pos (6UL) /*!< PERI_GR_PPU_RG ATT1: NS (Bit 6) */ +#define PERI_GR_PPU_RG_ATT1_NS_Msk (0x40UL) /*!< PERI_GR_PPU_RG ATT1: NS (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Pos (8UL) /*!< PERI_GR_PPU_RG ATT1: PC_MASK_0 (Bit 8) */ +#define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Msk (0x100UL) /*!< PERI_GR_PPU_RG ATT1: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Pos (9UL) /*!< PERI_GR_PPU_RG ATT1: PC_MASK_15_TO_1 (Bit 9) */ +#define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Msk (0xfffe00UL) /*!< PERI_GR_PPU_RG ATT1: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +#define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Pos (24UL) /*!< PERI_GR_PPU_RG ATT1: REGION_SIZE (Bit 24) */ +#define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Msk (0x1f000000UL) /*!< PERI_GR_PPU_RG ATT1: REGION_SIZE (Bitfield-Mask: 0x1f) */ +#define PERI_GR_PPU_RG_ATT1_PC_MATCH_Pos (30UL) /*!< PERI_GR_PPU_RG ATT1: PC_MATCH (Bit 30) */ +#define PERI_GR_PPU_RG_ATT1_PC_MATCH_Msk (0x40000000UL) /*!< PERI_GR_PPU_RG ATT1: PC_MATCH (Bitfield-Mask: 0x01) */ +#define PERI_GR_PPU_RG_ATT1_ENABLED_Pos (31UL) /*!< PERI_GR_PPU_RG ATT1: ENABLED (Bit 31) */ +#define PERI_GR_PPU_RG_ATT1_ENABLED_Msk (0x80000000UL) /*!< PERI_GR_PPU_RG ATT1: ENABLED (Bitfield-Mask: 0x01) */ + + +/* ===================================================== PERI.DIV_CMD ====================================================== */ +#define PERI_DIV_CMD_DIV_SEL_Pos (0UL) /*!< PERI DIV_CMD: DIV_SEL (Bit 0) */ +#define PERI_DIV_CMD_DIV_SEL_Msk (0x3fUL) /*!< PERI DIV_CMD: DIV_SEL (Bitfield-Mask: 0x3f) */ +#define PERI_DIV_CMD_TYPE_SEL_Pos (6UL) /*!< PERI DIV_CMD: TYPE_SEL (Bit 6) */ +#define PERI_DIV_CMD_TYPE_SEL_Msk (0xc0UL) /*!< PERI DIV_CMD: TYPE_SEL (Bitfield-Mask: 0x03) */ +#define PERI_DIV_CMD_PA_DIV_SEL_Pos (8UL) /*!< PERI DIV_CMD: PA_DIV_SEL (Bit 8) */ +#define PERI_DIV_CMD_PA_DIV_SEL_Msk (0x3f00UL) /*!< PERI DIV_CMD: PA_DIV_SEL (Bitfield-Mask: 0x3f) */ +#define PERI_DIV_CMD_PA_TYPE_SEL_Pos (14UL) /*!< PERI DIV_CMD: PA_TYPE_SEL (Bit 14) */ +#define PERI_DIV_CMD_PA_TYPE_SEL_Msk (0xc000UL) /*!< PERI DIV_CMD: PA_TYPE_SEL (Bitfield-Mask: 0x03) */ +#define PERI_DIV_CMD_DISABLE_Pos (30UL) /*!< PERI DIV_CMD: DISABLE (Bit 30) */ +#define PERI_DIV_CMD_DISABLE_Msk (0x40000000UL) /*!< PERI DIV_CMD: DISABLE (Bitfield-Mask: 0x01) */ +#define PERI_DIV_CMD_ENABLE_Pos (31UL) /*!< PERI DIV_CMD: ENABLE (Bit 31) */ +#define PERI_DIV_CMD_ENABLE_Msk (0x80000000UL) /*!< PERI DIV_CMD: ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== PERI.DIV_8_CTL ===================================================== */ +#define PERI_DIV_8_CTL_EN_Pos (0UL) /*!< PERI DIV_8_CTL: EN (Bit 0) */ +#define PERI_DIV_8_CTL_EN_Msk (0x1UL) /*!< PERI DIV_8_CTL: EN (Bitfield-Mask: 0x01) */ +#define PERI_DIV_8_CTL_INT8_DIV_Pos (8UL) /*!< PERI DIV_8_CTL: INT8_DIV (Bit 8) */ +#define PERI_DIV_8_CTL_INT8_DIV_Msk (0xff00UL) /*!< PERI DIV_8_CTL: INT8_DIV (Bitfield-Mask: 0xff) */ +/* ==================================================== PERI.DIV_16_CTL ==================================================== */ +#define PERI_DIV_16_CTL_EN_Pos (0UL) /*!< PERI DIV_16_CTL: EN (Bit 0) */ +#define PERI_DIV_16_CTL_EN_Msk (0x1UL) /*!< PERI DIV_16_CTL: EN (Bitfield-Mask: 0x01) */ +#define PERI_DIV_16_CTL_INT16_DIV_Pos (8UL) /*!< PERI DIV_16_CTL: INT16_DIV (Bit 8) */ +#define PERI_DIV_16_CTL_INT16_DIV_Msk (0xffff00UL) /*!< PERI DIV_16_CTL: INT16_DIV (Bitfield-Mask: 0xffff) */ +/* =================================================== PERI.DIV_16_5_CTL =================================================== */ +#define PERI_DIV_16_5_CTL_EN_Pos (0UL) /*!< PERI DIV_16_5_CTL: EN (Bit 0) */ +#define PERI_DIV_16_5_CTL_EN_Msk (0x1UL) /*!< PERI DIV_16_5_CTL: EN (Bitfield-Mask: 0x01) */ +#define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos (3UL) /*!< PERI DIV_16_5_CTL: FRAC5_DIV (Bit 3) */ +#define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk (0xf8UL) /*!< PERI DIV_16_5_CTL: FRAC5_DIV (Bitfield-Mask: 0x1f) */ +#define PERI_DIV_16_5_CTL_INT16_DIV_Pos (8UL) /*!< PERI DIV_16_5_CTL: INT16_DIV (Bit 8) */ +#define PERI_DIV_16_5_CTL_INT16_DIV_Msk (0xffff00UL) /*!< PERI DIV_16_5_CTL: INT16_DIV (Bitfield-Mask: 0xffff) */ +/* =================================================== PERI.DIV_24_5_CTL =================================================== */ +#define PERI_DIV_24_5_CTL_EN_Pos (0UL) /*!< PERI DIV_24_5_CTL: EN (Bit 0) */ +#define PERI_DIV_24_5_CTL_EN_Msk (0x1UL) /*!< PERI DIV_24_5_CTL: EN (Bitfield-Mask: 0x01) */ +#define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos (3UL) /*!< PERI DIV_24_5_CTL: FRAC5_DIV (Bit 3) */ +#define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk (0xf8UL) /*!< PERI DIV_24_5_CTL: FRAC5_DIV (Bitfield-Mask: 0x1f) */ +#define PERI_DIV_24_5_CTL_INT24_DIV_Pos (8UL) /*!< PERI DIV_24_5_CTL: INT24_DIV (Bit 8) */ +#define PERI_DIV_24_5_CTL_INT24_DIV_Msk (0xffffff00UL) /*!< PERI DIV_24_5_CTL: INT24_DIV (Bitfield-Mask: 0xffffff) */ +/* ==================================================== PERI.CLOCK_CTL ===================================================== */ +#define PERI_CLOCK_CTL_DIV_SEL_Pos (0UL) /*!< PERI CLOCK_CTL: DIV_SEL (Bit 0) */ +#define PERI_CLOCK_CTL_DIV_SEL_Msk (0x3fUL) /*!< PERI CLOCK_CTL: DIV_SEL (Bitfield-Mask: 0x3f) */ +#define PERI_CLOCK_CTL_TYPE_SEL_Pos (6UL) /*!< PERI CLOCK_CTL: TYPE_SEL (Bit 6) */ +#define PERI_CLOCK_CTL_TYPE_SEL_Msk (0xc0UL) /*!< PERI CLOCK_CTL: TYPE_SEL (Bitfield-Mask: 0x03) */ +/* ====================================================== PERI.TR_CMD ====================================================== */ +#define PERI_TR_CMD_TR_SEL_Pos (0UL) /*!< PERI TR_CMD: TR_SEL (Bit 0) */ +#define PERI_TR_CMD_TR_SEL_Msk (0x7fUL) /*!< PERI TR_CMD: TR_SEL (Bitfield-Mask: 0x7f) */ +#define PERI_TR_CMD_GROUP_SEL_Pos (8UL) /*!< PERI TR_CMD: GROUP_SEL (Bit 8) */ +#define PERI_TR_CMD_GROUP_SEL_Msk (0xf00UL) /*!< PERI TR_CMD: GROUP_SEL (Bitfield-Mask: 0x0f) */ +#define PERI_TR_CMD_COUNT_Pos (16UL) /*!< PERI TR_CMD: COUNT (Bit 16) */ +#define PERI_TR_CMD_COUNT_Msk (0xff0000UL) /*!< PERI TR_CMD: COUNT (Bitfield-Mask: 0xff) */ +#define PERI_TR_CMD_OUT_SEL_Pos (30UL) /*!< PERI TR_CMD: OUT_SEL (Bit 30) */ +#define PERI_TR_CMD_OUT_SEL_Msk (0x40000000UL) /*!< PERI TR_CMD: OUT_SEL (Bitfield-Mask: 0x01) */ +#define PERI_TR_CMD_ACTIVATE_Pos (31UL) /*!< PERI TR_CMD: ACTIVATE (Bit 31) */ +#define PERI_TR_CMD_ACTIVATE_Msk (0x80000000UL) /*!< PERI TR_CMD: ACTIVATE (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_PERI_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_profile.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_profile.h new file mode 100644 index 0000000000..24b504e6df --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_profile.h @@ -0,0 +1,105 @@ +/***************************************************************************//** +* \file cyip_profile.h +* +* \brief +* PROFILE IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_PROFILE_H_ +#define _CYIP_PROFILE_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ PROFILE ================ */ +/* =========================================================================================================================== */ + +#define PROFILE_CNT_STRUCT_SECTION_SIZE 0x00000010UL +#define PROFILE_SECTION_SIZE 0x00010000UL + +/** + * \brief Profile counter structure (PROFILE_CNT_STRUCT) + */ +typedef struct { + __IOM uint32_t CTL; /*!< 0x00000000 Profile counter configuration */ + __IM uint32_t RESERVED; + __IOM uint32_t CNT; /*!< 0x00000008 Profile counter value */ + __IM uint32_t RESERVED1; +} PROFILE_CNT_STRUCT_Type; /*!< Size = 12 (0xC) */ + +/** + * \brief Energy Profiler IP (PROFILE) + */ +typedef struct { /*!< PROFILE Structure */ + __IOM uint32_t CTL; /*!< 0x00000000 Profile control */ + __IM uint32_t STATUS; /*!< 0x00000004 Profile status */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t CMD; /*!< 0x00000010 Profile command */ + __IM uint32_t RESERVED1[491]; + __IOM uint32_t INTR; /*!< 0x000007C0 Profile interrupt */ + __IOM uint32_t INTR_SET; /*!< 0x000007C4 Profile interrupt set */ + __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Profile interrupt mask */ + __IM uint32_t INTR_MASKED; /*!< 0x000007CC Profile interrupt masked */ + __IM uint32_t RESERVED2[12]; + PROFILE_CNT_STRUCT_Type CNT_STRUCT[16]; /*!< 0x00000800 Profile counter structure */ +} PROFILE_Type; /*!< Size = 2304 (0x900) */ + + +/* ================================================ PROFILE_CNT_STRUCT.CTL ================================================= */ +#define PROFILE_CNT_STRUCT_CTL_CNT_DURATION_Pos (0UL) /*!< PROFILE_CNT_STRUCT CTL: CNT_DURATION (Bit 0) */ +#define PROFILE_CNT_STRUCT_CTL_CNT_DURATION_Msk (0x1UL) /*!< PROFILE_CNT_STRUCT CTL: CNT_DURATION (Bitfield-Mask: 0x01)*/ +#define PROFILE_CNT_STRUCT_CTL_REF_CLK_SEL_Pos (4UL) /*!< PROFILE_CNT_STRUCT CTL: REF_CLK_SEL (Bit 4) */ +#define PROFILE_CNT_STRUCT_CTL_REF_CLK_SEL_Msk (0x70UL) /*!< PROFILE_CNT_STRUCT CTL: REF_CLK_SEL (Bitfield-Mask: 0x07) */ +#define PROFILE_CNT_STRUCT_CTL_MON_SEL_Pos (16UL) /*!< PROFILE_CNT_STRUCT CTL: MON_SEL (Bit 16) */ +#define PROFILE_CNT_STRUCT_CTL_MON_SEL_Msk (0x7f0000UL) /*!< PROFILE_CNT_STRUCT CTL: MON_SEL (Bitfield-Mask: 0x7f) */ +#define PROFILE_CNT_STRUCT_CTL_ENABLED_Pos (31UL) /*!< PROFILE_CNT_STRUCT CTL: ENABLED (Bit 31) */ +#define PROFILE_CNT_STRUCT_CTL_ENABLED_Msk (0x80000000UL) /*!< PROFILE_CNT_STRUCT CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================ PROFILE_CNT_STRUCT.CNT ================================================= */ +#define PROFILE_CNT_STRUCT_CNT_CNT_Pos (0UL) /*!< PROFILE_CNT_STRUCT CNT: CNT (Bit 0) */ +#define PROFILE_CNT_STRUCT_CNT_CNT_Msk (0xffffffffUL) /*!< PROFILE_CNT_STRUCT CNT: CNT (Bitfield-Mask: 0xffffffff) */ + + +/* ====================================================== PROFILE.CTL ====================================================== */ +#define PROFILE_CTL_WIN_MODE_Pos (0UL) /*!< PROFILE CTL: WIN_MODE (Bit 0) */ +#define PROFILE_CTL_WIN_MODE_Msk (0x1UL) /*!< PROFILE CTL: WIN_MODE (Bitfield-Mask: 0x01) */ +#define PROFILE_CTL_ENABLED_Pos (31UL) /*!< PROFILE CTL: ENABLED (Bit 31) */ +#define PROFILE_CTL_ENABLED_Msk (0x80000000UL) /*!< PROFILE CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ==================================================== PROFILE.STATUS ===================================================== */ +#define PROFILE_STATUS_WIN_ACTIVE_Pos (0UL) /*!< PROFILE STATUS: WIN_ACTIVE (Bit 0) */ +#define PROFILE_STATUS_WIN_ACTIVE_Msk (0x1UL) /*!< PROFILE STATUS: WIN_ACTIVE (Bitfield-Mask: 0x01) */ +/* ====================================================== PROFILE.CMD ====================================================== */ +#define PROFILE_CMD_START_TR_Pos (0UL) /*!< PROFILE CMD: START_TR (Bit 0) */ +#define PROFILE_CMD_START_TR_Msk (0x1UL) /*!< PROFILE CMD: START_TR (Bitfield-Mask: 0x01) */ +#define PROFILE_CMD_STOP_TR_Pos (1UL) /*!< PROFILE CMD: STOP_TR (Bit 1) */ +#define PROFILE_CMD_STOP_TR_Msk (0x2UL) /*!< PROFILE CMD: STOP_TR (Bitfield-Mask: 0x01) */ +#define PROFILE_CMD_CLR_ALL_CNT_Pos (8UL) /*!< PROFILE CMD: CLR_ALL_CNT (Bit 8) */ +#define PROFILE_CMD_CLR_ALL_CNT_Msk (0x100UL) /*!< PROFILE CMD: CLR_ALL_CNT (Bitfield-Mask: 0x01) */ +/* ===================================================== PROFILE.INTR ====================================================== */ +#define PROFILE_INTR_CNT_OVFLW_Pos (0UL) /*!< PROFILE INTR: CNT_OVFLW (Bit 0) */ +#define PROFILE_INTR_CNT_OVFLW_Msk (0xffffffffUL) /*!< PROFILE INTR: CNT_OVFLW (Bitfield-Mask: 0xffffffff) */ +/* =================================================== PROFILE.INTR_SET ==================================================== */ +#define PROFILE_INTR_SET_CNT_OVFLW_Pos (0UL) /*!< PROFILE INTR_SET: CNT_OVFLW (Bit 0) */ +#define PROFILE_INTR_SET_CNT_OVFLW_Msk (0xffffffffUL) /*!< PROFILE INTR_SET: CNT_OVFLW (Bitfield-Mask: 0xffffffff) */ +/* =================================================== PROFILE.INTR_MASK =================================================== */ +#define PROFILE_INTR_MASK_CNT_OVFLW_Pos (0UL) /*!< PROFILE INTR_MASK: CNT_OVFLW (Bit 0) */ +#define PROFILE_INTR_MASK_CNT_OVFLW_Msk (0xffffffffUL) /*!< PROFILE INTR_MASK: CNT_OVFLW (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PROFILE.INTR_MASKED ================================================== */ +#define PROFILE_INTR_MASKED_CNT_OVFLW_Pos (0UL) /*!< PROFILE INTR_MASKED: CNT_OVFLW (Bit 0) */ +#define PROFILE_INTR_MASKED_CNT_OVFLW_Msk (0xffffffffUL) /*!< PROFILE INTR_MASKED: CNT_OVFLW (Bitfield-Mask: 0xffffffff)*/ + + +#endif /* _CYIP_PROFILE_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_prot.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_prot.h new file mode 100644 index 0000000000..3d8cc5843d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_prot.h @@ -0,0 +1,374 @@ +/***************************************************************************//** +* \file cyip_prot.h +* +* \brief +* PROT IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_PROT_H_ +#define _CYIP_PROT_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ PROT ================ */ +/* =========================================================================================================================== */ + +#define PROT_SMPU_SMPU_STRUCT_SECTION_SIZE 0x00000040UL +#define PROT_SMPU_SECTION_SIZE 0x00004000UL +#define PROT_MPU_MPU_STRUCT_SECTION_SIZE 0x00000020UL +#define PROT_MPU_SECTION_SIZE 0x00000400UL +#define PROT_SECTION_SIZE 0x00010000UL + +/** + * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT) + */ +typedef struct { + __IOM uint32_t ADDR0; /*!< 0x00000000 SMPU region address 0 (slave structure) */ + __IOM uint32_t ATT0; /*!< 0x00000004 SMPU region attributes 0 (slave structure) */ + __IM uint32_t RESERVED[6]; + __IM uint32_t ADDR1; /*!< 0x00000020 SMPU region address 1 (master structure) */ + __IOM uint32_t ATT1; /*!< 0x00000024 SMPU region attributes 1 (master structure) */ + __IM uint32_t RESERVED1[6]; +} PROT_SMPU_SMPU_STRUCT_Type; /*!< Size = 40 (0x28) */ + +/** + * \brief SMPU (PROT_SMPU) + */ +typedef struct { + __IOM uint32_t MS0_CTL; /*!< 0x00000000 Master 0 protection context control */ + __IOM uint32_t MS1_CTL; /*!< 0x00000004 Master 1 protection context control */ + __IOM uint32_t MS2_CTL; /*!< 0x00000008 Master 2 protection context control */ + __IOM uint32_t MS3_CTL; /*!< 0x0000000C Master 3 protection context control */ + __IOM uint32_t MS4_CTL; /*!< 0x00000010 Master 4 protection context control */ + __IOM uint32_t MS5_CTL; /*!< 0x00000014 Master 5 protection context control */ + __IOM uint32_t MS6_CTL; /*!< 0x00000018 Master 6 protection context control */ + __IOM uint32_t MS7_CTL; /*!< 0x0000001C Master 7 protection context control */ + __IOM uint32_t MS8_CTL; /*!< 0x00000020 Master 8 protection context control */ + __IOM uint32_t MS9_CTL; /*!< 0x00000024 Master 9 protection context control */ + __IOM uint32_t MS10_CTL; /*!< 0x00000028 Master 10 protection context control */ + __IOM uint32_t MS11_CTL; /*!< 0x0000002C Master 11 protection context control */ + __IOM uint32_t MS12_CTL; /*!< 0x00000030 Master 12 protection context control */ + __IOM uint32_t MS13_CTL; /*!< 0x00000034 Master 13 protection context control */ + __IOM uint32_t MS14_CTL; /*!< 0x00000038 Master 14 protection context control */ + __IOM uint32_t MS15_CTL; /*!< 0x0000003C Master 15 protection context control */ + __IM uint32_t RESERVED[2032]; + PROT_SMPU_SMPU_STRUCT_Type SMPU_STRUCT[32]; /*!< 0x00002000 SMPU structure */ + __IM uint32_t RESERVED1[1536]; +} PROT_SMPU_Type; /*!< Size = 10240 (0x2800) */ + +/** + * \brief MPU structure (PROT_MPU_MPU_STRUCT) + */ +typedef struct { + __IOM uint32_t ADDR; /*!< 0x00000000 MPU region address */ + __IOM uint32_t ATT; /*!< 0x00000004 MPU region attrributes */ + __IM uint32_t RESERVED[6]; +} PROT_MPU_MPU_STRUCT_Type; /*!< Size = 8 (0x8) */ + +/** + * \brief MPU (PROT_MPU) + */ +typedef struct { + __IOM uint32_t MS_CTL; /*!< 0x00000000 Master control */ + __IM uint32_t RESERVED[127]; + PROT_MPU_MPU_STRUCT_Type MPU_STRUCT[16]; /*!< 0x00000200 MPU structure */ +} PROT_MPU_Type; /*!< Size = 1024 (0x400) */ + +/** + * \brief Protection (PROT) + */ +typedef struct { /*!< PROT Structure */ + PROT_SMPU_Type SMPU; /*!< 0x00000000 SMPU */ + PROT_MPU_Type CYMPU[16]; /*!< 0x00004000 MPU */ +} PROT_Type; /*!< Size = 32768 (0x8000) */ + + +/* ============================================== PROT_SMPU_SMPU_STRUCT.ADDR0 ============================================== */ +#define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Pos (0UL) /*!< PROT_SMPU_SMPU_STRUCT ADDR0: SUBREGION_DISABLE (Bit 0) */ +#define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Msk (0xffUL) /*!< PROT_SMPU_SMPU_STRUCT ADDR0: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Pos (8UL) /*!< PROT_SMPU_SMPU_STRUCT ADDR0: ADDR24 (Bit 8) */ +#define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Msk (0xffffff00UL) /*!< PROT_SMPU_SMPU_STRUCT ADDR0: ADDR24 (Bitfield-Mask: 0xffffff)*/ +/* ============================================== PROT_SMPU_SMPU_STRUCT.ATT0 =============================================== */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Pos (0UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: UR (Bit 0) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Msk (0x1UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: UR (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Pos (1UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: UW (Bit 1) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Msk (0x2UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: UW (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Pos (2UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: UX (Bit 2) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Msk (0x4UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: UX (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Pos (3UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PR (Bit 3) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Msk (0x8UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PR (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Pos (4UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PW (Bit 4) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Msk (0x10UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PW (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Pos (5UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PX (Bit 5) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Msk (0x20UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PX (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Pos (6UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: NS (Bit 6) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Msk (0x40UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Pos (8UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PC_MASK_0 (Bit 8) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk (0x100UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PC_MASK_0 (Bitfield-Mask: 0x01)*/ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Pos (9UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PC_MASK_15_TO_1 (Bit 9) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Msk (0xfffe00UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +#define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Pos (24UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: REGION_SIZE (Bit 24) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Msk (0x1f000000UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: REGION_SIZE (Bitfield-Mask: 0x1f)*/ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Pos (30UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PC_MATCH (Bit 30) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Msk (0x40000000UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: PC_MATCH (Bitfield-Mask: 0x01)*/ +#define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Pos (31UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: ENABLED (Bit 31) */ +#define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Msk (0x80000000UL) /*!< PROT_SMPU_SMPU_STRUCT ATT0: ENABLED (Bitfield-Mask: 0x01) */ +/* ============================================== PROT_SMPU_SMPU_STRUCT.ADDR1 ============================================== */ +#define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Pos (0UL) /*!< PROT_SMPU_SMPU_STRUCT ADDR1: SUBREGION_DISABLE (Bit 0) */ +#define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Msk (0xffUL) /*!< PROT_SMPU_SMPU_STRUCT ADDR1: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Pos (8UL) /*!< PROT_SMPU_SMPU_STRUCT ADDR1: ADDR24 (Bit 8) */ +#define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Msk (0xffffff00UL) /*!< PROT_SMPU_SMPU_STRUCT ADDR1: ADDR24 (Bitfield-Mask: 0xffffff)*/ +/* ============================================== PROT_SMPU_SMPU_STRUCT.ATT1 =============================================== */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Pos (0UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: UR (Bit 0) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Msk (0x1UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: UR (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Pos (1UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: UW (Bit 1) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Msk (0x2UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: UW (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Pos (2UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: UX (Bit 2) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk (0x4UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: UX (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Pos (3UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PR (Bit 3) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Msk (0x8UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PR (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Pos (4UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PW (Bit 4) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Msk (0x10UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PW (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Pos (5UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PX (Bit 5) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk (0x20UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PX (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Pos (6UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: NS (Bit 6) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Msk (0x40UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Pos (8UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PC_MASK_0 (Bit 8) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk (0x100UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PC_MASK_0 (Bitfield-Mask: 0x01)*/ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Pos (9UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PC_MASK_15_TO_1 (Bit 9) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Msk (0xfffe00UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +#define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Pos (24UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: REGION_SIZE (Bit 24) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk (0x1f000000UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: REGION_SIZE (Bitfield-Mask: 0x1f)*/ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Pos (30UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PC_MATCH (Bit 30) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Msk (0x40000000UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: PC_MATCH (Bitfield-Mask: 0x01)*/ +#define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Pos (31UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: ENABLED (Bit 31) */ +#define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Msk (0x80000000UL) /*!< PROT_SMPU_SMPU_STRUCT ATT1: ENABLED (Bitfield-Mask: 0x01) */ + + +/* =================================================== PROT_SMPU.MS0_CTL =================================================== */ +#define PROT_SMPU_MS0_CTL_P_Pos (0UL) /*!< PROT_SMPU MS0_CTL: P (Bit 0) */ +#define PROT_SMPU_MS0_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS0_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS0_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS0_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS0_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS0_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS0_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS0_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS0_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS0_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS0_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS0_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS0_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS0_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS0_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS0_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* =================================================== PROT_SMPU.MS1_CTL =================================================== */ +#define PROT_SMPU_MS1_CTL_P_Pos (0UL) /*!< PROT_SMPU MS1_CTL: P (Bit 0) */ +#define PROT_SMPU_MS1_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS1_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS1_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS1_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS1_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS1_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS1_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS1_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS1_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS1_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS1_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS1_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS1_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS1_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS1_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS1_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* =================================================== PROT_SMPU.MS2_CTL =================================================== */ +#define PROT_SMPU_MS2_CTL_P_Pos (0UL) /*!< PROT_SMPU MS2_CTL: P (Bit 0) */ +#define PROT_SMPU_MS2_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS2_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS2_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS2_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS2_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS2_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS2_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS2_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS2_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS2_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS2_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS2_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS2_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS2_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS2_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS2_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* =================================================== PROT_SMPU.MS3_CTL =================================================== */ +#define PROT_SMPU_MS3_CTL_P_Pos (0UL) /*!< PROT_SMPU MS3_CTL: P (Bit 0) */ +#define PROT_SMPU_MS3_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS3_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS3_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS3_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS3_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS3_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS3_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS3_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS3_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS3_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS3_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS3_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS3_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS3_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS3_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS3_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* =================================================== PROT_SMPU.MS4_CTL =================================================== */ +#define PROT_SMPU_MS4_CTL_P_Pos (0UL) /*!< PROT_SMPU MS4_CTL: P (Bit 0) */ +#define PROT_SMPU_MS4_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS4_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS4_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS4_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS4_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS4_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS4_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS4_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS4_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS4_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS4_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS4_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS4_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS4_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS4_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS4_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* =================================================== PROT_SMPU.MS5_CTL =================================================== */ +#define PROT_SMPU_MS5_CTL_P_Pos (0UL) /*!< PROT_SMPU MS5_CTL: P (Bit 0) */ +#define PROT_SMPU_MS5_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS5_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS5_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS5_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS5_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS5_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS5_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS5_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS5_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS5_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS5_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS5_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS5_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS5_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS5_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS5_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* =================================================== PROT_SMPU.MS6_CTL =================================================== */ +#define PROT_SMPU_MS6_CTL_P_Pos (0UL) /*!< PROT_SMPU MS6_CTL: P (Bit 0) */ +#define PROT_SMPU_MS6_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS6_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS6_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS6_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS6_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS6_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS6_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS6_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS6_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS6_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS6_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS6_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS6_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS6_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS6_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS6_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* =================================================== PROT_SMPU.MS7_CTL =================================================== */ +#define PROT_SMPU_MS7_CTL_P_Pos (0UL) /*!< PROT_SMPU MS7_CTL: P (Bit 0) */ +#define PROT_SMPU_MS7_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS7_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS7_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS7_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS7_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS7_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS7_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS7_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS7_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS7_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS7_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS7_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS7_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS7_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS7_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS7_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* =================================================== PROT_SMPU.MS8_CTL =================================================== */ +#define PROT_SMPU_MS8_CTL_P_Pos (0UL) /*!< PROT_SMPU MS8_CTL: P (Bit 0) */ +#define PROT_SMPU_MS8_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS8_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS8_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS8_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS8_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS8_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS8_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS8_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS8_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS8_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS8_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS8_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS8_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS8_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS8_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS8_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* =================================================== PROT_SMPU.MS9_CTL =================================================== */ +#define PROT_SMPU_MS9_CTL_P_Pos (0UL) /*!< PROT_SMPU MS9_CTL: P (Bit 0) */ +#define PROT_SMPU_MS9_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS9_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS9_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS9_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS9_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS9_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS9_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS9_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS9_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS9_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS9_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS9_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS9_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS9_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS9_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS9_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* ================================================== PROT_SMPU.MS10_CTL =================================================== */ +#define PROT_SMPU_MS10_CTL_P_Pos (0UL) /*!< PROT_SMPU MS10_CTL: P (Bit 0) */ +#define PROT_SMPU_MS10_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS10_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS10_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS10_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS10_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS10_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS10_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS10_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS10_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS10_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS10_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS10_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS10_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS10_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS10_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS10_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* ================================================== PROT_SMPU.MS11_CTL =================================================== */ +#define PROT_SMPU_MS11_CTL_P_Pos (0UL) /*!< PROT_SMPU MS11_CTL: P (Bit 0) */ +#define PROT_SMPU_MS11_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS11_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS11_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS11_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS11_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS11_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS11_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS11_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS11_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS11_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS11_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS11_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS11_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS11_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS11_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS11_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* ================================================== PROT_SMPU.MS12_CTL =================================================== */ +#define PROT_SMPU_MS12_CTL_P_Pos (0UL) /*!< PROT_SMPU MS12_CTL: P (Bit 0) */ +#define PROT_SMPU_MS12_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS12_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS12_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS12_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS12_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS12_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS12_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS12_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS12_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS12_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS12_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS12_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS12_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS12_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS12_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS12_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* ================================================== PROT_SMPU.MS13_CTL =================================================== */ +#define PROT_SMPU_MS13_CTL_P_Pos (0UL) /*!< PROT_SMPU MS13_CTL: P (Bit 0) */ +#define PROT_SMPU_MS13_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS13_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS13_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS13_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS13_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS13_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS13_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS13_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS13_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS13_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS13_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS13_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS13_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS13_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS13_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS13_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* ================================================== PROT_SMPU.MS14_CTL =================================================== */ +#define PROT_SMPU_MS14_CTL_P_Pos (0UL) /*!< PROT_SMPU MS14_CTL: P (Bit 0) */ +#define PROT_SMPU_MS14_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS14_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS14_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS14_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS14_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS14_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS14_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS14_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS14_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS14_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS14_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS14_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS14_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS14_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS14_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS14_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ +/* ================================================== PROT_SMPU.MS15_CTL =================================================== */ +#define PROT_SMPU_MS15_CTL_P_Pos (0UL) /*!< PROT_SMPU MS15_CTL: P (Bit 0) */ +#define PROT_SMPU_MS15_CTL_P_Msk (0x1UL) /*!< PROT_SMPU MS15_CTL: P (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS15_CTL_NS_Pos (1UL) /*!< PROT_SMPU MS15_CTL: NS (Bit 1) */ +#define PROT_SMPU_MS15_CTL_NS_Msk (0x2UL) /*!< PROT_SMPU MS15_CTL: NS (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS15_CTL_PRIO_Pos (8UL) /*!< PROT_SMPU MS15_CTL: PRIO (Bit 8) */ +#define PROT_SMPU_MS15_CTL_PRIO_Msk (0x300UL) /*!< PROT_SMPU MS15_CTL: PRIO (Bitfield-Mask: 0x03) */ +#define PROT_SMPU_MS15_CTL_PC_MASK_0_Pos (16UL) /*!< PROT_SMPU MS15_CTL: PC_MASK_0 (Bit 16) */ +#define PROT_SMPU_MS15_CTL_PC_MASK_0_Msk (0x10000UL) /*!< PROT_SMPU MS15_CTL: PC_MASK_0 (Bitfield-Mask: 0x01) */ +#define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Pos (17UL) /*!< PROT_SMPU MS15_CTL: PC_MASK_15_TO_1 (Bit 17) */ +#define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Msk (0xfffe0000UL) /*!< PROT_SMPU MS15_CTL: PC_MASK_15_TO_1 (Bitfield-Mask: 0x7fff)*/ + + +/* =============================================== PROT_MPU_MPU_STRUCT.ADDR ================================================ */ +#define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Pos (0UL) /*!< PROT_MPU_MPU_STRUCT ADDR: SUBREGION_DISABLE (Bit 0) */ +#define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Msk (0xffUL) /*!< PROT_MPU_MPU_STRUCT ADDR: SUBREGION_DISABLE (Bitfield-Mask: 0xff)*/ +#define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Pos (8UL) /*!< PROT_MPU_MPU_STRUCT ADDR: ADDR24 (Bit 8) */ +#define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Msk (0xffffff00UL) /*!< PROT_MPU_MPU_STRUCT ADDR: ADDR24 (Bitfield-Mask: 0xffffff)*/ +/* ================================================ PROT_MPU_MPU_STRUCT.ATT ================================================ */ +#define PROT_MPU_MPU_STRUCT_ATT_UR_Pos (0UL) /*!< PROT_MPU_MPU_STRUCT ATT: UR (Bit 0) */ +#define PROT_MPU_MPU_STRUCT_ATT_UR_Msk (0x1UL) /*!< PROT_MPU_MPU_STRUCT ATT: UR (Bitfield-Mask: 0x01) */ +#define PROT_MPU_MPU_STRUCT_ATT_UW_Pos (1UL) /*!< PROT_MPU_MPU_STRUCT ATT: UW (Bit 1) */ +#define PROT_MPU_MPU_STRUCT_ATT_UW_Msk (0x2UL) /*!< PROT_MPU_MPU_STRUCT ATT: UW (Bitfield-Mask: 0x01) */ +#define PROT_MPU_MPU_STRUCT_ATT_UX_Pos (2UL) /*!< PROT_MPU_MPU_STRUCT ATT: UX (Bit 2) */ +#define PROT_MPU_MPU_STRUCT_ATT_UX_Msk (0x4UL) /*!< PROT_MPU_MPU_STRUCT ATT: UX (Bitfield-Mask: 0x01) */ +#define PROT_MPU_MPU_STRUCT_ATT_PR_Pos (3UL) /*!< PROT_MPU_MPU_STRUCT ATT: PR (Bit 3) */ +#define PROT_MPU_MPU_STRUCT_ATT_PR_Msk (0x8UL) /*!< PROT_MPU_MPU_STRUCT ATT: PR (Bitfield-Mask: 0x01) */ +#define PROT_MPU_MPU_STRUCT_ATT_PW_Pos (4UL) /*!< PROT_MPU_MPU_STRUCT ATT: PW (Bit 4) */ +#define PROT_MPU_MPU_STRUCT_ATT_PW_Msk (0x10UL) /*!< PROT_MPU_MPU_STRUCT ATT: PW (Bitfield-Mask: 0x01) */ +#define PROT_MPU_MPU_STRUCT_ATT_PX_Pos (5UL) /*!< PROT_MPU_MPU_STRUCT ATT: PX (Bit 5) */ +#define PROT_MPU_MPU_STRUCT_ATT_PX_Msk (0x20UL) /*!< PROT_MPU_MPU_STRUCT ATT: PX (Bitfield-Mask: 0x01) */ +#define PROT_MPU_MPU_STRUCT_ATT_NS_Pos (6UL) /*!< PROT_MPU_MPU_STRUCT ATT: NS (Bit 6) */ +#define PROT_MPU_MPU_STRUCT_ATT_NS_Msk (0x40UL) /*!< PROT_MPU_MPU_STRUCT ATT: NS (Bitfield-Mask: 0x01) */ +#define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Pos (24UL) /*!< PROT_MPU_MPU_STRUCT ATT: REGION_SIZE (Bit 24) */ +#define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Msk (0x1f000000UL) /*!< PROT_MPU_MPU_STRUCT ATT: REGION_SIZE (Bitfield-Mask: 0x1f)*/ +#define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Pos (31UL) /*!< PROT_MPU_MPU_STRUCT ATT: ENABLED (Bit 31) */ +#define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Msk (0x80000000UL) /*!< PROT_MPU_MPU_STRUCT ATT: ENABLED (Bitfield-Mask: 0x01) */ + + +/* ==================================================== PROT_MPU.MS_CTL ==================================================== */ +#define PROT_MPU_MS_CTL_PC_Pos (0UL) /*!< PROT_MPU MS_CTL: PC (Bit 0) */ +#define PROT_MPU_MS_CTL_PC_Msk (0xfUL) /*!< PROT_MPU MS_CTL: PC (Bitfield-Mask: 0x0f) */ +#define PROT_MPU_MS_CTL_PC_SAVED_Pos (16UL) /*!< PROT_MPU MS_CTL: PC_SAVED (Bit 16) */ +#define PROT_MPU_MS_CTL_PC_SAVED_Msk (0xf0000UL) /*!< PROT_MPU MS_CTL: PC_SAVED (Bitfield-Mask: 0x0f) */ + + +#endif /* _CYIP_PROT_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_sar.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_sar.h new file mode 100644 index 0000000000..d07d89d564 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_sar.h @@ -0,0 +1,627 @@ +/***************************************************************************//** +* \file cyip_sar.h +* +* \brief +* SAR IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_SAR_H_ +#define _CYIP_SAR_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +#define SAR_SECTION_SIZE 0x00010000UL + +/** + * \brief SAR ADC with Sequencer (SAR) + */ +typedef struct { /*!< SAR Structure */ + __IOM uint32_t CTRL; /*!< 0x00000000 Analog control register. */ + __IOM uint32_t SAMPLE_CTRL; /*!< 0x00000004 Sample control register. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t SAMPLE_TIME01; /*!< 0x00000010 Sample time specification ST0 and ST1 */ + __IOM uint32_t SAMPLE_TIME23; /*!< 0x00000014 Sample time specification ST2 and ST3 */ + __IOM uint32_t RANGE_THRES; /*!< 0x00000018 Global range detect threshold register. */ + __IOM uint32_t RANGE_COND; /*!< 0x0000001C Global range detect mode register. */ + __IOM uint32_t CHAN_EN; /*!< 0x00000020 Enable bits for the channels */ + __IOM uint32_t START_CTRL; /*!< 0x00000024 Start control register (firmware trigger). */ + __IM uint32_t RESERVED1[22]; + __IOM uint32_t CHAN_CONFIG[16]; /*!< 0x00000080 Channel configuration register. */ + __IM uint32_t RESERVED2[16]; + __IM uint32_t CHAN_WORK[16]; /*!< 0x00000100 Channel working data register */ + __IM uint32_t RESERVED3[16]; + __IM uint32_t CHAN_RESULT[16]; /*!< 0x00000180 Channel result data register */ + __IM uint32_t RESERVED4[16]; + __IM uint32_t CHAN_WORK_UPDATED; /*!< 0x00000200 Channel working data register 'updated' bits */ + __IM uint32_t CHAN_RESULT_UPDATED; /*!< 0x00000204 Channel result data register 'updated' bits */ + __IM uint32_t CHAN_WORK_NEWVALUE; /*!< 0x00000208 Channel working data register 'new value' bits */ + __IM uint32_t CHAN_RESULT_NEWVALUE; /*!< 0x0000020C Channel result data register 'new value' bits */ + __IOM uint32_t INTR; /*!< 0x00000210 Interrupt request register. */ + __IOM uint32_t INTR_SET; /*!< 0x00000214 Interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000218 Interrupt mask register. */ + __IM uint32_t INTR_MASKED; /*!< 0x0000021C Interrupt masked request register */ + __IOM uint32_t SATURATE_INTR; /*!< 0x00000220 Saturate interrupt request register. */ + __IOM uint32_t SATURATE_INTR_SET; /*!< 0x00000224 Saturate interrupt set request register */ + __IOM uint32_t SATURATE_INTR_MASK; /*!< 0x00000228 Saturate interrupt mask register. */ + __IM uint32_t SATURATE_INTR_MASKED; /*!< 0x0000022C Saturate interrupt masked request register */ + __IOM uint32_t RANGE_INTR; /*!< 0x00000230 Range detect interrupt request register. */ + __IOM uint32_t RANGE_INTR_SET; /*!< 0x00000234 Range detect interrupt set request register */ + __IOM uint32_t RANGE_INTR_MASK; /*!< 0x00000238 Range detect interrupt mask register. */ + __IM uint32_t RANGE_INTR_MASKED; /*!< 0x0000023C Range interrupt masked request register */ + __IM uint32_t INTR_CAUSE; /*!< 0x00000240 Interrupt cause register */ + __IM uint32_t RESERVED5[15]; + __IOM uint32_t INJ_CHAN_CONFIG; /*!< 0x00000280 Injection channel configuration register. */ + __IM uint32_t RESERVED6[3]; + __IM uint32_t INJ_RESULT; /*!< 0x00000290 Injection channel result register */ + __IM uint32_t RESERVED7[3]; + __IM uint32_t STATUS; /*!< 0x000002A0 Current status of internal SAR registers (mostly for debug) */ + __IM uint32_t AVG_STAT; /*!< 0x000002A4 Current averaging status (for debug) */ + __IM uint32_t RESERVED8[22]; + __IOM uint32_t MUX_SWITCH0; /*!< 0x00000300 SARMUX Firmware switch controls */ + __IOM uint32_t MUX_SWITCH_CLEAR0; /*!< 0x00000304 SARMUX Firmware switch control clear */ + __IM uint32_t RESERVED9[14]; + __IOM uint32_t MUX_SWITCH_DS_CTRL; /*!< 0x00000340 SARMUX switch DSI control */ + __IOM uint32_t MUX_SWITCH_SQ_CTRL; /*!< 0x00000344 SARMUX switch Sar Sequencer control */ + __IM uint32_t MUX_SWITCH_STATUS; /*!< 0x00000348 SARMUX switch status */ + __IM uint32_t RESERVED10[749]; + __IOM uint32_t ANA_TRIM0; /*!< 0x00000F00 Analog trim register. */ + __IOM uint32_t ANA_TRIM1; /*!< 0x00000F04 Analog trim register. */ +} SAR_Type; /*!< Size = 3848 (0xF08) */ + + +/* ======================================================= SAR.CTRL ======================================================== */ +#define SAR_CTRL_PWR_CTRL_VREF_Pos (0UL) /*!< SAR CTRL: PWR_CTRL_VREF (Bit 0) */ +#define SAR_CTRL_PWR_CTRL_VREF_Msk (0x7UL) /*!< SAR CTRL: PWR_CTRL_VREF (Bitfield-Mask: 0x07) */ +#define SAR_CTRL_VREF_SEL_Pos (4UL) /*!< SAR CTRL: VREF_SEL (Bit 4) */ +#define SAR_CTRL_VREF_SEL_Msk (0x70UL) /*!< SAR CTRL: VREF_SEL (Bitfield-Mask: 0x07) */ +#define SAR_CTRL_VREF_BYP_CAP_EN_Pos (7UL) /*!< SAR CTRL: VREF_BYP_CAP_EN (Bit 7) */ +#define SAR_CTRL_VREF_BYP_CAP_EN_Msk (0x80UL) /*!< SAR CTRL: VREF_BYP_CAP_EN (Bitfield-Mask: 0x01) */ +#define SAR_CTRL_NEG_SEL_Pos (9UL) /*!< SAR CTRL: NEG_SEL (Bit 9) */ +#define SAR_CTRL_NEG_SEL_Msk (0xe00UL) /*!< SAR CTRL: NEG_SEL (Bitfield-Mask: 0x07) */ +#define SAR_CTRL_SAR_HW_CTRL_NEGVREF_Pos (13UL) /*!< SAR CTRL: SAR_HW_CTRL_NEGVREF (Bit 13) */ +#define SAR_CTRL_SAR_HW_CTRL_NEGVREF_Msk (0x2000UL) /*!< SAR CTRL: SAR_HW_CTRL_NEGVREF (Bitfield-Mask: 0x01) */ +#define SAR_CTRL_COMP_DLY_Pos (14UL) /*!< SAR CTRL: COMP_DLY (Bit 14) */ +#define SAR_CTRL_COMP_DLY_Msk (0xc000UL) /*!< SAR CTRL: COMP_DLY (Bitfield-Mask: 0x03) */ +#define SAR_CTRL_SPARE_Pos (16UL) /*!< SAR CTRL: SPARE (Bit 16) */ +#define SAR_CTRL_SPARE_Msk (0xf0000UL) /*!< SAR CTRL: SPARE (Bitfield-Mask: 0x0f) */ +#define SAR_CTRL_BOOSTPUMP_EN_Pos (20UL) /*!< SAR CTRL: BOOSTPUMP_EN (Bit 20) */ +#define SAR_CTRL_BOOSTPUMP_EN_Msk (0x100000UL) /*!< SAR CTRL: BOOSTPUMP_EN (Bitfield-Mask: 0x01) */ +#define SAR_CTRL_REFBUF_EN_Pos (21UL) /*!< SAR CTRL: REFBUF_EN (Bit 21) */ +#define SAR_CTRL_REFBUF_EN_Msk (0x200000UL) /*!< SAR CTRL: REFBUF_EN (Bitfield-Mask: 0x01) */ +#define SAR_CTRL_COMP_PWR_Pos (24UL) /*!< SAR CTRL: COMP_PWR (Bit 24) */ +#define SAR_CTRL_COMP_PWR_Msk (0x7000000UL) /*!< SAR CTRL: COMP_PWR (Bitfield-Mask: 0x07) */ +#define SAR_CTRL_DEEPSLEEP_ON_Pos (27UL) /*!< SAR CTRL: DEEPSLEEP_ON (Bit 27) */ +#define SAR_CTRL_DEEPSLEEP_ON_Msk (0x8000000UL) /*!< SAR CTRL: DEEPSLEEP_ON (Bitfield-Mask: 0x01) */ +#define SAR_CTRL_DSI_SYNC_CONFIG_Pos (28UL) /*!< SAR CTRL: DSI_SYNC_CONFIG (Bit 28) */ +#define SAR_CTRL_DSI_SYNC_CONFIG_Msk (0x10000000UL) /*!< SAR CTRL: DSI_SYNC_CONFIG (Bitfield-Mask: 0x01) */ +#define SAR_CTRL_DSI_MODE_Pos (29UL) /*!< SAR CTRL: DSI_MODE (Bit 29) */ +#define SAR_CTRL_DSI_MODE_Msk (0x20000000UL) /*!< SAR CTRL: DSI_MODE (Bitfield-Mask: 0x01) */ +#define SAR_CTRL_SWITCH_DISABLE_Pos (30UL) /*!< SAR CTRL: SWITCH_DISABLE (Bit 30) */ +#define SAR_CTRL_SWITCH_DISABLE_Msk (0x40000000UL) /*!< SAR CTRL: SWITCH_DISABLE (Bitfield-Mask: 0x01) */ +#define SAR_CTRL_ENABLED_Pos (31UL) /*!< SAR CTRL: ENABLED (Bit 31) */ +#define SAR_CTRL_ENABLED_Msk (0x80000000UL) /*!< SAR CTRL: ENABLED (Bitfield-Mask: 0x01) */ +/* ==================================================== SAR.SAMPLE_CTRL ==================================================== */ +#define SAR_SAMPLE_CTRL_LEFT_ALIGN_Pos (1UL) /*!< SAR SAMPLE_CTRL: LEFT_ALIGN (Bit 1) */ +#define SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk (0x2UL) /*!< SAR SAMPLE_CTRL: LEFT_ALIGN (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos (2UL) /*!< SAR SAMPLE_CTRL: SINGLE_ENDED_SIGNED (Bit 2) */ +#define SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk (0x4UL) /*!< SAR SAMPLE_CTRL: SINGLE_ENDED_SIGNED (Bitfield-Mask: 0x01)*/ +#define SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos (3UL) /*!< SAR SAMPLE_CTRL: DIFFERENTIAL_SIGNED (Bit 3) */ +#define SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk (0x8UL) /*!< SAR SAMPLE_CTRL: DIFFERENTIAL_SIGNED (Bitfield-Mask: 0x01)*/ +#define SAR_SAMPLE_CTRL_AVG_CNT_Pos (4UL) /*!< SAR SAMPLE_CTRL: AVG_CNT (Bit 4) */ +#define SAR_SAMPLE_CTRL_AVG_CNT_Msk (0x70UL) /*!< SAR SAMPLE_CTRL: AVG_CNT (Bitfield-Mask: 0x07) */ +#define SAR_SAMPLE_CTRL_AVG_SHIFT_Pos (7UL) /*!< SAR SAMPLE_CTRL: AVG_SHIFT (Bit 7) */ +#define SAR_SAMPLE_CTRL_AVG_SHIFT_Msk (0x80UL) /*!< SAR SAMPLE_CTRL: AVG_SHIFT (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_AVG_MODE_Pos (8UL) /*!< SAR SAMPLE_CTRL: AVG_MODE (Bit 8) */ +#define SAR_SAMPLE_CTRL_AVG_MODE_Msk (0x100UL) /*!< SAR SAMPLE_CTRL: AVG_MODE (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_CONTINUOUS_Pos (16UL) /*!< SAR SAMPLE_CTRL: CONTINUOUS (Bit 16) */ +#define SAR_SAMPLE_CTRL_CONTINUOUS_Msk (0x10000UL) /*!< SAR SAMPLE_CTRL: CONTINUOUS (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Pos (17UL) /*!< SAR SAMPLE_CTRL: DSI_TRIGGER_EN (Bit 17) */ +#define SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk (0x20000UL) /*!< SAR SAMPLE_CTRL: DSI_TRIGGER_EN (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Pos (18UL) /*!< SAR SAMPLE_CTRL: DSI_TRIGGER_LEVEL (Bit 18) */ +#define SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk (0x40000UL) /*!< SAR SAMPLE_CTRL: DSI_TRIGGER_LEVEL (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Pos (19UL) /*!< SAR SAMPLE_CTRL: DSI_SYNC_TRIGGER (Bit 19) */ +#define SAR_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Msk (0x80000UL) /*!< SAR SAMPLE_CTRL: DSI_SYNC_TRIGGER (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_UAB_SCAN_MODE_Pos (22UL) /*!< SAR SAMPLE_CTRL: UAB_SCAN_MODE (Bit 22) */ +#define SAR_SAMPLE_CTRL_UAB_SCAN_MODE_Msk (0x400000UL) /*!< SAR SAMPLE_CTRL: UAB_SCAN_MODE (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_REPEAT_INVALID_Pos (23UL) /*!< SAR SAMPLE_CTRL: REPEAT_INVALID (Bit 23) */ +#define SAR_SAMPLE_CTRL_REPEAT_INVALID_Msk (0x800000UL) /*!< SAR SAMPLE_CTRL: REPEAT_INVALID (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_VALID_SEL_Pos (24UL) /*!< SAR SAMPLE_CTRL: VALID_SEL (Bit 24) */ +#define SAR_SAMPLE_CTRL_VALID_SEL_Msk (0x7000000UL) /*!< SAR SAMPLE_CTRL: VALID_SEL (Bitfield-Mask: 0x07) */ +#define SAR_SAMPLE_CTRL_VALID_SEL_EN_Pos (27UL) /*!< SAR SAMPLE_CTRL: VALID_SEL_EN (Bit 27) */ +#define SAR_SAMPLE_CTRL_VALID_SEL_EN_Msk (0x8000000UL) /*!< SAR SAMPLE_CTRL: VALID_SEL_EN (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_VALID_IGNORE_Pos (28UL) /*!< SAR SAMPLE_CTRL: VALID_IGNORE (Bit 28) */ +#define SAR_SAMPLE_CTRL_VALID_IGNORE_Msk (0x10000000UL) /*!< SAR SAMPLE_CTRL: VALID_IGNORE (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_TRIGGER_OUT_EN_Pos (30UL) /*!< SAR SAMPLE_CTRL: TRIGGER_OUT_EN (Bit 30) */ +#define SAR_SAMPLE_CTRL_TRIGGER_OUT_EN_Msk (0x40000000UL) /*!< SAR SAMPLE_CTRL: TRIGGER_OUT_EN (Bitfield-Mask: 0x01) */ +#define SAR_SAMPLE_CTRL_EOS_DSI_OUT_EN_Pos (31UL) /*!< SAR SAMPLE_CTRL: EOS_DSI_OUT_EN (Bit 31) */ +#define SAR_SAMPLE_CTRL_EOS_DSI_OUT_EN_Msk (0x80000000UL) /*!< SAR SAMPLE_CTRL: EOS_DSI_OUT_EN (Bitfield-Mask: 0x01) */ +/* =================================================== SAR.SAMPLE_TIME01 =================================================== */ +#define SAR_SAMPLE_TIME01_SAMPLE_TIME0_Pos (0UL) /*!< SAR SAMPLE_TIME01: SAMPLE_TIME0 (Bit 0) */ +#define SAR_SAMPLE_TIME01_SAMPLE_TIME0_Msk (0x3ffUL) /*!< SAR SAMPLE_TIME01: SAMPLE_TIME0 (Bitfield-Mask: 0x3ff) */ +#define SAR_SAMPLE_TIME01_SAMPLE_TIME1_Pos (16UL) /*!< SAR SAMPLE_TIME01: SAMPLE_TIME1 (Bit 16) */ +#define SAR_SAMPLE_TIME01_SAMPLE_TIME1_Msk (0x3ff0000UL) /*!< SAR SAMPLE_TIME01: SAMPLE_TIME1 (Bitfield-Mask: 0x3ff) */ +/* =================================================== SAR.SAMPLE_TIME23 =================================================== */ +#define SAR_SAMPLE_TIME23_SAMPLE_TIME2_Pos (0UL) /*!< SAR SAMPLE_TIME23: SAMPLE_TIME2 (Bit 0) */ +#define SAR_SAMPLE_TIME23_SAMPLE_TIME2_Msk (0x3ffUL) /*!< SAR SAMPLE_TIME23: SAMPLE_TIME2 (Bitfield-Mask: 0x3ff) */ +#define SAR_SAMPLE_TIME23_SAMPLE_TIME3_Pos (16UL) /*!< SAR SAMPLE_TIME23: SAMPLE_TIME3 (Bit 16) */ +#define SAR_SAMPLE_TIME23_SAMPLE_TIME3_Msk (0x3ff0000UL) /*!< SAR SAMPLE_TIME23: SAMPLE_TIME3 (Bitfield-Mask: 0x3ff) */ +/* ==================================================== SAR.RANGE_THRES ==================================================== */ +#define SAR_RANGE_THRES_RANGE_LOW_Pos (0UL) /*!< SAR RANGE_THRES: RANGE_LOW (Bit 0) */ +#define SAR_RANGE_THRES_RANGE_LOW_Msk (0xffffUL) /*!< SAR RANGE_THRES: RANGE_LOW (Bitfield-Mask: 0xffff) */ +#define SAR_RANGE_THRES_RANGE_HIGH_Pos (16UL) /*!< SAR RANGE_THRES: RANGE_HIGH (Bit 16) */ +#define SAR_RANGE_THRES_RANGE_HIGH_Msk (0xffff0000UL) /*!< SAR RANGE_THRES: RANGE_HIGH (Bitfield-Mask: 0xffff) */ +/* ==================================================== SAR.RANGE_COND ===================================================== */ +#define SAR_RANGE_COND_RANGE_COND_Pos (30UL) /*!< SAR RANGE_COND: RANGE_COND (Bit 30) */ +#define SAR_RANGE_COND_RANGE_COND_Msk (0xc0000000UL) /*!< SAR RANGE_COND: RANGE_COND (Bitfield-Mask: 0x03) */ +/* ====================================================== SAR.CHAN_EN ====================================================== */ +#define SAR_CHAN_EN_CHAN_EN_Pos (0UL) /*!< SAR CHAN_EN: CHAN_EN (Bit 0) */ +#define SAR_CHAN_EN_CHAN_EN_Msk (0xffffUL) /*!< SAR CHAN_EN: CHAN_EN (Bitfield-Mask: 0xffff) */ +/* ==================================================== SAR.START_CTRL ===================================================== */ +#define SAR_START_CTRL_FW_TRIGGER_Pos (0UL) /*!< SAR START_CTRL: FW_TRIGGER (Bit 0) */ +#define SAR_START_CTRL_FW_TRIGGER_Msk (0x1UL) /*!< SAR START_CTRL: FW_TRIGGER (Bitfield-Mask: 0x01) */ +/* ==================================================== SAR.CHAN_CONFIG ==================================================== */ +#define SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos (0UL) /*!< SAR CHAN_CONFIG: POS_PIN_ADDR (Bit 0) */ +#define SAR_CHAN_CONFIG_POS_PIN_ADDR_Msk (0x7UL) /*!< SAR CHAN_CONFIG: POS_PIN_ADDR (Bitfield-Mask: 0x07) */ +#define SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos (4UL) /*!< SAR CHAN_CONFIG: POS_PORT_ADDR (Bit 4) */ +#define SAR_CHAN_CONFIG_POS_PORT_ADDR_Msk (0x70UL) /*!< SAR CHAN_CONFIG: POS_PORT_ADDR (Bitfield-Mask: 0x07) */ +#define SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Pos (8UL) /*!< SAR CHAN_CONFIG: DIFFERENTIAL_EN (Bit 8) */ +#define SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Msk (0x100UL) /*!< SAR CHAN_CONFIG: DIFFERENTIAL_EN (Bitfield-Mask: 0x01) */ +#define SAR_CHAN_CONFIG_AVG_EN_Pos (10UL) /*!< SAR CHAN_CONFIG: AVG_EN (Bit 10) */ +#define SAR_CHAN_CONFIG_AVG_EN_Msk (0x400UL) /*!< SAR CHAN_CONFIG: AVG_EN (Bitfield-Mask: 0x01) */ +#define SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos (12UL) /*!< SAR CHAN_CONFIG: SAMPLE_TIME_SEL (Bit 12) */ +#define SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Msk (0x3000UL) /*!< SAR CHAN_CONFIG: SAMPLE_TIME_SEL (Bitfield-Mask: 0x03) */ +#define SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos (16UL) /*!< SAR CHAN_CONFIG: NEG_PIN_ADDR (Bit 16) */ +#define SAR_CHAN_CONFIG_NEG_PIN_ADDR_Msk (0x70000UL) /*!< SAR CHAN_CONFIG: NEG_PIN_ADDR (Bitfield-Mask: 0x07) */ +#define SAR_CHAN_CONFIG_NEG_PORT_ADDR_Pos (20UL) /*!< SAR CHAN_CONFIG: NEG_PORT_ADDR (Bit 20) */ +#define SAR_CHAN_CONFIG_NEG_PORT_ADDR_Msk (0x700000UL) /*!< SAR CHAN_CONFIG: NEG_PORT_ADDR (Bitfield-Mask: 0x07) */ +#define SAR_CHAN_CONFIG_NEG_ADDR_EN_Pos (24UL) /*!< SAR CHAN_CONFIG: NEG_ADDR_EN (Bit 24) */ +#define SAR_CHAN_CONFIG_NEG_ADDR_EN_Msk (0x1000000UL) /*!< SAR CHAN_CONFIG: NEG_ADDR_EN (Bitfield-Mask: 0x01) */ +#define SAR_CHAN_CONFIG_DSI_OUT_EN_Pos (31UL) /*!< SAR CHAN_CONFIG: DSI_OUT_EN (Bit 31) */ +#define SAR_CHAN_CONFIG_DSI_OUT_EN_Msk (0x80000000UL) /*!< SAR CHAN_CONFIG: DSI_OUT_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== SAR.CHAN_WORK ===================================================== */ +#define SAR_CHAN_WORK_WORK_Pos (0UL) /*!< SAR CHAN_WORK: WORK (Bit 0) */ +#define SAR_CHAN_WORK_WORK_Msk (0xffffUL) /*!< SAR CHAN_WORK: WORK (Bitfield-Mask: 0xffff) */ +#define SAR_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Pos (27UL) /*!< SAR CHAN_WORK: CHAN_WORK_NEWVALUE_MIR (Bit 27) */ +#define SAR_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Msk (0x8000000UL) /*!< SAR CHAN_WORK: CHAN_WORK_NEWVALUE_MIR (Bitfield-Mask: 0x01)*/ +#define SAR_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Pos (31UL) /*!< SAR CHAN_WORK: CHAN_WORK_UPDATED_MIR (Bit 31) */ +#define SAR_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Msk (0x80000000UL) /*!< SAR CHAN_WORK: CHAN_WORK_UPDATED_MIR (Bitfield-Mask: 0x01)*/ +/* ==================================================== SAR.CHAN_RESULT ==================================================== */ +#define SAR_CHAN_RESULT_RESULT_Pos (0UL) /*!< SAR CHAN_RESULT: RESULT (Bit 0) */ +#define SAR_CHAN_RESULT_RESULT_Msk (0xffffUL) /*!< SAR CHAN_RESULT: RESULT (Bitfield-Mask: 0xffff) */ +#define SAR_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Pos (27UL) /*!< SAR CHAN_RESULT: CHAN_RESULT_NEWVALUE_MIR (Bit 27) */ +#define SAR_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Msk (0x8000000UL) /*!< SAR CHAN_RESULT: CHAN_RESULT_NEWVALUE_MIR (Bitfield-Mask: 0x01)*/ +#define SAR_CHAN_RESULT_SATURATE_INTR_MIR_Pos (29UL) /*!< SAR CHAN_RESULT: SATURATE_INTR_MIR (Bit 29) */ +#define SAR_CHAN_RESULT_SATURATE_INTR_MIR_Msk (0x20000000UL) /*!< SAR CHAN_RESULT: SATURATE_INTR_MIR (Bitfield-Mask: 0x01) */ +#define SAR_CHAN_RESULT_RANGE_INTR_MIR_Pos (30UL) /*!< SAR CHAN_RESULT: RANGE_INTR_MIR (Bit 30) */ +#define SAR_CHAN_RESULT_RANGE_INTR_MIR_Msk (0x40000000UL) /*!< SAR CHAN_RESULT: RANGE_INTR_MIR (Bitfield-Mask: 0x01) */ +#define SAR_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Pos (31UL) /*!< SAR CHAN_RESULT: CHAN_RESULT_UPDATED_MIR (Bit 31) */ +#define SAR_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Msk (0x80000000UL) /*!< SAR CHAN_RESULT: CHAN_RESULT_UPDATED_MIR (Bitfield-Mask: 0x01)*/ +/* ================================================= SAR.CHAN_WORK_UPDATED ================================================= */ +#define SAR_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Pos (0UL) /*!< SAR CHAN_WORK_UPDATED: CHAN_WORK_UPDATED (Bit 0) */ +#define SAR_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Msk (0xffffUL) /*!< SAR CHAN_WORK_UPDATED: CHAN_WORK_UPDATED (Bitfield-Mask: 0xffff)*/ +/* ================================================ SAR.CHAN_RESULT_UPDATED ================================================ */ +#define SAR_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Pos (0UL) /*!< SAR CHAN_RESULT_UPDATED: CHAN_RESULT_UPDATED (Bit 0) */ +#define SAR_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Msk (0xffffUL) /*!< SAR CHAN_RESULT_UPDATED: CHAN_RESULT_UPDATED (Bitfield-Mask: 0xffff)*/ +/* ================================================ SAR.CHAN_WORK_NEWVALUE ================================================= */ +#define SAR_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Pos (0UL) /*!< SAR CHAN_WORK_NEWVALUE: CHAN_WORK_NEWVALUE (Bit 0) */ +#define SAR_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Msk (0xffffUL) /*!< SAR CHAN_WORK_NEWVALUE: CHAN_WORK_NEWVALUE (Bitfield-Mask: 0xffff)*/ +/* =============================================== SAR.CHAN_RESULT_NEWVALUE ================================================ */ +#define SAR_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Pos (0UL) /*!< SAR CHAN_RESULT_NEWVALUE: CHAN_RESULT_NEWVALUE (Bit 0) */ +#define SAR_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Msk (0xffffUL) /*!< SAR CHAN_RESULT_NEWVALUE: CHAN_RESULT_NEWVALUE (Bitfield-Mask: 0xffff)*/ +/* ======================================================= SAR.INTR ======================================================== */ +#define SAR_INTR_EOS_INTR_Pos (0UL) /*!< SAR INTR: EOS_INTR (Bit 0) */ +#define SAR_INTR_EOS_INTR_Msk (0x1UL) /*!< SAR INTR: EOS_INTR (Bitfield-Mask: 0x01) */ +#define SAR_INTR_OVERFLOW_INTR_Pos (1UL) /*!< SAR INTR: OVERFLOW_INTR (Bit 1) */ +#define SAR_INTR_OVERFLOW_INTR_Msk (0x2UL) /*!< SAR INTR: OVERFLOW_INTR (Bitfield-Mask: 0x01) */ +#define SAR_INTR_FW_COLLISION_INTR_Pos (2UL) /*!< SAR INTR: FW_COLLISION_INTR (Bit 2) */ +#define SAR_INTR_FW_COLLISION_INTR_Msk (0x4UL) /*!< SAR INTR: FW_COLLISION_INTR (Bitfield-Mask: 0x01) */ +#define SAR_INTR_DSI_COLLISION_INTR_Pos (3UL) /*!< SAR INTR: DSI_COLLISION_INTR (Bit 3) */ +#define SAR_INTR_DSI_COLLISION_INTR_Msk (0x8UL) /*!< SAR INTR: DSI_COLLISION_INTR (Bitfield-Mask: 0x01) */ +#define SAR_INTR_INJ_EOC_INTR_Pos (4UL) /*!< SAR INTR: INJ_EOC_INTR (Bit 4) */ +#define SAR_INTR_INJ_EOC_INTR_Msk (0x10UL) /*!< SAR INTR: INJ_EOC_INTR (Bitfield-Mask: 0x01) */ +#define SAR_INTR_INJ_SATURATE_INTR_Pos (5UL) /*!< SAR INTR: INJ_SATURATE_INTR (Bit 5) */ +#define SAR_INTR_INJ_SATURATE_INTR_Msk (0x20UL) /*!< SAR INTR: INJ_SATURATE_INTR (Bitfield-Mask: 0x01) */ +#define SAR_INTR_INJ_RANGE_INTR_Pos (6UL) /*!< SAR INTR: INJ_RANGE_INTR (Bit 6) */ +#define SAR_INTR_INJ_RANGE_INTR_Msk (0x40UL) /*!< SAR INTR: INJ_RANGE_INTR (Bitfield-Mask: 0x01) */ +#define SAR_INTR_INJ_COLLISION_INTR_Pos (7UL) /*!< SAR INTR: INJ_COLLISION_INTR (Bit 7) */ +#define SAR_INTR_INJ_COLLISION_INTR_Msk (0x80UL) /*!< SAR INTR: INJ_COLLISION_INTR (Bitfield-Mask: 0x01) */ +/* ===================================================== SAR.INTR_SET ====================================================== */ +#define SAR_INTR_SET_EOS_SET_Pos (0UL) /*!< SAR INTR_SET: EOS_SET (Bit 0) */ +#define SAR_INTR_SET_EOS_SET_Msk (0x1UL) /*!< SAR INTR_SET: EOS_SET (Bitfield-Mask: 0x01) */ +#define SAR_INTR_SET_OVERFLOW_SET_Pos (1UL) /*!< SAR INTR_SET: OVERFLOW_SET (Bit 1) */ +#define SAR_INTR_SET_OVERFLOW_SET_Msk (0x2UL) /*!< SAR INTR_SET: OVERFLOW_SET (Bitfield-Mask: 0x01) */ +#define SAR_INTR_SET_FW_COLLISION_SET_Pos (2UL) /*!< SAR INTR_SET: FW_COLLISION_SET (Bit 2) */ +#define SAR_INTR_SET_FW_COLLISION_SET_Msk (0x4UL) /*!< SAR INTR_SET: FW_COLLISION_SET (Bitfield-Mask: 0x01) */ +#define SAR_INTR_SET_DSI_COLLISION_SET_Pos (3UL) /*!< SAR INTR_SET: DSI_COLLISION_SET (Bit 3) */ +#define SAR_INTR_SET_DSI_COLLISION_SET_Msk (0x8UL) /*!< SAR INTR_SET: DSI_COLLISION_SET (Bitfield-Mask: 0x01) */ +#define SAR_INTR_SET_INJ_EOC_SET_Pos (4UL) /*!< SAR INTR_SET: INJ_EOC_SET (Bit 4) */ +#define SAR_INTR_SET_INJ_EOC_SET_Msk (0x10UL) /*!< SAR INTR_SET: INJ_EOC_SET (Bitfield-Mask: 0x01) */ +#define SAR_INTR_SET_INJ_SATURATE_SET_Pos (5UL) /*!< SAR INTR_SET: INJ_SATURATE_SET (Bit 5) */ +#define SAR_INTR_SET_INJ_SATURATE_SET_Msk (0x20UL) /*!< SAR INTR_SET: INJ_SATURATE_SET (Bitfield-Mask: 0x01) */ +#define SAR_INTR_SET_INJ_RANGE_SET_Pos (6UL) /*!< SAR INTR_SET: INJ_RANGE_SET (Bit 6) */ +#define SAR_INTR_SET_INJ_RANGE_SET_Msk (0x40UL) /*!< SAR INTR_SET: INJ_RANGE_SET (Bitfield-Mask: 0x01) */ +#define SAR_INTR_SET_INJ_COLLISION_SET_Pos (7UL) /*!< SAR INTR_SET: INJ_COLLISION_SET (Bit 7) */ +#define SAR_INTR_SET_INJ_COLLISION_SET_Msk (0x80UL) /*!< SAR INTR_SET: INJ_COLLISION_SET (Bitfield-Mask: 0x01) */ +/* ===================================================== SAR.INTR_MASK ===================================================== */ +#define SAR_INTR_MASK_EOS_MASK_Pos (0UL) /*!< SAR INTR_MASK: EOS_MASK (Bit 0) */ +#define SAR_INTR_MASK_EOS_MASK_Msk (0x1UL) /*!< SAR INTR_MASK: EOS_MASK (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASK_OVERFLOW_MASK_Pos (1UL) /*!< SAR INTR_MASK: OVERFLOW_MASK (Bit 1) */ +#define SAR_INTR_MASK_OVERFLOW_MASK_Msk (0x2UL) /*!< SAR INTR_MASK: OVERFLOW_MASK (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASK_FW_COLLISION_MASK_Pos (2UL) /*!< SAR INTR_MASK: FW_COLLISION_MASK (Bit 2) */ +#define SAR_INTR_MASK_FW_COLLISION_MASK_Msk (0x4UL) /*!< SAR INTR_MASK: FW_COLLISION_MASK (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASK_DSI_COLLISION_MASK_Pos (3UL) /*!< SAR INTR_MASK: DSI_COLLISION_MASK (Bit 3) */ +#define SAR_INTR_MASK_DSI_COLLISION_MASK_Msk (0x8UL) /*!< SAR INTR_MASK: DSI_COLLISION_MASK (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASK_INJ_EOC_MASK_Pos (4UL) /*!< SAR INTR_MASK: INJ_EOC_MASK (Bit 4) */ +#define SAR_INTR_MASK_INJ_EOC_MASK_Msk (0x10UL) /*!< SAR INTR_MASK: INJ_EOC_MASK (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASK_INJ_SATURATE_MASK_Pos (5UL) /*!< SAR INTR_MASK: INJ_SATURATE_MASK (Bit 5) */ +#define SAR_INTR_MASK_INJ_SATURATE_MASK_Msk (0x20UL) /*!< SAR INTR_MASK: INJ_SATURATE_MASK (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASK_INJ_RANGE_MASK_Pos (6UL) /*!< SAR INTR_MASK: INJ_RANGE_MASK (Bit 6) */ +#define SAR_INTR_MASK_INJ_RANGE_MASK_Msk (0x40UL) /*!< SAR INTR_MASK: INJ_RANGE_MASK (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASK_INJ_COLLISION_MASK_Pos (7UL) /*!< SAR INTR_MASK: INJ_COLLISION_MASK (Bit 7) */ +#define SAR_INTR_MASK_INJ_COLLISION_MASK_Msk (0x80UL) /*!< SAR INTR_MASK: INJ_COLLISION_MASK (Bitfield-Mask: 0x01) */ +/* ==================================================== SAR.INTR_MASKED ==================================================== */ +#define SAR_INTR_MASKED_EOS_MASKED_Pos (0UL) /*!< SAR INTR_MASKED: EOS_MASKED (Bit 0) */ +#define SAR_INTR_MASKED_EOS_MASKED_Msk (0x1UL) /*!< SAR INTR_MASKED: EOS_MASKED (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASKED_OVERFLOW_MASKED_Pos (1UL) /*!< SAR INTR_MASKED: OVERFLOW_MASKED (Bit 1) */ +#define SAR_INTR_MASKED_OVERFLOW_MASKED_Msk (0x2UL) /*!< SAR INTR_MASKED: OVERFLOW_MASKED (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASKED_FW_COLLISION_MASKED_Pos (2UL) /*!< SAR INTR_MASKED: FW_COLLISION_MASKED (Bit 2) */ +#define SAR_INTR_MASKED_FW_COLLISION_MASKED_Msk (0x4UL) /*!< SAR INTR_MASKED: FW_COLLISION_MASKED (Bitfield-Mask: 0x01)*/ +#define SAR_INTR_MASKED_DSI_COLLISION_MASKED_Pos (3UL) /*!< SAR INTR_MASKED: DSI_COLLISION_MASKED (Bit 3) */ +#define SAR_INTR_MASKED_DSI_COLLISION_MASKED_Msk (0x8UL) /*!< SAR INTR_MASKED: DSI_COLLISION_MASKED (Bitfield-Mask: 0x01)*/ +#define SAR_INTR_MASKED_INJ_EOC_MASKED_Pos (4UL) /*!< SAR INTR_MASKED: INJ_EOC_MASKED (Bit 4) */ +#define SAR_INTR_MASKED_INJ_EOC_MASKED_Msk (0x10UL) /*!< SAR INTR_MASKED: INJ_EOC_MASKED (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASKED_INJ_SATURATE_MASKED_Pos (5UL) /*!< SAR INTR_MASKED: INJ_SATURATE_MASKED (Bit 5) */ +#define SAR_INTR_MASKED_INJ_SATURATE_MASKED_Msk (0x20UL) /*!< SAR INTR_MASKED: INJ_SATURATE_MASKED (Bitfield-Mask: 0x01)*/ +#define SAR_INTR_MASKED_INJ_RANGE_MASKED_Pos (6UL) /*!< SAR INTR_MASKED: INJ_RANGE_MASKED (Bit 6) */ +#define SAR_INTR_MASKED_INJ_RANGE_MASKED_Msk (0x40UL) /*!< SAR INTR_MASKED: INJ_RANGE_MASKED (Bitfield-Mask: 0x01) */ +#define SAR_INTR_MASKED_INJ_COLLISION_MASKED_Pos (7UL) /*!< SAR INTR_MASKED: INJ_COLLISION_MASKED (Bit 7) */ +#define SAR_INTR_MASKED_INJ_COLLISION_MASKED_Msk (0x80UL) /*!< SAR INTR_MASKED: INJ_COLLISION_MASKED (Bitfield-Mask: 0x01)*/ +/* =================================================== SAR.SATURATE_INTR =================================================== */ +#define SAR_SATURATE_INTR_SATURATE_INTR_Pos (0UL) /*!< SAR SATURATE_INTR: SATURATE_INTR (Bit 0) */ +#define SAR_SATURATE_INTR_SATURATE_INTR_Msk (0xffffUL) /*!< SAR SATURATE_INTR: SATURATE_INTR (Bitfield-Mask: 0xffff) */ +/* ================================================= SAR.SATURATE_INTR_SET ================================================= */ +#define SAR_SATURATE_INTR_SET_SATURATE_SET_Pos (0UL) /*!< SAR SATURATE_INTR_SET: SATURATE_SET (Bit 0) */ +#define SAR_SATURATE_INTR_SET_SATURATE_SET_Msk (0xffffUL) /*!< SAR SATURATE_INTR_SET: SATURATE_SET (Bitfield-Mask: 0xffff)*/ +/* ================================================ SAR.SATURATE_INTR_MASK ================================================= */ +#define SAR_SATURATE_INTR_MASK_SATURATE_MASK_Pos (0UL) /*!< SAR SATURATE_INTR_MASK: SATURATE_MASK (Bit 0) */ +#define SAR_SATURATE_INTR_MASK_SATURATE_MASK_Msk (0xffffUL) /*!< SAR SATURATE_INTR_MASK: SATURATE_MASK (Bitfield-Mask: 0xffff)*/ +/* =============================================== SAR.SATURATE_INTR_MASKED ================================================ */ +#define SAR_SATURATE_INTR_MASKED_SATURATE_MASKED_Pos (0UL) /*!< SAR SATURATE_INTR_MASKED: SATURATE_MASKED (Bit 0) */ +#define SAR_SATURATE_INTR_MASKED_SATURATE_MASKED_Msk (0xffffUL) /*!< SAR SATURATE_INTR_MASKED: SATURATE_MASKED (Bitfield-Mask: 0xffff)*/ +/* ==================================================== SAR.RANGE_INTR ===================================================== */ +#define SAR_RANGE_INTR_RANGE_INTR_Pos (0UL) /*!< SAR RANGE_INTR: RANGE_INTR (Bit 0) */ +#define SAR_RANGE_INTR_RANGE_INTR_Msk (0xffffUL) /*!< SAR RANGE_INTR: RANGE_INTR (Bitfield-Mask: 0xffff) */ +/* ================================================== SAR.RANGE_INTR_SET =================================================== */ +#define SAR_RANGE_INTR_SET_RANGE_SET_Pos (0UL) /*!< SAR RANGE_INTR_SET: RANGE_SET (Bit 0) */ +#define SAR_RANGE_INTR_SET_RANGE_SET_Msk (0xffffUL) /*!< SAR RANGE_INTR_SET: RANGE_SET (Bitfield-Mask: 0xffff) */ +/* ================================================== SAR.RANGE_INTR_MASK ================================================== */ +#define SAR_RANGE_INTR_MASK_RANGE_MASK_Pos (0UL) /*!< SAR RANGE_INTR_MASK: RANGE_MASK (Bit 0) */ +#define SAR_RANGE_INTR_MASK_RANGE_MASK_Msk (0xffffUL) /*!< SAR RANGE_INTR_MASK: RANGE_MASK (Bitfield-Mask: 0xffff) */ +/* ================================================= SAR.RANGE_INTR_MASKED ================================================= */ +#define SAR_RANGE_INTR_MASKED_RANGE_MASKED_Pos (0UL) /*!< SAR RANGE_INTR_MASKED: RANGE_MASKED (Bit 0) */ +#define SAR_RANGE_INTR_MASKED_RANGE_MASKED_Msk (0xffffUL) /*!< SAR RANGE_INTR_MASKED: RANGE_MASKED (Bitfield-Mask: 0xffff)*/ +/* ==================================================== SAR.INTR_CAUSE ===================================================== */ +#define SAR_INTR_CAUSE_EOS_MASKED_MIR_Pos (0UL) /*!< SAR INTR_CAUSE: EOS_MASKED_MIR (Bit 0) */ +#define SAR_INTR_CAUSE_EOS_MASKED_MIR_Msk (0x1UL) /*!< SAR INTR_CAUSE: EOS_MASKED_MIR (Bitfield-Mask: 0x01) */ +#define SAR_INTR_CAUSE_OVERFLOW_MASKED_MIR_Pos (1UL) /*!< SAR INTR_CAUSE: OVERFLOW_MASKED_MIR (Bit 1) */ +#define SAR_INTR_CAUSE_OVERFLOW_MASKED_MIR_Msk (0x2UL) /*!< SAR INTR_CAUSE: OVERFLOW_MASKED_MIR (Bitfield-Mask: 0x01) */ +#define SAR_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Pos (2UL) /*!< SAR INTR_CAUSE: FW_COLLISION_MASKED_MIR (Bit 2) */ +#define SAR_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Msk (0x4UL) /*!< SAR INTR_CAUSE: FW_COLLISION_MASKED_MIR (Bitfield-Mask: 0x01)*/ +#define SAR_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Pos (3UL) /*!< SAR INTR_CAUSE: DSI_COLLISION_MASKED_MIR (Bit 3) */ +#define SAR_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Msk (0x8UL) /*!< SAR INTR_CAUSE: DSI_COLLISION_MASKED_MIR (Bitfield-Mask: 0x01)*/ +#define SAR_INTR_CAUSE_INJ_EOC_MASKED_MIR_Pos (4UL) /*!< SAR INTR_CAUSE: INJ_EOC_MASKED_MIR (Bit 4) */ +#define SAR_INTR_CAUSE_INJ_EOC_MASKED_MIR_Msk (0x10UL) /*!< SAR INTR_CAUSE: INJ_EOC_MASKED_MIR (Bitfield-Mask: 0x01) */ +#define SAR_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Pos (5UL) /*!< SAR INTR_CAUSE: INJ_SATURATE_MASKED_MIR (Bit 5) */ +#define SAR_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Msk (0x20UL) /*!< SAR INTR_CAUSE: INJ_SATURATE_MASKED_MIR (Bitfield-Mask: 0x01)*/ +#define SAR_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Pos (6UL) /*!< SAR INTR_CAUSE: INJ_RANGE_MASKED_MIR (Bit 6) */ +#define SAR_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Msk (0x40UL) /*!< SAR INTR_CAUSE: INJ_RANGE_MASKED_MIR (Bitfield-Mask: 0x01)*/ +#define SAR_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Pos (7UL) /*!< SAR INTR_CAUSE: INJ_COLLISION_MASKED_MIR (Bit 7) */ +#define SAR_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Msk (0x80UL) /*!< SAR INTR_CAUSE: INJ_COLLISION_MASKED_MIR (Bitfield-Mask: 0x01)*/ +#define SAR_INTR_CAUSE_SATURATE_MASKED_RED_Pos (30UL) /*!< SAR INTR_CAUSE: SATURATE_MASKED_RED (Bit 30) */ +#define SAR_INTR_CAUSE_SATURATE_MASKED_RED_Msk (0x40000000UL) /*!< SAR INTR_CAUSE: SATURATE_MASKED_RED (Bitfield-Mask: 0x01) */ +#define SAR_INTR_CAUSE_RANGE_MASKED_RED_Pos (31UL) /*!< SAR INTR_CAUSE: RANGE_MASKED_RED (Bit 31) */ +#define SAR_INTR_CAUSE_RANGE_MASKED_RED_Msk (0x80000000UL) /*!< SAR INTR_CAUSE: RANGE_MASKED_RED (Bitfield-Mask: 0x01) */ +/* ================================================== SAR.INJ_CHAN_CONFIG ================================================== */ +#define SAR_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Pos (0UL) /*!< SAR INJ_CHAN_CONFIG: INJ_PIN_ADDR (Bit 0) */ +#define SAR_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Msk (0x7UL) /*!< SAR INJ_CHAN_CONFIG: INJ_PIN_ADDR (Bitfield-Mask: 0x07) */ +#define SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos (4UL) /*!< SAR INJ_CHAN_CONFIG: INJ_PORT_ADDR (Bit 4) */ +#define SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Msk (0x70UL) /*!< SAR INJ_CHAN_CONFIG: INJ_PORT_ADDR (Bitfield-Mask: 0x07) */ +#define SAR_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Pos (8UL) /*!< SAR INJ_CHAN_CONFIG: INJ_DIFFERENTIAL_EN (Bit 8) */ +#define SAR_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Msk (0x100UL) /*!< SAR INJ_CHAN_CONFIG: INJ_DIFFERENTIAL_EN (Bitfield-Mask: 0x01)*/ +#define SAR_INJ_CHAN_CONFIG_INJ_AVG_EN_Pos (10UL) /*!< SAR INJ_CHAN_CONFIG: INJ_AVG_EN (Bit 10) */ +#define SAR_INJ_CHAN_CONFIG_INJ_AVG_EN_Msk (0x400UL) /*!< SAR INJ_CHAN_CONFIG: INJ_AVG_EN (Bitfield-Mask: 0x01) */ +#define SAR_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Pos (12UL) /*!< SAR INJ_CHAN_CONFIG: INJ_SAMPLE_TIME_SEL (Bit 12) */ +#define SAR_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Msk (0x3000UL) /*!< SAR INJ_CHAN_CONFIG: INJ_SAMPLE_TIME_SEL (Bitfield-Mask: 0x03)*/ +#define SAR_INJ_CHAN_CONFIG_INJ_TAILGATING_Pos (30UL) /*!< SAR INJ_CHAN_CONFIG: INJ_TAILGATING (Bit 30) */ +#define SAR_INJ_CHAN_CONFIG_INJ_TAILGATING_Msk (0x40000000UL) /*!< SAR INJ_CHAN_CONFIG: INJ_TAILGATING (Bitfield-Mask: 0x01) */ +#define SAR_INJ_CHAN_CONFIG_INJ_START_EN_Pos (31UL) /*!< SAR INJ_CHAN_CONFIG: INJ_START_EN (Bit 31) */ +#define SAR_INJ_CHAN_CONFIG_INJ_START_EN_Msk (0x80000000UL) /*!< SAR INJ_CHAN_CONFIG: INJ_START_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== SAR.INJ_RESULT ===================================================== */ +#define SAR_INJ_RESULT_INJ_RESULT_Pos (0UL) /*!< SAR INJ_RESULT: INJ_RESULT (Bit 0) */ +#define SAR_INJ_RESULT_INJ_RESULT_Msk (0xffffUL) /*!< SAR INJ_RESULT: INJ_RESULT (Bitfield-Mask: 0xffff) */ +#define SAR_INJ_RESULT_INJ_NEWVALUE_Pos (27UL) /*!< SAR INJ_RESULT: INJ_NEWVALUE (Bit 27) */ +#define SAR_INJ_RESULT_INJ_NEWVALUE_Msk (0x8000000UL) /*!< SAR INJ_RESULT: INJ_NEWVALUE (Bitfield-Mask: 0x01) */ +#define SAR_INJ_RESULT_INJ_COLLISION_INTR_MIR_Pos (28UL) /*!< SAR INJ_RESULT: INJ_COLLISION_INTR_MIR (Bit 28) */ +#define SAR_INJ_RESULT_INJ_COLLISION_INTR_MIR_Msk (0x10000000UL) /*!< SAR INJ_RESULT: INJ_COLLISION_INTR_MIR (Bitfield-Mask: 0x01)*/ +#define SAR_INJ_RESULT_INJ_SATURATE_INTR_MIR_Pos (29UL) /*!< SAR INJ_RESULT: INJ_SATURATE_INTR_MIR (Bit 29) */ +#define SAR_INJ_RESULT_INJ_SATURATE_INTR_MIR_Msk (0x20000000UL) /*!< SAR INJ_RESULT: INJ_SATURATE_INTR_MIR (Bitfield-Mask: 0x01)*/ +#define SAR_INJ_RESULT_INJ_RANGE_INTR_MIR_Pos (30UL) /*!< SAR INJ_RESULT: INJ_RANGE_INTR_MIR (Bit 30) */ +#define SAR_INJ_RESULT_INJ_RANGE_INTR_MIR_Msk (0x40000000UL) /*!< SAR INJ_RESULT: INJ_RANGE_INTR_MIR (Bitfield-Mask: 0x01) */ +#define SAR_INJ_RESULT_INJ_EOC_INTR_MIR_Pos (31UL) /*!< SAR INJ_RESULT: INJ_EOC_INTR_MIR (Bit 31) */ +#define SAR_INJ_RESULT_INJ_EOC_INTR_MIR_Msk (0x80000000UL) /*!< SAR INJ_RESULT: INJ_EOC_INTR_MIR (Bitfield-Mask: 0x01) */ +/* ====================================================== SAR.STATUS ======================================================= */ +#define SAR_STATUS_CUR_CHAN_Pos (0UL) /*!< SAR STATUS: CUR_CHAN (Bit 0) */ +#define SAR_STATUS_CUR_CHAN_Msk (0x1fUL) /*!< SAR STATUS: CUR_CHAN (Bitfield-Mask: 0x1f) */ +#define SAR_STATUS_SW_VREF_NEG_Pos (30UL) /*!< SAR STATUS: SW_VREF_NEG (Bit 30) */ +#define SAR_STATUS_SW_VREF_NEG_Msk (0x40000000UL) /*!< SAR STATUS: SW_VREF_NEG (Bitfield-Mask: 0x01) */ +#define SAR_STATUS_BUSY_Pos (31UL) /*!< SAR STATUS: BUSY (Bit 31) */ +#define SAR_STATUS_BUSY_Msk (0x80000000UL) /*!< SAR STATUS: BUSY (Bitfield-Mask: 0x01) */ +/* ===================================================== SAR.AVG_STAT ====================================================== */ +#define SAR_AVG_STAT_CUR_AVG_ACCU_Pos (0UL) /*!< SAR AVG_STAT: CUR_AVG_ACCU (Bit 0) */ +#define SAR_AVG_STAT_CUR_AVG_ACCU_Msk (0xfffffUL) /*!< SAR AVG_STAT: CUR_AVG_ACCU (Bitfield-Mask: 0xfffff) */ +#define SAR_AVG_STAT_INTRLV_BUSY_Pos (23UL) /*!< SAR AVG_STAT: INTRLV_BUSY (Bit 23) */ +#define SAR_AVG_STAT_INTRLV_BUSY_Msk (0x800000UL) /*!< SAR AVG_STAT: INTRLV_BUSY (Bitfield-Mask: 0x01) */ +#define SAR_AVG_STAT_CUR_AVG_CNT_Pos (24UL) /*!< SAR AVG_STAT: CUR_AVG_CNT (Bit 24) */ +#define SAR_AVG_STAT_CUR_AVG_CNT_Msk (0xff000000UL) /*!< SAR AVG_STAT: CUR_AVG_CNT (Bitfield-Mask: 0xff) */ +/* ==================================================== SAR.MUX_SWITCH0 ==================================================== */ +#define SAR_MUX_SWITCH0_MUX_FW_P0_VPLUS_Pos (0UL) /*!< SAR MUX_SWITCH0: MUX_FW_P0_VPLUS (Bit 0) */ +#define SAR_MUX_SWITCH0_MUX_FW_P0_VPLUS_Msk (0x1UL) /*!< SAR MUX_SWITCH0: MUX_FW_P0_VPLUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P1_VPLUS_Pos (1UL) /*!< SAR MUX_SWITCH0: MUX_FW_P1_VPLUS (Bit 1) */ +#define SAR_MUX_SWITCH0_MUX_FW_P1_VPLUS_Msk (0x2UL) /*!< SAR MUX_SWITCH0: MUX_FW_P1_VPLUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P2_VPLUS_Pos (2UL) /*!< SAR MUX_SWITCH0: MUX_FW_P2_VPLUS (Bit 2) */ +#define SAR_MUX_SWITCH0_MUX_FW_P2_VPLUS_Msk (0x4UL) /*!< SAR MUX_SWITCH0: MUX_FW_P2_VPLUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P3_VPLUS_Pos (3UL) /*!< SAR MUX_SWITCH0: MUX_FW_P3_VPLUS (Bit 3) */ +#define SAR_MUX_SWITCH0_MUX_FW_P3_VPLUS_Msk (0x8UL) /*!< SAR MUX_SWITCH0: MUX_FW_P3_VPLUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P4_VPLUS_Pos (4UL) /*!< SAR MUX_SWITCH0: MUX_FW_P4_VPLUS (Bit 4) */ +#define SAR_MUX_SWITCH0_MUX_FW_P4_VPLUS_Msk (0x10UL) /*!< SAR MUX_SWITCH0: MUX_FW_P4_VPLUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P5_VPLUS_Pos (5UL) /*!< SAR MUX_SWITCH0: MUX_FW_P5_VPLUS (Bit 5) */ +#define SAR_MUX_SWITCH0_MUX_FW_P5_VPLUS_Msk (0x20UL) /*!< SAR MUX_SWITCH0: MUX_FW_P5_VPLUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P6_VPLUS_Pos (6UL) /*!< SAR MUX_SWITCH0: MUX_FW_P6_VPLUS (Bit 6) */ +#define SAR_MUX_SWITCH0_MUX_FW_P6_VPLUS_Msk (0x40UL) /*!< SAR MUX_SWITCH0: MUX_FW_P6_VPLUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P7_VPLUS_Pos (7UL) /*!< SAR MUX_SWITCH0: MUX_FW_P7_VPLUS (Bit 7) */ +#define SAR_MUX_SWITCH0_MUX_FW_P7_VPLUS_Msk (0x80UL) /*!< SAR MUX_SWITCH0: MUX_FW_P7_VPLUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P0_VMINUS_Pos (8UL) /*!< SAR MUX_SWITCH0: MUX_FW_P0_VMINUS (Bit 8) */ +#define SAR_MUX_SWITCH0_MUX_FW_P0_VMINUS_Msk (0x100UL) /*!< SAR MUX_SWITCH0: MUX_FW_P0_VMINUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P1_VMINUS_Pos (9UL) /*!< SAR MUX_SWITCH0: MUX_FW_P1_VMINUS (Bit 9) */ +#define SAR_MUX_SWITCH0_MUX_FW_P1_VMINUS_Msk (0x200UL) /*!< SAR MUX_SWITCH0: MUX_FW_P1_VMINUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P2_VMINUS_Pos (10UL) /*!< SAR MUX_SWITCH0: MUX_FW_P2_VMINUS (Bit 10) */ +#define SAR_MUX_SWITCH0_MUX_FW_P2_VMINUS_Msk (0x400UL) /*!< SAR MUX_SWITCH0: MUX_FW_P2_VMINUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P3_VMINUS_Pos (11UL) /*!< SAR MUX_SWITCH0: MUX_FW_P3_VMINUS (Bit 11) */ +#define SAR_MUX_SWITCH0_MUX_FW_P3_VMINUS_Msk (0x800UL) /*!< SAR MUX_SWITCH0: MUX_FW_P3_VMINUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P4_VMINUS_Pos (12UL) /*!< SAR MUX_SWITCH0: MUX_FW_P4_VMINUS (Bit 12) */ +#define SAR_MUX_SWITCH0_MUX_FW_P4_VMINUS_Msk (0x1000UL) /*!< SAR MUX_SWITCH0: MUX_FW_P4_VMINUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P5_VMINUS_Pos (13UL) /*!< SAR MUX_SWITCH0: MUX_FW_P5_VMINUS (Bit 13) */ +#define SAR_MUX_SWITCH0_MUX_FW_P5_VMINUS_Msk (0x2000UL) /*!< SAR MUX_SWITCH0: MUX_FW_P5_VMINUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P6_VMINUS_Pos (14UL) /*!< SAR MUX_SWITCH0: MUX_FW_P6_VMINUS (Bit 14) */ +#define SAR_MUX_SWITCH0_MUX_FW_P6_VMINUS_Msk (0x4000UL) /*!< SAR MUX_SWITCH0: MUX_FW_P6_VMINUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P7_VMINUS_Pos (15UL) /*!< SAR MUX_SWITCH0: MUX_FW_P7_VMINUS (Bit 15) */ +#define SAR_MUX_SWITCH0_MUX_FW_P7_VMINUS_Msk (0x8000UL) /*!< SAR MUX_SWITCH0: MUX_FW_P7_VMINUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Pos (16UL) /*!< SAR MUX_SWITCH0: MUX_FW_VSSA_VMINUS (Bit 16) */ +#define SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk (0x10000UL) /*!< SAR MUX_SWITCH0: MUX_FW_VSSA_VMINUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Pos (17UL) /*!< SAR MUX_SWITCH0: MUX_FW_TEMP_VPLUS (Bit 17) */ +#define SAR_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Msk (0x20000UL) /*!< SAR MUX_SWITCH0: MUX_FW_TEMP_VPLUS (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Pos (18UL) /*!< SAR MUX_SWITCH0: MUX_FW_AMUXBUSA_VPLUS (Bit 18) */ +#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk (0x40000UL) /*!< SAR MUX_SWITCH0: MUX_FW_AMUXBUSA_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Pos (19UL) /*!< SAR MUX_SWITCH0: MUX_FW_AMUXBUSB_VPLUS (Bit 19) */ +#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Msk (0x80000UL) /*!< SAR MUX_SWITCH0: MUX_FW_AMUXBUSB_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Pos (20UL) /*!< SAR MUX_SWITCH0: MUX_FW_AMUXBUSA_VMINUS (Bit 20) */ +#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Msk (0x100000UL) /*!< SAR MUX_SWITCH0: MUX_FW_AMUXBUSA_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Pos (21UL) /*!< SAR MUX_SWITCH0: MUX_FW_AMUXBUSB_VMINUS (Bit 21) */ +#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Msk (0x200000UL) /*!< SAR MUX_SWITCH0: MUX_FW_AMUXBUSB_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Pos (22UL) /*!< SAR MUX_SWITCH0: MUX_FW_SARBUS0_VPLUS (Bit 22) */ +#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Msk (0x400000UL) /*!< SAR MUX_SWITCH0: MUX_FW_SARBUS0_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Pos (23UL) /*!< SAR MUX_SWITCH0: MUX_FW_SARBUS1_VPLUS (Bit 23) */ +#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Msk (0x800000UL) /*!< SAR MUX_SWITCH0: MUX_FW_SARBUS1_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Pos (24UL) /*!< SAR MUX_SWITCH0: MUX_FW_SARBUS0_VMINUS (Bit 24) */ +#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Msk (0x1000000UL) /*!< SAR MUX_SWITCH0: MUX_FW_SARBUS0_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Pos (25UL) /*!< SAR MUX_SWITCH0: MUX_FW_SARBUS1_VMINUS (Bit 25) */ +#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Msk (0x2000000UL) /*!< SAR MUX_SWITCH0: MUX_FW_SARBUS1_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH0_MUX_FW_P4_COREIO0_Pos (26UL) /*!< SAR MUX_SWITCH0: MUX_FW_P4_COREIO0 (Bit 26) */ +#define SAR_MUX_SWITCH0_MUX_FW_P4_COREIO0_Msk (0x4000000UL) /*!< SAR MUX_SWITCH0: MUX_FW_P4_COREIO0 (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P5_COREIO1_Pos (27UL) /*!< SAR MUX_SWITCH0: MUX_FW_P5_COREIO1 (Bit 27) */ +#define SAR_MUX_SWITCH0_MUX_FW_P5_COREIO1_Msk (0x8000000UL) /*!< SAR MUX_SWITCH0: MUX_FW_P5_COREIO1 (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P6_COREIO2_Pos (28UL) /*!< SAR MUX_SWITCH0: MUX_FW_P6_COREIO2 (Bit 28) */ +#define SAR_MUX_SWITCH0_MUX_FW_P6_COREIO2_Msk (0x10000000UL) /*!< SAR MUX_SWITCH0: MUX_FW_P6_COREIO2 (Bitfield-Mask: 0x01) */ +#define SAR_MUX_SWITCH0_MUX_FW_P7_COREIO3_Pos (29UL) /*!< SAR MUX_SWITCH0: MUX_FW_P7_COREIO3 (Bit 29) */ +#define SAR_MUX_SWITCH0_MUX_FW_P7_COREIO3_Msk (0x20000000UL) /*!< SAR MUX_SWITCH0: MUX_FW_P7_COREIO3 (Bitfield-Mask: 0x01) */ +/* ================================================= SAR.MUX_SWITCH_CLEAR0 ================================================= */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Pos (0UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P0_VPLUS (Bit 0) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Msk (0x1UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P0_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Pos (1UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P1_VPLUS (Bit 1) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Msk (0x2UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P1_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Pos (2UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P2_VPLUS (Bit 2) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Msk (0x4UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P2_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Pos (3UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P3_VPLUS (Bit 3) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Msk (0x8UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P3_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Pos (4UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P4_VPLUS (Bit 4) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Msk (0x10UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P4_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Pos (5UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P5_VPLUS (Bit 5) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Msk (0x20UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P5_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Pos (6UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P6_VPLUS (Bit 6) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Msk (0x40UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P6_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Pos (7UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P7_VPLUS (Bit 7) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Msk (0x80UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P7_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Pos (8UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P0_VMINUS (Bit 8) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Msk (0x100UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P0_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Pos (9UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P1_VMINUS (Bit 9) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Msk (0x200UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P1_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Pos (10UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P2_VMINUS (Bit 10) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Msk (0x400UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P2_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Pos (11UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P3_VMINUS (Bit 11) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Msk (0x800UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P3_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Pos (12UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P4_VMINUS (Bit 12) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Msk (0x1000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P4_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Pos (13UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P5_VMINUS (Bit 13) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Msk (0x2000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P5_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Pos (14UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P6_VMINUS (Bit 14) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Msk (0x4000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P6_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Pos (15UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P7_VMINUS (Bit 15) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Msk (0x8000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P7_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Pos (16UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_VSSA_VMINUS (Bit 16) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Msk (0x10000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_VSSA_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Pos (17UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_TEMP_VPLUS (Bit 17) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Msk (0x20000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_TEMP_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Pos (18UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_AMUXBUSA_VPLUS (Bit 18) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Msk (0x40000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_AMUXBUSA_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Pos (19UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_AMUXBUSB_VPLUS (Bit 19) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Msk (0x80000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_AMUXBUSB_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Pos (20UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_AMUXBUSA_VMINUS (Bit 20) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Msk (0x100000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_AMUXBUSA_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Pos (21UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_AMUXBUSB_VMINUS (Bit 21) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Msk (0x200000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_AMUXBUSB_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Pos (22UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_SARBUS0_VPLUS (Bit 22) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Msk (0x400000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_SARBUS0_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Pos (23UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_SARBUS1_VPLUS (Bit 23) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Msk (0x800000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_SARBUS1_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Pos (24UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_SARBUS0_VMINUS (Bit 24) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Msk (0x1000000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_SARBUS0_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Pos (25UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_SARBUS1_VMINUS (Bit 25) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Msk (0x2000000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_SARBUS1_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Pos (26UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P4_COREIO0 (Bit 26) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Msk (0x4000000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P4_COREIO0 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Pos (27UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P5_COREIO1 (Bit 27) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Msk (0x8000000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P5_COREIO1 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Pos (28UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P6_COREIO2 (Bit 28) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Msk (0x10000000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P6_COREIO2 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Pos (29UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P7_COREIO3 (Bit 29) */ +#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Msk (0x20000000UL) /*!< SAR MUX_SWITCH_CLEAR0: MUX_FW_P7_COREIO3 (Bitfield-Mask: 0x01)*/ +/* ================================================ SAR.MUX_SWITCH_DS_CTRL ================================================= */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P0_Pos (0UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P0 (Bit 0) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P0_Msk (0x1UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P0 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P1_Pos (1UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P1 (Bit 1) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P1_Msk (0x2UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P1 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P2_Pos (2UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P2 (Bit 2) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P2_Msk (0x4UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P2 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P3_Pos (3UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P3 (Bit 3) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P3_Msk (0x8UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P3 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P4_Pos (4UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P4 (Bit 4) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P4_Msk (0x10UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P4 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P5_Pos (5UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P5 (Bit 5) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P5_Msk (0x20UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P5 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P6_Pos (6UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P6 (Bit 6) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P6_Msk (0x40UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P6 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P7_Pos (7UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P7 (Bit 7) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P7_Msk (0x80UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_P7 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_VSSA_Pos (16UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_VSSA (Bit 16) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_VSSA_Msk (0x10000UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_VSSA (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_TEMP_Pos (17UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_TEMP (Bit 17) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_TEMP_Msk (0x20000UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_TEMP (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSA_Pos (18UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_AMUXBUSA (Bit 18) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSA_Msk (0x40000UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_AMUXBUSA (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSB_Pos (19UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_AMUXBUSB (Bit 19) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSB_Msk (0x80000UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_AMUXBUSB (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS0_Pos (22UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_SARBUS0 (Bit 22) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS0_Msk (0x400000UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_SARBUS0 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS1_Pos (23UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_SARBUS1 (Bit 23) */ +#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS1_Msk (0x800000UL) /*!< SAR MUX_SWITCH_DS_CTRL: MUX_DS_CTRL_SARBUS1 (Bitfield-Mask: 0x01)*/ +/* ================================================ SAR.MUX_SWITCH_SQ_CTRL ================================================= */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Pos (0UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P0 (Bit 0) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk (0x1UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P0 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Pos (1UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P1 (Bit 1) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk (0x2UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P1 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Pos (2UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P2 (Bit 2) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk (0x4UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P2 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Pos (3UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P3 (Bit 3) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk (0x8UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P3 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Pos (4UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P4 (Bit 4) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk (0x10UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P4 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Pos (5UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P5 (Bit 5) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk (0x20UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P5 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Pos (6UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P6 (Bit 6) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk (0x40UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P6 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Pos (7UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P7 (Bit 7) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk (0x80UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_P7 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Pos (16UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_VSSA (Bit 16) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk (0x10000UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_VSSA (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Pos (17UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_TEMP (Bit 17) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk (0x20000UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_TEMP (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Pos (18UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_AMUXBUSA (Bit 18) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk (0x40000UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_AMUXBUSA (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Pos (19UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_AMUXBUSB (Bit 19) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk (0x80000UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_AMUXBUSB (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Pos (22UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_SARBUS0 (Bit 22) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk (0x400000UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_SARBUS0 (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Pos (23UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_SARBUS1 (Bit 23) */ +#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk (0x800000UL) /*!< SAR MUX_SWITCH_SQ_CTRL: MUX_SQ_CTRL_SARBUS1 (Bitfield-Mask: 0x01)*/ +/* ================================================= SAR.MUX_SWITCH_STATUS ================================================= */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Pos (0UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P0_VPLUS (Bit 0) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Msk (0x1UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P0_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Pos (1UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P1_VPLUS (Bit 1) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Msk (0x2UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P1_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Pos (2UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P2_VPLUS (Bit 2) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Msk (0x4UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P2_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Pos (3UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P3_VPLUS (Bit 3) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Msk (0x8UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P3_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Pos (4UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P4_VPLUS (Bit 4) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Msk (0x10UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P4_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Pos (5UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P5_VPLUS (Bit 5) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Msk (0x20UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P5_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Pos (6UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P6_VPLUS (Bit 6) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Msk (0x40UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P6_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Pos (7UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P7_VPLUS (Bit 7) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Msk (0x80UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P7_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Pos (8UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P0_VMINUS (Bit 8) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Msk (0x100UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P0_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Pos (9UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P1_VMINUS (Bit 9) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Msk (0x200UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P1_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Pos (10UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P2_VMINUS (Bit 10) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Msk (0x400UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P2_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Pos (11UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P3_VMINUS (Bit 11) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Msk (0x800UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P3_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Pos (12UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P4_VMINUS (Bit 12) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Msk (0x1000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P4_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Pos (13UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P5_VMINUS (Bit 13) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Msk (0x2000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P5_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Pos (14UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P6_VMINUS (Bit 14) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Msk (0x4000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P6_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Pos (15UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P7_VMINUS (Bit 15) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Msk (0x8000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_P7_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Pos (16UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_VSSA_VMINUS (Bit 16) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Msk (0x10000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_VSSA_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Pos (17UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_TEMP_VPLUS (Bit 17) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Msk (0x20000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_TEMP_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Pos (18UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_AMUXBUSA_VPLUS (Bit 18) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Msk (0x40000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_AMUXBUSA_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Pos (19UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_AMUXBUSB_VPLUS (Bit 19) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Msk (0x80000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_AMUXBUSB_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Pos (20UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_AMUXBUSA_VMINUS (Bit 20) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Msk (0x100000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_AMUXBUSA_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Pos (21UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_AMUXBUSB_VMINUS (Bit 21) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Msk (0x200000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_AMUXBUSB_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Pos (22UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_SARBUS0_VPLUS (Bit 22) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Msk (0x400000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_SARBUS0_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Pos (23UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_SARBUS1_VPLUS (Bit 23) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Msk (0x800000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_SARBUS1_VPLUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Pos (24UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_SARBUS0_VMINUS (Bit 24) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Msk (0x1000000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_SARBUS0_VMINUS (Bitfield-Mask: 0x01)*/ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Pos (25UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_SARBUS1_VMINUS (Bit 25) */ +#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Msk (0x2000000UL) /*!< SAR MUX_SWITCH_STATUS: MUX_FW_SARBUS1_VMINUS (Bitfield-Mask: 0x01)*/ +/* ===================================================== SAR.ANA_TRIM0 ===================================================== */ +#define SAR_ANA_TRIM0_CAP_TRIM_Pos (0UL) /*!< SAR ANA_TRIM0: CAP_TRIM (Bit 0) */ +#define SAR_ANA_TRIM0_CAP_TRIM_Msk (0x1fUL) /*!< SAR ANA_TRIM0: CAP_TRIM (Bitfield-Mask: 0x1f) */ +#define SAR_ANA_TRIM0_TRIMUNIT_Pos (5UL) /*!< SAR ANA_TRIM0: TRIMUNIT (Bit 5) */ +#define SAR_ANA_TRIM0_TRIMUNIT_Msk (0x20UL) /*!< SAR ANA_TRIM0: TRIMUNIT (Bitfield-Mask: 0x01) */ +/* ===================================================== SAR.ANA_TRIM1 ===================================================== */ +#define SAR_ANA_TRIM1_SAR_REF_BUF_TRIM_Pos (0UL) /*!< SAR ANA_TRIM1: SAR_REF_BUF_TRIM (Bit 0) */ +#define SAR_ANA_TRIM1_SAR_REF_BUF_TRIM_Msk (0x3fUL) /*!< SAR ANA_TRIM1: SAR_REF_BUF_TRIM (Bitfield-Mask: 0x3f) */ + + +#endif /* _CYIP_SAR_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_scb.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_scb.h new file mode 100644 index 0000000000..4af1c623a6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_scb.h @@ -0,0 +1,755 @@ +/***************************************************************************//** +* \file cyip_scb.h +* +* \brief +* SCB IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_SCB_H_ +#define _CYIP_SCB_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ SCB ================ */ +/* =========================================================================================================================== */ + +#define SCB_SECTION_SIZE 0x00010000UL + +/** + * \brief Serial Communications Block (SPI/UART/I2C) (CySCB) + */ +typedef struct { /*!< CySCB Structure */ + __IOM uint32_t CTRL; /*!< 0x00000000 Generic control */ + __IM uint32_t STATUS; /*!< 0x00000004 Generic status */ + __IOM uint32_t CMD_RESP_CTRL; /*!< 0x00000008 Command/response control */ + __IM uint32_t CMD_RESP_STATUS; /*!< 0x0000000C Command/response status */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t SPI_CTRL; /*!< 0x00000020 SPI control */ + __IM uint32_t SPI_STATUS; /*!< 0x00000024 SPI status */ + __IM uint32_t RESERVED1[6]; + __IOM uint32_t UART_CTRL; /*!< 0x00000040 UART control */ + __IOM uint32_t UART_TX_CTRL; /*!< 0x00000044 UART transmitter control */ + __IOM uint32_t UART_RX_CTRL; /*!< 0x00000048 UART receiver control */ + __IM uint32_t UART_RX_STATUS; /*!< 0x0000004C UART receiver status */ + __IOM uint32_t UART_FLOW_CTRL; /*!< 0x00000050 UART flow control */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t I2C_CTRL; /*!< 0x00000060 I2C control */ + __IM uint32_t I2C_STATUS; /*!< 0x00000064 I2C status */ + __IOM uint32_t I2C_M_CMD; /*!< 0x00000068 I2C master command */ + __IOM uint32_t I2C_S_CMD; /*!< 0x0000006C I2C slave command */ + __IOM uint32_t I2C_CFG; /*!< 0x00000070 I2C configuration */ + __IM uint32_t RESERVED3[35]; + __IOM uint32_t DDFT_CTRL; /*!< 0x00000100 Digital DfT control */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t TX_CTRL; /*!< 0x00000200 Transmitter control */ + __IOM uint32_t TX_FIFO_CTRL; /*!< 0x00000204 Transmitter FIFO control */ + __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000208 Transmitter FIFO status */ + __IM uint32_t RESERVED5[13]; + __OM uint32_t TX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */ + __IM uint32_t RESERVED6[47]; + __IOM uint32_t RX_CTRL; /*!< 0x00000300 Receiver control */ + __IOM uint32_t RX_FIFO_CTRL; /*!< 0x00000304 Receiver FIFO control */ + __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000308 Receiver FIFO status */ + __IM uint32_t RESERVED7; + __IOM uint32_t RX_MATCH; /*!< 0x00000310 Slave address and mask */ + __IM uint32_t RESERVED8[11]; + __IM uint32_t RX_FIFO_RD; /*!< 0x00000340 Receiver FIFO read */ + __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x00000344 Receiver FIFO read silent */ + __IM uint32_t RESERVED9[46]; + __IOM uint32_t EZ_DATA[512]; /*!< 0x00000400 Memory buffer */ + __IM uint32_t RESERVED10[128]; + __IM uint32_t INTR_CAUSE; /*!< 0x00000E00 Active clocked interrupt signal */ + __IM uint32_t RESERVED11[31]; + __IOM uint32_t INTR_I2C_EC; /*!< 0x00000E80 Externally clocked I2C interrupt request */ + __IM uint32_t RESERVED12; + __IOM uint32_t INTR_I2C_EC_MASK; /*!< 0x00000E88 Externally clocked I2C interrupt mask */ + __IM uint32_t INTR_I2C_EC_MASKED; /*!< 0x00000E8C Externally clocked I2C interrupt masked */ + __IM uint32_t RESERVED13[12]; + __IOM uint32_t INTR_SPI_EC; /*!< 0x00000EC0 Externally clocked SPI interrupt request */ + __IM uint32_t RESERVED14; + __IOM uint32_t INTR_SPI_EC_MASK; /*!< 0x00000EC8 Externally clocked SPI interrupt mask */ + __IM uint32_t INTR_SPI_EC_MASKED; /*!< 0x00000ECC Externally clocked SPI interrupt masked */ + __IM uint32_t RESERVED15[12]; + __IOM uint32_t INTR_M; /*!< 0x00000F00 Master interrupt request */ + __IOM uint32_t INTR_M_SET; /*!< 0x00000F04 Master interrupt set request */ + __IOM uint32_t INTR_M_MASK; /*!< 0x00000F08 Master interrupt mask */ + __IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */ + __IM uint32_t RESERVED16[12]; + __IOM uint32_t INTR_S; /*!< 0x00000F40 Slave interrupt request */ + __IOM uint32_t INTR_S_SET; /*!< 0x00000F44 Slave interrupt set request */ + __IOM uint32_t INTR_S_MASK; /*!< 0x00000F48 Slave interrupt mask */ + __IM uint32_t INTR_S_MASKED; /*!< 0x00000F4C Slave interrupt masked request */ + __IM uint32_t RESERVED17[12]; + __IOM uint32_t INTR_TX; /*!< 0x00000F80 Transmitter interrupt request */ + __IOM uint32_t INTR_TX_SET; /*!< 0x00000F84 Transmitter interrupt set request */ + __IOM uint32_t INTR_TX_MASK; /*!< 0x00000F88 Transmitter interrupt mask */ + __IM uint32_t INTR_TX_MASKED; /*!< 0x00000F8C Transmitter interrupt masked request */ + __IM uint32_t RESERVED18[12]; + __IOM uint32_t INTR_RX; /*!< 0x00000FC0 Receiver interrupt request */ + __IOM uint32_t INTR_RX_SET; /*!< 0x00000FC4 Receiver interrupt set request */ + __IOM uint32_t INTR_RX_MASK; /*!< 0x00000FC8 Receiver interrupt mask */ + __IM uint32_t INTR_RX_MASKED; /*!< 0x00000FCC Receiver interrupt masked request */ +} CySCB_Type; /*!< Size = 4048 (0xFD0) */ + + +/* ======================================================= SCB.CTRL ======================================================== */ +#define SCB_CTRL_OVS_Pos (0UL) /*!< SCB CTRL: OVS (Bit 0) */ +#define SCB_CTRL_OVS_Msk (0xfUL) /*!< SCB CTRL: OVS (Bitfield-Mask: 0x0f) */ +#define SCB_CTRL_EC_AM_MODE_Pos (8UL) /*!< SCB CTRL: EC_AM_MODE (Bit 8) */ +#define SCB_CTRL_EC_AM_MODE_Msk (0x100UL) /*!< SCB CTRL: EC_AM_MODE (Bitfield-Mask: 0x01) */ +#define SCB_CTRL_EC_OP_MODE_Pos (9UL) /*!< SCB CTRL: EC_OP_MODE (Bit 9) */ +#define SCB_CTRL_EC_OP_MODE_Msk (0x200UL) /*!< SCB CTRL: EC_OP_MODE (Bitfield-Mask: 0x01) */ +#define SCB_CTRL_EZ_MODE_Pos (10UL) /*!< SCB CTRL: EZ_MODE (Bit 10) */ +#define SCB_CTRL_EZ_MODE_Msk (0x400UL) /*!< SCB CTRL: EZ_MODE (Bitfield-Mask: 0x01) */ +#define SCB_CTRL_BYTE_MODE_Pos (11UL) /*!< SCB CTRL: BYTE_MODE (Bit 11) */ +#define SCB_CTRL_BYTE_MODE_Msk (0x800UL) /*!< SCB CTRL: BYTE_MODE (Bitfield-Mask: 0x01) */ +#define SCB_CTRL_CMD_RESP_MODE_Pos (12UL) /*!< SCB CTRL: CMD_RESP_MODE (Bit 12) */ +#define SCB_CTRL_CMD_RESP_MODE_Msk (0x1000UL) /*!< SCB CTRL: CMD_RESP_MODE (Bitfield-Mask: 0x01) */ +#define SCB_CTRL_ADDR_ACCEPT_Pos (16UL) /*!< SCB CTRL: ADDR_ACCEPT (Bit 16) */ +#define SCB_CTRL_ADDR_ACCEPT_Msk (0x10000UL) /*!< SCB CTRL: ADDR_ACCEPT (Bitfield-Mask: 0x01) */ +#define SCB_CTRL_BLOCK_Pos (17UL) /*!< SCB CTRL: BLOCK (Bit 17) */ +#define SCB_CTRL_BLOCK_Msk (0x20000UL) /*!< SCB CTRL: BLOCK (Bitfield-Mask: 0x01) */ +#define SCB_CTRL_MODE_Pos (24UL) /*!< SCB CTRL: MODE (Bit 24) */ +#define SCB_CTRL_MODE_Msk (0x3000000UL) /*!< SCB CTRL: MODE (Bitfield-Mask: 0x03) */ +#define SCB_CTRL_ENABLED_Pos (31UL) /*!< SCB CTRL: ENABLED (Bit 31) */ +#define SCB_CTRL_ENABLED_Msk (0x80000000UL) /*!< SCB CTRL: ENABLED (Bitfield-Mask: 0x01) */ +/* ====================================================== SCB.STATUS ======================================================= */ +#define SCB_STATUS_EC_BUSY_Pos (0UL) /*!< SCB STATUS: EC_BUSY (Bit 0) */ +#define SCB_STATUS_EC_BUSY_Msk (0x1UL) /*!< SCB STATUS: EC_BUSY (Bitfield-Mask: 0x01) */ +/* =================================================== SCB.CMD_RESP_CTRL =================================================== */ +#define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Pos (0UL) /*!< SCB CMD_RESP_CTRL: BASE_RD_ADDR (Bit 0) */ +#define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Msk (0x1ffUL) /*!< SCB CMD_RESP_CTRL: BASE_RD_ADDR (Bitfield-Mask: 0x1ff) */ +#define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Pos (16UL) /*!< SCB CMD_RESP_CTRL: BASE_WR_ADDR (Bit 16) */ +#define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Msk (0x1ff0000UL) /*!< SCB CMD_RESP_CTRL: BASE_WR_ADDR (Bitfield-Mask: 0x1ff) */ +/* ================================================== SCB.CMD_RESP_STATUS ================================================== */ +#define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Pos (0UL) /*!< SCB CMD_RESP_STATUS: CURR_RD_ADDR (Bit 0) */ +#define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Msk (0x1ffUL) /*!< SCB CMD_RESP_STATUS: CURR_RD_ADDR (Bitfield-Mask: 0x1ff) */ +#define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Pos (16UL) /*!< SCB CMD_RESP_STATUS: CURR_WR_ADDR (Bit 16) */ +#define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Msk (0x1ff0000UL) /*!< SCB CMD_RESP_STATUS: CURR_WR_ADDR (Bitfield-Mask: 0x1ff) */ +#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Pos (30UL) /*!< SCB CMD_RESP_STATUS: CMD_RESP_EC_BUS_BUSY (Bit 30) */ +#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Msk (0x40000000UL) /*!< SCB CMD_RESP_STATUS: CMD_RESP_EC_BUS_BUSY (Bitfield-Mask: 0x01)*/ +#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Pos (31UL) /*!< SCB CMD_RESP_STATUS: CMD_RESP_EC_BUSY (Bit 31) */ +#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Msk (0x80000000UL) /*!< SCB CMD_RESP_STATUS: CMD_RESP_EC_BUSY (Bitfield-Mask: 0x01)*/ +/* ===================================================== SCB.SPI_CTRL ====================================================== */ +#define SCB_SPI_CTRL_SSEL_CONTINUOUS_Pos (0UL) /*!< SCB SPI_CTRL: SSEL_CONTINUOUS (Bit 0) */ +#define SCB_SPI_CTRL_SSEL_CONTINUOUS_Msk (0x1UL) /*!< SCB SPI_CTRL: SSEL_CONTINUOUS (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_SELECT_PRECEDE_Pos (1UL) /*!< SCB SPI_CTRL: SELECT_PRECEDE (Bit 1) */ +#define SCB_SPI_CTRL_SELECT_PRECEDE_Msk (0x2UL) /*!< SCB SPI_CTRL: SELECT_PRECEDE (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_CPHA_Pos (2UL) /*!< SCB SPI_CTRL: CPHA (Bit 2) */ +#define SCB_SPI_CTRL_CPHA_Msk (0x4UL) /*!< SCB SPI_CTRL: CPHA (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_CPOL_Pos (3UL) /*!< SCB SPI_CTRL: CPOL (Bit 3) */ +#define SCB_SPI_CTRL_CPOL_Msk (0x8UL) /*!< SCB SPI_CTRL: CPOL (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Pos (4UL) /*!< SCB SPI_CTRL: LATE_MISO_SAMPLE (Bit 4) */ +#define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Msk (0x10UL) /*!< SCB SPI_CTRL: LATE_MISO_SAMPLE (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_SCLK_CONTINUOUS_Pos (5UL) /*!< SCB SPI_CTRL: SCLK_CONTINUOUS (Bit 5) */ +#define SCB_SPI_CTRL_SCLK_CONTINUOUS_Msk (0x20UL) /*!< SCB SPI_CTRL: SCLK_CONTINUOUS (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_SSEL_POLARITY0_Pos (8UL) /*!< SCB SPI_CTRL: SSEL_POLARITY0 (Bit 8) */ +#define SCB_SPI_CTRL_SSEL_POLARITY0_Msk (0x100UL) /*!< SCB SPI_CTRL: SSEL_POLARITY0 (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_SSEL_POLARITY1_Pos (9UL) /*!< SCB SPI_CTRL: SSEL_POLARITY1 (Bit 9) */ +#define SCB_SPI_CTRL_SSEL_POLARITY1_Msk (0x200UL) /*!< SCB SPI_CTRL: SSEL_POLARITY1 (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_SSEL_POLARITY2_Pos (10UL) /*!< SCB SPI_CTRL: SSEL_POLARITY2 (Bit 10) */ +#define SCB_SPI_CTRL_SSEL_POLARITY2_Msk (0x400UL) /*!< SCB SPI_CTRL: SSEL_POLARITY2 (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_SSEL_POLARITY3_Pos (11UL) /*!< SCB SPI_CTRL: SSEL_POLARITY3 (Bit 11) */ +#define SCB_SPI_CTRL_SSEL_POLARITY3_Msk (0x800UL) /*!< SCB SPI_CTRL: SSEL_POLARITY3 (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_LOOPBACK_Pos (16UL) /*!< SCB SPI_CTRL: LOOPBACK (Bit 16) */ +#define SCB_SPI_CTRL_LOOPBACK_Msk (0x10000UL) /*!< SCB SPI_CTRL: LOOPBACK (Bitfield-Mask: 0x01) */ +#define SCB_SPI_CTRL_MODE_Pos (24UL) /*!< SCB SPI_CTRL: MODE (Bit 24) */ +#define SCB_SPI_CTRL_MODE_Msk (0x3000000UL) /*!< SCB SPI_CTRL: MODE (Bitfield-Mask: 0x03) */ +#define SCB_SPI_CTRL_SSEL_Pos (26UL) /*!< SCB SPI_CTRL: SSEL (Bit 26) */ +#define SCB_SPI_CTRL_SSEL_Msk (0xc000000UL) /*!< SCB SPI_CTRL: SSEL (Bitfield-Mask: 0x03) */ +#define SCB_SPI_CTRL_MASTER_MODE_Pos (31UL) /*!< SCB SPI_CTRL: MASTER_MODE (Bit 31) */ +#define SCB_SPI_CTRL_MASTER_MODE_Msk (0x80000000UL) /*!< SCB SPI_CTRL: MASTER_MODE (Bitfield-Mask: 0x01) */ +/* ==================================================== SCB.SPI_STATUS ===================================================== */ +#define SCB_SPI_STATUS_BUS_BUSY_Pos (0UL) /*!< SCB SPI_STATUS: BUS_BUSY (Bit 0) */ +#define SCB_SPI_STATUS_BUS_BUSY_Msk (0x1UL) /*!< SCB SPI_STATUS: BUS_BUSY (Bitfield-Mask: 0x01) */ +#define SCB_SPI_STATUS_SPI_EC_BUSY_Pos (1UL) /*!< SCB SPI_STATUS: SPI_EC_BUSY (Bit 1) */ +#define SCB_SPI_STATUS_SPI_EC_BUSY_Msk (0x2UL) /*!< SCB SPI_STATUS: SPI_EC_BUSY (Bitfield-Mask: 0x01) */ +#define SCB_SPI_STATUS_CURR_EZ_ADDR_Pos (8UL) /*!< SCB SPI_STATUS: CURR_EZ_ADDR (Bit 8) */ +#define SCB_SPI_STATUS_CURR_EZ_ADDR_Msk (0xff00UL) /*!< SCB SPI_STATUS: CURR_EZ_ADDR (Bitfield-Mask: 0xff) */ +#define SCB_SPI_STATUS_BASE_EZ_ADDR_Pos (16UL) /*!< SCB SPI_STATUS: BASE_EZ_ADDR (Bit 16) */ +#define SCB_SPI_STATUS_BASE_EZ_ADDR_Msk (0xff0000UL) /*!< SCB SPI_STATUS: BASE_EZ_ADDR (Bitfield-Mask: 0xff) */ +/* ===================================================== SCB.UART_CTRL ===================================================== */ +#define SCB_UART_CTRL_LOOPBACK_Pos (16UL) /*!< SCB UART_CTRL: LOOPBACK (Bit 16) */ +#define SCB_UART_CTRL_LOOPBACK_Msk (0x10000UL) /*!< SCB UART_CTRL: LOOPBACK (Bitfield-Mask: 0x01) */ +#define SCB_UART_CTRL_MODE_Pos (24UL) /*!< SCB UART_CTRL: MODE (Bit 24) */ +#define SCB_UART_CTRL_MODE_Msk (0x3000000UL) /*!< SCB UART_CTRL: MODE (Bitfield-Mask: 0x03) */ +/* =================================================== SCB.UART_TX_CTRL ==================================================== */ +#define SCB_UART_TX_CTRL_STOP_BITS_Pos (0UL) /*!< SCB UART_TX_CTRL: STOP_BITS (Bit 0) */ +#define SCB_UART_TX_CTRL_STOP_BITS_Msk (0x7UL) /*!< SCB UART_TX_CTRL: STOP_BITS (Bitfield-Mask: 0x07) */ +#define SCB_UART_TX_CTRL_PARITY_Pos (4UL) /*!< SCB UART_TX_CTRL: PARITY (Bit 4) */ +#define SCB_UART_TX_CTRL_PARITY_Msk (0x10UL) /*!< SCB UART_TX_CTRL: PARITY (Bitfield-Mask: 0x01) */ +#define SCB_UART_TX_CTRL_PARITY_ENABLED_Pos (5UL) /*!< SCB UART_TX_CTRL: PARITY_ENABLED (Bit 5) */ +#define SCB_UART_TX_CTRL_PARITY_ENABLED_Msk (0x20UL) /*!< SCB UART_TX_CTRL: PARITY_ENABLED (Bitfield-Mask: 0x01) */ +#define SCB_UART_TX_CTRL_RETRY_ON_NACK_Pos (8UL) /*!< SCB UART_TX_CTRL: RETRY_ON_NACK (Bit 8) */ +#define SCB_UART_TX_CTRL_RETRY_ON_NACK_Msk (0x100UL) /*!< SCB UART_TX_CTRL: RETRY_ON_NACK (Bitfield-Mask: 0x01) */ +/* =================================================== SCB.UART_RX_CTRL ==================================================== */ +#define SCB_UART_RX_CTRL_STOP_BITS_Pos (0UL) /*!< SCB UART_RX_CTRL: STOP_BITS (Bit 0) */ +#define SCB_UART_RX_CTRL_STOP_BITS_Msk (0x7UL) /*!< SCB UART_RX_CTRL: STOP_BITS (Bitfield-Mask: 0x07) */ +#define SCB_UART_RX_CTRL_PARITY_Pos (4UL) /*!< SCB UART_RX_CTRL: PARITY (Bit 4) */ +#define SCB_UART_RX_CTRL_PARITY_Msk (0x10UL) /*!< SCB UART_RX_CTRL: PARITY (Bitfield-Mask: 0x01) */ +#define SCB_UART_RX_CTRL_PARITY_ENABLED_Pos (5UL) /*!< SCB UART_RX_CTRL: PARITY_ENABLED (Bit 5) */ +#define SCB_UART_RX_CTRL_PARITY_ENABLED_Msk (0x20UL) /*!< SCB UART_RX_CTRL: PARITY_ENABLED (Bitfield-Mask: 0x01) */ +#define SCB_UART_RX_CTRL_POLARITY_Pos (6UL) /*!< SCB UART_RX_CTRL: POLARITY (Bit 6) */ +#define SCB_UART_RX_CTRL_POLARITY_Msk (0x40UL) /*!< SCB UART_RX_CTRL: POLARITY (Bitfield-Mask: 0x01) */ +#define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Pos (8UL) /*!< SCB UART_RX_CTRL: DROP_ON_PARITY_ERROR (Bit 8) */ +#define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk (0x100UL) /*!< SCB UART_RX_CTRL: DROP_ON_PARITY_ERROR (Bitfield-Mask: 0x01)*/ +#define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Pos (9UL) /*!< SCB UART_RX_CTRL: DROP_ON_FRAME_ERROR (Bit 9) */ +#define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk (0x200UL) /*!< SCB UART_RX_CTRL: DROP_ON_FRAME_ERROR (Bitfield-Mask: 0x01)*/ +#define SCB_UART_RX_CTRL_MP_MODE_Pos (10UL) /*!< SCB UART_RX_CTRL: MP_MODE (Bit 10) */ +#define SCB_UART_RX_CTRL_MP_MODE_Msk (0x400UL) /*!< SCB UART_RX_CTRL: MP_MODE (Bitfield-Mask: 0x01) */ +#define SCB_UART_RX_CTRL_LIN_MODE_Pos (12UL) /*!< SCB UART_RX_CTRL: LIN_MODE (Bit 12) */ +#define SCB_UART_RX_CTRL_LIN_MODE_Msk (0x1000UL) /*!< SCB UART_RX_CTRL: LIN_MODE (Bitfield-Mask: 0x01) */ +#define SCB_UART_RX_CTRL_SKIP_START_Pos (13UL) /*!< SCB UART_RX_CTRL: SKIP_START (Bit 13) */ +#define SCB_UART_RX_CTRL_SKIP_START_Msk (0x2000UL) /*!< SCB UART_RX_CTRL: SKIP_START (Bitfield-Mask: 0x01) */ +#define SCB_UART_RX_CTRL_BREAK_WIDTH_Pos (16UL) /*!< SCB UART_RX_CTRL: BREAK_WIDTH (Bit 16) */ +#define SCB_UART_RX_CTRL_BREAK_WIDTH_Msk (0xf0000UL) /*!< SCB UART_RX_CTRL: BREAK_WIDTH (Bitfield-Mask: 0x0f) */ +/* ================================================== SCB.UART_RX_STATUS =================================================== */ +#define SCB_UART_RX_STATUS_BR_COUNTER_Pos (0UL) /*!< SCB UART_RX_STATUS: BR_COUNTER (Bit 0) */ +#define SCB_UART_RX_STATUS_BR_COUNTER_Msk (0xfffUL) /*!< SCB UART_RX_STATUS: BR_COUNTER (Bitfield-Mask: 0xfff) */ +/* ================================================== SCB.UART_FLOW_CTRL =================================================== */ +#define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Pos (0UL) /*!< SCB UART_FLOW_CTRL: TRIGGER_LEVEL (Bit 0) */ +#define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Msk (0xffUL) /*!< SCB UART_FLOW_CTRL: TRIGGER_LEVEL (Bitfield-Mask: 0xff) */ +#define SCB_UART_FLOW_CTRL_RTS_POLARITY_Pos (16UL) /*!< SCB UART_FLOW_CTRL: RTS_POLARITY (Bit 16) */ +#define SCB_UART_FLOW_CTRL_RTS_POLARITY_Msk (0x10000UL) /*!< SCB UART_FLOW_CTRL: RTS_POLARITY (Bitfield-Mask: 0x01) */ +#define SCB_UART_FLOW_CTRL_CTS_POLARITY_Pos (24UL) /*!< SCB UART_FLOW_CTRL: CTS_POLARITY (Bit 24) */ +#define SCB_UART_FLOW_CTRL_CTS_POLARITY_Msk (0x1000000UL) /*!< SCB UART_FLOW_CTRL: CTS_POLARITY (Bitfield-Mask: 0x01) */ +#define SCB_UART_FLOW_CTRL_CTS_ENABLED_Pos (25UL) /*!< SCB UART_FLOW_CTRL: CTS_ENABLED (Bit 25) */ +#define SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk (0x2000000UL) /*!< SCB UART_FLOW_CTRL: CTS_ENABLED (Bitfield-Mask: 0x01) */ +/* ===================================================== SCB.I2C_CTRL ====================================================== */ +#define SCB_I2C_CTRL_HIGH_PHASE_OVS_Pos (0UL) /*!< SCB I2C_CTRL: HIGH_PHASE_OVS (Bit 0) */ +#define SCB_I2C_CTRL_HIGH_PHASE_OVS_Msk (0xfUL) /*!< SCB I2C_CTRL: HIGH_PHASE_OVS (Bitfield-Mask: 0x0f) */ +#define SCB_I2C_CTRL_LOW_PHASE_OVS_Pos (4UL) /*!< SCB I2C_CTRL: LOW_PHASE_OVS (Bit 4) */ +#define SCB_I2C_CTRL_LOW_PHASE_OVS_Msk (0xf0UL) /*!< SCB I2C_CTRL: LOW_PHASE_OVS (Bitfield-Mask: 0x0f) */ +#define SCB_I2C_CTRL_M_READY_DATA_ACK_Pos (8UL) /*!< SCB I2C_CTRL: M_READY_DATA_ACK (Bit 8) */ +#define SCB_I2C_CTRL_M_READY_DATA_ACK_Msk (0x100UL) /*!< SCB I2C_CTRL: M_READY_DATA_ACK (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Pos (9UL) /*!< SCB I2C_CTRL: M_NOT_READY_DATA_NACK (Bit 9) */ +#define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Msk (0x200UL) /*!< SCB I2C_CTRL: M_NOT_READY_DATA_NACK (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CTRL_S_GENERAL_IGNORE_Pos (11UL) /*!< SCB I2C_CTRL: S_GENERAL_IGNORE (Bit 11) */ +#define SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk (0x800UL) /*!< SCB I2C_CTRL: S_GENERAL_IGNORE (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CTRL_S_READY_ADDR_ACK_Pos (12UL) /*!< SCB I2C_CTRL: S_READY_ADDR_ACK (Bit 12) */ +#define SCB_I2C_CTRL_S_READY_ADDR_ACK_Msk (0x1000UL) /*!< SCB I2C_CTRL: S_READY_ADDR_ACK (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CTRL_S_READY_DATA_ACK_Pos (13UL) /*!< SCB I2C_CTRL: S_READY_DATA_ACK (Bit 13) */ +#define SCB_I2C_CTRL_S_READY_DATA_ACK_Msk (0x2000UL) /*!< SCB I2C_CTRL: S_READY_DATA_ACK (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Pos (14UL) /*!< SCB I2C_CTRL: S_NOT_READY_ADDR_NACK (Bit 14) */ +#define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk (0x4000UL) /*!< SCB I2C_CTRL: S_NOT_READY_ADDR_NACK (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Pos (15UL) /*!< SCB I2C_CTRL: S_NOT_READY_DATA_NACK (Bit 15) */ +#define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk (0x8000UL) /*!< SCB I2C_CTRL: S_NOT_READY_DATA_NACK (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CTRL_LOOPBACK_Pos (16UL) /*!< SCB I2C_CTRL: LOOPBACK (Bit 16) */ +#define SCB_I2C_CTRL_LOOPBACK_Msk (0x10000UL) /*!< SCB I2C_CTRL: LOOPBACK (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CTRL_SLAVE_MODE_Pos (30UL) /*!< SCB I2C_CTRL: SLAVE_MODE (Bit 30) */ +#define SCB_I2C_CTRL_SLAVE_MODE_Msk (0x40000000UL) /*!< SCB I2C_CTRL: SLAVE_MODE (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CTRL_MASTER_MODE_Pos (31UL) /*!< SCB I2C_CTRL: MASTER_MODE (Bit 31) */ +#define SCB_I2C_CTRL_MASTER_MODE_Msk (0x80000000UL) /*!< SCB I2C_CTRL: MASTER_MODE (Bitfield-Mask: 0x01) */ +/* ==================================================== SCB.I2C_STATUS ===================================================== */ +#define SCB_I2C_STATUS_BUS_BUSY_Pos (0UL) /*!< SCB I2C_STATUS: BUS_BUSY (Bit 0) */ +#define SCB_I2C_STATUS_BUS_BUSY_Msk (0x1UL) /*!< SCB I2C_STATUS: BUS_BUSY (Bitfield-Mask: 0x01) */ +#define SCB_I2C_STATUS_I2C_EC_BUSY_Pos (1UL) /*!< SCB I2C_STATUS: I2C_EC_BUSY (Bit 1) */ +#define SCB_I2C_STATUS_I2C_EC_BUSY_Msk (0x2UL) /*!< SCB I2C_STATUS: I2C_EC_BUSY (Bitfield-Mask: 0x01) */ +#define SCB_I2C_STATUS_S_READ_Pos (4UL) /*!< SCB I2C_STATUS: S_READ (Bit 4) */ +#define SCB_I2C_STATUS_S_READ_Msk (0x10UL) /*!< SCB I2C_STATUS: S_READ (Bitfield-Mask: 0x01) */ +#define SCB_I2C_STATUS_M_READ_Pos (5UL) /*!< SCB I2C_STATUS: M_READ (Bit 5) */ +#define SCB_I2C_STATUS_M_READ_Msk (0x20UL) /*!< SCB I2C_STATUS: M_READ (Bitfield-Mask: 0x01) */ +#define SCB_I2C_STATUS_CURR_EZ_ADDR_Pos (8UL) /*!< SCB I2C_STATUS: CURR_EZ_ADDR (Bit 8) */ +#define SCB_I2C_STATUS_CURR_EZ_ADDR_Msk (0xff00UL) /*!< SCB I2C_STATUS: CURR_EZ_ADDR (Bitfield-Mask: 0xff) */ +#define SCB_I2C_STATUS_BASE_EZ_ADDR_Pos (16UL) /*!< SCB I2C_STATUS: BASE_EZ_ADDR (Bit 16) */ +#define SCB_I2C_STATUS_BASE_EZ_ADDR_Msk (0xff0000UL) /*!< SCB I2C_STATUS: BASE_EZ_ADDR (Bitfield-Mask: 0xff) */ +/* ===================================================== SCB.I2C_M_CMD ===================================================== */ +#define SCB_I2C_M_CMD_M_START_Pos (0UL) /*!< SCB I2C_M_CMD: M_START (Bit 0) */ +#define SCB_I2C_M_CMD_M_START_Msk (0x1UL) /*!< SCB I2C_M_CMD: M_START (Bitfield-Mask: 0x01) */ +#define SCB_I2C_M_CMD_M_START_ON_IDLE_Pos (1UL) /*!< SCB I2C_M_CMD: M_START_ON_IDLE (Bit 1) */ +#define SCB_I2C_M_CMD_M_START_ON_IDLE_Msk (0x2UL) /*!< SCB I2C_M_CMD: M_START_ON_IDLE (Bitfield-Mask: 0x01) */ +#define SCB_I2C_M_CMD_M_ACK_Pos (2UL) /*!< SCB I2C_M_CMD: M_ACK (Bit 2) */ +#define SCB_I2C_M_CMD_M_ACK_Msk (0x4UL) /*!< SCB I2C_M_CMD: M_ACK (Bitfield-Mask: 0x01) */ +#define SCB_I2C_M_CMD_M_NACK_Pos (3UL) /*!< SCB I2C_M_CMD: M_NACK (Bit 3) */ +#define SCB_I2C_M_CMD_M_NACK_Msk (0x8UL) /*!< SCB I2C_M_CMD: M_NACK (Bitfield-Mask: 0x01) */ +#define SCB_I2C_M_CMD_M_STOP_Pos (4UL) /*!< SCB I2C_M_CMD: M_STOP (Bit 4) */ +#define SCB_I2C_M_CMD_M_STOP_Msk (0x10UL) /*!< SCB I2C_M_CMD: M_STOP (Bitfield-Mask: 0x01) */ +/* ===================================================== SCB.I2C_S_CMD ===================================================== */ +#define SCB_I2C_S_CMD_S_ACK_Pos (0UL) /*!< SCB I2C_S_CMD: S_ACK (Bit 0) */ +#define SCB_I2C_S_CMD_S_ACK_Msk (0x1UL) /*!< SCB I2C_S_CMD: S_ACK (Bitfield-Mask: 0x01) */ +#define SCB_I2C_S_CMD_S_NACK_Pos (1UL) /*!< SCB I2C_S_CMD: S_NACK (Bit 1) */ +#define SCB_I2C_S_CMD_S_NACK_Msk (0x2UL) /*!< SCB I2C_S_CMD: S_NACK (Bitfield-Mask: 0x01) */ +/* ====================================================== SCB.I2C_CFG ====================================================== */ +#define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Pos (0UL) /*!< SCB I2C_CFG: SDA_IN_FILT_TRIM (Bit 0) */ +#define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Msk (0x3UL) /*!< SCB I2C_CFG: SDA_IN_FILT_TRIM (Bitfield-Mask: 0x03) */ +#define SCB_I2C_CFG_SDA_IN_FILT_SEL_Pos (4UL) /*!< SCB I2C_CFG: SDA_IN_FILT_SEL (Bit 4) */ +#define SCB_I2C_CFG_SDA_IN_FILT_SEL_Msk (0x10UL) /*!< SCB I2C_CFG: SDA_IN_FILT_SEL (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Pos (8UL) /*!< SCB I2C_CFG: SCL_IN_FILT_TRIM (Bit 8) */ +#define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Msk (0x300UL) /*!< SCB I2C_CFG: SCL_IN_FILT_TRIM (Bitfield-Mask: 0x03) */ +#define SCB_I2C_CFG_SCL_IN_FILT_SEL_Pos (12UL) /*!< SCB I2C_CFG: SCL_IN_FILT_SEL (Bit 12) */ +#define SCB_I2C_CFG_SCL_IN_FILT_SEL_Msk (0x1000UL) /*!< SCB I2C_CFG: SCL_IN_FILT_SEL (Bitfield-Mask: 0x01) */ +#define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Pos (16UL) /*!< SCB I2C_CFG: SDA_OUT_FILT0_TRIM (Bit 16) */ +#define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Msk (0x30000UL) /*!< SCB I2C_CFG: SDA_OUT_FILT0_TRIM (Bitfield-Mask: 0x03) */ +#define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Pos (18UL) /*!< SCB I2C_CFG: SDA_OUT_FILT1_TRIM (Bit 18) */ +#define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Msk (0xc0000UL) /*!< SCB I2C_CFG: SDA_OUT_FILT1_TRIM (Bitfield-Mask: 0x03) */ +#define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Pos (20UL) /*!< SCB I2C_CFG: SDA_OUT_FILT2_TRIM (Bit 20) */ +#define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk (0x300000UL) /*!< SCB I2C_CFG: SDA_OUT_FILT2_TRIM (Bitfield-Mask: 0x03) */ +#define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Pos (28UL) /*!< SCB I2C_CFG: SDA_OUT_FILT_SEL (Bit 28) */ +#define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Msk (0x30000000UL) /*!< SCB I2C_CFG: SDA_OUT_FILT_SEL (Bitfield-Mask: 0x03) */ +/* ===================================================== SCB.DDFT_CTRL ===================================================== */ +#define SCB_DDFT_CTRL_DDFT_IN0_SEL_Pos (0UL) /*!< SCB DDFT_CTRL: DDFT_IN0_SEL (Bit 0) */ +#define SCB_DDFT_CTRL_DDFT_IN0_SEL_Msk (0x1UL) /*!< SCB DDFT_CTRL: DDFT_IN0_SEL (Bitfield-Mask: 0x01) */ +#define SCB_DDFT_CTRL_DDFT_IN1_SEL_Pos (4UL) /*!< SCB DDFT_CTRL: DDFT_IN1_SEL (Bit 4) */ +#define SCB_DDFT_CTRL_DDFT_IN1_SEL_Msk (0x10UL) /*!< SCB DDFT_CTRL: DDFT_IN1_SEL (Bitfield-Mask: 0x01) */ +#define SCB_DDFT_CTRL_DDFT_OUT0_SEL_Pos (16UL) /*!< SCB DDFT_CTRL: DDFT_OUT0_SEL (Bit 16) */ +#define SCB_DDFT_CTRL_DDFT_OUT0_SEL_Msk (0x70000UL) /*!< SCB DDFT_CTRL: DDFT_OUT0_SEL (Bitfield-Mask: 0x07) */ +#define SCB_DDFT_CTRL_DDFT_OUT1_SEL_Pos (20UL) /*!< SCB DDFT_CTRL: DDFT_OUT1_SEL (Bit 20) */ +#define SCB_DDFT_CTRL_DDFT_OUT1_SEL_Msk (0x700000UL) /*!< SCB DDFT_CTRL: DDFT_OUT1_SEL (Bitfield-Mask: 0x07) */ +/* ====================================================== SCB.TX_CTRL ====================================================== */ +#define SCB_TX_CTRL_DATA_WIDTH_Pos (0UL) /*!< SCB TX_CTRL: DATA_WIDTH (Bit 0) */ +#define SCB_TX_CTRL_DATA_WIDTH_Msk (0xfUL) /*!< SCB TX_CTRL: DATA_WIDTH (Bitfield-Mask: 0x0f) */ +#define SCB_TX_CTRL_MSB_FIRST_Pos (8UL) /*!< SCB TX_CTRL: MSB_FIRST (Bit 8) */ +#define SCB_TX_CTRL_MSB_FIRST_Msk (0x100UL) /*!< SCB TX_CTRL: MSB_FIRST (Bitfield-Mask: 0x01) */ +/* =================================================== SCB.TX_FIFO_CTRL ==================================================== */ +#define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Pos (0UL) /*!< SCB TX_FIFO_CTRL: TRIGGER_LEVEL (Bit 0) */ +#define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Msk (0xffUL) /*!< SCB TX_FIFO_CTRL: TRIGGER_LEVEL (Bitfield-Mask: 0xff) */ +#define SCB_TX_FIFO_CTRL_CLEAR_Pos (16UL) /*!< SCB TX_FIFO_CTRL: CLEAR (Bit 16) */ +#define SCB_TX_FIFO_CTRL_CLEAR_Msk (0x10000UL) /*!< SCB TX_FIFO_CTRL: CLEAR (Bitfield-Mask: 0x01) */ +#define SCB_TX_FIFO_CTRL_FREEZE_Pos (17UL) /*!< SCB TX_FIFO_CTRL: FREEZE (Bit 17) */ +#define SCB_TX_FIFO_CTRL_FREEZE_Msk (0x20000UL) /*!< SCB TX_FIFO_CTRL: FREEZE (Bitfield-Mask: 0x01) */ +/* ================================================== SCB.TX_FIFO_STATUS =================================================== */ +#define SCB_TX_FIFO_STATUS_USED_Pos (0UL) /*!< SCB TX_FIFO_STATUS: USED (Bit 0) */ +#define SCB_TX_FIFO_STATUS_USED_Msk (0x1ffUL) /*!< SCB TX_FIFO_STATUS: USED (Bitfield-Mask: 0x1ff) */ +#define SCB_TX_FIFO_STATUS_SR_VALID_Pos (15UL) /*!< SCB TX_FIFO_STATUS: SR_VALID (Bit 15) */ +#define SCB_TX_FIFO_STATUS_SR_VALID_Msk (0x8000UL) /*!< SCB TX_FIFO_STATUS: SR_VALID (Bitfield-Mask: 0x01) */ +#define SCB_TX_FIFO_STATUS_RD_PTR_Pos (16UL) /*!< SCB TX_FIFO_STATUS: RD_PTR (Bit 16) */ +#define SCB_TX_FIFO_STATUS_RD_PTR_Msk (0xff0000UL) /*!< SCB TX_FIFO_STATUS: RD_PTR (Bitfield-Mask: 0xff) */ +#define SCB_TX_FIFO_STATUS_WR_PTR_Pos (24UL) /*!< SCB TX_FIFO_STATUS: WR_PTR (Bit 24) */ +#define SCB_TX_FIFO_STATUS_WR_PTR_Msk (0xff000000UL) /*!< SCB TX_FIFO_STATUS: WR_PTR (Bitfield-Mask: 0xff) */ +/* ==================================================== SCB.TX_FIFO_WR ===================================================== */ +#define SCB_TX_FIFO_WR_DATA_Pos (0UL) /*!< SCB TX_FIFO_WR: DATA (Bit 0) */ +#define SCB_TX_FIFO_WR_DATA_Msk (0xffffUL) /*!< SCB TX_FIFO_WR: DATA (Bitfield-Mask: 0xffff) */ +/* ====================================================== SCB.RX_CTRL ====================================================== */ +#define SCB_RX_CTRL_DATA_WIDTH_Pos (0UL) /*!< SCB RX_CTRL: DATA_WIDTH (Bit 0) */ +#define SCB_RX_CTRL_DATA_WIDTH_Msk (0xfUL) /*!< SCB RX_CTRL: DATA_WIDTH (Bitfield-Mask: 0x0f) */ +#define SCB_RX_CTRL_MSB_FIRST_Pos (8UL) /*!< SCB RX_CTRL: MSB_FIRST (Bit 8) */ +#define SCB_RX_CTRL_MSB_FIRST_Msk (0x100UL) /*!< SCB RX_CTRL: MSB_FIRST (Bitfield-Mask: 0x01) */ +#define SCB_RX_CTRL_MEDIAN_Pos (9UL) /*!< SCB RX_CTRL: MEDIAN (Bit 9) */ +#define SCB_RX_CTRL_MEDIAN_Msk (0x200UL) /*!< SCB RX_CTRL: MEDIAN (Bitfield-Mask: 0x01) */ +/* =================================================== SCB.RX_FIFO_CTRL ==================================================== */ +#define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos (0UL) /*!< SCB RX_FIFO_CTRL: TRIGGER_LEVEL (Bit 0) */ +#define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk (0xffUL) /*!< SCB RX_FIFO_CTRL: TRIGGER_LEVEL (Bitfield-Mask: 0xff) */ +#define SCB_RX_FIFO_CTRL_CLEAR_Pos (16UL) /*!< SCB RX_FIFO_CTRL: CLEAR (Bit 16) */ +#define SCB_RX_FIFO_CTRL_CLEAR_Msk (0x10000UL) /*!< SCB RX_FIFO_CTRL: CLEAR (Bitfield-Mask: 0x01) */ +#define SCB_RX_FIFO_CTRL_FREEZE_Pos (17UL) /*!< SCB RX_FIFO_CTRL: FREEZE (Bit 17) */ +#define SCB_RX_FIFO_CTRL_FREEZE_Msk (0x20000UL) /*!< SCB RX_FIFO_CTRL: FREEZE (Bitfield-Mask: 0x01) */ +/* ================================================== SCB.RX_FIFO_STATUS =================================================== */ +#define SCB_RX_FIFO_STATUS_USED_Pos (0UL) /*!< SCB RX_FIFO_STATUS: USED (Bit 0) */ +#define SCB_RX_FIFO_STATUS_USED_Msk (0x1ffUL) /*!< SCB RX_FIFO_STATUS: USED (Bitfield-Mask: 0x1ff) */ +#define SCB_RX_FIFO_STATUS_SR_VALID_Pos (15UL) /*!< SCB RX_FIFO_STATUS: SR_VALID (Bit 15) */ +#define SCB_RX_FIFO_STATUS_SR_VALID_Msk (0x8000UL) /*!< SCB RX_FIFO_STATUS: SR_VALID (Bitfield-Mask: 0x01) */ +#define SCB_RX_FIFO_STATUS_RD_PTR_Pos (16UL) /*!< SCB RX_FIFO_STATUS: RD_PTR (Bit 16) */ +#define SCB_RX_FIFO_STATUS_RD_PTR_Msk (0xff0000UL) /*!< SCB RX_FIFO_STATUS: RD_PTR (Bitfield-Mask: 0xff) */ +#define SCB_RX_FIFO_STATUS_WR_PTR_Pos (24UL) /*!< SCB RX_FIFO_STATUS: WR_PTR (Bit 24) */ +#define SCB_RX_FIFO_STATUS_WR_PTR_Msk (0xff000000UL) /*!< SCB RX_FIFO_STATUS: WR_PTR (Bitfield-Mask: 0xff) */ +/* ===================================================== SCB.RX_MATCH ====================================================== */ +#define SCB_RX_MATCH_ADDR_Pos (0UL) /*!< SCB RX_MATCH: ADDR (Bit 0) */ +#define SCB_RX_MATCH_ADDR_Msk (0xffUL) /*!< SCB RX_MATCH: ADDR (Bitfield-Mask: 0xff) */ +#define SCB_RX_MATCH_MASK_Pos (16UL) /*!< SCB RX_MATCH: MASK (Bit 16) */ +#define SCB_RX_MATCH_MASK_Msk (0xff0000UL) /*!< SCB RX_MATCH: MASK (Bitfield-Mask: 0xff) */ +/* ==================================================== SCB.RX_FIFO_RD ===================================================== */ +#define SCB_RX_FIFO_RD_DATA_Pos (0UL) /*!< SCB RX_FIFO_RD: DATA (Bit 0) */ +#define SCB_RX_FIFO_RD_DATA_Msk (0xffffUL) /*!< SCB RX_FIFO_RD: DATA (Bitfield-Mask: 0xffff) */ +/* ================================================= SCB.RX_FIFO_RD_SILENT ================================================= */ +#define SCB_RX_FIFO_RD_SILENT_DATA_Pos (0UL) /*!< SCB RX_FIFO_RD_SILENT: DATA (Bit 0) */ +#define SCB_RX_FIFO_RD_SILENT_DATA_Msk (0xffffUL) /*!< SCB RX_FIFO_RD_SILENT: DATA (Bitfield-Mask: 0xffff) */ +/* ====================================================== SCB.EZ_DATA ====================================================== */ +#define SCB_EZ_DATA_EZ_DATA_Pos (0UL) /*!< SCB EZ_DATA: EZ_DATA (Bit 0) */ +#define SCB_EZ_DATA_EZ_DATA_Msk (0xffUL) /*!< SCB EZ_DATA: EZ_DATA (Bitfield-Mask: 0xff) */ +/* ==================================================== SCB.INTR_CAUSE ===================================================== */ +#define SCB_INTR_CAUSE_M_Pos (0UL) /*!< SCB INTR_CAUSE: M (Bit 0) */ +#define SCB_INTR_CAUSE_M_Msk (0x1UL) /*!< SCB INTR_CAUSE: M (Bitfield-Mask: 0x01) */ +#define SCB_INTR_CAUSE_S_Pos (1UL) /*!< SCB INTR_CAUSE: S (Bit 1) */ +#define SCB_INTR_CAUSE_S_Msk (0x2UL) /*!< SCB INTR_CAUSE: S (Bitfield-Mask: 0x01) */ +#define SCB_INTR_CAUSE_TX_Pos (2UL) /*!< SCB INTR_CAUSE: TX (Bit 2) */ +#define SCB_INTR_CAUSE_TX_Msk (0x4UL) /*!< SCB INTR_CAUSE: TX (Bitfield-Mask: 0x01) */ +#define SCB_INTR_CAUSE_RX_Pos (3UL) /*!< SCB INTR_CAUSE: RX (Bit 3) */ +#define SCB_INTR_CAUSE_RX_Msk (0x8UL) /*!< SCB INTR_CAUSE: RX (Bitfield-Mask: 0x01) */ +#define SCB_INTR_CAUSE_I2C_EC_Pos (4UL) /*!< SCB INTR_CAUSE: I2C_EC (Bit 4) */ +#define SCB_INTR_CAUSE_I2C_EC_Msk (0x10UL) /*!< SCB INTR_CAUSE: I2C_EC (Bitfield-Mask: 0x01) */ +#define SCB_INTR_CAUSE_SPI_EC_Pos (5UL) /*!< SCB INTR_CAUSE: SPI_EC (Bit 5) */ +#define SCB_INTR_CAUSE_SPI_EC_Msk (0x20UL) /*!< SCB INTR_CAUSE: SPI_EC (Bitfield-Mask: 0x01) */ +/* ==================================================== SCB.INTR_I2C_EC ==================================================== */ +#define SCB_INTR_I2C_EC_WAKE_UP_Pos (0UL) /*!< SCB INTR_I2C_EC: WAKE_UP (Bit 0) */ +#define SCB_INTR_I2C_EC_WAKE_UP_Msk (0x1UL) /*!< SCB INTR_I2C_EC: WAKE_UP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_I2C_EC_EZ_STOP_Pos (1UL) /*!< SCB INTR_I2C_EC: EZ_STOP (Bit 1) */ +#define SCB_INTR_I2C_EC_EZ_STOP_Msk (0x2UL) /*!< SCB INTR_I2C_EC: EZ_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Pos (2UL) /*!< SCB INTR_I2C_EC: EZ_WRITE_STOP (Bit 2) */ +#define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Msk (0x4UL) /*!< SCB INTR_I2C_EC: EZ_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_I2C_EC_EZ_READ_STOP_Pos (3UL) /*!< SCB INTR_I2C_EC: EZ_READ_STOP (Bit 3) */ +#define SCB_INTR_I2C_EC_EZ_READ_STOP_Msk (0x8UL) /*!< SCB INTR_I2C_EC: EZ_READ_STOP (Bitfield-Mask: 0x01) */ +/* ================================================= SCB.INTR_I2C_EC_MASK ================================================== */ +#define SCB_INTR_I2C_EC_MASK_WAKE_UP_Pos (0UL) /*!< SCB INTR_I2C_EC_MASK: WAKE_UP (Bit 0) */ +#define SCB_INTR_I2C_EC_MASK_WAKE_UP_Msk (0x1UL) /*!< SCB INTR_I2C_EC_MASK: WAKE_UP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_I2C_EC_MASK_EZ_STOP_Pos (1UL) /*!< SCB INTR_I2C_EC_MASK: EZ_STOP (Bit 1) */ +#define SCB_INTR_I2C_EC_MASK_EZ_STOP_Msk (0x2UL) /*!< SCB INTR_I2C_EC_MASK: EZ_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Pos (2UL) /*!< SCB INTR_I2C_EC_MASK: EZ_WRITE_STOP (Bit 2) */ +#define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Msk (0x4UL) /*!< SCB INTR_I2C_EC_MASK: EZ_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Pos (3UL) /*!< SCB INTR_I2C_EC_MASK: EZ_READ_STOP (Bit 3) */ +#define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Msk (0x8UL) /*!< SCB INTR_I2C_EC_MASK: EZ_READ_STOP (Bitfield-Mask: 0x01) */ +/* ================================================ SCB.INTR_I2C_EC_MASKED ================================================= */ +#define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Pos (0UL) /*!< SCB INTR_I2C_EC_MASKED: WAKE_UP (Bit 0) */ +#define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Msk (0x1UL) /*!< SCB INTR_I2C_EC_MASKED: WAKE_UP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Pos (1UL) /*!< SCB INTR_I2C_EC_MASKED: EZ_STOP (Bit 1) */ +#define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Msk (0x2UL) /*!< SCB INTR_I2C_EC_MASKED: EZ_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Pos (2UL) /*!< SCB INTR_I2C_EC_MASKED: EZ_WRITE_STOP (Bit 2) */ +#define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Msk (0x4UL) /*!< SCB INTR_I2C_EC_MASKED: EZ_WRITE_STOP (Bitfield-Mask: 0x01)*/ +#define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Pos (3UL) /*!< SCB INTR_I2C_EC_MASKED: EZ_READ_STOP (Bit 3) */ +#define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Msk (0x8UL) /*!< SCB INTR_I2C_EC_MASKED: EZ_READ_STOP (Bitfield-Mask: 0x01)*/ +/* ==================================================== SCB.INTR_SPI_EC ==================================================== */ +#define SCB_INTR_SPI_EC_WAKE_UP_Pos (0UL) /*!< SCB INTR_SPI_EC: WAKE_UP (Bit 0) */ +#define SCB_INTR_SPI_EC_WAKE_UP_Msk (0x1UL) /*!< SCB INTR_SPI_EC: WAKE_UP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_SPI_EC_EZ_STOP_Pos (1UL) /*!< SCB INTR_SPI_EC: EZ_STOP (Bit 1) */ +#define SCB_INTR_SPI_EC_EZ_STOP_Msk (0x2UL) /*!< SCB INTR_SPI_EC: EZ_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Pos (2UL) /*!< SCB INTR_SPI_EC: EZ_WRITE_STOP (Bit 2) */ +#define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Msk (0x4UL) /*!< SCB INTR_SPI_EC: EZ_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_SPI_EC_EZ_READ_STOP_Pos (3UL) /*!< SCB INTR_SPI_EC: EZ_READ_STOP (Bit 3) */ +#define SCB_INTR_SPI_EC_EZ_READ_STOP_Msk (0x8UL) /*!< SCB INTR_SPI_EC: EZ_READ_STOP (Bitfield-Mask: 0x01) */ +/* ================================================= SCB.INTR_SPI_EC_MASK ================================================== */ +#define SCB_INTR_SPI_EC_MASK_WAKE_UP_Pos (0UL) /*!< SCB INTR_SPI_EC_MASK: WAKE_UP (Bit 0) */ +#define SCB_INTR_SPI_EC_MASK_WAKE_UP_Msk (0x1UL) /*!< SCB INTR_SPI_EC_MASK: WAKE_UP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_SPI_EC_MASK_EZ_STOP_Pos (1UL) /*!< SCB INTR_SPI_EC_MASK: EZ_STOP (Bit 1) */ +#define SCB_INTR_SPI_EC_MASK_EZ_STOP_Msk (0x2UL) /*!< SCB INTR_SPI_EC_MASK: EZ_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Pos (2UL) /*!< SCB INTR_SPI_EC_MASK: EZ_WRITE_STOP (Bit 2) */ +#define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Msk (0x4UL) /*!< SCB INTR_SPI_EC_MASK: EZ_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Pos (3UL) /*!< SCB INTR_SPI_EC_MASK: EZ_READ_STOP (Bit 3) */ +#define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Msk (0x8UL) /*!< SCB INTR_SPI_EC_MASK: EZ_READ_STOP (Bitfield-Mask: 0x01) */ +/* ================================================ SCB.INTR_SPI_EC_MASKED ================================================= */ +#define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Pos (0UL) /*!< SCB INTR_SPI_EC_MASKED: WAKE_UP (Bit 0) */ +#define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Msk (0x1UL) /*!< SCB INTR_SPI_EC_MASKED: WAKE_UP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Pos (1UL) /*!< SCB INTR_SPI_EC_MASKED: EZ_STOP (Bit 1) */ +#define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Msk (0x2UL) /*!< SCB INTR_SPI_EC_MASKED: EZ_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Pos (2UL) /*!< SCB INTR_SPI_EC_MASKED: EZ_WRITE_STOP (Bit 2) */ +#define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Msk (0x4UL) /*!< SCB INTR_SPI_EC_MASKED: EZ_WRITE_STOP (Bitfield-Mask: 0x01)*/ +#define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Pos (3UL) /*!< SCB INTR_SPI_EC_MASKED: EZ_READ_STOP (Bit 3) */ +#define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Msk (0x8UL) /*!< SCB INTR_SPI_EC_MASKED: EZ_READ_STOP (Bitfield-Mask: 0x01)*/ +/* ====================================================== SCB.INTR_M ======================================================= */ +#define SCB_INTR_M_I2C_ARB_LOST_Pos (0UL) /*!< SCB INTR_M: I2C_ARB_LOST (Bit 0) */ +#define SCB_INTR_M_I2C_ARB_LOST_Msk (0x1UL) /*!< SCB INTR_M: I2C_ARB_LOST (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_I2C_NACK_Pos (1UL) /*!< SCB INTR_M: I2C_NACK (Bit 1) */ +#define SCB_INTR_M_I2C_NACK_Msk (0x2UL) /*!< SCB INTR_M: I2C_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_I2C_ACK_Pos (2UL) /*!< SCB INTR_M: I2C_ACK (Bit 2) */ +#define SCB_INTR_M_I2C_ACK_Msk (0x4UL) /*!< SCB INTR_M: I2C_ACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_I2C_STOP_Pos (4UL) /*!< SCB INTR_M: I2C_STOP (Bit 4) */ +#define SCB_INTR_M_I2C_STOP_Msk (0x10UL) /*!< SCB INTR_M: I2C_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_I2C_BUS_ERROR_Pos (8UL) /*!< SCB INTR_M: I2C_BUS_ERROR (Bit 8) */ +#define SCB_INTR_M_I2C_BUS_ERROR_Msk (0x100UL) /*!< SCB INTR_M: I2C_BUS_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_SPI_DONE_Pos (9UL) /*!< SCB INTR_M: SPI_DONE (Bit 9) */ +#define SCB_INTR_M_SPI_DONE_Msk (0x200UL) /*!< SCB INTR_M: SPI_DONE (Bitfield-Mask: 0x01) */ +/* ==================================================== SCB.INTR_M_SET ===================================================== */ +#define SCB_INTR_M_SET_I2C_ARB_LOST_Pos (0UL) /*!< SCB INTR_M_SET: I2C_ARB_LOST (Bit 0) */ +#define SCB_INTR_M_SET_I2C_ARB_LOST_Msk (0x1UL) /*!< SCB INTR_M_SET: I2C_ARB_LOST (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_SET_I2C_NACK_Pos (1UL) /*!< SCB INTR_M_SET: I2C_NACK (Bit 1) */ +#define SCB_INTR_M_SET_I2C_NACK_Msk (0x2UL) /*!< SCB INTR_M_SET: I2C_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_SET_I2C_ACK_Pos (2UL) /*!< SCB INTR_M_SET: I2C_ACK (Bit 2) */ +#define SCB_INTR_M_SET_I2C_ACK_Msk (0x4UL) /*!< SCB INTR_M_SET: I2C_ACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_SET_I2C_STOP_Pos (4UL) /*!< SCB INTR_M_SET: I2C_STOP (Bit 4) */ +#define SCB_INTR_M_SET_I2C_STOP_Msk (0x10UL) /*!< SCB INTR_M_SET: I2C_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_SET_I2C_BUS_ERROR_Pos (8UL) /*!< SCB INTR_M_SET: I2C_BUS_ERROR (Bit 8) */ +#define SCB_INTR_M_SET_I2C_BUS_ERROR_Msk (0x100UL) /*!< SCB INTR_M_SET: I2C_BUS_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_SET_SPI_DONE_Pos (9UL) /*!< SCB INTR_M_SET: SPI_DONE (Bit 9) */ +#define SCB_INTR_M_SET_SPI_DONE_Msk (0x200UL) /*!< SCB INTR_M_SET: SPI_DONE (Bitfield-Mask: 0x01) */ +/* ==================================================== SCB.INTR_M_MASK ==================================================== */ +#define SCB_INTR_M_MASK_I2C_ARB_LOST_Pos (0UL) /*!< SCB INTR_M_MASK: I2C_ARB_LOST (Bit 0) */ +#define SCB_INTR_M_MASK_I2C_ARB_LOST_Msk (0x1UL) /*!< SCB INTR_M_MASK: I2C_ARB_LOST (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_MASK_I2C_NACK_Pos (1UL) /*!< SCB INTR_M_MASK: I2C_NACK (Bit 1) */ +#define SCB_INTR_M_MASK_I2C_NACK_Msk (0x2UL) /*!< SCB INTR_M_MASK: I2C_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_MASK_I2C_ACK_Pos (2UL) /*!< SCB INTR_M_MASK: I2C_ACK (Bit 2) */ +#define SCB_INTR_M_MASK_I2C_ACK_Msk (0x4UL) /*!< SCB INTR_M_MASK: I2C_ACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_MASK_I2C_STOP_Pos (4UL) /*!< SCB INTR_M_MASK: I2C_STOP (Bit 4) */ +#define SCB_INTR_M_MASK_I2C_STOP_Msk (0x10UL) /*!< SCB INTR_M_MASK: I2C_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_MASK_I2C_BUS_ERROR_Pos (8UL) /*!< SCB INTR_M_MASK: I2C_BUS_ERROR (Bit 8) */ +#define SCB_INTR_M_MASK_I2C_BUS_ERROR_Msk (0x100UL) /*!< SCB INTR_M_MASK: I2C_BUS_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_MASK_SPI_DONE_Pos (9UL) /*!< SCB INTR_M_MASK: SPI_DONE (Bit 9) */ +#define SCB_INTR_M_MASK_SPI_DONE_Msk (0x200UL) /*!< SCB INTR_M_MASK: SPI_DONE (Bitfield-Mask: 0x01) */ +/* =================================================== SCB.INTR_M_MASKED =================================================== */ +#define SCB_INTR_M_MASKED_I2C_ARB_LOST_Pos (0UL) /*!< SCB INTR_M_MASKED: I2C_ARB_LOST (Bit 0) */ +#define SCB_INTR_M_MASKED_I2C_ARB_LOST_Msk (0x1UL) /*!< SCB INTR_M_MASKED: I2C_ARB_LOST (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_MASKED_I2C_NACK_Pos (1UL) /*!< SCB INTR_M_MASKED: I2C_NACK (Bit 1) */ +#define SCB_INTR_M_MASKED_I2C_NACK_Msk (0x2UL) /*!< SCB INTR_M_MASKED: I2C_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_MASKED_I2C_ACK_Pos (2UL) /*!< SCB INTR_M_MASKED: I2C_ACK (Bit 2) */ +#define SCB_INTR_M_MASKED_I2C_ACK_Msk (0x4UL) /*!< SCB INTR_M_MASKED: I2C_ACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_MASKED_I2C_STOP_Pos (4UL) /*!< SCB INTR_M_MASKED: I2C_STOP (Bit 4) */ +#define SCB_INTR_M_MASKED_I2C_STOP_Msk (0x10UL) /*!< SCB INTR_M_MASKED: I2C_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Pos (8UL) /*!< SCB INTR_M_MASKED: I2C_BUS_ERROR (Bit 8) */ +#define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Msk (0x100UL) /*!< SCB INTR_M_MASKED: I2C_BUS_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_M_MASKED_SPI_DONE_Pos (9UL) /*!< SCB INTR_M_MASKED: SPI_DONE (Bit 9) */ +#define SCB_INTR_M_MASKED_SPI_DONE_Msk (0x200UL) /*!< SCB INTR_M_MASKED: SPI_DONE (Bitfield-Mask: 0x01) */ +/* ====================================================== SCB.INTR_S ======================================================= */ +#define SCB_INTR_S_I2C_ARB_LOST_Pos (0UL) /*!< SCB INTR_S: I2C_ARB_LOST (Bit 0) */ +#define SCB_INTR_S_I2C_ARB_LOST_Msk (0x1UL) /*!< SCB INTR_S: I2C_ARB_LOST (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_I2C_NACK_Pos (1UL) /*!< SCB INTR_S: I2C_NACK (Bit 1) */ +#define SCB_INTR_S_I2C_NACK_Msk (0x2UL) /*!< SCB INTR_S: I2C_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_I2C_ACK_Pos (2UL) /*!< SCB INTR_S: I2C_ACK (Bit 2) */ +#define SCB_INTR_S_I2C_ACK_Msk (0x4UL) /*!< SCB INTR_S: I2C_ACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_I2C_WRITE_STOP_Pos (3UL) /*!< SCB INTR_S: I2C_WRITE_STOP (Bit 3) */ +#define SCB_INTR_S_I2C_WRITE_STOP_Msk (0x8UL) /*!< SCB INTR_S: I2C_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_I2C_STOP_Pos (4UL) /*!< SCB INTR_S: I2C_STOP (Bit 4) */ +#define SCB_INTR_S_I2C_STOP_Msk (0x10UL) /*!< SCB INTR_S: I2C_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_I2C_START_Pos (5UL) /*!< SCB INTR_S: I2C_START (Bit 5) */ +#define SCB_INTR_S_I2C_START_Msk (0x20UL) /*!< SCB INTR_S: I2C_START (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_I2C_ADDR_MATCH_Pos (6UL) /*!< SCB INTR_S: I2C_ADDR_MATCH (Bit 6) */ +#define SCB_INTR_S_I2C_ADDR_MATCH_Msk (0x40UL) /*!< SCB INTR_S: I2C_ADDR_MATCH (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_I2C_GENERAL_Pos (7UL) /*!< SCB INTR_S: I2C_GENERAL (Bit 7) */ +#define SCB_INTR_S_I2C_GENERAL_Msk (0x80UL) /*!< SCB INTR_S: I2C_GENERAL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_I2C_BUS_ERROR_Pos (8UL) /*!< SCB INTR_S: I2C_BUS_ERROR (Bit 8) */ +#define SCB_INTR_S_I2C_BUS_ERROR_Msk (0x100UL) /*!< SCB INTR_S: I2C_BUS_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SPI_EZ_WRITE_STOP_Pos (9UL) /*!< SCB INTR_S: SPI_EZ_WRITE_STOP (Bit 9) */ +#define SCB_INTR_S_SPI_EZ_WRITE_STOP_Msk (0x200UL) /*!< SCB INTR_S: SPI_EZ_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SPI_EZ_STOP_Pos (10UL) /*!< SCB INTR_S: SPI_EZ_STOP (Bit 10) */ +#define SCB_INTR_S_SPI_EZ_STOP_Msk (0x400UL) /*!< SCB INTR_S: SPI_EZ_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SPI_BUS_ERROR_Pos (11UL) /*!< SCB INTR_S: SPI_BUS_ERROR (Bit 11) */ +#define SCB_INTR_S_SPI_BUS_ERROR_Msk (0x800UL) /*!< SCB INTR_S: SPI_BUS_ERROR (Bitfield-Mask: 0x01) */ +/* ==================================================== SCB.INTR_S_SET ===================================================== */ +#define SCB_INTR_S_SET_I2C_ARB_LOST_Pos (0UL) /*!< SCB INTR_S_SET: I2C_ARB_LOST (Bit 0) */ +#define SCB_INTR_S_SET_I2C_ARB_LOST_Msk (0x1UL) /*!< SCB INTR_S_SET: I2C_ARB_LOST (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_I2C_NACK_Pos (1UL) /*!< SCB INTR_S_SET: I2C_NACK (Bit 1) */ +#define SCB_INTR_S_SET_I2C_NACK_Msk (0x2UL) /*!< SCB INTR_S_SET: I2C_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_I2C_ACK_Pos (2UL) /*!< SCB INTR_S_SET: I2C_ACK (Bit 2) */ +#define SCB_INTR_S_SET_I2C_ACK_Msk (0x4UL) /*!< SCB INTR_S_SET: I2C_ACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_I2C_WRITE_STOP_Pos (3UL) /*!< SCB INTR_S_SET: I2C_WRITE_STOP (Bit 3) */ +#define SCB_INTR_S_SET_I2C_WRITE_STOP_Msk (0x8UL) /*!< SCB INTR_S_SET: I2C_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_I2C_STOP_Pos (4UL) /*!< SCB INTR_S_SET: I2C_STOP (Bit 4) */ +#define SCB_INTR_S_SET_I2C_STOP_Msk (0x10UL) /*!< SCB INTR_S_SET: I2C_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_I2C_START_Pos (5UL) /*!< SCB INTR_S_SET: I2C_START (Bit 5) */ +#define SCB_INTR_S_SET_I2C_START_Msk (0x20UL) /*!< SCB INTR_S_SET: I2C_START (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_I2C_ADDR_MATCH_Pos (6UL) /*!< SCB INTR_S_SET: I2C_ADDR_MATCH (Bit 6) */ +#define SCB_INTR_S_SET_I2C_ADDR_MATCH_Msk (0x40UL) /*!< SCB INTR_S_SET: I2C_ADDR_MATCH (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_I2C_GENERAL_Pos (7UL) /*!< SCB INTR_S_SET: I2C_GENERAL (Bit 7) */ +#define SCB_INTR_S_SET_I2C_GENERAL_Msk (0x80UL) /*!< SCB INTR_S_SET: I2C_GENERAL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_I2C_BUS_ERROR_Pos (8UL) /*!< SCB INTR_S_SET: I2C_BUS_ERROR (Bit 8) */ +#define SCB_INTR_S_SET_I2C_BUS_ERROR_Msk (0x100UL) /*!< SCB INTR_S_SET: I2C_BUS_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Pos (9UL) /*!< SCB INTR_S_SET: SPI_EZ_WRITE_STOP (Bit 9) */ +#define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Msk (0x200UL) /*!< SCB INTR_S_SET: SPI_EZ_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_SPI_EZ_STOP_Pos (10UL) /*!< SCB INTR_S_SET: SPI_EZ_STOP (Bit 10) */ +#define SCB_INTR_S_SET_SPI_EZ_STOP_Msk (0x400UL) /*!< SCB INTR_S_SET: SPI_EZ_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_SET_SPI_BUS_ERROR_Pos (11UL) /*!< SCB INTR_S_SET: SPI_BUS_ERROR (Bit 11) */ +#define SCB_INTR_S_SET_SPI_BUS_ERROR_Msk (0x800UL) /*!< SCB INTR_S_SET: SPI_BUS_ERROR (Bitfield-Mask: 0x01) */ +/* ==================================================== SCB.INTR_S_MASK ==================================================== */ +#define SCB_INTR_S_MASK_I2C_ARB_LOST_Pos (0UL) /*!< SCB INTR_S_MASK: I2C_ARB_LOST (Bit 0) */ +#define SCB_INTR_S_MASK_I2C_ARB_LOST_Msk (0x1UL) /*!< SCB INTR_S_MASK: I2C_ARB_LOST (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_I2C_NACK_Pos (1UL) /*!< SCB INTR_S_MASK: I2C_NACK (Bit 1) */ +#define SCB_INTR_S_MASK_I2C_NACK_Msk (0x2UL) /*!< SCB INTR_S_MASK: I2C_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_I2C_ACK_Pos (2UL) /*!< SCB INTR_S_MASK: I2C_ACK (Bit 2) */ +#define SCB_INTR_S_MASK_I2C_ACK_Msk (0x4UL) /*!< SCB INTR_S_MASK: I2C_ACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_I2C_WRITE_STOP_Pos (3UL) /*!< SCB INTR_S_MASK: I2C_WRITE_STOP (Bit 3) */ +#define SCB_INTR_S_MASK_I2C_WRITE_STOP_Msk (0x8UL) /*!< SCB INTR_S_MASK: I2C_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_I2C_STOP_Pos (4UL) /*!< SCB INTR_S_MASK: I2C_STOP (Bit 4) */ +#define SCB_INTR_S_MASK_I2C_STOP_Msk (0x10UL) /*!< SCB INTR_S_MASK: I2C_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_I2C_START_Pos (5UL) /*!< SCB INTR_S_MASK: I2C_START (Bit 5) */ +#define SCB_INTR_S_MASK_I2C_START_Msk (0x20UL) /*!< SCB INTR_S_MASK: I2C_START (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Pos (6UL) /*!< SCB INTR_S_MASK: I2C_ADDR_MATCH (Bit 6) */ +#define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Msk (0x40UL) /*!< SCB INTR_S_MASK: I2C_ADDR_MATCH (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_I2C_GENERAL_Pos (7UL) /*!< SCB INTR_S_MASK: I2C_GENERAL (Bit 7) */ +#define SCB_INTR_S_MASK_I2C_GENERAL_Msk (0x80UL) /*!< SCB INTR_S_MASK: I2C_GENERAL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_I2C_BUS_ERROR_Pos (8UL) /*!< SCB INTR_S_MASK: I2C_BUS_ERROR (Bit 8) */ +#define SCB_INTR_S_MASK_I2C_BUS_ERROR_Msk (0x100UL) /*!< SCB INTR_S_MASK: I2C_BUS_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Pos (9UL) /*!< SCB INTR_S_MASK: SPI_EZ_WRITE_STOP (Bit 9) */ +#define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Msk (0x200UL) /*!< SCB INTR_S_MASK: SPI_EZ_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_SPI_EZ_STOP_Pos (10UL) /*!< SCB INTR_S_MASK: SPI_EZ_STOP (Bit 10) */ +#define SCB_INTR_S_MASK_SPI_EZ_STOP_Msk (0x400UL) /*!< SCB INTR_S_MASK: SPI_EZ_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASK_SPI_BUS_ERROR_Pos (11UL) /*!< SCB INTR_S_MASK: SPI_BUS_ERROR (Bit 11) */ +#define SCB_INTR_S_MASK_SPI_BUS_ERROR_Msk (0x800UL) /*!< SCB INTR_S_MASK: SPI_BUS_ERROR (Bitfield-Mask: 0x01) */ +/* =================================================== SCB.INTR_S_MASKED =================================================== */ +#define SCB_INTR_S_MASKED_I2C_ARB_LOST_Pos (0UL) /*!< SCB INTR_S_MASKED: I2C_ARB_LOST (Bit 0) */ +#define SCB_INTR_S_MASKED_I2C_ARB_LOST_Msk (0x1UL) /*!< SCB INTR_S_MASKED: I2C_ARB_LOST (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASKED_I2C_NACK_Pos (1UL) /*!< SCB INTR_S_MASKED: I2C_NACK (Bit 1) */ +#define SCB_INTR_S_MASKED_I2C_NACK_Msk (0x2UL) /*!< SCB INTR_S_MASKED: I2C_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASKED_I2C_ACK_Pos (2UL) /*!< SCB INTR_S_MASKED: I2C_ACK (Bit 2) */ +#define SCB_INTR_S_MASKED_I2C_ACK_Msk (0x4UL) /*!< SCB INTR_S_MASKED: I2C_ACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Pos (3UL) /*!< SCB INTR_S_MASKED: I2C_WRITE_STOP (Bit 3) */ +#define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Msk (0x8UL) /*!< SCB INTR_S_MASKED: I2C_WRITE_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASKED_I2C_STOP_Pos (4UL) /*!< SCB INTR_S_MASKED: I2C_STOP (Bit 4) */ +#define SCB_INTR_S_MASKED_I2C_STOP_Msk (0x10UL) /*!< SCB INTR_S_MASKED: I2C_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASKED_I2C_START_Pos (5UL) /*!< SCB INTR_S_MASKED: I2C_START (Bit 5) */ +#define SCB_INTR_S_MASKED_I2C_START_Msk (0x20UL) /*!< SCB INTR_S_MASKED: I2C_START (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Pos (6UL) /*!< SCB INTR_S_MASKED: I2C_ADDR_MATCH (Bit 6) */ +#define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Msk (0x40UL) /*!< SCB INTR_S_MASKED: I2C_ADDR_MATCH (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASKED_I2C_GENERAL_Pos (7UL) /*!< SCB INTR_S_MASKED: I2C_GENERAL (Bit 7) */ +#define SCB_INTR_S_MASKED_I2C_GENERAL_Msk (0x80UL) /*!< SCB INTR_S_MASKED: I2C_GENERAL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Pos (8UL) /*!< SCB INTR_S_MASKED: I2C_BUS_ERROR (Bit 8) */ +#define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Msk (0x100UL) /*!< SCB INTR_S_MASKED: I2C_BUS_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Pos (9UL) /*!< SCB INTR_S_MASKED: SPI_EZ_WRITE_STOP (Bit 9) */ +#define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Msk (0x200UL) /*!< SCB INTR_S_MASKED: SPI_EZ_WRITE_STOP (Bitfield-Mask: 0x01)*/ +#define SCB_INTR_S_MASKED_SPI_EZ_STOP_Pos (10UL) /*!< SCB INTR_S_MASKED: SPI_EZ_STOP (Bit 10) */ +#define SCB_INTR_S_MASKED_SPI_EZ_STOP_Msk (0x400UL) /*!< SCB INTR_S_MASKED: SPI_EZ_STOP (Bitfield-Mask: 0x01) */ +#define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Pos (11UL) /*!< SCB INTR_S_MASKED: SPI_BUS_ERROR (Bit 11) */ +#define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Msk (0x800UL) /*!< SCB INTR_S_MASKED: SPI_BUS_ERROR (Bitfield-Mask: 0x01) */ +/* ====================================================== SCB.INTR_TX ====================================================== */ +#define SCB_INTR_TX_TRIGGER_Pos (0UL) /*!< SCB INTR_TX: TRIGGER (Bit 0) */ +#define SCB_INTR_TX_TRIGGER_Msk (0x1UL) /*!< SCB INTR_TX: TRIGGER (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_NOT_FULL_Pos (1UL) /*!< SCB INTR_TX: NOT_FULL (Bit 1) */ +#define SCB_INTR_TX_NOT_FULL_Msk (0x2UL) /*!< SCB INTR_TX: NOT_FULL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_EMPTY_Pos (4UL) /*!< SCB INTR_TX: EMPTY (Bit 4) */ +#define SCB_INTR_TX_EMPTY_Msk (0x10UL) /*!< SCB INTR_TX: EMPTY (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_OVERFLOW_Pos (5UL) /*!< SCB INTR_TX: OVERFLOW (Bit 5) */ +#define SCB_INTR_TX_OVERFLOW_Msk (0x20UL) /*!< SCB INTR_TX: OVERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_UNDERFLOW_Pos (6UL) /*!< SCB INTR_TX: UNDERFLOW (Bit 6) */ +#define SCB_INTR_TX_UNDERFLOW_Msk (0x40UL) /*!< SCB INTR_TX: UNDERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_BLOCKED_Pos (7UL) /*!< SCB INTR_TX: BLOCKED (Bit 7) */ +#define SCB_INTR_TX_BLOCKED_Msk (0x80UL) /*!< SCB INTR_TX: BLOCKED (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_UART_NACK_Pos (8UL) /*!< SCB INTR_TX: UART_NACK (Bit 8) */ +#define SCB_INTR_TX_UART_NACK_Msk (0x100UL) /*!< SCB INTR_TX: UART_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_UART_DONE_Pos (9UL) /*!< SCB INTR_TX: UART_DONE (Bit 9) */ +#define SCB_INTR_TX_UART_DONE_Msk (0x200UL) /*!< SCB INTR_TX: UART_DONE (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_UART_ARB_LOST_Pos (10UL) /*!< SCB INTR_TX: UART_ARB_LOST (Bit 10) */ +#define SCB_INTR_TX_UART_ARB_LOST_Msk (0x400UL) /*!< SCB INTR_TX: UART_ARB_LOST (Bitfield-Mask: 0x01) */ +/* ==================================================== SCB.INTR_TX_SET ==================================================== */ +#define SCB_INTR_TX_SET_TRIGGER_Pos (0UL) /*!< SCB INTR_TX_SET: TRIGGER (Bit 0) */ +#define SCB_INTR_TX_SET_TRIGGER_Msk (0x1UL) /*!< SCB INTR_TX_SET: TRIGGER (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_SET_NOT_FULL_Pos (1UL) /*!< SCB INTR_TX_SET: NOT_FULL (Bit 1) */ +#define SCB_INTR_TX_SET_NOT_FULL_Msk (0x2UL) /*!< SCB INTR_TX_SET: NOT_FULL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_SET_EMPTY_Pos (4UL) /*!< SCB INTR_TX_SET: EMPTY (Bit 4) */ +#define SCB_INTR_TX_SET_EMPTY_Msk (0x10UL) /*!< SCB INTR_TX_SET: EMPTY (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_SET_OVERFLOW_Pos (5UL) /*!< SCB INTR_TX_SET: OVERFLOW (Bit 5) */ +#define SCB_INTR_TX_SET_OVERFLOW_Msk (0x20UL) /*!< SCB INTR_TX_SET: OVERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_SET_UNDERFLOW_Pos (6UL) /*!< SCB INTR_TX_SET: UNDERFLOW (Bit 6) */ +#define SCB_INTR_TX_SET_UNDERFLOW_Msk (0x40UL) /*!< SCB INTR_TX_SET: UNDERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_SET_BLOCKED_Pos (7UL) /*!< SCB INTR_TX_SET: BLOCKED (Bit 7) */ +#define SCB_INTR_TX_SET_BLOCKED_Msk (0x80UL) /*!< SCB INTR_TX_SET: BLOCKED (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_SET_UART_NACK_Pos (8UL) /*!< SCB INTR_TX_SET: UART_NACK (Bit 8) */ +#define SCB_INTR_TX_SET_UART_NACK_Msk (0x100UL) /*!< SCB INTR_TX_SET: UART_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_SET_UART_DONE_Pos (9UL) /*!< SCB INTR_TX_SET: UART_DONE (Bit 9) */ +#define SCB_INTR_TX_SET_UART_DONE_Msk (0x200UL) /*!< SCB INTR_TX_SET: UART_DONE (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_SET_UART_ARB_LOST_Pos (10UL) /*!< SCB INTR_TX_SET: UART_ARB_LOST (Bit 10) */ +#define SCB_INTR_TX_SET_UART_ARB_LOST_Msk (0x400UL) /*!< SCB INTR_TX_SET: UART_ARB_LOST (Bitfield-Mask: 0x01) */ +/* =================================================== SCB.INTR_TX_MASK ==================================================== */ +#define SCB_INTR_TX_MASK_TRIGGER_Pos (0UL) /*!< SCB INTR_TX_MASK: TRIGGER (Bit 0) */ +#define SCB_INTR_TX_MASK_TRIGGER_Msk (0x1UL) /*!< SCB INTR_TX_MASK: TRIGGER (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASK_NOT_FULL_Pos (1UL) /*!< SCB INTR_TX_MASK: NOT_FULL (Bit 1) */ +#define SCB_INTR_TX_MASK_NOT_FULL_Msk (0x2UL) /*!< SCB INTR_TX_MASK: NOT_FULL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASK_EMPTY_Pos (4UL) /*!< SCB INTR_TX_MASK: EMPTY (Bit 4) */ +#define SCB_INTR_TX_MASK_EMPTY_Msk (0x10UL) /*!< SCB INTR_TX_MASK: EMPTY (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASK_OVERFLOW_Pos (5UL) /*!< SCB INTR_TX_MASK: OVERFLOW (Bit 5) */ +#define SCB_INTR_TX_MASK_OVERFLOW_Msk (0x20UL) /*!< SCB INTR_TX_MASK: OVERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASK_UNDERFLOW_Pos (6UL) /*!< SCB INTR_TX_MASK: UNDERFLOW (Bit 6) */ +#define SCB_INTR_TX_MASK_UNDERFLOW_Msk (0x40UL) /*!< SCB INTR_TX_MASK: UNDERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASK_BLOCKED_Pos (7UL) /*!< SCB INTR_TX_MASK: BLOCKED (Bit 7) */ +#define SCB_INTR_TX_MASK_BLOCKED_Msk (0x80UL) /*!< SCB INTR_TX_MASK: BLOCKED (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASK_UART_NACK_Pos (8UL) /*!< SCB INTR_TX_MASK: UART_NACK (Bit 8) */ +#define SCB_INTR_TX_MASK_UART_NACK_Msk (0x100UL) /*!< SCB INTR_TX_MASK: UART_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASK_UART_DONE_Pos (9UL) /*!< SCB INTR_TX_MASK: UART_DONE (Bit 9) */ +#define SCB_INTR_TX_MASK_UART_DONE_Msk (0x200UL) /*!< SCB INTR_TX_MASK: UART_DONE (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASK_UART_ARB_LOST_Pos (10UL) /*!< SCB INTR_TX_MASK: UART_ARB_LOST (Bit 10) */ +#define SCB_INTR_TX_MASK_UART_ARB_LOST_Msk (0x400UL) /*!< SCB INTR_TX_MASK: UART_ARB_LOST (Bitfield-Mask: 0x01) */ +/* ================================================== SCB.INTR_TX_MASKED =================================================== */ +#define SCB_INTR_TX_MASKED_TRIGGER_Pos (0UL) /*!< SCB INTR_TX_MASKED: TRIGGER (Bit 0) */ +#define SCB_INTR_TX_MASKED_TRIGGER_Msk (0x1UL) /*!< SCB INTR_TX_MASKED: TRIGGER (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASKED_NOT_FULL_Pos (1UL) /*!< SCB INTR_TX_MASKED: NOT_FULL (Bit 1) */ +#define SCB_INTR_TX_MASKED_NOT_FULL_Msk (0x2UL) /*!< SCB INTR_TX_MASKED: NOT_FULL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASKED_EMPTY_Pos (4UL) /*!< SCB INTR_TX_MASKED: EMPTY (Bit 4) */ +#define SCB_INTR_TX_MASKED_EMPTY_Msk (0x10UL) /*!< SCB INTR_TX_MASKED: EMPTY (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASKED_OVERFLOW_Pos (5UL) /*!< SCB INTR_TX_MASKED: OVERFLOW (Bit 5) */ +#define SCB_INTR_TX_MASKED_OVERFLOW_Msk (0x20UL) /*!< SCB INTR_TX_MASKED: OVERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASKED_UNDERFLOW_Pos (6UL) /*!< SCB INTR_TX_MASKED: UNDERFLOW (Bit 6) */ +#define SCB_INTR_TX_MASKED_UNDERFLOW_Msk (0x40UL) /*!< SCB INTR_TX_MASKED: UNDERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASKED_BLOCKED_Pos (7UL) /*!< SCB INTR_TX_MASKED: BLOCKED (Bit 7) */ +#define SCB_INTR_TX_MASKED_BLOCKED_Msk (0x80UL) /*!< SCB INTR_TX_MASKED: BLOCKED (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASKED_UART_NACK_Pos (8UL) /*!< SCB INTR_TX_MASKED: UART_NACK (Bit 8) */ +#define SCB_INTR_TX_MASKED_UART_NACK_Msk (0x100UL) /*!< SCB INTR_TX_MASKED: UART_NACK (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASKED_UART_DONE_Pos (9UL) /*!< SCB INTR_TX_MASKED: UART_DONE (Bit 9) */ +#define SCB_INTR_TX_MASKED_UART_DONE_Msk (0x200UL) /*!< SCB INTR_TX_MASKED: UART_DONE (Bitfield-Mask: 0x01) */ +#define SCB_INTR_TX_MASKED_UART_ARB_LOST_Pos (10UL) /*!< SCB INTR_TX_MASKED: UART_ARB_LOST (Bit 10) */ +#define SCB_INTR_TX_MASKED_UART_ARB_LOST_Msk (0x400UL) /*!< SCB INTR_TX_MASKED: UART_ARB_LOST (Bitfield-Mask: 0x01) */ +/* ====================================================== SCB.INTR_RX ====================================================== */ +#define SCB_INTR_RX_TRIGGER_Pos (0UL) /*!< SCB INTR_RX: TRIGGER (Bit 0) */ +#define SCB_INTR_RX_TRIGGER_Msk (0x1UL) /*!< SCB INTR_RX: TRIGGER (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_NOT_EMPTY_Pos (2UL) /*!< SCB INTR_RX: NOT_EMPTY (Bit 2) */ +#define SCB_INTR_RX_NOT_EMPTY_Msk (0x4UL) /*!< SCB INTR_RX: NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_FULL_Pos (3UL) /*!< SCB INTR_RX: FULL (Bit 3) */ +#define SCB_INTR_RX_FULL_Msk (0x8UL) /*!< SCB INTR_RX: FULL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_OVERFLOW_Pos (5UL) /*!< SCB INTR_RX: OVERFLOW (Bit 5) */ +#define SCB_INTR_RX_OVERFLOW_Msk (0x20UL) /*!< SCB INTR_RX: OVERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_UNDERFLOW_Pos (6UL) /*!< SCB INTR_RX: UNDERFLOW (Bit 6) */ +#define SCB_INTR_RX_UNDERFLOW_Msk (0x40UL) /*!< SCB INTR_RX: UNDERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_BLOCKED_Pos (7UL) /*!< SCB INTR_RX: BLOCKED (Bit 7) */ +#define SCB_INTR_RX_BLOCKED_Msk (0x80UL) /*!< SCB INTR_RX: BLOCKED (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_FRAME_ERROR_Pos (8UL) /*!< SCB INTR_RX: FRAME_ERROR (Bit 8) */ +#define SCB_INTR_RX_FRAME_ERROR_Msk (0x100UL) /*!< SCB INTR_RX: FRAME_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_PARITY_ERROR_Pos (9UL) /*!< SCB INTR_RX: PARITY_ERROR (Bit 9) */ +#define SCB_INTR_RX_PARITY_ERROR_Msk (0x200UL) /*!< SCB INTR_RX: PARITY_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_BAUD_DETECT_Pos (10UL) /*!< SCB INTR_RX: BAUD_DETECT (Bit 10) */ +#define SCB_INTR_RX_BAUD_DETECT_Msk (0x400UL) /*!< SCB INTR_RX: BAUD_DETECT (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_BREAK_DETECT_Pos (11UL) /*!< SCB INTR_RX: BREAK_DETECT (Bit 11) */ +#define SCB_INTR_RX_BREAK_DETECT_Msk (0x800UL) /*!< SCB INTR_RX: BREAK_DETECT (Bitfield-Mask: 0x01) */ +/* ==================================================== SCB.INTR_RX_SET ==================================================== */ +#define SCB_INTR_RX_SET_TRIGGER_Pos (0UL) /*!< SCB INTR_RX_SET: TRIGGER (Bit 0) */ +#define SCB_INTR_RX_SET_TRIGGER_Msk (0x1UL) /*!< SCB INTR_RX_SET: TRIGGER (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_SET_NOT_EMPTY_Pos (2UL) /*!< SCB INTR_RX_SET: NOT_EMPTY (Bit 2) */ +#define SCB_INTR_RX_SET_NOT_EMPTY_Msk (0x4UL) /*!< SCB INTR_RX_SET: NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_SET_FULL_Pos (3UL) /*!< SCB INTR_RX_SET: FULL (Bit 3) */ +#define SCB_INTR_RX_SET_FULL_Msk (0x8UL) /*!< SCB INTR_RX_SET: FULL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_SET_OVERFLOW_Pos (5UL) /*!< SCB INTR_RX_SET: OVERFLOW (Bit 5) */ +#define SCB_INTR_RX_SET_OVERFLOW_Msk (0x20UL) /*!< SCB INTR_RX_SET: OVERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_SET_UNDERFLOW_Pos (6UL) /*!< SCB INTR_RX_SET: UNDERFLOW (Bit 6) */ +#define SCB_INTR_RX_SET_UNDERFLOW_Msk (0x40UL) /*!< SCB INTR_RX_SET: UNDERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_SET_BLOCKED_Pos (7UL) /*!< SCB INTR_RX_SET: BLOCKED (Bit 7) */ +#define SCB_INTR_RX_SET_BLOCKED_Msk (0x80UL) /*!< SCB INTR_RX_SET: BLOCKED (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_SET_FRAME_ERROR_Pos (8UL) /*!< SCB INTR_RX_SET: FRAME_ERROR (Bit 8) */ +#define SCB_INTR_RX_SET_FRAME_ERROR_Msk (0x100UL) /*!< SCB INTR_RX_SET: FRAME_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_SET_PARITY_ERROR_Pos (9UL) /*!< SCB INTR_RX_SET: PARITY_ERROR (Bit 9) */ +#define SCB_INTR_RX_SET_PARITY_ERROR_Msk (0x200UL) /*!< SCB INTR_RX_SET: PARITY_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_SET_BAUD_DETECT_Pos (10UL) /*!< SCB INTR_RX_SET: BAUD_DETECT (Bit 10) */ +#define SCB_INTR_RX_SET_BAUD_DETECT_Msk (0x400UL) /*!< SCB INTR_RX_SET: BAUD_DETECT (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_SET_BREAK_DETECT_Pos (11UL) /*!< SCB INTR_RX_SET: BREAK_DETECT (Bit 11) */ +#define SCB_INTR_RX_SET_BREAK_DETECT_Msk (0x800UL) /*!< SCB INTR_RX_SET: BREAK_DETECT (Bitfield-Mask: 0x01) */ +/* =================================================== SCB.INTR_RX_MASK ==================================================== */ +#define SCB_INTR_RX_MASK_TRIGGER_Pos (0UL) /*!< SCB INTR_RX_MASK: TRIGGER (Bit 0) */ +#define SCB_INTR_RX_MASK_TRIGGER_Msk (0x1UL) /*!< SCB INTR_RX_MASK: TRIGGER (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASK_NOT_EMPTY_Pos (2UL) /*!< SCB INTR_RX_MASK: NOT_EMPTY (Bit 2) */ +#define SCB_INTR_RX_MASK_NOT_EMPTY_Msk (0x4UL) /*!< SCB INTR_RX_MASK: NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASK_FULL_Pos (3UL) /*!< SCB INTR_RX_MASK: FULL (Bit 3) */ +#define SCB_INTR_RX_MASK_FULL_Msk (0x8UL) /*!< SCB INTR_RX_MASK: FULL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASK_OVERFLOW_Pos (5UL) /*!< SCB INTR_RX_MASK: OVERFLOW (Bit 5) */ +#define SCB_INTR_RX_MASK_OVERFLOW_Msk (0x20UL) /*!< SCB INTR_RX_MASK: OVERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASK_UNDERFLOW_Pos (6UL) /*!< SCB INTR_RX_MASK: UNDERFLOW (Bit 6) */ +#define SCB_INTR_RX_MASK_UNDERFLOW_Msk (0x40UL) /*!< SCB INTR_RX_MASK: UNDERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASK_BLOCKED_Pos (7UL) /*!< SCB INTR_RX_MASK: BLOCKED (Bit 7) */ +#define SCB_INTR_RX_MASK_BLOCKED_Msk (0x80UL) /*!< SCB INTR_RX_MASK: BLOCKED (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASK_FRAME_ERROR_Pos (8UL) /*!< SCB INTR_RX_MASK: FRAME_ERROR (Bit 8) */ +#define SCB_INTR_RX_MASK_FRAME_ERROR_Msk (0x100UL) /*!< SCB INTR_RX_MASK: FRAME_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASK_PARITY_ERROR_Pos (9UL) /*!< SCB INTR_RX_MASK: PARITY_ERROR (Bit 9) */ +#define SCB_INTR_RX_MASK_PARITY_ERROR_Msk (0x200UL) /*!< SCB INTR_RX_MASK: PARITY_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASK_BAUD_DETECT_Pos (10UL) /*!< SCB INTR_RX_MASK: BAUD_DETECT (Bit 10) */ +#define SCB_INTR_RX_MASK_BAUD_DETECT_Msk (0x400UL) /*!< SCB INTR_RX_MASK: BAUD_DETECT (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASK_BREAK_DETECT_Pos (11UL) /*!< SCB INTR_RX_MASK: BREAK_DETECT (Bit 11) */ +#define SCB_INTR_RX_MASK_BREAK_DETECT_Msk (0x800UL) /*!< SCB INTR_RX_MASK: BREAK_DETECT (Bitfield-Mask: 0x01) */ +/* ================================================== SCB.INTR_RX_MASKED =================================================== */ +#define SCB_INTR_RX_MASKED_TRIGGER_Pos (0UL) /*!< SCB INTR_RX_MASKED: TRIGGER (Bit 0) */ +#define SCB_INTR_RX_MASKED_TRIGGER_Msk (0x1UL) /*!< SCB INTR_RX_MASKED: TRIGGER (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASKED_NOT_EMPTY_Pos (2UL) /*!< SCB INTR_RX_MASKED: NOT_EMPTY (Bit 2) */ +#define SCB_INTR_RX_MASKED_NOT_EMPTY_Msk (0x4UL) /*!< SCB INTR_RX_MASKED: NOT_EMPTY (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASKED_FULL_Pos (3UL) /*!< SCB INTR_RX_MASKED: FULL (Bit 3) */ +#define SCB_INTR_RX_MASKED_FULL_Msk (0x8UL) /*!< SCB INTR_RX_MASKED: FULL (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASKED_OVERFLOW_Pos (5UL) /*!< SCB INTR_RX_MASKED: OVERFLOW (Bit 5) */ +#define SCB_INTR_RX_MASKED_OVERFLOW_Msk (0x20UL) /*!< SCB INTR_RX_MASKED: OVERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASKED_UNDERFLOW_Pos (6UL) /*!< SCB INTR_RX_MASKED: UNDERFLOW (Bit 6) */ +#define SCB_INTR_RX_MASKED_UNDERFLOW_Msk (0x40UL) /*!< SCB INTR_RX_MASKED: UNDERFLOW (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASKED_BLOCKED_Pos (7UL) /*!< SCB INTR_RX_MASKED: BLOCKED (Bit 7) */ +#define SCB_INTR_RX_MASKED_BLOCKED_Msk (0x80UL) /*!< SCB INTR_RX_MASKED: BLOCKED (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASKED_FRAME_ERROR_Pos (8UL) /*!< SCB INTR_RX_MASKED: FRAME_ERROR (Bit 8) */ +#define SCB_INTR_RX_MASKED_FRAME_ERROR_Msk (0x100UL) /*!< SCB INTR_RX_MASKED: FRAME_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASKED_PARITY_ERROR_Pos (9UL) /*!< SCB INTR_RX_MASKED: PARITY_ERROR (Bit 9) */ +#define SCB_INTR_RX_MASKED_PARITY_ERROR_Msk (0x200UL) /*!< SCB INTR_RX_MASKED: PARITY_ERROR (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASKED_BAUD_DETECT_Pos (10UL) /*!< SCB INTR_RX_MASKED: BAUD_DETECT (Bit 10) */ +#define SCB_INTR_RX_MASKED_BAUD_DETECT_Msk (0x400UL) /*!< SCB INTR_RX_MASKED: BAUD_DETECT (Bitfield-Mask: 0x01) */ +#define SCB_INTR_RX_MASKED_BREAK_DETECT_Pos (11UL) /*!< SCB INTR_RX_MASKED: BREAK_DETECT (Bit 11) */ +#define SCB_INTR_RX_MASKED_BREAK_DETECT_Msk (0x800UL) /*!< SCB INTR_RX_MASKED: BREAK_DETECT (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_SCB_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_sflash.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_sflash.h new file mode 100644 index 0000000000..4c1f70ca60 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_sflash.h @@ -0,0 +1,186 @@ +/***************************************************************************//** +* \file cyip_sflash.h +* +* \brief +* SFLASH IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_SFLASH_H_ +#define _CYIP_SFLASH_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ SFLASH ================ */ +/* =========================================================================================================================== */ + +#define SFLASH_SECTION_SIZE 0x00008000UL + +/** + * \brief FLASH Supervisory Region (SFLASH) + */ +typedef struct { /*!< SFLASH Structure */ + __IM uint16_t RESERVED; + __IOM uint16_t SILICON_ID; /*!< 0x00000002 Indicates siliconID of the device */ + __IM uint32_t RESERVED1[383]; + __IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */ + __IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */ + __IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */ + __IOM uint8_t DIE_Y; /*!< 0x00000605 Y Position on Wafer, CHI Pass/Fail Bin */ + __IOM uint8_t DIE_SORT; /*!< 0x00000606 Sort1/2/3 Pass/Fail Bin */ + __IOM uint8_t DIE_MINOR; /*!< 0x00000607 Minor Revision Number */ + __IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */ + __IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */ + __IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */ + __IM uint8_t RESERVED2[501]; + __IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */ + __IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */ + __IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */ + __IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */ + __IM uint32_t RESERVED3[302]; + __IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */ + __IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */ + __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */ + __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ATTR[16]; /*!< 0x00001518 Standard SMPU STRUCT Slave Attribute value */ + __IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */ + __IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */ + __IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */ + __IOM uint32_t CSP_PANEL_ID; /*!< 0x00001618 CSP Panel Id to record panel ID of CSP die */ + __IM uint32_t RESERVED4[121]; + __IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */ + __IM uint16_t RESERVED5[1023]; + __IOM uint32_t FLASH_BOOT_IDENTIFIER; /*!< 0x00002000 Flash Boot Firmware Identifier */ + __IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002004 N/A */ + __IOM uint32_t FLASH_BOOT_CMAC_ADDRESS; /*!< 0x00002008 Flash boot CMAC address */ + __IOM uint32_t FLASH_BOOT_ADDRESS; /*!< 0x0000200C Flash Boot Code Address */ + __IOM uint32_t FLASH_BOOT_NEXT_ADDRESS; /*!< 0x00002010 Flash Boot Next Code Address to be executed */ + __IOM uint32_t FLASH_BOOT_ID_TYPE; /*!< 0x00002014 Contains processor details */ + __IOM uint32_t FLASH_BOOT_VECTOR_TABLE[48]; /*!< 0x00002018 Flash Boot Vector Table */ + __IOM uint8_t FLASH_BOOT_CODE[8192]; /*!< 0x000020D8 Flash Boot Code 8KB */ + __IOM uint8_t FLASH_BOOT_CMAC[16]; /*!< 0x000040D8 Secure Hash/CMAC */ +} SFLASH_Type; /*!< Size = 16616 (0x40E8) */ + + +/* =================================================== SFLASH.SILICON_ID =================================================== */ +#define SFLASH_SILICON_ID_ID_Pos (0UL) /*!< SFLASH SILICON_ID: ID (Bit 0) */ +#define SFLASH_SILICON_ID_ID_Msk (0xffffUL) /*!< SFLASH SILICON_ID: ID (Bitfield-Mask: 0xffff) */ +/* ==================================================== SFLASH.DIE_LOT ===================================================== */ +#define SFLASH_DIE_LOT_LOT_Pos (0UL) /*!< SFLASH DIE_LOT: LOT (Bit 0) */ +#define SFLASH_DIE_LOT_LOT_Msk (0xffUL) /*!< SFLASH DIE_LOT: LOT (Bitfield-Mask: 0xff) */ +/* =================================================== SFLASH.DIE_WAFER ==================================================== */ +#define SFLASH_DIE_WAFER_WAFER_Pos (0UL) /*!< SFLASH DIE_WAFER: WAFER (Bit 0) */ +#define SFLASH_DIE_WAFER_WAFER_Msk (0xffUL) /*!< SFLASH DIE_WAFER: WAFER (Bitfield-Mask: 0xff) */ +/* ===================================================== SFLASH.DIE_X ====================================================== */ +#define SFLASH_DIE_X_X_Pos (0UL) /*!< SFLASH DIE_X: X (Bit 0) */ +#define SFLASH_DIE_X_X_Msk (0xffUL) /*!< SFLASH DIE_X: X (Bitfield-Mask: 0xff) */ +/* ===================================================== SFLASH.DIE_Y ====================================================== */ +#define SFLASH_DIE_Y_Y_Pos (0UL) /*!< SFLASH DIE_Y: Y (Bit 0) */ +#define SFLASH_DIE_Y_Y_Msk (0xffUL) /*!< SFLASH DIE_Y: Y (Bitfield-Mask: 0xff) */ +/* ==================================================== SFLASH.DIE_SORT ==================================================== */ +#define SFLASH_DIE_SORT_S1_PASS_Pos (0UL) /*!< SFLASH DIE_SORT: S1_PASS (Bit 0) */ +#define SFLASH_DIE_SORT_S1_PASS_Msk (0x1UL) /*!< SFLASH DIE_SORT: S1_PASS (Bitfield-Mask: 0x01) */ +#define SFLASH_DIE_SORT_S2_PASS_Pos (1UL) /*!< SFLASH DIE_SORT: S2_PASS (Bit 1) */ +#define SFLASH_DIE_SORT_S2_PASS_Msk (0x2UL) /*!< SFLASH DIE_SORT: S2_PASS (Bitfield-Mask: 0x01) */ +#define SFLASH_DIE_SORT_S3_PASS_Pos (2UL) /*!< SFLASH DIE_SORT: S3_PASS (Bit 2) */ +#define SFLASH_DIE_SORT_S3_PASS_Msk (0x4UL) /*!< SFLASH DIE_SORT: S3_PASS (Bitfield-Mask: 0x01) */ +#define SFLASH_DIE_SORT_CRI_PASS_Pos (3UL) /*!< SFLASH DIE_SORT: CRI_PASS (Bit 3) */ +#define SFLASH_DIE_SORT_CRI_PASS_Msk (0x8UL) /*!< SFLASH DIE_SORT: CRI_PASS (Bitfield-Mask: 0x01) */ +#define SFLASH_DIE_SORT_CHI_PASS_Pos (4UL) /*!< SFLASH DIE_SORT: CHI_PASS (Bit 4) */ +#define SFLASH_DIE_SORT_CHI_PASS_Msk (0x10UL) /*!< SFLASH DIE_SORT: CHI_PASS (Bitfield-Mask: 0x01) */ +#define SFLASH_DIE_SORT_ENG_PASS_Pos (5UL) /*!< SFLASH DIE_SORT: ENG_PASS (Bit 5) */ +#define SFLASH_DIE_SORT_ENG_PASS_Msk (0x20UL) /*!< SFLASH DIE_SORT: ENG_PASS (Bitfield-Mask: 0x01) */ +/* =================================================== SFLASH.DIE_MINOR ==================================================== */ +#define SFLASH_DIE_MINOR_MINOR_Pos (0UL) /*!< SFLASH DIE_MINOR: MINOR (Bit 0) */ +#define SFLASH_DIE_MINOR_MINOR_Msk (0xffUL) /*!< SFLASH DIE_MINOR: MINOR (Bitfield-Mask: 0xff) */ +/* ==================================================== SFLASH.DIE_DAY ===================================================== */ +#define SFLASH_DIE_DAY_MINOR_Pos (0UL) /*!< SFLASH DIE_DAY: MINOR (Bit 0) */ +#define SFLASH_DIE_DAY_MINOR_Msk (0xffUL) /*!< SFLASH DIE_DAY: MINOR (Bitfield-Mask: 0xff) */ +/* =================================================== SFLASH.DIE_MONTH ==================================================== */ +#define SFLASH_DIE_MONTH_MINOR_Pos (0UL) /*!< SFLASH DIE_MONTH: MINOR (Bit 0) */ +#define SFLASH_DIE_MONTH_MINOR_Msk (0xffUL) /*!< SFLASH DIE_MONTH: MINOR (Bitfield-Mask: 0xff) */ +/* ==================================================== SFLASH.DIE_YEAR ==================================================== */ +#define SFLASH_DIE_YEAR_MINOR_Pos (0UL) /*!< SFLASH DIE_YEAR: MINOR (Bit 0) */ +#define SFLASH_DIE_YEAR_MINOR_Msk (0xffUL) /*!< SFLASH DIE_YEAR: MINOR (Bitfield-Mask: 0xff) */ +/* =============================================== SFLASH.BLE_DEVICE_ADDRESS =============================================== */ +#define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Pos (0UL) /*!< SFLASH BLE_DEVICE_ADDRESS: ADDR (Bit 0) */ +#define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Msk (0xffffffffUL) /*!< SFLASH BLE_DEVICE_ADDRESS: ADDR (Bitfield-Mask: 0xffffffff)*/ +/* ================================================= SFLASH.USER_FREE_ROW1 ================================================= */ +#define SFLASH_USER_FREE_ROW1_DATA32_Pos (0UL) /*!< SFLASH USER_FREE_ROW1: DATA32 (Bit 0) */ +#define SFLASH_USER_FREE_ROW1_DATA32_Msk (0xffffffffUL) /*!< SFLASH USER_FREE_ROW1: DATA32 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SFLASH.USER_FREE_ROW2 ================================================= */ +#define SFLASH_USER_FREE_ROW2_DATA32_Pos (0UL) /*!< SFLASH USER_FREE_ROW2: DATA32 (Bit 0) */ +#define SFLASH_USER_FREE_ROW2_DATA32_Msk (0xffffffffUL) /*!< SFLASH USER_FREE_ROW2: DATA32 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SFLASH.USER_FREE_ROW3 ================================================= */ +#define SFLASH_USER_FREE_ROW3_DATA32_Pos (0UL) /*!< SFLASH USER_FREE_ROW3: DATA32 (Bit 0) */ +#define SFLASH_USER_FREE_ROW3_DATA32_Msk (0xffffffffUL) /*!< SFLASH USER_FREE_ROW3: DATA32 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== SFLASH.DEVICE_UID =================================================== */ +#define SFLASH_DEVICE_UID_DATA_Pos (0UL) /*!< SFLASH DEVICE_UID: DATA (Bit 0) */ +#define SFLASH_DEVICE_UID_DATA_Msk (0xffUL) /*!< SFLASH DEVICE_UID: DATA (Bitfield-Mask: 0xff) */ +/* =================================================== SFLASH.MASTER_KEY =================================================== */ +#define SFLASH_MASTER_KEY_DATA_Pos (0UL) /*!< SFLASH MASTER_KEY: DATA (Bit 0) */ +#define SFLASH_MASTER_KEY_DATA_Msk (0xffUL) /*!< SFLASH MASTER_KEY: DATA (Bitfield-Mask: 0xff) */ +/* ======================================== SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ADDR ========================================= */ +#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Pos (0UL) /*!< SFLASH STANDARD_SMPU_STRUCT_SLAVE_ADDR: DATA32 (Bit 0) */ +#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Msk (0xffffffffUL) /*!< SFLASH STANDARD_SMPU_STRUCT_SLAVE_ADDR: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ======================================== SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ATTR ========================================= */ +#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Pos (0UL) /*!< SFLASH STANDARD_SMPU_STRUCT_SLAVE_ATTR: DATA32 (Bit 0) */ +#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Msk (0xffffffffUL) /*!< SFLASH STANDARD_SMPU_STRUCT_SLAVE_ATTR: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ======================================== SFLASH.STANDARD_SMPU_STRUCT_MASTER_ATTR ======================================== */ +#define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Pos (0UL) /*!< SFLASH STANDARD_SMPU_STRUCT_MASTER_ATTR: DATA32 (Bit 0) */ +#define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Msk (0xffffffffUL) /*!< SFLASH STANDARD_SMPU_STRUCT_MASTER_ATTR: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== SFLASH.STANDARD_MPU_STRUCT =============================================== */ +#define SFLASH_STANDARD_MPU_STRUCT_DATA32_Pos (0UL) /*!< SFLASH STANDARD_MPU_STRUCT: DATA32 (Bit 0) */ +#define SFLASH_STANDARD_MPU_STRUCT_DATA32_Msk (0xffffffffUL) /*!< SFLASH STANDARD_MPU_STRUCT: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== SFLASH.STANDARD_PPU_STRUCT =============================================== */ +#define SFLASH_STANDARD_PPU_STRUCT_DATA32_Pos (0UL) /*!< SFLASH STANDARD_PPU_STRUCT: DATA32 (Bit 0) */ +#define SFLASH_STANDARD_PPU_STRUCT_DATA32_Msk (0xffffffffUL) /*!< SFLASH STANDARD_PPU_STRUCT: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ================================================== SFLASH.CSP_PANEL_ID ================================================== */ +#define SFLASH_CSP_PANEL_ID_DATA32_Pos (0UL) /*!< SFLASH CSP_PANEL_ID: DATA32 (Bit 0) */ +#define SFLASH_CSP_PANEL_ID_DATA32_Msk (0xffffffffUL) /*!< SFLASH CSP_PANEL_ID: DATA32 (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SFLASH.PILO_FREQ_STEP ================================================= */ +#define SFLASH_PILO_FREQ_STEP_STEP_Pos (0UL) /*!< SFLASH PILO_FREQ_STEP: STEP (Bit 0) */ +#define SFLASH_PILO_FREQ_STEP_STEP_Msk (0xffffUL) /*!< SFLASH PILO_FREQ_STEP: STEP (Bitfield-Mask: 0xffff) */ +/* ============================================= SFLASH.FLASH_BOOT_IDENTIFIER ============================================== */ +#define SFLASH_FLASH_BOOT_IDENTIFIER_DATA32_Pos (0UL) /*!< SFLASH FLASH_BOOT_IDENTIFIER: DATA32 (Bit 0) */ +#define SFLASH_FLASH_BOOT_IDENTIFIER_DATA32_Msk (0xffffffffUL) /*!< SFLASH FLASH_BOOT_IDENTIFIER: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== SFLASH.FLASH_BOOT_ATTRIBUTE ============================================== */ +#define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Pos (0UL) /*!< SFLASH FLASH_BOOT_ATTRIBUTE: DATA32 (Bit 0) */ +#define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Msk (0xffffffffUL) /*!< SFLASH FLASH_BOOT_ATTRIBUTE: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ============================================ SFLASH.FLASH_BOOT_CMAC_ADDRESS ============================================= */ +#define SFLASH_FLASH_BOOT_CMAC_ADDRESS_DATA32_Pos (0UL) /*!< SFLASH FLASH_BOOT_CMAC_ADDRESS: DATA32 (Bit 0) */ +#define SFLASH_FLASH_BOOT_CMAC_ADDRESS_DATA32_Msk (0xffffffffUL) /*!< SFLASH FLASH_BOOT_CMAC_ADDRESS: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* =============================================== SFLASH.FLASH_BOOT_ADDRESS =============================================== */ +#define SFLASH_FLASH_BOOT_ADDRESS_DATA32_Pos (0UL) /*!< SFLASH FLASH_BOOT_ADDRESS: DATA32 (Bit 0) */ +#define SFLASH_FLASH_BOOT_ADDRESS_DATA32_Msk (0xffffffffUL) /*!< SFLASH FLASH_BOOT_ADDRESS: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ============================================ SFLASH.FLASH_BOOT_NEXT_ADDRESS ============================================= */ +#define SFLASH_FLASH_BOOT_NEXT_ADDRESS_DATA32_Pos (0UL) /*!< SFLASH FLASH_BOOT_NEXT_ADDRESS: DATA32 (Bit 0) */ +#define SFLASH_FLASH_BOOT_NEXT_ADDRESS_DATA32_Msk (0xffffffffUL) /*!< SFLASH FLASH_BOOT_NEXT_ADDRESS: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* =============================================== SFLASH.FLASH_BOOT_ID_TYPE =============================================== */ +#define SFLASH_FLASH_BOOT_ID_TYPE_DATA32_Pos (0UL) /*!< SFLASH FLASH_BOOT_ID_TYPE: DATA32 (Bit 0) */ +#define SFLASH_FLASH_BOOT_ID_TYPE_DATA32_Msk (0xffffffffUL) /*!< SFLASH FLASH_BOOT_ID_TYPE: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ============================================ SFLASH.FLASH_BOOT_VECTOR_TABLE ============================================= */ +#define SFLASH_FLASH_BOOT_VECTOR_TABLE_DATA32_Pos (0UL) /*!< SFLASH FLASH_BOOT_VECTOR_TABLE: DATA32 (Bit 0) */ +#define SFLASH_FLASH_BOOT_VECTOR_TABLE_DATA32_Msk (0xffffffffUL) /*!< SFLASH FLASH_BOOT_VECTOR_TABLE: DATA32 (Bitfield-Mask: 0xffffffff)*/ +/* ================================================ SFLASH.FLASH_BOOT_CODE ================================================= */ +#define SFLASH_FLASH_BOOT_CODE_DATA_Pos (0UL) /*!< SFLASH FLASH_BOOT_CODE: DATA (Bit 0) */ +#define SFLASH_FLASH_BOOT_CODE_DATA_Msk (0xffUL) /*!< SFLASH FLASH_BOOT_CODE: DATA (Bitfield-Mask: 0xff) */ +/* ================================================ SFLASH.FLASH_BOOT_CMAC ================================================= */ +#define SFLASH_FLASH_BOOT_CMAC_DATA_Pos (0UL) /*!< SFLASH FLASH_BOOT_CMAC: DATA (Bit 0) */ +#define SFLASH_FLASH_BOOT_CMAC_DATA_Msk (0xffUL) /*!< SFLASH FLASH_BOOT_CMAC: DATA (Bitfield-Mask: 0xff) */ + + +#endif /* _CYIP_SFLASH_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_smartio.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_smartio.h new file mode 100644 index 0000000000..09d188f2fd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_smartio.h @@ -0,0 +1,109 @@ +/***************************************************************************//** +* \file cyip_smartio.h +* +* \brief +* SMARTIO IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_SMARTIO_H_ +#define _CYIP_SMARTIO_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ SMARTIO ================ */ +/* =========================================================================================================================== */ + +#define SMARTIO_PRT_SECTION_SIZE 0x00000100UL +#define SMARTIO_SECTION_SIZE 0x00010000UL + +/** + * \brief Programmable IO port registers (SMARTIO_PRT) + */ +typedef struct { + __IOM uint32_t CTL; /*!< 0x00000000 Control register */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t SYNC_CTL; /*!< 0x00000010 Synchronization control register */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t LUT_SEL[8]; /*!< 0x00000020 LUT component input selection */ + __IOM uint32_t LUT_CTL[8]; /*!< 0x00000040 LUT component control register */ + __IM uint32_t RESERVED2[24]; + __IOM uint32_t DU_SEL; /*!< 0x000000C0 Data unit component input selection */ + __IOM uint32_t DU_CTL; /*!< 0x000000C4 Data unit component control register */ + __IM uint32_t RESERVED3[10]; + __IOM uint32_t DATA; /*!< 0x000000F0 Data register */ + __IM uint32_t RESERVED4[3]; +} SMARTIO_PRT_Type; /*!< Size = 244 (0xF4) */ + +/** + * \brief Programmable IO configuration (SMARTIO) + */ +typedef struct { /*!< SMARTIO Structure */ + SMARTIO_PRT_Type PRT[128]; /*!< 0x00000000 Programmable IO port registers */ +} SMARTIO_Type; /*!< Size = 32768 (0x8000) */ + + +/* ==================================================== SMARTIO_PRT.CTL ==================================================== */ +#define SMARTIO_PRT_CTL_BYPASS_Pos (0UL) /*!< SMARTIO_PRT CTL: BYPASS (Bit 0) */ +#define SMARTIO_PRT_CTL_BYPASS_Msk (0xffUL) /*!< SMARTIO_PRT CTL: BYPASS (Bitfield-Mask: 0xff) */ +#define SMARTIO_PRT_CTL_CLOCK_SRC_Pos (8UL) /*!< SMARTIO_PRT CTL: CLOCK_SRC (Bit 8) */ +#define SMARTIO_PRT_CTL_CLOCK_SRC_Msk (0x1f00UL) /*!< SMARTIO_PRT CTL: CLOCK_SRC (Bitfield-Mask: 0x1f) */ +#define SMARTIO_PRT_CTL_HLD_OVR_Pos (24UL) /*!< SMARTIO_PRT CTL: HLD_OVR (Bit 24) */ +#define SMARTIO_PRT_CTL_HLD_OVR_Msk (0x1000000UL) /*!< SMARTIO_PRT CTL: HLD_OVR (Bitfield-Mask: 0x01) */ +#define SMARTIO_PRT_CTL_PIPELINE_EN_Pos (25UL) /*!< SMARTIO_PRT CTL: PIPELINE_EN (Bit 25) */ +#define SMARTIO_PRT_CTL_PIPELINE_EN_Msk (0x2000000UL) /*!< SMARTIO_PRT CTL: PIPELINE_EN (Bitfield-Mask: 0x01) */ +#define SMARTIO_PRT_CTL_ENABLED_Pos (31UL) /*!< SMARTIO_PRT CTL: ENABLED (Bit 31) */ +#define SMARTIO_PRT_CTL_ENABLED_Msk (0x80000000UL) /*!< SMARTIO_PRT CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ================================================= SMARTIO_PRT.SYNC_CTL ================================================== */ +#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Pos (0UL) /*!< SMARTIO_PRT SYNC_CTL: IO_SYNC_EN (Bit 0) */ +#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Msk (0xffUL) /*!< SMARTIO_PRT SYNC_CTL: IO_SYNC_EN (Bitfield-Mask: 0xff) */ +#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Pos (8UL) /*!< SMARTIO_PRT SYNC_CTL: CHIP_SYNC_EN (Bit 8) */ +#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Msk (0xff00UL) /*!< SMARTIO_PRT SYNC_CTL: CHIP_SYNC_EN (Bitfield-Mask: 0xff) */ +/* ================================================== SMARTIO_PRT.LUT_SEL ================================================== */ +#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Pos (0UL) /*!< SMARTIO_PRT LUT_SEL: LUT_TR0_SEL (Bit 0) */ +#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk (0xfUL) /*!< SMARTIO_PRT LUT_SEL: LUT_TR0_SEL (Bitfield-Mask: 0x0f) */ +#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Pos (8UL) /*!< SMARTIO_PRT LUT_SEL: LUT_TR1_SEL (Bit 8) */ +#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk (0xf00UL) /*!< SMARTIO_PRT LUT_SEL: LUT_TR1_SEL (Bitfield-Mask: 0x0f) */ +#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Pos (16UL) /*!< SMARTIO_PRT LUT_SEL: LUT_TR2_SEL (Bit 16) */ +#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Msk (0xf0000UL) /*!< SMARTIO_PRT LUT_SEL: LUT_TR2_SEL (Bitfield-Mask: 0x0f) */ +/* ================================================== SMARTIO_PRT.LUT_CTL ================================================== */ +#define SMARTIO_PRT_LUT_CTL_LUT_Pos (0UL) /*!< SMARTIO_PRT LUT_CTL: LUT (Bit 0) */ +#define SMARTIO_PRT_LUT_CTL_LUT_Msk (0xffUL) /*!< SMARTIO_PRT LUT_CTL: LUT (Bitfield-Mask: 0xff) */ +#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Pos (8UL) /*!< SMARTIO_PRT LUT_CTL: LUT_OPC (Bit 8) */ +#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Msk (0x300UL) /*!< SMARTIO_PRT LUT_CTL: LUT_OPC (Bitfield-Mask: 0x03) */ +/* ================================================== SMARTIO_PRT.DU_SEL =================================================== */ +#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Pos (0UL) /*!< SMARTIO_PRT DU_SEL: DU_TR0_SEL (Bit 0) */ +#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk (0xfUL) /*!< SMARTIO_PRT DU_SEL: DU_TR0_SEL (Bitfield-Mask: 0x0f) */ +#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Pos (8UL) /*!< SMARTIO_PRT DU_SEL: DU_TR1_SEL (Bit 8) */ +#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk (0xf00UL) /*!< SMARTIO_PRT DU_SEL: DU_TR1_SEL (Bitfield-Mask: 0x0f) */ +#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Pos (16UL) /*!< SMARTIO_PRT DU_SEL: DU_TR2_SEL (Bit 16) */ +#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Msk (0xf0000UL) /*!< SMARTIO_PRT DU_SEL: DU_TR2_SEL (Bitfield-Mask: 0x0f) */ +#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Pos (24UL) /*!< SMARTIO_PRT DU_SEL: DU_DATA0_SEL (Bit 24) */ +#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Msk (0x3000000UL) /*!< SMARTIO_PRT DU_SEL: DU_DATA0_SEL (Bitfield-Mask: 0x03) */ +#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Pos (28UL) /*!< SMARTIO_PRT DU_SEL: DU_DATA1_SEL (Bit 28) */ +#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Msk (0x30000000UL) /*!< SMARTIO_PRT DU_SEL: DU_DATA1_SEL (Bitfield-Mask: 0x03) */ +/* ================================================== SMARTIO_PRT.DU_CTL =================================================== */ +#define SMARTIO_PRT_DU_CTL_DU_SIZE_Pos (0UL) /*!< SMARTIO_PRT DU_CTL: DU_SIZE (Bit 0) */ +#define SMARTIO_PRT_DU_CTL_DU_SIZE_Msk (0x7UL) /*!< SMARTIO_PRT DU_CTL: DU_SIZE (Bitfield-Mask: 0x07) */ +#define SMARTIO_PRT_DU_CTL_DU_OPC_Pos (8UL) /*!< SMARTIO_PRT DU_CTL: DU_OPC (Bit 8) */ +#define SMARTIO_PRT_DU_CTL_DU_OPC_Msk (0xf00UL) /*!< SMARTIO_PRT DU_CTL: DU_OPC (Bitfield-Mask: 0x0f) */ +/* =================================================== SMARTIO_PRT.DATA ==================================================== */ +#define SMARTIO_PRT_DATA_DATA_Pos (0UL) /*!< SMARTIO_PRT DATA: DATA (Bit 0) */ +#define SMARTIO_PRT_DATA_DATA_Msk (0xffUL) /*!< SMARTIO_PRT DATA: DATA (Bitfield-Mask: 0xff) */ + + +#endif /* _CYIP_SMARTIO_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_smif.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_smif.h new file mode 100644 index 0000000000..0012e9a490 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_smif.h @@ -0,0 +1,404 @@ +/***************************************************************************//** +* \file cyip_smif.h +* +* \brief +* SMIF IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_SMIF_H_ +#define _CYIP_SMIF_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ SMIF ================ */ +/* =========================================================================================================================== */ + +#define SMIF_DEVICE_SECTION_SIZE 0x00000080UL +#define SMIF_SECTION_SIZE 0x00010000UL + +/** + * \brief Device (only used in XIP mode) (SMIF_DEVICE) + */ +typedef struct { + __IOM uint32_t CTL; /*!< 0x00000000 Control */ + __IM uint32_t RESERVED; + __IOM uint32_t ADDR; /*!< 0x00000008 Device region base address */ + __IOM uint32_t MASK; /*!< 0x0000000C Device region mask */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t ADDR_CTL; /*!< 0x00000020 Address control */ + __IM uint32_t RESERVED2[7]; + __IOM uint32_t RD_CMD_CTL; /*!< 0x00000040 Read command control */ + __IOM uint32_t RD_ADDR_CTL; /*!< 0x00000044 Read address control */ + __IOM uint32_t RD_MODE_CTL; /*!< 0x00000048 Read mode control */ + __IOM uint32_t RD_DUMMY_CTL; /*!< 0x0000004C Read dummy control */ + __IOM uint32_t RD_DATA_CTL; /*!< 0x00000050 Read data control */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t WR_CMD_CTL; /*!< 0x00000060 Write command control */ + __IOM uint32_t WR_ADDR_CTL; /*!< 0x00000064 Write address control */ + __IOM uint32_t WR_MODE_CTL; /*!< 0x00000068 Write mode control */ + __IOM uint32_t WR_DUMMY_CTL; /*!< 0x0000006C Write dummy control */ + __IOM uint32_t WR_DATA_CTL; /*!< 0x00000070 Write data control */ + __IM uint32_t RESERVED4[3]; +} SMIF_DEVICE_Type; /*!< Size = 116 (0x74) */ + +/** + * \brief Serial Memory Interface (SMIF) + */ +typedef struct { /*!< SMIF Structure */ + __IOM uint32_t CTL; /*!< 0x00000000 Control */ + __IM uint32_t STATUS; /*!< 0x00000004 Status */ + __IM uint32_t RESERVED[15]; + __IM uint32_t TX_CMD_FIFO_STATUS; /*!< 0x00000044 Transmitter command FIFO status */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TX_CMD_FIFO_WR; /*!< 0x00000050 Transmitter command FIFO write */ + __IM uint32_t RESERVED2[11]; + __IOM uint32_t TX_DATA_FIFO_CTL; /*!< 0x00000080 Transmitter data FIFO control */ + __IM uint32_t TX_DATA_FIFO_STATUS; /*!< 0x00000084 Transmitter data FIFO status */ + __IM uint32_t RESERVED3[2]; + __OM uint32_t TX_DATA_FIFO_WR1; /*!< 0x00000090 Transmitter data FIFO write */ + __OM uint32_t TX_DATA_FIFO_WR2; /*!< 0x00000094 Transmitter data FIFO write */ + __OM uint32_t TX_DATA_FIFO_WR4; /*!< 0x00000098 Transmitter data FIFO write */ + __IM uint32_t RESERVED4[9]; + __IOM uint32_t RX_DATA_FIFO_CTL; /*!< 0x000000C0 Receiver data FIFO control */ + __IM uint32_t RX_DATA_FIFO_STATUS; /*!< 0x000000C4 Receiver data FIFO status */ + __IM uint32_t RESERVED5[2]; + __IM uint32_t RX_DATA_FIFO_RD1; /*!< 0x000000D0 Receiver data FIFO read */ + __IM uint32_t RX_DATA_FIFO_RD2; /*!< 0x000000D4 Receiver data FIFO read */ + __IM uint32_t RX_DATA_FIFO_RD4; /*!< 0x000000D8 Receiver data FIFO read */ + __IM uint32_t RESERVED6; + __IM uint32_t RX_DATA_FIFO_RD1_SILENT; /*!< 0x000000E0 Receiver data FIFO silent read */ + __IM uint32_t RESERVED7[7]; + __IOM uint32_t SLOW_CA_CTL; /*!< 0x00000100 Slow cache control */ + __IM uint32_t RESERVED8; + __IOM uint32_t SLOW_CA_CMD; /*!< 0x00000108 Slow cache command */ + __IM uint32_t RESERVED9[13]; + __IM uint32_t SLOW_CA_STATUS0; /*!< 0x00000140 Slow cache status 0 */ + __IM uint32_t SLOW_CA_STATUS1; /*!< 0x00000144 Slow cache status 1 */ + __IM uint32_t SLOW_CA_STATUS2; /*!< 0x00000148 Slow cache status 2 */ + __IM uint32_t RESERVED10[13]; + __IOM uint32_t FAST_CA_CTL; /*!< 0x00000180 Fast cache control */ + __IM uint32_t RESERVED11; + __IOM uint32_t FAST_CA_CMD; /*!< 0x00000188 Fast cache command */ + __IM uint32_t RESERVED12[13]; + __IM uint32_t FAST_CA_STATUS0; /*!< 0x000001C0 Fast cache status 0 */ + __IM uint32_t FAST_CA_STATUS1; /*!< 0x000001C4 Fast cache status 1 */ + __IM uint32_t FAST_CA_STATUS2; /*!< 0x000001C8 Fast cache status 2 */ + __IM uint32_t RESERVED13[13]; + __IOM uint32_t CRYPTO_CMD; /*!< 0x00000200 Cryptography Command */ + __IM uint32_t RESERVED14[7]; + __IOM uint32_t CRYPTO_INPUT0; /*!< 0x00000220 Cryptography input 0 */ + __IOM uint32_t CRYPTO_INPUT1; /*!< 0x00000224 Cryptography input 1 */ + __IOM uint32_t CRYPTO_INPUT2; /*!< 0x00000228 Cryptography input 2 */ + __IOM uint32_t CRYPTO_INPUT3; /*!< 0x0000022C Cryptography input 3 */ + __IM uint32_t RESERVED15[4]; + __OM uint32_t CRYPTO_KEY0; /*!< 0x00000240 Cryptography key 0 */ + __OM uint32_t CRYPTO_KEY1; /*!< 0x00000244 Cryptography key 1 */ + __OM uint32_t CRYPTO_KEY2; /*!< 0x00000248 Cryptography key 2 */ + __OM uint32_t CRYPTO_KEY3; /*!< 0x0000024C Cryptography key 3 */ + __IM uint32_t RESERVED16[4]; + __IOM uint32_t CRYPTO_OUTPUT0; /*!< 0x00000260 Cryptography output 0 */ + __IOM uint32_t CRYPTO_OUTPUT1; /*!< 0x00000264 Cryptography output 1 */ + __IOM uint32_t CRYPTO_OUTPUT2; /*!< 0x00000268 Cryptography output 2 */ + __IOM uint32_t CRYPTO_OUTPUT3; /*!< 0x0000026C Cryptography output 3 */ + __IM uint32_t RESERVED17[340]; + __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */ + __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */ + __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */ + __IM uint32_t RESERVED18[12]; + SMIF_DEVICE_Type DEVICE[4]; /*!< 0x00000800 Device (only used in XIP mode) */ +} SMIF_Type; /*!< Size = 2560 (0xA00) */ + + +/* ==================================================== SMIF_DEVICE.CTL ==================================================== */ +#define SMIF_DEVICE_CTL_WR_EN_Pos (0UL) /*!< SMIF_DEVICE CTL: WR_EN (Bit 0) */ +#define SMIF_DEVICE_CTL_WR_EN_Msk (0x1UL) /*!< SMIF_DEVICE CTL: WR_EN (Bitfield-Mask: 0x01) */ +#define SMIF_DEVICE_CTL_CRYPTO_EN_Pos (8UL) /*!< SMIF_DEVICE CTL: CRYPTO_EN (Bit 8) */ +#define SMIF_DEVICE_CTL_CRYPTO_EN_Msk (0x100UL) /*!< SMIF_DEVICE CTL: CRYPTO_EN (Bitfield-Mask: 0x01) */ +#define SMIF_DEVICE_CTL_DATA_SEL_Pos (16UL) /*!< SMIF_DEVICE CTL: DATA_SEL (Bit 16) */ +#define SMIF_DEVICE_CTL_DATA_SEL_Msk (0x30000UL) /*!< SMIF_DEVICE CTL: DATA_SEL (Bitfield-Mask: 0x03) */ +#define SMIF_DEVICE_CTL_ENABLED_Pos (31UL) /*!< SMIF_DEVICE CTL: ENABLED (Bit 31) */ +#define SMIF_DEVICE_CTL_ENABLED_Msk (0x80000000UL) /*!< SMIF_DEVICE CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* =================================================== SMIF_DEVICE.ADDR ==================================================== */ +#define SMIF_DEVICE_ADDR_ADDR_Pos (8UL) /*!< SMIF_DEVICE ADDR: ADDR (Bit 8) */ +#define SMIF_DEVICE_ADDR_ADDR_Msk (0xffffff00UL) /*!< SMIF_DEVICE ADDR: ADDR (Bitfield-Mask: 0xffffff) */ +/* =================================================== SMIF_DEVICE.MASK ==================================================== */ +#define SMIF_DEVICE_MASK_MASK_Pos (8UL) /*!< SMIF_DEVICE MASK: MASK (Bit 8) */ +#define SMIF_DEVICE_MASK_MASK_Msk (0xffffff00UL) /*!< SMIF_DEVICE MASK: MASK (Bitfield-Mask: 0xffffff) */ +/* ================================================= SMIF_DEVICE.ADDR_CTL ================================================== */ +#define SMIF_DEVICE_ADDR_CTL_SIZE2_Pos (0UL) /*!< SMIF_DEVICE ADDR_CTL: SIZE2 (Bit 0) */ +#define SMIF_DEVICE_ADDR_CTL_SIZE2_Msk (0x3UL) /*!< SMIF_DEVICE ADDR_CTL: SIZE2 (Bitfield-Mask: 0x03) */ +#define SMIF_DEVICE_ADDR_CTL_DIV2_Pos (8UL) /*!< SMIF_DEVICE ADDR_CTL: DIV2 (Bit 8) */ +#define SMIF_DEVICE_ADDR_CTL_DIV2_Msk (0x100UL) /*!< SMIF_DEVICE ADDR_CTL: DIV2 (Bitfield-Mask: 0x01) */ +/* ================================================ SMIF_DEVICE.RD_CMD_CTL ================================================= */ +#define SMIF_DEVICE_RD_CMD_CTL_CODE_Pos (0UL) /*!< SMIF_DEVICE RD_CMD_CTL: CODE (Bit 0) */ +#define SMIF_DEVICE_RD_CMD_CTL_CODE_Msk (0xffUL) /*!< SMIF_DEVICE RD_CMD_CTL: CODE (Bitfield-Mask: 0xff) */ +#define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Pos (16UL) /*!< SMIF_DEVICE RD_CMD_CTL: WIDTH (Bit 16) */ +#define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Msk (0x30000UL) /*!< SMIF_DEVICE RD_CMD_CTL: WIDTH (Bitfield-Mask: 0x03) */ +#define SMIF_DEVICE_RD_CMD_CTL_PRESENT_Pos (31UL) /*!< SMIF_DEVICE RD_CMD_CTL: PRESENT (Bit 31) */ +#define SMIF_DEVICE_RD_CMD_CTL_PRESENT_Msk (0x80000000UL) /*!< SMIF_DEVICE RD_CMD_CTL: PRESENT (Bitfield-Mask: 0x01) */ +/* ================================================ SMIF_DEVICE.RD_ADDR_CTL ================================================ */ +#define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Pos (16UL) /*!< SMIF_DEVICE RD_ADDR_CTL: WIDTH (Bit 16) */ +#define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Msk (0x30000UL) /*!< SMIF_DEVICE RD_ADDR_CTL: WIDTH (Bitfield-Mask: 0x03) */ +/* ================================================ SMIF_DEVICE.RD_MODE_CTL ================================================ */ +#define SMIF_DEVICE_RD_MODE_CTL_CODE_Pos (0UL) /*!< SMIF_DEVICE RD_MODE_CTL: CODE (Bit 0) */ +#define SMIF_DEVICE_RD_MODE_CTL_CODE_Msk (0xffUL) /*!< SMIF_DEVICE RD_MODE_CTL: CODE (Bitfield-Mask: 0xff) */ +#define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Pos (16UL) /*!< SMIF_DEVICE RD_MODE_CTL: WIDTH (Bit 16) */ +#define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Msk (0x30000UL) /*!< SMIF_DEVICE RD_MODE_CTL: WIDTH (Bitfield-Mask: 0x03) */ +#define SMIF_DEVICE_RD_MODE_CTL_PRESENT_Pos (31UL) /*!< SMIF_DEVICE RD_MODE_CTL: PRESENT (Bit 31) */ +#define SMIF_DEVICE_RD_MODE_CTL_PRESENT_Msk (0x80000000UL) /*!< SMIF_DEVICE RD_MODE_CTL: PRESENT (Bitfield-Mask: 0x01) */ +/* =============================================== SMIF_DEVICE.RD_DUMMY_CTL ================================================ */ +#define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Pos (0UL) /*!< SMIF_DEVICE RD_DUMMY_CTL: SIZE5 (Bit 0) */ +#define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Msk (0x1fUL) /*!< SMIF_DEVICE RD_DUMMY_CTL: SIZE5 (Bitfield-Mask: 0x1f) */ +#define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Pos (31UL) /*!< SMIF_DEVICE RD_DUMMY_CTL: PRESENT (Bit 31) */ +#define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Msk (0x80000000UL) /*!< SMIF_DEVICE RD_DUMMY_CTL: PRESENT (Bitfield-Mask: 0x01) */ +/* ================================================ SMIF_DEVICE.RD_DATA_CTL ================================================ */ +#define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Pos (16UL) /*!< SMIF_DEVICE RD_DATA_CTL: WIDTH (Bit 16) */ +#define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Msk (0x30000UL) /*!< SMIF_DEVICE RD_DATA_CTL: WIDTH (Bitfield-Mask: 0x03) */ +/* ================================================ SMIF_DEVICE.WR_CMD_CTL ================================================= */ +#define SMIF_DEVICE_WR_CMD_CTL_CODE_Pos (0UL) /*!< SMIF_DEVICE WR_CMD_CTL: CODE (Bit 0) */ +#define SMIF_DEVICE_WR_CMD_CTL_CODE_Msk (0xffUL) /*!< SMIF_DEVICE WR_CMD_CTL: CODE (Bitfield-Mask: 0xff) */ +#define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Pos (16UL) /*!< SMIF_DEVICE WR_CMD_CTL: WIDTH (Bit 16) */ +#define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Msk (0x30000UL) /*!< SMIF_DEVICE WR_CMD_CTL: WIDTH (Bitfield-Mask: 0x03) */ +#define SMIF_DEVICE_WR_CMD_CTL_PRESENT_Pos (31UL) /*!< SMIF_DEVICE WR_CMD_CTL: PRESENT (Bit 31) */ +#define SMIF_DEVICE_WR_CMD_CTL_PRESENT_Msk (0x80000000UL) /*!< SMIF_DEVICE WR_CMD_CTL: PRESENT (Bitfield-Mask: 0x01) */ +/* ================================================ SMIF_DEVICE.WR_ADDR_CTL ================================================ */ +#define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Pos (16UL) /*!< SMIF_DEVICE WR_ADDR_CTL: WIDTH (Bit 16) */ +#define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Msk (0x30000UL) /*!< SMIF_DEVICE WR_ADDR_CTL: WIDTH (Bitfield-Mask: 0x03) */ +/* ================================================ SMIF_DEVICE.WR_MODE_CTL ================================================ */ +#define SMIF_DEVICE_WR_MODE_CTL_CODE_Pos (0UL) /*!< SMIF_DEVICE WR_MODE_CTL: CODE (Bit 0) */ +#define SMIF_DEVICE_WR_MODE_CTL_CODE_Msk (0xffUL) /*!< SMIF_DEVICE WR_MODE_CTL: CODE (Bitfield-Mask: 0xff) */ +#define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Pos (16UL) /*!< SMIF_DEVICE WR_MODE_CTL: WIDTH (Bit 16) */ +#define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Msk (0x30000UL) /*!< SMIF_DEVICE WR_MODE_CTL: WIDTH (Bitfield-Mask: 0x03) */ +#define SMIF_DEVICE_WR_MODE_CTL_PRESENT_Pos (31UL) /*!< SMIF_DEVICE WR_MODE_CTL: PRESENT (Bit 31) */ +#define SMIF_DEVICE_WR_MODE_CTL_PRESENT_Msk (0x80000000UL) /*!< SMIF_DEVICE WR_MODE_CTL: PRESENT (Bitfield-Mask: 0x01) */ +/* =============================================== SMIF_DEVICE.WR_DUMMY_CTL ================================================ */ +#define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Pos (0UL) /*!< SMIF_DEVICE WR_DUMMY_CTL: SIZE5 (Bit 0) */ +#define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Msk (0x1fUL) /*!< SMIF_DEVICE WR_DUMMY_CTL: SIZE5 (Bitfield-Mask: 0x1f) */ +#define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Pos (31UL) /*!< SMIF_DEVICE WR_DUMMY_CTL: PRESENT (Bit 31) */ +#define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Msk (0x80000000UL) /*!< SMIF_DEVICE WR_DUMMY_CTL: PRESENT (Bitfield-Mask: 0x01) */ +/* ================================================ SMIF_DEVICE.WR_DATA_CTL ================================================ */ +#define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Pos (16UL) /*!< SMIF_DEVICE WR_DATA_CTL: WIDTH (Bit 16) */ +#define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Msk (0x30000UL) /*!< SMIF_DEVICE WR_DATA_CTL: WIDTH (Bitfield-Mask: 0x03) */ + + +/* ======================================================= SMIF.CTL ======================================================== */ +#define SMIF_CTL_XIP_MODE_Pos (0UL) /*!< SMIF CTL: XIP_MODE (Bit 0) */ +#define SMIF_CTL_XIP_MODE_Msk (0x1UL) /*!< SMIF CTL: XIP_MODE (Bitfield-Mask: 0x01) */ +#define SMIF_CTL_CLOCK_IF_RX_SEL_Pos (12UL) /*!< SMIF CTL: CLOCK_IF_RX_SEL (Bit 12) */ +#define SMIF_CTL_CLOCK_IF_RX_SEL_Msk (0x3000UL) /*!< SMIF CTL: CLOCK_IF_RX_SEL (Bitfield-Mask: 0x03) */ +#define SMIF_CTL_DESELECT_DELAY_Pos (16UL) /*!< SMIF CTL: DESELECT_DELAY (Bit 16) */ +#define SMIF_CTL_DESELECT_DELAY_Msk (0x70000UL) /*!< SMIF CTL: DESELECT_DELAY (Bitfield-Mask: 0x07) */ +#define SMIF_CTL_BLOCK_Pos (24UL) /*!< SMIF CTL: BLOCK (Bit 24) */ +#define SMIF_CTL_BLOCK_Msk (0x1000000UL) /*!< SMIF CTL: BLOCK (Bitfield-Mask: 0x01) */ +#define SMIF_CTL_ENABLED_Pos (31UL) /*!< SMIF CTL: ENABLED (Bit 31) */ +#define SMIF_CTL_ENABLED_Msk (0x80000000UL) /*!< SMIF CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* ====================================================== SMIF.STATUS ====================================================== */ +#define SMIF_STATUS_BUSY_Pos (31UL) /*!< SMIF STATUS: BUSY (Bit 31) */ +#define SMIF_STATUS_BUSY_Msk (0x80000000UL) /*!< SMIF STATUS: BUSY (Bitfield-Mask: 0x01) */ +/* ================================================ SMIF.TX_CMD_FIFO_STATUS ================================================ */ +#define SMIF_TX_CMD_FIFO_STATUS_USED3_Pos (0UL) /*!< SMIF TX_CMD_FIFO_STATUS: USED3 (Bit 0) */ +#define SMIF_TX_CMD_FIFO_STATUS_USED3_Msk (0x7UL) /*!< SMIF TX_CMD_FIFO_STATUS: USED3 (Bitfield-Mask: 0x07) */ +/* ================================================== SMIF.TX_CMD_FIFO_WR ================================================== */ +#define SMIF_TX_CMD_FIFO_WR_DATA20_Pos (0UL) /*!< SMIF TX_CMD_FIFO_WR: DATA20 (Bit 0) */ +#define SMIF_TX_CMD_FIFO_WR_DATA20_Msk (0xfffffUL) /*!< SMIF TX_CMD_FIFO_WR: DATA20 (Bitfield-Mask: 0xfffff) */ +/* ================================================= SMIF.TX_DATA_FIFO_CTL ================================================= */ +#define SMIF_TX_DATA_FIFO_CTL_TRIGGER_LEVEL_Pos (0UL) /*!< SMIF TX_DATA_FIFO_CTL: TRIGGER_LEVEL (Bit 0) */ +#define SMIF_TX_DATA_FIFO_CTL_TRIGGER_LEVEL_Msk (0x7UL) /*!< SMIF TX_DATA_FIFO_CTL: TRIGGER_LEVEL (Bitfield-Mask: 0x07)*/ +/* =============================================== SMIF.TX_DATA_FIFO_STATUS ================================================ */ +#define SMIF_TX_DATA_FIFO_STATUS_USED4_Pos (0UL) /*!< SMIF TX_DATA_FIFO_STATUS: USED4 (Bit 0) */ +#define SMIF_TX_DATA_FIFO_STATUS_USED4_Msk (0xfUL) /*!< SMIF TX_DATA_FIFO_STATUS: USED4 (Bitfield-Mask: 0x0f) */ +/* ================================================= SMIF.TX_DATA_FIFO_WR1 ================================================= */ +#define SMIF_TX_DATA_FIFO_WR1_DATA0_Pos (0UL) /*!< SMIF TX_DATA_FIFO_WR1: DATA0 (Bit 0) */ +#define SMIF_TX_DATA_FIFO_WR1_DATA0_Msk (0xffUL) /*!< SMIF TX_DATA_FIFO_WR1: DATA0 (Bitfield-Mask: 0xff) */ +/* ================================================= SMIF.TX_DATA_FIFO_WR2 ================================================= */ +#define SMIF_TX_DATA_FIFO_WR2_DATA0_Pos (0UL) /*!< SMIF TX_DATA_FIFO_WR2: DATA0 (Bit 0) */ +#define SMIF_TX_DATA_FIFO_WR2_DATA0_Msk (0xffUL) /*!< SMIF TX_DATA_FIFO_WR2: DATA0 (Bitfield-Mask: 0xff) */ +#define SMIF_TX_DATA_FIFO_WR2_DATA1_Pos (8UL) /*!< SMIF TX_DATA_FIFO_WR2: DATA1 (Bit 8) */ +#define SMIF_TX_DATA_FIFO_WR2_DATA1_Msk (0xff00UL) /*!< SMIF TX_DATA_FIFO_WR2: DATA1 (Bitfield-Mask: 0xff) */ +/* ================================================= SMIF.TX_DATA_FIFO_WR4 ================================================= */ +#define SMIF_TX_DATA_FIFO_WR4_DATA0_Pos (0UL) /*!< SMIF TX_DATA_FIFO_WR4: DATA0 (Bit 0) */ +#define SMIF_TX_DATA_FIFO_WR4_DATA0_Msk (0xffUL) /*!< SMIF TX_DATA_FIFO_WR4: DATA0 (Bitfield-Mask: 0xff) */ +#define SMIF_TX_DATA_FIFO_WR4_DATA1_Pos (8UL) /*!< SMIF TX_DATA_FIFO_WR4: DATA1 (Bit 8) */ +#define SMIF_TX_DATA_FIFO_WR4_DATA1_Msk (0xff00UL) /*!< SMIF TX_DATA_FIFO_WR4: DATA1 (Bitfield-Mask: 0xff) */ +#define SMIF_TX_DATA_FIFO_WR4_DATA2_Pos (16UL) /*!< SMIF TX_DATA_FIFO_WR4: DATA2 (Bit 16) */ +#define SMIF_TX_DATA_FIFO_WR4_DATA2_Msk (0xff0000UL) /*!< SMIF TX_DATA_FIFO_WR4: DATA2 (Bitfield-Mask: 0xff) */ +#define SMIF_TX_DATA_FIFO_WR4_DATA3_Pos (24UL) /*!< SMIF TX_DATA_FIFO_WR4: DATA3 (Bit 24) */ +#define SMIF_TX_DATA_FIFO_WR4_DATA3_Msk (0xff000000UL) /*!< SMIF TX_DATA_FIFO_WR4: DATA3 (Bitfield-Mask: 0xff) */ +/* ================================================= SMIF.RX_DATA_FIFO_CTL ================================================= */ +#define SMIF_RX_DATA_FIFO_CTL_TRIGGER_LEVEL_Pos (0UL) /*!< SMIF RX_DATA_FIFO_CTL: TRIGGER_LEVEL (Bit 0) */ +#define SMIF_RX_DATA_FIFO_CTL_TRIGGER_LEVEL_Msk (0x7UL) /*!< SMIF RX_DATA_FIFO_CTL: TRIGGER_LEVEL (Bitfield-Mask: 0x07)*/ +/* =============================================== SMIF.RX_DATA_FIFO_STATUS ================================================ */ +#define SMIF_RX_DATA_FIFO_STATUS_USED4_Pos (0UL) /*!< SMIF RX_DATA_FIFO_STATUS: USED4 (Bit 0) */ +#define SMIF_RX_DATA_FIFO_STATUS_USED4_Msk (0xfUL) /*!< SMIF RX_DATA_FIFO_STATUS: USED4 (Bitfield-Mask: 0x0f) */ +/* ================================================= SMIF.RX_DATA_FIFO_RD1 ================================================= */ +#define SMIF_RX_DATA_FIFO_RD1_DATA0_Pos (0UL) /*!< SMIF RX_DATA_FIFO_RD1: DATA0 (Bit 0) */ +#define SMIF_RX_DATA_FIFO_RD1_DATA0_Msk (0xffUL) /*!< SMIF RX_DATA_FIFO_RD1: DATA0 (Bitfield-Mask: 0xff) */ +/* ================================================= SMIF.RX_DATA_FIFO_RD2 ================================================= */ +#define SMIF_RX_DATA_FIFO_RD2_DATA0_Pos (0UL) /*!< SMIF RX_DATA_FIFO_RD2: DATA0 (Bit 0) */ +#define SMIF_RX_DATA_FIFO_RD2_DATA0_Msk (0xffUL) /*!< SMIF RX_DATA_FIFO_RD2: DATA0 (Bitfield-Mask: 0xff) */ +#define SMIF_RX_DATA_FIFO_RD2_DATA1_Pos (8UL) /*!< SMIF RX_DATA_FIFO_RD2: DATA1 (Bit 8) */ +#define SMIF_RX_DATA_FIFO_RD2_DATA1_Msk (0xff00UL) /*!< SMIF RX_DATA_FIFO_RD2: DATA1 (Bitfield-Mask: 0xff) */ +/* ================================================= SMIF.RX_DATA_FIFO_RD4 ================================================= */ +#define SMIF_RX_DATA_FIFO_RD4_DATA0_Pos (0UL) /*!< SMIF RX_DATA_FIFO_RD4: DATA0 (Bit 0) */ +#define SMIF_RX_DATA_FIFO_RD4_DATA0_Msk (0xffUL) /*!< SMIF RX_DATA_FIFO_RD4: DATA0 (Bitfield-Mask: 0xff) */ +#define SMIF_RX_DATA_FIFO_RD4_DATA1_Pos (8UL) /*!< SMIF RX_DATA_FIFO_RD4: DATA1 (Bit 8) */ +#define SMIF_RX_DATA_FIFO_RD4_DATA1_Msk (0xff00UL) /*!< SMIF RX_DATA_FIFO_RD4: DATA1 (Bitfield-Mask: 0xff) */ +#define SMIF_RX_DATA_FIFO_RD4_DATA2_Pos (16UL) /*!< SMIF RX_DATA_FIFO_RD4: DATA2 (Bit 16) */ +#define SMIF_RX_DATA_FIFO_RD4_DATA2_Msk (0xff0000UL) /*!< SMIF RX_DATA_FIFO_RD4: DATA2 (Bitfield-Mask: 0xff) */ +#define SMIF_RX_DATA_FIFO_RD4_DATA3_Pos (24UL) /*!< SMIF RX_DATA_FIFO_RD4: DATA3 (Bit 24) */ +#define SMIF_RX_DATA_FIFO_RD4_DATA3_Msk (0xff000000UL) /*!< SMIF RX_DATA_FIFO_RD4: DATA3 (Bitfield-Mask: 0xff) */ +/* ============================================= SMIF.RX_DATA_FIFO_RD1_SILENT ============================================== */ +#define SMIF_RX_DATA_FIFO_RD1_SILENT_DATA0_Pos (0UL) /*!< SMIF RX_DATA_FIFO_RD1_SILENT: DATA0 (Bit 0) */ +#define SMIF_RX_DATA_FIFO_RD1_SILENT_DATA0_Msk (0xffUL) /*!< SMIF RX_DATA_FIFO_RD1_SILENT: DATA0 (Bitfield-Mask: 0xff) */ +/* =================================================== SMIF.SLOW_CA_CTL ==================================================== */ +#define SMIF_SLOW_CA_CTL_WAY_Pos (16UL) /*!< SMIF SLOW_CA_CTL: WAY (Bit 16) */ +#define SMIF_SLOW_CA_CTL_WAY_Msk (0x30000UL) /*!< SMIF SLOW_CA_CTL: WAY (Bitfield-Mask: 0x03) */ +#define SMIF_SLOW_CA_CTL_SET_ADDR_Pos (24UL) /*!< SMIF SLOW_CA_CTL: SET_ADDR (Bit 24) */ +#define SMIF_SLOW_CA_CTL_SET_ADDR_Msk (0x3000000UL) /*!< SMIF SLOW_CA_CTL: SET_ADDR (Bitfield-Mask: 0x03) */ +#define SMIF_SLOW_CA_CTL_PREF_EN_Pos (30UL) /*!< SMIF SLOW_CA_CTL: PREF_EN (Bit 30) */ +#define SMIF_SLOW_CA_CTL_PREF_EN_Msk (0x40000000UL) /*!< SMIF SLOW_CA_CTL: PREF_EN (Bitfield-Mask: 0x01) */ +#define SMIF_SLOW_CA_CTL_ENABLED_Pos (31UL) /*!< SMIF SLOW_CA_CTL: ENABLED (Bit 31) */ +#define SMIF_SLOW_CA_CTL_ENABLED_Msk (0x80000000UL) /*!< SMIF SLOW_CA_CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* =================================================== SMIF.SLOW_CA_CMD ==================================================== */ +#define SMIF_SLOW_CA_CMD_INV_Pos (0UL) /*!< SMIF SLOW_CA_CMD: INV (Bit 0) */ +#define SMIF_SLOW_CA_CMD_INV_Msk (0x1UL) /*!< SMIF SLOW_CA_CMD: INV (Bitfield-Mask: 0x01) */ +/* ================================================= SMIF.SLOW_CA_STATUS0 ================================================== */ +#define SMIF_SLOW_CA_STATUS0_VALID16_Pos (0UL) /*!< SMIF SLOW_CA_STATUS0: VALID16 (Bit 0) */ +#define SMIF_SLOW_CA_STATUS0_VALID16_Msk (0xffffUL) /*!< SMIF SLOW_CA_STATUS0: VALID16 (Bitfield-Mask: 0xffff) */ +/* ================================================= SMIF.SLOW_CA_STATUS1 ================================================== */ +#define SMIF_SLOW_CA_STATUS1_TAG_Pos (0UL) /*!< SMIF SLOW_CA_STATUS1: TAG (Bit 0) */ +#define SMIF_SLOW_CA_STATUS1_TAG_Msk (0xffffffffUL) /*!< SMIF SLOW_CA_STATUS1: TAG (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SMIF.SLOW_CA_STATUS2 ================================================== */ +#define SMIF_SLOW_CA_STATUS2_LRU_Pos (0UL) /*!< SMIF SLOW_CA_STATUS2: LRU (Bit 0) */ +#define SMIF_SLOW_CA_STATUS2_LRU_Msk (0x3fUL) /*!< SMIF SLOW_CA_STATUS2: LRU (Bitfield-Mask: 0x3f) */ +/* =================================================== SMIF.FAST_CA_CTL ==================================================== */ +#define SMIF_FAST_CA_CTL_WAY_Pos (16UL) /*!< SMIF FAST_CA_CTL: WAY (Bit 16) */ +#define SMIF_FAST_CA_CTL_WAY_Msk (0x30000UL) /*!< SMIF FAST_CA_CTL: WAY (Bitfield-Mask: 0x03) */ +#define SMIF_FAST_CA_CTL_SET_ADDR_Pos (24UL) /*!< SMIF FAST_CA_CTL: SET_ADDR (Bit 24) */ +#define SMIF_FAST_CA_CTL_SET_ADDR_Msk (0x3000000UL) /*!< SMIF FAST_CA_CTL: SET_ADDR (Bitfield-Mask: 0x03) */ +#define SMIF_FAST_CA_CTL_PREF_EN_Pos (30UL) /*!< SMIF FAST_CA_CTL: PREF_EN (Bit 30) */ +#define SMIF_FAST_CA_CTL_PREF_EN_Msk (0x40000000UL) /*!< SMIF FAST_CA_CTL: PREF_EN (Bitfield-Mask: 0x01) */ +#define SMIF_FAST_CA_CTL_ENABLED_Pos (31UL) /*!< SMIF FAST_CA_CTL: ENABLED (Bit 31) */ +#define SMIF_FAST_CA_CTL_ENABLED_Msk (0x80000000UL) /*!< SMIF FAST_CA_CTL: ENABLED (Bitfield-Mask: 0x01) */ +/* =================================================== SMIF.FAST_CA_CMD ==================================================== */ +#define SMIF_FAST_CA_CMD_INV_Pos (0UL) /*!< SMIF FAST_CA_CMD: INV (Bit 0) */ +#define SMIF_FAST_CA_CMD_INV_Msk (0x1UL) /*!< SMIF FAST_CA_CMD: INV (Bitfield-Mask: 0x01) */ +/* ================================================= SMIF.FAST_CA_STATUS0 ================================================== */ +#define SMIF_FAST_CA_STATUS0_VALID16_Pos (0UL) /*!< SMIF FAST_CA_STATUS0: VALID16 (Bit 0) */ +#define SMIF_FAST_CA_STATUS0_VALID16_Msk (0xffffUL) /*!< SMIF FAST_CA_STATUS0: VALID16 (Bitfield-Mask: 0xffff) */ +/* ================================================= SMIF.FAST_CA_STATUS1 ================================================== */ +#define SMIF_FAST_CA_STATUS1_TAG_Pos (0UL) /*!< SMIF FAST_CA_STATUS1: TAG (Bit 0) */ +#define SMIF_FAST_CA_STATUS1_TAG_Msk (0xffffffffUL) /*!< SMIF FAST_CA_STATUS1: TAG (Bitfield-Mask: 0xffffffff) */ +/* ================================================= SMIF.FAST_CA_STATUS2 ================================================== */ +#define SMIF_FAST_CA_STATUS2_LRU_Pos (0UL) /*!< SMIF FAST_CA_STATUS2: LRU (Bit 0) */ +#define SMIF_FAST_CA_STATUS2_LRU_Msk (0x3fUL) /*!< SMIF FAST_CA_STATUS2: LRU (Bitfield-Mask: 0x3f) */ +/* ==================================================== SMIF.CRYPTO_CMD ==================================================== */ +#define SMIF_CRYPTO_CMD_START_Pos (0UL) /*!< SMIF CRYPTO_CMD: START (Bit 0) */ +#define SMIF_CRYPTO_CMD_START_Msk (0x1UL) /*!< SMIF CRYPTO_CMD: START (Bitfield-Mask: 0x01) */ +/* ================================================== SMIF.CRYPTO_INPUT0 =================================================== */ +#define SMIF_CRYPTO_INPUT0_INPUT_Pos (0UL) /*!< SMIF CRYPTO_INPUT0: INPUT (Bit 0) */ +#define SMIF_CRYPTO_INPUT0_INPUT_Msk (0xffffffffUL) /*!< SMIF CRYPTO_INPUT0: INPUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== SMIF.CRYPTO_INPUT1 =================================================== */ +#define SMIF_CRYPTO_INPUT1_INPUT_Pos (0UL) /*!< SMIF CRYPTO_INPUT1: INPUT (Bit 0) */ +#define SMIF_CRYPTO_INPUT1_INPUT_Msk (0xffffffffUL) /*!< SMIF CRYPTO_INPUT1: INPUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== SMIF.CRYPTO_INPUT2 =================================================== */ +#define SMIF_CRYPTO_INPUT2_INPUT_Pos (0UL) /*!< SMIF CRYPTO_INPUT2: INPUT (Bit 0) */ +#define SMIF_CRYPTO_INPUT2_INPUT_Msk (0xffffffffUL) /*!< SMIF CRYPTO_INPUT2: INPUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== SMIF.CRYPTO_INPUT3 =================================================== */ +#define SMIF_CRYPTO_INPUT3_INPUT_Pos (0UL) /*!< SMIF CRYPTO_INPUT3: INPUT (Bit 0) */ +#define SMIF_CRYPTO_INPUT3_INPUT_Msk (0xffffffffUL) /*!< SMIF CRYPTO_INPUT3: INPUT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== SMIF.CRYPTO_KEY0 ==================================================== */ +#define SMIF_CRYPTO_KEY0_KEY_Pos (0UL) /*!< SMIF CRYPTO_KEY0: KEY (Bit 0) */ +#define SMIF_CRYPTO_KEY0_KEY_Msk (0xffffffffUL) /*!< SMIF CRYPTO_KEY0: KEY (Bitfield-Mask: 0xffffffff) */ +/* =================================================== SMIF.CRYPTO_KEY1 ==================================================== */ +#define SMIF_CRYPTO_KEY1_KEY_Pos (0UL) /*!< SMIF CRYPTO_KEY1: KEY (Bit 0) */ +#define SMIF_CRYPTO_KEY1_KEY_Msk (0xffffffffUL) /*!< SMIF CRYPTO_KEY1: KEY (Bitfield-Mask: 0xffffffff) */ +/* =================================================== SMIF.CRYPTO_KEY2 ==================================================== */ +#define SMIF_CRYPTO_KEY2_KEY_Pos (0UL) /*!< SMIF CRYPTO_KEY2: KEY (Bit 0) */ +#define SMIF_CRYPTO_KEY2_KEY_Msk (0xffffffffUL) /*!< SMIF CRYPTO_KEY2: KEY (Bitfield-Mask: 0xffffffff) */ +/* =================================================== SMIF.CRYPTO_KEY3 ==================================================== */ +#define SMIF_CRYPTO_KEY3_KEY_Pos (0UL) /*!< SMIF CRYPTO_KEY3: KEY (Bit 0) */ +#define SMIF_CRYPTO_KEY3_KEY_Msk (0xffffffffUL) /*!< SMIF CRYPTO_KEY3: KEY (Bitfield-Mask: 0xffffffff) */ +/* ================================================== SMIF.CRYPTO_OUTPUT0 ================================================== */ +#define SMIF_CRYPTO_OUTPUT0_OUTPUT_Pos (0UL) /*!< SMIF CRYPTO_OUTPUT0: OUTPUT (Bit 0) */ +#define SMIF_CRYPTO_OUTPUT0_OUTPUT_Msk (0xffffffffUL) /*!< SMIF CRYPTO_OUTPUT0: OUTPUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== SMIF.CRYPTO_OUTPUT1 ================================================== */ +#define SMIF_CRYPTO_OUTPUT1_OUTPUT_Pos (0UL) /*!< SMIF CRYPTO_OUTPUT1: OUTPUT (Bit 0) */ +#define SMIF_CRYPTO_OUTPUT1_OUTPUT_Msk (0xffffffffUL) /*!< SMIF CRYPTO_OUTPUT1: OUTPUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== SMIF.CRYPTO_OUTPUT2 ================================================== */ +#define SMIF_CRYPTO_OUTPUT2_OUTPUT_Pos (0UL) /*!< SMIF CRYPTO_OUTPUT2: OUTPUT (Bit 0) */ +#define SMIF_CRYPTO_OUTPUT2_OUTPUT_Msk (0xffffffffUL) /*!< SMIF CRYPTO_OUTPUT2: OUTPUT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== SMIF.CRYPTO_OUTPUT3 ================================================== */ +#define SMIF_CRYPTO_OUTPUT3_OUTPUT_Pos (0UL) /*!< SMIF CRYPTO_OUTPUT3: OUTPUT (Bit 0) */ +#define SMIF_CRYPTO_OUTPUT3_OUTPUT_Msk (0xffffffffUL) /*!< SMIF CRYPTO_OUTPUT3: OUTPUT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SMIF.INTR ======================================================= */ +#define SMIF_INTR_TR_TX_REQ_Pos (0UL) /*!< SMIF INTR: TR_TX_REQ (Bit 0) */ +#define SMIF_INTR_TR_TX_REQ_Msk (0x1UL) /*!< SMIF INTR: TR_TX_REQ (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_TR_RX_REQ_Pos (1UL) /*!< SMIF INTR: TR_RX_REQ (Bit 1) */ +#define SMIF_INTR_TR_RX_REQ_Msk (0x2UL) /*!< SMIF INTR: TR_RX_REQ (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_XIP_ALIGNMENT_ERROR_Pos (2UL) /*!< SMIF INTR: XIP_ALIGNMENT_ERROR (Bit 2) */ +#define SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk (0x4UL) /*!< SMIF INTR: XIP_ALIGNMENT_ERROR (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Pos (3UL) /*!< SMIF INTR: TX_CMD_FIFO_OVERFLOW (Bit 3) */ +#define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk (0x8UL) /*!< SMIF INTR: TX_CMD_FIFO_OVERFLOW (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Pos (4UL) /*!< SMIF INTR: TX_DATA_FIFO_OVERFLOW (Bit 4) */ +#define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk (0x10UL) /*!< SMIF INTR: TX_DATA_FIFO_OVERFLOW (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Pos (5UL) /*!< SMIF INTR: RX_DATA_FIFO_UNDERFLOW (Bit 5) */ +#define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk (0x20UL) /*!< SMIF INTR: RX_DATA_FIFO_UNDERFLOW (Bitfield-Mask: 0x01) */ +/* ===================================================== SMIF.INTR_SET ===================================================== */ +#define SMIF_INTR_SET_TR_TX_REQ_Pos (0UL) /*!< SMIF INTR_SET: TR_TX_REQ (Bit 0) */ +#define SMIF_INTR_SET_TR_TX_REQ_Msk (0x1UL) /*!< SMIF INTR_SET: TR_TX_REQ (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_SET_TR_RX_REQ_Pos (1UL) /*!< SMIF INTR_SET: TR_RX_REQ (Bit 1) */ +#define SMIF_INTR_SET_TR_RX_REQ_Msk (0x2UL) /*!< SMIF INTR_SET: TR_RX_REQ (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Pos (2UL) /*!< SMIF INTR_SET: XIP_ALIGNMENT_ERROR (Bit 2) */ +#define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Msk (0x4UL) /*!< SMIF INTR_SET: XIP_ALIGNMENT_ERROR (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Pos (3UL) /*!< SMIF INTR_SET: TX_CMD_FIFO_OVERFLOW (Bit 3) */ +#define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Msk (0x8UL) /*!< SMIF INTR_SET: TX_CMD_FIFO_OVERFLOW (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Pos (4UL) /*!< SMIF INTR_SET: TX_DATA_FIFO_OVERFLOW (Bit 4) */ +#define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Msk (0x10UL) /*!< SMIF INTR_SET: TX_DATA_FIFO_OVERFLOW (Bitfield-Mask: 0x01)*/ +#define SMIF_INTR_SET_RX_DATA_FIFO_UNDERFLOW_Pos (5UL) /*!< SMIF INTR_SET: RX_DATA_FIFO_UNDERFLOW (Bit 5) */ +#define SMIF_INTR_SET_RX_DATA_FIFO_UNDERFLOW_Msk (0x20UL) /*!< SMIF INTR_SET: RX_DATA_FIFO_UNDERFLOW (Bitfield-Mask: 0x01)*/ +/* ==================================================== SMIF.INTR_MASK ===================================================== */ +#define SMIF_INTR_MASK_TR_TX_REQ_Pos (0UL) /*!< SMIF INTR_MASK: TR_TX_REQ (Bit 0) */ +#define SMIF_INTR_MASK_TR_TX_REQ_Msk (0x1UL) /*!< SMIF INTR_MASK: TR_TX_REQ (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_MASK_TR_RX_REQ_Pos (1UL) /*!< SMIF INTR_MASK: TR_RX_REQ (Bit 1) */ +#define SMIF_INTR_MASK_TR_RX_REQ_Msk (0x2UL) /*!< SMIF INTR_MASK: TR_RX_REQ (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Pos (2UL) /*!< SMIF INTR_MASK: XIP_ALIGNMENT_ERROR (Bit 2) */ +#define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Msk (0x4UL) /*!< SMIF INTR_MASK: XIP_ALIGNMENT_ERROR (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Pos (3UL) /*!< SMIF INTR_MASK: TX_CMD_FIFO_OVERFLOW (Bit 3) */ +#define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Msk (0x8UL) /*!< SMIF INTR_MASK: TX_CMD_FIFO_OVERFLOW (Bitfield-Mask: 0x01)*/ +#define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Pos (4UL) /*!< SMIF INTR_MASK: TX_DATA_FIFO_OVERFLOW (Bit 4) */ +#define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Msk (0x10UL) /*!< SMIF INTR_MASK: TX_DATA_FIFO_OVERFLOW (Bitfield-Mask: 0x01)*/ +#define SMIF_INTR_MASK_RX_DATA_FIFO_UNDERFLOW_Pos (5UL) /*!< SMIF INTR_MASK: RX_DATA_FIFO_UNDERFLOW (Bit 5) */ +#define SMIF_INTR_MASK_RX_DATA_FIFO_UNDERFLOW_Msk (0x20UL) /*!< SMIF INTR_MASK: RX_DATA_FIFO_UNDERFLOW (Bitfield-Mask: 0x01)*/ +/* =================================================== SMIF.INTR_MASKED ==================================================== */ +#define SMIF_INTR_MASKED_TR_TX_REQ_Pos (0UL) /*!< SMIF INTR_MASKED: TR_TX_REQ (Bit 0) */ +#define SMIF_INTR_MASKED_TR_TX_REQ_Msk (0x1UL) /*!< SMIF INTR_MASKED: TR_TX_REQ (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_MASKED_TR_RX_REQ_Pos (1UL) /*!< SMIF INTR_MASKED: TR_RX_REQ (Bit 1) */ +#define SMIF_INTR_MASKED_TR_RX_REQ_Msk (0x2UL) /*!< SMIF INTR_MASKED: TR_RX_REQ (Bitfield-Mask: 0x01) */ +#define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Pos (2UL) /*!< SMIF INTR_MASKED: XIP_ALIGNMENT_ERROR (Bit 2) */ +#define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Msk (0x4UL) /*!< SMIF INTR_MASKED: XIP_ALIGNMENT_ERROR (Bitfield-Mask: 0x01)*/ +#define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Pos (3UL) /*!< SMIF INTR_MASKED: TX_CMD_FIFO_OVERFLOW (Bit 3) */ +#define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Msk (0x8UL) /*!< SMIF INTR_MASKED: TX_CMD_FIFO_OVERFLOW (Bitfield-Mask: 0x01)*/ +#define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Pos (4UL) /*!< SMIF INTR_MASKED: TX_DATA_FIFO_OVERFLOW (Bit 4) */ +#define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Msk (0x10UL) /*!< SMIF INTR_MASKED: TX_DATA_FIFO_OVERFLOW (Bitfield-Mask: 0x01)*/ +#define SMIF_INTR_MASKED_RX_DATA_FIFO_UNDERFLOW_Pos (5UL) /*!< SMIF INTR_MASKED: RX_DATA_FIFO_UNDERFLOW (Bit 5) */ +#define SMIF_INTR_MASKED_RX_DATA_FIFO_UNDERFLOW_Msk (0x20UL) /*!< SMIF INTR_MASKED: RX_DATA_FIFO_UNDERFLOW (Bitfield-Mask: 0x01)*/ + + +#endif /* _CYIP_SMIF_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_srss.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_srss.h new file mode 100644 index 0000000000..53b9d7d786 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_srss.h @@ -0,0 +1,655 @@ +/***************************************************************************//** +* \file cyip_srss.h +* +* \brief +* SRSS IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_SRSS_H_ +#define _CYIP_SRSS_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ SRSS ================ */ +/* =========================================================================================================================== */ + +#define MCWDT_STRUCT_SECTION_SIZE 0x00000040UL +#define CLK_CSV_SECTION_SIZE 0x00000010UL +#define SRSS_SECTION_SIZE 0x00010000UL + +/** + * \brief Multi-Counter Watchdog Timer (MCWDT_STRUCT) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t MCWDT_CNTLOW; /*!< 0x00000004 Multi-Counter Watchdog Sub-counters 0/1 */ + __IOM uint32_t MCWDT_CNTHIGH; /*!< 0x00000008 Multi-Counter Watchdog Sub-counter 2 */ + __IOM uint32_t MCWDT_MATCH; /*!< 0x0000000C Multi-Counter Watchdog Counter Match Register */ + __IOM uint32_t MCWDT_CONFIG; /*!< 0x00000010 Multi-Counter Watchdog Counter Configuration */ + __IOM uint32_t MCWDT_CTL; /*!< 0x00000014 Multi-Counter Watchdog Counter Control */ + __IOM uint32_t MCWDT_INTR; /*!< 0x00000018 Multi-Counter Watchdog Counter Interrupt Register */ + __IOM uint32_t MCWDT_INTR_SET; /*!< 0x0000001C Multi-Counter Watchdog Counter Interrupt Set Register */ + __IOM uint32_t MCWDT_INTR_MASK; /*!< 0x00000020 Multi-Counter Watchdog Counter Interrupt Mask Register */ + __IM uint32_t MCWDT_INTR_MASKED; /*!< 0x00000024 Multi-Counter Watchdog Counter Interrupt Masked Register */ + __IOM uint32_t MCWDT_LOCK; /*!< 0x00000028 Multi-Counter Watchdog Counter Lock Register */ + __IM uint32_t RESERVED1[5]; +} MCWDT_STRUCT_Type; /*!< Size = 44 (0x2C) */ + +/** + * \brief SRSS Clock Supervisor (CSV) registers (CLK_CSV) + */ +typedef struct { + __IOM uint32_t HF_CTL; /*!< 0x00000000 HFCLK Clock Supervision Control Register */ + __IOM uint32_t HF_LIMIT; /*!< 0x00000004 HFCLK Clock Supervision Limit Register */ + __IM uint32_t HF_CNT; /*!< 0x00000008 HFCLK Clock Supervision Count Register */ + __IM uint32_t RESERVED; +} CLK_CSV_Type; /*!< Size = 12 (0xC) */ + +/** + * \brief SRSS Core Registers (SRSS) + */ +typedef struct { /*!< SRSS Structure */ + __IOM uint32_t PWR_CTL; /*!< 0x00000000 Power Mode Control */ + __IOM uint32_t PWR_HIBERNATE; /*!< 0x00000004 HIBERNATE Mode Register */ + __IOM uint32_t PWR_LVD_CTL; /*!< 0x00000008 Low Voltage Detector (LVD) Configuration Register */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t PWR_BUCK_CTL; /*!< 0x00000014 SIMO Buck Control Register */ + __IOM uint32_t PWR_BUCK_CTL2; /*!< 0x00000018 SIMO Buck Control Register 2 */ + __IM uint32_t PWR_LVD_STATUS; /*!< 0x0000001C Low Voltage Detector (LVD) Status Register */ + __IM uint32_t RESERVED1[24]; + __IOM uint32_t PWR_HIB_DATA[16]; /*!< 0x00000080 HIBERNATE Data Register */ + __IM uint32_t RESERVED2[48]; + __IOM uint32_t WDT_CTL; /*!< 0x00000180 Watchdog Counter Control Register */ + __IOM uint32_t WDT_CNT; /*!< 0x00000184 Watchdog Counter Count Register */ + __IOM uint32_t WDT_MATCH; /*!< 0x00000188 Watchdog Counter Match Register */ + __IM uint32_t RESERVED3[29]; + MCWDT_STRUCT_Type MCWDT_STRUCT[4]; /*!< 0x00000200 Multi-Counter Watchdog Timer */ + __IOM uint32_t CLK_DSI_SELECT[16]; /*!< 0x00000300 Clock DSI Select Register */ + __IOM uint32_t CLK_PATH_SELECT[16]; /*!< 0x00000340 Clock Path Select Register */ + __IOM uint32_t CLK_ROOT_SELECT[16]; /*!< 0x00000380 Clock Root Select Register */ + __IM uint32_t RESERVED4[16]; + CLK_CSV_Type CLK_CSV[16]; /*!< 0x00000400 SRSS Clock Supervisor (CSV) registers */ + __IOM uint32_t CLK_SELECT; /*!< 0x00000500 Clock selection register */ + __IOM uint32_t CLK_TIMER_CTL; /*!< 0x00000504 Timer Clock Control Register */ + __IOM uint32_t CLK_CSV_WCO_CTL; /*!< 0x00000508 WCO Clock Supervision Control Register */ + __IOM uint32_t CLK_ILO_CONFIG; /*!< 0x0000050C HVILO Configuration */ + __IOM uint32_t CLK_IMO_CONFIG; /*!< 0x00000510 IMO Configuration */ + __IOM uint32_t CLK_OUTPUT_FAST; /*!< 0x00000514 Fast Clock Output Select Register */ + __IOM uint32_t CLK_OUTPUT_SLOW; /*!< 0x00000518 Slow Clock Output Select Register */ + __IOM uint32_t CLK_CAL_CNT1; /*!< 0x0000051C Clock Calibration Counter 1 */ + __IM uint32_t CLK_CAL_CNT2; /*!< 0x00000520 Clock Calibration Counter 2 */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t CLK_ECO_CONFIG; /*!< 0x0000052C ECO Configuration Register */ + __IM uint32_t CLK_ECO_STATUS; /*!< 0x00000530 ECO Status Register */ + __IM uint32_t RESERVED6; + __IOM uint32_t CLK_WCO_DPLL; /*!< 0x00000538 WCO DPLL Register */ + __IOM uint32_t CLK_PILO_CONFIG; /*!< 0x0000053C Precision ILO Configuration Register */ + __IM uint32_t RESERVED7[16]; + __IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00000580 FLL Configuration Register */ + __IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00000584 FLL Configuration Register 2 */ + __IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00000588 FLL Configuration Register 3 */ + __IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000058C FLL Configuration Register 4 */ + __IOM uint32_t CLK_FLL_STATUS; /*!< 0x00000590 FLL Status Register */ + __IM uint32_t RESERVED8[27]; + __IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00000600 PLL Configuration Register */ + __IM uint32_t RESERVED9; + __IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00000640 PLL Status Register */ + __IM uint32_t RESERVED10[33]; + __IOM uint32_t SRSS_INTR; /*!< 0x00000700 SRSS Interrupt Register */ + __IOM uint32_t SRSS_INTR_SET; /*!< 0x00000704 SRSS Interrupt Set Register */ + __IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000708 SRSS Interrupt Mask Register */ + __IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000070C SRSS Interrupt Masked Register */ + __IOM uint32_t SRSS_INTR_CFG; /*!< 0x00000710 SRSS Interrupt Configuration Register */ + __IM uint32_t RESERVED11[59]; + __IOM uint32_t RES_CAUSE; /*!< 0x00000800 Reset Cause Observation Register */ + __IOM uint32_t RES_CAUSE2; /*!< 0x00000804 Reset Cause Observation Register 2 */ + __IM uint32_t RESERVED12[7614]; + __IOM uint32_t PWR_TRIM_REF_CTL; /*!< 0x00007F00 Reference Trim Register */ + __IOM uint32_t PWR_TRIM_BODOVP_CTL; /*!< 0x00007F04 BOD/OVP Trim Register */ + __IOM uint32_t CLK_TRIM_CCO_CTL; /*!< 0x00007F08 CCO Trim Register */ + __IOM uint32_t CLK_TRIM_CCO_CTL2; /*!< 0x00007F0C CCO Trim Register 2 */ + __IM uint32_t RESERVED13[8]; + __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00007F30 Wakeup Trim Register */ + __IM uint32_t RESERVED14[8183]; + __IOM uint32_t PWR_TRIM_LVD_CTL; /*!< 0x0000FF10 LVD Trim Register */ + __IM uint32_t RESERVED15; + __IOM uint32_t CLK_TRIM_ILO_CTL; /*!< 0x0000FF18 ILO Trim Register */ + __IOM uint32_t PWR_TRIM_PWRSYS_CTL; /*!< 0x0000FF1C Power System Trim Register */ + __IOM uint32_t CLK_TRIM_ECO_CTL; /*!< 0x0000FF20 ECO Trim Register */ + __IOM uint32_t CLK_TRIM_PILO_CTL; /*!< 0x0000FF24 PILO Trim Register */ + __IOM uint32_t CLK_TRIM_PILO_CTL2; /*!< 0x0000FF28 PILO Trim Register 2 */ + __IOM uint32_t CLK_TRIM_PILO_CTL3; /*!< 0x0000FF2C PILO Trim Register 3 */ +} SRSS_Type; /*!< Size = 65328 (0xFF30) */ + + +/* =============================================== MCWDT_STRUCT.MCWDT_CNTLOW =============================================== */ +#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Pos (0UL) /*!< MCWDT_STRUCT MCWDT_CNTLOW: WDT_CTR0 (Bit 0) */ +#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk (0xffffUL) /*!< MCWDT_STRUCT MCWDT_CNTLOW: WDT_CTR0 (Bitfield-Mask: 0xffff)*/ +#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos (16UL) /*!< MCWDT_STRUCT MCWDT_CNTLOW: WDT_CTR1 (Bit 16) */ +#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Msk (0xffff0000UL) /*!< MCWDT_STRUCT MCWDT_CNTLOW: WDT_CTR1 (Bitfield-Mask: 0xffff)*/ +/* ============================================== MCWDT_STRUCT.MCWDT_CNTHIGH =============================================== */ +#define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Pos (0UL) /*!< MCWDT_STRUCT MCWDT_CNTHIGH: WDT_CTR2 (Bit 0) */ +#define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Msk (0xffffffffUL) /*!< MCWDT_STRUCT MCWDT_CNTHIGH: WDT_CTR2 (Bitfield-Mask: 0xffffffff)*/ +/* =============================================== MCWDT_STRUCT.MCWDT_MATCH ================================================ */ +#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Pos (0UL) /*!< MCWDT_STRUCT MCWDT_MATCH: WDT_MATCH0 (Bit 0) */ +#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk (0xffffUL) /*!< MCWDT_STRUCT MCWDT_MATCH: WDT_MATCH0 (Bitfield-Mask: 0xffff)*/ +#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Pos (16UL) /*!< MCWDT_STRUCT MCWDT_MATCH: WDT_MATCH1 (Bit 16) */ +#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Msk (0xffff0000UL) /*!< MCWDT_STRUCT MCWDT_MATCH: WDT_MATCH1 (Bitfield-Mask: 0xffff)*/ +/* =============================================== MCWDT_STRUCT.MCWDT_CONFIG =============================================== */ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Pos (0UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_MODE0 (Bit 0) */ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Msk (0x3UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_MODE0 (Bitfield-Mask: 0x03)*/ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Pos (2UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_CLEAR0 (Bit 2) */ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk (0x4UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_CLEAR0 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Pos (3UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_CASCADE0_1 (Bit 3) */ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk (0x8UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_CASCADE0_1 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Pos (8UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_MODE1 (Bit 8) */ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Msk (0x300UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_MODE1 (Bitfield-Mask: 0x03)*/ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Pos (10UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_CLEAR1 (Bit 10) */ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk (0x400UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_CLEAR1 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Pos (11UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_CASCADE1_2 (Bit 11) */ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk (0x800UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_CASCADE1_2 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Pos (16UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_MODE2 (Bit 16) */ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Msk (0x10000UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_MODE2 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Pos (24UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_BITS2 (Bit 24) */ +#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Msk (0x1f000000UL) /*!< MCWDT_STRUCT MCWDT_CONFIG: WDT_BITS2 (Bitfield-Mask: 0x1f)*/ +/* ================================================ MCWDT_STRUCT.MCWDT_CTL ================================================= */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Pos (0UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLE0 (Bit 0) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk (0x1UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLE0 (Bitfield-Mask: 0x01) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Pos (1UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLED0 (Bit 1) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Msk (0x2UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLED0 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Pos (3UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_RESET0 (Bit 3) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk (0x8UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_RESET0 (Bitfield-Mask: 0x01) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Pos (8UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLE1 (Bit 8) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk (0x100UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLE1 (Bitfield-Mask: 0x01) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Pos (9UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLED1 (Bit 9) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Msk (0x200UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLED1 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Pos (11UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_RESET1 (Bit 11) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk (0x800UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_RESET1 (Bitfield-Mask: 0x01) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Pos (16UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLE2 (Bit 16) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk (0x10000UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLE2 (Bitfield-Mask: 0x01) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Pos (17UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLED2 (Bit 17) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Msk (0x20000UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_ENABLED2 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Pos (19UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_RESET2 (Bit 19) */ +#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk (0x80000UL) /*!< MCWDT_STRUCT MCWDT_CTL: WDT_RESET2 (Bitfield-Mask: 0x01) */ +/* ================================================ MCWDT_STRUCT.MCWDT_INTR ================================================ */ +#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Pos (0UL) /*!< MCWDT_STRUCT MCWDT_INTR: MCWDT_INT0 (Bit 0) */ +#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Msk (0x1UL) /*!< MCWDT_STRUCT MCWDT_INTR: MCWDT_INT0 (Bitfield-Mask: 0x01) */ +#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Pos (1UL) /*!< MCWDT_STRUCT MCWDT_INTR: MCWDT_INT1 (Bit 1) */ +#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Msk (0x2UL) /*!< MCWDT_STRUCT MCWDT_INTR: MCWDT_INT1 (Bitfield-Mask: 0x01) */ +#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Pos (2UL) /*!< MCWDT_STRUCT MCWDT_INTR: MCWDT_INT2 (Bit 2) */ +#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Msk (0x4UL) /*!< MCWDT_STRUCT MCWDT_INTR: MCWDT_INT2 (Bitfield-Mask: 0x01) */ +/* ============================================== MCWDT_STRUCT.MCWDT_INTR_SET ============================================== */ +#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Pos (0UL) /*!< MCWDT_STRUCT MCWDT_INTR_SET: MCWDT_INT0 (Bit 0) */ +#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Msk (0x1UL) /*!< MCWDT_STRUCT MCWDT_INTR_SET: MCWDT_INT0 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Pos (1UL) /*!< MCWDT_STRUCT MCWDT_INTR_SET: MCWDT_INT1 (Bit 1) */ +#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Msk (0x2UL) /*!< MCWDT_STRUCT MCWDT_INTR_SET: MCWDT_INT1 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Pos (2UL) /*!< MCWDT_STRUCT MCWDT_INTR_SET: MCWDT_INT2 (Bit 2) */ +#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Msk (0x4UL) /*!< MCWDT_STRUCT MCWDT_INTR_SET: MCWDT_INT2 (Bitfield-Mask: 0x01)*/ +/* ============================================= MCWDT_STRUCT.MCWDT_INTR_MASK ============================================== */ +#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Pos (0UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASK: MCWDT_INT0 (Bit 0) */ +#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Msk (0x1UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASK: MCWDT_INT0 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Pos (1UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASK: MCWDT_INT1 (Bit 1) */ +#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Msk (0x2UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASK: MCWDT_INT1 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Pos (2UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASK: MCWDT_INT2 (Bit 2) */ +#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Msk (0x4UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASK: MCWDT_INT2 (Bitfield-Mask: 0x01)*/ +/* ============================================ MCWDT_STRUCT.MCWDT_INTR_MASKED ============================================= */ +#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Pos (0UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASKED: MCWDT_INT0 (Bit 0) */ +#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Msk (0x1UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASKED: MCWDT_INT0 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Pos (1UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASKED: MCWDT_INT1 (Bit 1) */ +#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Msk (0x2UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASKED: MCWDT_INT1 (Bitfield-Mask: 0x01)*/ +#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Pos (2UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASKED: MCWDT_INT2 (Bit 2) */ +#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Msk (0x4UL) /*!< MCWDT_STRUCT MCWDT_INTR_MASKED: MCWDT_INT2 (Bitfield-Mask: 0x01)*/ +/* ================================================ MCWDT_STRUCT.MCWDT_LOCK ================================================ */ +#define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Pos (30UL) /*!< MCWDT_STRUCT MCWDT_LOCK: MCWDT_LOCK (Bit 30) */ +#define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk (0xc0000000UL) /*!< MCWDT_STRUCT MCWDT_LOCK: MCWDT_LOCK (Bitfield-Mask: 0x03) */ + + +/* ==================================================== CLK_CSV.HF_CTL ===================================================== */ +#define CLK_CSV_HF_CTL_CSV_FREQ_WINDOW_Pos (0UL) /*!< CLK_CSV HF_CTL: CSV_FREQ_WINDOW (Bit 0) */ +#define CLK_CSV_HF_CTL_CSV_FREQ_WINDOW_Msk (0xffffUL) /*!< CLK_CSV HF_CTL: CSV_FREQ_WINDOW (Bitfield-Mask: 0xffff) */ +#define CLK_CSV_HF_CTL_CSV_MUX_Pos (16UL) /*!< CLK_CSV HF_CTL: CSV_MUX (Bit 16) */ +#define CLK_CSV_HF_CTL_CSV_MUX_Msk (0x30000UL) /*!< CLK_CSV HF_CTL: CSV_MUX (Bitfield-Mask: 0x03) */ +#define CLK_CSV_HF_CTL_CSV_LOSS_WINDOW_Pos (20UL) /*!< CLK_CSV HF_CTL: CSV_LOSS_WINDOW (Bit 20) */ +#define CLK_CSV_HF_CTL_CSV_LOSS_WINDOW_Msk (0x700000UL) /*!< CLK_CSV HF_CTL: CSV_LOSS_WINDOW (Bitfield-Mask: 0x07) */ +#define CLK_CSV_HF_CTL_CSV_FREQ_ACTION_Pos (24UL) /*!< CLK_CSV HF_CTL: CSV_FREQ_ACTION (Bit 24) */ +#define CLK_CSV_HF_CTL_CSV_FREQ_ACTION_Msk (0x3000000UL) /*!< CLK_CSV HF_CTL: CSV_FREQ_ACTION (Bitfield-Mask: 0x03) */ +#define CLK_CSV_HF_CTL_CSV_FREQ_ONESHOT_Pos (26UL) /*!< CLK_CSV HF_CTL: CSV_FREQ_ONESHOT (Bit 26) */ +#define CLK_CSV_HF_CTL_CSV_FREQ_ONESHOT_Msk (0x4000000UL) /*!< CLK_CSV HF_CTL: CSV_FREQ_ONESHOT (Bitfield-Mask: 0x01) */ +#define CLK_CSV_HF_CTL_CSV_FREQ_EN_Pos (27UL) /*!< CLK_CSV HF_CTL: CSV_FREQ_EN (Bit 27) */ +#define CLK_CSV_HF_CTL_CSV_FREQ_EN_Msk (0x8000000UL) /*!< CLK_CSV HF_CTL: CSV_FREQ_EN (Bitfield-Mask: 0x01) */ +#define CLK_CSV_HF_CTL_CSV_LOSS_ACTION_Pos (28UL) /*!< CLK_CSV HF_CTL: CSV_LOSS_ACTION (Bit 28) */ +#define CLK_CSV_HF_CTL_CSV_LOSS_ACTION_Msk (0x30000000UL) /*!< CLK_CSV HF_CTL: CSV_LOSS_ACTION (Bitfield-Mask: 0x03) */ +#define CLK_CSV_HF_CTL_CSV_LOSS_EN_Pos (31UL) /*!< CLK_CSV HF_CTL: CSV_LOSS_EN (Bit 31) */ +#define CLK_CSV_HF_CTL_CSV_LOSS_EN_Msk (0x80000000UL) /*!< CLK_CSV HF_CTL: CSV_LOSS_EN (Bitfield-Mask: 0x01) */ +/* =================================================== CLK_CSV.HF_LIMIT ==================================================== */ +#define CLK_CSV_HF_LIMIT_LOWER_LIMIT_Pos (0UL) /*!< CLK_CSV HF_LIMIT: LOWER_LIMIT (Bit 0) */ +#define CLK_CSV_HF_LIMIT_LOWER_LIMIT_Msk (0xffffUL) /*!< CLK_CSV HF_LIMIT: LOWER_LIMIT (Bitfield-Mask: 0xffff) */ +#define CLK_CSV_HF_LIMIT_UPPER_LIMIT_Pos (16UL) /*!< CLK_CSV HF_LIMIT: UPPER_LIMIT (Bit 16) */ +#define CLK_CSV_HF_LIMIT_UPPER_LIMIT_Msk (0xffff0000UL) /*!< CLK_CSV HF_LIMIT: UPPER_LIMIT (Bitfield-Mask: 0xffff) */ +/* ==================================================== CLK_CSV.HF_CNT ===================================================== */ +#define CLK_CSV_HF_CNT_CNT_Pos (0UL) /*!< CLK_CSV HF_CNT: CNT (Bit 0) */ +#define CLK_CSV_HF_CNT_CNT_Msk (0xffffUL) /*!< CLK_CSV HF_CNT: CNT (Bitfield-Mask: 0xffff) */ + + +/* ===================================================== SRSS.PWR_CTL ====================================================== */ +#define SRSS_PWR_CTL_POWER_MODE_Pos (0UL) /*!< SRSS PWR_CTL: POWER_MODE (Bit 0) */ +#define SRSS_PWR_CTL_POWER_MODE_Msk (0x3UL) /*!< SRSS PWR_CTL: POWER_MODE (Bitfield-Mask: 0x03) */ +#define SRSS_PWR_CTL_DEBUG_SESSION_Pos (4UL) /*!< SRSS PWR_CTL: DEBUG_SESSION (Bit 4) */ +#define SRSS_PWR_CTL_DEBUG_SESSION_Msk (0x10UL) /*!< SRSS PWR_CTL: DEBUG_SESSION (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_LPM_READY_Pos (5UL) /*!< SRSS PWR_CTL: LPM_READY (Bit 5) */ +#define SRSS_PWR_CTL_LPM_READY_Msk (0x20UL) /*!< SRSS PWR_CTL: LPM_READY (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_DPSLP_REG_DIS_Pos (20UL) /*!< SRSS PWR_CTL: DPSLP_REG_DIS (Bit 20) */ +#define SRSS_PWR_CTL_DPSLP_REG_DIS_Msk (0x100000UL) /*!< SRSS PWR_CTL: DPSLP_REG_DIS (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_RET_REG_DIS_Pos (21UL) /*!< SRSS PWR_CTL: RET_REG_DIS (Bit 21) */ +#define SRSS_PWR_CTL_RET_REG_DIS_Msk (0x200000UL) /*!< SRSS PWR_CTL: RET_REG_DIS (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_NWELL_REG_DIS_Pos (22UL) /*!< SRSS PWR_CTL: NWELL_REG_DIS (Bit 22) */ +#define SRSS_PWR_CTL_NWELL_REG_DIS_Msk (0x400000UL) /*!< SRSS PWR_CTL: NWELL_REG_DIS (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_LINREG_DIS_Pos (23UL) /*!< SRSS PWR_CTL: LINREG_DIS (Bit 23) */ +#define SRSS_PWR_CTL_LINREG_DIS_Msk (0x800000UL) /*!< SRSS PWR_CTL: LINREG_DIS (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_LINREG_LPMODE_Pos (24UL) /*!< SRSS PWR_CTL: LINREG_LPMODE (Bit 24) */ +#define SRSS_PWR_CTL_LINREG_LPMODE_Msk (0x1000000UL) /*!< SRSS PWR_CTL: LINREG_LPMODE (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_PORBOD_LPMODE_Pos (25UL) /*!< SRSS PWR_CTL: PORBOD_LPMODE (Bit 25) */ +#define SRSS_PWR_CTL_PORBOD_LPMODE_Msk (0x2000000UL) /*!< SRSS PWR_CTL: PORBOD_LPMODE (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_BGREF_LPMODE_Pos (26UL) /*!< SRSS PWR_CTL: BGREF_LPMODE (Bit 26) */ +#define SRSS_PWR_CTL_BGREF_LPMODE_Msk (0x4000000UL) /*!< SRSS PWR_CTL: BGREF_LPMODE (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_PLL_LS_BYPASS_Pos (27UL) /*!< SRSS PWR_CTL: PLL_LS_BYPASS (Bit 27) */ +#define SRSS_PWR_CTL_PLL_LS_BYPASS_Msk (0x8000000UL) /*!< SRSS PWR_CTL: PLL_LS_BYPASS (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_VREFBUF_LPMODE_Pos (28UL) /*!< SRSS PWR_CTL: VREFBUF_LPMODE (Bit 28) */ +#define SRSS_PWR_CTL_VREFBUF_LPMODE_Msk (0x10000000UL) /*!< SRSS PWR_CTL: VREFBUF_LPMODE (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_VREFBUF_DIS_Pos (29UL) /*!< SRSS PWR_CTL: VREFBUF_DIS (Bit 29) */ +#define SRSS_PWR_CTL_VREFBUF_DIS_Msk (0x20000000UL) /*!< SRSS PWR_CTL: VREFBUF_DIS (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_ACT_REF_DIS_Pos (30UL) /*!< SRSS PWR_CTL: ACT_REF_DIS (Bit 30) */ +#define SRSS_PWR_CTL_ACT_REF_DIS_Msk (0x40000000UL) /*!< SRSS PWR_CTL: ACT_REF_DIS (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_CTL_ACT_REF_OK_Pos (31UL) /*!< SRSS PWR_CTL: ACT_REF_OK (Bit 31) */ +#define SRSS_PWR_CTL_ACT_REF_OK_Msk (0x80000000UL) /*!< SRSS PWR_CTL: ACT_REF_OK (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.PWR_HIBERNATE =================================================== */ +#define SRSS_PWR_HIBERNATE_TOKEN_Pos (0UL) /*!< SRSS PWR_HIBERNATE: TOKEN (Bit 0) */ +#define SRSS_PWR_HIBERNATE_TOKEN_Msk (0xffUL) /*!< SRSS PWR_HIBERNATE: TOKEN (Bitfield-Mask: 0xff) */ +#define SRSS_PWR_HIBERNATE_UNLOCK_Pos (8UL) /*!< SRSS PWR_HIBERNATE: UNLOCK (Bit 8) */ +#define SRSS_PWR_HIBERNATE_UNLOCK_Msk (0xff00UL) /*!< SRSS PWR_HIBERNATE: UNLOCK (Bitfield-Mask: 0xff) */ +#define SRSS_PWR_HIBERNATE_FREEZE_Pos (17UL) /*!< SRSS PWR_HIBERNATE: FREEZE (Bit 17) */ +#define SRSS_PWR_HIBERNATE_FREEZE_Msk (0x20000UL) /*!< SRSS PWR_HIBERNATE: FREEZE (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos (18UL) /*!< SRSS PWR_HIBERNATE: MASK_HIBALARM (Bit 18) */ +#define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk (0x40000UL) /*!< SRSS PWR_HIBERNATE: MASK_HIBALARM (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Pos (19UL) /*!< SRSS PWR_HIBERNATE: MASK_HIBWDT (Bit 19) */ +#define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk (0x80000UL) /*!< SRSS PWR_HIBERNATE: MASK_HIBWDT (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos (20UL) /*!< SRSS PWR_HIBERNATE: POLARITY_HIBPIN (Bit 20) */ +#define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk (0xf00000UL) /*!< SRSS PWR_HIBERNATE: POLARITY_HIBPIN (Bitfield-Mask: 0x0f) */ +#define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos (24UL) /*!< SRSS PWR_HIBERNATE: MASK_HIBPIN (Bit 24) */ +#define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk (0xf000000UL) /*!< SRSS PWR_HIBERNATE: MASK_HIBPIN (Bitfield-Mask: 0x0f) */ +#define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Pos (30UL) /*!< SRSS PWR_HIBERNATE: HIBERNATE_DISABLE (Bit 30) */ +#define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Msk (0x40000000UL) /*!< SRSS PWR_HIBERNATE: HIBERNATE_DISABLE (Bitfield-Mask: 0x01)*/ +#define SRSS_PWR_HIBERNATE_HIBERNATE_Pos (31UL) /*!< SRSS PWR_HIBERNATE: HIBERNATE (Bit 31) */ +#define SRSS_PWR_HIBERNATE_HIBERNATE_Msk (0x80000000UL) /*!< SRSS PWR_HIBERNATE: HIBERNATE (Bitfield-Mask: 0x01) */ +/* =================================================== SRSS.PWR_LVD_CTL ==================================================== */ +#define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Pos (0UL) /*!< SRSS PWR_LVD_CTL: HVLVD1_TRIPSEL (Bit 0) */ +#define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Msk (0xfUL) /*!< SRSS PWR_LVD_CTL: HVLVD1_TRIPSEL (Bitfield-Mask: 0x0f) */ +#define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Pos (4UL) /*!< SRSS PWR_LVD_CTL: HVLVD1_SRCSEL (Bit 4) */ +#define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Msk (0x70UL) /*!< SRSS PWR_LVD_CTL: HVLVD1_SRCSEL (Bitfield-Mask: 0x07) */ +#define SRSS_PWR_LVD_CTL_HVLVD1_EN_Pos (7UL) /*!< SRSS PWR_LVD_CTL: HVLVD1_EN (Bit 7) */ +#define SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk (0x80UL) /*!< SRSS PWR_LVD_CTL: HVLVD1_EN (Bitfield-Mask: 0x01) */ +/* =================================================== SRSS.PWR_BUCK_CTL =================================================== */ +#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Pos (0UL) /*!< SRSS PWR_BUCK_CTL: BUCK_OUT1_SEL (Bit 0) */ +#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Msk (0x7UL) /*!< SRSS PWR_BUCK_CTL: BUCK_OUT1_SEL (Bitfield-Mask: 0x07) */ +#define SRSS_PWR_BUCK_CTL_BUCK_EN_Pos (30UL) /*!< SRSS PWR_BUCK_CTL: BUCK_EN (Bit 30) */ +#define SRSS_PWR_BUCK_CTL_BUCK_EN_Msk (0x40000000UL) /*!< SRSS PWR_BUCK_CTL: BUCK_EN (Bitfield-Mask: 0x01) */ +#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Pos (31UL) /*!< SRSS PWR_BUCK_CTL: BUCK_OUT1_EN (Bit 31) */ +#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Msk (0x80000000UL) /*!< SRSS PWR_BUCK_CTL: BUCK_OUT1_EN (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.PWR_BUCK_CTL2 =================================================== */ +#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Pos (0UL) /*!< SRSS PWR_BUCK_CTL2: BUCK_OUT2_SEL (Bit 0) */ +#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Msk (0x7UL) /*!< SRSS PWR_BUCK_CTL2: BUCK_OUT2_SEL (Bitfield-Mask: 0x07) */ +#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Pos (30UL) /*!< SRSS PWR_BUCK_CTL2: BUCK_OUT2_HW_SEL (Bit 30) */ +#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Msk (0x40000000UL) /*!< SRSS PWR_BUCK_CTL2: BUCK_OUT2_HW_SEL (Bitfield-Mask: 0x01)*/ +#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Pos (31UL) /*!< SRSS PWR_BUCK_CTL2: BUCK_OUT2_EN (Bit 31) */ +#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Msk (0x80000000UL) /*!< SRSS PWR_BUCK_CTL2: BUCK_OUT2_EN (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.PWR_LVD_STATUS ================================================== */ +#define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Pos (0UL) /*!< SRSS PWR_LVD_STATUS: HVLVD1_OK (Bit 0) */ +#define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Msk (0x1UL) /*!< SRSS PWR_LVD_STATUS: HVLVD1_OK (Bitfield-Mask: 0x01) */ +/* =================================================== SRSS.PWR_HIB_DATA =================================================== */ +#define SRSS_PWR_HIB_DATA_HIB_DATA_Pos (0UL) /*!< SRSS PWR_HIB_DATA: HIB_DATA (Bit 0) */ +#define SRSS_PWR_HIB_DATA_HIB_DATA_Msk (0xffffffffUL) /*!< SRSS PWR_HIB_DATA: HIB_DATA (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== SRSS.WDT_CTL ====================================================== */ +#define SRSS_WDT_CTL_WDT_EN_Pos (0UL) /*!< SRSS WDT_CTL: WDT_EN (Bit 0) */ +#define SRSS_WDT_CTL_WDT_EN_Msk (0x1UL) /*!< SRSS WDT_CTL: WDT_EN (Bitfield-Mask: 0x01) */ +#define SRSS_WDT_CTL_WDT_LOCK_Pos (30UL) /*!< SRSS WDT_CTL: WDT_LOCK (Bit 30) */ +#define SRSS_WDT_CTL_WDT_LOCK_Msk (0xc0000000UL) /*!< SRSS WDT_CTL: WDT_LOCK (Bitfield-Mask: 0x03) */ +/* ===================================================== SRSS.WDT_CNT ====================================================== */ +#define SRSS_WDT_CNT_COUNTER_Pos (0UL) /*!< SRSS WDT_CNT: COUNTER (Bit 0) */ +#define SRSS_WDT_CNT_COUNTER_Msk (0xffffUL) /*!< SRSS WDT_CNT: COUNTER (Bitfield-Mask: 0xffff) */ +/* ==================================================== SRSS.WDT_MATCH ===================================================== */ +#define SRSS_WDT_MATCH_MATCH_Pos (0UL) /*!< SRSS WDT_MATCH: MATCH (Bit 0) */ +#define SRSS_WDT_MATCH_MATCH_Msk (0xffffUL) /*!< SRSS WDT_MATCH: MATCH (Bitfield-Mask: 0xffff) */ +#define SRSS_WDT_MATCH_IGNORE_BITS_Pos (16UL) /*!< SRSS WDT_MATCH: IGNORE_BITS (Bit 16) */ +#define SRSS_WDT_MATCH_IGNORE_BITS_Msk (0xf0000UL) /*!< SRSS WDT_MATCH: IGNORE_BITS (Bitfield-Mask: 0x0f) */ +/* ================================================== SRSS.CLK_DSI_SELECT ================================================== */ +#define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos (0UL) /*!< SRSS CLK_DSI_SELECT: DSI_MUX (Bit 0) */ +#define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk (0x1fUL) /*!< SRSS CLK_DSI_SELECT: DSI_MUX (Bitfield-Mask: 0x1f) */ +/* ================================================= SRSS.CLK_PATH_SELECT ================================================== */ +#define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos (0UL) /*!< SRSS CLK_PATH_SELECT: PATH_MUX (Bit 0) */ +#define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk (0x7UL) /*!< SRSS CLK_PATH_SELECT: PATH_MUX (Bitfield-Mask: 0x07) */ +/* ================================================= SRSS.CLK_ROOT_SELECT ================================================== */ +#define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos (0UL) /*!< SRSS CLK_ROOT_SELECT: ROOT_MUX (Bit 0) */ +#define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk (0xfUL) /*!< SRSS CLK_ROOT_SELECT: ROOT_MUX (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos (4UL) /*!< SRSS CLK_ROOT_SELECT: ROOT_DIV (Bit 4) */ +#define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk (0x30UL) /*!< SRSS CLK_ROOT_SELECT: ROOT_DIV (Bitfield-Mask: 0x03) */ +#define SRSS_CLK_ROOT_SELECT_ENABLE_Pos (31UL) /*!< SRSS CLK_ROOT_SELECT: ENABLE (Bit 31) */ +#define SRSS_CLK_ROOT_SELECT_ENABLE_Msk (0x80000000UL) /*!< SRSS CLK_ROOT_SELECT: ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== SRSS.CLK_SELECT ==================================================== */ +#define SRSS_CLK_SELECT_LFCLK_SEL_Pos (0UL) /*!< SRSS CLK_SELECT: LFCLK_SEL (Bit 0) */ +#define SRSS_CLK_SELECT_LFCLK_SEL_Msk (0x3UL) /*!< SRSS CLK_SELECT: LFCLK_SEL (Bitfield-Mask: 0x03) */ +#define SRSS_CLK_SELECT_PUMP_SEL_Pos (8UL) /*!< SRSS CLK_SELECT: PUMP_SEL (Bit 8) */ +#define SRSS_CLK_SELECT_PUMP_SEL_Msk (0xf00UL) /*!< SRSS CLK_SELECT: PUMP_SEL (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_SELECT_PUMP_DIV_Pos (12UL) /*!< SRSS CLK_SELECT: PUMP_DIV (Bit 12) */ +#define SRSS_CLK_SELECT_PUMP_DIV_Msk (0x7000UL) /*!< SRSS CLK_SELECT: PUMP_DIV (Bitfield-Mask: 0x07) */ +#define SRSS_CLK_SELECT_PUMP_ENABLE_Pos (15UL) /*!< SRSS CLK_SELECT: PUMP_ENABLE (Bit 15) */ +#define SRSS_CLK_SELECT_PUMP_ENABLE_Msk (0x8000UL) /*!< SRSS CLK_SELECT: PUMP_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.CLK_TIMER_CTL =================================================== */ +#define SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos (0UL) /*!< SRSS CLK_TIMER_CTL: TIMER_SEL (Bit 0) */ +#define SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk (0x1UL) /*!< SRSS CLK_TIMER_CTL: TIMER_SEL (Bitfield-Mask: 0x01) */ +#define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos (8UL) /*!< SRSS CLK_TIMER_CTL: TIMER_HF0_DIV (Bit 8) */ +#define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk (0x300UL) /*!< SRSS CLK_TIMER_CTL: TIMER_HF0_DIV (Bitfield-Mask: 0x03) */ +#define SRSS_CLK_TIMER_CTL_TIMER_DIV_Pos (16UL) /*!< SRSS CLK_TIMER_CTL: TIMER_DIV (Bit 16) */ +#define SRSS_CLK_TIMER_CTL_TIMER_DIV_Msk (0xff0000UL) /*!< SRSS CLK_TIMER_CTL: TIMER_DIV (Bitfield-Mask: 0xff) */ +#define SRSS_CLK_TIMER_CTL_ENABLE_Pos (31UL) /*!< SRSS CLK_TIMER_CTL: ENABLE (Bit 31) */ +#define SRSS_CLK_TIMER_CTL_ENABLE_Msk (0x80000000UL) /*!< SRSS CLK_TIMER_CTL: ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================= SRSS.CLK_CSV_WCO_CTL ================================================== */ +#define SRSS_CLK_CSV_WCO_CTL_CSV_MUX_Pos (16UL) /*!< SRSS CLK_CSV_WCO_CTL: CSV_MUX (Bit 16) */ +#define SRSS_CLK_CSV_WCO_CTL_CSV_MUX_Msk (0x30000UL) /*!< SRSS CLK_CSV_WCO_CTL: CSV_MUX (Bitfield-Mask: 0x03) */ +#define SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_WINDOW_Pos (20UL) /*!< SRSS CLK_CSV_WCO_CTL: CSV_LOSS_WINDOW (Bit 20) */ +#define SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_WINDOW_Msk (0x700000UL) /*!< SRSS CLK_CSV_WCO_CTL: CSV_LOSS_WINDOW (Bitfield-Mask: 0x07)*/ +#define SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_ACTION_Pos (28UL) /*!< SRSS CLK_CSV_WCO_CTL: CSV_LOSS_ACTION (Bit 28) */ +#define SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_ACTION_Msk (0x30000000UL) /*!< SRSS CLK_CSV_WCO_CTL: CSV_LOSS_ACTION (Bitfield-Mask: 0x03)*/ +#define SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_EN_Pos (31UL) /*!< SRSS CLK_CSV_WCO_CTL: CSV_LOSS_EN (Bit 31) */ +#define SRSS_CLK_CSV_WCO_CTL_CSV_LOSS_EN_Msk (0x80000000UL) /*!< SRSS CLK_CSV_WCO_CTL: CSV_LOSS_EN (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.CLK_ILO_CONFIG ================================================== */ +#define SRSS_CLK_ILO_CONFIG_HVILO_BACKUP_Pos (0UL) /*!< SRSS CLK_ILO_CONFIG: HVILO_BACKUP (Bit 0) */ +#define SRSS_CLK_ILO_CONFIG_HVILO_BACKUP_Msk (0x1UL) /*!< SRSS CLK_ILO_CONFIG: HVILO_BACKUP (Bitfield-Mask: 0x01) */ +#define SRSS_CLK_ILO_CONFIG_ENABLE_Pos (31UL) /*!< SRSS CLK_ILO_CONFIG: ENABLE (Bit 31) */ +#define SRSS_CLK_ILO_CONFIG_ENABLE_Msk (0x80000000UL) /*!< SRSS CLK_ILO_CONFIG: ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.CLK_IMO_CONFIG ================================================== */ +#define SRSS_CLK_IMO_CONFIG_ENABLE_Pos (31UL) /*!< SRSS CLK_IMO_CONFIG: ENABLE (Bit 31) */ +#define SRSS_CLK_IMO_CONFIG_ENABLE_Msk (0x80000000UL) /*!< SRSS CLK_IMO_CONFIG: ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================= SRSS.CLK_OUTPUT_FAST ================================================== */ +#define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos (0UL) /*!< SRSS CLK_OUTPUT_FAST: FAST_SEL0 (Bit 0) */ +#define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk (0xfUL) /*!< SRSS CLK_OUTPUT_FAST: FAST_SEL0 (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos (4UL) /*!< SRSS CLK_OUTPUT_FAST: PATH_SEL0 (Bit 4) */ +#define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk (0xf0UL) /*!< SRSS CLK_OUTPUT_FAST: PATH_SEL0 (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos (8UL) /*!< SRSS CLK_OUTPUT_FAST: HFCLK_SEL0 (Bit 8) */ +#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk (0xf00UL) /*!< SRSS CLK_OUTPUT_FAST: HFCLK_SEL0 (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos (16UL) /*!< SRSS CLK_OUTPUT_FAST: FAST_SEL1 (Bit 16) */ +#define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk (0xf0000UL) /*!< SRSS CLK_OUTPUT_FAST: FAST_SEL1 (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos (20UL) /*!< SRSS CLK_OUTPUT_FAST: PATH_SEL1 (Bit 20) */ +#define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk (0xf00000UL) /*!< SRSS CLK_OUTPUT_FAST: PATH_SEL1 (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos (24UL) /*!< SRSS CLK_OUTPUT_FAST: HFCLK_SEL1 (Bit 24) */ +#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk (0xf000000UL) /*!< SRSS CLK_OUTPUT_FAST: HFCLK_SEL1 (Bitfield-Mask: 0x0f) */ +/* ================================================= SRSS.CLK_OUTPUT_SLOW ================================================== */ +#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos (0UL) /*!< SRSS CLK_OUTPUT_SLOW: SLOW_SEL0 (Bit 0) */ +#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk (0xfUL) /*!< SRSS CLK_OUTPUT_SLOW: SLOW_SEL0 (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos (4UL) /*!< SRSS CLK_OUTPUT_SLOW: SLOW_SEL1 (Bit 4) */ +#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk (0xf0UL) /*!< SRSS CLK_OUTPUT_SLOW: SLOW_SEL1 (Bitfield-Mask: 0x0f) */ +/* =================================================== SRSS.CLK_CAL_CNT1 =================================================== */ +#define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos (0UL) /*!< SRSS CLK_CAL_CNT1: CAL_COUNTER1 (Bit 0) */ +#define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk (0xffffffUL) /*!< SRSS CLK_CAL_CNT1: CAL_COUNTER1 (Bitfield-Mask: 0xffffff) */ +#define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos (31UL) /*!< SRSS CLK_CAL_CNT1: CAL_COUNTER_DONE (Bit 31) */ +#define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk (0x80000000UL) /*!< SRSS CLK_CAL_CNT1: CAL_COUNTER_DONE (Bitfield-Mask: 0x01) */ +/* =================================================== SRSS.CLK_CAL_CNT2 =================================================== */ +#define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos (0UL) /*!< SRSS CLK_CAL_CNT2: CAL_COUNTER2 (Bit 0) */ +#define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk (0xffffffUL) /*!< SRSS CLK_CAL_CNT2: CAL_COUNTER2 (Bitfield-Mask: 0xffffff) */ +/* ================================================== SRSS.CLK_ECO_CONFIG ================================================== */ +#define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos (1UL) /*!< SRSS CLK_ECO_CONFIG: AGC_EN (Bit 1) */ +#define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk (0x2UL) /*!< SRSS CLK_ECO_CONFIG: AGC_EN (Bitfield-Mask: 0x01) */ +#define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos (31UL) /*!< SRSS CLK_ECO_CONFIG: ECO_EN (Bit 31) */ +#define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk (0x80000000UL) /*!< SRSS CLK_ECO_CONFIG: ECO_EN (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.CLK_ECO_STATUS ================================================== */ +#define SRSS_CLK_ECO_STATUS_ECO_OK_Pos (0UL) /*!< SRSS CLK_ECO_STATUS: ECO_OK (Bit 0) */ +#define SRSS_CLK_ECO_STATUS_ECO_OK_Msk (0x1UL) /*!< SRSS CLK_ECO_STATUS: ECO_OK (Bitfield-Mask: 0x01) */ +#define SRSS_CLK_ECO_STATUS_ECO_READY_Pos (1UL) /*!< SRSS CLK_ECO_STATUS: ECO_READY (Bit 1) */ +#define SRSS_CLK_ECO_STATUS_ECO_READY_Msk (0x2UL) /*!< SRSS CLK_ECO_STATUS: ECO_READY (Bitfield-Mask: 0x01) */ +/* =================================================== SRSS.CLK_WCO_DPLL =================================================== */ +#define SRSS_CLK_WCO_DPLL_DPLL_MULT_Pos (0UL) /*!< SRSS CLK_WCO_DPLL: DPLL_MULT (Bit 0) */ +#define SRSS_CLK_WCO_DPLL_DPLL_MULT_Msk (0x7ffUL) /*!< SRSS CLK_WCO_DPLL: DPLL_MULT (Bitfield-Mask: 0x7ff) */ +#define SRSS_CLK_WCO_DPLL_DPLL_LF_IGAIN_Pos (16UL) /*!< SRSS CLK_WCO_DPLL: DPLL_LF_IGAIN (Bit 16) */ +#define SRSS_CLK_WCO_DPLL_DPLL_LF_IGAIN_Msk (0x70000UL) /*!< SRSS CLK_WCO_DPLL: DPLL_LF_IGAIN (Bitfield-Mask: 0x07) */ +#define SRSS_CLK_WCO_DPLL_DPLL_LF_PGAIN_Pos (19UL) /*!< SRSS CLK_WCO_DPLL: DPLL_LF_PGAIN (Bit 19) */ +#define SRSS_CLK_WCO_DPLL_DPLL_LF_PGAIN_Msk (0x380000UL) /*!< SRSS CLK_WCO_DPLL: DPLL_LF_PGAIN (Bitfield-Mask: 0x07) */ +#define SRSS_CLK_WCO_DPLL_DPLL_LF_LIMIT_Pos (22UL) /*!< SRSS CLK_WCO_DPLL: DPLL_LF_LIMIT (Bit 22) */ +#define SRSS_CLK_WCO_DPLL_DPLL_LF_LIMIT_Msk (0x3fc00000UL) /*!< SRSS CLK_WCO_DPLL: DPLL_LF_LIMIT (Bitfield-Mask: 0xff) */ +#define SRSS_CLK_WCO_DPLL_DPLL_EN_Pos (31UL) /*!< SRSS CLK_WCO_DPLL: DPLL_EN (Bit 31) */ +#define SRSS_CLK_WCO_DPLL_DPLL_EN_Msk (0x80000000UL) /*!< SRSS CLK_WCO_DPLL: DPLL_EN (Bitfield-Mask: 0x01) */ +/* ================================================= SRSS.CLK_PILO_CONFIG ================================================== */ +#define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Pos (0UL) /*!< SRSS CLK_PILO_CONFIG: PILO_FFREQ (Bit 0) */ +#define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk (0x3ffUL) /*!< SRSS CLK_PILO_CONFIG: PILO_FFREQ (Bitfield-Mask: 0x3ff) */ +#define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Pos (29UL) /*!< SRSS CLK_PILO_CONFIG: PILO_CLK_EN (Bit 29) */ +#define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk (0x20000000UL) /*!< SRSS CLK_PILO_CONFIG: PILO_CLK_EN (Bitfield-Mask: 0x01) */ +#define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Pos (30UL) /*!< SRSS CLK_PILO_CONFIG: PILO_RESET_N (Bit 30) */ +#define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk (0x40000000UL) /*!< SRSS CLK_PILO_CONFIG: PILO_RESET_N (Bitfield-Mask: 0x01) */ +#define SRSS_CLK_PILO_CONFIG_PILO_EN_Pos (31UL) /*!< SRSS CLK_PILO_CONFIG: PILO_EN (Bit 31) */ +#define SRSS_CLK_PILO_CONFIG_PILO_EN_Msk (0x80000000UL) /*!< SRSS CLK_PILO_CONFIG: PILO_EN (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.CLK_FLL_CONFIG ================================================== */ +#define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos (0UL) /*!< SRSS CLK_FLL_CONFIG: FLL_MULT (Bit 0) */ +#define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk (0x3ffffUL) /*!< SRSS CLK_FLL_CONFIG: FLL_MULT (Bitfield-Mask: 0x3ffff) */ +#define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos (24UL) /*!< SRSS CLK_FLL_CONFIG: FLL_OUTPUT_DIV (Bit 24) */ +#define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk (0x1000000UL) /*!< SRSS CLK_FLL_CONFIG: FLL_OUTPUT_DIV (Bitfield-Mask: 0x01) */ +#define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos (31UL) /*!< SRSS CLK_FLL_CONFIG: FLL_ENABLE (Bit 31) */ +#define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk (0x80000000UL) /*!< SRSS CLK_FLL_CONFIG: FLL_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================= SRSS.CLK_FLL_CONFIG2 ================================================== */ +#define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos (0UL) /*!< SRSS CLK_FLL_CONFIG2: FLL_REF_DIV (Bit 0) */ +#define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk (0x1fffUL) /*!< SRSS CLK_FLL_CONFIG2: FLL_REF_DIV (Bitfield-Mask: 0x1fff) */ +#define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos (16UL) /*!< SRSS CLK_FLL_CONFIG2: LOCK_TOL (Bit 16) */ +#define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk (0x1ff0000UL) /*!< SRSS CLK_FLL_CONFIG2: LOCK_TOL (Bitfield-Mask: 0x1ff) */ +/* ================================================= SRSS.CLK_FLL_CONFIG3 ================================================== */ +#define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos (0UL) /*!< SRSS CLK_FLL_CONFIG3: FLL_LF_IGAIN (Bit 0) */ +#define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk (0xfUL) /*!< SRSS CLK_FLL_CONFIG3: FLL_LF_IGAIN (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos (4UL) /*!< SRSS CLK_FLL_CONFIG3: FLL_LF_PGAIN (Bit 4) */ +#define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk (0xf0UL) /*!< SRSS CLK_FLL_CONFIG3: FLL_LF_PGAIN (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos (8UL) /*!< SRSS CLK_FLL_CONFIG3: SETTLING_COUNT (Bit 8) */ +#define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk (0x1fff00UL) /*!< SRSS CLK_FLL_CONFIG3: SETTLING_COUNT (Bitfield-Mask: 0x1fff)*/ +#define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos (28UL) /*!< SRSS CLK_FLL_CONFIG3: BYPASS_SEL (Bit 28) */ +#define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk (0x30000000UL) /*!< SRSS CLK_FLL_CONFIG3: BYPASS_SEL (Bitfield-Mask: 0x03) */ +/* ================================================= SRSS.CLK_FLL_CONFIG4 ================================================== */ +#define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Pos (0UL) /*!< SRSS CLK_FLL_CONFIG4: CCO_LIMIT (Bit 0) */ +#define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Msk (0xffUL) /*!< SRSS CLK_FLL_CONFIG4: CCO_LIMIT (Bitfield-Mask: 0xff) */ +#define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos (8UL) /*!< SRSS CLK_FLL_CONFIG4: CCO_RANGE (Bit 8) */ +#define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk (0x700UL) /*!< SRSS CLK_FLL_CONFIG4: CCO_RANGE (Bitfield-Mask: 0x07) */ +#define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos (16UL) /*!< SRSS CLK_FLL_CONFIG4: CCO_FREQ (Bit 16) */ +#define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk (0x1ff0000UL) /*!< SRSS CLK_FLL_CONFIG4: CCO_FREQ (Bitfield-Mask: 0x1ff) */ +#define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos (31UL) /*!< SRSS CLK_FLL_CONFIG4: CCO_ENABLE (Bit 31) */ +#define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk (0x80000000UL) /*!< SRSS CLK_FLL_CONFIG4: CCO_ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.CLK_FLL_STATUS ================================================== */ +#define SRSS_CLK_FLL_STATUS_LOCKED_Pos (0UL) /*!< SRSS CLK_FLL_STATUS: LOCKED (Bit 0) */ +#define SRSS_CLK_FLL_STATUS_LOCKED_Msk (0x1UL) /*!< SRSS CLK_FLL_STATUS: LOCKED (Bitfield-Mask: 0x01) */ +#define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Pos (1UL) /*!< SRSS CLK_FLL_STATUS: UNLOCK_OCCURRED (Bit 1) */ +#define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Msk (0x2UL) /*!< SRSS CLK_FLL_STATUS: UNLOCK_OCCURRED (Bitfield-Mask: 0x01)*/ +#define SRSS_CLK_FLL_STATUS_CCO_READY_Pos (2UL) /*!< SRSS CLK_FLL_STATUS: CCO_READY (Bit 2) */ +#define SRSS_CLK_FLL_STATUS_CCO_READY_Msk (0x4UL) /*!< SRSS CLK_FLL_STATUS: CCO_READY (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.CLK_PLL_CONFIG ================================================== */ +#define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos (0UL) /*!< SRSS CLK_PLL_CONFIG: FEEDBACK_DIV (Bit 0) */ +#define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk (0x7fUL) /*!< SRSS CLK_PLL_CONFIG: FEEDBACK_DIV (Bitfield-Mask: 0x7f) */ +#define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos (8UL) /*!< SRSS CLK_PLL_CONFIG: REFERENCE_DIV (Bit 8) */ +#define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk (0x1f00UL) /*!< SRSS CLK_PLL_CONFIG: REFERENCE_DIV (Bitfield-Mask: 0x1f) */ +#define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos (16UL) /*!< SRSS CLK_PLL_CONFIG: OUTPUT_DIV (Bit 16) */ +#define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk (0x1f0000UL) /*!< SRSS CLK_PLL_CONFIG: OUTPUT_DIV (Bitfield-Mask: 0x1f) */ +#define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos (27UL) /*!< SRSS CLK_PLL_CONFIG: PLL_LF_MODE (Bit 27) */ +#define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk (0x8000000UL) /*!< SRSS CLK_PLL_CONFIG: PLL_LF_MODE (Bitfield-Mask: 0x01) */ +#define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos (28UL) /*!< SRSS CLK_PLL_CONFIG: BYPASS_SEL (Bit 28) */ +#define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk (0x30000000UL) /*!< SRSS CLK_PLL_CONFIG: BYPASS_SEL (Bitfield-Mask: 0x03) */ +#define SRSS_CLK_PLL_CONFIG_ENABLE_Pos (31UL) /*!< SRSS CLK_PLL_CONFIG: ENABLE (Bit 31) */ +#define SRSS_CLK_PLL_CONFIG_ENABLE_Msk (0x80000000UL) /*!< SRSS CLK_PLL_CONFIG: ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.CLK_PLL_STATUS ================================================== */ +#define SRSS_CLK_PLL_STATUS_LOCKED_Pos (0UL) /*!< SRSS CLK_PLL_STATUS: LOCKED (Bit 0) */ +#define SRSS_CLK_PLL_STATUS_LOCKED_Msk (0x1UL) /*!< SRSS CLK_PLL_STATUS: LOCKED (Bitfield-Mask: 0x01) */ +#define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos (1UL) /*!< SRSS CLK_PLL_STATUS: UNLOCK_OCCURRED (Bit 1) */ +#define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk (0x2UL) /*!< SRSS CLK_PLL_STATUS: UNLOCK_OCCURRED (Bitfield-Mask: 0x01)*/ +/* ==================================================== SRSS.SRSS_INTR ===================================================== */ +#define SRSS_SRSS_INTR_WDT_MATCH_Pos (0UL) /*!< SRSS SRSS_INTR: WDT_MATCH (Bit 0) */ +#define SRSS_SRSS_INTR_WDT_MATCH_Msk (0x1UL) /*!< SRSS SRSS_INTR: WDT_MATCH (Bitfield-Mask: 0x01) */ +#define SRSS_SRSS_INTR_HVLVD1_Pos (1UL) /*!< SRSS SRSS_INTR: HVLVD1 (Bit 1) */ +#define SRSS_SRSS_INTR_HVLVD1_Msk (0x2UL) /*!< SRSS SRSS_INTR: HVLVD1 (Bitfield-Mask: 0x01) */ +#define SRSS_SRSS_INTR_CLK_CAL_Pos (5UL) /*!< SRSS SRSS_INTR: CLK_CAL (Bit 5) */ +#define SRSS_SRSS_INTR_CLK_CAL_Msk (0x20UL) /*!< SRSS SRSS_INTR: CLK_CAL (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.SRSS_INTR_SET =================================================== */ +#define SRSS_SRSS_INTR_SET_WDT_MATCH_Pos (0UL) /*!< SRSS SRSS_INTR_SET: WDT_MATCH (Bit 0) */ +#define SRSS_SRSS_INTR_SET_WDT_MATCH_Msk (0x1UL) /*!< SRSS SRSS_INTR_SET: WDT_MATCH (Bitfield-Mask: 0x01) */ +#define SRSS_SRSS_INTR_SET_HVLVD1_Pos (1UL) /*!< SRSS SRSS_INTR_SET: HVLVD1 (Bit 1) */ +#define SRSS_SRSS_INTR_SET_HVLVD1_Msk (0x2UL) /*!< SRSS SRSS_INTR_SET: HVLVD1 (Bitfield-Mask: 0x01) */ +#define SRSS_SRSS_INTR_SET_CLK_CAL_Pos (5UL) /*!< SRSS SRSS_INTR_SET: CLK_CAL (Bit 5) */ +#define SRSS_SRSS_INTR_SET_CLK_CAL_Msk (0x20UL) /*!< SRSS SRSS_INTR_SET: CLK_CAL (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.SRSS_INTR_MASK ================================================== */ +#define SRSS_SRSS_INTR_MASK_WDT_MATCH_Pos (0UL) /*!< SRSS SRSS_INTR_MASK: WDT_MATCH (Bit 0) */ +#define SRSS_SRSS_INTR_MASK_WDT_MATCH_Msk (0x1UL) /*!< SRSS SRSS_INTR_MASK: WDT_MATCH (Bitfield-Mask: 0x01) */ +#define SRSS_SRSS_INTR_MASK_HVLVD1_Pos (1UL) /*!< SRSS SRSS_INTR_MASK: HVLVD1 (Bit 1) */ +#define SRSS_SRSS_INTR_MASK_HVLVD1_Msk (0x2UL) /*!< SRSS SRSS_INTR_MASK: HVLVD1 (Bitfield-Mask: 0x01) */ +#define SRSS_SRSS_INTR_MASK_CLK_CAL_Pos (5UL) /*!< SRSS SRSS_INTR_MASK: CLK_CAL (Bit 5) */ +#define SRSS_SRSS_INTR_MASK_CLK_CAL_Msk (0x20UL) /*!< SRSS SRSS_INTR_MASK: CLK_CAL (Bitfield-Mask: 0x01) */ +/* ================================================= SRSS.SRSS_INTR_MASKED ================================================= */ +#define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Pos (0UL) /*!< SRSS SRSS_INTR_MASKED: WDT_MATCH (Bit 0) */ +#define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Msk (0x1UL) /*!< SRSS SRSS_INTR_MASKED: WDT_MATCH (Bitfield-Mask: 0x01) */ +#define SRSS_SRSS_INTR_MASKED_HVLVD1_Pos (1UL) /*!< SRSS SRSS_INTR_MASKED: HVLVD1 (Bit 1) */ +#define SRSS_SRSS_INTR_MASKED_HVLVD1_Msk (0x2UL) /*!< SRSS SRSS_INTR_MASKED: HVLVD1 (Bitfield-Mask: 0x01) */ +#define SRSS_SRSS_INTR_MASKED_CLK_CAL_Pos (5UL) /*!< SRSS SRSS_INTR_MASKED: CLK_CAL (Bit 5) */ +#define SRSS_SRSS_INTR_MASKED_CLK_CAL_Msk (0x20UL) /*!< SRSS SRSS_INTR_MASKED: CLK_CAL (Bitfield-Mask: 0x01) */ +/* ================================================== SRSS.SRSS_INTR_CFG =================================================== */ +#define SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL_Pos (0UL) /*!< SRSS SRSS_INTR_CFG: HVLVD1_EDGE_SEL (Bit 0) */ +#define SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL_Msk (0x3UL) /*!< SRSS SRSS_INTR_CFG: HVLVD1_EDGE_SEL (Bitfield-Mask: 0x03) */ +/* ==================================================== SRSS.RES_CAUSE ===================================================== */ +#define SRSS_RES_CAUSE_RESET_WDT_Pos (0UL) /*!< SRSS RES_CAUSE: RESET_WDT (Bit 0) */ +#define SRSS_RES_CAUSE_RESET_WDT_Msk (0x1UL) /*!< SRSS RES_CAUSE: RESET_WDT (Bitfield-Mask: 0x01) */ +#define SRSS_RES_CAUSE_RESET_ACT_FAULT_Pos (1UL) /*!< SRSS RES_CAUSE: RESET_ACT_FAULT (Bit 1) */ +#define SRSS_RES_CAUSE_RESET_ACT_FAULT_Msk (0x2UL) /*!< SRSS RES_CAUSE: RESET_ACT_FAULT (Bitfield-Mask: 0x01) */ +#define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Pos (2UL) /*!< SRSS RES_CAUSE: RESET_DPSLP_FAULT (Bit 2) */ +#define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Msk (0x4UL) /*!< SRSS RES_CAUSE: RESET_DPSLP_FAULT (Bitfield-Mask: 0x01) */ +#define SRSS_RES_CAUSE_RESET_CSV_WCO_LOSS_Pos (3UL) /*!< SRSS RES_CAUSE: RESET_CSV_WCO_LOSS (Bit 3) */ +#define SRSS_RES_CAUSE_RESET_CSV_WCO_LOSS_Msk (0x8UL) /*!< SRSS RES_CAUSE: RESET_CSV_WCO_LOSS (Bitfield-Mask: 0x01) */ +#define SRSS_RES_CAUSE_RESET_SOFT_Pos (4UL) /*!< SRSS RES_CAUSE: RESET_SOFT (Bit 4) */ +#define SRSS_RES_CAUSE_RESET_SOFT_Msk (0x10UL) /*!< SRSS RES_CAUSE: RESET_SOFT (Bitfield-Mask: 0x01) */ +#define SRSS_RES_CAUSE_RESET_MCWDT0_Pos (5UL) /*!< SRSS RES_CAUSE: RESET_MCWDT0 (Bit 5) */ +#define SRSS_RES_CAUSE_RESET_MCWDT0_Msk (0x20UL) /*!< SRSS RES_CAUSE: RESET_MCWDT0 (Bitfield-Mask: 0x01) */ +#define SRSS_RES_CAUSE_RESET_MCWDT1_Pos (6UL) /*!< SRSS RES_CAUSE: RESET_MCWDT1 (Bit 6) */ +#define SRSS_RES_CAUSE_RESET_MCWDT1_Msk (0x40UL) /*!< SRSS RES_CAUSE: RESET_MCWDT1 (Bitfield-Mask: 0x01) */ +#define SRSS_RES_CAUSE_RESET_MCWDT2_Pos (7UL) /*!< SRSS RES_CAUSE: RESET_MCWDT2 (Bit 7) */ +#define SRSS_RES_CAUSE_RESET_MCWDT2_Msk (0x80UL) /*!< SRSS RES_CAUSE: RESET_MCWDT2 (Bitfield-Mask: 0x01) */ +#define SRSS_RES_CAUSE_RESET_MCWDT3_Pos (8UL) /*!< SRSS RES_CAUSE: RESET_MCWDT3 (Bit 8) */ +#define SRSS_RES_CAUSE_RESET_MCWDT3_Msk (0x100UL) /*!< SRSS RES_CAUSE: RESET_MCWDT3 (Bitfield-Mask: 0x01) */ +/* ==================================================== SRSS.RES_CAUSE2 ==================================================== */ +#define SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Pos (0UL) /*!< SRSS RES_CAUSE2: RESET_CSV_HF_LOSS (Bit 0) */ +#define SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Msk (0xffffUL) /*!< SRSS RES_CAUSE2: RESET_CSV_HF_LOSS (Bitfield-Mask: 0xffff)*/ +#define SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Pos (16UL) /*!< SRSS RES_CAUSE2: RESET_CSV_HF_FREQ (Bit 16) */ +#define SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Msk (0xffff0000UL) /*!< SRSS RES_CAUSE2: RESET_CSV_HF_FREQ (Bitfield-Mask: 0xffff)*/ +/* ================================================= SRSS.PWR_TRIM_REF_CTL ================================================= */ +#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_TCTRIM_Pos (0UL) /*!< SRSS PWR_TRIM_REF_CTL: ACT_REF_TCTRIM (Bit 0) */ +#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_TCTRIM_Msk (0xfUL) /*!< SRSS PWR_TRIM_REF_CTL: ACT_REF_TCTRIM (Bitfield-Mask: 0x0f)*/ +#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ITRIM_Pos (4UL) /*!< SRSS PWR_TRIM_REF_CTL: ACT_REF_ITRIM (Bit 4) */ +#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ITRIM_Msk (0xf0UL) /*!< SRSS PWR_TRIM_REF_CTL: ACT_REF_ITRIM (Bitfield-Mask: 0x0f)*/ +#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ABSTRIM_Pos (8UL) /*!< SRSS PWR_TRIM_REF_CTL: ACT_REF_ABSTRIM (Bit 8) */ +#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ABSTRIM_Msk (0x1f00UL) /*!< SRSS PWR_TRIM_REF_CTL: ACT_REF_ABSTRIM (Bitfield-Mask: 0x1f)*/ +#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_IBOOST_Pos (14UL) /*!< SRSS PWR_TRIM_REF_CTL: ACT_REF_IBOOST (Bit 14) */ +#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_IBOOST_Msk (0x4000UL) /*!< SRSS PWR_TRIM_REF_CTL: ACT_REF_IBOOST (Bitfield-Mask: 0x01)*/ +#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_TCTRIM_Pos (16UL) /*!< SRSS PWR_TRIM_REF_CTL: DPSLP_REF_TCTRIM (Bit 16) */ +#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_TCTRIM_Msk (0xf0000UL) /*!< SRSS PWR_TRIM_REF_CTL: DPSLP_REF_TCTRIM (Bitfield-Mask: 0x0f)*/ +#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ABSTRIM_Pos (20UL) /*!< SRSS PWR_TRIM_REF_CTL: DPSLP_REF_ABSTRIM (Bit 20) */ +#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ABSTRIM_Msk (0x1f00000UL) /*!< SRSS PWR_TRIM_REF_CTL: DPSLP_REF_ABSTRIM (Bitfield-Mask: 0x1f)*/ +#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ITRIM_Pos (28UL) /*!< SRSS PWR_TRIM_REF_CTL: DPSLP_REF_ITRIM (Bit 28) */ +#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ITRIM_Msk (0xf0000000UL) /*!< SRSS PWR_TRIM_REF_CTL: DPSLP_REF_ITRIM (Bitfield-Mask: 0x0f)*/ +/* =============================================== SRSS.PWR_TRIM_BODOVP_CTL ================================================ */ +#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_TRIPSEL_Pos (0UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: HVPORBOD_TRIPSEL (Bit 0) */ +#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_TRIPSEL_Msk (0x7UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: HVPORBOD_TRIPSEL (Bitfield-Mask: 0x07)*/ +#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_OFSTRIM_Pos (4UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: HVPORBOD_OFSTRIM (Bit 4) */ +#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_OFSTRIM_Msk (0x70UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: HVPORBOD_OFSTRIM (Bitfield-Mask: 0x07)*/ +#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_ITRIM_Pos (7UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: HVPORBOD_ITRIM (Bit 7) */ +#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_ITRIM_Msk (0x380UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: HVPORBOD_ITRIM (Bitfield-Mask: 0x07)*/ +#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_TRIPSEL_Pos (10UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: LVPORBOD_TRIPSEL (Bit 10) */ +#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_TRIPSEL_Msk (0x1c00UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: LVPORBOD_TRIPSEL (Bitfield-Mask: 0x07)*/ +#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_OFSTRIM_Pos (14UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: LVPORBOD_OFSTRIM (Bit 14) */ +#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_OFSTRIM_Msk (0x1c000UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: LVPORBOD_OFSTRIM (Bitfield-Mask: 0x07)*/ +#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_ITRIM_Pos (17UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: LVPORBOD_ITRIM (Bit 17) */ +#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_ITRIM_Msk (0xe0000UL) /*!< SRSS PWR_TRIM_BODOVP_CTL: LVPORBOD_ITRIM (Bitfield-Mask: 0x07)*/ +/* ================================================= SRSS.CLK_TRIM_CCO_CTL ================================================= */ +#define SRSS_CLK_TRIM_CCO_CTL_CCO_RCSTRIM_Pos (0UL) /*!< SRSS CLK_TRIM_CCO_CTL: CCO_RCSTRIM (Bit 0) */ +#define SRSS_CLK_TRIM_CCO_CTL_CCO_RCSTRIM_Msk (0x3fUL) /*!< SRSS CLK_TRIM_CCO_CTL: CCO_RCSTRIM (Bitfield-Mask: 0x3f) */ +#define SRSS_CLK_TRIM_CCO_CTL_CCO_STABLE_CNT_Pos (24UL) /*!< SRSS CLK_TRIM_CCO_CTL: CCO_STABLE_CNT (Bit 24) */ +#define SRSS_CLK_TRIM_CCO_CTL_CCO_STABLE_CNT_Msk (0x3f000000UL) /*!< SRSS CLK_TRIM_CCO_CTL: CCO_STABLE_CNT (Bitfield-Mask: 0x3f)*/ +#define SRSS_CLK_TRIM_CCO_CTL_ENABLE_CNT_Pos (31UL) /*!< SRSS CLK_TRIM_CCO_CTL: ENABLE_CNT (Bit 31) */ +#define SRSS_CLK_TRIM_CCO_CTL_ENABLE_CNT_Msk (0x80000000UL) /*!< SRSS CLK_TRIM_CCO_CTL: ENABLE_CNT (Bitfield-Mask: 0x01) */ +/* ================================================ SRSS.CLK_TRIM_CCO_CTL2 ================================================= */ +#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM1_Pos (0UL) /*!< SRSS CLK_TRIM_CCO_CTL2: CCO_FCTRIM1 (Bit 0) */ +#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM1_Msk (0x1fUL) /*!< SRSS CLK_TRIM_CCO_CTL2: CCO_FCTRIM1 (Bitfield-Mask: 0x1f) */ +#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM2_Pos (5UL) /*!< SRSS CLK_TRIM_CCO_CTL2: CCO_FCTRIM2 (Bit 5) */ +#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM2_Msk (0x3e0UL) /*!< SRSS CLK_TRIM_CCO_CTL2: CCO_FCTRIM2 (Bitfield-Mask: 0x1f) */ +#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM3_Pos (10UL) /*!< SRSS CLK_TRIM_CCO_CTL2: CCO_FCTRIM3 (Bit 10) */ +#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM3_Msk (0x7c00UL) /*!< SRSS CLK_TRIM_CCO_CTL2: CCO_FCTRIM3 (Bitfield-Mask: 0x1f) */ +#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM4_Pos (15UL) /*!< SRSS CLK_TRIM_CCO_CTL2: CCO_FCTRIM4 (Bit 15) */ +#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM4_Msk (0xf8000UL) /*!< SRSS CLK_TRIM_CCO_CTL2: CCO_FCTRIM4 (Bitfield-Mask: 0x1f) */ +#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM5_Pos (20UL) /*!< SRSS CLK_TRIM_CCO_CTL2: CCO_FCTRIM5 (Bit 20) */ +#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM5_Msk (0x1f00000UL) /*!< SRSS CLK_TRIM_CCO_CTL2: CCO_FCTRIM5 (Bitfield-Mask: 0x1f) */ +/* ================================================ SRSS.PWR_TRIM_WAKE_CTL ================================================= */ +#define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos (0UL) /*!< SRSS PWR_TRIM_WAKE_CTL: WAKE_DELAY (Bit 0) */ +#define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk (0xffUL) /*!< SRSS PWR_TRIM_WAKE_CTL: WAKE_DELAY (Bitfield-Mask: 0xff) */ +/* ================================================= SRSS.PWR_TRIM_LVD_CTL ================================================= */ +#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_OFSTRIM_Pos (0UL) /*!< SRSS PWR_TRIM_LVD_CTL: HVLVD1_OFSTRIM (Bit 0) */ +#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_OFSTRIM_Msk (0x7UL) /*!< SRSS PWR_TRIM_LVD_CTL: HVLVD1_OFSTRIM (Bitfield-Mask: 0x07)*/ +#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_ITRIM_Pos (4UL) /*!< SRSS PWR_TRIM_LVD_CTL: HVLVD1_ITRIM (Bit 4) */ +#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_ITRIM_Msk (0x70UL) /*!< SRSS PWR_TRIM_LVD_CTL: HVLVD1_ITRIM (Bitfield-Mask: 0x07) */ +/* ================================================= SRSS.CLK_TRIM_ILO_CTL ================================================= */ +#define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Pos (0UL) /*!< SRSS CLK_TRIM_ILO_CTL: ILO_FTRIM (Bit 0) */ +#define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Msk (0x3fUL) /*!< SRSS CLK_TRIM_ILO_CTL: ILO_FTRIM (Bitfield-Mask: 0x3f) */ +/* =============================================== SRSS.PWR_TRIM_PWRSYS_CTL ================================================ */ +#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Pos (0UL) /*!< SRSS PWR_TRIM_PWRSYS_CTL: ACT_REG_TRIM (Bit 0) */ +#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Msk (0x1fUL) /*!< SRSS PWR_TRIM_PWRSYS_CTL: ACT_REG_TRIM (Bitfield-Mask: 0x1f)*/ +#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Pos (30UL) /*!< SRSS PWR_TRIM_PWRSYS_CTL: ACT_REG_BOOST (Bit 30) */ +#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Msk (0xc0000000UL) /*!< SRSS PWR_TRIM_PWRSYS_CTL: ACT_REG_BOOST (Bitfield-Mask: 0x03)*/ +/* ================================================= SRSS.CLK_TRIM_ECO_CTL ================================================= */ +#define SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Pos (0UL) /*!< SRSS CLK_TRIM_ECO_CTL: WDTRIM (Bit 0) */ +#define SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Msk (0x7UL) /*!< SRSS CLK_TRIM_ECO_CTL: WDTRIM (Bitfield-Mask: 0x07) */ +#define SRSS_CLK_TRIM_ECO_CTL_ATRIM_Pos (4UL) /*!< SRSS CLK_TRIM_ECO_CTL: ATRIM (Bit 4) */ +#define SRSS_CLK_TRIM_ECO_CTL_ATRIM_Msk (0xf0UL) /*!< SRSS CLK_TRIM_ECO_CTL: ATRIM (Bitfield-Mask: 0x0f) */ +#define SRSS_CLK_TRIM_ECO_CTL_FTRIM_Pos (8UL) /*!< SRSS CLK_TRIM_ECO_CTL: FTRIM (Bit 8) */ +#define SRSS_CLK_TRIM_ECO_CTL_FTRIM_Msk (0x300UL) /*!< SRSS CLK_TRIM_ECO_CTL: FTRIM (Bitfield-Mask: 0x03) */ +#define SRSS_CLK_TRIM_ECO_CTL_RTRIM_Pos (10UL) /*!< SRSS CLK_TRIM_ECO_CTL: RTRIM (Bit 10) */ +#define SRSS_CLK_TRIM_ECO_CTL_RTRIM_Msk (0xc00UL) /*!< SRSS CLK_TRIM_ECO_CTL: RTRIM (Bitfield-Mask: 0x03) */ +#define SRSS_CLK_TRIM_ECO_CTL_GTRIM_Pos (12UL) /*!< SRSS CLK_TRIM_ECO_CTL: GTRIM (Bit 12) */ +#define SRSS_CLK_TRIM_ECO_CTL_GTRIM_Msk (0x3000UL) /*!< SRSS CLK_TRIM_ECO_CTL: GTRIM (Bitfield-Mask: 0x03) */ +#define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Pos (16UL) /*!< SRSS CLK_TRIM_ECO_CTL: ITRIM (Bit 16) */ +#define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Msk (0x3f0000UL) /*!< SRSS CLK_TRIM_ECO_CTL: ITRIM (Bitfield-Mask: 0x3f) */ +/* ================================================ SRSS.CLK_TRIM_PILO_CTL ================================================= */ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Pos (0UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_CFREQ (Bit 0) */ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Msk (0x3fUL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_CFREQ (Bitfield-Mask: 0x3f) */ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Pos (12UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_OSC_TRIM (Bit 12) */ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Msk (0x7000UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_OSC_TRIM (Bitfield-Mask: 0x07)*/ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Pos (16UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_COMP_TRIM (Bit 16) */ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Msk (0x30000UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_COMP_TRIM (Bitfield-Mask: 0x03)*/ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Pos (18UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_NBIAS_TRIM (Bit 18) */ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Msk (0xc0000UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_NBIAS_TRIM (Bitfield-Mask: 0x03)*/ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Pos (20UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_RES_TRIM (Bit 20) */ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Msk (0x1f00000UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_RES_TRIM (Bitfield-Mask: 0x1f)*/ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Pos (26UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_ISLOPE_TRIM (Bit 26) */ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Msk (0xc000000UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_ISLOPE_TRIM (Bitfield-Mask: 0x03)*/ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Pos (28UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_VTDIFF_TRIM (Bit 28) */ +#define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Msk (0x70000000UL) /*!< SRSS CLK_TRIM_PILO_CTL: PILO_VTDIFF_TRIM (Bitfield-Mask: 0x07)*/ +/* ================================================ SRSS.CLK_TRIM_PILO_CTL2 ================================================ */ +#define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Pos (0UL) /*!< SRSS CLK_TRIM_PILO_CTL2: PILO_VREF_TRIM (Bit 0) */ +#define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Msk (0xffUL) /*!< SRSS CLK_TRIM_PILO_CTL2: PILO_VREF_TRIM (Bitfield-Mask: 0xff)*/ +#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Pos (8UL) /*!< SRSS CLK_TRIM_PILO_CTL2: PILO_IREFBM_TRIM (Bit 8) */ +#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Msk (0x1f00UL) /*!< SRSS CLK_TRIM_PILO_CTL2: PILO_IREFBM_TRIM (Bitfield-Mask: 0x1f)*/ +#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Pos (16UL) /*!< SRSS CLK_TRIM_PILO_CTL2: PILO_IREF_TRIM (Bit 16) */ +#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Msk (0xff0000UL) /*!< SRSS CLK_TRIM_PILO_CTL2: PILO_IREF_TRIM (Bitfield-Mask: 0xff)*/ +/* ================================================ SRSS.CLK_TRIM_PILO_CTL3 ================================================ */ +#define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Pos (0UL) /*!< SRSS CLK_TRIM_PILO_CTL3: PILO_ENGOPT (Bit 0) */ +#define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Msk (0xffffUL) /*!< SRSS CLK_TRIM_PILO_CTL3: PILO_ENGOPT (Bitfield-Mask: 0xffff)*/ + + +#endif /* _CYIP_SRSS_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_tcpwm.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_tcpwm.h new file mode 100644 index 0000000000..72a3c48110 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_tcpwm.h @@ -0,0 +1,191 @@ +/***************************************************************************//** +* \file cyip_tcpwm.h +* +* \brief +* TCPWM IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_TCPWM_H_ +#define _CYIP_TCPWM_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ TCPWM ================ */ +/* =========================================================================================================================== */ + +#define TCPWM_CNT_SECTION_SIZE 0x00000040UL +#define TCPWM_SECTION_SIZE 0x00010000UL + +/** + * \brief Timer/Counter/PWM Counter Module (TCPWM_CNT) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */ + __IM uint32_t STATUS; /*!< 0x00000004 Counter status register */ + __IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */ + __IOM uint32_t CC; /*!< 0x0000000C Counter compare/capture register */ + __IOM uint32_t CC_BUFF; /*!< 0x00000010 Counter buffered compare/capture register */ + __IOM uint32_t PERIOD; /*!< 0x00000014 Counter period register */ + __IOM uint32_t PERIOD_BUFF; /*!< 0x00000018 Counter buffered period register */ + __IM uint32_t RESERVED; + __IOM uint32_t TR_CTRL0; /*!< 0x00000020 Counter trigger control register 0 */ + __IOM uint32_t TR_CTRL1; /*!< 0x00000024 Counter trigger control register 1 */ + __IOM uint32_t TR_CTRL2; /*!< 0x00000028 Counter trigger control register 2 */ + __IM uint32_t RESERVED1; + __IOM uint32_t INTR; /*!< 0x00000030 Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000034 Interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000038 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x0000003C Interrupt masked request register */ +} TCPWM_CNT_Type; /*!< Size = 64 (0x40) */ + +/** + * \brief Timer/Counter/PWM (TCPWM) + */ +typedef struct { /*!< TCPWM Structure */ + __IOM uint32_t CTRL; /*!< 0x00000000 TCPWM control register */ + __IOM uint32_t CTRL_CLR; /*!< 0x00000004 TCPWM control clear register */ + __IOM uint32_t CTRL_SET; /*!< 0x00000008 TCPWM control set register */ + __IOM uint32_t CMD_CAPTURE; /*!< 0x0000000C TCPWM capture command register */ + __IOM uint32_t CMD_RELOAD; /*!< 0x00000010 TCPWM reload command register */ + __IOM uint32_t CMD_STOP; /*!< 0x00000014 TCPWM stop command register */ + __IOM uint32_t CMD_START; /*!< 0x00000018 TCPWM start command register */ + __IM uint32_t INTR_CAUSE; /*!< 0x0000001C TCPWM Counter interrupt cause register */ + __IM uint32_t RESERVED[56]; + TCPWM_CNT_Type CNT[32]; /*!< 0x00000100 Timer/Counter/PWM Counter Module */ +} TCPWM_Type; /*!< Size = 2304 (0x900) */ + + +/* ==================================================== TCPWM_CNT.CTRL ===================================================== */ +#define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Pos (0UL) /*!< TCPWM_CNT CTRL: AUTO_RELOAD_CC (Bit 0) */ +#define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk (0x1UL) /*!< TCPWM_CNT CTRL: AUTO_RELOAD_CC (Bitfield-Mask: 0x01) */ +#define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos (1UL) /*!< TCPWM_CNT CTRL: AUTO_RELOAD_PERIOD (Bit 1) */ +#define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk (0x2UL) /*!< TCPWM_CNT CTRL: AUTO_RELOAD_PERIOD (Bitfield-Mask: 0x01) */ +#define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Pos (2UL) /*!< TCPWM_CNT CTRL: PWM_SYNC_KILL (Bit 2) */ +#define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Msk (0x4UL) /*!< TCPWM_CNT CTRL: PWM_SYNC_KILL (Bitfield-Mask: 0x01) */ +#define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Pos (3UL) /*!< TCPWM_CNT CTRL: PWM_STOP_ON_KILL (Bit 3) */ +#define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Msk (0x8UL) /*!< TCPWM_CNT CTRL: PWM_STOP_ON_KILL (Bitfield-Mask: 0x01) */ +#define TCPWM_CNT_CTRL_GENERIC_Pos (8UL) /*!< TCPWM_CNT CTRL: GENERIC (Bit 8) */ +#define TCPWM_CNT_CTRL_GENERIC_Msk (0xff00UL) /*!< TCPWM_CNT CTRL: GENERIC (Bitfield-Mask: 0xff) */ +#define TCPWM_CNT_CTRL_UP_DOWN_MODE_Pos (16UL) /*!< TCPWM_CNT CTRL: UP_DOWN_MODE (Bit 16) */ +#define TCPWM_CNT_CTRL_UP_DOWN_MODE_Msk (0x30000UL) /*!< TCPWM_CNT CTRL: UP_DOWN_MODE (Bitfield-Mask: 0x03) */ +#define TCPWM_CNT_CTRL_ONE_SHOT_Pos (18UL) /*!< TCPWM_CNT CTRL: ONE_SHOT (Bit 18) */ +#define TCPWM_CNT_CTRL_ONE_SHOT_Msk (0x40000UL) /*!< TCPWM_CNT CTRL: ONE_SHOT (Bitfield-Mask: 0x01) */ +#define TCPWM_CNT_CTRL_QUADRATURE_MODE_Pos (20UL) /*!< TCPWM_CNT CTRL: QUADRATURE_MODE (Bit 20) */ +#define TCPWM_CNT_CTRL_QUADRATURE_MODE_Msk (0x300000UL) /*!< TCPWM_CNT CTRL: QUADRATURE_MODE (Bitfield-Mask: 0x03) */ +#define TCPWM_CNT_CTRL_MODE_Pos (24UL) /*!< TCPWM_CNT CTRL: MODE (Bit 24) */ +#define TCPWM_CNT_CTRL_MODE_Msk (0x7000000UL) /*!< TCPWM_CNT CTRL: MODE (Bitfield-Mask: 0x07) */ +/* =================================================== TCPWM_CNT.STATUS ==================================================== */ +#define TCPWM_CNT_STATUS_DOWN_Pos (0UL) /*!< TCPWM_CNT STATUS: DOWN (Bit 0) */ +#define TCPWM_CNT_STATUS_DOWN_Msk (0x1UL) /*!< TCPWM_CNT STATUS: DOWN (Bitfield-Mask: 0x01) */ +#define TCPWM_CNT_STATUS_GENERIC_Pos (8UL) /*!< TCPWM_CNT STATUS: GENERIC (Bit 8) */ +#define TCPWM_CNT_STATUS_GENERIC_Msk (0xff00UL) /*!< TCPWM_CNT STATUS: GENERIC (Bitfield-Mask: 0xff) */ +#define TCPWM_CNT_STATUS_RUNNING_Pos (31UL) /*!< TCPWM_CNT STATUS: RUNNING (Bit 31) */ +#define TCPWM_CNT_STATUS_RUNNING_Msk (0x80000000UL) /*!< TCPWM_CNT STATUS: RUNNING (Bitfield-Mask: 0x01) */ +/* =================================================== TCPWM_CNT.COUNTER =================================================== */ +#define TCPWM_CNT_COUNTER_COUNTER_Pos (0UL) /*!< TCPWM_CNT COUNTER: COUNTER (Bit 0) */ +#define TCPWM_CNT_COUNTER_COUNTER_Msk (0xffffffffUL) /*!< TCPWM_CNT COUNTER: COUNTER (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TCPWM_CNT.CC ====================================================== */ +#define TCPWM_CNT_CC_CC_Pos (0UL) /*!< TCPWM_CNT CC: CC (Bit 0) */ +#define TCPWM_CNT_CC_CC_Msk (0xffffffffUL) /*!< TCPWM_CNT CC: CC (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TCPWM_CNT.CC_BUFF =================================================== */ +#define TCPWM_CNT_CC_BUFF_CC_Pos (0UL) /*!< TCPWM_CNT CC_BUFF: CC (Bit 0) */ +#define TCPWM_CNT_CC_BUFF_CC_Msk (0xffffffffUL) /*!< TCPWM_CNT CC_BUFF: CC (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TCPWM_CNT.PERIOD ==================================================== */ +#define TCPWM_CNT_PERIOD_PERIOD_Pos (0UL) /*!< TCPWM_CNT PERIOD: PERIOD (Bit 0) */ +#define TCPWM_CNT_PERIOD_PERIOD_Msk (0xffffffffUL) /*!< TCPWM_CNT PERIOD: PERIOD (Bitfield-Mask: 0xffffffff) */ +/* ================================================= TCPWM_CNT.PERIOD_BUFF ================================================= */ +#define TCPWM_CNT_PERIOD_BUFF_PERIOD_Pos (0UL) /*!< TCPWM_CNT PERIOD_BUFF: PERIOD (Bit 0) */ +#define TCPWM_CNT_PERIOD_BUFF_PERIOD_Msk (0xffffffffUL) /*!< TCPWM_CNT PERIOD_BUFF: PERIOD (Bitfield-Mask: 0xffffffff) */ +/* ================================================== TCPWM_CNT.TR_CTRL0 =================================================== */ +#define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Pos (0UL) /*!< TCPWM_CNT TR_CTRL0: CAPTURE_SEL (Bit 0) */ +#define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Msk (0xfUL) /*!< TCPWM_CNT TR_CTRL0: CAPTURE_SEL (Bitfield-Mask: 0x0f) */ +#define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Pos (4UL) /*!< TCPWM_CNT TR_CTRL0: COUNT_SEL (Bit 4) */ +#define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Msk (0xf0UL) /*!< TCPWM_CNT TR_CTRL0: COUNT_SEL (Bitfield-Mask: 0x0f) */ +#define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Pos (8UL) /*!< TCPWM_CNT TR_CTRL0: RELOAD_SEL (Bit 8) */ +#define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Msk (0xf00UL) /*!< TCPWM_CNT TR_CTRL0: RELOAD_SEL (Bitfield-Mask: 0x0f) */ +#define TCPWM_CNT_TR_CTRL0_STOP_SEL_Pos (12UL) /*!< TCPWM_CNT TR_CTRL0: STOP_SEL (Bit 12) */ +#define TCPWM_CNT_TR_CTRL0_STOP_SEL_Msk (0xf000UL) /*!< TCPWM_CNT TR_CTRL0: STOP_SEL (Bitfield-Mask: 0x0f) */ +#define TCPWM_CNT_TR_CTRL0_START_SEL_Pos (16UL) /*!< TCPWM_CNT TR_CTRL0: START_SEL (Bit 16) */ +#define TCPWM_CNT_TR_CTRL0_START_SEL_Msk (0xf0000UL) /*!< TCPWM_CNT TR_CTRL0: START_SEL (Bitfield-Mask: 0x0f) */ +/* ================================================== TCPWM_CNT.TR_CTRL1 =================================================== */ +#define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Pos (0UL) /*!< TCPWM_CNT TR_CTRL1: CAPTURE_EDGE (Bit 0) */ +#define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Msk (0x3UL) /*!< TCPWM_CNT TR_CTRL1: CAPTURE_EDGE (Bitfield-Mask: 0x03) */ +#define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Pos (2UL) /*!< TCPWM_CNT TR_CTRL1: COUNT_EDGE (Bit 2) */ +#define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Msk (0xcUL) /*!< TCPWM_CNT TR_CTRL1: COUNT_EDGE (Bitfield-Mask: 0x03) */ +#define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Pos (4UL) /*!< TCPWM_CNT TR_CTRL1: RELOAD_EDGE (Bit 4) */ +#define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Msk (0x30UL) /*!< TCPWM_CNT TR_CTRL1: RELOAD_EDGE (Bitfield-Mask: 0x03) */ +#define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Pos (6UL) /*!< TCPWM_CNT TR_CTRL1: STOP_EDGE (Bit 6) */ +#define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Msk (0xc0UL) /*!< TCPWM_CNT TR_CTRL1: STOP_EDGE (Bitfield-Mask: 0x03) */ +#define TCPWM_CNT_TR_CTRL1_START_EDGE_Pos (8UL) /*!< TCPWM_CNT TR_CTRL1: START_EDGE (Bit 8) */ +#define TCPWM_CNT_TR_CTRL1_START_EDGE_Msk (0x300UL) /*!< TCPWM_CNT TR_CTRL1: START_EDGE (Bitfield-Mask: 0x03) */ +/* ================================================== TCPWM_CNT.TR_CTRL2 =================================================== */ +#define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Pos (0UL) /*!< TCPWM_CNT TR_CTRL2: CC_MATCH_MODE (Bit 0) */ +#define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Msk (0x3UL) /*!< TCPWM_CNT TR_CTRL2: CC_MATCH_MODE (Bitfield-Mask: 0x03) */ +#define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Pos (2UL) /*!< TCPWM_CNT TR_CTRL2: OVERFLOW_MODE (Bit 2) */ +#define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Msk (0xcUL) /*!< TCPWM_CNT TR_CTRL2: OVERFLOW_MODE (Bitfield-Mask: 0x03) */ +#define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Pos (4UL) /*!< TCPWM_CNT TR_CTRL2: UNDERFLOW_MODE (Bit 4) */ +#define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Msk (0x30UL) /*!< TCPWM_CNT TR_CTRL2: UNDERFLOW_MODE (Bitfield-Mask: 0x03) */ +/* ==================================================== TCPWM_CNT.INTR ===================================================== */ +#define TCPWM_CNT_INTR_TC_Pos (0UL) /*!< TCPWM_CNT INTR: TC (Bit 0) */ +#define TCPWM_CNT_INTR_TC_Msk (0x1UL) /*!< TCPWM_CNT INTR: TC (Bitfield-Mask: 0x01) */ +#define TCPWM_CNT_INTR_CC_MATCH_Pos (1UL) /*!< TCPWM_CNT INTR: CC_MATCH (Bit 1) */ +#define TCPWM_CNT_INTR_CC_MATCH_Msk (0x2UL) /*!< TCPWM_CNT INTR: CC_MATCH (Bitfield-Mask: 0x01) */ +/* ================================================== TCPWM_CNT.INTR_SET =================================================== */ +#define TCPWM_CNT_INTR_SET_TC_Pos (0UL) /*!< TCPWM_CNT INTR_SET: TC (Bit 0) */ +#define TCPWM_CNT_INTR_SET_TC_Msk (0x1UL) /*!< TCPWM_CNT INTR_SET: TC (Bitfield-Mask: 0x01) */ +#define TCPWM_CNT_INTR_SET_CC_MATCH_Pos (1UL) /*!< TCPWM_CNT INTR_SET: CC_MATCH (Bit 1) */ +#define TCPWM_CNT_INTR_SET_CC_MATCH_Msk (0x2UL) /*!< TCPWM_CNT INTR_SET: CC_MATCH (Bitfield-Mask: 0x01) */ +/* ================================================== TCPWM_CNT.INTR_MASK ================================================== */ +#define TCPWM_CNT_INTR_MASK_TC_Pos (0UL) /*!< TCPWM_CNT INTR_MASK: TC (Bit 0) */ +#define TCPWM_CNT_INTR_MASK_TC_Msk (0x1UL) /*!< TCPWM_CNT INTR_MASK: TC (Bitfield-Mask: 0x01) */ +#define TCPWM_CNT_INTR_MASK_CC_MATCH_Pos (1UL) /*!< TCPWM_CNT INTR_MASK: CC_MATCH (Bit 1) */ +#define TCPWM_CNT_INTR_MASK_CC_MATCH_Msk (0x2UL) /*!< TCPWM_CNT INTR_MASK: CC_MATCH (Bitfield-Mask: 0x01) */ +/* ================================================= TCPWM_CNT.INTR_MASKED ================================================= */ +#define TCPWM_CNT_INTR_MASKED_TC_Pos (0UL) /*!< TCPWM_CNT INTR_MASKED: TC (Bit 0) */ +#define TCPWM_CNT_INTR_MASKED_TC_Msk (0x1UL) /*!< TCPWM_CNT INTR_MASKED: TC (Bitfield-Mask: 0x01) */ +#define TCPWM_CNT_INTR_MASKED_CC_MATCH_Pos (1UL) /*!< TCPWM_CNT INTR_MASKED: CC_MATCH (Bit 1) */ +#define TCPWM_CNT_INTR_MASKED_CC_MATCH_Msk (0x2UL) /*!< TCPWM_CNT INTR_MASKED: CC_MATCH (Bitfield-Mask: 0x01) */ + + +/* ====================================================== TCPWM.CTRL ======================================================= */ +#define TCPWM_CTRL_COUNTER_ENABLED_Pos (0UL) /*!< TCPWM CTRL: COUNTER_ENABLED (Bit 0) */ +#define TCPWM_CTRL_COUNTER_ENABLED_Msk (0xffffffffUL) /*!< TCPWM CTRL: COUNTER_ENABLED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TCPWM.CTRL_CLR ===================================================== */ +#define TCPWM_CTRL_CLR_COUNTER_ENABLED_Pos (0UL) /*!< TCPWM CTRL_CLR: COUNTER_ENABLED (Bit 0) */ +#define TCPWM_CTRL_CLR_COUNTER_ENABLED_Msk (0xffffffffUL) /*!< TCPWM CTRL_CLR: COUNTER_ENABLED (Bitfield-Mask: 0xffffffff)*/ +/* ==================================================== TCPWM.CTRL_SET ===================================================== */ +#define TCPWM_CTRL_SET_COUNTER_ENABLED_Pos (0UL) /*!< TCPWM CTRL_SET: COUNTER_ENABLED (Bit 0) */ +#define TCPWM_CTRL_SET_COUNTER_ENABLED_Msk (0xffffffffUL) /*!< TCPWM CTRL_SET: COUNTER_ENABLED (Bitfield-Mask: 0xffffffff)*/ +/* =================================================== TCPWM.CMD_CAPTURE =================================================== */ +#define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Pos (0UL) /*!< TCPWM CMD_CAPTURE: COUNTER_CAPTURE (Bit 0) */ +#define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Msk (0xffffffffUL) /*!< TCPWM CMD_CAPTURE: COUNTER_CAPTURE (Bitfield-Mask: 0xffffffff)*/ +/* =================================================== TCPWM.CMD_RELOAD ==================================================== */ +#define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Pos (0UL) /*!< TCPWM CMD_RELOAD: COUNTER_RELOAD (Bit 0) */ +#define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Msk (0xffffffffUL) /*!< TCPWM CMD_RELOAD: COUNTER_RELOAD (Bitfield-Mask: 0xffffffff)*/ +/* ==================================================== TCPWM.CMD_STOP ===================================================== */ +#define TCPWM_CMD_STOP_COUNTER_STOP_Pos (0UL) /*!< TCPWM CMD_STOP: COUNTER_STOP (Bit 0) */ +#define TCPWM_CMD_STOP_COUNTER_STOP_Msk (0xffffffffUL) /*!< TCPWM CMD_STOP: COUNTER_STOP (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TCPWM.CMD_START ==================================================== */ +#define TCPWM_CMD_START_COUNTER_START_Pos (0UL) /*!< TCPWM CMD_START: COUNTER_START (Bit 0) */ +#define TCPWM_CMD_START_COUNTER_START_Msk (0xffffffffUL) /*!< TCPWM CMD_START: COUNTER_START (Bitfield-Mask: 0xffffffff)*/ +/* =================================================== TCPWM.INTR_CAUSE ==================================================== */ +#define TCPWM_INTR_CAUSE_COUNTER_INT_Pos (0UL) /*!< TCPWM INTR_CAUSE: COUNTER_INT (Bit 0) */ +#define TCPWM_INTR_CAUSE_COUNTER_INT_Msk (0xffffffffUL) /*!< TCPWM INTR_CAUSE: COUNTER_INT (Bitfield-Mask: 0xffffffff) */ + + +#endif /* _CYIP_TCPWM_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_udb.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_udb.h new file mode 100644 index 0000000000..163e6eeaf4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/ip/cyip_udb.h @@ -0,0 +1,2052 @@ +/***************************************************************************//** +* \file cyip_udb.h +* +* \brief +* UDB IP definitions +* +* \note +* Generated 2/9/2017 by CyDeviceHeaderGenerator v1.1.0.47 +* from the register map configuration rev#961378 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CYIP_UDB_H_ +#define _CYIP_UDB_H_ + +#include "cyip_headers.h" + +/* =========================================================================================================================== */ +/* ================ UDB ================ */ +/* =========================================================================================================================== */ + +#define UDB_WRKONE_SECTION_SIZE 0x00000800UL +#define UDB_WRKMULT_SECTION_SIZE 0x00001000UL +#define UDB_UDBPAIR_UDBSNG_SECTION_SIZE 0x00000080UL +#define UDB_UDBPAIR_ROUTE_SECTION_SIZE 0x00000100UL +#define UDB_UDBPAIR_SECTION_SIZE 0x00000200UL +#define UDB_DSI_SECTION_SIZE 0x00000080UL +#define UDB_PA_SECTION_SIZE 0x00000040UL +#define UDB_BCTL_SECTION_SIZE 0x00000080UL +#define UDB_UDBIF_SECTION_SIZE 0x00000020UL +#define UDB_SECTION_SIZE 0x00010000UL + +/** + * \brief UDB Working Registers (2 registers from one UDB at a time) (UDB_WRKONE) + */ +typedef struct { + __IOM uint32_t A[64]; /*!< 0x00000000 Accumulator Registers {A1,A0} */ + __IOM uint32_t D[64]; /*!< 0x00000100 Data Registers {D1,D0} */ + __IOM uint32_t F[64]; /*!< 0x00000200 FIFOs {F1,F0} */ + __IOM uint32_t CTL_ST[64]; /*!< 0x00000300 Status and Control Registers {CTL,ST} */ + __IOM uint32_t ACTL_MSK[64]; /*!< 0x00000400 Mask and Auxiliary Control Registers {ACTL,MSK} */ + __IM uint32_t MC[64]; /*!< 0x00000500 PLD Macrocell Read Registers {00,MC} */ + __IM uint32_t RESERVED[128]; +} UDB_WRKONE_Type; /*!< Size = 1536 (0x600) */ + +/** + * \brief UDB Working Registers (1 register from multiple UDBs at a time) (UDB_WRKMULT) + */ +typedef struct { + __IOM uint32_t A0[64]; /*!< 0x00000000 Accumulator 0 */ + __IOM uint32_t A1[64]; /*!< 0x00000100 Accumulator 1 */ + __IOM uint32_t D0[64]; /*!< 0x00000200 Data 0 */ + __IOM uint32_t D1[64]; /*!< 0x00000300 Data 1 */ + __IOM uint32_t F0[64]; /*!< 0x00000400 FIFO 0 */ + __IOM uint32_t F1[64]; /*!< 0x00000500 FIFO 1 */ + __IM uint32_t ST[64]; /*!< 0x00000600 Status Register */ + __IOM uint32_t CTL[64]; /*!< 0x00000700 Control Register */ + __IOM uint32_t MSK[64]; /*!< 0x00000800 Interrupt Mask */ + __IOM uint32_t ACTL[64]; /*!< 0x00000900 Auxiliary Control */ + __IM uint32_t MC[64]; /*!< 0x00000A00 PLD Macrocell reading */ + __IM uint32_t RESERVED[320]; +} UDB_WRKMULT_Type; /*!< Size = 2816 (0xB00) */ + +/** + * \brief Single UDB Configuration (UDB_UDBPAIR_UDBSNG) + */ +typedef struct { + __IOM uint32_t PLD_IT[12]; /*!< 0x00000000 PLD Input Terms */ + __IOM uint32_t PLD_ORT0; /*!< 0x00000030 PLD OR Terms */ + __IOM uint32_t PLD_ORT1; /*!< 0x00000034 PLD OR Terms */ + __IOM uint32_t PLD_CFG0; /*!< 0x00000038 PLD configuration for Carry Enable, Constant, and XOR feedback */ + __IOM uint32_t PLD_CFG1; /*!< 0x0000003C PLD configuration for Set / Reset selection, and Bypass control*/ + __IOM uint32_t DPATH_CFG0; /*!< 0x00000040 Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, + D0_LD, D1_LD) */ + __IOM uint32_t DPATH_CFG1; /*!< 0x00000044 Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 + thru OUT5) */ + __IOM uint32_t DPATH_CFG2; /*!< 0x00000048 Datapath output synchronization, ALU mask, compare 0 and 1 + masks */ + __IOM uint32_t DPATH_CFG3; /*!< 0x0000004C Datapath mask enables, shift in, carry in, compare, chaining, + MSB configs; FIFO, shift and parallel input control */ + __IOM uint32_t DPATH_CFG4; /*!< 0x00000050 Datapath FIFO and register access configuration control */ + __IOM uint32_t SC_CFG0; /*!< 0x00000054 SC Mode 0 and 1 control registers; status register input mode; + general SC configuration */ + __IOM uint32_t SC_CFG1; /*!< 0x00000058 SC counter control */ + __IOM uint32_t RC_CFG0; /*!< 0x0000005C PLD0, PLD1, Datatpath, and SC clock and reset control */ + __IOM uint32_t RC_CFG1; /*!< 0x00000060 PLD0, PLD1, Datatpath, and SC clock selection, general reset + control */ + __IOM uint32_t DPATH_OPC[4]; /*!< 0x00000064 Datapath opcode configuration */ + __IM uint32_t RESERVED[3]; +} UDB_UDBPAIR_UDBSNG_Type; /*!< Size = 116 (0x74) */ + +/** + * \brief Routing Configuration for one UDB Pair (UDB_UDBPAIR_ROUTE) + */ +typedef struct { + __IOM uint32_t TOP_V_BOT; /*!< 0x00000000 See mxudb BROS 002-10714 Appendix A section 'TVI vs. BVI + Muxing' */ + __IOM uint32_t LVI1_V_2; /*!< 0x00000004 See mxudb BROS 002-10714 Appendix A section 'LVI / RVI for + Horizontal Muxing' */ + __IOM uint32_t RVI1_V_2; /*!< 0x00000008 See mxudb BROS 002-10714 Appendix A section 'LVI / RVI for + Horizontal Muxing' */ + __IOM uint32_t TUI_CFG0; /*!< 0x0000000C See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t TUI_CFG1; /*!< 0x00000010 See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t TUI_CFG2; /*!< 0x00000014 See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t TUI_CFG3; /*!< 0x00000018 See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t TUI_CFG4; /*!< 0x0000001C See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t TUI_CFG5; /*!< 0x00000020 See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t BUI_CFG0; /*!< 0x00000024 See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t BUI_CFG1; /*!< 0x00000028 See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t BUI_CFG2; /*!< 0x0000002C See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t BUI_CFG3; /*!< 0x00000030 See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t BUI_CFG4; /*!< 0x00000034 See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t BUI_CFG5; /*!< 0x00000038 See mxudb BROS 002-10714 Appendix A section 'TUI / BUI Muxing' */ + __IOM uint32_t RVO_CFG0; /*!< 0x0000003C See mxudb BROS 002-10714 Appendix A section 'RVO Muxing' */ + __IOM uint32_t RVO_CFG1; /*!< 0x00000040 See mxudb BROS 002-10714 Appendix A section 'RVO Muxing' */ + __IOM uint32_t RVO_CFG2; /*!< 0x00000044 See mxudb BROS 002-10714 Appendix A section 'RVO Muxing' */ + __IOM uint32_t RVO_CFG3; /*!< 0x00000048 See mxudb BROS 002-10714 Appendix A section 'RVO Muxing' */ + __IOM uint32_t LVO_CFG0; /*!< 0x0000004C See mxudb BROS 002-10714 Appendix A section 'LVO Muxing' */ + __IOM uint32_t LVO_CFG1; /*!< 0x00000050 See mxudb BROS 002-10714 Appendix A section 'LVO Muxing' */ + __IOM uint32_t RHO_CFG0; /*!< 0x00000054 See mxudb BROS 002-10714 Appendix A section 'RHO Muxing' */ + __IOM uint32_t RHO_CFG1; /*!< 0x00000058 See mxudb BROS 002-10714 Appendix A section 'RHO Muxing' */ + __IOM uint32_t RHO_CFG2; /*!< 0x0000005C See mxudb BROS 002-10714 Appendix A section 'RHO Muxing' */ + __IOM uint32_t LHO_CFG0; /*!< 0x00000060 See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG1; /*!< 0x00000064 See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG2; /*!< 0x00000068 See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG3; /*!< 0x0000006C See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG4; /*!< 0x00000070 See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG5; /*!< 0x00000074 See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG6; /*!< 0x00000078 See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG7; /*!< 0x0000007C See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG8; /*!< 0x00000080 See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG9; /*!< 0x00000084 See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG10; /*!< 0x00000088 See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IOM uint32_t LHO_CFG11; /*!< 0x0000008C See mxudb BROS 002-10714 Appendix A section 'LHO Muxing' */ + __IM uint32_t RESERVED[28]; +} UDB_UDBPAIR_ROUTE_Type; /*!< Size = 144 (0x90) */ + +/** + * \brief UDB Pair Configuration (up to 32 Pairs) (UDB_UDBPAIR) + */ +typedef struct { + UDB_UDBPAIR_UDBSNG_Type UDBSNG[2]; /*!< 0x00000000 Single UDB Configuration */ + UDB_UDBPAIR_ROUTE_Type ROUTE; /*!< 0x00000100 Routing Configuration for one UDB Pair */ +} UDB_UDBPAIR_Type; /*!< Size = 512 (0x200) */ + +/** + * \brief DSI Configuration (up to 32 DSI) (UDB_DSI) + */ +typedef struct { + __IOM uint32_t LVI1_V_2; /*!< 0x00000000 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LVI / RVI for Horizontal Muxing' as + being equivalent */ + __IOM uint32_t RVI1_V_2; /*!< 0x00000004 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LVI / RVI for Horizontal Muxing' as + being equivalent */ + __IOM uint32_t DOP_CFG0; /*!< 0x00000008 See mxudb BROS 002-10714 Appendix B section 'DOP Muxing' */ + __IOM uint32_t DOP_CFG1; /*!< 0x0000000C See mxudb BROS 002-10714 Appendix B section 'DOP Muxing' */ + __IOM uint32_t DOP_CFG2; /*!< 0x00000010 See mxudb BROS 002-10714 Appendix B section 'DOP Muxing' */ + __IOM uint32_t DOP_CFG3; /*!< 0x00000014 See mxudb BROS 002-10714 Appendix B section 'DOP Muxing' */ + __IOM uint32_t DOT_CFG0; /*!< 0x00000018 See mxudb BROS 002-10714 Appendix B section 'DOT Muxing' */ + __IOM uint32_t DOT_CFG1; /*!< 0x0000001C See mxudb BROS 002-10714 Appendix B section 'DOT Muxing' */ + __IOM uint32_t DOT_CFG2; /*!< 0x00000020 See mxudb BROS 002-10714 Appendix B section 'DOT Muxing' */ + __IOM uint32_t DOT_CFG3; /*!< 0x00000024 See mxudb BROS 002-10714 Appendix B section 'DOT Muxing' */ + __IOM uint32_t RVO_CFG0; /*!< 0x00000028 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'RVO Muxing' as being equivalent */ + __IOM uint32_t RVO_CFG1; /*!< 0x0000002C See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'RVO Muxing' as being equivalent */ + __IOM uint32_t RVO_CFG2; /*!< 0x00000030 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'RVO Muxing' as being equivalent */ + __IOM uint32_t RVO_CFG3; /*!< 0x00000034 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'RVO Muxing' as being equivalent */ + __IOM uint32_t LVO_CFG0; /*!< 0x00000038 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LVO Muxing' as being equivalent */ + __IOM uint32_t LVO_CFG1; /*!< 0x0000003C See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LVO Muxing' as being equivalent */ + __IOM uint32_t RHO_CFG0; /*!< 0x00000040 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'RHO Muxing' as being equivalent */ + __IOM uint32_t RHO_CFG1; /*!< 0x00000044 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'RHO Muxing' as being equivalent */ + __IOM uint32_t RHO_CFG2; /*!< 0x00000048 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'RHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG0; /*!< 0x0000004C See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG1; /*!< 0x00000050 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG2; /*!< 0x00000054 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG3; /*!< 0x00000058 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG4; /*!< 0x0000005C See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG5; /*!< 0x00000060 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG6; /*!< 0x00000064 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG7; /*!< 0x00000068 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG8; /*!< 0x0000006C See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG9; /*!< 0x00000070 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG10; /*!< 0x00000074 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IOM uint32_t LHO_CFG11; /*!< 0x00000078 See mxudb BROS 002-10714 Appendix B DSI Routing which refers + to Appendix A section 'LHO Muxing' as being equivalent */ + __IM uint32_t RESERVED; +} UDB_DSI_Type; /*!< Size = 124 (0x7C) */ + +/** + * \brief Port Adapter Configuration (up to 32 PA) (UDB_PA) + */ +typedef struct { + __IOM uint32_t CFG0; /*!< 0x00000000 PA Data In Clock Control Register */ + __IOM uint32_t CFG1; /*!< 0x00000004 PA Data Out Clock Control Register */ + __IOM uint32_t CFG2; /*!< 0x00000008 PA Clock Select Register */ + __IOM uint32_t CFG3; /*!< 0x0000000C PA Reset Select Register */ + __IOM uint32_t CFG4; /*!< 0x00000010 PA Reset Enable Register */ + __IOM uint32_t CFG5; /*!< 0x00000014 PA Reset Pin Select Register */ + __IOM uint32_t CFG6; /*!< 0x00000018 PA Input Data Sync Control Register - Low */ + __IOM uint32_t CFG7; /*!< 0x0000001C PA Input Data Sync Control Register - High */ + __IOM uint32_t CFG8; /*!< 0x00000020 PA Output Data Sync Control Register - Low */ + __IOM uint32_t CFG9; /*!< 0x00000024 PA Output Data Sync Control Register - High */ + __IOM uint32_t CFG10; /*!< 0x00000028 PA Output Data Select Register - Low */ + __IOM uint32_t CFG11; /*!< 0x0000002C PA Output Data Select Register - High */ + __IOM uint32_t CFG12; /*!< 0x00000030 PA OE Select Register - Low */ + __IOM uint32_t CFG13; /*!< 0x00000034 PA OE Select Register - High */ + __IOM uint32_t CFG14; /*!< 0x00000038 PA OE Sync Register */ + __IM uint32_t RESERVED; +} UDB_PA_Type; /*!< Size = 60 (0x3C) */ + +/** + * \brief UDB Array Bank Control (UDB_BCTL) + */ +typedef struct { + __IOM uint32_t MDCLK_EN; /*!< 0x00000000 Master Digital Clock Enable Register */ + __IOM uint32_t MBCLK_EN; /*!< 0x00000004 Master clk_peri_app Enable Register */ + __IOM uint32_t BOTSEL_L; /*!< 0x00000008 Lower Nibble Bottom Digital Clock Select Register */ + __IOM uint32_t BOTSEL_U; /*!< 0x0000000C Upper Nibble Bottom Digital Clock Select Register */ + __IOM uint32_t QCLK_EN[16]; /*!< 0x00000010 Quadrant Digital Clock Enable Registers */ + __IM uint32_t RESERVED[12]; +} UDB_BCTL_Type; /*!< Size = 80 (0x50) */ + +/** + * \brief UDB Subsystem Interface Configuration (UDB_UDBIF) + */ +typedef struct { + __IOM uint32_t BANK_CTL; /*!< 0x00000000 Bank Control */ + __IOM uint32_t INT_CLK_CTL; /*!< 0x00000004 Interrupt Clock Control */ + __IOM uint32_t INT_CFG; /*!< 0x00000008 Interrupt Configuration */ + __IOM uint32_t TR_CLK_CTL; /*!< 0x0000000C Trigger Clock Control */ + __IOM uint32_t TR_CFG; /*!< 0x00000010 Trigger Configuration */ + __IOM uint32_t PRIVATE; /*!< 0x00000014 Internal use only */ + __IM uint32_t RESERVED[2]; +} UDB_UDBIF_Type; /*!< Size = 24 (0x18) */ + +/** + * \brief Programmable Digital Subsystem (UDB) + */ +typedef struct { /*!< UDB Structure */ + UDB_WRKONE_Type WRKONE; /*!< 0x00000000 UDB Working Registers (2 registers from one UDB at a time) */ + __IM uint32_t RESERVED[512]; + UDB_WRKMULT_Type WRKMULT; /*!< 0x00001000 UDB Working Registers (1 register from multiple UDBs at a time)*/ + UDB_UDBPAIR_Type UDBPAIR[32]; /*!< 0x00002000 UDB Pair Configuration (up to 32 Pairs) */ + UDB_DSI_Type DSI[32]; /*!< 0x00006000 DSI Configuration (up to 32 DSI) */ + UDB_PA_Type PA[32]; /*!< 0x00007000 Port Adapter Configuration (up to 32 PA) */ + UDB_BCTL_Type BCTL; /*!< 0x00007800 UDB Array Bank Control */ + __IM uint32_t RESERVED1[32]; + UDB_UDBIF_Type UDBIF; /*!< 0x00007900 UDB Subsystem Interface Configuration */ +} UDB_Type; /*!< Size = 31008 (0x7920) */ + + +/* ===================================================== UDB_WRKONE.A ====================================================== */ +#define UDB_WRKONE_A_A0_Pos (0UL) /*!< UDB_WRKONE A: A0 (Bit 0) */ +#define UDB_WRKONE_A_A0_Msk (0xffUL) /*!< UDB_WRKONE A: A0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKONE_A_A1_Pos (8UL) /*!< UDB_WRKONE A: A1 (Bit 8) */ +#define UDB_WRKONE_A_A1_Msk (0xff00UL) /*!< UDB_WRKONE A: A1 (Bitfield-Mask: 0xff) */ +/* ===================================================== UDB_WRKONE.D ====================================================== */ +#define UDB_WRKONE_D_D0_Pos (0UL) /*!< UDB_WRKONE D: D0 (Bit 0) */ +#define UDB_WRKONE_D_D0_Msk (0xffUL) /*!< UDB_WRKONE D: D0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKONE_D_D1_Pos (8UL) /*!< UDB_WRKONE D: D1 (Bit 8) */ +#define UDB_WRKONE_D_D1_Msk (0xff00UL) /*!< UDB_WRKONE D: D1 (Bitfield-Mask: 0xff) */ +/* ===================================================== UDB_WRKONE.F ====================================================== */ +#define UDB_WRKONE_F_F0_Pos (0UL) /*!< UDB_WRKONE F: F0 (Bit 0) */ +#define UDB_WRKONE_F_F0_Msk (0xffUL) /*!< UDB_WRKONE F: F0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKONE_F_F1_Pos (8UL) /*!< UDB_WRKONE F: F1 (Bit 8) */ +#define UDB_WRKONE_F_F1_Msk (0xff00UL) /*!< UDB_WRKONE F: F1 (Bitfield-Mask: 0xff) */ +/* =================================================== UDB_WRKONE.CTL_ST =================================================== */ +#define UDB_WRKONE_CTL_ST_ST_Pos (0UL) /*!< UDB_WRKONE CTL_ST: ST (Bit 0) */ +#define UDB_WRKONE_CTL_ST_ST_Msk (0xffUL) /*!< UDB_WRKONE CTL_ST: ST (Bitfield-Mask: 0xff) */ +#define UDB_WRKONE_CTL_ST_CTL_Pos (8UL) /*!< UDB_WRKONE CTL_ST: CTL (Bit 8) */ +#define UDB_WRKONE_CTL_ST_CTL_Msk (0xff00UL) /*!< UDB_WRKONE CTL_ST: CTL (Bitfield-Mask: 0xff) */ +/* ================================================== UDB_WRKONE.ACTL_MSK ================================================== */ +#define UDB_WRKONE_ACTL_MSK_MSK_Pos (0UL) /*!< UDB_WRKONE ACTL_MSK: MSK (Bit 0) */ +#define UDB_WRKONE_ACTL_MSK_MSK_Msk (0x7fUL) /*!< UDB_WRKONE ACTL_MSK: MSK (Bitfield-Mask: 0x7f) */ +#define UDB_WRKONE_ACTL_MSK_FIFO0_CLR_Pos (8UL) /*!< UDB_WRKONE ACTL_MSK: FIFO0_CLR (Bit 8) */ +#define UDB_WRKONE_ACTL_MSK_FIFO0_CLR_Msk (0x100UL) /*!< UDB_WRKONE ACTL_MSK: FIFO0_CLR (Bitfield-Mask: 0x01) */ +#define UDB_WRKONE_ACTL_MSK_FIFO1_CLR_Pos (9UL) /*!< UDB_WRKONE ACTL_MSK: FIFO1_CLR (Bit 9) */ +#define UDB_WRKONE_ACTL_MSK_FIFO1_CLR_Msk (0x200UL) /*!< UDB_WRKONE ACTL_MSK: FIFO1_CLR (Bitfield-Mask: 0x01) */ +#define UDB_WRKONE_ACTL_MSK_FIFO0_LVL_Pos (10UL) /*!< UDB_WRKONE ACTL_MSK: FIFO0_LVL (Bit 10) */ +#define UDB_WRKONE_ACTL_MSK_FIFO0_LVL_Msk (0x400UL) /*!< UDB_WRKONE ACTL_MSK: FIFO0_LVL (Bitfield-Mask: 0x01) */ +#define UDB_WRKONE_ACTL_MSK_FIFO1_LVL_Pos (11UL) /*!< UDB_WRKONE ACTL_MSK: FIFO1_LVL (Bit 11) */ +#define UDB_WRKONE_ACTL_MSK_FIFO1_LVL_Msk (0x800UL) /*!< UDB_WRKONE ACTL_MSK: FIFO1_LVL (Bitfield-Mask: 0x01) */ +#define UDB_WRKONE_ACTL_MSK_INT_EN_Pos (12UL) /*!< UDB_WRKONE ACTL_MSK: INT_EN (Bit 12) */ +#define UDB_WRKONE_ACTL_MSK_INT_EN_Msk (0x1000UL) /*!< UDB_WRKONE ACTL_MSK: INT_EN (Bitfield-Mask: 0x01) */ +#define UDB_WRKONE_ACTL_MSK_CNT_START_Pos (13UL) /*!< UDB_WRKONE ACTL_MSK: CNT_START (Bit 13) */ +#define UDB_WRKONE_ACTL_MSK_CNT_START_Msk (0x2000UL) /*!< UDB_WRKONE ACTL_MSK: CNT_START (Bitfield-Mask: 0x01) */ +/* ===================================================== UDB_WRKONE.MC ===================================================== */ +#define UDB_WRKONE_MC_PLD0_MC_Pos (0UL) /*!< UDB_WRKONE MC: PLD0_MC (Bit 0) */ +#define UDB_WRKONE_MC_PLD0_MC_Msk (0xfUL) /*!< UDB_WRKONE MC: PLD0_MC (Bitfield-Mask: 0x0f) */ +#define UDB_WRKONE_MC_PLD1_MC_Pos (4UL) /*!< UDB_WRKONE MC: PLD1_MC (Bit 4) */ +#define UDB_WRKONE_MC_PLD1_MC_Msk (0xf0UL) /*!< UDB_WRKONE MC: PLD1_MC (Bitfield-Mask: 0x0f) */ + + +/* ==================================================== UDB_WRKMULT.A0 ===================================================== */ +#define UDB_WRKMULT_A0_A0_0_Pos (0UL) /*!< UDB_WRKMULT A0: A0_0 (Bit 0) */ +#define UDB_WRKMULT_A0_A0_0_Msk (0xffUL) /*!< UDB_WRKMULT A0: A0_0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_A0_A0_1_Pos (8UL) /*!< UDB_WRKMULT A0: A0_1 (Bit 8) */ +#define UDB_WRKMULT_A0_A0_1_Msk (0xff00UL) /*!< UDB_WRKMULT A0: A0_1 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_A0_A0_2_Pos (16UL) /*!< UDB_WRKMULT A0: A0_2 (Bit 16) */ +#define UDB_WRKMULT_A0_A0_2_Msk (0xff0000UL) /*!< UDB_WRKMULT A0: A0_2 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_A0_A0_3_Pos (24UL) /*!< UDB_WRKMULT A0: A0_3 (Bit 24) */ +#define UDB_WRKMULT_A0_A0_3_Msk (0xff000000UL) /*!< UDB_WRKMULT A0: A0_3 (Bitfield-Mask: 0xff) */ +/* ==================================================== UDB_WRKMULT.A1 ===================================================== */ +#define UDB_WRKMULT_A1_A1_0_Pos (0UL) /*!< UDB_WRKMULT A1: A1_0 (Bit 0) */ +#define UDB_WRKMULT_A1_A1_0_Msk (0xffUL) /*!< UDB_WRKMULT A1: A1_0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_A1_A1_1_Pos (8UL) /*!< UDB_WRKMULT A1: A1_1 (Bit 8) */ +#define UDB_WRKMULT_A1_A1_1_Msk (0xff00UL) /*!< UDB_WRKMULT A1: A1_1 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_A1_A1_2_Pos (16UL) /*!< UDB_WRKMULT A1: A1_2 (Bit 16) */ +#define UDB_WRKMULT_A1_A1_2_Msk (0xff0000UL) /*!< UDB_WRKMULT A1: A1_2 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_A1_A1_3_Pos (24UL) /*!< UDB_WRKMULT A1: A1_3 (Bit 24) */ +#define UDB_WRKMULT_A1_A1_3_Msk (0xff000000UL) /*!< UDB_WRKMULT A1: A1_3 (Bitfield-Mask: 0xff) */ +/* ==================================================== UDB_WRKMULT.D0 ===================================================== */ +#define UDB_WRKMULT_D0_D0_0_Pos (0UL) /*!< UDB_WRKMULT D0: D0_0 (Bit 0) */ +#define UDB_WRKMULT_D0_D0_0_Msk (0xffUL) /*!< UDB_WRKMULT D0: D0_0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_D0_D0_1_Pos (8UL) /*!< UDB_WRKMULT D0: D0_1 (Bit 8) */ +#define UDB_WRKMULT_D0_D0_1_Msk (0xff00UL) /*!< UDB_WRKMULT D0: D0_1 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_D0_D0_2_Pos (16UL) /*!< UDB_WRKMULT D0: D0_2 (Bit 16) */ +#define UDB_WRKMULT_D0_D0_2_Msk (0xff0000UL) /*!< UDB_WRKMULT D0: D0_2 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_D0_D0_3_Pos (24UL) /*!< UDB_WRKMULT D0: D0_3 (Bit 24) */ +#define UDB_WRKMULT_D0_D0_3_Msk (0xff000000UL) /*!< UDB_WRKMULT D0: D0_3 (Bitfield-Mask: 0xff) */ +/* ==================================================== UDB_WRKMULT.D1 ===================================================== */ +#define UDB_WRKMULT_D1_D1_0_Pos (0UL) /*!< UDB_WRKMULT D1: D1_0 (Bit 0) */ +#define UDB_WRKMULT_D1_D1_0_Msk (0xffUL) /*!< UDB_WRKMULT D1: D1_0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_D1_D1_1_Pos (8UL) /*!< UDB_WRKMULT D1: D1_1 (Bit 8) */ +#define UDB_WRKMULT_D1_D1_1_Msk (0xff00UL) /*!< UDB_WRKMULT D1: D1_1 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_D1_D1_2_Pos (16UL) /*!< UDB_WRKMULT D1: D1_2 (Bit 16) */ +#define UDB_WRKMULT_D1_D1_2_Msk (0xff0000UL) /*!< UDB_WRKMULT D1: D1_2 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_D1_D1_3_Pos (24UL) /*!< UDB_WRKMULT D1: D1_3 (Bit 24) */ +#define UDB_WRKMULT_D1_D1_3_Msk (0xff000000UL) /*!< UDB_WRKMULT D1: D1_3 (Bitfield-Mask: 0xff) */ +/* ==================================================== UDB_WRKMULT.F0 ===================================================== */ +#define UDB_WRKMULT_F0_F0_0_Pos (0UL) /*!< UDB_WRKMULT F0: F0_0 (Bit 0) */ +#define UDB_WRKMULT_F0_F0_0_Msk (0xffUL) /*!< UDB_WRKMULT F0: F0_0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_F0_F0_1_Pos (8UL) /*!< UDB_WRKMULT F0: F0_1 (Bit 8) */ +#define UDB_WRKMULT_F0_F0_1_Msk (0xff00UL) /*!< UDB_WRKMULT F0: F0_1 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_F0_F0_2_Pos (16UL) /*!< UDB_WRKMULT F0: F0_2 (Bit 16) */ +#define UDB_WRKMULT_F0_F0_2_Msk (0xff0000UL) /*!< UDB_WRKMULT F0: F0_2 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_F0_F0_3_Pos (24UL) /*!< UDB_WRKMULT F0: F0_3 (Bit 24) */ +#define UDB_WRKMULT_F0_F0_3_Msk (0xff000000UL) /*!< UDB_WRKMULT F0: F0_3 (Bitfield-Mask: 0xff) */ +/* ==================================================== UDB_WRKMULT.F1 ===================================================== */ +#define UDB_WRKMULT_F1_F1_0_Pos (0UL) /*!< UDB_WRKMULT F1: F1_0 (Bit 0) */ +#define UDB_WRKMULT_F1_F1_0_Msk (0xffUL) /*!< UDB_WRKMULT F1: F1_0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_F1_F1_1_Pos (8UL) /*!< UDB_WRKMULT F1: F1_1 (Bit 8) */ +#define UDB_WRKMULT_F1_F1_1_Msk (0xff00UL) /*!< UDB_WRKMULT F1: F1_1 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_F1_F1_2_Pos (16UL) /*!< UDB_WRKMULT F1: F1_2 (Bit 16) */ +#define UDB_WRKMULT_F1_F1_2_Msk (0xff0000UL) /*!< UDB_WRKMULT F1: F1_2 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_F1_F1_3_Pos (24UL) /*!< UDB_WRKMULT F1: F1_3 (Bit 24) */ +#define UDB_WRKMULT_F1_F1_3_Msk (0xff000000UL) /*!< UDB_WRKMULT F1: F1_3 (Bitfield-Mask: 0xff) */ +/* ==================================================== UDB_WRKMULT.ST ===================================================== */ +#define UDB_WRKMULT_ST_ST_0_Pos (0UL) /*!< UDB_WRKMULT ST: ST_0 (Bit 0) */ +#define UDB_WRKMULT_ST_ST_0_Msk (0xffUL) /*!< UDB_WRKMULT ST: ST_0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_ST_ST_1_Pos (8UL) /*!< UDB_WRKMULT ST: ST_1 (Bit 8) */ +#define UDB_WRKMULT_ST_ST_1_Msk (0xff00UL) /*!< UDB_WRKMULT ST: ST_1 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_ST_ST_2_Pos (16UL) /*!< UDB_WRKMULT ST: ST_2 (Bit 16) */ +#define UDB_WRKMULT_ST_ST_2_Msk (0xff0000UL) /*!< UDB_WRKMULT ST: ST_2 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_ST_ST_3_Pos (24UL) /*!< UDB_WRKMULT ST: ST_3 (Bit 24) */ +#define UDB_WRKMULT_ST_ST_3_Msk (0xff000000UL) /*!< UDB_WRKMULT ST: ST_3 (Bitfield-Mask: 0xff) */ +/* ==================================================== UDB_WRKMULT.CTL ==================================================== */ +#define UDB_WRKMULT_CTL_CTL_0_Pos (0UL) /*!< UDB_WRKMULT CTL: CTL_0 (Bit 0) */ +#define UDB_WRKMULT_CTL_CTL_0_Msk (0xffUL) /*!< UDB_WRKMULT CTL: CTL_0 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_CTL_CTL_1_Pos (8UL) /*!< UDB_WRKMULT CTL: CTL_1 (Bit 8) */ +#define UDB_WRKMULT_CTL_CTL_1_Msk (0xff00UL) /*!< UDB_WRKMULT CTL: CTL_1 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_CTL_CTL_2_Pos (16UL) /*!< UDB_WRKMULT CTL: CTL_2 (Bit 16) */ +#define UDB_WRKMULT_CTL_CTL_2_Msk (0xff0000UL) /*!< UDB_WRKMULT CTL: CTL_2 (Bitfield-Mask: 0xff) */ +#define UDB_WRKMULT_CTL_CTL_3_Pos (24UL) /*!< UDB_WRKMULT CTL: CTL_3 (Bit 24) */ +#define UDB_WRKMULT_CTL_CTL_3_Msk (0xff000000UL) /*!< UDB_WRKMULT CTL: CTL_3 (Bitfield-Mask: 0xff) */ +/* ==================================================== UDB_WRKMULT.MSK ==================================================== */ +#define UDB_WRKMULT_MSK_MSK_0_Pos (0UL) /*!< UDB_WRKMULT MSK: MSK_0 (Bit 0) */ +#define UDB_WRKMULT_MSK_MSK_0_Msk (0x7fUL) /*!< UDB_WRKMULT MSK: MSK_0 (Bitfield-Mask: 0x7f) */ +#define UDB_WRKMULT_MSK_MSK_1_Pos (8UL) /*!< UDB_WRKMULT MSK: MSK_1 (Bit 8) */ +#define UDB_WRKMULT_MSK_MSK_1_Msk (0x7f00UL) /*!< UDB_WRKMULT MSK: MSK_1 (Bitfield-Mask: 0x7f) */ +#define UDB_WRKMULT_MSK_MSK_2_Pos (16UL) /*!< UDB_WRKMULT MSK: MSK_2 (Bit 16) */ +#define UDB_WRKMULT_MSK_MSK_2_Msk (0x7f0000UL) /*!< UDB_WRKMULT MSK: MSK_2 (Bitfield-Mask: 0x7f) */ +#define UDB_WRKMULT_MSK_MSK_3_Pos (24UL) /*!< UDB_WRKMULT MSK: MSK_3 (Bit 24) */ +#define UDB_WRKMULT_MSK_MSK_3_Msk (0x7f000000UL) /*!< UDB_WRKMULT MSK: MSK_3 (Bitfield-Mask: 0x7f) */ +/* =================================================== UDB_WRKMULT.ACTL ==================================================== */ +#define UDB_WRKMULT_ACTL_FIFO0_CLR_0_Pos (0UL) /*!< UDB_WRKMULT ACTL: FIFO0_CLR_0 (Bit 0) */ +#define UDB_WRKMULT_ACTL_FIFO0_CLR_0_Msk (0x1UL) /*!< UDB_WRKMULT ACTL: FIFO0_CLR_0 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO1_CLR_0_Pos (1UL) /*!< UDB_WRKMULT ACTL: FIFO1_CLR_0 (Bit 1) */ +#define UDB_WRKMULT_ACTL_FIFO1_CLR_0_Msk (0x2UL) /*!< UDB_WRKMULT ACTL: FIFO1_CLR_0 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO0_LVL_0_Pos (2UL) /*!< UDB_WRKMULT ACTL: FIFO0_LVL_0 (Bit 2) */ +#define UDB_WRKMULT_ACTL_FIFO0_LVL_0_Msk (0x4UL) /*!< UDB_WRKMULT ACTL: FIFO0_LVL_0 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO1_LVL_0_Pos (3UL) /*!< UDB_WRKMULT ACTL: FIFO1_LVL_0 (Bit 3) */ +#define UDB_WRKMULT_ACTL_FIFO1_LVL_0_Msk (0x8UL) /*!< UDB_WRKMULT ACTL: FIFO1_LVL_0 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_INT_EN_0_Pos (4UL) /*!< UDB_WRKMULT ACTL: INT_EN_0 (Bit 4) */ +#define UDB_WRKMULT_ACTL_INT_EN_0_Msk (0x10UL) /*!< UDB_WRKMULT ACTL: INT_EN_0 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_CNT_START_0_Pos (5UL) /*!< UDB_WRKMULT ACTL: CNT_START_0 (Bit 5) */ +#define UDB_WRKMULT_ACTL_CNT_START_0_Msk (0x20UL) /*!< UDB_WRKMULT ACTL: CNT_START_0 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO0_CLR_1_Pos (8UL) /*!< UDB_WRKMULT ACTL: FIFO0_CLR_1 (Bit 8) */ +#define UDB_WRKMULT_ACTL_FIFO0_CLR_1_Msk (0x100UL) /*!< UDB_WRKMULT ACTL: FIFO0_CLR_1 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO1_CLR_1_Pos (9UL) /*!< UDB_WRKMULT ACTL: FIFO1_CLR_1 (Bit 9) */ +#define UDB_WRKMULT_ACTL_FIFO1_CLR_1_Msk (0x200UL) /*!< UDB_WRKMULT ACTL: FIFO1_CLR_1 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO0_LVL_1_Pos (10UL) /*!< UDB_WRKMULT ACTL: FIFO0_LVL_1 (Bit 10) */ +#define UDB_WRKMULT_ACTL_FIFO0_LVL_1_Msk (0x400UL) /*!< UDB_WRKMULT ACTL: FIFO0_LVL_1 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO1_LVL_1_Pos (11UL) /*!< UDB_WRKMULT ACTL: FIFO1_LVL_1 (Bit 11) */ +#define UDB_WRKMULT_ACTL_FIFO1_LVL_1_Msk (0x800UL) /*!< UDB_WRKMULT ACTL: FIFO1_LVL_1 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_INT_EN_1_Pos (12UL) /*!< UDB_WRKMULT ACTL: INT_EN_1 (Bit 12) */ +#define UDB_WRKMULT_ACTL_INT_EN_1_Msk (0x1000UL) /*!< UDB_WRKMULT ACTL: INT_EN_1 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_CNT_START_1_Pos (13UL) /*!< UDB_WRKMULT ACTL: CNT_START_1 (Bit 13) */ +#define UDB_WRKMULT_ACTL_CNT_START_1_Msk (0x2000UL) /*!< UDB_WRKMULT ACTL: CNT_START_1 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO0_CLR_2_Pos (16UL) /*!< UDB_WRKMULT ACTL: FIFO0_CLR_2 (Bit 16) */ +#define UDB_WRKMULT_ACTL_FIFO0_CLR_2_Msk (0x10000UL) /*!< UDB_WRKMULT ACTL: FIFO0_CLR_2 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO1_CLR_2_Pos (17UL) /*!< UDB_WRKMULT ACTL: FIFO1_CLR_2 (Bit 17) */ +#define UDB_WRKMULT_ACTL_FIFO1_CLR_2_Msk (0x20000UL) /*!< UDB_WRKMULT ACTL: FIFO1_CLR_2 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO0_LVL_2_Pos (18UL) /*!< UDB_WRKMULT ACTL: FIFO0_LVL_2 (Bit 18) */ +#define UDB_WRKMULT_ACTL_FIFO0_LVL_2_Msk (0x40000UL) /*!< UDB_WRKMULT ACTL: FIFO0_LVL_2 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO1_LVL_2_Pos (19UL) /*!< UDB_WRKMULT ACTL: FIFO1_LVL_2 (Bit 19) */ +#define UDB_WRKMULT_ACTL_FIFO1_LVL_2_Msk (0x80000UL) /*!< UDB_WRKMULT ACTL: FIFO1_LVL_2 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_INT_EN_2_Pos (20UL) /*!< UDB_WRKMULT ACTL: INT_EN_2 (Bit 20) */ +#define UDB_WRKMULT_ACTL_INT_EN_2_Msk (0x100000UL) /*!< UDB_WRKMULT ACTL: INT_EN_2 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_CNT_START_2_Pos (21UL) /*!< UDB_WRKMULT ACTL: CNT_START_2 (Bit 21) */ +#define UDB_WRKMULT_ACTL_CNT_START_2_Msk (0x200000UL) /*!< UDB_WRKMULT ACTL: CNT_START_2 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO0_CLR_3_Pos (24UL) /*!< UDB_WRKMULT ACTL: FIFO0_CLR_3 (Bit 24) */ +#define UDB_WRKMULT_ACTL_FIFO0_CLR_3_Msk (0x1000000UL) /*!< UDB_WRKMULT ACTL: FIFO0_CLR_3 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO1_CLR_3_Pos (25UL) /*!< UDB_WRKMULT ACTL: FIFO1_CLR_3 (Bit 25) */ +#define UDB_WRKMULT_ACTL_FIFO1_CLR_3_Msk (0x2000000UL) /*!< UDB_WRKMULT ACTL: FIFO1_CLR_3 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO0_LVL_3_Pos (26UL) /*!< UDB_WRKMULT ACTL: FIFO0_LVL_3 (Bit 26) */ +#define UDB_WRKMULT_ACTL_FIFO0_LVL_3_Msk (0x4000000UL) /*!< UDB_WRKMULT ACTL: FIFO0_LVL_3 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_FIFO1_LVL_3_Pos (27UL) /*!< UDB_WRKMULT ACTL: FIFO1_LVL_3 (Bit 27) */ +#define UDB_WRKMULT_ACTL_FIFO1_LVL_3_Msk (0x8000000UL) /*!< UDB_WRKMULT ACTL: FIFO1_LVL_3 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_INT_EN_3_Pos (28UL) /*!< UDB_WRKMULT ACTL: INT_EN_3 (Bit 28) */ +#define UDB_WRKMULT_ACTL_INT_EN_3_Msk (0x10000000UL) /*!< UDB_WRKMULT ACTL: INT_EN_3 (Bitfield-Mask: 0x01) */ +#define UDB_WRKMULT_ACTL_CNT_START_3_Pos (29UL) /*!< UDB_WRKMULT ACTL: CNT_START_3 (Bit 29) */ +#define UDB_WRKMULT_ACTL_CNT_START_3_Msk (0x20000000UL) /*!< UDB_WRKMULT ACTL: CNT_START_3 (Bitfield-Mask: 0x01) */ +/* ==================================================== UDB_WRKMULT.MC ===================================================== */ +#define UDB_WRKMULT_MC_PLD0_MC_0_Pos (0UL) /*!< UDB_WRKMULT MC: PLD0_MC_0 (Bit 0) */ +#define UDB_WRKMULT_MC_PLD0_MC_0_Msk (0xfUL) /*!< UDB_WRKMULT MC: PLD0_MC_0 (Bitfield-Mask: 0x0f) */ +#define UDB_WRKMULT_MC_PLD1_MC_0_Pos (4UL) /*!< UDB_WRKMULT MC: PLD1_MC_0 (Bit 4) */ +#define UDB_WRKMULT_MC_PLD1_MC_0_Msk (0xf0UL) /*!< UDB_WRKMULT MC: PLD1_MC_0 (Bitfield-Mask: 0x0f) */ +#define UDB_WRKMULT_MC_PLD0_MC_1_Pos (8UL) /*!< UDB_WRKMULT MC: PLD0_MC_1 (Bit 8) */ +#define UDB_WRKMULT_MC_PLD0_MC_1_Msk (0xf00UL) /*!< UDB_WRKMULT MC: PLD0_MC_1 (Bitfield-Mask: 0x0f) */ +#define UDB_WRKMULT_MC_PLD1_MC_1_Pos (12UL) /*!< UDB_WRKMULT MC: PLD1_MC_1 (Bit 12) */ +#define UDB_WRKMULT_MC_PLD1_MC_1_Msk (0xf000UL) /*!< UDB_WRKMULT MC: PLD1_MC_1 (Bitfield-Mask: 0x0f) */ +#define UDB_WRKMULT_MC_PLD0_MC_2_Pos (16UL) /*!< UDB_WRKMULT MC: PLD0_MC_2 (Bit 16) */ +#define UDB_WRKMULT_MC_PLD0_MC_2_Msk (0xf0000UL) /*!< UDB_WRKMULT MC: PLD0_MC_2 (Bitfield-Mask: 0x0f) */ +#define UDB_WRKMULT_MC_PLD1_MC_2_Pos (20UL) /*!< UDB_WRKMULT MC: PLD1_MC_2 (Bit 20) */ +#define UDB_WRKMULT_MC_PLD1_MC_2_Msk (0xf00000UL) /*!< UDB_WRKMULT MC: PLD1_MC_2 (Bitfield-Mask: 0x0f) */ +#define UDB_WRKMULT_MC_PLD0_MC_3_Pos (24UL) /*!< UDB_WRKMULT MC: PLD0_MC_3 (Bit 24) */ +#define UDB_WRKMULT_MC_PLD0_MC_3_Msk (0xf000000UL) /*!< UDB_WRKMULT MC: PLD0_MC_3 (Bitfield-Mask: 0x0f) */ +#define UDB_WRKMULT_MC_PLD1_MC_3_Pos (28UL) /*!< UDB_WRKMULT MC: PLD1_MC_3 (Bit 28) */ +#define UDB_WRKMULT_MC_PLD1_MC_3_Msk (0xf0000000UL) /*!< UDB_WRKMULT MC: PLD1_MC_3 (Bitfield-Mask: 0x0f) */ + + +/* =============================================== UDB_UDBPAIR_UDBSNG.PLD_IT =============================================== */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT0_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT0 (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT0_Msk (0x1UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT1_Pos (1UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT1 (Bit 1) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT1_Msk (0x2UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT2_Pos (2UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT2 (Bit 2) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT2_Msk (0x4UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT3_Pos (3UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT3 (Bit 3) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT3_Msk (0x8UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT4_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT4 (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT4_Msk (0x10UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT4 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT5_Pos (5UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT5 (Bit 5) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT5_Msk (0x20UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT5 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT6_Pos (6UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT6 (Bit 6) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT6_Msk (0x40UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT6 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT7_Pos (7UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT7 (Bit 7) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_C_FOR_PT7_Msk (0x80UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_C_FOR_PT7 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT0_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT0 (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT0_Msk (0x100UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT1_Pos (9UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT1 (Bit 9) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT1_Msk (0x200UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT2_Pos (10UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT2 (Bit 10) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT2_Msk (0x400UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT3_Pos (11UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT3 (Bit 11) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT3_Msk (0x800UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT4_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT4 (Bit 12) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT4_Msk (0x1000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT4 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT5_Pos (13UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT5 (Bit 13) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT5_Msk (0x2000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT5 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT6_Pos (14UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT6 (Bit 14) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT6_Msk (0x4000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT6 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT7_Pos (15UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT7 (Bit 15) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_C_FOR_PT7_Msk (0x8000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_C_FOR_PT7 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT0_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT0 (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT0_Msk (0x10000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT1_Pos (17UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT1 (Bit 17) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT1_Msk (0x20000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT2_Pos (18UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT2 (Bit 18) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT2_Msk (0x40000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT3_Pos (19UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT3 (Bit 19) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT3_Msk (0x80000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT4_Pos (20UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT4 (Bit 20) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT4_Msk (0x100000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT4 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT5_Pos (21UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT5 (Bit 21) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT5_Msk (0x200000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT5 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT6_Pos (22UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT6 (Bit 22) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT6_Msk (0x400000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT6 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT7_Pos (23UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT7 (Bit 23) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD0_INX_T_FOR_PT7_Msk (0x800000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD0_INX_T_FOR_PT7 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT0_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT0 (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT0_Msk (0x1000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT1_Pos (25UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT1 (Bit 25) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT1_Msk (0x2000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT2_Pos (26UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT2 (Bit 26) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT2_Msk (0x4000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT3_Pos (27UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT3 (Bit 27) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT3_Msk (0x8000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT4_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT4 (Bit 28) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT4_Msk (0x10000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT4 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT5_Pos (29UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT5 (Bit 29) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT5_Msk (0x20000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT5 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT6_Pos (30UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT6 (Bit 30) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT6_Msk (0x40000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT6 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT7_Pos (31UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT7 (Bit 31) */ +#define UDB_UDBPAIR_UDBSNG_PLD_IT_PLD1_INX_T_FOR_PT7_Msk (0x80000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_IT: PLD1_INX_T_FOR_PT7 (Bitfield-Mask: 0x01)*/ +/* ============================================== UDB_UDBPAIR_UDBSNG.PLD_ORT0 ============================================== */ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT0_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT0_T_FOR_OUT0 (Bit 0)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT0_Msk (0x1UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT0_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT0_Pos (1UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT1_T_FOR_OUT0 (Bit 1)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT0_Msk (0x2UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT1_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT0_Pos (2UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT2_T_FOR_OUT0 (Bit 2)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT0_Msk (0x4UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT2_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT0_Pos (3UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT3_T_FOR_OUT0 (Bit 3)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT0_Msk (0x8UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT3_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT0_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT4_T_FOR_OUT0 (Bit 4)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT0_Msk (0x10UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT4_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT0_Pos (5UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT5_T_FOR_OUT0 (Bit 5)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT0_Msk (0x20UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT5_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT0_Pos (6UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT6_T_FOR_OUT0 (Bit 6)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT0_Msk (0x40UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT6_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT0_Pos (7UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT7_T_FOR_OUT0 (Bit 7)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT0_Msk (0x80UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT7_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT0_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT0_T_FOR_OUT0 (Bit 8)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT0_Msk (0x100UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT0_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT0_Pos (9UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT1_T_FOR_OUT0 (Bit 9)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT0_Msk (0x200UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT1_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT0_Pos (10UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT2_T_FOR_OUT0 (Bit 10)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT0_Msk (0x400UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT2_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT0_Pos (11UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT3_T_FOR_OUT0 (Bit 11)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT0_Msk (0x800UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT3_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT0_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT4_T_FOR_OUT0 (Bit 12)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT0_Msk (0x1000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT4_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT0_Pos (13UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT5_T_FOR_OUT0 (Bit 13)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT0_Msk (0x2000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT5_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT0_Pos (14UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT6_T_FOR_OUT0 (Bit 14)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT0_Msk (0x4000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT6_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT0_Pos (15UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT7_T_FOR_OUT0 (Bit 15)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT0_Msk (0x8000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT7_T_FOR_OUT0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT1_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT0_T_FOR_OUT1 (Bit 16)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT0_T_FOR_OUT1_Msk (0x10000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT0_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT1_Pos (17UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT1_T_FOR_OUT1 (Bit 17)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT1_T_FOR_OUT1_Msk (0x20000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT1_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT1_Pos (18UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT2_T_FOR_OUT1 (Bit 18)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT2_T_FOR_OUT1_Msk (0x40000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT2_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT1_Pos (19UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT3_T_FOR_OUT1 (Bit 19)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT3_T_FOR_OUT1_Msk (0x80000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT3_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT1_Pos (20UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT4_T_FOR_OUT1 (Bit 20)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT4_T_FOR_OUT1_Msk (0x100000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT4_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT1_Pos (21UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT5_T_FOR_OUT1 (Bit 21)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT5_T_FOR_OUT1_Msk (0x200000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT5_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT1_Pos (22UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT6_T_FOR_OUT1 (Bit 22)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT6_T_FOR_OUT1_Msk (0x400000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT6_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT1_Pos (23UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT7_T_FOR_OUT1 (Bit 23)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD0_PT7_T_FOR_OUT1_Msk (0x800000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD0_PT7_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT1_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT0_T_FOR_OUT1 (Bit 24)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT0_T_FOR_OUT1_Msk (0x1000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT0_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT1_Pos (25UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT1_T_FOR_OUT1 (Bit 25)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT1_T_FOR_OUT1_Msk (0x2000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT1_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT1_Pos (26UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT2_T_FOR_OUT1 (Bit 26)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT2_T_FOR_OUT1_Msk (0x4000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT2_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT1_Pos (27UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT3_T_FOR_OUT1 (Bit 27)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT3_T_FOR_OUT1_Msk (0x8000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT3_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT1_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT4_T_FOR_OUT1 (Bit 28)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT4_T_FOR_OUT1_Msk (0x10000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT4_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT1_Pos (29UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT5_T_FOR_OUT1 (Bit 29)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT5_T_FOR_OUT1_Msk (0x20000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT5_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT1_Pos (30UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT6_T_FOR_OUT1 (Bit 30)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT6_T_FOR_OUT1_Msk (0x40000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT6_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT1_Pos (31UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT7_T_FOR_OUT1 (Bit 31)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT0_PLD1_PT7_T_FOR_OUT1_Msk (0x80000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT0: PLD1_PT7_T_FOR_OUT1 (Bitfield-Mask: 0x01)*/ +/* ============================================== UDB_UDBPAIR_UDBSNG.PLD_ORT1 ============================================== */ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT2_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT0_T_FOR_OUT2 (Bit 0)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT2_Msk (0x1UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT0_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT2_Pos (1UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT1_T_FOR_OUT2 (Bit 1)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT2_Msk (0x2UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT1_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT2_Pos (2UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT2_T_FOR_OUT2 (Bit 2)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT2_Msk (0x4UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT2_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT2_Pos (3UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT3_T_FOR_OUT2 (Bit 3)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT2_Msk (0x8UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT3_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT2_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT4_T_FOR_OUT2 (Bit 4)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT2_Msk (0x10UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT4_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT2_Pos (5UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT5_T_FOR_OUT2 (Bit 5)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT2_Msk (0x20UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT5_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT2_Pos (6UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT6_T_FOR_OUT2 (Bit 6)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT2_Msk (0x40UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT6_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT2_Pos (7UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT7_T_FOR_OUT2 (Bit 7)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT2_Msk (0x80UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT7_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT2_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT0_T_FOR_OUT2 (Bit 8)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT2_Msk (0x100UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT0_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT2_Pos (9UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT1_T_FOR_OUT2 (Bit 9)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT2_Msk (0x200UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT1_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT2_Pos (10UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT2_T_FOR_OUT2 (Bit 10)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT2_Msk (0x400UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT2_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT2_Pos (11UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT3_T_FOR_OUT2 (Bit 11)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT2_Msk (0x800UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT3_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT2_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT4_T_FOR_OUT2 (Bit 12)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT2_Msk (0x1000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT4_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT2_Pos (13UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT5_T_FOR_OUT2 (Bit 13)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT2_Msk (0x2000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT5_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT2_Pos (14UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT6_T_FOR_OUT2 (Bit 14)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT2_Msk (0x4000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT6_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT2_Pos (15UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT7_T_FOR_OUT2 (Bit 15)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT2_Msk (0x8000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT7_T_FOR_OUT2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT3_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT0_T_FOR_OUT3 (Bit 16)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT0_T_FOR_OUT3_Msk (0x10000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT0_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT3_Pos (17UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT1_T_FOR_OUT3 (Bit 17)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT1_T_FOR_OUT3_Msk (0x20000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT1_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT3_Pos (18UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT2_T_FOR_OUT3 (Bit 18)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT2_T_FOR_OUT3_Msk (0x40000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT2_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT3_Pos (19UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT3_T_FOR_OUT3 (Bit 19)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT3_T_FOR_OUT3_Msk (0x80000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT3_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT3_Pos (20UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT4_T_FOR_OUT3 (Bit 20)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT4_T_FOR_OUT3_Msk (0x100000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT4_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT3_Pos (21UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT5_T_FOR_OUT3 (Bit 21)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT5_T_FOR_OUT3_Msk (0x200000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT5_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT3_Pos (22UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT6_T_FOR_OUT3 (Bit 22)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT6_T_FOR_OUT3_Msk (0x400000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT6_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT3_Pos (23UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT7_T_FOR_OUT3 (Bit 23)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD0_PT7_T_FOR_OUT3_Msk (0x800000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD0_PT7_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT3_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT0_T_FOR_OUT3 (Bit 24)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT0_T_FOR_OUT3_Msk (0x1000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT0_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT3_Pos (25UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT1_T_FOR_OUT3 (Bit 25)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT1_T_FOR_OUT3_Msk (0x2000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT1_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT3_Pos (26UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT2_T_FOR_OUT3 (Bit 26)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT2_T_FOR_OUT3_Msk (0x4000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT2_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT3_Pos (27UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT3_T_FOR_OUT3 (Bit 27)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT3_T_FOR_OUT3_Msk (0x8000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT3_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT3_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT4_T_FOR_OUT3 (Bit 28)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT4_T_FOR_OUT3_Msk (0x10000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT4_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT3_Pos (29UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT5_T_FOR_OUT3 (Bit 29)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT5_T_FOR_OUT3_Msk (0x20000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT5_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT3_Pos (30UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT6_T_FOR_OUT3 (Bit 30)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT6_T_FOR_OUT3_Msk (0x40000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT6_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT3_Pos (31UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT7_T_FOR_OUT3 (Bit 31)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_ORT1_PLD1_PT7_T_FOR_OUT3_Msk (0x80000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_ORT1: PLD1_PT7_T_FOR_OUT3 (Bitfield-Mask: 0x01)*/ +/* ============================================== UDB_UDBPAIR_UDBSNG.PLD_CFG0 ============================================== */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_CEN_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC0_CEN (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_CEN_Msk (0x1UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC0_CEN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_DFF_C_Pos (1UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC0_DFF_C (Bit 1) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_DFF_C_Msk (0x2UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC0_DFF_C (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_CEN_Pos (2UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC1_CEN (Bit 2) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_CEN_Msk (0x4UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC1_CEN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_DFF_C_Pos (3UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC1_DFF_C (Bit 3) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_DFF_C_Msk (0x8UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC1_DFF_C (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_CEN_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC2_CEN (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_CEN_Msk (0x10UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC2_CEN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_DFF_C_Pos (5UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC2_DFF_C (Bit 5) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_DFF_C_Msk (0x20UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC2_DFF_C (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_CEN_Pos (6UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC3_CEN (Bit 6) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_CEN_Msk (0x40UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC3_CEN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_DFF_C_Pos (7UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC3_DFF_C (Bit 7) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_DFF_C_Msk (0x80UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC3_DFF_C (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_CEN_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC0_CEN (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_CEN_Msk (0x100UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC0_CEN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_DFF_C_Pos (9UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC0_DFF_C (Bit 9) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_DFF_C_Msk (0x200UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC0_DFF_C (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_CEN_Pos (10UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC1_CEN (Bit 10) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_CEN_Msk (0x400UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC1_CEN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_DFF_C_Pos (11UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC1_DFF_C (Bit 11) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_DFF_C_Msk (0x800UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC1_DFF_C (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_CEN_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC2_CEN (Bit 12) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_CEN_Msk (0x1000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC2_CEN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_DFF_C_Pos (13UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC2_DFF_C (Bit 13) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_DFF_C_Msk (0x2000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC2_DFF_C (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_CEN_Pos (14UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC3_CEN (Bit 14) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_CEN_Msk (0x4000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC3_CEN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_DFF_C_Pos (15UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC3_DFF_C (Bit 15) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_DFF_C_Msk (0x8000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC3_DFF_C (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_XORFB_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC0_XORFB (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC0_XORFB_Msk (0x30000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC0_XORFB (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_XORFB_Pos (18UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC1_XORFB (Bit 18) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC1_XORFB_Msk (0xc0000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC1_XORFB (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_XORFB_Pos (20UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC2_XORFB (Bit 20) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC2_XORFB_Msk (0x300000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC2_XORFB (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_XORFB_Pos (22UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC3_XORFB (Bit 22) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD0_MC3_XORFB_Msk (0xc00000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD0_MC3_XORFB (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_XORFB_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC0_XORFB (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC0_XORFB_Msk (0x3000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC0_XORFB (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_XORFB_Pos (26UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC1_XORFB (Bit 26) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC1_XORFB_Msk (0xc000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC1_XORFB (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_XORFB_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC2_XORFB (Bit 28) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC2_XORFB_Msk (0x30000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC2_XORFB (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_XORFB_Pos (30UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC3_XORFB (Bit 30) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG0_PLD1_MC3_XORFB_Msk (0xc0000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG0: PLD1_MC3_XORFB (Bitfield-Mask: 0x03)*/ +/* ============================================== UDB_UDBPAIR_UDBSNG.PLD_CFG1 ============================================== */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_SET_SEL_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC0_SET_SEL (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_SET_SEL_Msk (0x1UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC0_SET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_RESET_SEL_Pos (1UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC0_RESET_SEL (Bit 1) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_RESET_SEL_Msk (0x2UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC0_RESET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_SET_SEL_Pos (2UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC1_SET_SEL (Bit 2) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_SET_SEL_Msk (0x4UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC1_SET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_RESET_SEL_Pos (3UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC1_RESET_SEL (Bit 3) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_RESET_SEL_Msk (0x8UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC1_RESET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_SET_SEL_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC2_SET_SEL (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_SET_SEL_Msk (0x10UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC2_SET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_RESET_SEL_Pos (5UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC2_RESET_SEL (Bit 5) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_RESET_SEL_Msk (0x20UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC2_RESET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_SET_SEL_Pos (6UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC3_SET_SEL (Bit 6) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_SET_SEL_Msk (0x40UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC3_SET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_RESET_SEL_Pos (7UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC3_RESET_SEL (Bit 7) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_RESET_SEL_Msk (0x80UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC3_RESET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_SET_SEL_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC0_SET_SEL (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_SET_SEL_Msk (0x100UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC0_SET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_RESET_SEL_Pos (9UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC0_RESET_SEL (Bit 9) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_RESET_SEL_Msk (0x200UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC0_RESET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_SET_SEL_Pos (10UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC1_SET_SEL (Bit 10) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_SET_SEL_Msk (0x400UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC1_SET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_RESET_SEL_Pos (11UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC1_RESET_SEL (Bit 11)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_RESET_SEL_Msk (0x800UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC1_RESET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_SET_SEL_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC2_SET_SEL (Bit 12) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_SET_SEL_Msk (0x1000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC2_SET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_RESET_SEL_Pos (13UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC2_RESET_SEL (Bit 13)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_RESET_SEL_Msk (0x2000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC2_RESET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_SET_SEL_Pos (14UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC3_SET_SEL (Bit 14) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_SET_SEL_Msk (0x4000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC3_SET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_RESET_SEL_Pos (15UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC3_RESET_SEL (Bit 15)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_RESET_SEL_Msk (0x8000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC3_RESET_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_BYPASS_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC0_BYPASS (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC0_BYPASS_Msk (0x10000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC0_BYPASS (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_BYPASS_Pos (18UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC1_BYPASS (Bit 18) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC1_BYPASS_Msk (0x40000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC1_BYPASS (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_BYPASS_Pos (20UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC2_BYPASS (Bit 20) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC2_BYPASS_Msk (0x100000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC2_BYPASS (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_BYPASS_Pos (22UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC3_BYPASS (Bit 22) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD0_MC3_BYPASS_Msk (0x400000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD0_MC3_BYPASS (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_BYPASS_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC0_BYPASS (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC0_BYPASS_Msk (0x1000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC0_BYPASS (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_BYPASS_Pos (26UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC1_BYPASS (Bit 26) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC1_BYPASS_Msk (0x4000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC1_BYPASS (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_BYPASS_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC2_BYPASS (Bit 28) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC2_BYPASS_Msk (0x10000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC2_BYPASS (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_BYPASS_Pos (30UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC3_BYPASS (Bit 30) */ +#define UDB_UDBPAIR_UDBSNG_PLD_CFG1_PLD1_MC3_BYPASS_Msk (0x40000000UL) /*!< UDB_UDBPAIR_UDBSNG PLD_CFG1: PLD1_MC3_BYPASS (Bitfield-Mask: 0x01)*/ +/* ============================================= UDB_UDBPAIR_UDBSNG.DPATH_CFG0 ============================================= */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD0_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: RAD0 (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD0_Msk (0x7UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: RAD0 (Bitfield-Mask: 0x07) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD1_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: RAD1 (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD1_Msk (0x70UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: RAD1 (Bitfield-Mask: 0x07) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD2_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: RAD2 (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_RAD2_Msk (0x700UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: RAD2 (Bitfield-Mask: 0x07) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS0_Pos (11UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS0 (Bit 11) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS0_Msk (0x800UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS1_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS1 (Bit 12) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS1_Msk (0x1000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS2_Pos (13UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS2 (Bit 13) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS2_Msk (0x2000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS2 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS3_Pos (14UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS3 (Bit 14) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS3_Msk (0x4000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS3 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS4_Pos (15UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS4 (Bit 15) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS4_Msk (0x8000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS4 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F0_LD_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: F0_LD (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F0_LD_Msk (0x70000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: F0_LD (Bitfield-Mask: 0x07)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS5_Pos (19UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS5 (Bit 19) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_DP_RTE_BYPASS5_Msk (0x80000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: DP_RTE_BYPASS5 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F1_LD_Pos (20UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: F1_LD (Bit 20) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_F1_LD_Msk (0x700000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: F1_LD (Bitfield-Mask: 0x07)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D0_LD_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: D0_LD (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D0_LD_Msk (0x7000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: D0_LD (Bitfield-Mask: 0x07)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D1_LD_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: D1_LD (Bit 28) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG0_D1_LD_Msk (0x70000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG0: D1_LD (Bitfield-Mask: 0x07)*/ +/* ============================================= UDB_UDBPAIR_UDBSNG.DPATH_CFG1 ============================================= */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_SI_MUX_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: SI_MUX (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_SI_MUX_Msk (0x7UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: SI_MUX (Bitfield-Mask: 0x07)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_CI_MUX_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: CI_MUX (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_CI_MUX_Msk (0x70UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: CI_MUX (Bitfield-Mask: 0x07)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT0_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT0 (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT0_Msk (0xf00UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT0 (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT1_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT1 (Bit 12) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT1_Msk (0xf000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT1 (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT2_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT2 (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT2_Msk (0xf0000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT2 (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT3_Pos (20UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT3 (Bit 20) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT3_Msk (0xf00000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT3 (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT4_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT4 (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT4_Msk (0xf000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT4 (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT5_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT5 (Bit 28) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG1_OUT5_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG1: OUT5 (Bitfield-Mask: 0x0f) */ +/* ============================================= UDB_UDBPAIR_UDBSNG.DPATH_CFG2 ============================================= */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_OUT_SYNC_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG2: OUT_SYNC (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_OUT_SYNC_Msk (0x3fUL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG2: OUT_SYNC (Bitfield-Mask: 0x3f)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_AMASK_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG2: AMASK (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_AMASK_Msk (0xff00UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG2: AMASK (Bitfield-Mask: 0xff)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK0_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG2: CMASK0 (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK0_Msk (0xff0000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG2: CMASK0 (Bitfield-Mask: 0xff)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK1_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG2: CMASK1 (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG2_CMASK1_Msk (0xff000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG2: CMASK1 (Bitfield-Mask: 0xff)*/ +/* ============================================= UDB_UDBPAIR_UDBSNG.DPATH_CFG3 ============================================= */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELA_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: SI_SELA (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELA_Msk (0x3UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: SI_SELA (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELB_Pos (2UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: SI_SELB (Bit 2) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SI_SELB_Msk (0xcUL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: SI_SELB (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_DEF_SI_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: DEF_SI (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_DEF_SI_Msk (0x10UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: DEF_SI (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_AMASK_EN_Pos (5UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: AMASK_EN (Bit 5) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_AMASK_EN_Msk (0x20UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: AMASK_EN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK0_EN_Pos (6UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CMASK0_EN (Bit 6) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK0_EN_Msk (0x40UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CMASK0_EN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK1_EN_Pos (7UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CMASK1_EN (Bit 7) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMASK1_EN_Msk (0x80UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CMASK1_EN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELA_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CI_SELA (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELA_Msk (0x300UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CI_SELA (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELB_Pos (10UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CI_SELB (Bit 10) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CI_SELB_Msk (0xc00UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CI_SELB (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELA_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CMP_SELA (Bit 12) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELA_Msk (0x3000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CMP_SELA (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELB_Pos (14UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CMP_SELB (Bit 14) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CMP_SELB_Msk (0xc000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CMP_SELB (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN0_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CHAIN0 (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN0_Msk (0x10000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CHAIN0 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN1_Pos (17UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CHAIN1 (Bit 17) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN1_Msk (0x20000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CHAIN1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_FB_Pos (18UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CHAIN_FB (Bit 18) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_FB_Msk (0x40000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CHAIN_FB (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_CMSB_Pos (19UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CHAIN_CMSB (Bit 19) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_CHAIN_CMSB_Msk (0x80000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: CHAIN_CMSB (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SEL_Pos (20UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: MSB_SEL (Bit 20) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SEL_Msk (0x700000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: MSB_SEL (Bitfield-Mask: 0x07)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_EN_Pos (23UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: MSB_EN (Bit 23) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_EN_Msk (0x800000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: MSB_EN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F0_INSEL_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: F0_INSEL (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F0_INSEL_Msk (0x3000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: F0_INSEL (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F1_INSEL_Pos (26UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: F1_INSEL (Bit 26) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_F1_INSEL_Msk (0xc000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: F1_INSEL (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SI_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: MSB_SI (Bit 28) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_MSB_SI_Msk (0x10000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: MSB_SI (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_DYN_Pos (29UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: PI_DYN (Bit 29) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_DYN_Msk (0x20000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: PI_DYN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SHIFT_SEL_Pos (30UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: SHIFT_SEL (Bit 30) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_SHIFT_SEL_Msk (0x40000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: SHIFT_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_SEL_Pos (31UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: PI_SEL (Bit 31) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG3_PI_SEL_Msk (0x80000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG3: PI_SEL (Bitfield-Mask: 0x01)*/ +/* ============================================= UDB_UDBPAIR_UDBSNG.DPATH_CFG4 ============================================= */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_EXT_CRCPRS_Pos (1UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: EXT_CRCPRS (Bit 1) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_EXT_CRCPRS_Msk (0x2UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: EXT_CRCPRS (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ASYNC_Pos (2UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: FIFO_ASYNC (Bit 2) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ASYNC_Msk (0x4UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: FIFO_ASYNC (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_EDGE_Pos (3UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: FIFO_EDGE (Bit 3) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_EDGE_Msk (0x8UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: FIFO_EDGE (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_CAP_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: FIFO_CAP (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_CAP_Msk (0x10UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: FIFO_CAP (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_FAST_Pos (5UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: FIFO_FAST (Bit 5) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_FAST_Msk (0x20UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: FIFO_FAST (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_CK_INV_Pos (6UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: F0_CK_INV (Bit 6) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_CK_INV_Msk (0x40UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: F0_CK_INV (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_CK_INV_Pos (7UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: F1_CK_INV (Bit 7) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_CK_INV_Msk (0x80UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: F1_CK_INV (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_DYN_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: F0_DYN (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F0_DYN_Msk (0x100UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: F0_DYN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_DYN_Pos (9UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: F1_DYN (Bit 9) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_F1_DYN_Msk (0x200UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: F1_DYN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ADD_SYNC_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: FIFO_ADD_SYNC (Bit 12) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_CFG4_FIFO_ADD_SYNC_Msk (0x1000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_CFG4: FIFO_ADD_SYNC (Bitfield-Mask: 0x01)*/ +/* ============================================== UDB_UDBPAIR_UDBSNG.SC_CFG0 =============================================== */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD0_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: CTL_MD0 (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD0_Msk (0xffUL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: CTL_MD0 (Bitfield-Mask: 0xff) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD1_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: CTL_MD1 (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_CTL_MD1_Msk (0xff00UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: CTL_MD1 (Bitfield-Mask: 0xff) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_STAT_MD_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: STAT_MD (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_STAT_MD_Msk (0xff0000UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: STAT_MD (Bitfield-Mask: 0xff) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_OUT_CTL_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: SC_OUT_CTL (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_OUT_CTL_Msk (0x3000000UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: SC_OUT_CTL (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_INT_MD_Pos (26UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: SC_INT_MD (Bit 26) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_INT_MD_Msk (0x4000000UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: SC_INT_MD (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_SYNC_MD_Pos (27UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: SC_SYNC_MD (Bit 27) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_SYNC_MD_Msk (0x8000000UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: SC_SYNC_MD (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_EXT_RES_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: SC_EXT_RES (Bit 28) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG0_SC_EXT_RES_Msk (0x10000000UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG0: SC_EXT_RES (Bitfield-Mask: 0x01)*/ +/* ============================================== UDB_UDBPAIR_UDBSNG.SC_CFG1 =============================================== */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_LD_SEL_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG1: CNT_LD_SEL (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_LD_SEL_Msk (0x3UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG1: CNT_LD_SEL (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_EN_SEL_Pos (2UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG1: CNT_EN_SEL (Bit 2) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG1_CNT_EN_SEL_Msk (0xcUL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG1: CNT_EN_SEL (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_LD_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG1: ROUTE_LD (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_LD_Msk (0x10UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG1: ROUTE_LD (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_EN_Pos (5UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG1: ROUTE_EN (Bit 5) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ROUTE_EN_Msk (0x20UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG1: ROUTE_EN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ALT_CNT_Pos (6UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG1: ALT_CNT (Bit 6) */ +#define UDB_UDBPAIR_UDBSNG_SC_CFG1_ALT_CNT_Msk (0x40UL) /*!< UDB_UDBPAIR_UDBSNG SC_CFG1: ALT_CNT (Bitfield-Mask: 0x01) */ +/* ============================================== UDB_UDBPAIR_UDBSNG.RC_CFG0 =============================================== */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_SEL_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_EN_SEL (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_SEL_Msk (0x3UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_EN_SEL (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_MODE_Pos (2UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_EN_MODE (Bit 2) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_MODE_Msk (0xcUL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_EN_MODE (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_INV_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_EN_INV (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_EN_INV_Msk (0x10UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_EN_INV (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_INV_Pos (5UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_INV (Bit 5) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_INV_Msk (0x20UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_INV (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL0_OR_FRES_Pos (6UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_RES_SEL0_OR_FRES (Bit 6)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL0_OR_FRES_Msk (0x40UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_RES_SEL0_OR_FRES (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL1_Pos (7UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_RES_SEL1 (Bit 7) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD0_RC_RES_SEL1_Msk (0x80UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD0_RC_RES_SEL1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_SEL_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD1_RC_EN_SEL (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_SEL_Msk (0x300UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD1_RC_EN_SEL (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_MODE_Pos (10UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD1_RC_EN_MODE (Bit 10) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_MODE_Msk (0xc00UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD1_RC_EN_MODE (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_INV_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD1_RC_EN_INV (Bit 12) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_EN_INV_Msk (0x1000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD1_RC_EN_INV (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_INV_Pos (13UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD1_RC_INV (Bit 13) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_INV_Msk (0x2000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD1_RC_INV (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_RES_SEL0_OR_FRES_Pos (14UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD1_RC_RES_SEL0_OR_FRES (Bit 14)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_PLD1_RC_RES_SEL0_OR_FRES_Msk (0x4000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: PLD1_RC_RES_SEL0_OR_FRES (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_SEL_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_EN_SEL (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_SEL_Msk (0x30000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_EN_SEL (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_MODE_Pos (18UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_EN_MODE (Bit 18) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_MODE_Msk (0xc0000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_EN_MODE (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_INV_Pos (20UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_EN_INV (Bit 20) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_EN_INV_Msk (0x100000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_EN_INV (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_INV_Pos (21UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_INV (Bit 21) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_INV_Msk (0x200000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_INV (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL0_OR_FRES_Pos (22UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_RES_SEL0_OR_FRES (Bit 22)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL0_OR_FRES_Msk (0x400000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_RES_SEL0_OR_FRES (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL1_Pos (23UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_RES_SEL1 (Bit 23) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_DP_RC_RES_SEL1_Msk (0x800000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: DP_RC_RES_SEL1 (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_SEL_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_EN_SEL (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_SEL_Msk (0x3000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_EN_SEL (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_MODE_Pos (26UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_EN_MODE (Bit 26) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_MODE_Msk (0xc000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_EN_MODE (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_INV_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_EN_INV (Bit 28) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_EN_INV_Msk (0x10000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_EN_INV (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_INV_Pos (29UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_INV (Bit 29) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_INV_Msk (0x20000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_INV (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL0_OR_FRES_Pos (30UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_RES_SEL0_OR_FRES (Bit 30)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL0_OR_FRES_Msk (0x40000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_RES_SEL0_OR_FRES (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL1_Pos (31UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_RES_SEL1 (Bit 31) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG0_SC_RC_RES_SEL1_Msk (0x80000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG0: SC_RC_RES_SEL1 (Bitfield-Mask: 0x01)*/ +/* ============================================== UDB_UDBPAIR_UDBSNG.RC_CFG1 =============================================== */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_CK_SEL_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: PLD0_CK_SEL (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_CK_SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: PLD0_CK_SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD1_CK_SEL_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: PLD1_CK_SEL (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD1_CK_SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: PLD1_CK_SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_CK_SEL_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: DP_CK_SEL (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_CK_SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: DP_CK_SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_CK_SEL_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: SC_CK_SEL (Bit 12) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_CK_SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: SC_CK_SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_SEL_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: RES_SEL (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_SEL_Msk (0x30000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: RES_SEL (Bitfield-Mask: 0x03) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_POL_Pos (18UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: RES_POL (Bit 18) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_RES_POL_Msk (0x40000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: RES_POL (Bitfield-Mask: 0x01) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_CNTCTL_Pos (19UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: EN_RES_CNTCTL (Bit 19) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_CNTCTL_Msk (0x80000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: EN_RES_CNTCTL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_RES_POL_Pos (22UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: DP_RES_POL (Bit 22) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_DP_RES_POL_Msk (0x400000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: DP_RES_POL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_RES_POL_Pos (23UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: SC_RES_POL (Bit 23) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_SC_RES_POL_Msk (0x800000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: SC_RES_POL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_ALT_RES_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: ALT_RES (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_ALT_RES_Msk (0x1000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: ALT_RES (Bitfield-Mask: 0x01) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_SYNC_Pos (25UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: EXT_SYNC (Bit 25) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_SYNC_Msk (0x2000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: EXT_SYNC (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_STAT_Pos (26UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: EN_RES_STAT (Bit 26) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_STAT_Msk (0x4000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: EN_RES_STAT (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_DP_Pos (27UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: EN_RES_DP (Bit 27) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EN_RES_DP_Msk (0x8000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: EN_RES_DP (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_CK_SEL_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: EXT_CK_SEL (Bit 28) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_EXT_CK_SEL_Msk (0x30000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: EXT_CK_SEL (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_RES_POL_Pos (30UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: PLD0_RES_POL (Bit 30) */ +#define UDB_UDBPAIR_UDBSNG_RC_CFG1_PLD0_RES_POL_Msk (0x40000000UL) /*!< UDB_UDBPAIR_UDBSNG RC_CFG1: PLD0_RES_POL (Bitfield-Mask: 0x01)*/ +/* ============================================= UDB_UDBPAIR_UDBSNG.DPATH_OPC ============================================== */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CMP_SEL_Pos (0UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_CMP_SEL (Bit 0) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CMP_SEL_Msk (0x1UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_CMP_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SI_SEL_Pos (1UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_SI_SEL (Bit 1) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SI_SEL_Msk (0x2UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_SI_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CI_SEL_Pos (2UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_CI_SEL (Bit 2) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CI_SEL_Msk (0x4UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_CI_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CFB_EN_Pos (3UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_CFB_EN (Bit 3) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_CFB_EN_Msk (0x8UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_CFB_EN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A1_WR_SRC_Pos (4UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_A1_WR_SRC (Bit 4) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A1_WR_SRC_Msk (0x30UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_A1_WR_SRC (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A0_WR_SRC_Pos (6UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_A0_WR_SRC (Bit 6) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_A0_WR_SRC_Msk (0xc0UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_A0_WR_SRC (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SHIFT_Pos (8UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_SHIFT (Bit 8) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SHIFT_Msk (0x300UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_SHIFT (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_B_Pos (10UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_SRC_B (Bit 10) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_B_Msk (0xc00UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_SRC_B (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_A_Pos (12UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_SRC_A (Bit 12) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_SRC_A_Msk (0x1000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_SRC_A (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_FUNC_Pos (13UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_FUNC (Bit 13) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC0_FUNC_Msk (0xe000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC0_FUNC (Bitfield-Mask: 0x07)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CMP_SEL_Pos (16UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_CMP_SEL (Bit 16) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CMP_SEL_Msk (0x10000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_CMP_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SI_SEL_Pos (17UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_SI_SEL (Bit 17) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SI_SEL_Msk (0x20000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_SI_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CI_SEL_Pos (18UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_CI_SEL (Bit 18) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CI_SEL_Msk (0x40000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_CI_SEL (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CFB_EN_Pos (19UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_CFB_EN (Bit 19) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_CFB_EN_Msk (0x80000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_CFB_EN (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A1_WR_SRC_Pos (20UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_A1_WR_SRC (Bit 20) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A1_WR_SRC_Msk (0x300000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_A1_WR_SRC (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A0_WR_SRC_Pos (22UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_A0_WR_SRC (Bit 22) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_A0_WR_SRC_Msk (0xc00000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_A0_WR_SRC (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SHIFT_Pos (24UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_SHIFT (Bit 24) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SHIFT_Msk (0x3000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_SHIFT (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_B_Pos (26UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_SRC_B (Bit 26) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_B_Msk (0xc000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_SRC_B (Bitfield-Mask: 0x03)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_A_Pos (28UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_SRC_A (Bit 28) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_SRC_A_Msk (0x10000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_SRC_A (Bitfield-Mask: 0x01)*/ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_FUNC_Pos (29UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_FUNC (Bit 29) */ +#define UDB_UDBPAIR_UDBSNG_DPATH_OPC_OPC1_FUNC_Msk (0xe0000000UL) /*!< UDB_UDBPAIR_UDBSNG DPATH_OPC: OPC1_FUNC (Bitfield-Mask: 0x07)*/ + + +/* ============================================== UDB_UDBPAIR_ROUTE.TOP_V_BOT ============================================== */ +#define UDB_UDBPAIR_ROUTE_TOP_V_BOT_TOP_V_BOT_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE TOP_V_BOT: TOP_V_BOT (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_TOP_V_BOT_TOP_V_BOT_Msk (0xffffffffUL) /*!< UDB_UDBPAIR_ROUTE TOP_V_BOT: TOP_V_BOT (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LVI1_V_2 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LVI1_V_2_LVI1_V_2_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LVI1_V_2: LVI1_V_2 (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LVI1_V_2_LVI1_V_2_Msk (0xffffffffUL) /*!< UDB_UDBPAIR_ROUTE LVI1_V_2: LVI1_V_2 (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.RVI1_V_2 =============================================== */ +#define UDB_UDBPAIR_ROUTE_RVI1_V_2_RVI1_V_2_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE RVI1_V_2: RVI1_V_2 (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_RVI1_V_2_RVI1_V_2_Msk (0xffffffffUL) /*!< UDB_UDBPAIR_ROUTE RVI1_V_2: RVI1_V_2 (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.TUI_CFG0 =============================================== */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI0SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI0SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI0SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI0SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI1SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI1SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI1SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI1SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI2SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI2SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI2SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI2SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI3SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI3SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI3SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI3SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI4SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI4SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI4SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI4SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI5SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI5SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI5SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI5SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI6SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI6SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI6SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI6SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI7SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI7SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG0_TUI7SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG0: TUI7SEL (Bitfield-Mask: 0x0f) */ +/* ============================================== UDB_UDBPAIR_ROUTE.TUI_CFG1 =============================================== */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI8SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI8SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI8SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI8SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI9SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI9SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI9SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI9SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI10SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI10SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI10SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI10SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI11SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI11SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI11SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI11SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI12SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI12SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI12SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI12SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI13SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI13SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI13SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI13SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI14SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI14SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI14SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI14SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI15SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI15SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG1_TUI15SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG1: TUI15SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.TUI_CFG2 =============================================== */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI16SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI16SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI16SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI16SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI17SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI17SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI17SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI17SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI18SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI18SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI18SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI18SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI19SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI19SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI19SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI19SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI20SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI20SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI20SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI20SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI21SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI21SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI21SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI21SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI22SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI22SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI22SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI22SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI23SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI23SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG2_TUI23SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG2: TUI23SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.TUI_CFG3 =============================================== */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI24SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI24SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI24SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI24SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI25SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI25SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI25SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI25SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI26SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI26SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI26SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI26SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI27SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI27SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI27SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI27SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI28SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI28SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI28SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI28SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI29SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI29SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI29SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI29SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI30SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI30SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI30SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI30SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI31SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI31SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG3_TUI31SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG3: TUI31SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.TUI_CFG4 =============================================== */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI32SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI32SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI32SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI32SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI33SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI33SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI33SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI33SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI34SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI34SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI34SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI34SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI35SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI35SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI35SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI35SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI36SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI36SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI36SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI36SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI37SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI37SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI37SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI37SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI38SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI38SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI38SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI38SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI39SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI39SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG4_TUI39SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG4: TUI39SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.TUI_CFG5 =============================================== */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI40SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG5: TUI40SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI40SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG5: TUI40SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI41SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG5: TUI41SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_TUI_CFG5_TUI41SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE TUI_CFG5: TUI41SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.BUI_CFG0 =============================================== */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI0SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI0SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI0SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI0SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI1SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI1SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI1SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI1SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI2SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI2SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI2SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI2SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI3SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI3SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI3SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI3SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI4SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI4SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI4SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI4SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI5SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI5SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI5SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI5SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI6SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI6SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI6SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI6SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI7SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI7SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG0_BUI7SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG0: BUI7SEL (Bitfield-Mask: 0x0f) */ +/* ============================================== UDB_UDBPAIR_ROUTE.BUI_CFG1 =============================================== */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI8SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI8SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI8SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI8SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI9SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI9SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI9SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI9SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI10SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI10SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI10SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI10SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI11SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI11SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI11SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI11SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI12SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI12SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI12SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI12SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI13SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI13SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI13SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI13SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI14SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI14SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI14SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI14SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI15SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI15SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG1_BUI15SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG1: BUI15SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.BUI_CFG2 =============================================== */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI16SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI16SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI16SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI16SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI17SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI17SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI17SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI17SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI18SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI18SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI18SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI18SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI19SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI19SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI19SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI19SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI20SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI20SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI20SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI20SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI21SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI21SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI21SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI21SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI22SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI22SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI22SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI22SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI23SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI23SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG2_BUI23SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG2: BUI23SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.BUI_CFG3 =============================================== */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI24SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI24SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI24SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI24SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI25SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI25SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI25SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI25SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI26SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI26SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI26SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI26SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI27SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI27SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI27SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI27SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI28SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI28SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI28SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI28SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI29SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI29SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI29SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI29SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI30SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI30SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI30SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI30SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI31SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI31SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG3_BUI31SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG3: BUI31SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.BUI_CFG4 =============================================== */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI32SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI32SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI32SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI32SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI33SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI33SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI33SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI33SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI34SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI34SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI34SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI34SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI35SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI35SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI35SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI35SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI36SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI36SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI36SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI36SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI37SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI37SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI37SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI37SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI38SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI38SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI38SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI38SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI39SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI39SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG4_BUI39SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG4: BUI39SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.BUI_CFG5 =============================================== */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI40SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG5: BUI40SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI40SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG5: BUI40SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI41SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG5: BUI41SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_BUI_CFG5_BUI41SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE BUI_CFG5: BUI41SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.RVO_CFG0 =============================================== */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO0SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG0: RVO0SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO0SEL_Msk (0x1fUL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG0: RVO0SEL (Bitfield-Mask: 0x1f) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO1SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG0: RVO1SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO1SEL_Msk (0x1f00UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG0: RVO1SEL (Bitfield-Mask: 0x1f) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO2SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG0: RVO2SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO2SEL_Msk (0x1f0000UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG0: RVO2SEL (Bitfield-Mask: 0x1f) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO3SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG0: RVO3SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG0_RVO3SEL_Msk (0x1f000000UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG0: RVO3SEL (Bitfield-Mask: 0x1f) */ +/* ============================================== UDB_UDBPAIR_ROUTE.RVO_CFG1 =============================================== */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO4SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG1: RVO4SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO4SEL_Msk (0x1fUL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG1: RVO4SEL (Bitfield-Mask: 0x1f) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO5SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG1: RVO5SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO5SEL_Msk (0x1f00UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG1: RVO5SEL (Bitfield-Mask: 0x1f) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO6SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG1: RVO6SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO6SEL_Msk (0x1f0000UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG1: RVO6SEL (Bitfield-Mask: 0x1f) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO7SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG1: RVO7SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG1_RVO7SEL_Msk (0x1f000000UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG1: RVO7SEL (Bitfield-Mask: 0x1f) */ +/* ============================================== UDB_UDBPAIR_ROUTE.RVO_CFG2 =============================================== */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO8SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG2: RVO8SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO8SEL_Msk (0x1fUL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG2: RVO8SEL (Bitfield-Mask: 0x1f) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO9SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG2: RVO9SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO9SEL_Msk (0x1f00UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG2: RVO9SEL (Bitfield-Mask: 0x1f) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO10SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG2: RVO10SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO10SEL_Msk (0x1f0000UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG2: RVO10SEL (Bitfield-Mask: 0x1f)*/ +#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO11SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG2: RVO11SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG2_RVO11SEL_Msk (0x1f000000UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG2: RVO11SEL (Bitfield-Mask: 0x1f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.RVO_CFG3 =============================================== */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO12SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG3: RVO12SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO12SEL_Msk (0x1fUL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG3: RVO12SEL (Bitfield-Mask: 0x1f)*/ +#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO13SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG3: RVO13SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO13SEL_Msk (0x1f00UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG3: RVO13SEL (Bitfield-Mask: 0x1f)*/ +#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO14SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG3: RVO14SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO14SEL_Msk (0x1f0000UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG3: RVO14SEL (Bitfield-Mask: 0x1f)*/ +#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO15SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG3: RVO15SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_RVO_CFG3_RVO15SEL_Msk (0x1f000000UL) /*!< UDB_UDBPAIR_ROUTE RVO_CFG3: RVO15SEL (Bitfield-Mask: 0x1f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LVO_CFG0 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO0SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO0SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO0SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO0SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO1SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO1SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO1SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO1SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO2SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO2SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO2SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO2SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO3SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO3SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO3SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO3SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO4SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO4SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO4SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO4SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO5SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO5SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO5SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO5SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO6SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO6SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO6SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO6SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO7SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO7SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG0_LVO7SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG0: LVO7SEL (Bitfield-Mask: 0x0f) */ +/* ============================================== UDB_UDBPAIR_ROUTE.LVO_CFG1 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO8SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO8SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO8SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO8SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO9SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO9SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO9SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO9SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO10SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO10SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO10SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO10SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO11SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO11SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO11SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO11SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO12SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO12SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO12SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO12SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO13SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO13SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO13SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO13SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO14SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO14SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO14SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO14SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO15SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO15SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LVO_CFG1_LVO15SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LVO_CFG1: LVO15SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.RHO_CFG0 =============================================== */ +#define UDB_UDBPAIR_ROUTE_RHO_CFG0_RHOSEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE RHO_CFG0: RHOSEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_RHO_CFG0_RHOSEL_Msk (0xffffffffUL) /*!< UDB_UDBPAIR_ROUTE RHO_CFG0: RHOSEL (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.RHO_CFG1 =============================================== */ +#define UDB_UDBPAIR_ROUTE_RHO_CFG1_RHOSEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE RHO_CFG1: RHOSEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_RHO_CFG1_RHOSEL_Msk (0xffffffffUL) /*!< UDB_UDBPAIR_ROUTE RHO_CFG1: RHOSEL (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.RHO_CFG2 =============================================== */ +#define UDB_UDBPAIR_ROUTE_RHO_CFG2_RHOSEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE RHO_CFG2: RHOSEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_RHO_CFG2_RHOSEL_Msk (0xffffffffUL) /*!< UDB_UDBPAIR_ROUTE RHO_CFG2: RHOSEL (Bitfield-Mask: 0xffffffff)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG0 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO0SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO0SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO0SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO0SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO1SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO1SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO1SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO1SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO2SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO2SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO2SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO2SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO3SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO3SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO3SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO3SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO4SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO4SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO4SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO4SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO5SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO5SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO5SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO5SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO6SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO6SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO6SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO6SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO7SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO7SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG0_LHO7SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG0: LHO7SEL (Bitfield-Mask: 0x0f) */ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG1 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO8SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO8SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO8SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO8SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO9SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO9SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO9SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO9SEL (Bitfield-Mask: 0x0f) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO10SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO10SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO10SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO10SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO11SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO11SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO11SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO11SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO12SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO12SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO12SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO12SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO13SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO13SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO13SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO13SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO14SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO14SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO14SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO14SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO15SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO15SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG1_LHO15SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG1: LHO15SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG2 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO16SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO16SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO16SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO16SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO17SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO17SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO17SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO17SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO18SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO18SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO18SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO18SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO19SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO19SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO19SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO19SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO20SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO20SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO20SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO20SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO21SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO21SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO21SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO21SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO22SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO22SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO22SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO22SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO23SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO23SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG2_LHO23SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG2: LHO23SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG3 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO24SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO24SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO24SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO24SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO25SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO25SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO25SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO25SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO26SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO26SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO26SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO26SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO27SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO27SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO27SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO27SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO28SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO28SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO28SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO28SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO29SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO29SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO29SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO29SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO30SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO30SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO30SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO30SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO31SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO31SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG3_LHO31SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG3: LHO31SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG4 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO32SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO32SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO32SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO32SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO33SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO33SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO33SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO33SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO34SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO34SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO34SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO34SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO35SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO35SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO35SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO35SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO36SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO36SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO36SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO36SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO37SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO37SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO37SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO37SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO38SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO38SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO38SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO38SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO39SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO39SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG4_LHO39SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG4: LHO39SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG5 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO40SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO40SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO40SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO40SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO41SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO41SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO41SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO41SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO42SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO42SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO42SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO42SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO43SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO43SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO43SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO43SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO44SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO44SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO44SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO44SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO45SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO45SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO45SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO45SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO46SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO46SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO46SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO46SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO47SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO47SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG5_LHO47SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG5: LHO47SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG6 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO48SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO48SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO48SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO48SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO49SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO49SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO49SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO49SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO50SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO50SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO50SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO50SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO51SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO51SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO51SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO51SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO52SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO52SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO52SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO52SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO53SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO53SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO53SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO53SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO54SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO54SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO54SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO54SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO55SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO55SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG6_LHO55SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG6: LHO55SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG7 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO56SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO56SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO56SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO56SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO57SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO57SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO57SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO57SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO58SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO58SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO58SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO58SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO59SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO59SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO59SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO59SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO60SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO60SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO60SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO60SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO61SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO61SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO61SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO61SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO62SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO62SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO62SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO62SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO63SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO63SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG7_LHO63SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG7: LHO63SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG8 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO64SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO64SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO64SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO64SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO65SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO65SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO65SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO65SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO66SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO66SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO66SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO66SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO67SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO67SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO67SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO67SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO68SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO68SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO68SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO68SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO69SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO69SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO69SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO69SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO70SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO70SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO70SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO70SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO71SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO71SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG8_LHO71SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG8: LHO71SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG9 =============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO72SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO72SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO72SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO72SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO73SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO73SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO73SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO73SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO74SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO74SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO74SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO74SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO75SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO75SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO75SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO75SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO76SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO76SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO76SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO76SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO77SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO77SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO77SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO77SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO78SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO78SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO78SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO78SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO79SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO79SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG9_LHO79SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG9: LHO79SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG10 ============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO80SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO80SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO80SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO80SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO81SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO81SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO81SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO81SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO82SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO82SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO82SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO82SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO83SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO83SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO83SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO83SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO84SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO84SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO84SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO84SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO85SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO85SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO85SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO85SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO86SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO86SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO86SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO86SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO87SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO87SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG10_LHO87SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG10: LHO87SEL (Bitfield-Mask: 0x0f)*/ +/* ============================================== UDB_UDBPAIR_ROUTE.LHO_CFG11 ============================================== */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO88SEL_Pos (0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO88SEL (Bit 0) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO88SEL_Msk (0xfUL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO88SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO89SEL_Pos (4UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO89SEL (Bit 4) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO89SEL_Msk (0xf0UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO89SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO90SEL_Pos (8UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO90SEL (Bit 8) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO90SEL_Msk (0xf00UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO90SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO91SEL_Pos (12UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO91SEL (Bit 12) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO91SEL_Msk (0xf000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO91SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO92SEL_Pos (16UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO92SEL (Bit 16) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO92SEL_Msk (0xf0000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO92SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO93SEL_Pos (20UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO93SEL (Bit 20) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO93SEL_Msk (0xf00000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO93SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO94SEL_Pos (24UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO94SEL (Bit 24) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO94SEL_Msk (0xf000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO94SEL (Bitfield-Mask: 0x0f)*/ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO95SEL_Pos (28UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO95SEL (Bit 28) */ +#define UDB_UDBPAIR_ROUTE_LHO_CFG11_LHO95SEL_Msk (0xf0000000UL) /*!< UDB_UDBPAIR_ROUTE LHO_CFG11: LHO95SEL (Bitfield-Mask: 0x0f)*/ + + +/* =================================================== UDB_DSI.LVI1_V_2 ==================================================== */ +#define UDB_DSI_LVI1_V_2_LVI1_V_2_Pos (0UL) /*!< UDB_DSI LVI1_V_2: LVI1_V_2 (Bit 0) */ +#define UDB_DSI_LVI1_V_2_LVI1_V_2_Msk (0xffffffffUL) /*!< UDB_DSI LVI1_V_2: LVI1_V_2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== UDB_DSI.RVI1_V_2 ==================================================== */ +#define UDB_DSI_RVI1_V_2_RVI1_V_2_Pos (0UL) /*!< UDB_DSI RVI1_V_2: RVI1_V_2 (Bit 0) */ +#define UDB_DSI_RVI1_V_2_RVI1_V_2_Msk (0xffffffffUL) /*!< UDB_DSI RVI1_V_2: RVI1_V_2 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== UDB_DSI.DOP_CFG0 ==================================================== */ +#define UDB_DSI_DOP_CFG0_DOP0SEL_Pos (0UL) /*!< UDB_DSI DOP_CFG0: DOP0SEL (Bit 0) */ +#define UDB_DSI_DOP_CFG0_DOP0SEL_Msk (0x1fUL) /*!< UDB_DSI DOP_CFG0: DOP0SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG0_DOP1SEL_Pos (8UL) /*!< UDB_DSI DOP_CFG0: DOP1SEL (Bit 8) */ +#define UDB_DSI_DOP_CFG0_DOP1SEL_Msk (0x1f00UL) /*!< UDB_DSI DOP_CFG0: DOP1SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG0_DOP2SEL_Pos (16UL) /*!< UDB_DSI DOP_CFG0: DOP2SEL (Bit 16) */ +#define UDB_DSI_DOP_CFG0_DOP2SEL_Msk (0x1f0000UL) /*!< UDB_DSI DOP_CFG0: DOP2SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG0_DOP3SEL_Pos (24UL) /*!< UDB_DSI DOP_CFG0: DOP3SEL (Bit 24) */ +#define UDB_DSI_DOP_CFG0_DOP3SEL_Msk (0x1f000000UL) /*!< UDB_DSI DOP_CFG0: DOP3SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.DOP_CFG1 ==================================================== */ +#define UDB_DSI_DOP_CFG1_DOP4SEL_Pos (0UL) /*!< UDB_DSI DOP_CFG1: DOP4SEL (Bit 0) */ +#define UDB_DSI_DOP_CFG1_DOP4SEL_Msk (0x1fUL) /*!< UDB_DSI DOP_CFG1: DOP4SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG1_DOP5SEL_Pos (8UL) /*!< UDB_DSI DOP_CFG1: DOP5SEL (Bit 8) */ +#define UDB_DSI_DOP_CFG1_DOP5SEL_Msk (0x1f00UL) /*!< UDB_DSI DOP_CFG1: DOP5SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG1_DOP6SEL_Pos (16UL) /*!< UDB_DSI DOP_CFG1: DOP6SEL (Bit 16) */ +#define UDB_DSI_DOP_CFG1_DOP6SEL_Msk (0x1f0000UL) /*!< UDB_DSI DOP_CFG1: DOP6SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG1_DOP7SEL_Pos (24UL) /*!< UDB_DSI DOP_CFG1: DOP7SEL (Bit 24) */ +#define UDB_DSI_DOP_CFG1_DOP7SEL_Msk (0x1f000000UL) /*!< UDB_DSI DOP_CFG1: DOP7SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.DOP_CFG2 ==================================================== */ +#define UDB_DSI_DOP_CFG2_DOP8SEL_Pos (0UL) /*!< UDB_DSI DOP_CFG2: DOP8SEL (Bit 0) */ +#define UDB_DSI_DOP_CFG2_DOP8SEL_Msk (0x1fUL) /*!< UDB_DSI DOP_CFG2: DOP8SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG2_DOP9SEL_Pos (8UL) /*!< UDB_DSI DOP_CFG2: DOP9SEL (Bit 8) */ +#define UDB_DSI_DOP_CFG2_DOP9SEL_Msk (0x1f00UL) /*!< UDB_DSI DOP_CFG2: DOP9SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG2_DOP10SEL_Pos (16UL) /*!< UDB_DSI DOP_CFG2: DOP10SEL (Bit 16) */ +#define UDB_DSI_DOP_CFG2_DOP10SEL_Msk (0x1f0000UL) /*!< UDB_DSI DOP_CFG2: DOP10SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG2_DOP11SEL_Pos (24UL) /*!< UDB_DSI DOP_CFG2: DOP11SEL (Bit 24) */ +#define UDB_DSI_DOP_CFG2_DOP11SEL_Msk (0x1f000000UL) /*!< UDB_DSI DOP_CFG2: DOP11SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.DOP_CFG3 ==================================================== */ +#define UDB_DSI_DOP_CFG3_DOP12SEL_Pos (0UL) /*!< UDB_DSI DOP_CFG3: DOP12SEL (Bit 0) */ +#define UDB_DSI_DOP_CFG3_DOP12SEL_Msk (0x1fUL) /*!< UDB_DSI DOP_CFG3: DOP12SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG3_DOP13SEL_Pos (8UL) /*!< UDB_DSI DOP_CFG3: DOP13SEL (Bit 8) */ +#define UDB_DSI_DOP_CFG3_DOP13SEL_Msk (0x1f00UL) /*!< UDB_DSI DOP_CFG3: DOP13SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG3_DOP14SEL_Pos (16UL) /*!< UDB_DSI DOP_CFG3: DOP14SEL (Bit 16) */ +#define UDB_DSI_DOP_CFG3_DOP14SEL_Msk (0x1f0000UL) /*!< UDB_DSI DOP_CFG3: DOP14SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOP_CFG3_DOP15SEL_Pos (24UL) /*!< UDB_DSI DOP_CFG3: DOP15SEL (Bit 24) */ +#define UDB_DSI_DOP_CFG3_DOP15SEL_Msk (0x1f000000UL) /*!< UDB_DSI DOP_CFG3: DOP15SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.DOT_CFG0 ==================================================== */ +#define UDB_DSI_DOT_CFG0_DOT0SEL_Pos (0UL) /*!< UDB_DSI DOT_CFG0: DOT0SEL (Bit 0) */ +#define UDB_DSI_DOT_CFG0_DOT0SEL_Msk (0x1fUL) /*!< UDB_DSI DOT_CFG0: DOT0SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG0_DOT1SEL_Pos (8UL) /*!< UDB_DSI DOT_CFG0: DOT1SEL (Bit 8) */ +#define UDB_DSI_DOT_CFG0_DOT1SEL_Msk (0x1f00UL) /*!< UDB_DSI DOT_CFG0: DOT1SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG0_DOT2SEL_Pos (16UL) /*!< UDB_DSI DOT_CFG0: DOT2SEL (Bit 16) */ +#define UDB_DSI_DOT_CFG0_DOT2SEL_Msk (0x1f0000UL) /*!< UDB_DSI DOT_CFG0: DOT2SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG0_DOT3SEL_Pos (24UL) /*!< UDB_DSI DOT_CFG0: DOT3SEL (Bit 24) */ +#define UDB_DSI_DOT_CFG0_DOT3SEL_Msk (0x1f000000UL) /*!< UDB_DSI DOT_CFG0: DOT3SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.DOT_CFG1 ==================================================== */ +#define UDB_DSI_DOT_CFG1_DOT4SEL_Pos (0UL) /*!< UDB_DSI DOT_CFG1: DOT4SEL (Bit 0) */ +#define UDB_DSI_DOT_CFG1_DOT4SEL_Msk (0x1fUL) /*!< UDB_DSI DOT_CFG1: DOT4SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG1_DOT5SEL_Pos (8UL) /*!< UDB_DSI DOT_CFG1: DOT5SEL (Bit 8) */ +#define UDB_DSI_DOT_CFG1_DOT5SEL_Msk (0x1f00UL) /*!< UDB_DSI DOT_CFG1: DOT5SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG1_DOT6SEL_Pos (16UL) /*!< UDB_DSI DOT_CFG1: DOT6SEL (Bit 16) */ +#define UDB_DSI_DOT_CFG1_DOT6SEL_Msk (0x1f0000UL) /*!< UDB_DSI DOT_CFG1: DOT6SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG1_DOT7SEL_Pos (24UL) /*!< UDB_DSI DOT_CFG1: DOT7SEL (Bit 24) */ +#define UDB_DSI_DOT_CFG1_DOT7SEL_Msk (0x1f000000UL) /*!< UDB_DSI DOT_CFG1: DOT7SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.DOT_CFG2 ==================================================== */ +#define UDB_DSI_DOT_CFG2_DOT8SEL_Pos (0UL) /*!< UDB_DSI DOT_CFG2: DOT8SEL (Bit 0) */ +#define UDB_DSI_DOT_CFG2_DOT8SEL_Msk (0x1fUL) /*!< UDB_DSI DOT_CFG2: DOT8SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG2_DOT9SEL_Pos (8UL) /*!< UDB_DSI DOT_CFG2: DOT9SEL (Bit 8) */ +#define UDB_DSI_DOT_CFG2_DOT9SEL_Msk (0x1f00UL) /*!< UDB_DSI DOT_CFG2: DOT9SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG2_DOT10SEL_Pos (16UL) /*!< UDB_DSI DOT_CFG2: DOT10SEL (Bit 16) */ +#define UDB_DSI_DOT_CFG2_DOT10SEL_Msk (0x1f0000UL) /*!< UDB_DSI DOT_CFG2: DOT10SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG2_DOT11SEL_Pos (24UL) /*!< UDB_DSI DOT_CFG2: DOT11SEL (Bit 24) */ +#define UDB_DSI_DOT_CFG2_DOT11SEL_Msk (0x1f000000UL) /*!< UDB_DSI DOT_CFG2: DOT11SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.DOT_CFG3 ==================================================== */ +#define UDB_DSI_DOT_CFG3_DOT12SEL_Pos (0UL) /*!< UDB_DSI DOT_CFG3: DOT12SEL (Bit 0) */ +#define UDB_DSI_DOT_CFG3_DOT12SEL_Msk (0x1fUL) /*!< UDB_DSI DOT_CFG3: DOT12SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG3_DOT13SEL_Pos (8UL) /*!< UDB_DSI DOT_CFG3: DOT13SEL (Bit 8) */ +#define UDB_DSI_DOT_CFG3_DOT13SEL_Msk (0x1f00UL) /*!< UDB_DSI DOT_CFG3: DOT13SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG3_DOT14SEL_Pos (16UL) /*!< UDB_DSI DOT_CFG3: DOT14SEL (Bit 16) */ +#define UDB_DSI_DOT_CFG3_DOT14SEL_Msk (0x1f0000UL) /*!< UDB_DSI DOT_CFG3: DOT14SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_DOT_CFG3_DOT15SEL_Pos (24UL) /*!< UDB_DSI DOT_CFG3: DOT15SEL (Bit 24) */ +#define UDB_DSI_DOT_CFG3_DOT15SEL_Msk (0x1f000000UL) /*!< UDB_DSI DOT_CFG3: DOT15SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.RVO_CFG0 ==================================================== */ +#define UDB_DSI_RVO_CFG0_RVO0SEL_Pos (0UL) /*!< UDB_DSI RVO_CFG0: RVO0SEL (Bit 0) */ +#define UDB_DSI_RVO_CFG0_RVO0SEL_Msk (0x1fUL) /*!< UDB_DSI RVO_CFG0: RVO0SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG0_RVO1SEL_Pos (8UL) /*!< UDB_DSI RVO_CFG0: RVO1SEL (Bit 8) */ +#define UDB_DSI_RVO_CFG0_RVO1SEL_Msk (0x1f00UL) /*!< UDB_DSI RVO_CFG0: RVO1SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG0_RVO2SEL_Pos (16UL) /*!< UDB_DSI RVO_CFG0: RVO2SEL (Bit 16) */ +#define UDB_DSI_RVO_CFG0_RVO2SEL_Msk (0x1f0000UL) /*!< UDB_DSI RVO_CFG0: RVO2SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG0_RVO3SEL_Pos (24UL) /*!< UDB_DSI RVO_CFG0: RVO3SEL (Bit 24) */ +#define UDB_DSI_RVO_CFG0_RVO3SEL_Msk (0x1f000000UL) /*!< UDB_DSI RVO_CFG0: RVO3SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.RVO_CFG1 ==================================================== */ +#define UDB_DSI_RVO_CFG1_RVO4SEL_Pos (0UL) /*!< UDB_DSI RVO_CFG1: RVO4SEL (Bit 0) */ +#define UDB_DSI_RVO_CFG1_RVO4SEL_Msk (0x1fUL) /*!< UDB_DSI RVO_CFG1: RVO4SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG1_RVO5SEL_Pos (8UL) /*!< UDB_DSI RVO_CFG1: RVO5SEL (Bit 8) */ +#define UDB_DSI_RVO_CFG1_RVO5SEL_Msk (0x1f00UL) /*!< UDB_DSI RVO_CFG1: RVO5SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG1_RVO6SEL_Pos (16UL) /*!< UDB_DSI RVO_CFG1: RVO6SEL (Bit 16) */ +#define UDB_DSI_RVO_CFG1_RVO6SEL_Msk (0x1f0000UL) /*!< UDB_DSI RVO_CFG1: RVO6SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG1_RVO7SEL_Pos (24UL) /*!< UDB_DSI RVO_CFG1: RVO7SEL (Bit 24) */ +#define UDB_DSI_RVO_CFG1_RVO7SEL_Msk (0x1f000000UL) /*!< UDB_DSI RVO_CFG1: RVO7SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.RVO_CFG2 ==================================================== */ +#define UDB_DSI_RVO_CFG2_RVO8SEL_Pos (0UL) /*!< UDB_DSI RVO_CFG2: RVO8SEL (Bit 0) */ +#define UDB_DSI_RVO_CFG2_RVO8SEL_Msk (0x1fUL) /*!< UDB_DSI RVO_CFG2: RVO8SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG2_RVO9SEL_Pos (8UL) /*!< UDB_DSI RVO_CFG2: RVO9SEL (Bit 8) */ +#define UDB_DSI_RVO_CFG2_RVO9SEL_Msk (0x1f00UL) /*!< UDB_DSI RVO_CFG2: RVO9SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG2_RVO10SEL_Pos (16UL) /*!< UDB_DSI RVO_CFG2: RVO10SEL (Bit 16) */ +#define UDB_DSI_RVO_CFG2_RVO10SEL_Msk (0x1f0000UL) /*!< UDB_DSI RVO_CFG2: RVO10SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG2_RVO11SEL_Pos (24UL) /*!< UDB_DSI RVO_CFG2: RVO11SEL (Bit 24) */ +#define UDB_DSI_RVO_CFG2_RVO11SEL_Msk (0x1f000000UL) /*!< UDB_DSI RVO_CFG2: RVO11SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.RVO_CFG3 ==================================================== */ +#define UDB_DSI_RVO_CFG3_RVO12SEL_Pos (0UL) /*!< UDB_DSI RVO_CFG3: RVO12SEL (Bit 0) */ +#define UDB_DSI_RVO_CFG3_RVO12SEL_Msk (0x1fUL) /*!< UDB_DSI RVO_CFG3: RVO12SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG3_RVO13SEL_Pos (8UL) /*!< UDB_DSI RVO_CFG3: RVO13SEL (Bit 8) */ +#define UDB_DSI_RVO_CFG3_RVO13SEL_Msk (0x1f00UL) /*!< UDB_DSI RVO_CFG3: RVO13SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG3_RVO14SEL_Pos (16UL) /*!< UDB_DSI RVO_CFG3: RVO14SEL (Bit 16) */ +#define UDB_DSI_RVO_CFG3_RVO14SEL_Msk (0x1f0000UL) /*!< UDB_DSI RVO_CFG3: RVO14SEL (Bitfield-Mask: 0x1f) */ +#define UDB_DSI_RVO_CFG3_RVO15SEL_Pos (24UL) /*!< UDB_DSI RVO_CFG3: RVO15SEL (Bit 24) */ +#define UDB_DSI_RVO_CFG3_RVO15SEL_Msk (0x1f000000UL) /*!< UDB_DSI RVO_CFG3: RVO15SEL (Bitfield-Mask: 0x1f) */ +/* =================================================== UDB_DSI.LVO_CFG0 ==================================================== */ +#define UDB_DSI_LVO_CFG0_LVO0SEL_Pos (0UL) /*!< UDB_DSI LVO_CFG0: LVO0SEL (Bit 0) */ +#define UDB_DSI_LVO_CFG0_LVO0SEL_Msk (0xfUL) /*!< UDB_DSI LVO_CFG0: LVO0SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG0_LVO1SEL_Pos (4UL) /*!< UDB_DSI LVO_CFG0: LVO1SEL (Bit 4) */ +#define UDB_DSI_LVO_CFG0_LVO1SEL_Msk (0xf0UL) /*!< UDB_DSI LVO_CFG0: LVO1SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG0_LVO2SEL_Pos (8UL) /*!< UDB_DSI LVO_CFG0: LVO2SEL (Bit 8) */ +#define UDB_DSI_LVO_CFG0_LVO2SEL_Msk (0xf00UL) /*!< UDB_DSI LVO_CFG0: LVO2SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG0_LVO3SEL_Pos (12UL) /*!< UDB_DSI LVO_CFG0: LVO3SEL (Bit 12) */ +#define UDB_DSI_LVO_CFG0_LVO3SEL_Msk (0xf000UL) /*!< UDB_DSI LVO_CFG0: LVO3SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG0_LVO4SEL_Pos (16UL) /*!< UDB_DSI LVO_CFG0: LVO4SEL (Bit 16) */ +#define UDB_DSI_LVO_CFG0_LVO4SEL_Msk (0xf0000UL) /*!< UDB_DSI LVO_CFG0: LVO4SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG0_LVO5SEL_Pos (20UL) /*!< UDB_DSI LVO_CFG0: LVO5SEL (Bit 20) */ +#define UDB_DSI_LVO_CFG0_LVO5SEL_Msk (0xf00000UL) /*!< UDB_DSI LVO_CFG0: LVO5SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG0_LVO6SEL_Pos (24UL) /*!< UDB_DSI LVO_CFG0: LVO6SEL (Bit 24) */ +#define UDB_DSI_LVO_CFG0_LVO6SEL_Msk (0xf000000UL) /*!< UDB_DSI LVO_CFG0: LVO6SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG0_LVO7SEL_Pos (28UL) /*!< UDB_DSI LVO_CFG0: LVO7SEL (Bit 28) */ +#define UDB_DSI_LVO_CFG0_LVO7SEL_Msk (0xf0000000UL) /*!< UDB_DSI LVO_CFG0: LVO7SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LVO_CFG1 ==================================================== */ +#define UDB_DSI_LVO_CFG1_LVO8SEL_Pos (0UL) /*!< UDB_DSI LVO_CFG1: LVO8SEL (Bit 0) */ +#define UDB_DSI_LVO_CFG1_LVO8SEL_Msk (0xfUL) /*!< UDB_DSI LVO_CFG1: LVO8SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG1_LVO9SEL_Pos (4UL) /*!< UDB_DSI LVO_CFG1: LVO9SEL (Bit 4) */ +#define UDB_DSI_LVO_CFG1_LVO9SEL_Msk (0xf0UL) /*!< UDB_DSI LVO_CFG1: LVO9SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG1_LVO10SEL_Pos (8UL) /*!< UDB_DSI LVO_CFG1: LVO10SEL (Bit 8) */ +#define UDB_DSI_LVO_CFG1_LVO10SEL_Msk (0xf00UL) /*!< UDB_DSI LVO_CFG1: LVO10SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG1_LVO11SEL_Pos (12UL) /*!< UDB_DSI LVO_CFG1: LVO11SEL (Bit 12) */ +#define UDB_DSI_LVO_CFG1_LVO11SEL_Msk (0xf000UL) /*!< UDB_DSI LVO_CFG1: LVO11SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG1_LVO12SEL_Pos (16UL) /*!< UDB_DSI LVO_CFG1: LVO12SEL (Bit 16) */ +#define UDB_DSI_LVO_CFG1_LVO12SEL_Msk (0xf0000UL) /*!< UDB_DSI LVO_CFG1: LVO12SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG1_LVO13SEL_Pos (20UL) /*!< UDB_DSI LVO_CFG1: LVO13SEL (Bit 20) */ +#define UDB_DSI_LVO_CFG1_LVO13SEL_Msk (0xf00000UL) /*!< UDB_DSI LVO_CFG1: LVO13SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG1_LVO14SEL_Pos (24UL) /*!< UDB_DSI LVO_CFG1: LVO14SEL (Bit 24) */ +#define UDB_DSI_LVO_CFG1_LVO14SEL_Msk (0xf000000UL) /*!< UDB_DSI LVO_CFG1: LVO14SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LVO_CFG1_LVO15SEL_Pos (28UL) /*!< UDB_DSI LVO_CFG1: LVO15SEL (Bit 28) */ +#define UDB_DSI_LVO_CFG1_LVO15SEL_Msk (0xf0000000UL) /*!< UDB_DSI LVO_CFG1: LVO15SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.RHO_CFG0 ==================================================== */ +#define UDB_DSI_RHO_CFG0_RHOSEL_Pos (0UL) /*!< UDB_DSI RHO_CFG0: RHOSEL (Bit 0) */ +#define UDB_DSI_RHO_CFG0_RHOSEL_Msk (0xffffffffUL) /*!< UDB_DSI RHO_CFG0: RHOSEL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== UDB_DSI.RHO_CFG1 ==================================================== */ +#define UDB_DSI_RHO_CFG1_RHOSEL_Pos (0UL) /*!< UDB_DSI RHO_CFG1: RHOSEL (Bit 0) */ +#define UDB_DSI_RHO_CFG1_RHOSEL_Msk (0xffffffffUL) /*!< UDB_DSI RHO_CFG1: RHOSEL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== UDB_DSI.RHO_CFG2 ==================================================== */ +#define UDB_DSI_RHO_CFG2_RHOSEL_Pos (0UL) /*!< UDB_DSI RHO_CFG2: RHOSEL (Bit 0) */ +#define UDB_DSI_RHO_CFG2_RHOSEL_Msk (0xffffffffUL) /*!< UDB_DSI RHO_CFG2: RHOSEL (Bitfield-Mask: 0xffffffff) */ +/* =================================================== UDB_DSI.LHO_CFG0 ==================================================== */ +#define UDB_DSI_LHO_CFG0_LHO0SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG0: LHO0SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG0_LHO0SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG0: LHO0SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG0_LHO1SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG0: LHO1SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG0_LHO1SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG0: LHO1SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG0_LHO2SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG0: LHO2SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG0_LHO2SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG0: LHO2SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG0_LHO3SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG0: LHO3SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG0_LHO3SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG0: LHO3SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG0_LHO4SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG0: LHO4SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG0_LHO4SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG0: LHO4SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG0_LHO5SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG0: LHO5SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG0_LHO5SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG0: LHO5SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG0_LHO6SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG0: LHO6SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG0_LHO6SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG0: LHO6SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG0_LHO7SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG0: LHO7SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG0_LHO7SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG0: LHO7SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG1 ==================================================== */ +#define UDB_DSI_LHO_CFG1_LHO8SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG1: LHO8SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG1_LHO8SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG1: LHO8SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG1_LHO9SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG1: LHO9SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG1_LHO9SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG1: LHO9SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG1_LHO10SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG1: LHO10SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG1_LHO10SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG1: LHO10SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG1_LHO11SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG1: LHO11SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG1_LHO11SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG1: LHO11SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG1_LHO12SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG1: LHO12SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG1_LHO12SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG1: LHO12SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG1_LHO13SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG1: LHO13SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG1_LHO13SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG1: LHO13SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG1_LHO14SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG1: LHO14SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG1_LHO14SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG1: LHO14SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG1_LHO15SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG1: LHO15SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG1_LHO15SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG1: LHO15SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG2 ==================================================== */ +#define UDB_DSI_LHO_CFG2_LHO16SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG2: LHO16SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG2_LHO16SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG2: LHO16SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG2_LHO17SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG2: LHO17SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG2_LHO17SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG2: LHO17SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG2_LHO18SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG2: LHO18SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG2_LHO18SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG2: LHO18SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG2_LHO19SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG2: LHO19SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG2_LHO19SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG2: LHO19SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG2_LHO20SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG2: LHO20SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG2_LHO20SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG2: LHO20SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG2_LHO21SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG2: LHO21SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG2_LHO21SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG2: LHO21SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG2_LHO22SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG2: LHO22SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG2_LHO22SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG2: LHO22SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG2_LHO23SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG2: LHO23SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG2_LHO23SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG2: LHO23SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG3 ==================================================== */ +#define UDB_DSI_LHO_CFG3_LHO24SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG3: LHO24SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG3_LHO24SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG3: LHO24SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG3_LHO25SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG3: LHO25SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG3_LHO25SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG3: LHO25SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG3_LHO26SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG3: LHO26SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG3_LHO26SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG3: LHO26SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG3_LHO27SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG3: LHO27SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG3_LHO27SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG3: LHO27SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG3_LHO28SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG3: LHO28SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG3_LHO28SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG3: LHO28SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG3_LHO29SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG3: LHO29SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG3_LHO29SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG3: LHO29SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG3_LHO30SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG3: LHO30SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG3_LHO30SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG3: LHO30SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG3_LHO31SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG3: LHO31SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG3_LHO31SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG3: LHO31SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG4 ==================================================== */ +#define UDB_DSI_LHO_CFG4_LHO32SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG4: LHO32SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG4_LHO32SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG4: LHO32SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG4_LHO33SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG4: LHO33SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG4_LHO33SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG4: LHO33SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG4_LHO34SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG4: LHO34SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG4_LHO34SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG4: LHO34SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG4_LHO35SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG4: LHO35SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG4_LHO35SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG4: LHO35SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG4_LHO36SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG4: LHO36SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG4_LHO36SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG4: LHO36SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG4_LHO37SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG4: LHO37SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG4_LHO37SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG4: LHO37SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG4_LHO38SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG4: LHO38SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG4_LHO38SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG4: LHO38SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG4_LHO39SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG4: LHO39SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG4_LHO39SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG4: LHO39SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG5 ==================================================== */ +#define UDB_DSI_LHO_CFG5_LHO40SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG5: LHO40SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG5_LHO40SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG5: LHO40SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG5_LHO41SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG5: LHO41SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG5_LHO41SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG5: LHO41SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG5_LHO42SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG5: LHO42SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG5_LHO42SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG5: LHO42SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG5_LHO43SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG5: LHO43SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG5_LHO43SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG5: LHO43SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG5_LHO44SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG5: LHO44SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG5_LHO44SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG5: LHO44SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG5_LHO45SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG5: LHO45SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG5_LHO45SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG5: LHO45SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG5_LHO46SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG5: LHO46SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG5_LHO46SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG5: LHO46SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG5_LHO47SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG5: LHO47SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG5_LHO47SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG5: LHO47SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG6 ==================================================== */ +#define UDB_DSI_LHO_CFG6_LHO48SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG6: LHO48SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG6_LHO48SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG6: LHO48SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG6_LHO49SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG6: LHO49SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG6_LHO49SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG6: LHO49SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG6_LHO50SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG6: LHO50SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG6_LHO50SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG6: LHO50SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG6_LHO51SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG6: LHO51SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG6_LHO51SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG6: LHO51SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG6_LHO52SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG6: LHO52SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG6_LHO52SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG6: LHO52SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG6_LHO53SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG6: LHO53SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG6_LHO53SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG6: LHO53SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG6_LHO54SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG6: LHO54SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG6_LHO54SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG6: LHO54SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG6_LHO55SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG6: LHO55SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG6_LHO55SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG6: LHO55SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG7 ==================================================== */ +#define UDB_DSI_LHO_CFG7_LHO56SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG7: LHO56SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG7_LHO56SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG7: LHO56SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG7_LHO57SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG7: LHO57SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG7_LHO57SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG7: LHO57SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG7_LHO58SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG7: LHO58SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG7_LHO58SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG7: LHO58SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG7_LHO59SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG7: LHO59SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG7_LHO59SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG7: LHO59SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG7_LHO60SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG7: LHO60SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG7_LHO60SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG7: LHO60SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG7_LHO61SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG7: LHO61SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG7_LHO61SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG7: LHO61SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG7_LHO62SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG7: LHO62SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG7_LHO62SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG7: LHO62SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG7_LHO63SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG7: LHO63SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG7_LHO63SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG7: LHO63SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG8 ==================================================== */ +#define UDB_DSI_LHO_CFG8_LHO64SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG8: LHO64SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG8_LHO64SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG8: LHO64SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG8_LHO65SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG8: LHO65SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG8_LHO65SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG8: LHO65SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG8_LHO66SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG8: LHO66SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG8_LHO66SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG8: LHO66SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG8_LHO67SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG8: LHO67SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG8_LHO67SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG8: LHO67SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG8_LHO68SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG8: LHO68SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG8_LHO68SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG8: LHO68SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG8_LHO69SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG8: LHO69SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG8_LHO69SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG8: LHO69SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG8_LHO70SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG8: LHO70SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG8_LHO70SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG8: LHO70SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG8_LHO71SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG8: LHO71SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG8_LHO71SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG8: LHO71SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG9 ==================================================== */ +#define UDB_DSI_LHO_CFG9_LHO72SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG9: LHO72SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG9_LHO72SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG9: LHO72SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG9_LHO73SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG9: LHO73SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG9_LHO73SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG9: LHO73SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG9_LHO74SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG9: LHO74SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG9_LHO74SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG9: LHO74SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG9_LHO75SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG9: LHO75SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG9_LHO75SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG9: LHO75SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG9_LHO76SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG9: LHO76SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG9_LHO76SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG9: LHO76SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG9_LHO77SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG9: LHO77SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG9_LHO77SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG9: LHO77SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG9_LHO78SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG9: LHO78SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG9_LHO78SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG9: LHO78SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG9_LHO79SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG9: LHO79SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG9_LHO79SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG9: LHO79SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG10 =================================================== */ +#define UDB_DSI_LHO_CFG10_LHO80SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG10: LHO80SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG10_LHO80SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG10: LHO80SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG10_LHO81SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG10: LHO81SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG10_LHO81SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG10: LHO81SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG10_LHO82SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG10: LHO82SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG10_LHO82SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG10: LHO82SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG10_LHO83SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG10: LHO83SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG10_LHO83SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG10: LHO83SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG10_LHO84SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG10: LHO84SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG10_LHO84SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG10: LHO84SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG10_LHO85SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG10: LHO85SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG10_LHO85SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG10: LHO85SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG10_LHO86SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG10: LHO86SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG10_LHO86SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG10: LHO86SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG10_LHO87SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG10: LHO87SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG10_LHO87SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG10: LHO87SEL (Bitfield-Mask: 0x0f) */ +/* =================================================== UDB_DSI.LHO_CFG11 =================================================== */ +#define UDB_DSI_LHO_CFG11_LHO88SEL_Pos (0UL) /*!< UDB_DSI LHO_CFG11: LHO88SEL (Bit 0) */ +#define UDB_DSI_LHO_CFG11_LHO88SEL_Msk (0xfUL) /*!< UDB_DSI LHO_CFG11: LHO88SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG11_LHO89SEL_Pos (4UL) /*!< UDB_DSI LHO_CFG11: LHO89SEL (Bit 4) */ +#define UDB_DSI_LHO_CFG11_LHO89SEL_Msk (0xf0UL) /*!< UDB_DSI LHO_CFG11: LHO89SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG11_LHO90SEL_Pos (8UL) /*!< UDB_DSI LHO_CFG11: LHO90SEL (Bit 8) */ +#define UDB_DSI_LHO_CFG11_LHO90SEL_Msk (0xf00UL) /*!< UDB_DSI LHO_CFG11: LHO90SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG11_LHO91SEL_Pos (12UL) /*!< UDB_DSI LHO_CFG11: LHO91SEL (Bit 12) */ +#define UDB_DSI_LHO_CFG11_LHO91SEL_Msk (0xf000UL) /*!< UDB_DSI LHO_CFG11: LHO91SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG11_LHO92SEL_Pos (16UL) /*!< UDB_DSI LHO_CFG11: LHO92SEL (Bit 16) */ +#define UDB_DSI_LHO_CFG11_LHO92SEL_Msk (0xf0000UL) /*!< UDB_DSI LHO_CFG11: LHO92SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG11_LHO93SEL_Pos (20UL) /*!< UDB_DSI LHO_CFG11: LHO93SEL (Bit 20) */ +#define UDB_DSI_LHO_CFG11_LHO93SEL_Msk (0xf00000UL) /*!< UDB_DSI LHO_CFG11: LHO93SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG11_LHO94SEL_Pos (24UL) /*!< UDB_DSI LHO_CFG11: LHO94SEL (Bit 24) */ +#define UDB_DSI_LHO_CFG11_LHO94SEL_Msk (0xf000000UL) /*!< UDB_DSI LHO_CFG11: LHO94SEL (Bitfield-Mask: 0x0f) */ +#define UDB_DSI_LHO_CFG11_LHO95SEL_Pos (28UL) /*!< UDB_DSI LHO_CFG11: LHO95SEL (Bit 28) */ +#define UDB_DSI_LHO_CFG11_LHO95SEL_Msk (0xf0000000UL) /*!< UDB_DSI LHO_CFG11: LHO95SEL (Bitfield-Mask: 0x0f) */ + + +/* ====================================================== UDB_PA.CFG0 ====================================================== */ +#define UDB_PA_CFG0_CLKIN_EN_SEL_Pos (0UL) /*!< UDB_PA CFG0: CLKIN_EN_SEL (Bit 0) */ +#define UDB_PA_CFG0_CLKIN_EN_SEL_Msk (0x3UL) /*!< UDB_PA CFG0: CLKIN_EN_SEL (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG0_CLKIN_EN_MODE_Pos (2UL) /*!< UDB_PA CFG0: CLKIN_EN_MODE (Bit 2) */ +#define UDB_PA_CFG0_CLKIN_EN_MODE_Msk (0xcUL) /*!< UDB_PA CFG0: CLKIN_EN_MODE (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG0_CLKIN_EN_INV_Pos (4UL) /*!< UDB_PA CFG0: CLKIN_EN_INV (Bit 4) */ +#define UDB_PA_CFG0_CLKIN_EN_INV_Msk (0x10UL) /*!< UDB_PA CFG0: CLKIN_EN_INV (Bitfield-Mask: 0x01) */ +#define UDB_PA_CFG0_CLKIN_INV_Pos (5UL) /*!< UDB_PA CFG0: CLKIN_INV (Bit 5) */ +#define UDB_PA_CFG0_CLKIN_INV_Msk (0x20UL) /*!< UDB_PA CFG0: CLKIN_INV (Bitfield-Mask: 0x01) */ +/* ====================================================== UDB_PA.CFG1 ====================================================== */ +#define UDB_PA_CFG1_CLKOUT_EN_SEL_Pos (0UL) /*!< UDB_PA CFG1: CLKOUT_EN_SEL (Bit 0) */ +#define UDB_PA_CFG1_CLKOUT_EN_SEL_Msk (0x3UL) /*!< UDB_PA CFG1: CLKOUT_EN_SEL (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG1_CLKOUT_EN_MODE_Pos (2UL) /*!< UDB_PA CFG1: CLKOUT_EN_MODE (Bit 2) */ +#define UDB_PA_CFG1_CLKOUT_EN_MODE_Msk (0xcUL) /*!< UDB_PA CFG1: CLKOUT_EN_MODE (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG1_CLKOUT_EN_INV_Pos (4UL) /*!< UDB_PA CFG1: CLKOUT_EN_INV (Bit 4) */ +#define UDB_PA_CFG1_CLKOUT_EN_INV_Msk (0x10UL) /*!< UDB_PA CFG1: CLKOUT_EN_INV (Bitfield-Mask: 0x01) */ +#define UDB_PA_CFG1_CLKOUT_INV_Pos (5UL) /*!< UDB_PA CFG1: CLKOUT_INV (Bit 5) */ +#define UDB_PA_CFG1_CLKOUT_INV_Msk (0x20UL) /*!< UDB_PA CFG1: CLKOUT_INV (Bitfield-Mask: 0x01) */ +/* ====================================================== UDB_PA.CFG2 ====================================================== */ +#define UDB_PA_CFG2_CLKIN_SEL_Pos (0UL) /*!< UDB_PA CFG2: CLKIN_SEL (Bit 0) */ +#define UDB_PA_CFG2_CLKIN_SEL_Msk (0xfUL) /*!< UDB_PA CFG2: CLKIN_SEL (Bitfield-Mask: 0x0f) */ +#define UDB_PA_CFG2_CLKOUT_SEL_Pos (4UL) /*!< UDB_PA CFG2: CLKOUT_SEL (Bit 4) */ +#define UDB_PA_CFG2_CLKOUT_SEL_Msk (0xf0UL) /*!< UDB_PA CFG2: CLKOUT_SEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== UDB_PA.CFG3 ====================================================== */ +#define UDB_PA_CFG3_RES_IN_SEL_Pos (0UL) /*!< UDB_PA CFG3: RES_IN_SEL (Bit 0) */ +#define UDB_PA_CFG3_RES_IN_SEL_Msk (0x3UL) /*!< UDB_PA CFG3: RES_IN_SEL (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG3_RES_IN_INV_Pos (2UL) /*!< UDB_PA CFG3: RES_IN_INV (Bit 2) */ +#define UDB_PA_CFG3_RES_IN_INV_Msk (0x4UL) /*!< UDB_PA CFG3: RES_IN_INV (Bitfield-Mask: 0x01) */ +#define UDB_PA_CFG3_RES_OUT_SEL_Pos (4UL) /*!< UDB_PA CFG3: RES_OUT_SEL (Bit 4) */ +#define UDB_PA_CFG3_RES_OUT_SEL_Msk (0x30UL) /*!< UDB_PA CFG3: RES_OUT_SEL (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG3_RES_OUT_INV_Pos (6UL) /*!< UDB_PA CFG3: RES_OUT_INV (Bit 6) */ +#define UDB_PA_CFG3_RES_OUT_INV_Msk (0x40UL) /*!< UDB_PA CFG3: RES_OUT_INV (Bitfield-Mask: 0x01) */ +/* ====================================================== UDB_PA.CFG4 ====================================================== */ +#define UDB_PA_CFG4_RES_IN_EN_Pos (0UL) /*!< UDB_PA CFG4: RES_IN_EN (Bit 0) */ +#define UDB_PA_CFG4_RES_IN_EN_Msk (0x1UL) /*!< UDB_PA CFG4: RES_IN_EN (Bitfield-Mask: 0x01) */ +#define UDB_PA_CFG4_RES_OUT_EN_Pos (1UL) /*!< UDB_PA CFG4: RES_OUT_EN (Bit 1) */ +#define UDB_PA_CFG4_RES_OUT_EN_Msk (0x2UL) /*!< UDB_PA CFG4: RES_OUT_EN (Bitfield-Mask: 0x01) */ +#define UDB_PA_CFG4_RES_OE_EN_Pos (2UL) /*!< UDB_PA CFG4: RES_OE_EN (Bit 2) */ +#define UDB_PA_CFG4_RES_OE_EN_Msk (0x4UL) /*!< UDB_PA CFG4: RES_OE_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== UDB_PA.CFG5 ====================================================== */ +#define UDB_PA_CFG5_PIN_SEL_Pos (0UL) /*!< UDB_PA CFG5: PIN_SEL (Bit 0) */ +#define UDB_PA_CFG5_PIN_SEL_Msk (0x7UL) /*!< UDB_PA CFG5: PIN_SEL (Bitfield-Mask: 0x07) */ +/* ====================================================== UDB_PA.CFG6 ====================================================== */ +#define UDB_PA_CFG6_IN_SYNC0_Pos (0UL) /*!< UDB_PA CFG6: IN_SYNC0 (Bit 0) */ +#define UDB_PA_CFG6_IN_SYNC0_Msk (0x3UL) /*!< UDB_PA CFG6: IN_SYNC0 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG6_IN_SYNC1_Pos (2UL) /*!< UDB_PA CFG6: IN_SYNC1 (Bit 2) */ +#define UDB_PA_CFG6_IN_SYNC1_Msk (0xcUL) /*!< UDB_PA CFG6: IN_SYNC1 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG6_IN_SYNC2_Pos (4UL) /*!< UDB_PA CFG6: IN_SYNC2 (Bit 4) */ +#define UDB_PA_CFG6_IN_SYNC2_Msk (0x30UL) /*!< UDB_PA CFG6: IN_SYNC2 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG6_IN_SYNC3_Pos (6UL) /*!< UDB_PA CFG6: IN_SYNC3 (Bit 6) */ +#define UDB_PA_CFG6_IN_SYNC3_Msk (0xc0UL) /*!< UDB_PA CFG6: IN_SYNC3 (Bitfield-Mask: 0x03) */ +/* ====================================================== UDB_PA.CFG7 ====================================================== */ +#define UDB_PA_CFG7_IN_SYNC4_Pos (0UL) /*!< UDB_PA CFG7: IN_SYNC4 (Bit 0) */ +#define UDB_PA_CFG7_IN_SYNC4_Msk (0x3UL) /*!< UDB_PA CFG7: IN_SYNC4 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG7_IN_SYNC5_Pos (2UL) /*!< UDB_PA CFG7: IN_SYNC5 (Bit 2) */ +#define UDB_PA_CFG7_IN_SYNC5_Msk (0xcUL) /*!< UDB_PA CFG7: IN_SYNC5 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG7_IN_SYNC6_Pos (4UL) /*!< UDB_PA CFG7: IN_SYNC6 (Bit 4) */ +#define UDB_PA_CFG7_IN_SYNC6_Msk (0x30UL) /*!< UDB_PA CFG7: IN_SYNC6 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG7_IN_SYNC7_Pos (6UL) /*!< UDB_PA CFG7: IN_SYNC7 (Bit 6) */ +#define UDB_PA_CFG7_IN_SYNC7_Msk (0xc0UL) /*!< UDB_PA CFG7: IN_SYNC7 (Bitfield-Mask: 0x03) */ +/* ====================================================== UDB_PA.CFG8 ====================================================== */ +#define UDB_PA_CFG8_OUT_SYNC0_Pos (0UL) /*!< UDB_PA CFG8: OUT_SYNC0 (Bit 0) */ +#define UDB_PA_CFG8_OUT_SYNC0_Msk (0x3UL) /*!< UDB_PA CFG8: OUT_SYNC0 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG8_OUT_SYNC1_Pos (2UL) /*!< UDB_PA CFG8: OUT_SYNC1 (Bit 2) */ +#define UDB_PA_CFG8_OUT_SYNC1_Msk (0xcUL) /*!< UDB_PA CFG8: OUT_SYNC1 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG8_OUT_SYNC2_Pos (4UL) /*!< UDB_PA CFG8: OUT_SYNC2 (Bit 4) */ +#define UDB_PA_CFG8_OUT_SYNC2_Msk (0x30UL) /*!< UDB_PA CFG8: OUT_SYNC2 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG8_OUT_SYNC3_Pos (6UL) /*!< UDB_PA CFG8: OUT_SYNC3 (Bit 6) */ +#define UDB_PA_CFG8_OUT_SYNC3_Msk (0xc0UL) /*!< UDB_PA CFG8: OUT_SYNC3 (Bitfield-Mask: 0x03) */ +/* ====================================================== UDB_PA.CFG9 ====================================================== */ +#define UDB_PA_CFG9_OUT_SYNC4_Pos (0UL) /*!< UDB_PA CFG9: OUT_SYNC4 (Bit 0) */ +#define UDB_PA_CFG9_OUT_SYNC4_Msk (0x3UL) /*!< UDB_PA CFG9: OUT_SYNC4 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG9_OUT_SYNC5_Pos (2UL) /*!< UDB_PA CFG9: OUT_SYNC5 (Bit 2) */ +#define UDB_PA_CFG9_OUT_SYNC5_Msk (0xcUL) /*!< UDB_PA CFG9: OUT_SYNC5 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG9_OUT_SYNC6_Pos (4UL) /*!< UDB_PA CFG9: OUT_SYNC6 (Bit 4) */ +#define UDB_PA_CFG9_OUT_SYNC6_Msk (0x30UL) /*!< UDB_PA CFG9: OUT_SYNC6 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG9_OUT_SYNC7_Pos (6UL) /*!< UDB_PA CFG9: OUT_SYNC7 (Bit 6) */ +#define UDB_PA_CFG9_OUT_SYNC7_Msk (0xc0UL) /*!< UDB_PA CFG9: OUT_SYNC7 (Bitfield-Mask: 0x03) */ +/* ===================================================== UDB_PA.CFG10 ====================================================== */ +#define UDB_PA_CFG10_DATA_SEL0_Pos (0UL) /*!< UDB_PA CFG10: DATA_SEL0 (Bit 0) */ +#define UDB_PA_CFG10_DATA_SEL0_Msk (0x3UL) /*!< UDB_PA CFG10: DATA_SEL0 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG10_DATA_SEL1_Pos (2UL) /*!< UDB_PA CFG10: DATA_SEL1 (Bit 2) */ +#define UDB_PA_CFG10_DATA_SEL1_Msk (0xcUL) /*!< UDB_PA CFG10: DATA_SEL1 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG10_DATA_SEL2_Pos (4UL) /*!< UDB_PA CFG10: DATA_SEL2 (Bit 4) */ +#define UDB_PA_CFG10_DATA_SEL2_Msk (0x30UL) /*!< UDB_PA CFG10: DATA_SEL2 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG10_DATA_SEL3_Pos (6UL) /*!< UDB_PA CFG10: DATA_SEL3 (Bit 6) */ +#define UDB_PA_CFG10_DATA_SEL3_Msk (0xc0UL) /*!< UDB_PA CFG10: DATA_SEL3 (Bitfield-Mask: 0x03) */ +/* ===================================================== UDB_PA.CFG11 ====================================================== */ +#define UDB_PA_CFG11_DATA_SEL4_Pos (0UL) /*!< UDB_PA CFG11: DATA_SEL4 (Bit 0) */ +#define UDB_PA_CFG11_DATA_SEL4_Msk (0x3UL) /*!< UDB_PA CFG11: DATA_SEL4 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG11_DATA_SEL5_Pos (2UL) /*!< UDB_PA CFG11: DATA_SEL5 (Bit 2) */ +#define UDB_PA_CFG11_DATA_SEL5_Msk (0xcUL) /*!< UDB_PA CFG11: DATA_SEL5 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG11_DATA_SEL6_Pos (4UL) /*!< UDB_PA CFG11: DATA_SEL6 (Bit 4) */ +#define UDB_PA_CFG11_DATA_SEL6_Msk (0x30UL) /*!< UDB_PA CFG11: DATA_SEL6 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG11_DATA_SEL7_Pos (6UL) /*!< UDB_PA CFG11: DATA_SEL7 (Bit 6) */ +#define UDB_PA_CFG11_DATA_SEL7_Msk (0xc0UL) /*!< UDB_PA CFG11: DATA_SEL7 (Bitfield-Mask: 0x03) */ +/* ===================================================== UDB_PA.CFG12 ====================================================== */ +#define UDB_PA_CFG12_OE_SEL0_Pos (0UL) /*!< UDB_PA CFG12: OE_SEL0 (Bit 0) */ +#define UDB_PA_CFG12_OE_SEL0_Msk (0x3UL) /*!< UDB_PA CFG12: OE_SEL0 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG12_OE_SEL1_Pos (2UL) /*!< UDB_PA CFG12: OE_SEL1 (Bit 2) */ +#define UDB_PA_CFG12_OE_SEL1_Msk (0xcUL) /*!< UDB_PA CFG12: OE_SEL1 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG12_OE_SEL2_Pos (4UL) /*!< UDB_PA CFG12: OE_SEL2 (Bit 4) */ +#define UDB_PA_CFG12_OE_SEL2_Msk (0x30UL) /*!< UDB_PA CFG12: OE_SEL2 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG12_OE_SEL3_Pos (6UL) /*!< UDB_PA CFG12: OE_SEL3 (Bit 6) */ +#define UDB_PA_CFG12_OE_SEL3_Msk (0xc0UL) /*!< UDB_PA CFG12: OE_SEL3 (Bitfield-Mask: 0x03) */ +/* ===================================================== UDB_PA.CFG13 ====================================================== */ +#define UDB_PA_CFG13_OE_SEL4_Pos (0UL) /*!< UDB_PA CFG13: OE_SEL4 (Bit 0) */ +#define UDB_PA_CFG13_OE_SEL4_Msk (0x3UL) /*!< UDB_PA CFG13: OE_SEL4 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG13_OE_SEL5_Pos (2UL) /*!< UDB_PA CFG13: OE_SEL5 (Bit 2) */ +#define UDB_PA_CFG13_OE_SEL5_Msk (0xcUL) /*!< UDB_PA CFG13: OE_SEL5 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG13_OE_SEL6_Pos (4UL) /*!< UDB_PA CFG13: OE_SEL6 (Bit 4) */ +#define UDB_PA_CFG13_OE_SEL6_Msk (0x30UL) /*!< UDB_PA CFG13: OE_SEL6 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG13_OE_SEL7_Pos (6UL) /*!< UDB_PA CFG13: OE_SEL7 (Bit 6) */ +#define UDB_PA_CFG13_OE_SEL7_Msk (0xc0UL) /*!< UDB_PA CFG13: OE_SEL7 (Bitfield-Mask: 0x03) */ +/* ===================================================== UDB_PA.CFG14 ====================================================== */ +#define UDB_PA_CFG14_OE_SYNC0_Pos (0UL) /*!< UDB_PA CFG14: OE_SYNC0 (Bit 0) */ +#define UDB_PA_CFG14_OE_SYNC0_Msk (0x3UL) /*!< UDB_PA CFG14: OE_SYNC0 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG14_OE_SYNC1_Pos (2UL) /*!< UDB_PA CFG14: OE_SYNC1 (Bit 2) */ +#define UDB_PA_CFG14_OE_SYNC1_Msk (0xcUL) /*!< UDB_PA CFG14: OE_SYNC1 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG14_OE_SYNC2_Pos (4UL) /*!< UDB_PA CFG14: OE_SYNC2 (Bit 4) */ +#define UDB_PA_CFG14_OE_SYNC2_Msk (0x30UL) /*!< UDB_PA CFG14: OE_SYNC2 (Bitfield-Mask: 0x03) */ +#define UDB_PA_CFG14_OE_SYNC3_Pos (6UL) /*!< UDB_PA CFG14: OE_SYNC3 (Bit 6) */ +#define UDB_PA_CFG14_OE_SYNC3_Msk (0xc0UL) /*!< UDB_PA CFG14: OE_SYNC3 (Bitfield-Mask: 0x03) */ + + +/* =================================================== UDB_BCTL.MDCLK_EN =================================================== */ +#define UDB_BCTL_MDCLK_EN_DCEN_Pos (0UL) /*!< UDB_BCTL MDCLK_EN: DCEN (Bit 0) */ +#define UDB_BCTL_MDCLK_EN_DCEN_Msk (0xffUL) /*!< UDB_BCTL MDCLK_EN: DCEN (Bitfield-Mask: 0xff) */ +/* =================================================== UDB_BCTL.MBCLK_EN =================================================== */ +#define UDB_BCTL_MBCLK_EN_BCEN_Pos (0UL) /*!< UDB_BCTL MBCLK_EN: BCEN (Bit 0) */ +#define UDB_BCTL_MBCLK_EN_BCEN_Msk (0x1UL) /*!< UDB_BCTL MBCLK_EN: BCEN (Bitfield-Mask: 0x01) */ +/* =================================================== UDB_BCTL.BOTSEL_L =================================================== */ +#define UDB_BCTL_BOTSEL_L_CLK_SEL0_Pos (0UL) /*!< UDB_BCTL BOTSEL_L: CLK_SEL0 (Bit 0) */ +#define UDB_BCTL_BOTSEL_L_CLK_SEL0_Msk (0x3UL) /*!< UDB_BCTL BOTSEL_L: CLK_SEL0 (Bitfield-Mask: 0x03) */ +#define UDB_BCTL_BOTSEL_L_CLK_SEL1_Pos (2UL) /*!< UDB_BCTL BOTSEL_L: CLK_SEL1 (Bit 2) */ +#define UDB_BCTL_BOTSEL_L_CLK_SEL1_Msk (0xcUL) /*!< UDB_BCTL BOTSEL_L: CLK_SEL1 (Bitfield-Mask: 0x03) */ +#define UDB_BCTL_BOTSEL_L_CLK_SEL2_Pos (4UL) /*!< UDB_BCTL BOTSEL_L: CLK_SEL2 (Bit 4) */ +#define UDB_BCTL_BOTSEL_L_CLK_SEL2_Msk (0x30UL) /*!< UDB_BCTL BOTSEL_L: CLK_SEL2 (Bitfield-Mask: 0x03) */ +#define UDB_BCTL_BOTSEL_L_CLK_SEL3_Pos (6UL) /*!< UDB_BCTL BOTSEL_L: CLK_SEL3 (Bit 6) */ +#define UDB_BCTL_BOTSEL_L_CLK_SEL3_Msk (0xc0UL) /*!< UDB_BCTL BOTSEL_L: CLK_SEL3 (Bitfield-Mask: 0x03) */ +/* =================================================== UDB_BCTL.BOTSEL_U =================================================== */ +#define UDB_BCTL_BOTSEL_U_CLK_SEL4_Pos (0UL) /*!< UDB_BCTL BOTSEL_U: CLK_SEL4 (Bit 0) */ +#define UDB_BCTL_BOTSEL_U_CLK_SEL4_Msk (0x3UL) /*!< UDB_BCTL BOTSEL_U: CLK_SEL4 (Bitfield-Mask: 0x03) */ +#define UDB_BCTL_BOTSEL_U_CLK_SEL5_Pos (2UL) /*!< UDB_BCTL BOTSEL_U: CLK_SEL5 (Bit 2) */ +#define UDB_BCTL_BOTSEL_U_CLK_SEL5_Msk (0xcUL) /*!< UDB_BCTL BOTSEL_U: CLK_SEL5 (Bitfield-Mask: 0x03) */ +#define UDB_BCTL_BOTSEL_U_CLK_SEL6_Pos (4UL) /*!< UDB_BCTL BOTSEL_U: CLK_SEL6 (Bit 4) */ +#define UDB_BCTL_BOTSEL_U_CLK_SEL6_Msk (0x30UL) /*!< UDB_BCTL BOTSEL_U: CLK_SEL6 (Bitfield-Mask: 0x03) */ +#define UDB_BCTL_BOTSEL_U_CLK_SEL7_Pos (6UL) /*!< UDB_BCTL BOTSEL_U: CLK_SEL7 (Bit 6) */ +#define UDB_BCTL_BOTSEL_U_CLK_SEL7_Msk (0xc0UL) /*!< UDB_BCTL BOTSEL_U: CLK_SEL7 (Bitfield-Mask: 0x03) */ +/* =================================================== UDB_BCTL.QCLK_EN ==================================================== */ +#define UDB_BCTL_QCLK_EN_DCEN_Q_Pos (0UL) /*!< UDB_BCTL QCLK_EN: DCEN_Q (Bit 0) */ +#define UDB_BCTL_QCLK_EN_DCEN_Q_Msk (0xffUL) /*!< UDB_BCTL QCLK_EN: DCEN_Q (Bitfield-Mask: 0xff) */ +#define UDB_BCTL_QCLK_EN_BCEN_Q_Pos (8UL) /*!< UDB_BCTL QCLK_EN: BCEN_Q (Bit 8) */ +#define UDB_BCTL_QCLK_EN_BCEN_Q_Msk (0x100UL) /*!< UDB_BCTL QCLK_EN: BCEN_Q (Bitfield-Mask: 0x01) */ +#define UDB_BCTL_QCLK_EN_DISABLE_ROUTE_Pos (11UL) /*!< UDB_BCTL QCLK_EN: DISABLE_ROUTE (Bit 11) */ +#define UDB_BCTL_QCLK_EN_DISABLE_ROUTE_Msk (0x800UL) /*!< UDB_BCTL QCLK_EN: DISABLE_ROUTE (Bitfield-Mask: 0x01) */ + + +/* ================================================== UDB_UDBIF.BANK_CTL =================================================== */ +#define UDB_UDBIF_BANK_CTL_DIS_COR_Pos (0UL) /*!< UDB_UDBIF BANK_CTL: DIS_COR (Bit 0) */ +#define UDB_UDBIF_BANK_CTL_DIS_COR_Msk (0x1UL) /*!< UDB_UDBIF BANK_CTL: DIS_COR (Bitfield-Mask: 0x01) */ +#define UDB_UDBIF_BANK_CTL_ROUTE_EN_Pos (1UL) /*!< UDB_UDBIF BANK_CTL: ROUTE_EN (Bit 1) */ +#define UDB_UDBIF_BANK_CTL_ROUTE_EN_Msk (0x2UL) /*!< UDB_UDBIF BANK_CTL: ROUTE_EN (Bitfield-Mask: 0x01) */ +#define UDB_UDBIF_BANK_CTL_BANK_EN_Pos (2UL) /*!< UDB_UDBIF BANK_CTL: BANK_EN (Bit 2) */ +#define UDB_UDBIF_BANK_CTL_BANK_EN_Msk (0x4UL) /*!< UDB_UDBIF BANK_CTL: BANK_EN (Bitfield-Mask: 0x01) */ +#define UDB_UDBIF_BANK_CTL_READ_WAIT_Pos (8UL) /*!< UDB_UDBIF BANK_CTL: READ_WAIT (Bit 8) */ +#define UDB_UDBIF_BANK_CTL_READ_WAIT_Msk (0x100UL) /*!< UDB_UDBIF BANK_CTL: READ_WAIT (Bitfield-Mask: 0x01) */ +/* ================================================= UDB_UDBIF.INT_CLK_CTL ================================================= */ +#define UDB_UDBIF_INT_CLK_CTL_INT_CLK_ENABLE_Pos (0UL) /*!< UDB_UDBIF INT_CLK_CTL: INT_CLK_ENABLE (Bit 0) */ +#define UDB_UDBIF_INT_CLK_CTL_INT_CLK_ENABLE_Msk (0x1UL) /*!< UDB_UDBIF INT_CLK_CTL: INT_CLK_ENABLE (Bitfield-Mask: 0x01)*/ +/* =================================================== UDB_UDBIF.INT_CFG =================================================== */ +#define UDB_UDBIF_INT_CFG_INT_MODE_CFG_Pos (0UL) /*!< UDB_UDBIF INT_CFG: INT_MODE_CFG (Bit 0) */ +#define UDB_UDBIF_INT_CFG_INT_MODE_CFG_Msk (0xffffffffUL) /*!< UDB_UDBIF INT_CFG: INT_MODE_CFG (Bitfield-Mask: 0xffffffff)*/ +/* ================================================= UDB_UDBIF.TR_CLK_CTL ================================================== */ +#define UDB_UDBIF_TR_CLK_CTL_TR_CLOCK_ENABLE_Pos (0UL) /*!< UDB_UDBIF TR_CLK_CTL: TR_CLOCK_ENABLE (Bit 0) */ +#define UDB_UDBIF_TR_CLK_CTL_TR_CLOCK_ENABLE_Msk (0x1UL) /*!< UDB_UDBIF TR_CLK_CTL: TR_CLOCK_ENABLE (Bitfield-Mask: 0x01)*/ +/* =================================================== UDB_UDBIF.TR_CFG ==================================================== */ +#define UDB_UDBIF_TR_CFG_TR_MODE_CFG_Pos (0UL) /*!< UDB_UDBIF TR_CFG: TR_MODE_CFG (Bit 0) */ +#define UDB_UDBIF_TR_CFG_TR_MODE_CFG_Msk (0xffffffffUL) /*!< UDB_UDBIF TR_CFG: TR_MODE_CFG (Bitfield-Mask: 0xffffffff) */ +/* =================================================== UDB_UDBIF.PRIVATE =================================================== */ +#define UDB_UDBIF_PRIVATE_PIPELINE_MD_Pos (0UL) /*!< UDB_UDBIF PRIVATE: PIPELINE_MD (Bit 0) */ +#define UDB_UDBIF_PRIVATE_PIPELINE_MD_Msk (0x1UL) /*!< UDB_UDBIF PRIVATE: PIPELINE_MD (Bitfield-Mask: 0x01) */ + + +#endif /* _CYIP_UDB_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/middleware/ble/cy_ble_clk.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/middleware/ble/cy_ble_clk.c new file mode 100644 index 0000000000..5f7dacaab6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/middleware/ble/cy_ble_clk.c @@ -0,0 +1,491 @@ +/***************************************************************************//** +* \file cy_ble_clk.c +* \version 1.0 +* +* \brief +* Contains the source code for the BLE ECO clock. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_ble_clk.h" +#include "syslib/cy_syslib.h" +#include "sysclk/cy_sysclk.h" +#include "syspm/cy_syspm.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +static uint16_t Cy_BLE_HalRcbRegRead(uint16_t addr); +static void Cy_BLE_HalRcbRegWrite(uint16_t addr, uint16_t data); +static void Cy_BLE_HalEcoSetTrim(uint8_t trim); +static void Cy_BLE_HalMxdRadioEnableClocks(const cy_stc_ble_bless_eco_cfg_params_t *ecoConfig); + + +/******************************************************************************* +* Function Name: Cy_BLE_HAL_IsEcoCpuClockSrc +****************************************************************************//** +* +* If ECO from BLESS in CLK_PATH_SELECT register is selected return 1. +* +* \return +* uint8_t: 0 - ECO from BLESS is not used in DWR +* 1 - ECO from BLESS is selected in CLK_PATH_SELECT register +* +*******************************************************************************/ +uint8_t Cy_BLE_HAL_IsEcoCpuClockSrc(void) +{ + uint8_t returnVal = 0u; + uint32_t i; + + for(i = 0u; i < SRSS_NUM_CLKPATH; i++) + { + if(Cy_SysClk_ClkPathGetSource(i) == CY_SYSCLK_CLKPATH_IN_ALTHF) + { + returnVal = 1u; + break; + } + } + + return(returnVal); +} + + +/******************************************************************************* +* Function Name: Cy_BLE_HAL_IsWcoLfclkSrc +****************************************************************************//** +* +* In CLK_SELECT register if WCO or PILO return 1 +* +* \return +* uint8_t: 0 - WCO or PILO are not used in DWR +* 1 - WCO is selected in CLK_SELECT register +* +*******************************************************************************/ +uint8_t Cy_BLE_HAL_IsWcoLfclkSrc(void) +{ + cy_en_lfclk_input_sources_t lfclkSrs; + + lfclkSrs = Cy_SysClk_LfClkGetSource(); + + return(((lfclkSrs == CY_SYSCLK_LFCLK_IN_WCO) || (lfclkSrs == CY_SYSCLK_LFCLK_IN_PILO)) ? 1u : 0u); +} + + +/******************************************************************************* +* Function Name: Cy_BLE_HAL_Init +****************************************************************************//** +* +* Initializes the BLESS port. +* +* \return +* None +* +*******************************************************************************/ +void Cy_BLE_HAL_Init(void) +{ + /* Configures pins for BLESS */ + const cy_stc_gpio_prt_config_t port2_cfg = + { + .cfg = CY_BLE_PORT2_CFG_VAL, + .sel0Active = CY_BLE_PORT2_HSIOM_SEL0, + .sel1Active = CY_BLE_PORT2_HSIOM_SEL1 + }; + const cy_stc_gpio_prt_config_t port3_cfg = + { + .cfg = CY_BLE_PORT3_CFG_VAL, + .sel0Active = CY_BLE_PORT3_HSIOM_SEL0, + .sel1Active = CY_BLE_PORT3_HSIOM_SEL1 + }; + const cy_stc_gpio_prt_config_t port4_cfg = + { + .cfg = CY_BLE_PORT4_CFG_VAL, + .sel0Active = CY_BLE_PORT4_HSIOM_SEL0, + .sel1Active = CY_BLE_PORT4_HSIOM_SEL1 + }; + + Cy_GPIO_Port_Init(GPIO_PRT2, &port2_cfg); + Cy_GPIO_Port_Init(GPIO_PRT3, &port3_cfg); + Cy_GPIO_Port_Init(GPIO_PRT4, &port4_cfg); +} + + +/******************************************************************************* +* Function Name: Cy_BLE_HalRcbRegRead +****************************************************************************//** +* +* Reads Radio register. +* +* \param addr: Register address. +* +* \return +* Register data +* +*******************************************************************************/ +static uint16_t Cy_BLE_HalRcbRegRead(uint16_t addr) +{ + uint32_t temp = (uint32_t)((0x8000UL | addr) << 16u); + + /* Write Address to the RCB */ + BLE->RCB.TX_FIFO_WR = temp; + + /* Wait for Data. */ + while((BLE->RCB.INTR & BLE_RCB_INTR_RCB_DONE_Msk) == 0u) + { + } + + BLE->RCB.INTR |= BLE_RCB_INTR_RCB_DONE_Msk; + + return((uint16_t)BLE->RCB.RX_FIFO_RD); +} + + +/******************************************************************************* +* Function Name: Cy_BLE_HalRcbRegWrite +****************************************************************************//** +* +* Writes Radio register. +* +* \param addr: Register address. +* \param data: Register data. +* +* \return +* None +* +*******************************************************************************/ +static void Cy_BLE_HalRcbRegWrite(uint16_t addr, uint16_t data) +{ + uint32_t temp = ((uint32_t)((0x7FFFUL & addr) << 16u)) | data; + + BLE->RCB.TX_FIFO_WR = temp; + + /* Wait for RCB done. */ + while((BLE->RCB.INTR & BLE_RCB_INTR_RCB_DONE_Msk) == 0u) + { + } + + BLE->RCB.INTR |= BLE_RCB_INTR_RCB_DONE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_BLE_HalEcoSetTrim +****************************************************************************//** +* +* Sets ECO trim value. +* +* \param trim: Trim value. +* +* \return +* None +* +*******************************************************************************/ +static void Cy_BLE_HalEcoSetTrim(uint8_t trim) +{ + uint32_t reg; + + /* Read CY_BLE_RF_DCXO_CFG_REG */ + reg = Cy_BLE_HalRcbRegRead(CY_BLE_RF_DCXO_CFG_REG); + /* Clear the CAP value */ + reg &= ~(CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_MASK << CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_SHIFT); + /* Load the new CAP TRIM value */ + reg |= (uint32_t)trim << CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_SHIFT; + /* Write the new value to the register */ + Cy_BLE_HalRcbRegWrite(CY_BLE_RF_DCXO_CFG_REG, CY_LO16(reg)); +} + + +/******************************************************************************* +* Function Name: Cy_BLE_HalMxdRadioEnableClocks +****************************************************************************//** +* +* Enables and configures radio clock. +* +* \param ecoConfig: Clock configuration of type 'cy_stc_ble_bless_eco_cfg_params_t'. +* +* \return +* None +* +*******************************************************************************/ +static void Cy_BLE_HalMxdRadioEnableClocks(const cy_stc_ble_bless_eco_cfg_params_t *ecoConfig) +{ + uint16_t temp; + uint16_t blerdDivider; + uint16_t ecoSysDivider; + uint16_t blellDivider = 0u; + + /* Deassert active domain reset and enable clock buffer in MXD Radio */ + do + { + Cy_BLE_HalRcbRegWrite(CY_BLE_PMU_MODE_TRANSITION_REG, CY_BLE_MXD_RADIO_CLK_BUF_EN_VAL); + temp = Cy_BLE_HalRcbRegRead(CY_BLE_PMU_MODE_TRANSITION_REG); + } while(temp != CY_BLE_MXD_RADIO_CLK_BUF_EN_VAL); + + /* Check if ECO clock output is enabled + * In MXD_VER2, ECO clock is stopped on overwriting this bit */ + temp = Cy_BLE_HalRcbRegRead(CY_BLE_PMU_PMU_CTRL_REG); + if ((temp & CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL) == 0u) + { + /* Enable digital ECO clock output from MXD Radio to BLESS */ + do + { + Cy_BLE_HalRcbRegWrite(CY_BLE_PMU_PMU_CTRL_REG, CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL); + temp = Cy_BLE_HalRcbRegRead(CY_BLE_PMU_PMU_CTRL_REG); + } while(temp != CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL); + } + + /* Configure ECO clock frequency and clock divider in MXD Radio */ + + /* Read the MXD Radio register */ + temp = Cy_BLE_HalRcbRegRead(CY_BLE_RF_DCXO_BUF_CFG_REG); + /* Clear clock divider and select amp buffer output bits */ + temp &= CY_LO16(~((CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_MASK << CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT) | + (CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_MASK << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT))); + + /* Total ECO divider consist of divider located on BLERD and BLESS divider + Set BLERD divider to maximum value taking in to account that 8 Mhz is required for BLELL + BLELL clock frequency is set to 8Mhz irrespective of the crystal value. + */ + if(ecoConfig->ecoFreq == CY_BLE_BLESS_ECO_FREQ_32MHZ) + { + if(ecoConfig->ecoSysDiv >= (uint32_t)CY_BLE_BLESS_XTAL_CLK_DIV_4) + { + blerdDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_4; + } + else + { + blerdDivider = (uint16_t)ecoConfig->ecoSysDiv; + blellDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_4 - blerdDivider; + } + temp |= CY_BLE_RF_DCXO_BUF_CFG_REG_XTAL_32M_SEL_BIT; + temp |= (uint16_t)(CY_BLE_MXD_RADIO_CLK_BUF_AMP_32M_LARGE << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT); + + /* Update cy_BleEcoClockFreqHz for the proper Cy_SysLib_Delay functionality */ + cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ / (1UL << (uint16_t)ecoConfig->ecoSysDiv); + } + else + { + if(ecoConfig->ecoSysDiv >= (uint32_t)CY_BLE_BLESS_XTAL_CLK_DIV_2) + { + blerdDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_2; + } + else + { + blerdDivider = (uint16_t)ecoConfig->ecoSysDiv; + blellDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_2 - blerdDivider; + } + temp &= (uint16_t)~CY_BLE_RF_DCXO_BUF_CFG_REG_XTAL_32M_SEL_BIT; + temp |= (uint16_t)(CY_BLE_MXD_RADIO_CLK_BUF_AMP_16M_LARGE << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT); + + /* Update cy_BleEcoClockFreqHz for the proper Cy_SysLib_Delay functionality */ + cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ / (1UL << (uint16_t)ecoConfig->ecoSysDiv); + } + + temp |= (uint16_t)(blerdDivider << CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT); + /* Write the MXD Radio register */ + Cy_BLE_HalRcbRegWrite(CY_BLE_RF_DCXO_BUF_CFG_REG, temp); + + /* Reduce BLESS divider by BLERD divider value */ + ecoSysDivider = (uint16_t)ecoConfig->ecoSysDiv - blerdDivider; + temp = (uint16_t)(ecoSysDivider & BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Msk); + temp |= (uint16_t)(blellDivider << BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Pos); + /* Set clock divider */ + BLE->BLESS.XTAL_CLK_DIV_CONFIG = temp; + +} + + +/******************************************************************************* +* Function Name: Cy_BLE_EcoStop +****************************************************************************//** +* +* Disables BLE ECO clock. +* +* \return +* None +* +*******************************************************************************/ +void Cy_BLE_EcoStop(void) +{ + /* Initiate Soft Reset */ + BLE->BLESS.LL_CLK_EN |= BLE_BLESS_LL_CLK_EN_BLESS_RESET_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_BLE_EcoStart +****************************************************************************//** +* +* Configures and starts BLE ECO clock. +* By default, BLE stack starts BLE ECO clock with default parameters: +* CY_BLE_DEFAULT_OSC_STARTUP_DELAY_LF +* CY_BLE_DEFAULT_CAP_TRIM_VALUE +* CY_BLE_DEFAULT_ECO_FREQ +* CY_BLE_DEFAULT_ECO_DIV +* In case BLE ECO is used with different parameters, enable it in DWR or call +* this function with custom configuration. +* +* This clock is stopped in the deep sleep and hibernate power modes. +* +* \param ecoConfig: Clock configuration of type 'cy_stc_ble_bless_eco_cfg_params_t'. +* +* \return +* CY_BLE_ECO_SUCCESS - On successful operation. +* CY_BLE_ECO_BAD_PARAM - Wrong input parameter. +* CY_BLE_ECO_RCB_CONTROL_LL - If the RCB Control is with BLE Link Layer. +* CY_BLE_ECO_ALREADY_STARTED - If BLE ECO clock is aready started +* +*******************************************************************************/ +cy_en_ble_eco_status_t Cy_BLE_EcoStart(const cy_stc_ble_bless_eco_cfg_params_t *ecoConfig) +{ + cy_en_ble_eco_status_t status = CY_BLE_ECO_SUCCESS; + uint32_t temp; + + if(ecoConfig == NULL) + { + status = CY_BLE_ECO_BAD_PARAM; + } + else + { + if((BLE->BLESS.MT_CFG & BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk) != 0u) + { + status = CY_BLE_ECO_ALREADY_STARTED; + } + else + { + /* HAL Initialization */ + Cy_BLE_HAL_Init(); + + /* BLESS MT Delays configuration */ + BLE->BLESS.MT_DELAY_CFG = + (uint32_t)(CY_BLE_DEFAULT_HVLDO_STARTUP_DELAY << BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Pos) | + (uint32_t)(CY_BLE_DEFAULT_ISOLATE_DEASSERT_DELAY << BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Pos) | + (uint32_t)(CY_BLE_DEFAULT_ACT_TO_SWITCH_DELAY << BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Pos) | + (uint32_t)(CY_BLE_DEFAULT_HVLDO_DISABLE_DELAY << BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Pos); + + BLE->BLESS.MT_DELAY_CFG2 = + (uint32_t)((uint32_t)ecoConfig->ecoXtalStartUpTime << BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Pos) | + (uint32_t)(CY_BLE_DEFAULT_ACT_STARTUP_DELAY << BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Pos) | + (uint32_t)(CY_BLE_DEFAULT_DIG_LDO_STARTUP_DELAY << BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Pos); + + BLE->BLESS.MT_DELAY_CFG3 = + (uint32_t)(CY_BLE_DEFAULT_XTAL_DISABLE_DELAY << BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Pos) | + (uint32_t)(CY_BLE_DEFAULT_DIG_LDO_DISABLE_DELAY << BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Pos) | + (uint32_t)(CY_BLE_DEFAULT_VDDR_STABLE_DELAY << BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Pos); + + /* RCB Initialization */ + /* Check if the RCB Control is with LL. */ + if((BLE->RCB.RCBLL.CTRL & BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Msk) != 0u) + { + status = CY_BLE_ECO_RCB_CONTROL_LL; + } + else + { + uint32_t rcbDivider = 0u; + + /* If clock source for RCB is PeriClk */ + if((BLE_BLESS->LL_CLK_EN & BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Msk) == 0u) + { + if(cy_PeriClkFreqHz > CY_BLE_DEFAULT_RCB_CTRL_FREQ) + { + rcbDivider = (cy_PeriClkFreqHz / CY_BLE_DEFAULT_RCB_CTRL_FREQ) - 1u; + } + } + else + { + rcbDivider = CY_BLE_DEFAULT_RCB_CTRL_DIV; + } + + /* Configure default RCB Parameters. */ + BLE->RCB.CTRL |= + (BLE_RCB_CTRL_ENABLED_Msk | + BLE_RCB_CTRL_RX_CLK_EDGE_Msk | + (CY_BLE_DEFAULT_RCB_CTRL_LEAD << BLE_RCB_CTRL_LEAD_Pos) | + (CY_BLE_DEFAULT_RCB_CTRL_LAG << BLE_RCB_CTRL_LAG_Pos) | + ((rcbDivider > 0u) ? + ((rcbDivider << BLE_RCB_CTRL_DIV_Pos) | + BLE_RCB_CTRL_DIV_ENABLED_Msk) + : 0u) + ); + + /* Configure LDO if Buck2 is not already enabled */ + if(!Cy_SysPm_SimoBuckOutputIsEnabled(CY_SYSPM_BUCK_VRF)) + { + BLE->BLESS.MISC_EN_CTRL |= (BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Msk | + BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Msk); + } + + /* Enable the VIO supply and LDO in standby mode for slow ramp */ + temp = BLE->BLESS.MT_CFG; + temp |= BLE_BLESS_MT_CFG_HVLDO_BYPASS_Msk | + BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Msk | + BLE_BLESS_MT_CFG_HVLDO_EN_Msk | + BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Msk; + BLE->BLESS.MT_CFG = temp; + Cy_SysLib_DelayUs(64u); + + if ((BLE->BLESS.MT_VIO_CTRL & BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk) == 0u) + { + /* Enable LDO */ + BLE->BLESS.MT_VIO_CTRL = BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk; + /* Wait for 64us after turning HVLDO ON */ + Cy_SysLib_DelayUs(64u); + /* Enable LDO Delayed */ + BLE->BLESS.MT_VIO_CTRL = BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk | + BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Msk; + /* Wait for 64us */ + Cy_SysLib_DelayUs(64u); + } + + /* Disable override mode and let hardware take control of HVLDO */ + temp &= ~(BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Msk | + BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Msk); + BLE->BLESS.MT_CFG = temp; + + /* Wait for the VIO stable key write operation to complete */ + while ((GPIO->VDD_ACTIVE & 0x10u) == 0u) + { + } + + /* Clear the BLERD_ACTIVE_INTR */ + BLE->BLESS.INTR_STAT |= BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Msk; + + if(!Cy_SysPm_SimoBuckOutputIsEnabled(CY_SYSPM_BUCK_VRF)) + { + temp |= BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Msk; + } + /* Enable Radio */ + temp |= BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk; + /* Disable ECO in DeepSleep mode */ + temp &= ~BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Msk; + BLE->BLESS.MT_CFG = temp; + + while((BLE->BLESS.MT_STATUS & BLE_BLESS_MT_STATUS_BLESS_STATE_Msk) == 0u) + { + } + + /* Enable and configure radio clock */ + Cy_BLE_HalMxdRadioEnableClocks(ecoConfig); + + /* Set Load capacitance */ + Cy_BLE_HalEcoSetTrim(ecoConfig->loadCap); + } + } + } + return(status); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/middleware/ble/cy_ble_clk.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/middleware/ble/cy_ble_clk.h new file mode 100644 index 0000000000..b02062e431 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/middleware/ble/cy_ble_clk.h @@ -0,0 +1,220 @@ +/***************************************************************************//** +* \file cy_ble_clk.h +* \version 1.0 +* +* \brief +* Contains the function prototypes and constants for the BLE clock. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef CY_BLE_CLK_H +#define CY_BLE_CLK_H + +#include "cy_device_headers.h" +#include "gpio/cy_gpio.h" +#include "syslib/cy_syslib.h" +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define CY_BLE_CLK_ID (0x05u << 18u) + +#define CY_BLE_PORT2_CFG_VAL (0x66666666u) +#define CY_BLE_PORT3_CFG_VAL (0x66EEE666u) +#define CY_BLE_PORT4_CFG_VAL (0x6666E666u) + +#define CY_BLE_PORT2_HSIOM_SEL0 (0x1C1C1C1Cu) +#define CY_BLE_PORT2_HSIOM_SEL1 (0x1C1C1C1Cu) +#define CY_BLE_PORT3_HSIOM_SEL0 (0x1A1A1A1Cu) +#define CY_BLE_PORT3_HSIOM_SEL1 (0x00001A1Au) +#define CY_BLE_PORT4_HSIOM_SEL0 (0x1C001A1Au) +#define CY_BLE_PORT4_HSIOM_SEL1 (0x00000000u) + +#define CY_BLE_DEFAULT_OSC_STARTUP_DELAY_LF (45u) +#define CY_BLE_DEFAULT_CAP_TRIM_VALUE (32u) +#define CY_BLE_DEFAULT_ECO_FREQ (CY_BLE_BLESS_ECO_FREQ_32MHZ) +#define CY_BLE_DEFAULT_ECO_DIV (CY_BLE_SYS_ECO_CLK_DIV_4) + +#define CY_BLE_DEFAULT_HVLDO_STARTUP_DELAY (6UL) +#define CY_BLE_DEFAULT_ISOLATE_DEASSERT_DELAY (0UL) +#define CY_BLE_DEFAULT_ACT_TO_SWITCH_DELAY (0UL) +#define CY_BLE_DEFAULT_HVLDO_DISABLE_DELAY (1UL) + +#define CY_BLE_DEFAULT_ACT_STARTUP_DELAY (0UL) +#define CY_BLE_DEFAULT_DIG_LDO_STARTUP_DELAY (0UL) + +#define CY_BLE_DEFAULT_XTAL_DISABLE_DELAY (2UL) +#define CY_BLE_DEFAULT_DIG_LDO_DISABLE_DELAY (1UL) +#define CY_BLE_DEFAULT_VDDR_STABLE_DELAY (1UL) + +#define CY_BLE_DEFAULT_RCB_CTRL_LEAD (0x2UL) +#define CY_BLE_DEFAULT_RCB_CTRL_LAG (0x2UL) +#define CY_BLE_DEFAULT_RCB_CTRL_DIV (0x1UL) /* LL 8 MHz / 2 */ +#define CY_BLE_DEFAULT_RCB_CTRL_FREQ (4000000UL) /* Default RCB clock is 4 MHz */ + +#define CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ (32000000UL) +#define CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ (16000000UL) + +#define CY_BLE_MXD_RADIO_CLK_BUF_EN_VAL (CY_BLE_PMU_MODE_TRANSITION_REG_CLK_ANA_DIG_EN_BIT | \ + CY_BLE_PMU_MODE_TRANSITION_REG_RST_ACT_N_BIT) +#define CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL (CY_BLE_PMU_PMU_CTRL_REG_CLK_CMOS_SEL_BIT) + +/* Radio registers */ +#define CY_BLE_PMU_MODE_TRANSITION_REG (0x1e02u) +#define CY_BLE_PMU_MODE_TRANSITION_REG_CLK_ANA_DIG_EN_BIT (uint16_t)(1UL << 12u) +#define CY_BLE_PMU_MODE_TRANSITION_REG_RST_ACT_N_BIT (uint16_t)(1UL << 11u) + +#define CY_BLE_PMU_PMU_CTRL_REG (0x1e03u) +#define CY_BLE_PMU_PMU_CTRL_REG_CLK_CMOS_SEL_BIT (uint16_t)(1UL << 10u) + +#define CY_BLE_RF_DCXO_CFG_REG (0x1e08u) +#define CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_SHIFT (1u) +#define CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_MASK (0xffUL) + +#define CY_BLE_RF_DCXO_BUF_CFG_REG (0x1e09u) +#define CY_BLE_RF_DCXO_BUF_CFG_REG_XTAL_32M_SEL_BIT (uint16_t)(1UL << 6u) +#define CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT (4u) +#define CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_MASK (0x03UL) +#define CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT (0u) +#define CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_MASK (0x0fUL) + + +/** + \addtogroup group_ble_clock_api + @{ +*/ + +/*************************************** +* Data Types +***************************************/ + +/** BLE Radio ECO clock divider */ +typedef enum +{ + CY_BLE_MXD_RADIO_CLK_DIV_1 = 0u, + CY_BLE_MXD_RADIO_CLK_DIV_2 = 1u, + CY_BLE_MXD_RADIO_CLK_DIV_4 = 2u, + CY_BLE_MXD_RADIO_CLK_DIV_8 = 4u, + CY_BLE_MXD_RADIO_CLK_DIV_16 = 8u +} cy_en_ble_mxd_radio_clk_div_t; + +/** Sine wave buffer output capability select */ +typedef enum +{ + CY_BLE_MXD_RADIO_CLK_BUF_AMP_16M_SMALL = 0u, + CY_BLE_MXD_RADIO_CLK_BUF_AMP_16M_LARGE = 1u, + CY_BLE_MXD_RADIO_CLK_BUF_AMP_32M_SMALL = 2u, + CY_BLE_MXD_RADIO_CLK_BUF_AMP_32M_LARGE = 3u +} cy_en_ble_mxd_radio_clk_buf_amp_t; + +/** BLESS clock divider */ +typedef enum +{ + CY_BLE_BLESS_XTAL_CLK_DIV_1 = 0u, + CY_BLE_BLESS_XTAL_CLK_DIV_2 = 1u, + CY_BLE_BLESS_XTAL_CLK_DIV_4 = 2u, + CY_BLE_BLESS_XTAL_CLK_DIV_8 = 3u +}cy_en_ble_bless_xtal_clk_div_config_llclk_div_t; + +/** BLE ECO Clock Frequency. */ +typedef enum +{ + /** ECO Frequency of 16MHz */ + CY_BLE_BLESS_ECO_FREQ_16MHZ, + + /** ECO Frequency of 32MHz */ + CY_BLE_BLESS_ECO_FREQ_32MHZ + +} cy_en_ble_bless_eco_freq_t; + +/** BLE ECO System clock divider */ +typedef enum +{ + /** Link Layer clock divider = 1*/ + CY_BLE_SYS_ECO_CLK_DIV_1 = 0x00u, + + /** Link Layer clock divider = 2*/ + CY_BLE_SYS_ECO_CLK_DIV_2, + + /** Link Layer clock divider = 4*/ + CY_BLE_SYS_ECO_CLK_DIV_4, + + /** Link Layer clock divider = 8*/ + CY_BLE_SYS_ECO_CLK_DIV_8, + + /** Invalid Link Layer clock divider*/ + CY_BLE_SYS_ECO_CLK_DIV_INVALID + +} cy_en_ble_bless_sys_eco_clk_div_t; + +/** BLE ECO Clock return value */ +typedef enum { + /** ECO started successfully */ + CY_BLE_ECO_SUCCESS, + + /** Invalid input param values */ + CY_BLE_ECO_BAD_PARAM = CY_PDL_STATUS_ERROR | CY_BLE_CLK_ID | 0x0001u, + + /** RCB is not available for Firmware control to restart ECO */ + CY_BLE_ECO_RCB_CONTROL_LL, + + /** ECO already started */ + CY_BLE_ECO_ALREADY_STARTED + +} cy_en_ble_eco_status_t; + + +/** BLE ECO configuration parameters */ +typedef struct +{ + /** ECO crystal startup time in multiple of 31.25us (startup_time_from_user min - 31.25us) + * ecoXtalStartUpTime = startup_time_from_user/31.25 */ + uint8_t ecoXtalStartUpTime; + + /** ECO crystal load capacitance - In multiple of 0.075pF (pF_from_user min - 7.5pF, pF_from_user max - 26.625pF) + * loadcap = ((pF_from_user - 7.5)/0.075) */ + uint8_t loadCap; + + /** ECO Frequency. */ + cy_en_ble_bless_eco_freq_t ecoFreq; + + /** System divider for ECO clock */ + cy_en_ble_bless_sys_eco_clk_div_t ecoSysDiv; + +} cy_stc_ble_bless_eco_cfg_params_t; + + +/*************************************** +* Function Prototypes +***************************************/ +cy_en_ble_eco_status_t Cy_BLE_EcoStart(const cy_stc_ble_bless_eco_cfg_params_t *ecoConfig); +void Cy_BLE_EcoStop(void); + +/** @} */ + + +/*************************************** +* Private Function Prototypes +***************************************/ +uint8_t Cy_BLE_HAL_IsEcoCpuClockSrc(void); +uint8_t Cy_BLE_HAL_IsWcoLfclkSrc(void); +void Cy_BLE_HAL_Init(void); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* CY_BLE_CLK_H */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/project.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/project.h new file mode 100644 index 0000000000..6013bdc514 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/project.h @@ -0,0 +1,99 @@ +/******************************************************************************* +* File Name: project.h +* +* PSoC Creator 4.1 +* +* Description: +* It contains references to all generated header files and should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "sysint/cy_sysint.h" +#include "ipc/cy_ipc_drv.h" +#include "ipc/cy_ipc_lock.h" +#include "ipc/cy_ipc_pipe.h" +#include "sysclk/cy_sysclk.h" +#include "wdt/cy_wdt.h" +#include "tcpwm/cy_tcpwm.h" +#include "tcpwm/cy_tcpwm_counter.h" +#include "tcpwm/cy_tcpwm_pwm.h" +#include "tcpwm/cy_tcpwm_quaddec.h" +#include "scb/cy_scb_common.h" +#include "scb/cy_scb_i2c.h" +#include "scb/cy_scb_ezi2c.h" +#include "scb/cy_scb_spi.h" +#include "scb/cy_scb_uart.h" +#include "flash/cy_flash.h" +#include "gpio/cy_gpio.h" +#include "syspm/cy_syspm.h" +#include "syslib/cy_syslib.h" +#include "trigmux/cy_trigmux.h" +#include "systick/cy_systick.h" +#include "crypto/cy_crypto.h" +#include "crypto/cy_crypto_common.h" +#include "crypto/cy_crypto_server.h" +#include "crypto/cy_crypto_core_des.h" +#include "crypto/cy_crypto_core_aes.h" +#include "crypto/cy_crypto_core_cmac.h" +#include "crypto/cy_crypto_core_crc.h" +#include "crypto/cy_crypto_core_hmac.h" +#include "crypto/cy_crypto_core_instructions.h" +#include "crypto/cy_crypto_core_prng.h" +#include "crypto/cy_crypto_core_rsa.h" +#include "crypto/cy_crypto_core_sha.h" +#include "crypto/cy_crypto_core_str.h" +#include "crypto/cy_crypto_core_trng.h" +#include "crypto/cy_crypto_core_trng_config.h" +#include "crypto/cy_crypto_core_util.h" +#include "crypto/cy_crypto_core_vu.h" +#include "crypto/cy_crypto_core_vu_hw.h" +#include "profile/cy_profile.h" +#include "prot/cy_prot.h" +#include "ble/cy_ble_clk.h" +#include "cy8c637bzi_bld74.h" +#include "psoc6ble_config.h" +#include "cy_device_headers.h" +#include "gpio_psoc6ble_116_bga_ble.h" +#include "system_psoc6ble_cm0plus.h" +#include "cyip_sflash.h" +#include "cyip_peri.h" +#include "cyip_crypto.h" +#include "cyip_cpuss.h" +#include "cyip_fault.h" +#include "cyip_ipc.h" +#include "cyip_prot.h" +#include "cyip_flashc.h" +#include "cyip_srss.h" +#include "cyip_backup.h" +#include "cyip_dw.h" +#include "cyip_efuse.h" +#include "cyip_profile.h" +#include "cyip_hsiom.h" +#include "cyip_gpio.h" +#include "cyip_smartio.h" +#include "cyip_udb.h" +#include "cyip_lpcomp.h" +#include "cyip_csd.h" +#include "cyip_tcpwm.h" +#include "cyip_lcd.h" +#include "cyip_ble.h" +#include "cyip_smif.h" +#include "cyip_scb.h" +#include "cyip_ctbm.h" +#include "cyip_ctdac.h" +#include "cyip_sar.h" +#include "cyip_pass.h" +#include "cyip_i2s.h" +#include "cyip_pdm.h" +#include "cyip_headers.h" +#include "cyfitter_cfg.h" +#include "cyfitter.h" + +/*[]*/ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/gpio_api.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/gpio_api.c new file mode 100644 index 0000000000..c22c50f88c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/gpio_api.c @@ -0,0 +1,153 @@ + +#include "cmsis.h" +#include "device.h" +#include "mbed_assert.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "PortNames.h" + + +void _gpio_set_dir_mode(gpio_t *obj); +uint32_t _gpio_get_cy_drive_mode(PinDirection dir, PinMode mode); + + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + + MBED_ASSERT(obj->pin != NC); + + GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(CYPRESS_PORT(obj->pin)); + uint32_t ppin = CYPRESS_PIN(obj->pin); + + const cy_stc_gpio_pin_config_t config = { + .outVal = 0x01, // must be 1 for DigitalIn to work. Does not seems to influence DigitalOut. Tested with PullDefault = PullUp + .driveMode = _gpio_get_cy_drive_mode(obj->dir, obj->mode), + .hsiom = HSIOM_SEL_GPIO, + }; + Cy_GPIO_Pin_Init(port, ppin, &config); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + MBED_ASSERT(obj->pin != NC); + + obj->mode = mode; + _gpio_set_dir_mode(obj); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + MBED_ASSERT(obj->pin != NC); + + obj->dir = direction; + _gpio_set_dir_mode(obj); +} + +void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->pin != NC); + + GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(CYPRESS_PORT(obj->pin)); + uint32_t pin = CYPRESS_PIN(obj->pin); + + Cy_GPIO_Write(port, pin, value); +} + +/* + Return an integer representing the output setting of the pin if it is an + output, or read the input if set as an input. + (From DigitalOut::read) +*/ +int gpio_read(gpio_t *obj) +{ + int ret = 0; + + MBED_ASSERT(obj->pin != NC); + + GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(CYPRESS_PORT(obj->pin)); + uint32_t pin = CYPRESS_PIN(obj->pin); + + switch (obj->dir) { + case PIN_INPUT: + ret = Cy_GPIO_Read(port, pin); + break; + + case PIN_OUTPUT: + ret = Cy_GPIO_ReadOut(port, pin); + break; + } + + return ret; +} + +int gpio_is_connected(const gpio_t *obj) +{ + return obj->pin != NC; +} + +void _gpio_set_dir_mode(gpio_t *obj) +{ + MBED_ASSERT(obj->pin != NC); + + GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(CYPRESS_PORT(obj->pin)); + uint32_t pin = CYPRESS_PIN(obj->pin); + uint32_t cymode = _gpio_get_cy_drive_mode(obj->dir, obj->mode); + + Cy_GPIO_SetDrivemode(port, pin, cymode); +} + +uint32_t _gpio_get_cy_drive_mode(PinDirection dir, PinMode mode) +{ + uint32_t cymode = 0; + + switch (dir) { + case PIN_INPUT: + switch (mode) { + case PullNone: + cymode = CY_GPIO_DM_STRONG; + break; + case PullUp: + cymode = CY_GPIO_DM_PULLUP; + break; + case PullDown: + cymode = CY_GPIO_DM_PULLDOWN; + break; + case OpenDrainPullUp: + cymode = CY_GPIO_DM_OD_DRIVESHIGH; + break; + case OpenDrainNoPull: + cymode = CY_GPIO_DM_STRONG; + break; + case OpenDrainPullDown: + cymode = CY_GPIO_DM_OD_DRIVESLOW; + break; + } + break; + + case PIN_OUTPUT: + switch (mode) { + case PullNone: + cymode = CY_GPIO_DM_STRONG_IN_OFF; + break; + case PullUp: + cymode = CY_GPIO_DM_PULLUP_IN_OFF; + break; + case PullDown: + cymode = CY_GPIO_DM_PULLDOWN_IN_OFF; + break; + case OpenDrainPullUp: + cymode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF; + break; + case OpenDrainNoPull: + cymode = CY_GPIO_DM_STRONG_IN_OFF; + break; + case OpenDrainPullDown: + cymode = CY_GPIO_DM_OD_DRIVESLOW_IN_OFF; + break; + } + break; + } + + return cymode; +} diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/objects.h b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/objects.h new file mode 100644 index 0000000000..04acee707d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/objects.h @@ -0,0 +1,120 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) XXXX + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "PortNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + PinDirection dir; + PinMode mode; +} gpio_t; + +// struct gpio_irq_s { +// IRQn_Type irq_n; +// uint32_t irq_index; +// uint32_t event; +// PinName pin; +// uint32_t pin_index; +// uint32_t pin_num; +// uint32_t port_num; +// uint32_t rise_null; +// uint32_t fall_null; +// }; + +// struct port_s { +// PortName port; +// uint32_t mask; +// PinDirection direction; +// __IO uint32_t *reg_in; +// __IO uint32_t *reg_out; +// }; + +// struct analogin_s { +// ADCName adc; +// PinName pin; +// uint32_t channel; +// }; + +struct serial_s { + CySCB_Type *base; + PinName pin_rx; + PinName pin_tx; +}; + +// struct spi_s { +// SSP_TypeDef *spi; +// }; + +// struct i2c_s { +// I2CName I2Cx; +// PinName sda; +// PinName scl; +// uint16_t ADDRESS; +// uint16_t is_setAddress; +// }; + +// struct pwmout_s { +// PWM_CHn_TypeDef * PWM_CHx; +// PinName pin; +// uint32_t period; +// uint32_t pulse; +// uint32_t PrescalerValue; +// }; + +// struct dac_s { +// DACName dac; +// PinName pin; +// uint32_t channel; +// }; + +// struct can_s { +// CANName can; +// int index; +// }; + +// struct trng_s { +// RNG_HandleTypeDef handle; +// }; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/serial_api.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/serial_api.c new file mode 100644 index 0000000000..40418a30aa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/serial_api.c @@ -0,0 +1,219 @@ + +#if DEVICE_SERIAL + +#include + +#include "cmsis.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "PeripheralPins.h" +#include "pinmap.h" + +#include "serial_api.h" + + +serial_t stdio_uart; +int stdio_uart_inited = 0; + + +void serial_init_clock(serial_t *obj, uint32_t baudrate) +{ + uint32_t periClk = 50*1000*1000; // UART uses periClk (50 MHz) + uint32_t oversample = 12; // this must match the cy_stc_scb_uart_config_t cy_UART_config.oversample in serial_init_periph() + + uint32_t divider = periClk/(oversample*baudrate); + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0, divider); + Cy_SysClk_PeriphPhaseAlignDivider(CY_SYSCLK_DIV_16_BIT, 0, CY_SYSCLK_DIV_24_5_BIT, 0xFF); +} + +/* + Returns the UART's SCBx_BASE corresponding to the pin, NULL if not found. +*/ +CySCB_Type *pin_to_scb(PinName pin) +{ + switch (pin) { + case P0_2: // P0_2_SCB0_UART_RX + case P0_3: // P0_3_SCB0_UART_TX + return SCB0; + break; + + case P10_0: // P10_0_SCB1_UART_RX + case P10_1: // P10_1_SCB1_UART_TX + return SCB1; + break; + + case P9_0: // P9_0_SCB2_UART_RX + case P9_1: // P9_1_SCB2_UART_TX + return SCB2; + break; + + case P6_0: // P6_0_SCB3_UART_RX + case P6_1: // P6_1_SCB3_UART_TX + return SCB3; + break; + + case P7_0: // P7_0_SCB4_UART_RX + case P7_1: // P7_1_SCB4_UART_TX + case P8_0: // P8_0_SCB4_UART_RX + case P8_1: // P8_1_SCB4_UART_TX + return SCB4; + break; + + case P5_0: // P5_0_SCB5_UART_RX + case P5_1: // P5_1_SCB5_UART_TX + case P11_0: // P11_0_SCB5_UART_RX + case P11_1: // P11_1_SCB5_UART_TX + return SCB5; + break; + + case P12_0: // P12_0_SCB6_UART_RX + case P12_1: // P12_1_SCB6_UART_TX + case P13_0: // P13_0_SCB6_UART_RX + case P13_1: // P13_1_SCB6_UART_TX + case P6_4: // P6_4_SCB6_UART_RX + case P6_5: // P6_5_SCB6_UART_TX + return SCB6; + break; + + case P1_0: // P1_0_SCB7_UART_RX + case P1_1: // P1_1_SCB7_UART_TX + return SCB7; + break; + + default: + return NULL; + break; + } +} + +void serial_init_pins(serial_t *obj, PinName tx, PinName rx) +{ + CySCB_Type *scb_tx = NULL, *scb_rx = NULL; + GPIO_PRT_Type *port = NULL; + uint32_t pin = 0; + + obj->pin_tx = tx; + obj->pin_rx = rx; + + scb_tx = pin_to_scb(tx); + scb_rx = pin_to_scb(rx); + + if ((scb_tx == NULL) || (scb_rx == NULL)) + error("Invalid Serial pinout. Try another TX or RX pin."); + + if (scb_tx != scb_rx) + error("Serial pinout mismatch. Requested pins Rx and Tx can't be used for the same Serial communication."); + + obj->base = scb_tx; + + // init tx + port = Cy_GPIO_PortToAddr(CYPRESS_PORT(obj->pin_tx)); + pin = CYPRESS_PIN(obj->pin_tx); + cy_stc_gpio_pin_config_t config_tx = { + .outVal = 0x01, + .driveMode = 6, + .hsiom = HSIOM_SEL_ACT_6, + }; + Cy_GPIO_Pin_Init(port, pin, &config_tx); + + // init rx + port = Cy_GPIO_PortToAddr(CYPRESS_PORT(obj->pin_rx)); + pin = CYPRESS_PIN(obj->pin_rx); + cy_stc_gpio_pin_config_t config_rx = { + .outVal = 0x01, + .driveMode = 8, + .hsiom = HSIOM_SEL_ACT_6, + }; + Cy_GPIO_Pin_Init(port, pin, &config_rx); +} + +void serial_init_periph(serial_t *obj) +{ + cy_stc_scb_uart_config_t cy_UART_config = + { + .uartMode = CY_SCB_UART_STANDARD, + .enableMutliProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + + .oversample = 12UL, + + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + + .rxFifoTriggerLevel = 0UL, + .rxFifoIntEnableMask = 0x0UL, + + .txFifoTriggerLevel = 0UL, + .txFifoIntEnableMask = 0x0UL + }; + + Cy_SCB_UART_Init(obj->base, &cy_UART_config, NULL); + Cy_SCB_UART_Enable(obj->base); +} + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + if (stdio_uart_inited) + return; + stdio_uart_inited = 1; + + serial_init_clock(obj, 9600); + serial_init_pins(obj, tx, rx); + serial_init_periph(obj); +} + +void serial_baud(serial_t *obj, int baudrate) +{ + serial_init_clock(obj, baudrate); + serial_init_periph(obj); +} + +void serial_putc(serial_t *obj, int c) +{ + while (!serial_writable(obj)) + ; + Cy_SCB_UART_Put(obj->base, c); +} + +int serial_getc(serial_t *obj) +{ + while (!serial_readable(obj)) + ; + return Cy_SCB_UART_Get(obj->base); +} + +int serial_readable(serial_t *obj) +{ + return Cy_SCB_GetNumInRxFifo(obj->base) != 0; +} + +int serial_writable(serial_t *obj) +{ + return Cy_SCB_GetNumInTxFifo(obj->base) != Cy_SCB_GetFifoSize(obj->base); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + +} + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/us_ticker.c b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/us_ticker.c new file mode 100644 index 0000000000..c6f65934b1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/us_ticker.c @@ -0,0 +1,129 @@ + +#include +#include "PeripheralNames.h" +#include "us_ticker_api.h" + + +#define CY_Counter_TCPWM_CNT_HW TCPWM0_CNT0 +#define CY_Counter_TCPWM_CNT_IDX 0u +#define CY_Counter_TCPWM_HW TCPWM0 +#define CY_Counter_TCPWM_IDX 0u + +#define CY_Counter_INIT_COMPARE_OR_CAPTURE (0uL) + +/** This is a ptr to the base address of the TCPWM instance */ +#define CY_Counter_HW (CY_Counter_TCPWM_HW) + +/** This is a ptr to the base address of the TCPWM CNT instance */ +#define CY_Counter_CNT_HW (CY_Counter_TCPWM_CNT_HW) + +/** This is the counter instance number in the selected TCPWM */ +#define CY_Counter_CNT_NUM (CY_Counter_TCPWM_CNT_IDX) + +/** This is the bit field representing the counter instance in the selected TCPWM */ +#define CY_Counter_CNT_MASK (1uL << CY_Counter_CNT_NUM) + +#define CY_Counter_INPUT_MODE_MASK (0x3u) + + +#define CY_SysInt_INTC_CORTEXM0P_ASSIGNED 1 +#define CY_SysInt_INTC_CORTEXM0P_MUX 0u +#define CY_SysInt_INTC_CORTEXM0P_PRIORITY 3u +#define CY_SysInt_INTC_NUMBER 82u + +#define CY_SysInt_INTR_CORTEXM0P_SRC (CY_SysInt_INTC_NUMBER) +#define CY_SysInt_INTR_CORTEXM0P_PRIORITY (CY_SysInt_INTC_CORTEXM0P_PRIORITY) +#define CY_SysInt_INTR_CORTEXM0P_MUX (CY_SysInt_INTC_CORTEXM0P_MUX) + + +cy_stc_sysint_t cy_SysInt_cfg_cm0p = { + .intrSrc = (IRQn_Type)CY_SysInt_INTR_CORTEXM0P_SRC, + .intrCm0p = (IRQn_CM0P_Type)CY_SysInt_INTR_CORTEXM0P_MUX, + .intrPriority = CY_SysInt_INTR_CORTEXM0P_PRIORITY +}; + +int us_ticker_inited = 0; + + +void irq_handler(void) +{ + us_ticker_clear_interrupt(); + us_ticker_irq_handler(); +} + +void us_ticker_init(void) +{ + cy_stc_tcpwm_counter_config_t cy_counter_config = + { + .period = 4294967295uL, + .clockPrescaler = 0uL, + .runMode = 0uL, + .countDirection = 0uL, + .compareOrCapture = CY_Counter_INIT_COMPARE_OR_CAPTURE, + .compare0 = 0uL, + .compare1 = 0uL, + .enableCompareSwap = false, + .interruptSources = CY_TCPWM_INT_ON_CC, + .captureInputMode = 7uL & CY_Counter_INPUT_MODE_MASK, + .captureInput = CY_TCPWM_INPUT_CREATOR, + .reloadInputMode = 7uL & CY_Counter_INPUT_MODE_MASK, + .reloadInput = CY_TCPWM_INPUT_CREATOR, + .startInputMode = 7uL & CY_Counter_INPUT_MODE_MASK, + .startInput = CY_TCPWM_INPUT_CREATOR, + .stopInputMode = 7uL & CY_Counter_INPUT_MODE_MASK, + .stopInput = CY_TCPWM_INPUT_CREATOR, + .countInputMode = 7uL & CY_Counter_INPUT_MODE_MASK, + .countInput = CY_TCPWM_INPUT_CREATOR, + }; + + if (us_ticker_inited) + return; + us_ticker_inited = 1; + + /* + Configure the clock + */ + + // us_ticker 1 MHz from PCLK 50 MHz + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 49u); + Cy_SysClk_PeriphPhaseAlignDivider(CY_SYSCLK_DIV_8_BIT, 0u, CY_SYSCLK_DIV_24_5_BIT, 0xFF); + + /* + Configure the counter + */ + + Cy_TCPWM_Counter_Init(CY_Counter_HW, CY_Counter_CNT_NUM, &cy_counter_config); + Cy_TCPWM_Enable_Multiple(CY_Counter_HW, CY_Counter_CNT_MASK); + Cy_TCPWM_TriggerStart(CY_Counter_HW, CY_Counter_CNT_MASK); + + Cy_SysInt_Init(&cy_SysInt_cfg_cm0p, irq_handler); +} + +uint32_t us_ticker_read(void) +{ + if (!us_ticker_inited) + us_ticker_init(); + return Cy_TCPWM_Counter_GetCounter(CY_Counter_HW, CY_Counter_CNT_NUM); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + if (!us_ticker_inited) + us_ticker_init(); + + // Set new output compare value + Cy_TCPWM_Counter_SetCompare0(CY_Counter_HW, CY_Counter_CNT_NUM, timestamp); + // Enable int + NVIC_EnableIRQ((IRQn_Type)cy_SysInt_cfg_cm0p.intrCm0p); +} + +void us_ticker_disable_interrupt(void) +{ + NVIC_DisableIRQ((IRQn_Type)cy_SysInt_cfg_cm0p.intrCm0p); +} + +void us_ticker_clear_interrupt(void) +{ + Cy_TCPWM_ClearInterrupt(CY_Counter_HW, CY_Counter_CNT_NUM, CY_TCPWM_INT_ON_CC); +} diff --git a/targets/TARGET_Cypress/mbed_rtx.h b/targets/TARGET_Cypress/mbed_rtx.h new file mode 100644 index 0000000000..f16e7bb69f --- /dev/null +++ b/targets/TARGET_Cypress/mbed_rtx.h @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 u-blox + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#if defined(TARGET_PSoC6_CY8C_CM0p) + + #ifndef INITIAL_SP + #define INITIAL_SP (0x08000000 + 0x00024000) // Ram origin + length + #endif + +#else + + #error "Unknown board" + +#endif + +#endif // MBED_MBED_RTX_H From ec22815fee27f59def503b46d8346bf0d125b1ff Mon Sep 17 00:00:00 2001 From: Leszek Rusinowicz Date: Mon, 16 Oct 2017 16:01:40 +0200 Subject: [PATCH 2/9] Initial version with support for PSoC 6 CY8C63XX and both cores using updated PDL 3.0.1 beta. --- .../PeripheralNames.h | 0 .../PeripheralPins.h | 0 .../PinNamesTypes.h | 0 .../PortNames.h | 0 .../TARGET_PSoC6/TARGET_CY8C63XX/BLE_config.h | 330 ++ .../PeripheralPins.c | 0 .../TARGET_CY8CKIT_062_BLE_M0}/PinNames.h | 0 .../cy_ble_stack_mdk_controller_ipc_cm0p.a | Bin 0 -> 814258 bytes .../cy_ble_stack_mdk_controller_uart_cm0p.a | Bin 0 -> 805922 bytes .../cy_ble_stack_mdk_host_ipc_cm0p.a | Bin 0 -> 745418 bytes .../cy_ble_stack_mdk_host_uart_cm0p.a | Bin 0 -> 738318 bytes .../cy_ble_stack_mdk_radio_max_cm0p.a | Bin 0 -> 53906 bytes .../cy_ble_stack_mdk_soc_cm0p.a | Bin 0 -> 1496018 bytes .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld} | 160 +- .../libble_stack_gcc_controller_ipc_cm0p.a | Bin 0 -> 815250 bytes .../libble_stack_gcc_radio_max_cm0p.a | Bin 0 -> 54002 bytes .../startup_psoc63_cm0plus.S} | 141 +- .../system_psoc63_cm0plus.c} | 594 ++-- .../PeripheralPins.c | 131 + .../TARGET_CY8CKIT_062_BLE_M4/PinNames.h | 251 ++ .../cy_ble_stack_mdk_controller_ipc_cm4.a | Bin 0 -> 820884 bytes .../cy_ble_stack_mdk_controller_uart_cm4.a | Bin 0 -> 812496 bytes .../cy_ble_stack_mdk_host_ipc_cm4.a | Bin 0 -> 751250 bytes .../cy_ble_stack_mdk_host_uart_cm4.a | Bin 0 -> 744146 bytes .../cy_ble_stack_mdk_radio_max_cm4.a | Bin 0 -> 53890 bytes .../cy_ble_stack_mdk_soc_cm4.a | Bin 0 -> 1507342 bytes .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 381 +++ .../libcy_ble_stack_gcc_host_ipc_cm4.a | Bin 0 -> 752754 bytes .../TOOLCHAIN_GCC_ARM/startup_psoc63_cm4.S | 646 ++++ .../system_psoc63_cm4.c | 430 +++ .../TARGET_CY8C63XX}/device.h | 2 +- .../libcy_crypto_client_gcc.a | Bin 0 -> 10040 bytes .../libcy_crypto_server_gcc_base.a | Bin 0 -> 20240 bytes .../libcy_crypto_server_gcc_extra.a | Bin 0 -> 29300 bytes .../libcy_crypto_server_gcc_full.a | Bin 0 -> 37358 bytes .../TARGET_CY8C63XX}/device/cmsis.h | 3 +- .../device/cy8c6347bzi_bld53.h | 1285 +++++++ .../device/cy_device_headers.h | 61 + .../device/gpio_psoc63_116_bga_ble.h | 1808 ++++++++++ .../device/gpio_psoc6ble_116_bga_ble.h | 0 .../TARGET_CY8C63XX/device/psoc63_config.h | 2394 +++++++++++++ .../TARGET_CY8C63XX}/device/psoc6ble_config.h | 0 .../TARGET_CY8C63XX/device/system_psoc63.h | 494 +++ .../drivers/peripheral/crypto/cy_crypto.h | 1678 +++++++++ .../peripheral/crypto/cy_crypto_common.h | 727 ++++ .../peripheral/crypto/cy_crypto_config.c | 69 + .../peripheral/crypto/cy_crypto_config.h | 57 + .../peripheral/crypto/cy_crypto_server.h | 125 + .../device/drivers/peripheral/ctb/cy_ctb.c | 1311 ++++++++ .../device/drivers/peripheral/ctb/cy_ctb.h | 1334 ++++++++ .../drivers/peripheral/ctdac/cy_ctdac.c | 656 ++++ .../drivers/peripheral/ctdac/cy_ctdac.h | 891 +++++ .../device/drivers/peripheral/dma/cy_dma.c | 318 ++ .../device/drivers/peripheral/dma/cy_dma.h | 1811 ++++++++++ .../drivers/peripheral/flash/cy_flash.c | 886 +++++ .../drivers/peripheral}/flash/cy_flash.h | 215 +- .../device/drivers/peripheral}/gpio/cy_gpio.c | 10 +- .../device/drivers/peripheral}/gpio/cy_gpio.h | 119 +- .../device/drivers/peripheral/i2s/cy_i2s.c | 275 ++ .../device/drivers/peripheral/i2s/cy_i2s.h | 974 ++++++ .../drivers/peripheral/ipc/cy_ipc_config.c | 143 + .../drivers/peripheral/ipc/cy_ipc_config.h | 137 + .../drivers/peripheral/ipc/cy_ipc_drv.c | 172 + .../drivers/peripheral/ipc/cy_ipc_drv.h | 900 +++++ .../drivers/peripheral/ipc/cy_ipc_pipe.c | 515 +++ .../drivers/peripheral/ipc/cy_ipc_pipe.h | 266 ++ .../drivers/peripheral/ipc/cy_ipc_sema.c | 369 ++ .../drivers/peripheral/ipc/cy_ipc_sema.h | 116 + .../drivers/peripheral/lpcomp/cy_lpcomp.c | 545 +++ .../drivers/peripheral/lpcomp/cy_lpcomp.h | 687 ++++ .../device/drivers/peripheral/lvd/cy_lvd.c | 64 + .../device/drivers/peripheral/lvd/cy_lvd.h | 423 +++ .../drivers/peripheral/mcwdt/cy_mcwdt.c | 100 + .../drivers/peripheral/mcwdt/cy_mcwdt.h | 997 ++++++ .../drivers/peripheral/pdm_pcm/cy_pdm_pcm.c | 240 ++ .../drivers/peripheral/pdm_pcm/cy_pdm_pcm.h | 729 ++++ .../drivers/peripheral}/profile/cy_profile.c | 130 +- .../drivers/peripheral/profile/cy_profile.h | 376 +++ .../device/drivers/peripheral}/prot/cy_prot.c | 506 +-- .../device/drivers/peripheral}/prot/cy_prot.h | 77 +- .../device/drivers/peripheral/rtc/cy_rtc.c | 1694 ++++++++++ .../device/drivers/peripheral/rtc/cy_rtc.h | 1273 +++++++ .../device/drivers/peripheral/sar/cy_sar.c | 1190 +++++++ .../device/drivers/peripheral/sar/cy_sar.h | 1744 ++++++++++ .../drivers/peripheral}/scb/cy_scb_common.c | 48 +- .../drivers/peripheral}/scb/cy_scb_common.h | 336 +- .../drivers/peripheral}/scb/cy_scb_ezi2c.c | 650 ++-- .../drivers/peripheral/scb/cy_scb_ezi2c.h | 491 +++ .../drivers/peripheral}/scb/cy_scb_i2c.c | 1230 ++++--- .../drivers/peripheral}/scb/cy_scb_i2c.h | 713 ++-- .../drivers/peripheral}/scb/cy_scb_spi.c | 465 ++- .../drivers/peripheral}/scb/cy_scb_spi.h | 635 ++-- .../drivers/peripheral}/scb/cy_scb_uart.c | 495 ++- .../drivers/peripheral}/scb/cy_scb_uart.h | 611 ++-- .../device/drivers/peripheral/smif/cy_smif.c | 1409 ++++++++ .../device/drivers/peripheral/smif/cy_smif.h | 1401 ++++++++ .../drivers/peripheral/smif/cy_smif_memslot.c | 1375 ++++++++ .../drivers/peripheral/smif/cy_smif_memslot.h | 425 +++ .../peripheral/sysanalog/cy_sysanalog.c | 102 + .../peripheral/sysanalog/cy_sysanalog.h | 561 ++++ .../drivers/peripheral}/sysclk/cy_sysclk.c | 1138 ++++--- .../drivers/peripheral/sysclk/cy_sysclk.h | 2553 ++++++++++++++ .../drivers/peripheral}/sysint/cy_sysint.c | 227 +- .../drivers/peripheral}/sysint/cy_sysint.h | 230 +- .../syslib/TOOLCHAIN_ARM_STD/cy_syslib_mdk.s | 100 + .../syslib}/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S | 4 +- .../syslib/TOOLCHAIN_IAR/cy_syslib_iar.s | 89 + .../drivers/peripheral}/syslib/cy_syslib.c | 527 +-- .../drivers/peripheral/syslib/cy_syslib.h | 924 +++++ .../drivers/peripheral/syspm/cy_syspm.c | 2064 ++++++++++++ .../drivers/peripheral/syspm/cy_syspm.h | 1734 ++++++++++ .../drivers/peripheral}/systick/cy_systick.c | 181 +- .../drivers/peripheral/systick/cy_systick.h | 284 ++ .../drivers/peripheral}/tcpwm/cy_tcpwm.h | 240 +- .../peripheral}/tcpwm/cy_tcpwm_counter.c | 46 +- .../peripheral}/tcpwm/cy_tcpwm_counter.h | 89 +- .../drivers/peripheral}/tcpwm/cy_tcpwm_pwm.c | 43 +- .../drivers/peripheral}/tcpwm/cy_tcpwm_pwm.h | 176 +- .../peripheral}/tcpwm/cy_tcpwm_quaddec.c | 26 +- .../peripheral}/tcpwm/cy_tcpwm_quaddec.h | 51 +- .../drivers/peripheral}/trigmux/cy_trigmux.c | 82 +- .../drivers/peripheral}/trigmux/cy_trigmux.h | 140 +- .../device/drivers/peripheral}/wdt/cy_wdt.c | 170 +- .../device/drivers/peripheral/wdt/cy_wdt.h | 362 ++ .../TARGET_PSoC6/device/ip/cyip_backup.h | 225 ++ .../TARGET_PSoC6/device/ip/cyip_ble.h | 2246 +++++++++++++ .../TARGET_PSoC6/device/ip/cyip_cpuss.h | 332 ++ .../TARGET_PSoC6/device/ip/cyip_crypto.h | 35 + .../TARGET_PSoC6/device/ip/cyip_csd.h | 477 +++ .../TARGET_PSoC6/device/ip/cyip_ctbm.h | 287 ++ .../TARGET_PSoC6/device/ip/cyip_ctdac.h | 105 + .../TARGET_PSoC6/device/ip/cyip_dw.h | 171 + .../TARGET_PSoC6/device/ip/cyip_efuse.h | 318 ++ .../TARGET_PSoC6/device/ip/cyip_fault.h | 113 + .../TARGET_PSoC6/device/ip/cyip_flashc.h | 570 ++++ .../TARGET_PSoC6/device/ip/cyip_gpio.h | 468 +++ .../device/ip/cyip_headers.h | 7 +- .../TARGET_PSoC6/device/ip/cyip_hsiom.h | 110 + .../TARGET_PSoC6/device/ip/cyip_i2s.h | 280 ++ .../TARGET_PSoC6/device/ip/cyip_ipc.h | 123 + .../TARGET_PSoC6/device/ip/cyip_lcd.h | 92 + .../TARGET_PSoC6/device/ip/cyip_lpcomp.h | 171 + .../TARGET_PSoC6/device/ip/cyip_pass.h | 130 + .../TARGET_PSoC6/device/ip/cyip_pdm.h | 161 + .../TARGET_PSoC6/device/ip/cyip_peri.h | 482 +++ .../TARGET_PSoC6/device/ip/cyip_profile.h | 105 + .../TARGET_PSoC6/device/ip/cyip_prot.h | 374 +++ .../TARGET_PSoC6/device/ip/cyip_sar.h | 627 ++++ .../TARGET_PSoC6/device/ip/cyip_scb.h | 757 +++++ .../TARGET_PSoC6/device/ip/cyip_sflash.h | 394 +++ .../TARGET_PSoC6/device/ip/cyip_smartio.h | 109 + .../TARGET_PSoC6/device/ip/cyip_smif.h | 378 +++ .../TARGET_PSoC6/device/ip/cyip_srss.h | 601 ++++ .../TARGET_PSoC6/device/ip/cyip_tcpwm.h | 191 ++ .../TARGET_PSoC6/device/ip/cyip_udb.h | 2026 +++++++++++ .../TARGET_PSoC6/device/ip/cyip_usbfs.h | 1770 ++++++++++ .../device/middleware/ble/cy_ble.c | 657 ++++ .../device/middleware/ble/cy_ble.h | 410 +++ .../device/middleware/ble/cy_ble_aios.c | 2325 +++++++++++++ .../device/middleware/ble/cy_ble_aios.h | 319 ++ .../device/middleware/ble/cy_ble_ancs.c | 1359 ++++++++ .../device/middleware/ble/cy_ble_ancs.h | 206 ++ .../device/middleware/ble/cy_ble_ans.c | 1413 ++++++++ .../device/middleware/ble/cy_ble_ans.h | 235 ++ .../device/middleware/ble/cy_ble_bas.c | 1189 +++++++ .../device/middleware/ble/cy_ble_bas.h | 230 ++ .../device/middleware/ble/cy_ble_bcs.c | 1252 +++++++ .../device/middleware/ble/cy_ble_bcs.h | 208 ++ .../device/middleware/ble/cy_ble_bls.c | 1318 ++++++++ .../device/middleware/ble/cy_ble_bls.h | 229 ++ .../device/middleware/ble/cy_ble_bms.c | 1362 ++++++++ .../device/middleware/ble/cy_ble_bms.h | 223 ++ .../device/middleware/ble/cy_ble_bts.c | 509 +++ .../device/middleware/ble/cy_ble_bts.h | 125 + .../device/middleware/ble/cy_ble_cgms.c | 1612 +++++++++ .../device/middleware/ble/cy_ble_cgms.h | 246 ++ .../device/middleware/ble/cy_ble_clk.c | 627 ++++ .../device/middleware/ble/cy_ble_clk.h | 239 ++ .../device/middleware/ble/cy_ble_cps.c | 2226 ++++++++++++ .../device/middleware/ble/cy_ble_cps.h | 483 +++ .../device/middleware/ble/cy_ble_cscs.c | 1749 ++++++++++ .../device/middleware/ble/cy_ble_cscs.h | 236 ++ .../device/middleware/ble/cy_ble_cts.c | 1624 +++++++++ .../device/middleware/ble/cy_ble_cts.h | 316 ++ .../device/middleware/ble/cy_ble_custom.c | 513 +++ .../device/middleware/ble/cy_ble_custom.h | 193 ++ .../device/middleware/ble/cy_ble_dis.c | 561 ++++ .../device/middleware/ble/cy_ble_dis.h | 179 + .../device/middleware/ble/cy_ble_ds.h | 1728 ++++++++++ .../device/middleware/ble/cy_ble_ess.c | 2991 +++++++++++++++++ .../device/middleware/ble/cy_ble_ess.h | 439 +++ .../middleware/ble/cy_ble_event_handler.c | 1611 +++++++++ .../middleware/ble/cy_ble_event_handler.h | 2583 ++++++++++++++ .../device/middleware/ble/cy_ble_gap.c | 1440 ++++++++ .../device/middleware/ble/cy_ble_gap.h | 867 +++++ .../device/middleware/ble/cy_ble_gatt.c | 800 +++++ .../device/middleware/ble/cy_ble_gatt.h | 994 ++++++ .../device/middleware/ble/cy_ble_gls.c | 1505 +++++++++ .../device/middleware/ble/cy_ble_gls.h | 230 ++ .../device/middleware/ble/cy_ble_hal_int.c | 133 + .../device/middleware/ble/cy_ble_hal_pvt.c | 1557 +++++++++ .../device/middleware/ble/cy_ble_hal_pvt.h | 179 + .../device/middleware/ble/cy_ble_hids.c | 2134 ++++++++++++ .../device/middleware/ble/cy_ble_hids.h | 452 +++ .../device/middleware/ble/cy_ble_hps.c | 1877 +++++++++++ .../device/middleware/ble/cy_ble_hps.h | 247 ++ .../device/middleware/ble/cy_ble_hrs.c | 1270 +++++++ .../device/middleware/ble/cy_ble_hrs.h | 209 ++ .../device/middleware/ble/cy_ble_hts.c | 1551 +++++++++ .../device/middleware/ble/cy_ble_hts.h | 276 ++ .../device/middleware/ble/cy_ble_ias.c | 498 +++ .../device/middleware/ble/cy_ble_ias.h | 143 + .../device/middleware/ble/cy_ble_ips.c | 2273 +++++++++++++ .../device/middleware/ble/cy_ble_ips.h | 305 ++ .../device/middleware/ble/cy_ble_lls.c | 709 ++++ .../device/middleware/ble/cy_ble_lls.h | 145 + .../device/middleware/ble/cy_ble_lns.c | 1566 +++++++++ .../device/middleware/ble/cy_ble_lns.h | 248 ++ .../device/middleware/ble/cy_ble_ndcs.c | 504 +++ .../device/middleware/ble/cy_ble_ndcs.h | 142 + .../device/middleware/ble/cy_ble_pass.c | 1335 ++++++++ .../device/middleware/ble/cy_ble_pass.h | 249 ++ .../device/middleware/ble/cy_ble_plxs.c | 1699 ++++++++++ .../device/middleware/ble/cy_ble_plxs.h | 393 +++ .../device/middleware/ble/cy_ble_rscs.c | 1677 +++++++++ .../device/middleware/ble/cy_ble_rscs.h | 225 ++ .../device/middleware/ble/cy_ble_rtus.c | 678 ++++ .../device/middleware/ble/cy_ble_rtus.h | 179 + .../device/middleware/ble/cy_ble_scps.c | 1170 +++++++ .../device/middleware/ble/cy_ble_scps.h | 210 ++ .../device/middleware/ble/cy_ble_stack.h | 2160 ++++++++++++ .../device/middleware/ble/cy_ble_stack_gap.h | 1910 +++++++++++ .../middleware/ble/cy_ble_stack_gap_central.h | 653 ++++ .../ble/cy_ble_stack_gap_peripheral.h | 391 +++ .../device/middleware/ble/cy_ble_stack_gatt.h | 585 ++++ .../middleware/ble/cy_ble_stack_gatt_client.h | 1567 +++++++++ .../middleware/ble/cy_ble_stack_gatt_db.h | 615 ++++ .../middleware/ble/cy_ble_stack_gatt_server.h | 358 ++ .../middleware/ble/cy_ble_stack_host_error.h | 301 ++ .../middleware/ble/cy_ble_stack_host_main.h | 2272 +++++++++++++ .../middleware/ble/cy_ble_stack_l2cap.h | 830 +++++ .../device/middleware/ble/cy_ble_stack_pvt.h | 148 + .../device/middleware/ble/cy_ble_tps.c | 1091 ++++++ .../device/middleware/ble/cy_ble_tps.h | 206 ++ .../device/middleware/ble/cy_ble_uds.c | 2099 ++++++++++++ .../device/middleware/ble/cy_ble_uds.h | 259 ++ .../device/middleware/ble/cy_ble_wpts.c | 1598 +++++++++ .../device/middleware/ble/cy_ble_wpts.h | 246 ++ .../device/middleware/ble/cy_ble_wss.c | 1473 ++++++++ .../device/middleware/ble/cy_ble_wss.h | 219 ++ .../middleware/em_eeprom/cy_em_eeprom.c | 1215 +++++++ .../middleware/em_eeprom/cy_em_eeprom.h | 450 +++ .../gpio_api.c | 2 +- .../{ => TARGET_PSoC6}/mbed_rtx.h | 8 +- .../objects.h | 0 .../serial_api.c | 5 +- .../TARGET_Cypress/TARGET_PSoC6/us_ticker.c | 122 + .../device/cy8c637bzi_bld74.h | 1030 ------ .../device/cy_device_headers.h | 85 - .../device/system_psoc6ble_cm0plus.h | 185 - .../device/cy_crypto_config.h | 92 - .../TARGET_PSoC6_CY8C/device/cyapicallbacks.h | 28 - .../device/cydisabledsheets.h | 5 - .../TARGET_PSoC6_CY8C/device/cyfitter.h | 6 - .../TARGET_PSoC6_CY8C/device/cyfitter_cfg.c | 271 -- .../TARGET_PSoC6_CY8C/device/cyfitter_cfg.h | 29 - .../TARGET_PSoC6_CY8C/device/cyfitter_gpio.h | 6 - .../TARGET_PSoC6_CY8C/device/cymetadata.c | 48 - .../device/driver_periph/crypto/cy_crypto.c | 1809 ---------- .../device/driver_periph/crypto/cy_crypto.h | 450 --- .../driver_periph/crypto/cy_crypto_common.h | 504 --- .../driver_periph/crypto/cy_crypto_core_aes.c | 405 --- .../driver_periph/crypto/cy_crypto_core_aes.h | 77 - .../crypto/cy_crypto_core_cmac.c | 272 -- .../crypto/cy_crypto_core_cmac.h | 72 - .../driver_periph/crypto/cy_crypto_core_crc.c | 117 - .../driver_periph/crypto/cy_crypto_core_crc.h | 41 - .../driver_periph/crypto/cy_crypto_core_des.c | 208 -- .../driver_periph/crypto/cy_crypto_core_des.h | 48 - .../crypto/cy_crypto_core_hmac.c | 244 -- .../crypto/cy_crypto_core_hmac.h | 37 - .../crypto/cy_crypto_core_instructions.h | 180 - .../crypto/cy_crypto_core_prng.c | 99 - .../crypto/cy_crypto_core_prng.h | 39 - .../driver_periph/crypto/cy_crypto_core_rsa.c | 993 ------ .../driver_periph/crypto/cy_crypto_core_rsa.h | 62 - .../driver_periph/crypto/cy_crypto_core_sha.c | 442 --- .../driver_periph/crypto/cy_crypto_core_sha.h | 115 - .../driver_periph/crypto/cy_crypto_core_str.c | 194 -- .../driver_periph/crypto/cy_crypto_core_str.h | 43 - .../crypto/cy_crypto_core_trng.c | 93 - .../crypto/cy_crypto_core_trng.h | 37 - .../crypto/cy_crypto_core_trng_config.h | 239 -- .../crypto/cy_crypto_core_util.c | 485 --- .../crypto/cy_crypto_core_util.h | 132 - .../driver_periph/crypto/cy_crypto_core_vu.c | 66 - .../driver_periph/crypto/cy_crypto_core_vu.h | 136 - .../crypto/cy_crypto_core_vu_hw.h | 380 --- .../driver_periph/crypto/cy_crypto_server.c | 409 --- .../driver_periph/crypto/cy_crypto_server.h | 51 - .../device/driver_periph/flash/cy_flash.c | 470 --- .../device/driver_periph/ipc/cy_ipc_drv.c | 464 --- .../device/driver_periph/ipc/cy_ipc_drv.h | 288 -- .../device/driver_periph/ipc/cy_ipc_lock.c | 268 -- .../device/driver_periph/ipc/cy_ipc_lock.h | 84 - .../device/driver_periph/ipc/cy_ipc_pipe.c | 345 -- .../device/driver_periph/ipc/cy_ipc_pipe.h | 191 -- .../device/driver_periph/profile/cy_profile.h | 540 --- .../device/driver_periph/scb/cy_scb_ezi2c.h | 424 --- .../device/driver_periph/sysclk/cy_sysclk.h | 2165 ------------ .../device/driver_periph/syslib/cy_syslib.h | 800 ----- .../device/driver_periph/syspm/cy_syspm.c | 1879 ----------- .../device/driver_periph/syspm/cy_syspm.h | 820 ----- .../device/driver_periph/systick/cy_systick.h | 170 - .../device/driver_periph/wdt/cy_wdt.h | 261 -- .../TARGET_PSoC6_CY8C/device/ip/cyip_backup.h | 221 -- .../TARGET_PSoC6_CY8C/device/ip/cyip_ble.h | 2219 ------------ .../TARGET_PSoC6_CY8C/device/ip/cyip_cpuss.h | 346 -- .../TARGET_PSoC6_CY8C/device/ip/cyip_crypto.h | 375 --- .../TARGET_PSoC6_CY8C/device/ip/cyip_csd.h | 473 --- .../TARGET_PSoC6_CY8C/device/ip/cyip_ctbm.h | 287 -- .../TARGET_PSoC6_CY8C/device/ip/cyip_ctdac.h | 110 - .../TARGET_PSoC6_CY8C/device/ip/cyip_dw.h | 230 -- .../TARGET_PSoC6_CY8C/device/ip/cyip_efuse.h | 318 -- .../TARGET_PSoC6_CY8C/device/ip/cyip_fault.h | 113 - .../TARGET_PSoC6_CY8C/device/ip/cyip_flashc.h | 518 --- .../TARGET_PSoC6_CY8C/device/ip/cyip_gpio.h | 468 --- .../TARGET_PSoC6_CY8C/device/ip/cyip_hsiom.h | 88 - .../TARGET_PSoC6_CY8C/device/ip/cyip_i2s.h | 280 -- .../TARGET_PSoC6_CY8C/device/ip/cyip_ipc.h | 123 - .../TARGET_PSoC6_CY8C/device/ip/cyip_lcd.h | 92 - .../TARGET_PSoC6_CY8C/device/ip/cyip_lpcomp.h | 171 - .../TARGET_PSoC6_CY8C/device/ip/cyip_pass.h | 130 - .../TARGET_PSoC6_CY8C/device/ip/cyip_pdm.h | 169 - .../TARGET_PSoC6_CY8C/device/ip/cyip_peri.h | 482 --- .../device/ip/cyip_profile.h | 105 - .../TARGET_PSoC6_CY8C/device/ip/cyip_prot.h | 374 --- .../TARGET_PSoC6_CY8C/device/ip/cyip_sar.h | 627 ---- .../TARGET_PSoC6_CY8C/device/ip/cyip_scb.h | 755 ----- .../TARGET_PSoC6_CY8C/device/ip/cyip_sflash.h | 186 - .../device/ip/cyip_smartio.h | 109 - .../TARGET_PSoC6_CY8C/device/ip/cyip_smif.h | 404 --- .../TARGET_PSoC6_CY8C/device/ip/cyip_srss.h | 655 ---- .../TARGET_PSoC6_CY8C/device/ip/cyip_tcpwm.h | 191 -- .../TARGET_PSoC6_CY8C/device/ip/cyip_udb.h | 2052 ----------- .../device/middleware/ble/cy_ble_clk.c | 491 --- .../device/middleware/ble/cy_ble_clk.h | 220 -- .../TARGET_PSoC6_CY8C/device/project.h | 99 - .../TARGET_PSoC6_CY8C/us_ticker.c | 129 - 349 files changed, 150901 insertions(+), 37341 deletions(-) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C => TARGET_PSoC6}/PeripheralNames.h (100%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C => TARGET_PSoC6}/PeripheralPins.h (100%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C => TARGET_PSoC6}/PinNamesTypes.h (100%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C => TARGET_PSoC6}/PortNames.h (100%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/BLE_config.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p => TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0}/PeripheralPins.c (100%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p => TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0}/PinNames.h (100%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_controller_ipc_cm0p.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_controller_uart_cm0p.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_host_ipc_cm0p.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_host_uart_cm0p.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_radio_max_cm0p.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_soc_cm0p.a rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/cy8c6x7_cm0plus.ld => TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld} (76%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_GCC_ARM/libble_stack_gcc_controller_ipc_cm0p.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_GCC_ARM/libble_stack_gcc_radio_max_cm0p.a rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/TOOLCHAIN_GCC_ARM/startup_psoc6ble_cm0plus.S => TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm0plus.S} (60%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/system_psoc6ble_cm0plus.c => TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/system_psoc63_cm0plus.c} (52%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/PeripheralPins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/PinNames.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_controller_ipc_cm4.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_controller_uart_cm4.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_host_ipc_cm4.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_host_uart_cm4.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_radio_max_cm4.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_soc_cm4.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_GCC_ARM/libcy_ble_stack_gcc_host_ipc_cm4.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm4.S create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/system_psoc63_cm4.c rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p => TARGET_PSoC6/TARGET_CY8C63XX}/device.h (98%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/TOOLCHAIN_GCC_ARM/libcy_crypto_client_gcc.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/TOOLCHAIN_GCC_ARM/libcy_crypto_server_gcc_base.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/TOOLCHAIN_GCC_ARM/libcy_crypto_server_gcc_extra.a create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/TOOLCHAIN_GCC_ARM/libcy_crypto_server_gcc_full.a rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p => TARGET_PSoC6/TARGET_CY8C63XX}/device/cmsis.h (93%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cy_device_headers.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p => TARGET_PSoC6/TARGET_CY8C63XX}/device/gpio_psoc6ble_116_bga_ble.h (100%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/psoc63_config.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p => TARGET_PSoC6/TARGET_CY8C63XX}/device/psoc6ble_config.h (100%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/system_psoc63.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_common.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_config.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_config.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_server.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctb/cy_ctb.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctb/cy_ctb.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctdac/cy_ctdac.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctdac/cy_ctdac.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/dma/cy_dma.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/dma/cy_dma.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/flash/cy_flash.c rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/flash/cy_flash.h (57%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/gpio/cy_gpio.c (98%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/gpio/cy_gpio.h (97%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/i2s/cy_i2s.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/i2s/cy_i2s.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_config.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_config.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_drv.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_drv.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_sema.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_sema.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lvd/cy_lvd.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lvd/cy_lvd.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/mcwdt/cy_mcwdt.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/mcwdt/cy_mcwdt.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/pdm_pcm/cy_pdm_pcm.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/pdm_pcm/cy_pdm_pcm.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/profile/cy_profile.c (81%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/profile/cy_profile.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/prot/cy_prot.c (95%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/prot/cy_prot.h (91%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/rtc/cy_rtc.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/rtc/cy_rtc.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/sar/cy_sar.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/sar/cy_sar.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/scb/cy_scb_common.c (90%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/scb/cy_scb_common.h (80%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/scb/cy_scb_ezi2c.c (58%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/scb/cy_scb_ezi2c.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/scb/cy_scb_i2c.c (72%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/scb/cy_scb_i2c.h (55%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/scb/cy_scb_spi.c (59%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/scb/cy_scb_spi.h (64%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/scb/cy_scb_uart.c (69%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/scb/cy_scb_uart.h (67%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/smif/cy_smif.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/smif/cy_smif.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/smif/cy_smif_memslot.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/smif/cy_smif_memslot.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/sysanalog/cy_sysanalog.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/sysanalog/cy_sysanalog.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/sysclk/cy_sysclk.c (50%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/sysclk/cy_sysclk.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/sysint/cy_sysint.c (52%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/sysint/cy_sysint.h (51%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/syslib/TOOLCHAIN_ARM_STD/cy_syslib_mdk.s rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device => TARGET_PSoC6/device/drivers/peripheral/syslib}/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S (97%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/syslib/TOOLCHAIN_IAR/cy_syslib_iar.s rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/syslib/cy_syslib.c (50%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/syslib/cy_syslib.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/syspm/cy_syspm.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/syspm/cy_syspm.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/systick/cy_systick.c (57%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/systick/cy_systick.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/tcpwm/cy_tcpwm.h (73%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/tcpwm/cy_tcpwm_counter.c (68%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/tcpwm/cy_tcpwm_counter.h (87%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/tcpwm/cy_tcpwm_pwm.c (71%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/tcpwm/cy_tcpwm_pwm.h (71%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/tcpwm/cy_tcpwm_quaddec.c (79%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/tcpwm/cy_tcpwm_quaddec.h (87%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/trigmux/cy_trigmux.c (58%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/trigmux/cy_trigmux.h (69%) rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C/device/driver_periph => TARGET_PSoC6/device/drivers/peripheral}/wdt/cy_wdt.c (50%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/wdt/cy_wdt.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_backup.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_ble.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_cpuss.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_crypto.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_csd.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_ctbm.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_ctdac.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_dw.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_efuse.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_fault.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_flashc.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_gpio.h rename targets/TARGET_Cypress/{TARGET_PSoC6_CY8C => TARGET_PSoC6}/device/ip/cyip_headers.h (74%) create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_hsiom.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_i2s.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_ipc.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_lcd.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_lpcomp.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_pass.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_pdm.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_peri.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_profile.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_prot.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_sar.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_scb.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_sflash.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_smartio.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_smif.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_srss.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_tcpwm.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_udb.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/ip/cyip_usbfs.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_aios.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_aios.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_ancs.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_ancs.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_ans.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_ans.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_bas.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_bas.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_bcs.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_bcs.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_bls.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_bls.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_bms.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_bms.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_bts.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_bts.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_cgms.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_cgms.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_clk.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_clk.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_cps.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_cps.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_cscs.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_cscs.h create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_cts.c create mode 100644 targets/TARGET_Cypress/TARGET_PSoC6/device/middleware/ble/cy_ble_cts.h create mode 100644 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targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralNames.h rename to targets/TARGET_Cypress/TARGET_PSoC6/PeripheralNames.h diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralPins.h b/targets/TARGET_Cypress/TARGET_PSoC6/PeripheralPins.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PeripheralPins.h rename to targets/TARGET_Cypress/TARGET_PSoC6/PeripheralPins.h diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PinNamesTypes.h b/targets/TARGET_Cypress/TARGET_PSoC6/PinNamesTypes.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PinNamesTypes.h rename to targets/TARGET_Cypress/TARGET_PSoC6/PinNamesTypes.h diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PortNames.h b/targets/TARGET_Cypress/TARGET_PSoC6/PortNames.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/PortNames.h rename to targets/TARGET_Cypress/TARGET_PSoC6/PortNames.h diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/BLE_config.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/BLE_config.h new file mode 100644 index 0000000000..3aba0931a2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/BLE_config.h @@ -0,0 +1,330 @@ +/***************************************************************************//** +* \file CY_BLE_config.h +* \version 2.0 +* +* \brief +* Contains the function prototypes and constants for the BLE Component. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_BLE_CONFIG_H) +#define CY_BLE_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +//#include "cyfitter.h" +#include "syslib/cy_syslib.h" + + +/** +* \addtogroup group_macros +* @{ +*/ + +/* BLE_bless_isr */ +#define BLE_bless_isr__INTC_CORTEXM0P_ASSIGNED 1 +#define BLE_bless_isr__INTC_CORTEXM0P_MUX 3u +#define BLE_bless_isr__INTC_CORTEXM0P_PRIORITY 3u +#define BLE_bless_isr__INTC_CORTEXM4_ASSIGNED 1 +#define BLE_bless_isr__INTC_CORTEXM4_PRIORITY 7u +#define BLE_bless_isr__INTC_NUMBER 24u + + +/*************************************** +* Services Enable defines +***************************************/ + + + +/*************************************** +* API Constants +***************************************/ + +/** The component operating mode. */ +#define CY_BLE_CONFIG_MODE (0u) +#define CY_BLE_PROFILE (0u) +#define CY_BLE_HCI (1u) + +/** The core for the Host. For DUAL core device Controller will be compiled for different core. */ +#define CY_BLE_CONFIG_HOST_CORE (0u) +/** The core for the Controller in HCI mode. */ +#define CY_BLE_CONFIG_HCI_CONTR_CORE (1u) + +#define CY_BLE_CORE_CORTEX_M4 (0u) +#define CY_BLE_CORE_CORTEX_M0P (1u) +#define CY_BLE_CORE_CORTEX_NONE (0xffu) + +#define CY_BLE_HOST_CORE ((CY_BLE_CONFIG_HOST_CORE == CY_BLE_CORE_CORTEX_M4) ? \ + CY_CPU_CORTEX_M4 : CY_CPU_CORTEX_M0P) + +#define CY_BLE_HCI_CONTR_CORE ((CY_BLE_CONFIG_HCI_CONTR_CORE == CY_BLE_CORE_CORTEX_M4) ? \ + CY_CPU_CORTEX_M4 : CY_CPU_CORTEX_M0P) + +#define CY_BLE_CONTR_CORE ((CY_BLE_CONFIG_MODE == CY_BLE_HCI) ? CY_BLE_HCI_CONTR_CORE : \ + ((CY_BLE_CONFIG_HOST_CORE == CY_BLE_CORE_CORTEX_M0P) ? \ + CY_CPU_CORTEX_M4 : CY_CPU_CORTEX_M0P)) + +#define CY_BLE_MODE_PROFILE ((CY_BLE_CONFIG_MODE == CY_BLE_PROFILE) && (CY_BLE_HOST_CORE)) +#define CY_BLE_MODE_HCI ((CY_BLE_CONFIG_MODE == CY_BLE_HCI) && (CY_BLE_HCI_CONTR_CORE)) + +#define CY_BLE_CONFIG_EXT_PA_ENABLED ((0u | \ + 0u | \ + 0u) != 0u) + +/* Indicates whether deep sleep mode is used */ +#define CY_BLE_CONFIG_USE_DEEP_SLEEP (1u) + +/** Determines the internal stack mode. Used to switch the operation for debugging. + - ReleaseMode - Host and Controller with software interface. + - DebugMode - Host and Controller with IPC interface. + - HostOnly - Host with UART interface. + - HostContrUart - Host and Controller with a UART interface. +*/ +#define CY_BLE_CONFIG_STACK_MODE (2u) +#define CY_BLE_CONFIG_STACK_HOST_ONLY (1u) +#define CY_BLE_CONFIG_STACK_DEBUG (2u) +#define CY_BLE_CONFIG_STACK_RELEASE (3u) +#define CY_BLE_CONFIG_STACK_DEBUG_UART (4u) +#define CY_BLE_CONFIG_STACK_HOST_IPC (5u) + +#define CY_BLE_CONFIG_STACK_MODE_CONTR_UART ((CY_BLE_MODE_HCI) || \ + ((CY_BLE_CONFIG_MODE == CY_BLE_PROFILE) && \ + (CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_DEBUG_UART) && \ + CY_BLE_CONTR_CORE)) + +#define CY_BLE_CONFIG_STACK_MODE_HOST_UART ((CY_BLE_MODE_PROFILE) && \ + (((CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_HOST_ONLY) || \ + (CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_DEBUG_UART)) && \ + CY_BLE_HOST_CORE)) + +#define CY_BLE_CONFIG_STACK_MODE_HOST_IPC ((CY_BLE_MODE_PROFILE) && \ + (((CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_HOST_IPC) || \ + (CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_DEBUG)) && \ + CY_BLE_HOST_CORE)) + +#define CY_BLE_CONFIG_STACK_CONTR_CORE ((CY_BLE_MODE_HCI) || \ + ((CY_BLE_CONFIG_MODE == CY_BLE_PROFILE) && \ + ((CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_RELEASE) && \ + (CY_BLE_HOST_CORE)) || \ + (((CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_DEBUG) || \ + (CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_DEBUG_UART)) &&\ + (CY_BLE_CONTR_CORE)))) + +#define CY_BLE_CONFIG_STACK_IPC_CONTR_CORE ((CY_BLE_CONFIG_MODE == CY_BLE_PROFILE) && \ + (CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_DEBUG) && \ + (CY_BLE_CONTR_CORE)) + +#define CY_BLE_CONFIG_CONTR_CORE ((CY_BLE_CONFIG_MODE == CY_BLE_HCI) ? \ + CY_BLE_CONFIG_HCI_CONTR_CORE : \ + ((CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_RELEASE) ? \ + CY_BLE_CONFIG_HOST_CORE : \ + (((CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_DEBUG) || \ + (CY_BLE_CONFIG_STACK_MODE == CY_BLE_CONFIG_STACK_DEBUG_UART)) ? \ + ((CY_BLE_CONFIG_HOST_CORE == CY_BLE_CORE_CORTEX_M4) ? \ + CY_BLE_CORE_CORTEX_M0P : CY_BLE_CORE_CORTEX_M4) : \ + CY_BLE_CORE_CORTEX_NONE)) ) + +#define CY_BLE_HOST_CONTR_CORE (CY_BLE_MODE_PROFILE || CY_BLE_CONFIG_STACK_CONTR_CORE) + +#if(CY_BLE_CONFIG_STACK_CONTR_CORE) /* Check for the proper BLESS ISR configuration in the DWR */ + +#if ((CY_BLE_CONFIG_CONTR_CORE == CY_BLE_CORE_CORTEX_M4) && \ + (!defined BLE_bless_isr__INTC_CORTEXM4_ASSIGNED)) + #error Enable BLE_bless_isr interrupt for the ARM CM4 core in the interrupt configuration tab of \ + the Design-Wide Resources (DWR) file (project.cydwr) +#endif /* (CY_BLE_CONFIG_CONTR_CORE == CY_BLE_CORE_CORTEX_M4) */ +#if ((CY_BLE_CONFIG_CONTR_CORE == CY_BLE_CORE_CORTEX_M0P) && \ + (!defined BLE_bless_isr__INTC_CORTEXM0P_ASSIGNED)) + #error Enable BLE_bless_isr interrupt for the ARM CM0+ core in the interrupt configuration tab of \ + the Design-Wide Resources (DWR) file (project.cydwr) +#endif /* CY_BLE_CONFIG_CONTR_CORE == CY_BLE_CORE_CORTEX_M0P) */ + +#endif /* (CY_BLE_CONFIG_STACK_CONTR_CORE) */ + +#if(CY_BLE_CONFIG_STACK_MODE_CONTR_UART) /* Check for the proper UART ISR configuration in the DWR */ + +#if((CY_BLE_CONFIG_CONTR_CORE == CY_BLE_CORE_CORTEX_M4) && \ + (!defined BLE_uart_isr__INTC_CORTEXM4_ASSIGNED)) + #error Enable BLE_uart_isr interrupt for the ARM CM4 core in the interrupt configuration tab of \ + the Design-Wide Resources (DWR) file (project.cydwr) +#endif /* CY_BLE_CONFIG_CONTR_CORE == CY_BLE_CORE_CORTEX_M4 */ +#if((CY_BLE_CONFIG_CONTR_CORE == CY_BLE_CORE_CORTEX_M0P) && \ + (!defined BLE_uart_isr__INTC_CORTEXM0P_ASSIGNED)) + #error Enable BLE_uart_isr interrupt for the ARM CM0+ core in the interrupt configuration tab of \ + the Design-Wide Resources (DWR) file (project.cydwr) +#endif /* CY_BLE_CONFIG_CONTR_CORE == CY_BLE_CORE_CORTEX_M0P */ + +#endif /* (CY_BLE_CONFIG_STACK_MODE_CONTR_UART) */ + +#if(CY_BLE_CONFIG_STACK_MODE_HOST_UART) /* Check for the proper HOST UART ISR configuration in the DWR */ + +#if((CY_BLE_CONFIG_HOST_CORE == CY_BLE_CORE_CORTEX_M4) && \ + (!defined BLE_host_uart_isr__INTC_CORTEXM4_ASSIGNED)) + #error Enable BLE_host_uart_isr interrupt for the ARM CM4 core in the interrupt configuration tab of \ + the Design-Wide Resources (DWR) file (project.cydwr) +#endif /* CY_BLE_CONFIG_HOST_CORE == CY_BLE_CORE_CORTEX_M4 */ +#if((CY_BLE_CONFIG_HOST_CORE == CY_BLE_CORE_CORTEX_M0P) && \ + (!defined BLE_host_uart_isr__INTC_CORTEXM0P_ASSIGNED)) + #error Enable BLE_host_uart_isr interrupt for the ARM CM0+ core in the interrupt configuration tab of \ + the Design-Wide Resources (DWR) file (project.cydwr) +#endif /* CY_BLE_CONFIG_HOST_CORE == CY_BLE_CORE_CORTEX_M0P */ + +#endif /* (CY_BLE_CONFIG_STACK_MODE_HOST_UART) */ + +/** The maximum number of BLE connections */ +#define CY_BLE_CONFIG_CONN_COUNT (4u) +/** The number of BLE connections */ +#define CY_BLE_CONFIG_GATTC_COUNT (0x00u) +/** The number of GAP Peripheral configurations */ +#define CY_BLE_CONFIG_GAP_PERIPHERAL_COUNT (0x01u) +/** The number of GAP Broadcaster configurations */ +#define CY_BLE_CONFIG_GAP_BROADCASTER_COUNT (0x00u) +/** The number of GAP Central configurations */ +#define CY_BLE_CONFIG_GAP_CENTRAL_COUNT (0x00u) +/** The number of GAP Observer configurations */ +#define CY_BLE_CONFIG_GAP_OBSERVER_COUNT (0x00u) +/** The number of Security configurations */ +#define CY_BLE_CONFIG_AUTH_INFO_COUNT (0x01u) +/** LL Privacy 1.2 feature */ +#define CY_BLE_CONFIG_ENABLE_LL_PRIVACY (0x01u) +/** LE 2 Mbps feature */ +#define CY_BLE_CONFIG_ENABLE_PHY_UPDATE (0u) +/** Radio power calibration */ +#define CY_BLE_CONFIG_TX_POWER_CALIBRATION_ENABLE (0u) +/** The GAP security level */ +#define CY_BLE_CONFIG_GAP_SECURITY_LEVEL (0x00u) +#define CY_BLE_CONFIG_SHARING_MODE (0u) +/** The GAP Role */ +#define CY_BLE_CONFIG_GAP_ROLE (0x01u) +/** The Bonding Requirement */ +#define CY_BLE_CONFIG_BONDING_REQUIREMENT (0x00u) +/** The maximum number of bonded devices to be supported by this device. */ +#define CY_BLE_CONFIG_MAX_BONDED_DEVICES (16u) +/** The maximum number of peer devices whose addresses should be resolved by this device. */ +#define CY_BLE_CONFIG_MAX_RESOLVABLE_DEVICES (16u) +/** The maximum number of devices that can be added to the whitelist. */ +#define CY_BLE_CONFIG_MAX_WHITE_LIST_SIZE (16u) + +#define CY_BLE_SECURITY_CONFIGURATION_0_INDEX (0x00u) + +#define CY_BLE_ADV_PKT_0_INDEX_FLAGS (0x00u) +#define CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX (0x00u) + + +/* Additional queue depth provided from the customizer */ +#define CY_BLE_CONFIG_ADD_Q_DEPTH_PER_CONN (0u) + +/** GATT MTU Size */ +#define CY_BLE_CONFIG_GATT_MTU (0x0017u) + +/** GATT Maximum attribute length */ +#define CY_BLE_CONFIG_GATT_DB_MAX_VALUE_LEN (0x000Fu) + +#define CY_BLE_GATT_DB_INDEX_COUNT (0x000Fu) + +/** The number of characteristics supporting a Reliable Write property */ +#define CY_BLE_CONFIG_GATT_RELIABLE_CHAR_COUNT (0x0000u) +/** The total length of characteristics with Reliable Write property */ +#define CY_BLE_CONFIG_GATT_RELIABLE_CHAR_LENGTH (0x0000u) + +/** The parameter to enable an application to provide a dynamically allocated buffer for preparing a Write request. */ +#define CY_BLE_CONFIG_GATT_ENABLE_EXTERNAL_PREP_WRITE_BUFF (0u) + +/** The parameter to enable configuration of the L2CAP logical channels */ +#define CY_BLE_CONFIG_L2CAP_ENABLE (1u) + +#if(CY_BLE_CONFIG_L2CAP_ENABLE != 0u) + /** L2CAP MTU Size */ + #define CY_BLE_CONFIG_L2CAP_MTU (23u) + /** L2CAP MPS Size */ + #define CY_BLE_CONFIG_L2CAP_MPS (23u) + /** Number of L2CAP Logical channels */ + #define CY_BLE_CONFIG_L2CAP_LOGICAL_CHANNEL_COUNT (1u) + /** Number of L2CAP PSMs */ + #define CY_BLE_CONFIG_L2CAP_PSM_COUNT (1u) +#endif /* CY_BLE_L2CAP_ENABLE != 0u */ + + +#define CY_BLE_CONFIG_GATT_DB_ATT_VAL_COUNT (0x07u) + +/** Max Tx payload size */ +#define CY_BLE_CONFIG_LL_MAX_TX_PAYLOAD_SIZE (0x1Bu) +/** Max Rx payload size */ +#define CY_BLE_CONFIG_LL_MAX_RX_PAYLOAD_SIZE (0x1Bu) + +/** GATT Role */ +#define CY_BLE_CONFIG_GATT_ROLE (0x01u) +#define CY_BLE_CONFIG_GATT_DB_CCCD_COUNT (0x02u) + +/** Max unique services in the project */ +#define CY_BLE_MAX_SRVI (0x01u) + + +/*************************************** +* API Constants for BLE services +* (using in CY_BLE_.h) +***************************************/ + +/* HIDS */ +/** The maximum supported count of HID services for the GATT Server role */ +#define CY_BLE_CONFIG_HIDSS_SERVICE_COUNT (0x00u) +/** The maximum supported count of HID reports for the GATT Server role */ +#define CY_BLE_CONFIG_HIDSS_REPORT_COUNT (0x00u) + +/** The maximum supported count of HID services for the GATT Client role */ +#define CY_BLE_CONFIG_HIDSC_SERVICE_COUNT (0x00u) +/** The maximum supported count of HID reports for the GATT Client role */ +#define CY_BLE_CONFIG_HIDSC_REPORT_COUNT (0x00u) + + + + + +/* BAS */ +/** The maximum supported count of BAS services for the GATT Server role */ +#define CY_BLE_CONFIG_BASS_SERVICE_COUNT (0x00u) +/** The maximum supported count of BAS reports for the GATT Client role */ +#define CY_BLE_CONFIG_BASC_SERVICE_COUNT (0x00u) + + + +/* ESS */ +/** The maximum supported count of ESS characteristics for the GATT Client role */ +#define CY_BLE_CONFIG_ES_TOTAL_CHAR_COUNT (0x00u) + +/* AIOS */ +/** The maximum supported count of AIOS characteristics for the GATT Client role */ +#define CY_BLE_CONFIG_AIO_TOTAL_CHAR_COUNT (0x00u) + +/* CUSTOM */ +/** The maximum supported count of Custom services for the GATT Server role */ +#define CY_BLE_CONFIG_CUSTOMS_SERVICE_COUNT (0x00u) +/** The maximum supported count of Custom services for the GATT Client role */ +#define CY_BLE_CONFIG_CUSTOMC_SERVICE_COUNT (0x00u) +/** The maximum supported count of the Custom Service characteristics */ +#define CY_BLE_CONFIG_CUSTOM_SERVICE_CHAR_COUNT (0x00u) +/** The maximum supported count of the Custom Service descriptors in one characteristic */ +#define CY_BLE_CONFIG_CUSTOM_SERVICE_CHAR_DESCRIPTORS_COUNT (0x00u) + +/* Below are the indexes and handles of the defined Custom Services and their characteristics */ + + + +/** @} group_macros */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* CY_BLE_CONFIG_H */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/PeripheralPins.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PeripheralPins.c rename to targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/PeripheralPins.c diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/PinNames.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/PinNames.h similarity index 100% rename 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b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -1,8 +1,8 @@ /***************************************************************************//** -* \file cy8c6x7_cm0plus.ld -* \version 1.0 +* \file cy8c6xx7_cm0plus.ld +* \version 2.0 * -* \brief Linker file for the GNU C compiler. +* Linker file for the GNU C compiler. * * \note The entry point location is fixed and starts at 0x10000000. The valid * application image should be placed there. @@ -34,34 +34,20 @@ ENTRY(Reset_Handler) * option. */ EXTERN(Reset_Handler) -EXTERN(vectors) -EXTERN(ram_vectors) -EXTERN(cychipprotect) -EXTERN(cymeta) - -/* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00100000; -__cy_memory_0_row_size = 0x200; - -/* Working Flash */ -__cy_memory_1_start = 0x14000000; -__cy_memory_1_length = 0x8000; -__cy_memory_1_row_size = 0x200; - -/* XIP */ -__cy_memory_2_start = 0x18000000; -__cy_memory_2_length = 0x08000000; -__cy_memory_2_row_size = 0x200; /* Linker script to configure memory regions. */ MEMORY { - rom (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 - wrom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 - xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x08000000 - ram_cm0p (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000 + wflash (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x400 + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x24000 } @@ -100,13 +86,17 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) * __Vectors_End * __Vectors_Size */ -ENTRY(Reset_Handler) + SECTIONS { + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + .text : { - /* Cortex-M0+ ROM vector table */ . = ALIGN(4); __Vectors = . ; KEEP(*(.vectors)) @@ -139,26 +129,26 @@ SECTIONS *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) KEEP(*(.eh_frame*)) - } > rom + } > flash .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } > rom + } > flash __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom + } > flash __exidx_end = .; /* To copy multiple ROM to RAM sections, * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_psoc6ble_cm0plus.S */ + * define __STARTUP_COPY_MULTIPLE in startup_psoc63_cm0plus.S */ .copy.table : { . = ALIGN(4); @@ -175,13 +165,12 @@ SECTIONS LONG (__data_end__ - __data_start__) /* Size */ __copy_table_end__ = .; - } > rom - + } > flash /* To clear multiple BSS sections, * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6ble_cm0plus.S */ + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc63_cm0plus.S */ .zero.table : { . = ALIGN(4); @@ -189,7 +178,7 @@ SECTIONS LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) __zero_table_end__ = .; - } > rom + } > flash __etext = . ; @@ -199,7 +188,7 @@ SECTIONS __ram_vectors_start__ = .; KEEP(*(.ram_vectors)) __ram_vectors_end__ = .; - } > ram_cm0p + } > ram .data __ram_vectors_end__ : AT (__etext) @@ -233,9 +222,12 @@ SECTIONS KEEP(*(.jcr*)) . = ALIGN(4); + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + __data_end__ = .; - } > ram_cm0p + } > ram /* Place variables in the section that should not be initialized during the @@ -244,7 +236,7 @@ SECTIONS .noinit (NOLOAD) : ALIGN(8) { KEEP(*(.noinit)) - } > ram_cm0p + } > ram /* The uninitialized global or static variables are placed in this section. @@ -267,7 +259,7 @@ SECTIONS *(COMMON) . = ALIGN(4); __bss_end__ = .; - } > ram_cm0p + } > ram .heap (NOLOAD): @@ -277,7 +269,8 @@ SECTIONS end = __end__; KEEP(*(.heap*)) __HeapLimit = .; - } > ram_cm0p + } > ram + /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign @@ -285,11 +278,12 @@ SECTIONS .stack_dummy (NOLOAD): { KEEP(*(.stack*)) - } > ram_cm0p + } > ram + /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(ram_cm0p) + LENGTH(ram_cm0p); + __StackTop = ORIGIN(ram) + LENGTH(ram); __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); @@ -297,32 +291,88 @@ SECTIONS ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - /* The section is used for BLE bonding data storage. */ - ble_bond_data 0x14000000 : + /* Work Flash */ + .cy_wflash : { - __ble_bond_data_start = . ; - KEEP(*(.ble_bond_data)) - __ble_bond_data_end = . ; - } > wrom + KEEP(*(.cy_wflash)) + } > wflash + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 /* Places the code in the Execute in Place (XIP) section. See the smif driver * documentation for details. */ - .xip 0x18000000 : + .cy_xip : { - . = ALIGN(4); - __xip_data_start = . ; - KEEP(*(.xip)) - __xip_data_end = . ; + KEEP(*(.cy_xip)) } > xip + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + /* These sections are used for additional metadata (silicon revision, * Silicon/JTAG ID, etc.) storage. */ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE - .cychipprotect 0x90600000 : { KEEP(*(.cychipprotect)) } :NONE } +/* The following symbols used by the cypdlelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Working Flash */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + /* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_GCC_ARM/libble_stack_gcc_controller_ipc_cm0p.a b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M0/device/TOOLCHAIN_GCC_ARM/libble_stack_gcc_controller_ipc_cm0p.a new file mode 100644 index 0000000000000000000000000000000000000000..96f368b18caf96638e9602683b8cf0392e8e16cc GIT binary patch literal 815250 zcmeFa3w&J1bss#t0Eh=E3Zy8Blt^(&K{8}fe2JncTXG2EAwU8}h=5+PoW*jn09IT8 z>)nM2Dvm=XvLiWe>Q@}wQBoyw9Dj|QDr%S}{#p6#)Jc=pNkQ99q{wX<$6xF?PAkWD zqNZ-t|NqR)y>n;pT`VbCZu{~6u(&&@xx80hnHG z`*!cyyI(MqT}rk7Q>Fgd`@T27&poWvx&FTPcBQ`0ztrodRciMm$-hItt5SFTQ2cKa zymR@T98#%fe(yS_QjLB;f0;_1>+d($s?@9T`_pGsD(?3;Z&#^=UwYM>RKwq<532NQ z{k!vBD*e6sJ=Uet|3CV*to>VcUcVbxsg?`B3wiJg>p<(npHvrq7xLi$v^voC>9y)r z{r&ZN)%KmAy6|f<4_5umUe)mTFaA=kI^W-ad`7K``+e(UYSpX!Yk%FJs8{s+?SD}1 z=ke=k`*$kwcg0cF@k)NTe_eGn`+L_XRmV!dr$4Vcn)&_lRjT7$e}6xuI-2-(Zn#WE zepgSc&ZOVMQPp|AzxVx#>U=eSpZ&7xHGLwz2*w_s{L;KJGJ`z_50XPwffcg{T1@#Rs5~#{V{c3zq|fet!ea|dV^Xs^@jY( zL#4uaEtfw&T*#G`ko~nvX=J`wJ6fnNmTKBB?D5&f+SI~{dF`CNy-;J!`WNP>i!)KT!-ctp z%1PrkzEG(hTAVIaj6B9Be;mHG&#_ts!0e&X!R+9C?pUcXP$~=+a<#=uA?iLhd-9(0 z6cQKDtrQ>5K1x3*I3#nTILA0Kf|SG(9?nT+iF2)0bY9oOrL6JrY} z3YEhPQ?`**!OkDo9v3UQnyw&jtoS@WRGeNoTF6a#5eRs3$q{Bu=7>8QNs>IU62)2G zP_a;&@|&m#j>~glBoyN9h516Im>-$WYznikVoFVj4yHmFoCtKr6}s zCPv0UvC1xHFu!nQ9?7uv&-6TFm4fLKP?rV@rJU`;q&pa>&PlD2MwT61D%PSdI%VV4 zBjtjwMY)oL2Uq$Tsf%vVV2qZdz=@^XbH#bb4Te-ij*K5Y zGJf~iLRBa{>ZFq8xYuTp0aMvrtyalepT-Tn`&6u(js^v}$P+mou62`)bwG2AwZf7w zPdl=ot3xi%i*tEe=SEg%CJ10>vTt21EEcl4N(F6UMvqLIm@CfL7OL4<%mA|G1rR79 z*KJNu0gjAk5BJ@l9Ukl(%N`y)eB|f@3Qm#(xL56r!uXtKxtixW$#;b?DjbrcA;Is& zk%_+1?A`Ya-ZMC^bTsE?DwLj=EYVRXU6|Kw3^#M6H8lg7^NVxYh3PCA)sQncGgk|u zXeGlbh%IDPki3Tr;!{_|>BafH$-4?8U8q#%7nH7a)%Y7rxQ1OzEM4Qxo`D!*8% zptkBf)`g&IoC!ozMJGnJSk*|$GNCKkDrSJD@@8ub!Y9-QFPW2oF(KK6OWSf|yGI=! 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zb`|V6x&vQ4zwYO}i)vRvk0`HaxL#}+P`@ar^!Wu?Jhw!`zJp_t z|Fa121H3;4wij_NZ-)R^0XAU|GPXbFB8~x23^$+3D>w$v6ffbpjALlTDBr{JGLB0* zUe57Cj$v&a<Lk8uY!KimSldb^`dy|JEwKv?Wk=A!68V{eDh z$lRKv1JRy=STAg_jj4)|x+xr+ENJL$=#AW@1RCt!1Dgp`1R3mT>fIx6sb--DJM_5K zMS3IPCiX@*4t6wmvM7lS%IUsnn|jmlq+PyAhgBU!fR5dJx|5(Iwl@h@?TOtYHu~b; z-}7t@rW>&_0quQZ%ueYE(Clp{``u2VCs2p~3-!bg& zYo)stcZvX#E>z9x6FQJCuCd=H^9};}rP(!;$J_V!>O zSeSIYyMeb|kibsIdjojcgzJG0VK(9J&XV^Rz{@6nQ(;d>T^8xM3V7M*`x5Z7Nyocs z!VN-3O2vcJz<}or6egHrqTi>$a#a979N$6}OPC7YM+J-C3*=$B^=P~uKzJS8k%!?3 z-gJ#u1%2Q_&a+9pvv4hkdklCL;1~6wE}`#78gC5x%x#SyiFSK81Ud0Q(nHrTchztC4I2;D-kXXU6gQ70uRdvhKsg{ zpU!(-;z5&?miM;AE6Tt-EAcYz9dts2BjPtBgT4}p2Te%Y_*FGbW8cyluFx+ESB1Jmgnlz5r;Kn_bh7{(^_VH~iY3UdT_JE5EkBQEh?%e;vS WSgR*F2p-zt92fq7xjgk=wf_X #include -#include "system_psoc6ble_cm0plus.h" +#include "system_psoc63.h" #include "cy_device_headers.h" -#include "ipc/cy_ipc_drv.h" -#include "ipc/cy_ipc_pipe.h" -#include "ipc/cy_ipc_lock.h" -#include "sysint/cy_sysint.h" - -/******************************************************************************* -* Inter Process Communication (IPC) -*******************************************************************************/ -cy_stc_ipc_pipe_ep_t cy_ipc_pipe_sysEpArray[CPUSS_IPC_IPC_NR]; -uint32_t ipcLockArray[CY_IPC_LOCK_COUNT/CY_IPC_LOCKS_PER_WORD]; -cy_ipc_pipe_callback_ptr_t ipc_pipe_cyPipeCbArray[CY_IPC_CYPIPE_CLIENT_CNT]; +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "ipc/cy_ipc_pipe.h" + #include "ipc/cy_ipc_sema.h" +#endif /* CY_IPC_DEFAULT_CFG_DISABLE */ /******************************************************************************* @@ -35,34 +28,33 @@ cy_ipc_pipe_callback_ptr_t ipc_pipe_cyPipeCbArray[CY_IPC_CYPIPE_CLIENT_CNT]; *******************************************************************************/ /** Default HFClk frequency in Hz */ -#define CY_HFCLK0_FREQ_HZ_DEFAULT ( 8000000UL) +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT ( 8000000UL) /** Default PeriClk frequency in Hz */ -#define CY_PERICLK_FREQ_HZ_DEFAULT (4000000UL) +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) /** Default SlowClk system core frequency in Hz */ -#define CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT (4000000UL) +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL) +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) -#define CY_IMO_FREQ_HZ ( 8000000UL) -#ifndef CY_EXT_FREQ_HZ - #define CY_EXT_FREQ_HZ (24000000UL) -#endif -#ifndef CY_ECO_FREQ_HZ - #define CY_ECO_FREQ_HZ (24000000UL) -#endif +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) - #ifndef CY_ALTHF_FREQ_HZ - #define CY_ALTHF_FREQ_HZ (32000000UL) - #endif - uint32_t cy_BleEcoClockFreqHz = CY_ALTHF_FREQ_HZ; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) */ +#if (SRSS_PILO_PRESENT == 1U) || defined(CY_DOXYGEN) + /** PILO frequency in Hz */ + #define CY_CLK_PILO_FREQ_HZ (32768UL) +#endif /* (SRSS_PILO_PRESENT == 1U) || defined(CY_DOXYGEN) */ + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +#if (SRSS_ALTLF_PRESENT == 1U) || defined(CY_DOXYGEN) + /** ALTLF frequency in Hz */ + #define CY_CLK_ALTLF_FREQ_HZ (32768UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) || defined(CY_DOXYGEN) */ -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#define CY_ROOT_PATH_SRC_ECO (2UL) -#define CY_ROOT_PATH_SRC_ALTHF (3UL) /** Holds the SlowClk system core clock, which is the system clock frequency supplied to the SysTick timer and the * processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure @@ -71,114 +63,94 @@ cy_ipc_pipe_callback_ptr_t ipc_pipe_cyPipeCbArray[CY_IPC_CYPIPE_CLIENT_CNT]; * \attention Compilers must be configured to avoid removing this variable in case the application program is not using * it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure * the debugger. */ -uint32_t SystemCoreClock = CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT; +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; /** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_Hfclk0FreqHz = CY_HFCLK0_FREQ_HZ_DEFAULT; +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_PeriClkFreqHz = CY_PERICLK_FREQ_HZ_DEFAULT; +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; - -/* Do not use these definitions directly in your application */ -#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) -#define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) -#define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT; -uint32_t cy_delayFreqKhz = (CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; -uint8_t cy_delayFreqMhz = (uint8_t)((CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); -uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * ((CY_SYSTEM_CLOCK_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD); - - -/******************************************************************************* -* Table Of Content (TOC) -*******************************************************************************/ -typedef struct { - uint32_t securityImageAddr; /** Address of security image */ - uint32_t flashBootAddr; /** Address of Flash Boot stored in SFLASH */ - uint32_t flashBootSize; /** Size of Flash Boot (in bytes) */ - uint32_t objectOneAddr; /** Address of next object (0 if none) */ - uint32_t objectOneSize; /** Size of next object (0 if none) */ - uint32_t objectTwoAddr; /** Address of next object (0 if none) */ - uint32_t objectTwoSize; /** Size of next object (0 if none) */ - uint32_t objectThreeAddr; /** Address of next object (0 if none) */ - uint32_t objectThreeSize; /** Size of next object (0 if none) */ - uint32_t userAppAddr; /** Address of start of User Application */ - uint32_t userAppSize; /** Size of the User Application */ - uint32_t keyStorageAddr; /** Address of Key Storage Flash Blocks. */ - uint32_t keyStorageSize; /** Size of key storage area in bytes. */ - uint32_t smifConfigAddr; /** SMIF Configuration Table */ - uint32_t reserved[113u]; - uint32_t crc; /** 0x1FC CRC16-CCITT */ -} Cy_TOC_Type; - - -#define CY_TOC_BASE (0x100FFE00UL) -#define CY_TOC ((Cy_TOC_Type*) CY_TOC_BASE) - -#ifndef CY_TOC_FLASH_BOOT_ADDR - #define CY_TOC_FLASH_BOOT_ADDR (0x160020D8UL) -#endif - -#ifndef CY_TOC_FLASH_BOOT_SIZE - #define CY_TOC_FLASH_BOOT_SIZE (0x2000UL) -#endif - -#ifndef CY_TOC_SMIF_CONFIG_ADDR - #define CY_TOC_SMIF_CONFIG_ADDR (0xFFFFFFFFUL) -#endif - -#ifndef CY_TOC_USER_APP_ADDR - #define CY_TOC_USER_APP_ADDR (0x10000000UL) -#endif - -#ifndef CY_TOC_USER_APP_SIZE - #define CY_TOC_USER_APP_SIZE (0x80000UL) -#endif - -#ifdef CY_TOC_PRESENT - #if defined(__GNUC__) || defined(__ARMCC_VERSION) - __attribute__ ((__section__(".cy_toc"), used)) - #elif defined(__ICCARM__) - #pragma location=".cy_toc" - #endif - Cy_TOC_Type cyToc = { - .flashBootAddr = CY_TOC_FLASH_BOOT_ADDR, - .flashBootSize = CY_TOC_FLASH_BOOT_SIZE, - .smifConfigAddr = CY_TOC_SMIF_CONFIG_ADDR, - .userAppAddr = CY_TOC_USER_APP_ADDR, - .userAppSize = CY_TOC_USER_APP_SIZE - }; -#endif +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) */ /******************************************************************************* * SystemInit() *******************************************************************************/ +/* WDT lock bits */ #define CY_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u) #define CY_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u) -/* CLK_FLL_CONFIG default values, from MXS40-IP-SRSS */ +/* CLK_FLL_CONFIG default values */ #define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) #define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() +*******************************************************************************/ +#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) +#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) + /******************************************************************************* * Function Name: SystemInit ****************************************************************************//** * -* Initializes the system. +* Initializes the system: +* - Restores FLL registers to the default state. +* - Unlocks and disables WDT. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). * *******************************************************************************/ void SystemInit(void) { - /* Restores FLL to default state as it is not restored by ROM code */ + /* Restore FLL registers to the default state as they are not restored by the ROM code */ uint32_t copy = SRSS->CLK_FLL_CONFIG; copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; SRSS->CLK_FLL_CONFIG = copy; @@ -201,8 +173,17 @@ void SystemInit(void) Cy_SystemInit(); SystemCoreClockUpdate(); - Cy_SystemInitIpc(); - Cy_SMIF_StartupCallBack(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + /* Allocate and initialize semaphores for the system operations. */ + Cy_IPC_SystemSemaInit(); + Cy_IPC_SystemPipeInit(); +#endif /* CY_IPC_DEFAULT_CFG_DISABLE */ + + /* Clear data register of IPC structure #7, reserved for the Deep Sleep operations. */ + IPC_STRUCT7->DATA = 0UL; + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep Sleep entering. */ + IPC_STRUCT7->RELEASE = 0UL; } @@ -228,30 +209,15 @@ __WEAK void Cy_SystemInit(void) } -/******************************************************************************* -* Function Name: Cy_SMIF_StartupCallBack -****************************************************************************//** -* -* The function is called during device startup. Once SMIF functionality is -* required, user should implement the function as described by the SMIF -* documentation. -* -******************************************************************************/ -__WEAK void Cy_SMIF_StartupCallBack(void) -{ - /* Empty weak function. The actual implementation to be in the user's - * strong function. - */ -} - - /******************************************************************************* * Function Name: SystemCoreClockUpdate ****************************************************************************//** * -* Get Core Clock Frequency. +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. * -* Update \ref SystemCoreClock, \ref cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). * *******************************************************************************/ void SystemCoreClockUpdate (void) @@ -273,25 +239,60 @@ void SystemCoreClockUpdate (void) switch (srcClk) { case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_IMO_FREQ_HZ; + srcFreqHz = CY_CLK_IMO_FREQ_HZ; break; case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_EXT_FREQ_HZ; + srcFreqHz = CY_CLK_EXT_FREQ_HZ; break; - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_ECO_FREQ_HZ; - break; + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) case CY_ROOT_PATH_SRC_ALTHF: srcFreqHz = cy_BleEcoClockFreqHz; break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) */ +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; default: - srcFreqHz = CY_EXT_FREQ_HZ; + srcFreqHz = CY_CLK_EXT_FREQ_HZ; break; } @@ -373,93 +374,24 @@ void SystemCoreClockUpdate (void) } -/******************************************************************************* -* Function Name: Cy_SystemInitIpcCyPipeIsr -****************************************************************************//** -* -* This is the Interrupt Service Routine for the Cypress Pipe. -* -*******************************************************************************/ -void Cy_SystemInitIpcCyPipeIsr(void) -{ - Cy_IPC_PIPE_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_CYPIPE_ADDR]); -} - - -/******************************************************************************* -* Function Name: Cy_SystemInitIpc -****************************************************************************//** -* -* Performs initial IPC configuration. -* -*******************************************************************************/ -void Cy_SystemInitIpc(void) -{ - cy_stc_sysint_t ipc_intr_cypipeConfig; - - Cy_IPC_PIPE_Config(cy_ipc_pipe_sysEpArray); - - #if (CY_CPU_CORTEX_M0P) - /* Initialize the lock subsystem. Should be called only on one CPU. */ - (void) Cy_IPC_LOCK_Init(CY_IPC_LOCK_COUNT, ipcLockArray); - #endif /* (CY_CPU_CORTEX_M0P) */ - - /* Initialize the pipe endpoints */ - Cy_IPC_PIPE_Init(CY_IPC_EP_CYPIPE_ADDR, ipc_pipe_cyPipeCbArray, CY_IPC_CYPIPE_CLIENT_CNT, CY_IPC_CYPIPE_CONFIG); - - /* Configure interrupts */ - ipc_intr_cypipeConfig.intrSrc = CY_IPC_INTR_CYPIPE_SRC; - ipc_intr_cypipeConfig.intrCm0p = CY_IPC_INTR_CYPIPE_CM0SRC; - ipc_intr_cypipeConfig.intrPriority = CY_IPC_INTR_CYPIPE_PRIO; - - Cy_SysInt_Init(&ipc_intr_cypipeConfig, &Cy_SystemInitIpcCyPipeIsr); - #if (CY_CPU_CORTEX_M0P) - NVIC_EnableIRQ((IRQn_Type)ipc_intr_cypipeConfig.intrCm0p); - #else - NVIC_EnableIRQ((IRQn_Type)ipc_intr_cypipeConfig.intrSrc); - #endif -} - - +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) /******************************************************************************* * Function Name: Cy_SysGetCM4Status ****************************************************************************//** * -* Gets the Cortex-M4 core mode. +* Returns the Cortex-M4 core power mode. * -* \return \ref group_startup_macro +* \return \ref group_system_config_cm4_status_macro * *******************************************************************************/ uint32_t Cy_SysGetCM4Status(void) { - uint32_t returnValue; uint32_t regValue; - regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_Msk; - switch(regValue) - { - case CPUSS_CM4_PWR_CTL_DISABLED: - returnValue = CY_SYS_CM4_STATUS_DISABLED; - break; + /* Get current power mode */ + regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; - case CPUSS_CM4_PWR_CTL_RETAINED: - returnValue = CY_SYS_CM4_STATUS_RETAINED; - break; - - case CPUSS_CM4_PWR_CTL_ENABLED: - returnValue = CY_SYS_CM4_STATUS_ENABLED; - break; - - case CPUSS_CM4_PWR_CTL_RESET_MODE: - returnValue = CY_SYS_CM4_STATUS_RESET; - break; - - default: - returnValue = CY_SYS_CM4_STATUS_UNKNOWN; - break; - } - - return (returnValue); + return (regValue); } @@ -467,9 +399,9 @@ uint32_t Cy_SysGetCM4Status(void) * Function Name: Cy_SysEnableCM4 ****************************************************************************//** * -* Enables the Cortex-M4 core. The CPU is enabled once if it was in the disabled -* or retained mode. If the CPU is enabled, the vector table base address is -* updated and software reset of the Cortex-M4 core is performed. +* Sets vector table base address and enables the Cortex-M4 core. +* +* \note If the CPU is already enabled, it is reset and then enabled. * * \param vectorTableOffset The offset of the vector table base address from * memory address 0x00000000. The offset should be multiple to 1024 bytes. @@ -477,54 +409,28 @@ uint32_t Cy_SysGetCM4Status(void) *******************************************************************************/ void Cy_SysEnableCM4(uint32_t vectorTableOffset) { - uint32_t cm4Status; - uint32_t interruptState; + uint32_t regValue; + uint32_t interruptState; + uint32_t cpuState; interruptState = Cy_SaveIRQ(); - cm4Status = Cy_SysGetCM4Status(); - switch(cm4Status) + cpuState = Cy_SysGetCM4Status(); + if (CY_SYS_CM4_STATUS_ENABLED == cpuState) { - case CY_SYS_CM4_STATUS_DISABLED: - CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + Cy_SysResetCM4(); + } - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_POWER, 1UL); - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_ISOLATE, 1UL); - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); - break; + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; - case CY_SYS_CM4_STATUS_RETAINED: - CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_ENABLED; + CPUSS->CM4_PWR_CTL = regValue; - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_POWER, 1UL); - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_RETAIN, 1UL); - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_ISOLATE, 1UL); - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); - break; - - case CY_SYS_CM4_STATUS_RESET: - CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; - - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); - break; - - case CY_SYS_CM4_STATUS_ENABLED: - CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; - - /* Move to Reset from Enabled state */ - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); - - /* Move to Enabled from Reset state */ - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); - break; - - default: - /* Do nothing if Cortex-M4 is already enabled. */ - break; + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ } Cy_RestoreIRQ(interruptState); @@ -535,41 +441,32 @@ void Cy_SysEnableCM4(uint32_t vectorTableOffset) * Function Name: Cy_SysDisableCM4 ****************************************************************************//** * -* Disables the Cortex-M4 core. +* Disables the Cortex-M4 core and waits for the mode to take the effect. * * \warning Do not call the function while the Cortex-M4 is executing because * such a call may corrupt/abort a pending bus-transaction by the CPU and cause * unexpected behavior in the system including a deadlock. Call the function * while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use * the \ref group_syspm Power Management (syspm) API to put the CPU into the -* low-power modes. Use the \ref SysPm_ReadStatus() to get a status of the CPU. +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the +* CPU. * *******************************************************************************/ void Cy_SysDisableCM4(void) { - uint32_t cm4Status; - uint32_t interruptState; + uint32_t interruptState; + uint32_t regValue; interruptState = Cy_SaveIRQ(); - cm4Status = Cy_SysGetCM4Status(); - switch(cm4Status) + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_DISABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) { - case CY_SYS_CM4_STATUS_ENABLED: - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_ISOLATE, 1UL); - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_POWER, 1UL); - break; - - case CY_SYS_CM4_STATUS_RETAINED: - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_RETAIN, 1UL); - break; - - default: - /* Do nothing if Cortex-M4 is already disabled. */ - break; + /* Wait for the power mode to take effect */ } Cy_RestoreIRQ(interruptState); @@ -580,7 +477,10 @@ void Cy_SysDisableCM4(void) * Function Name: Cy_SysRetainCM4 ****************************************************************************//** * -* Retains the Cortex-M4 core. +* Retains the Cortex-M4 core and exists without waiting for the mode to take +* effect. +* +* \note The retained mode can be entered only from the enabled mode. * * \warning Do not call the function while the Cortex-M4 is executing because * such a call may corrupt/abort a pending bus-transaction by the CPU and cause @@ -592,30 +492,15 @@ void Cy_SysDisableCM4(void) *******************************************************************************/ void Cy_SysRetainCM4(void) { - uint32_t cm4Status; - uint32_t interruptState; + uint32_t interruptState; + uint32_t regValue; interruptState = Cy_SaveIRQ(); - cm4Status = Cy_SysGetCM4Status(); - switch(cm4Status) - { - case CY_SYS_CM4_STATUS_ENABLED: - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_ISOLATE, 1UL); - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_RETAIN, 1UL); - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_POWER, 1UL); - break; - - case CY_SYS_CM4_STATUS_DISABLED: - /* Switch from the DISABLED to the RETAINED state is not valid. - * Do nothing in this case. */ - break; - - default: - /* Do nothing if Cortex-M4 is already in the RETAINED state. */ - break; - } + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RETAINED; + CPUSS->CM4_PWR_CTL = regValue; Cy_RestoreIRQ(interruptState); } @@ -625,7 +510,9 @@ void Cy_SysRetainCM4(void) * Function Name: Cy_SysResetCM4 ****************************************************************************//** * -* Resets the Cortex-M4 core. +* Resets the Cortex-M4 core and waits for the mode to take the effect. +* +* \note The reset mode can not be entered from the retained mode. * * \warning Do not call the function while the Cortex-M4 is executing because * such a call may corrupt/abort a pending bus-transaction by the CPU and cause @@ -637,31 +524,90 @@ void Cy_SysRetainCM4(void) *******************************************************************************/ void Cy_SysResetCM4(void) { - uint32_t cm4Status; - uint32_t interruptState; + uint32_t interruptState; + uint32_t regValue; interruptState = Cy_SaveIRQ(); - cm4Status = Cy_SysGetCM4Status(); - switch(cm4Status) + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RESET; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) { - case CY_SYS_CM4_STATUS_ENABLED: - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_CLOCK, 1UL); - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_RESET, 1UL); - break; - - case CY_SYS_CM4_STATUS_DISABLED: - CPUSS->CM4_PWR_CTL |= _VAL2FLD(CPUSS_CM4_PWR_CTL_ISOLATE, 1UL); - CPUSS->CM4_PWR_CTL &= ~_VAL2FLD(CPUSS_CM4_PWR_CTL_POWER, 1UL); - break; - - default: - /* Do nothing if Cortex-M4 is already in the RETAINED state. */ - break; - } + /* Wait for the power mode to take effect */ + } Cy_RestoreIRQ(interruptState); } +#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cypdlelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Working Flash */ +__cy_memory_1_start EQU __cpp(CY_WFLASH_BASE) +__cy_memory_1_length EQU __cpp(CY_WFLASH_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) */ /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/PeripheralPins.c new file mode 100644 index 0000000000..451cf138c9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/PeripheralPins.c @@ -0,0 +1,131 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) XXX + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralNames.h" +#include "PeripheralPins.h" +#include "pinmap.h" + +// //*** ADC *** +// const PinMap PinMap_ADC[] = { +// {PC_15, ADC_0, STM_PIN_DATA_EXT(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0 +// {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1 +// {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2 +// {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3 +// {PC_11, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN4 +// {PC_10, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN5 +// {PC_9 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN6 +// {PC_8 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN7 +// {NC, NC, 0} +// }; + +// //*** DAC *** +// const PinMap PinMap_DAC[] = { +// {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1 +// {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2 (Warning: LED1 is also on this pin) +// {NC, NC, 0} +// }; + +// //*** SERIAL *** +// const PinMap PinMap_UART_TX[] = { +// {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {PC_10, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {NC, NC, 0} +// }; +// const PinMap PinMap_UART_RX[] = { +// {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {PC_11, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, +// {NC, NC, 0} +// }; + +// //*** I2C *** +// const PinMap PinMap_I2C_SDA[] = { +// {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PA_6, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC, NC, 0} +// }; +// const PinMap PinMap_I2C_SCL[] = { +// {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_8, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_4, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PA_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC, NC, 0} +// }; + +// //*** SPI *** +// const PinMap PinMap_SPI_SCLK[] = { +// {PA_6 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PB_1 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC , NC , 0} +// }; +// const PinMap PinMap_SPI_MOSI[] = { +// {PA_8 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PB_3 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_15, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC , NC , 0} +// }; +// const PinMap PinMap_SPI_MISO[] = { +// {PA_7 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PB_2 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_14, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC , NC , 0} +// }; +// const PinMap PinMap_SPI_SSEL[] = { +// {PA_5 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PB_0 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC , NC , 0} +// }; + +// //*** PWM *** +// const PinMap PinMap_PWM[] = { +// {PA_0 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_1 , PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, +// {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, +// {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, +// {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, +// {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, +// {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, +// {PC_10, PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, +// {NC , NC , WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)} +// }; diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/PinNames.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/PinNames.h new file mode 100644 index 0000000000..23ab89eee5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/PinNames.h @@ -0,0 +1,251 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) XXX + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" +#include "PortNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define CY_UART_RX P5_0 +#define CY_UART_TX P5_1 + +// PinName[15-0] = Port[15-8] + Pin[7-0] +typedef enum { + P0_0 = (Port0 << 8) + 0x00, + P0_1 = (Port0 << 8) + 0x01, + P0_2 = (Port0 << 8) + 0x02, + P0_3 = (Port0 << 8) + 0x03, + P0_4 = (Port0 << 8) + 0x04, + P0_5 = (Port0 << 8) + 0x05, + P0_6 = (Port0 << 8) + 0x06, + P0_7 = (Port0 << 8) + 0x07, + + P1_0 = (Port1 << 8) + 0x00, + P1_1 = (Port1 << 8) + 0x01, + P1_2 = (Port1 << 8) + 0x02, + P1_3 = (Port1 << 8) + 0x03, + P1_4 = (Port1 << 8) + 0x04, + P1_5 = (Port1 << 8) + 0x05, + P1_6 = (Port1 << 8) + 0x06, + P1_7 = (Port1 << 8) + 0x07, + + P2_0 = (Port2 << 8) + 0x00, + P2_1 = (Port2 << 8) + 0x01, + P2_2 = (Port2 << 8) + 0x02, + P2_3 = (Port2 << 8) + 0x03, + P2_4 = (Port2 << 8) + 0x04, + P2_5 = (Port2 << 8) + 0x05, + P2_6 = (Port2 << 8) + 0x06, + P2_7 = (Port2 << 8) + 0x07, + + P3_0 = (Port3 << 8) + 0x00, + P3_1 = (Port3 << 8) + 0x01, + P3_2 = (Port3 << 8) + 0x02, + P3_3 = (Port3 << 8) + 0x03, + P3_4 = (Port3 << 8) + 0x04, + P3_5 = (Port3 << 8) + 0x05, + P3_6 = (Port3 << 8) + 0x06, + P3_7 = (Port3 << 8) + 0x07, + + P4_0 = (Port4 << 8) + 0x00, + P4_1 = (Port4 << 8) + 0x01, + P4_2 = (Port4 << 8) + 0x02, + P4_3 = (Port4 << 8) + 0x03, + P4_4 = (Port4 << 8) + 0x04, + P4_5 = (Port4 << 8) + 0x05, + P4_6 = (Port4 << 8) + 0x06, + P4_7 = (Port4 << 8) + 0x07, + + P5_0 = (Port5 << 8) + 0x00, + P5_1 = (Port5 << 8) + 0x01, + P5_2 = (Port5 << 8) + 0x02, + P5_3 = (Port5 << 8) + 0x03, + P5_4 = (Port5 << 8) + 0x04, + P5_5 = (Port5 << 8) + 0x05, + P5_6 = (Port5 << 8) + 0x06, + P5_7 = (Port5 << 8) + 0x07, + + P6_0 = (Port6 << 8) + 0x00, + P6_1 = (Port6 << 8) + 0x01, + P6_2 = (Port6 << 8) + 0x02, + P6_3 = (Port6 << 8) + 0x03, + P6_4 = (Port6 << 8) + 0x04, + P6_5 = (Port6 << 8) + 0x05, + P6_6 = (Port6 << 8) + 0x06, + P6_7 = (Port6 << 8) + 0x07, + + P7_0 = (Port7 << 8) + 0x00, + P7_1 = (Port7 << 8) + 0x01, + P7_2 = (Port7 << 8) + 0x02, + P7_3 = (Port7 << 8) + 0x03, + P7_4 = (Port7 << 8) + 0x04, + P7_5 = (Port7 << 8) + 0x05, + P7_6 = (Port7 << 8) + 0x06, + P7_7 = (Port7 << 8) + 0x07, + + P8_0 = (Port8 << 8) + 0x00, + P8_1 = (Port8 << 8) + 0x01, + P8_2 = (Port8 << 8) + 0x02, + P8_3 = (Port8 << 8) + 0x03, + P8_4 = (Port8 << 8) + 0x04, + P8_5 = (Port8 << 8) + 0x05, + P8_6 = (Port8 << 8) + 0x06, + P8_7 = (Port8 << 8) + 0x07, + + P9_0 = (Port9 << 8) + 0x00, + P9_1 = (Port9 << 8) + 0x01, + P9_2 = (Port9 << 8) + 0x02, + P9_3 = (Port9 << 8) + 0x03, + P9_4 = (Port9 << 8) + 0x04, + P9_5 = (Port9 << 8) + 0x05, + P9_6 = (Port9 << 8) + 0x06, + P9_7 = (Port9 << 8) + 0x07, + + P10_0 = (Port10 << 8) + 0x00, + P10_1 = (Port10 << 8) + 0x01, + P10_2 = (Port10 << 8) + 0x02, + P10_3 = (Port10 << 8) + 0x03, + P10_4 = (Port10 << 8) + 0x04, + P10_5 = (Port10 << 8) + 0x05, + P10_6 = (Port10 << 8) + 0x06, + P10_7 = (Port10 << 8) + 0x07, + + P11_0 = (Port11 << 8) + 0x00, + P11_1 = (Port11 << 8) + 0x01, + P11_2 = (Port11 << 8) + 0x02, + P11_3 = (Port11 << 8) + 0x03, + P11_4 = (Port11 << 8) + 0x04, + P11_5 = (Port11 << 8) + 0x05, + P11_6 = (Port11 << 8) + 0x06, + P11_7 = (Port11 << 8) + 0x07, + + P12_0 = (Port12 << 8) + 0x00, + P12_1 = (Port12 << 8) + 0x01, + P12_2 = (Port12 << 8) + 0x02, + P12_3 = (Port12 << 8) + 0x03, + P12_4 = (Port12 << 8) + 0x04, + P12_5 = (Port12 << 8) + 0x05, + P12_6 = (Port12 << 8) + 0x06, + P12_7 = (Port12 << 8) + 0x07, + + P13_0 = (Port13 << 8) + 0x00, + P13_1 = (Port13 << 8) + 0x01, + P13_2 = (Port13 << 8) + 0x02, + P13_3 = (Port13 << 8) + 0x03, + P13_4 = (Port13 << 8) + 0x04, + P13_5 = (Port13 << 8) + 0x05, + P13_6 = (Port13 << 8) + 0x06, + P13_7 = (Port13 << 8) + 0x07, + + P14_0 = (Port14 << 8) + 0x00, + P14_1 = (Port14 << 8) + 0x01, + P14_2 = (Port14 << 8) + 0x02, + P14_3 = (Port14 << 8) + 0x03, + P14_4 = (Port14 << 8) + 0x04, + P14_5 = (Port14 << 8) + 0x05, + P14_6 = (Port14 << 8) + 0x06, + P14_7 = (Port14 << 8) + 0x07, + + P15_0 = (Port15 << 8) + 0x00, + P15_1 = (Port15 << 8) + 0x01, + P15_2 = (Port15 << 8) + 0x02, + P15_3 = (Port15 << 8) + 0x03, + P15_4 = (Port15 << 8) + 0x04, + P15_5 = (Port15 << 8) + 0x05, + P15_6 = (Port15 << 8) + 0x06, + P15_7 = (Port15 << 8) + 0x07, + + // Arduino connector namings + A0 = P10_0, + A1 = P10_1, + A2 = P10_2, + A3 = P10_3, + A4 = P10_4, + A5 = P10_5, + + D0 = P5_0, + D1 = P5_1, + D2 = P5_2, + D3 = P5_3, + D4 = P5_4, + D5 = P5_5, + D6 = P5_6, + D7 = P0_2, + D8 = P13_0, + D9 = P13_1, + D10 = P12_3, + D11 = P12_0, + D12 = P12_1, + D13 = P12_2, + + // Generic signals namings + + LED_RED = P0_3, + LED_GREEN = P1_1, + LED_BLUE = P11_1, + + SWITCH2 = P0_4, + + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_RED, + + USER_BUTTON = SWITCH2, + BUTTON1 = USER_BUTTON, + + // Standardized interfaces names + SERIAL_TX = CY_UART_TX, + SERIAL_RX = CY_UART_RX, + USBTX = CY_UART_TX, + USBRX = CY_UART_RX, + // I2C_SCL = PB_8, + // I2C_SDA = PB_9, + // SPI_MOSI = PA_7, + // SPI_MISO = PA_6, + // SPI_SCK = PA_5, + // SPI_CS = PB_6, + // PWM_OUT = PB_3, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_ARM_STD/cy_ble_stack_mdk_controller_ipc_cm4.a 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a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld new file mode 100644 index 0000000000..8192d3318e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -0,0 +1,381 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.ld +* \version 2.0 +* +* Linker file for the GNU C compiler. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + + +/* Linker script to configure memory regions. */ +MEMORY +{ + flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x80000 + wflash (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x400 + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ + ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x23800 +} + + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc63_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc63_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK appication. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Work Flash */ + .cy_wflash : + { + KEEP(*(.cy_wflash)) + } > wflash + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cypdlelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Working Flash */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + 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+/**************************************************************************//** + * @file startup_psoc63_cm4.s + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Saves and disables the interrupts */ + .global Cy_SaveIRQ + .func Cy_SaveIRQ, Cy_SaveIRQ + .type Cy_SaveIRQ, %function +Cy_SaveIRQ: + mrs r0, PRIMASK + cpsid i + bx lr + .size Cy_SaveIRQ, . - Cy_SaveIRQ + .endfunc + + /* Restores the interrupts */ + .global Cy_RestoreIRQ + .func Cy_RestoreIRQ, Cy_RestoreIRQ + .type Cy_RestoreIRQ, %function +Cy_RestoreIRQ: + msr PRIMASK, r0 + bx lr + .size Cy_RestoreIRQ, . - Cy_RestoreIRQ + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + + .type Fault_Handler, %function +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/system_psoc63_cm4.c b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/system_psoc63_cm4.c new file mode 100644 index 0000000000..c5437c7795 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/TARGET_CY8CKIT_062_BLE_M4/system_psoc63_cm4.c @@ -0,0 +1,430 @@ +/***************************************************************************//** +* \file system_psoc63_cm4.c +* \version 2.0 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include +#include "system_psoc63.h" +#include "cy_device_headers.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "ipc/cy_ipc_pipe.h" + #include "ipc/cy_ipc_sema.h" +#endif /* CY_IPC_DEFAULT_CFG_DISABLE */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT ( 8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +#if (SRSS_PILO_PRESENT == 1U) || defined(CY_DOXYGEN) + /** PILO frequency in Hz */ + #define CY_CLK_PILO_FREQ_HZ (32768UL) +#endif /* (SRSS_PILO_PRESENT == 1U) || defined(CY_DOXYGEN) */ + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +#if (SRSS_ALTLF_PRESENT == 1U) || defined(CY_DOXYGEN) + /** ALTLF frequency in Hz */ + #define CY_CLK_ALTLF_FREQ_HZ (32768UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) || defined(CY_DOXYGEN) */ + + +/** Holds the FastClk system core clock, which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure +* the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case the application program is not using +* it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure +* the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + /** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ +/* WDT lock bits */ +#define CY_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u) +#define CY_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system: +* - Unlocks and disables WDT. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* +*******************************************************************************/ +void SystemInit(void) +{ + /* Unlock and disable WDT */ + SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_WDT_LOCK_BIT0); + SRSS->WDT_CTL = (SRSS->WDT_CTL | CY_WDT_LOCK_BIT1); + SRSS->WDT_CTL &= (~ (uint32_t) SRSS_WDT_CTL_WDT_EN_Msk); + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + /* Allocate and initialize semaphores for the system operations. */ + Cy_IPC_SystemSemaInit(); + Cy_IPC_SystemPipeInit(); +#endif /* CY_IPC_DEFAULT_CFG_DISABLE */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if (rootPath == 1UL) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SaveIRQ(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_RestoreIRQ(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cypdlelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Working Flash */ +__cy_memory_1_start EQU __cpp(CY_WFLASH_BASE) +__cy_memory_1_length EQU __cpp(CY_WFLASH_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device.h similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device.h rename to targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device.h index fa47e5377a..b134699e38 100644 --- a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device.h 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zV>fD!QJ(dU|2LE6H(Qq9EKB+QHOj9j^v{_rCwx38m>@%3Bizp>E#PLV9u=|cRo z*)ul&jyOL)(l?A(e|AlH$&7mbt%8~>w{F5$Sn|&n%&t!n_@e_U0)LPoMd0rjqzL10 z6Id8Y@vt7#9AP}nwQgspKCa>lB%OCPsYE8~oP|eu5bB{lwsZ zWblDx{<#b+$3)~O`)KCt5(6_H(k~nMg4chCwAc~XZBvbBG!aw#u|0lZZ75?1t!jzc z|6OqEVN+d$zy98ZKP10p)jxNb{OSlk3iCTJk&qkOVX(32gUfIW!rQZHC1RT}<8yXI@W!2Lq1}epnG0vfh0wXtTak zpc8Nkl)hWQFza&_=FWVCPC$qj|Aa;VMK4k3@gdMjyZ7HS1dlC36jZ#U_1!Zs-ewM`(vx*sedyU#h12EBv6S zI+WLsAct-{36voq*_2B{H{$)a@&s2s603Khum=m%2?Q*~Gtl* zsRWgW$WFlUGYL9h|NZ3WDOgoE0q+52*)vV3VyOGBVU;COT{{my$x#BL)Dk$PWZl?L+9!kvKQyU>l) O?{F>{hQ9)(@Bab#@@j$r literal 0 HcmV?d00001 diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cmsis.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cmsis.h similarity index 93% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cmsis.h rename to targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cmsis.h index 5de272b134..18c5387bd3 100644 --- a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/cmsis.h +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cmsis.h @@ -32,7 +32,6 @@ #ifndef MBED_CMSIS_H #define MBED_CMSIS_H -#include "cy8c637bzi_bld74.h" // IRQn - could include "include/cy_device_headers.h" -#include "core_cm0plus.h" // NVIC +#include "cy_device_headers.h" #endif diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h new file mode 100644 index 0000000000..24e44b7bb0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h @@ -0,0 +1,1285 @@ +/***************************************************************************//** +* \file cy8c6347bzi_bld53.h +* +* \brief +* CY8C6347BZI-BLD53 device header +* +* \note +* Generated 9/21/2017 by CyDeviceHeaderGenerator v1.2.0.101 +* from the register map configuration rev#1007711 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CY8C6347BZI_BLD53_H_ +#define _CY8C6347BZI_BLD53_H_ + +/** +* \addtogroup group_device CY8C6347BZI-BLD53 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* ARM Cortex-M0+ NVIC Mux inputs. Allow routing of device interrupts to the CM0+ NVIC */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */ + NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */ + NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */ + NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */ + NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */ + NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */ + NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */ + NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */ + NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */ + NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */ + NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */ + NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */ + NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */ + NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */ + NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */ + NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */ + NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */ + NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */ + NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */ + NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */ + NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */ + NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */ + NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */ + NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */ + NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6347BZI-BLD53 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6347BZI-BLD53 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + disconnected_IRQn = 240 /*!< 240 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_psoc63.h" /*!< PSoC 63 System */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_psoc63.h" /*!< PSoC 63 System */ + +#endif + +#include "psoc63_config.h" +#include "gpio_psoc63_116_bga_ble.h" + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00020000UL +#define CY_SRAM0_BASE 0x08000000UL +#define CY_SRAM0_SIZE 0x00048000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_WFLASH_BASE 0x14000000UL +#define CY_WFLASH_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x000000C8UL + +#define CY_SILICON_ID 0xE2072100UL + +#define CY_HF_CLK_MAX_FREQ 150000000UL + +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB_GET_EZ_DATA_NR(base) 256u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB_IS_I2C_SLAVE_CAPABLE(base) true +/* I2C master support? ('0': no, '1': yes) */ +#define SCB_IS_I2C_MASTER_CAPABLE(base) ((base) != SCB8) +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB_IS_I2C_DS_CAPABLE(base) ((base) == SCB8) +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB_IS_SPI_SLAVE_CAPABLE(base) true +/* SPI master support? ('0': no, '1': yes) */ +#define SCB_IS_SPI_MASTER_CAPABLE(base) ((base) != SCB8) +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB_IS_SPI_DS_CAPABLE(base) ((base) == SCB8) +/* UART support? ('0': no, '1': yes) */ +#define SCB_IS_UART_CAPABLE(base) ((base) != SCB8) + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 1u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 1u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40PASS_CTDAC 1u +#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u +#define CY_IP_MXS40PASS_CTDAC_VERSION 1u +#define CY_IP_MXS40PASS_CTB 1u +#define CY_IP_MXS40PASS_CTB_INSTANCES 1u +#define CY_IP_MXS40PASS_CTB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +/* Include IP definitions */ +#include "cyip_sflash.h" +#include "cyip_peri.h" +#include "cyip_crypto.h" +#include "cyip_cpuss.h" +#include "cyip_fault.h" +#include "cyip_ipc.h" +#include "cyip_prot.h" +#include "cyip_flashc.h" +#include "cyip_srss.h" +#include "cyip_backup.h" +#include "cyip_dw.h" +#include "cyip_efuse.h" +#include "cyip_profile.h" +#include "cyip_hsiom.h" +#include "cyip_gpio.h" +#include "cyip_smartio.h" +#include "cyip_udb.h" +#include "cyip_lpcomp.h" +#include "cyip_csd.h" +#include "cyip_tcpwm.h" +#include "cyip_lcd.h" +#include "cyip_ble.h" +#include "cyip_smif.h" +#include "cyip_scb.h" +#include "cyip_ctbm.h" +#include "cyip_ctdac.h" +#include "cyip_sar.h" +#include "cyip_pass.h" +#include "cyip_i2s.h" +#include "cyip_pdm.h" + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40010000UL +#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL +#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL +#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL +#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL +#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL +#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL +#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL +#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL +#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL +#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL +#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL +#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL +#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL +#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL +#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL +#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL +#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL +#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL +#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL +#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL +#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL +#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL +#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL +#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL +#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL +#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL +#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL +#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL +#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL +#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL +#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL +#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL +#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL +#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL +#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL +#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL +#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL +#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL +#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL +#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL +#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL +#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL +#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL +#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL +#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL +#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL +#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL +#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL +#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL +#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL +#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL +#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL +#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL +#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL +#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL +#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL +#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL +#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL +#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL +#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL +#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL +#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL +#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL +#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ +#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ +#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ +#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ +#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ +#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ +#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ +#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ +#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ +#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ +#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ +#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ +#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ +#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ +#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ +#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ +#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ +#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ +#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ +#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ +#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ +#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ +#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ +#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ +#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ +#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ +#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ +#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ +#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ +#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ +#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ +#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ +#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ +#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ +#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ +#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ +#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ +#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ +#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ +#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ +#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ +#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ +#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ +#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ +#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ +#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ +#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ +#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ +#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ +#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ +#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ +#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ +#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ +#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ +#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ +#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ +#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ +#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ +#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ +#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ +#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ +#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ +#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ +#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ +#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ +#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ +#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ +#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ +#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ +#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ +#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ +#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ +#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ +#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ +#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ +#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ +#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ +#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ +#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ +#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ +#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ +#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ +#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ +#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ +#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ +#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ +#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ +#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ +#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */ +#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ +#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ +#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40110000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40210000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40220000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40230000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40240000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40250000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40281000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40310000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40320000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40330000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ + +/******************************************************************************* +* UDB +*******************************************************************************/ + +#define UDB_BASE 0x40340000UL +#define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ +#define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ +#define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ +#define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ +#define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ +#define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */ +#define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */ +#define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */ +#define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */ +#define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */ +#define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */ +#define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */ +#define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */ +#define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */ +#define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */ +#define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */ +#define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */ +#define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ +#define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ +#define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ +#define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ +#define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ +#define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ +#define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */ +#define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */ +#define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */ +#define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */ +#define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */ +#define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */ +#define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */ +#define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */ +#define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */ +#define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */ +#define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */ +#define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */ +#define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */ +#define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */ +#define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */ +#define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */ +#define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */ +#define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */ +#define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */ +#define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */ +#define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */ +#define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */ +#define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* BLE +*******************************************************************************/ + +#define BLE_BASE 0x403C0000UL +#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ +#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ +#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40610000UL +#define SCB1_BASE 0x40620000UL +#define SCB2_BASE 0x40630000UL +#define SCB3_BASE 0x40640000UL +#define SCB4_BASE 0x40650000UL +#define SCB5_BASE 0x40660000UL +#define SCB6_BASE 0x40670000UL +#define SCB7_BASE 0x40680000UL +#define SCB8_BASE 0x40690000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x41100000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x41140000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x411D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x411F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S_BASE 0x42A10000UL +#define I2S ((I2S_Type*) I2S_BASE) /* 0x42A10000 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM_BASE 0x42A20000UL +#define PDM ((PDM_Type*) PDM_BASE) /* 0x42A20000 */ + +/** \} CY8C6347BZI-BLD53 */ + +#endif /* _CY8C6347BZI_BLD53_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cy_device_headers.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cy_device_headers.h new file mode 100644 index 0000000000..b9775ccc88 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/cy_device_headers.h @@ -0,0 +1,61 @@ +/***************************************************************************//** +* \file cy_device_headers.h +* +* \brief +* Common header file to be included by the drivers. +* +* \note +* Generated 9/21/2017 by CyDeviceHeaderGenerator v1.2.0.101 +* from the register map configuration rev#1007711 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CY_DEVICE_HEADERS_H_ +#define _CY_DEVICE_HEADERS_H_ + +#if defined (CY8C6336BZI_BLF03) + #include "cy8c6336bzi_blf03.h" +#elif defined (CY8C6316BZI_BLF03) + #include "cy8c6316bzi_blf03.h" +#elif defined (CY8C6316BZI_BLF53) + #include "cy8c6316bzi_blf53.h" +#elif defined (CY8C6336BZI_BLD13) + #include "cy8c6336bzi_bld13.h" +#elif defined (CY8C6347BZI_BLD43) + #include "cy8c6347bzi_bld43.h" +#elif defined (CY8C6347BZI_BLD33) + #include "cy8c6347bzi_bld33.h" +#elif defined (CY8C6347BZI_BLD53) + #include "cy8c6347bzi_bld53.h" +#elif defined (CY8C6347FMI_BLD13) + #include "cy8c6347fmi_bld13.h" +#elif defined (CY8C6347FMI_BLD43) + #include "cy8c6347fmi_bld43.h" +#elif defined (CY8C6347FMI_BLD33) + #include "cy8c6347fmi_bld33.h" +#elif defined (CY8C6347FMI_BLD53) + #include "cy8c6347fmi_bld53.h" +#elif defined (CY8C637BZI_MD76) + #include "cy8c637bzi_md76.h" +#elif defined (CY8C637BZI_BLD74) + #include "cy8c637bzi_bld74.h" +#elif defined (CY8C637FMI_BLD73) + #include "cy8c637fmi_bld73.h" +#elif defined (CY8C68237BZ_BLE) + #include "cy8c68237bz_ble.h" +#elif defined (CY8C68237FM_BLE) + #include "cy8c68237fm_ble.h" +#else + #error Undefined part number +#endif + +#endif /* _CY_DEVICE_HEADERS_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h new file mode 100644 index 0000000000..b3a17d5830 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h @@ -0,0 +1,1808 @@ +/***************************************************************************//** +* \file gpio_psoc63_116_bga_ble.h +* +* \brief +* PSoC 63 device GPIO header for 116-BGA-BLE package +* +* \note +* Generated 9/21/2017 by CyDeviceHeaderGenerator v1.2.0.101 +* from the register map configuration rev#1007711 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _GPIO_PSOC63_116_BGA_BLE_H_ +#define _GPIO_PSOC63_116_BGA_BLE_H_ + +/* Package type */ +enum +{ + CY_GPIO_PACKAGE_QFN, + CY_GPIO_PACKAGE_BGA, + CY_GPIO_PACKAGE_CSP, + CY_GPIO_PACKAGE_WLCSP, + CY_GPIO_PACKAGE_LQFP, +}; + +#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA + +/* Port List */ +/* PORT 0 (GPIO) */ +#define P0_0_PORT GPIO_PRT0 +#define P0_0_NUM 0u +#define P0_1_PORT GPIO_PRT0 +#define P0_1_NUM 1u +#define P0_2_PORT GPIO_PRT0 +#define P0_2_NUM 2u +#define P0_3_PORT GPIO_PRT0 +#define P0_3_NUM 3u +#define P0_4_PORT GPIO_PRT0 +#define P0_4_NUM 4u +#define P0_5_PORT GPIO_PRT0 +#define P0_5_NUM 5u + +/* PORT 1 (GPIO_OVT) */ +#define P1_0_PORT GPIO_PRT1 +#define P1_0_NUM 0u +#define P1_1_PORT GPIO_PRT1 +#define P1_1_NUM 1u +#define P1_2_PORT GPIO_PRT1 +#define P1_2_NUM 2u +#define P1_3_PORT GPIO_PRT1 +#define P1_3_NUM 3u +#define P1_4_PORT GPIO_PRT1 +#define P1_4_NUM 4u +#define P1_5_PORT GPIO_PRT1 +#define P1_5_NUM 5u + +/* PORT 5 (GPIO) */ +#define P5_0_PORT GPIO_PRT5 +#define P5_0_NUM 0u +#define P5_1_PORT GPIO_PRT5 +#define P5_1_NUM 1u +#define P5_2_PORT GPIO_PRT5 +#define P5_2_NUM 2u +#define P5_3_PORT GPIO_PRT5 +#define P5_3_NUM 3u +#define P5_4_PORT GPIO_PRT5 +#define P5_4_NUM 4u +#define P5_5_PORT GPIO_PRT5 +#define P5_5_NUM 5u +#define P5_6_PORT GPIO_PRT5 +#define P5_6_NUM 6u + +/* PORT 6 (GPIO) */ +#define P6_0_PORT GPIO_PRT6 +#define P6_0_NUM 0u +#define P6_1_PORT GPIO_PRT6 +#define P6_1_NUM 1u +#define P6_2_PORT GPIO_PRT6 +#define P6_2_NUM 2u +#define P6_3_PORT GPIO_PRT6 +#define P6_3_NUM 3u +#define P6_4_PORT GPIO_PRT6 +#define P6_4_NUM 4u +#define P6_5_PORT GPIO_PRT6 +#define P6_5_NUM 5u +#define P6_6_PORT GPIO_PRT6 +#define P6_6_NUM 6u +#define P6_7_PORT GPIO_PRT6 +#define P6_7_NUM 7u + +/* PORT 7 (GPIO) */ +#define P7_0_PORT GPIO_PRT7 +#define P7_0_NUM 0u +#define P7_1_PORT GPIO_PRT7 +#define P7_1_NUM 1u +#define P7_2_PORT GPIO_PRT7 +#define P7_2_NUM 2u +#define P7_3_PORT GPIO_PRT7 +#define P7_3_NUM 3u +#define P7_4_PORT GPIO_PRT7 +#define P7_4_NUM 4u +#define P7_5_PORT GPIO_PRT7 +#define P7_5_NUM 5u +#define P7_6_PORT GPIO_PRT7 +#define P7_6_NUM 6u +#define P7_7_PORT GPIO_PRT7 +#define P7_7_NUM 7u + +/* PORT 8 (GPIO) */ +#define P8_0_PORT GPIO_PRT8 +#define P8_0_NUM 0u +#define P8_1_PORT GPIO_PRT8 +#define P8_1_NUM 1u +#define P8_2_PORT GPIO_PRT8 +#define P8_2_NUM 2u +#define P8_3_PORT GPIO_PRT8 +#define P8_3_NUM 3u +#define P8_4_PORT GPIO_PRT8 +#define P8_4_NUM 4u +#define P8_5_PORT GPIO_PRT8 +#define P8_5_NUM 5u +#define P8_6_PORT GPIO_PRT8 +#define P8_6_NUM 6u +#define P8_7_PORT GPIO_PRT8 +#define P8_7_NUM 7u + +/* PORT 9 (GPIO) */ +#define P9_0_PORT GPIO_PRT9 +#define P9_0_NUM 0u +#define P9_1_PORT GPIO_PRT9 +#define P9_1_NUM 1u +#define P9_2_PORT GPIO_PRT9 +#define P9_2_NUM 2u +#define P9_3_PORT GPIO_PRT9 +#define P9_3_NUM 3u +#define P9_4_PORT GPIO_PRT9 +#define P9_4_NUM 4u +#define P9_5_PORT GPIO_PRT9 +#define P9_5_NUM 5u +#define P9_6_PORT GPIO_PRT9 +#define P9_6_NUM 6u +#define P9_7_PORT GPIO_PRT9 +#define P9_7_NUM 7u + +/* PORT 10 (GPIO) */ +#define P10_0_PORT GPIO_PRT10 +#define P10_0_NUM 0u +#define P10_1_PORT GPIO_PRT10 +#define P10_1_NUM 1u +#define P10_2_PORT GPIO_PRT10 +#define P10_2_NUM 2u +#define P10_3_PORT GPIO_PRT10 +#define P10_3_NUM 3u +#define P10_4_PORT GPIO_PRT10 +#define P10_4_NUM 4u +#define P10_5_PORT GPIO_PRT10 +#define P10_5_NUM 5u +#define P10_6_PORT GPIO_PRT10 +#define P10_6_NUM 6u + +/* PORT 11 (GPIO) */ +#define P11_0_PORT GPIO_PRT11 +#define P11_0_NUM 0u +#define P11_1_PORT GPIO_PRT11 +#define P11_1_NUM 1u +#define P11_2_PORT GPIO_PRT11 +#define P11_2_NUM 2u +#define P11_3_PORT GPIO_PRT11 +#define P11_3_NUM 3u +#define P11_4_PORT GPIO_PRT11 +#define P11_4_NUM 4u +#define P11_5_PORT GPIO_PRT11 +#define P11_5_NUM 5u +#define P11_6_PORT GPIO_PRT11 +#define P11_6_NUM 6u +#define P11_7_PORT GPIO_PRT11 +#define P11_7_NUM 7u + +/* PORT 12 (GPIO) */ +#define P12_0_PORT GPIO_PRT12 +#define P12_0_NUM 0u +#define P12_1_PORT GPIO_PRT12 +#define P12_1_NUM 1u +#define P12_2_PORT GPIO_PRT12 +#define P12_2_NUM 2u +#define P12_3_PORT GPIO_PRT12 +#define P12_3_NUM 3u +#define P12_4_PORT GPIO_PRT12 +#define P12_4_NUM 4u +#define P12_5_PORT GPIO_PRT12 +#define P12_5_NUM 5u +#define P12_6_PORT GPIO_PRT12 +#define P12_6_NUM 6u +#define P12_7_PORT GPIO_PRT12 +#define P12_7_NUM 7u + +/* PORT 13 (GPIO) */ +#define P13_0_PORT GPIO_PRT13 +#define P13_0_NUM 0u +#define P13_1_PORT GPIO_PRT13 +#define P13_1_NUM 1u +#define P13_6_PORT GPIO_PRT13 +#define P13_6_NUM 6u +#define P13_7_PORT GPIO_PRT13 +#define P13_7_NUM 7u + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_CSHIELDPADS_PORT 7u +#define CSD_CSHIELDPADS_PIN 7u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define IOSS_ADFT0_NET_PORT 10u +#define IOSS_ADFT0_NET_PIN 0u +#define IOSS_ADFT1_NET_PORT 10u +#define IOSS_ADFT1_NET_PIN 1u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP0_PORT 5u +#define LPCOMP_INP_COMP0_PIN 6u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_AREF_EXT_VREF_PORT 9u +#define PASS_AREF_EXT_VREF_PIN 7u +#define PASS_CTB_OA0_OUT_10X_PORT 9u +#define PASS_CTB_OA0_OUT_10X_PIN 2u +#define PASS_CTB_OA1_OUT_10X_PORT 9u +#define PASS_CTB_OA1_OUT_10X_PIN 3u +#define PASS_CTB_PADS0_PORT 9u +#define PASS_CTB_PADS0_PIN 0u +#define PASS_CTB_PADS1_PORT 9u +#define PASS_CTB_PADS1_PIN 1u +#define PASS_CTB_PADS2_PORT 9u +#define PASS_CTB_PADS2_PIN 2u +#define PASS_CTB_PADS3_PORT 9u +#define PASS_CTB_PADS3_PIN 3u +#define PASS_CTB_PADS4_PORT 9u +#define PASS_CTB_PADS4_PIN 4u +#define PASS_CTB_PADS5_PORT 9u +#define PASS_CTB_PADS5_PIN 5u +#define PASS_CTB_PADS6_PORT 9u +#define PASS_CTB_PADS6_PIN 6u +#define PASS_CTB_PADS7_PORT 9u +#define PASS_CTB_PADS7_PIN 7u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define PASS_SARMUX_PADS2_PORT 10u +#define PASS_SARMUX_PADS2_PIN 2u +#define PASS_SARMUX_PADS3_PORT 10u +#define PASS_SARMUX_PADS3_PIN 3u +#define PASS_SARMUX_PADS4_PORT 10u +#define PASS_SARMUX_PADS4_PIN 4u +#define PASS_SARMUX_PADS5_PORT 10u +#define PASS_SARMUX_PADS5_PIN 5u +#define PASS_SARMUX_PADS6_PORT 10u +#define PASS_SARMUX_PADS6_PIN 6u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_ECO_IN_PORT 12u +#define SRSS_ECO_IN_PIN 6u +#define SRSS_ECO_OUT_PORT 12u +#define SRSS_ECO_OUT_PIN 7u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ + + /* P0.0 */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ + P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_0_AMUXA = 4, /* Analog mux bus A */ + P0_0_AMUXB = 5, /* Analog mux bus B */ + P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ + P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_1_AMUXA = 4, /* Analog mux bus A */ + P0_1_AMUXB = 5, /* Analog mux bus B */ + P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P0.2 */ + P0_2_GPIO = 0, /* GPIO controls 'out' */ + P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_2_AMUXA = 4, /* Analog mux bus A */ + P0_2_AMUXB = 5, /* Analog mux bus B */ + P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ + P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ + P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ + P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ + P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ + P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ + P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ + P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ + P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ + + /* P0.3 */ + P0_3_GPIO = 0, /* GPIO controls 'out' */ + P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_3_AMUXA = 4, /* Analog mux bus A */ + P0_3_AMUXB = 5, /* Analog mux bus B */ + P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ + P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ + P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ + P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ + P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ + P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ + P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ + P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ + P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ + + /* P0.4 */ + P0_4_GPIO = 0, /* GPIO controls 'out' */ + P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_4_AMUXA = 4, /* Analog mux bus A */ + P0_4_AMUXB = 5, /* Analog mux bus B */ + P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ + P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ + P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ + P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ + P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ + P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ + P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ + P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ + P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ + + /* P0.5 */ + P0_5_GPIO = 0, /* GPIO controls 'out' */ + P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_5_AMUXA = 4, /* Analog mux bus A */ + P0_5_AMUXB = 5, /* Analog mux bus B */ + P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ + P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ + P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ + P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ + P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ + P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ + P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ + P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ + P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ + P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ + + /* P1.0 */ + P1_0_GPIO = 0, /* GPIO controls 'out' */ + P1_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_0_AMUXA = 4, /* Analog mux bus A */ + P1_0_AMUXB = 5, /* Analog mux bus B */ + P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ + P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ + P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ + P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ + P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ + P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ + P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */ + P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */ + P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */ + P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ + + /* P1.1 */ + P1_1_GPIO = 0, /* GPIO controls 'out' */ + P1_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_1_AMUXA = 4, /* Analog mux bus A */ + P1_1_AMUXB = 5, /* Analog mux bus B */ + P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ + P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ + P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ + P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ + P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ + P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ + P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */ + P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */ + P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */ + P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ + + /* P1.2 */ + P1_2_GPIO = 0, /* GPIO controls 'out' */ + P1_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_2_AMUXA = 4, /* Analog mux bus A */ + P1_2_AMUXB = 5, /* Analog mux bus B */ + P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_2_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:4 */ + P1_2_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:1 */ + P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ + P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ + P1_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ + P1_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ + P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */ + P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */ + + /* P1.3 */ + P1_3_GPIO = 0, /* GPIO controls 'out' */ + P1_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_3_AMUXA = 4, /* Analog mux bus A */ + P1_3_AMUXB = 5, /* Analog mux bus B */ + P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_3_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:4 */ + P1_3_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ + P1_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ + P1_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ + P1_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ + P1_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ + P1_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:0 */ + P1_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:0 */ + + /* P1.4 */ + P1_4_GPIO = 0, /* GPIO controls 'out' */ + P1_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_4_AMUXA = 4, /* Analog mux bus A */ + P1_4_AMUXB = 5, /* Analog mux bus B */ + P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */ + P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */ + P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ + P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ + P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ + P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ + P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */ + + /* P1.5 */ + P1_5_GPIO = 0, /* GPIO controls 'out' */ + P1_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_5_AMUXA = 4, /* Analog mux bus A */ + P1_5_AMUXB = 5, /* Analog mux bus B */ + P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */ + P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ + P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ + P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ + P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ + P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ + P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ + + /* P5.0 */ + P5_0_GPIO = 0, /* GPIO controls 'out' */ + P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_0_AMUXA = 4, /* Analog mux bus A */ + P5_0_AMUXB = 5, /* Analog mux bus B */ + P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ + P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ + P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ + P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ + P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ + P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ + P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ + P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ + P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ + P5_0_AUDIOSS_CLK_I2S_IF = 22, /* Digital Active - audioss.clk_i2s_if */ + P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ + + /* P5.1 */ + P5_1_GPIO = 0, /* GPIO controls 'out' */ + P5_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_1_AMUXA = 4, /* Analog mux bus A */ + P5_1_AMUXB = 5, /* Analog mux bus B */ + P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ + P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ + P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ + P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ + P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ + P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ + P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ + P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ + P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ + P5_1_AUDIOSS_TX_SCK = 22, /* Digital Active - audioss.tx_sck */ + P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ + + /* P5.2 */ + P5_2_GPIO = 0, /* GPIO controls 'out' */ + P5_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_2_AMUXA = 4, /* Analog mux bus A */ + P5_2_AMUXB = 5, /* Analog mux bus B */ + P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ + P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ + P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ + P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ + P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ + P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ + P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ + P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ + P5_2_AUDIOSS_TX_WS = 22, /* Digital Active - audioss.tx_ws */ + + /* P5.3 */ + P5_3_GPIO = 0, /* GPIO controls 'out' */ + P5_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_3_AMUXA = 4, /* Analog mux bus A */ + P5_3_AMUXB = 5, /* Analog mux bus B */ + P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */ + P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ + P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ + P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ + P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ + P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ + P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ + P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ + P5_3_AUDIOSS_TX_SDO = 22, /* Digital Active - audioss.tx_sdo */ + + /* P5.4 */ + P5_4_GPIO = 0, /* GPIO controls 'out' */ + P5_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_4_AMUXA = 4, /* Analog mux bus A */ + P5_4_AMUXB = 5, /* Analog mux bus B */ + P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ + P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ + P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ + P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ + P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ + P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ + P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ + P5_4_AUDIOSS_RX_SCK = 22, /* Digital Active - audioss.rx_sck */ + + /* P5.5 */ + P5_5_GPIO = 0, /* GPIO controls 'out' */ + P5_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_5_AMUXA = 4, /* Analog mux bus A */ + P5_5_AMUXB = 5, /* Analog mux bus B */ + P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */ + P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ + P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ + P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ + P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ + P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ + P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ + P5_5_AUDIOSS_RX_WS = 22, /* Digital Active - audioss.rx_ws */ + + /* P5.6 */ + P5_6_GPIO = 0, /* GPIO controls 'out' */ + P5_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_6_AMUXA = 4, /* Analog mux bus A */ + P5_6_AMUXB = 5, /* Analog mux bus B */ + P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ + P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ + P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ + P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ + P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ + P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ + P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ + P5_6_AUDIOSS_RX_SDI = 22, /* Digital Active - audioss.rx_sdi */ + + /* P6.0 */ + P6_0_GPIO = 0, /* GPIO controls 'out' */ + P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_0_AMUXA = 4, /* Analog mux bus A */ + P6_0_AMUXB = 5, /* Analog mux bus B */ + P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ + P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ + P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ + P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ + P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ + P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ + P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ + P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ + P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ + P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ + P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ + P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ + + /* P6.1 */ + P6_1_GPIO = 0, /* GPIO controls 'out' */ + P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_1_AMUXA = 4, /* Analog mux bus A */ + P6_1_AMUXB = 5, /* Analog mux bus B */ + P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ + P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ + P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ + P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ + P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ + P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ + P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ + P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ + P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ + P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ + P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ + P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ + + /* P6.2 */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ + P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_2_AMUXA = 4, /* Analog mux bus A */ + P6_2_AMUXB = 5, /* Analog mux bus B */ + P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ + P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ + P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ + + /* P6.3 */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ + P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_3_AMUXA = 4, /* Analog mux bus A */ + P6_3_AMUXB = 5, /* Analog mux bus B */ + P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ + P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ + P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ + + /* P6.4 */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ + P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_4_AMUXA = 4, /* Analog mux bus A */ + P6_4_AMUXB = 5, /* Analog mux bus B */ + P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ + P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ + P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ + P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ + P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ + P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_5_AMUXA = 4, /* Analog mux bus A */ + P6_5_AMUXB = 5, /* Analog mux bus B */ + P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ + P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ + P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ + P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ + P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ + P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ + P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_6_AMUXA = 4, /* Analog mux bus A */ + P6_6_AMUXB = 5, /* Analog mux bus B */ + P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ + P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ + P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ + P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ + P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_7_AMUXA = 4, /* Analog mux bus A */ + P6_7_AMUXB = 5, /* Analog mux bus B */ + P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ + P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ + P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ + P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ + P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ + P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ + P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ + + /* P7.4 */ + P7_4_GPIO = 0, /* GPIO controls 'out' */ + P7_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_4_AMUXA = 4, /* Analog mux bus A */ + P7_4_AMUXB = 5, /* Analog mux bus B */ + P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ + P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */ + P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ + P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ + P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ + P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ + P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ + P7_4_BLESS_EXT_LNA_RX_CTL_OUT = 26, /* Digital Active - bless.ext_lna_rx_ctl_out */ + P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ + + /* P7.5 */ + P7_5_GPIO = 0, /* GPIO controls 'out' */ + P7_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_5_AMUXA = 4, /* Analog mux bus A */ + P7_5_AMUXB = 5, /* Analog mux bus B */ + P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */ + P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ + P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ + P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ + P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ + P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ + P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ + P7_5_BLESS_EXT_PA_TX_CTL_OUT = 26, /* Digital Active - bless.ext_pa_tx_ctl_out */ + P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ + + /* P7.6 */ + P7_6_GPIO = 0, /* GPIO controls 'out' */ + P7_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_6_AMUXA = 4, /* Analog mux bus A */ + P7_6_AMUXB = 5, /* Analog mux bus B */ + P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ + P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */ + P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ + P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ + P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ + P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ + P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ + P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT = 26, /* Digital Active - bless.ext_pa_lna_chip_en_out */ + P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ + + /* P7.7 */ + P7_7_GPIO = 0, /* GPIO controls 'out' */ + P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_7_AMUXA = 4, /* Analog mux bus A */ + P7_7_AMUXB = 5, /* Analog mux bus B */ + P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ + P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ + P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ + P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ + P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ + P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ + P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ + P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ + P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ + + /* P8.0 */ + P8_0_GPIO = 0, /* GPIO controls 'out' */ + P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_0_AMUXA = 4, /* Analog mux bus A */ + P8_0_AMUXB = 5, /* Analog mux bus B */ + P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ + P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ + P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ + P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ + P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ + + /* P8.1 */ + P8_1_GPIO = 0, /* GPIO controls 'out' */ + P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_1_AMUXA = 4, /* Analog mux bus A */ + P8_1_AMUXB = 5, /* Analog mux bus B */ + P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ + P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ + P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ + P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ + P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ + + /* P8.2 */ + P8_2_GPIO = 0, /* GPIO controls 'out' */ + P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_2_AMUXA = 4, /* Analog mux bus A */ + P8_2_AMUXB = 5, /* Analog mux bus B */ + P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ + P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ + P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ + P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ + P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ + P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ + P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ + P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ + P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ + + /* P8.3 */ + P8_3_GPIO = 0, /* GPIO controls 'out' */ + P8_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_3_AMUXA = 4, /* Analog mux bus A */ + P8_3_AMUXB = 5, /* Analog mux bus B */ + P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ + P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ + P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ + P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ + P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ + P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ + P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ + P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ + P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ + + /* P8.4 */ + P8_4_GPIO = 0, /* GPIO controls 'out' */ + P8_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_4_AMUXA = 4, /* Analog mux bus A */ + P8_4_AMUXB = 5, /* Analog mux bus B */ + P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ + P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */ + P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ + P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ + P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ + P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ + P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ + + /* P8.5 */ + P8_5_GPIO = 0, /* GPIO controls 'out' */ + P8_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_5_AMUXA = 4, /* Analog mux bus A */ + P8_5_AMUXB = 5, /* Analog mux bus B */ + P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ + P8_5_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ + P8_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ + P8_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ + P8_5_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ + P8_5_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ + P8_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */ + + /* P8.6 */ + P8_6_GPIO = 0, /* GPIO controls 'out' */ + P8_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_6_AMUXA = 4, /* Analog mux bus A */ + P8_6_AMUXB = 5, /* Analog mux bus B */ + P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ + P8_6_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:0 */ + P8_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ + P8_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ + P8_6_LCD_COM60 = 12, /* Digital Deep Sleep - lcd.com[60]:0 */ + P8_6_LCD_SEG60 = 13, /* Digital Deep Sleep - lcd.seg[60]:0 */ + P8_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:0 */ + + /* P8.7 */ + P8_7_GPIO = 0, /* GPIO controls 'out' */ + P8_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_7_AMUXA = 4, /* Analog mux bus A */ + P8_7_AMUXB = 5, /* Analog mux bus B */ + P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ + P8_7_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ + P8_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ + P8_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ + P8_7_LCD_COM61 = 12, /* Digital Deep Sleep - lcd.com[61]:0 */ + P8_7_LCD_SEG61 = 13, /* Digital Deep Sleep - lcd.seg[61]:0 */ + P8_7_SCB3_SPI_SELECT2 = 20, /* Digital Active - scb[3].spi_select2:0 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ + P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ + P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ + P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ + P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ + P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ + P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ + P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ + P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ + P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ + P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ + P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ + P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P9.4 */ + P9_4_GPIO = 0, /* GPIO controls 'out' */ + P9_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_4_AMUXA = 4, /* Analog mux bus A */ + P9_4_AMUXB = 5, /* Analog mux bus B */ + P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */ + P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ + P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */ + P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */ + P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */ + P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */ + P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ + + /* P9.5 */ + P9_5_GPIO = 0, /* GPIO controls 'out' */ + P9_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_5_AMUXA = 4, /* Analog mux bus A */ + P9_5_AMUXB = 5, /* Analog mux bus B */ + P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_5_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:5 */ + P9_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */ + P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:67 */ + P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:67 */ + P9_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:1 */ + P9_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:1 */ + P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */ + + /* P9.6 */ + P9_6_GPIO = 0, /* GPIO controls 'out' */ + P9_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_6_AMUXA = 4, /* Analog mux bus A */ + P9_6_AMUXB = 5, /* Analog mux bus B */ + P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_6_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ + P9_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */ + P9_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:68 */ + P9_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:68 */ + P9_6_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:1 */ + P9_6_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:1 */ + P9_6_SCB2_SPI_SELECT3 = 20, /* Digital Active - scb[2].spi_select3:0 */ + + /* P9.7 */ + P9_7_GPIO = 0, /* GPIO controls 'out' */ + P9_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_7_AMUXA = 4, /* Analog mux bus A */ + P9_7_AMUXB = 5, /* Analog mux bus B */ + P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ + P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ + P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */ + P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */ + P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */ + P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ + P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ + P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ + P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ + P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ + P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ + P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + + /* P10.2 */ + P10_2_GPIO = 0, /* GPIO controls 'out' */ + P10_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_2_AMUXA = 4, /* Analog mux bus A */ + P10_2_AMUXB = 5, /* Analog mux bus B */ + P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ + P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ + P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ + P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ + P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ + P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ + P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ + P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ + P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ + + /* P10.3 */ + P10_3_GPIO = 0, /* GPIO controls 'out' */ + P10_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_3_AMUXA = 4, /* Analog mux bus A */ + P10_3_AMUXB = 5, /* Analog mux bus B */ + P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ + P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ + P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ + P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ + P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ + P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ + P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ + P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ + P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ + + /* P10.4 */ + P10_4_GPIO = 0, /* GPIO controls 'out' */ + P10_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_4_AMUXA = 4, /* Analog mux bus A */ + P10_4_AMUXB = 5, /* Analog mux bus B */ + P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ + P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ + P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ + P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ + P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ + P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ + P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ + P10_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:0 */ + + /* P10.5 */ + P10_5_GPIO = 0, /* GPIO controls 'out' */ + P10_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_5_AMUXA = 4, /* Analog mux bus A */ + P10_5_AMUXB = 5, /* Analog mux bus B */ + P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ + P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ + P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ + P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ + P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ + P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ + P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ + P10_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:0 */ + + /* P10.6 */ + P10_6_GPIO = 0, /* GPIO controls 'out' */ + P10_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_6_AMUXA = 4, /* Analog mux bus A */ + P10_6_AMUXB = 5, /* Analog mux bus B */ + P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ + P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ + P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */ + P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */ + P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */ + P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */ + P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ + + /* P11.0 */ + P11_0_GPIO = 0, /* GPIO controls 'out' */ + P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_0_AMUXA = 4, /* Analog mux bus A */ + P11_0_AMUXB = 5, /* Analog mux bus B */ + P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ + P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ + P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ + P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ + P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ + P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ + P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ + P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ + P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ + P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ + + /* P11.1 */ + P11_1_GPIO = 0, /* GPIO controls 'out' */ + P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_1_AMUXA = 4, /* Analog mux bus A */ + P11_1_AMUXB = 5, /* Analog mux bus B */ + P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ + P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ + P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ + P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ + P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ + P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ + P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ + P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ + P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ + P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ + P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_2_AMUXA = 4, /* Analog mux bus A */ + P11_2_AMUXB = 5, /* Analog mux bus B */ + P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ + P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ + P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ + P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_3_AMUXA = 4, /* Analog mux bus A */ + P11_3_AMUXB = 5, /* Analog mux bus B */ + P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ + P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ + P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ + P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_4_AMUXA = 4, /* Analog mux bus A */ + P11_4_AMUXB = 5, /* Analog mux bus B */ + P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ + P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ + P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ + P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_5_AMUXA = 4, /* Analog mux bus A */ + P11_5_AMUXB = 5, /* Analog mux bus B */ + P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ + P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ + P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ + P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_6_AMUXA = 4, /* Analog mux bus A */ + P11_6_AMUXB = 5, /* Analog mux bus B */ + P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ + P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ + P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ + P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_7_AMUXA = 4, /* Analog mux bus A */ + P11_7_AMUXB = 5, /* Analog mux bus B */ + P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ + + /* P12.0 */ + P12_0_GPIO = 0, /* GPIO controls 'out' */ + P12_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_0_AMUXA = 4, /* Analog mux bus A */ + P12_0_AMUXB = 5, /* Analog mux bus B */ + P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */ + P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ + P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */ + P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */ + P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */ + P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */ + P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ + P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ + P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ + P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ + P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ + + /* P12.1 */ + P12_1_GPIO = 0, /* GPIO controls 'out' */ + P12_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_1_AMUXA = 4, /* Analog mux bus A */ + P12_1_AMUXB = 5, /* Analog mux bus B */ + P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */ + P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ + P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */ + P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */ + P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */ + P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */ + P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ + P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ + P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ + P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ + P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ + + /* P12.2 */ + P12_2_GPIO = 0, /* GPIO controls 'out' */ + P12_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_2_AMUXA = 4, /* Analog mux bus A */ + P12_2_AMUXB = 5, /* Analog mux bus B */ + P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */ + P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ + P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */ + P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */ + P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */ + P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */ + P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ + P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ + P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ + + /* P12.3 */ + P12_3_GPIO = 0, /* GPIO controls 'out' */ + P12_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_3_AMUXA = 4, /* Analog mux bus A */ + P12_3_AMUXB = 5, /* Analog mux bus B */ + P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */ + P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ + P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */ + P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */ + P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */ + P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */ + P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ + P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ + P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ + + /* P12.4 */ + P12_4_GPIO = 0, /* GPIO controls 'out' */ + P12_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_4_AMUXA = 4, /* Analog mux bus A */ + P12_4_AMUXB = 5, /* Analog mux bus B */ + P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */ + P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ + P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */ + P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */ + P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */ + P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */ + P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ + P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ + P12_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:1 */ + + /* P12.5 */ + P12_5_GPIO = 0, /* GPIO controls 'out' */ + P12_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_5_AMUXA = 4, /* Analog mux bus A */ + P12_5_AMUXB = 5, /* Analog mux bus B */ + P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */ + P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ + P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */ + P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */ + P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */ + P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */ + P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ + P12_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:1 */ + + /* P12.6 */ + P12_6_GPIO = 0, /* GPIO controls 'out' */ + P12_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_6_AMUXA = 4, /* Analog mux bus A */ + P12_6_AMUXB = 5, /* Analog mux bus B */ + P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ + P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ + P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ + P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ + P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ + P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ + P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ + + /* P12.7 */ + P12_7_GPIO = 0, /* GPIO controls 'out' */ + P12_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_7_AMUXA = 4, /* Analog mux bus A */ + P12_7_AMUXB = 5, /* Analog mux bus B */ + P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ + P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ + P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ + P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ + P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ + P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ + + /* P13.0 */ + P13_0_GPIO = 0, /* GPIO controls 'out' */ + P13_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_0_AMUXA = 4, /* Analog mux bus A */ + P13_0_AMUXB = 5, /* Analog mux bus B */ + P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ + P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */ + P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */ + P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */ + P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */ + P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */ + P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ + P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ + P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */ + P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */ + + /* P13.1 */ + P13_1_GPIO = 0, /* GPIO controls 'out' */ + P13_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_1_AMUXA = 4, /* Analog mux bus A */ + P13_1_AMUXB = 5, /* Analog mux bus B */ + P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ + P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ + P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */ + P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */ + P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */ + P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */ + P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ + P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ + P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ + P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */ + + /* P13.6 */ + P13_6_GPIO = 0, /* GPIO controls 'out' */ + P13_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_6_AMUXA = 4, /* Analog mux bus A */ + P13_6_AMUXB = 5, /* Analog mux bus B */ + P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ + P13_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:1 */ + P13_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:99 */ + P13_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:99 */ + P13_6_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:1 */ + P13_6_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:1 */ + P13_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:1 */ + + /* P13.7 */ + P13_7_GPIO = 0, /* GPIO controls 'out' */ + P13_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_7_AMUXA = 4, /* Analog mux bus A */ + P13_7_AMUXB = 5, /* Analog mux bus B */ + P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ + P13_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ + P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ + P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ + P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ + P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC63_116_BGA_BLE_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/gpio_psoc6ble_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/gpio_psoc6ble_116_bga_ble.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/gpio_psoc6ble_116_bga_ble.h rename to targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/gpio_psoc6ble_116_bga_ble.h diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/psoc63_config.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/psoc63_config.h new file mode 100644 index 0000000000..f4f6196d97 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/psoc63_config.h @@ -0,0 +1,2394 @@ +/***************************************************************************//** +* \file psoc63_config.h +* +* \brief +* PSoC 63 device configuration header +* +* \note +* Generated 9/21/2017 by CyDeviceHeaderGenerator v1.2.0.101 +* from the register map configuration rev#1007711 +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _PSOC63_CONFIG_H_ +#define _PSOC63_CONFIG_H_ + +/* Clock Connections */ +typedef enum +{ + PCLK_SCB0_CLOCK = 0, /* scb[0].clock */ + PCLK_SCB1_CLOCK = 1, /* scb[1].clock */ + PCLK_SCB2_CLOCK = 2, /* scb[2].clock */ + PCLK_SCB3_CLOCK = 3, /* scb[3].clock */ + PCLK_SCB4_CLOCK = 4, /* scb[4].clock */ + PCLK_SCB5_CLOCK = 5, /* scb[5].clock */ + PCLK_SCB6_CLOCK = 6, /* scb[6].clock */ + PCLK_SCB7_CLOCK = 7, /* scb[7].clock */ + PCLK_SCB8_CLOCK = 8, /* scb[8].clock */ + PCLK_UDB_CLOCKS0 = 9, /* udb.clocks[0] */ + PCLK_UDB_CLOCKS1 = 10, /* udb.clocks[1] */ + PCLK_UDB_CLOCKS2 = 11, /* udb.clocks[2] */ + PCLK_UDB_CLOCKS3 = 12, /* udb.clocks[3] */ + PCLK_UDB_CLOCKS4 = 13, /* udb.clocks[4] */ + PCLK_UDB_CLOCKS5 = 14, /* udb.clocks[5] */ + PCLK_UDB_CLOCKS6 = 15, /* udb.clocks[6] */ + PCLK_UDB_CLOCKS7 = 16, /* udb.clocks[7] */ + PCLK_SMARTIO8_CLOCK = 17, /* smartio[8].clock */ + PCLK_SMARTIO9_CLOCK = 18, /* smartio[9].clock */ + PCLK_TCPWM0_CLOCKS0 = 19, /* tcpwm[0].clocks[0] */ + PCLK_TCPWM0_CLOCKS1 = 20, /* tcpwm[0].clocks[1] */ + PCLK_TCPWM0_CLOCKS2 = 21, /* tcpwm[0].clocks[2] */ + PCLK_TCPWM0_CLOCKS3 = 22, /* tcpwm[0].clocks[3] */ + PCLK_TCPWM0_CLOCKS4 = 23, /* tcpwm[0].clocks[4] */ + PCLK_TCPWM0_CLOCKS5 = 24, /* tcpwm[0].clocks[5] */ + PCLK_TCPWM0_CLOCKS6 = 25, /* tcpwm[0].clocks[6] */ + PCLK_TCPWM0_CLOCKS7 = 26, /* tcpwm[0].clocks[7] */ + PCLK_TCPWM1_CLOCKS0 = 27, /* tcpwm[1].clocks[0] */ + PCLK_TCPWM1_CLOCKS1 = 28, /* tcpwm[1].clocks[1] */ + PCLK_TCPWM1_CLOCKS2 = 29, /* tcpwm[1].clocks[2] */ + PCLK_TCPWM1_CLOCKS3 = 30, /* tcpwm[1].clocks[3] */ + PCLK_TCPWM1_CLOCKS4 = 31, /* tcpwm[1].clocks[4] */ + PCLK_TCPWM1_CLOCKS5 = 32, /* tcpwm[1].clocks[5] */ + PCLK_TCPWM1_CLOCKS6 = 33, /* tcpwm[1].clocks[6] */ + PCLK_TCPWM1_CLOCKS7 = 34, /* tcpwm[1].clocks[7] */ + PCLK_TCPWM1_CLOCKS8 = 35, /* tcpwm[1].clocks[8] */ + PCLK_TCPWM1_CLOCKS9 = 36, /* tcpwm[1].clocks[9] */ + PCLK_TCPWM1_CLOCKS10 = 37, /* tcpwm[1].clocks[10] */ + PCLK_TCPWM1_CLOCKS11 = 38, /* tcpwm[1].clocks[11] */ + PCLK_TCPWM1_CLOCKS12 = 39, /* tcpwm[1].clocks[12] */ + PCLK_TCPWM1_CLOCKS13 = 40, /* tcpwm[1].clocks[13] */ + PCLK_TCPWM1_CLOCKS14 = 41, /* tcpwm[1].clocks[14] */ + PCLK_TCPWM1_CLOCKS15 = 42, /* tcpwm[1].clocks[15] */ + PCLK_TCPWM1_CLOCKS16 = 43, /* tcpwm[1].clocks[16] */ + PCLK_TCPWM1_CLOCKS17 = 44, /* tcpwm[1].clocks[17] */ + PCLK_TCPWM1_CLOCKS18 = 45, /* tcpwm[1].clocks[18] */ + PCLK_TCPWM1_CLOCKS19 = 46, /* tcpwm[1].clocks[19] */ + PCLK_TCPWM1_CLOCKS20 = 47, /* tcpwm[1].clocks[20] */ + PCLK_TCPWM1_CLOCKS21 = 48, /* tcpwm[1].clocks[21] */ + PCLK_TCPWM1_CLOCKS22 = 49, /* tcpwm[1].clocks[22] */ + PCLK_TCPWM1_CLOCKS23 = 50, /* tcpwm[1].clocks[23] */ + PCLK_CSD_CLOCK = 51, /* csd.clock */ + PCLK_LCD_CLOCK = 52, /* lcd.clock */ + PCLK_PROFILE_CLOCK_PROFILE = 53, /* profile.clock_profile */ + PCLK_CPUSS_CLOCK_TRACE_IN = 54, /* cpuss.clock_trace_in */ + PCLK_PASS_CLOCK_CTDAC = 55, /* pass.clock_ctdac */ + PCLK_PASS_CLOCK_PUMP_PERI = 56, /* pass.clock_pump_peri */ + PCLK_PASS_CLOCK_SAR = 57, /* pass.clock_sar */ + PCLK_USB_CLOCK_DEV_BRS = 58 /* usb.clock_dev_brs */ +} en_clk_dst_t; + +/* Trigger Group */ +/* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. +* The constants are divided into four types because each signal of the TrigMux driver has a path +* through two multiplexers: the reduction multiplexer and the distribution multiplexer. This +* requires two calls for Cy_TrigMux_Connect() function. The first call - for the reduction +* multiplexer, the second call - for the distribution multiplexer. +* +* The four types of inputs/output parameters: +* 1) Parameters for reduction multiplexer's inputs (input signals of TrigMux) +* 2) Parameters for reduction multiplexer's outputs (intermediate signals); +* 3) Parameters for distribution multiplexer's inputs (intermediate signals); +* 4) Parameters for distribution multiplexer's outputs (output signals of TrigMux). +* +* The Cy_TrigMux_Connect() inTrig parameter can have 1) and 3) types parameters. The outTrig +* parameter can have 2) and 4) types parameters. +* The names of the constants for these parameters have the following format: +* +* 1) For reduction multiplexer's inputs: +* TRIG_IN_ +* the reduction multiplexer number; +* - the name of the IP block which is the source of the signal; +* - the source signal number in the IP block. +* +* Example: +* TRIG11_IN_TCPWM0_TR_OVERFLOW3 - the TCPWM0 tr_overflow[3] input of reduction multiplexer#11. +* +* 2) For reduction multiplexer's outputs: +* TRIG_OUT_TR_GROUP_INPUT +* - the reduction multiplexer number; +* - the distribution multiplexer number; +* - the input number of the distribution multiplexer. +* +* Example: +* TRIG11_OUT_TR_GROUP0_INPUT23 - Input#23 of the distribution multiplexer#0 is the destination +* of the reduction multiplexer#11. +* +* 3) For distribution multiplexer's inputs: +* TRIG_IN_TR_GROUP_OUTPUT +* - the reduction multiplexer number; +* - the distribution multiplexer number; +* - the output number of the reduction multiplexer; +* +* Example: +* TRIG0_IN_TR_GROUP11_OUTPUT15 - Output#15 of the reduction multiplexer#11 is the source of the +* distribution multiplexer#0. +* +* 4) For distribution multiplexer's outputs: +* TRIG_OUT_ +* - the distribution multiplexer number; +* - the name of the IP block which is the destination of the signal; +* - the input signal number in the IP block. +* +* Example: +* TRIG0_OUT_CPUSS_DW0_TR_IN3 - the DW0 tr_out[3] ouput of the distribution multiplexer 0.*/ +/* Trigger Group Inputs */ +/* Trigger Input Group 0 - DMA Request Assignments */ +typedef enum +{ + TRIG0_IN_CPUSS_ZERO = 0x00000000u, /* cpuss.zero */ + TRIG0_IN_TR_GROUP10_OUTPUT0 = 0x00000001u, /* tr_group[10].output[0] */ + TRIG0_IN_TR_GROUP10_OUTPUT1 = 0x00000002u, /* tr_group[10].output[1] */ + TRIG0_IN_TR_GROUP10_OUTPUT2 = 0x00000003u, /* tr_group[10].output[2] */ + TRIG0_IN_TR_GROUP10_OUTPUT3 = 0x00000004u, /* tr_group[10].output[3] */ + TRIG0_IN_TR_GROUP10_OUTPUT4 = 0x00000005u, /* tr_group[10].output[4] */ + TRIG0_IN_TR_GROUP10_OUTPUT5 = 0x00000006u, /* tr_group[10].output[5] */ + TRIG0_IN_TR_GROUP10_OUTPUT6 = 0x00000007u, /* tr_group[10].output[6] */ + TRIG0_IN_TR_GROUP10_OUTPUT7 = 0x00000008u, /* tr_group[10].output[7] */ + TRIG0_IN_TR_GROUP11_OUTPUT0 = 0x00000009u, /* tr_group[11].output[0] */ + TRIG0_IN_TR_GROUP11_OUTPUT1 = 0x0000000Au, /* tr_group[11].output[1] */ + TRIG0_IN_TR_GROUP11_OUTPUT2 = 0x0000000Bu, /* tr_group[11].output[2] */ + TRIG0_IN_TR_GROUP11_OUTPUT3 = 0x0000000Cu, /* tr_group[11].output[3] */ + TRIG0_IN_TR_GROUP11_OUTPUT4 = 0x0000000Du, /* tr_group[11].output[4] */ + TRIG0_IN_TR_GROUP11_OUTPUT5 = 0x0000000Eu, /* tr_group[11].output[5] */ + TRIG0_IN_TR_GROUP11_OUTPUT6 = 0x0000000Fu, /* tr_group[11].output[6] */ + TRIG0_IN_TR_GROUP11_OUTPUT7 = 0x00000010u, /* tr_group[11].output[7] */ + TRIG0_IN_TR_GROUP11_OUTPUT8 = 0x00000011u, /* tr_group[11].output[8] */ + TRIG0_IN_TR_GROUP11_OUTPUT9 = 0x00000012u, /* tr_group[11].output[9] */ + TRIG0_IN_TR_GROUP11_OUTPUT10 = 0x00000013u, /* tr_group[11].output[10] */ + TRIG0_IN_TR_GROUP11_OUTPUT11 = 0x00000014u, /* tr_group[11].output[11] */ + TRIG0_IN_TR_GROUP11_OUTPUT12 = 0x00000015u, /* tr_group[11].output[12] */ + TRIG0_IN_TR_GROUP11_OUTPUT13 = 0x00000016u, /* tr_group[11].output[13] */ + TRIG0_IN_TR_GROUP11_OUTPUT14 = 0x00000017u, /* tr_group[11].output[14] */ + TRIG0_IN_TR_GROUP11_OUTPUT15 = 0x00000018u, /* tr_group[11].output[15] */ + TRIG0_IN_TR_GROUP12_OUTPUT8 = 0x00000019u, /* tr_group[12].output[8] */ + TRIG0_IN_TR_GROUP12_OUTPUT9 = 0x0000001Au, /* tr_group[12].output[9] */ + TRIG0_IN_TR_GROUP13_OUTPUT0 = 0x0000001Bu, /* tr_group[13].output[0] */ + TRIG0_IN_TR_GROUP13_OUTPUT1 = 0x0000001Cu, /* tr_group[13].output[1] */ + TRIG0_IN_TR_GROUP13_OUTPUT2 = 0x0000001Du, /* tr_group[13].output[2] */ + TRIG0_IN_TR_GROUP13_OUTPUT3 = 0x0000001Eu, /* tr_group[13].output[3] */ + TRIG0_IN_TR_GROUP13_OUTPUT4 = 0x0000001Fu, /* tr_group[13].output[4] */ + TRIG0_IN_TR_GROUP13_OUTPUT5 = 0x00000020u, /* tr_group[13].output[5] */ + TRIG0_IN_TR_GROUP13_OUTPUT6 = 0x00000021u, /* tr_group[13].output[6] */ + TRIG0_IN_TR_GROUP13_OUTPUT7 = 0x00000022u, /* tr_group[13].output[7] */ + TRIG0_IN_TR_GROUP13_OUTPUT8 = 0x00000023u, /* tr_group[13].output[8] */ + TRIG0_IN_TR_GROUP13_OUTPUT9 = 0x00000024u, /* tr_group[13].output[9] */ + TRIG0_IN_TR_GROUP13_OUTPUT10 = 0x00000025u, /* tr_group[13].output[10] */ + TRIG0_IN_TR_GROUP13_OUTPUT11 = 0x00000026u, /* tr_group[13].output[11] */ + TRIG0_IN_TR_GROUP13_OUTPUT12 = 0x00000027u, /* tr_group[13].output[12] */ + TRIG0_IN_TR_GROUP13_OUTPUT13 = 0x00000028u, /* tr_group[13].output[13] */ + TRIG0_IN_TR_GROUP13_OUTPUT14 = 0x00000029u, /* tr_group[13].output[14] */ + TRIG0_IN_TR_GROUP13_OUTPUT15 = 0x0000002Au, /* tr_group[13].output[15] */ + TRIG0_IN_TR_GROUP14_OUTPUT0 = 0x0000002Bu, /* tr_group[14].output[0] */ + TRIG0_IN_TR_GROUP14_OUTPUT1 = 0x0000002Cu, /* tr_group[14].output[1] */ + TRIG0_IN_TR_GROUP14_OUTPUT2 = 0x0000002Du, /* tr_group[14].output[2] */ + TRIG0_IN_TR_GROUP14_OUTPUT3 = 0x0000002Eu, /* tr_group[14].output[3] */ + TRIG0_IN_TR_GROUP14_OUTPUT4 = 0x0000002Fu, /* tr_group[14].output[4] */ + TRIG0_IN_TR_GROUP14_OUTPUT5 = 0x00000030u, /* tr_group[14].output[5] */ + TRIG0_IN_TR_GROUP14_OUTPUT6 = 0x00000031u, /* tr_group[14].output[6] */ + TRIG0_IN_TR_GROUP14_OUTPUT7 = 0x00000032u /* tr_group[14].output[7] */ +} en_trig_input_grp0_t; + +/* Trigger Input Group 1 - DMA Request Assignments */ +typedef enum +{ + TRIG1_IN_CPUSS_ZERO = 0x00000100u, /* cpuss.zero */ + TRIG1_IN_TR_GROUP10_OUTPUT0 = 0x00000101u, /* tr_group[10].output[0] */ + TRIG1_IN_TR_GROUP10_OUTPUT1 = 0x00000102u, /* tr_group[10].output[1] */ + TRIG1_IN_TR_GROUP10_OUTPUT2 = 0x00000103u, /* tr_group[10].output[2] */ + TRIG1_IN_TR_GROUP10_OUTPUT3 = 0x00000104u, /* tr_group[10].output[3] */ + TRIG1_IN_TR_GROUP10_OUTPUT4 = 0x00000105u, /* tr_group[10].output[4] */ + TRIG1_IN_TR_GROUP10_OUTPUT5 = 0x00000106u, /* tr_group[10].output[5] */ + TRIG1_IN_TR_GROUP10_OUTPUT6 = 0x00000107u, /* tr_group[10].output[6] */ + TRIG1_IN_TR_GROUP10_OUTPUT7 = 0x00000108u, /* tr_group[10].output[7] */ + TRIG1_IN_TR_GROUP11_OUTPUT0 = 0x00000109u, /* tr_group[11].output[0] */ + TRIG1_IN_TR_GROUP11_OUTPUT1 = 0x0000010Au, /* tr_group[11].output[1] */ + TRIG1_IN_TR_GROUP11_OUTPUT2 = 0x0000010Bu, /* tr_group[11].output[2] */ + TRIG1_IN_TR_GROUP11_OUTPUT3 = 0x0000010Cu, /* tr_group[11].output[3] */ + TRIG1_IN_TR_GROUP11_OUTPUT4 = 0x0000010Du, /* tr_group[11].output[4] */ + TRIG1_IN_TR_GROUP11_OUTPUT5 = 0x0000010Eu, /* tr_group[11].output[5] */ + TRIG1_IN_TR_GROUP11_OUTPUT6 = 0x0000010Fu, /* tr_group[11].output[6] */ + TRIG1_IN_TR_GROUP11_OUTPUT7 = 0x00000110u, /* tr_group[11].output[7] */ + TRIG1_IN_TR_GROUP11_OUTPUT8 = 0x00000111u, /* tr_group[11].output[8] */ + TRIG1_IN_TR_GROUP11_OUTPUT9 = 0x00000112u, /* tr_group[11].output[9] */ + TRIG1_IN_TR_GROUP11_OUTPUT10 = 0x00000113u, /* tr_group[11].output[10] */ + TRIG1_IN_TR_GROUP11_OUTPUT11 = 0x00000114u, /* tr_group[11].output[11] */ + TRIG1_IN_TR_GROUP11_OUTPUT12 = 0x00000115u, /* tr_group[11].output[12] */ + TRIG1_IN_TR_GROUP11_OUTPUT13 = 0x00000116u, /* tr_group[11].output[13] */ + TRIG1_IN_TR_GROUP11_OUTPUT14 = 0x00000117u, /* tr_group[11].output[14] */ + TRIG1_IN_TR_GROUP11_OUTPUT15 = 0x00000118u, /* tr_group[11].output[15] */ + TRIG1_IN_TR_GROUP12_OUTPUT8 = 0x00000119u, /* tr_group[12].output[8] */ + TRIG1_IN_TR_GROUP12_OUTPUT9 = 0x0000011Au, /* tr_group[12].output[9] */ + TRIG1_IN_TR_GROUP13_OUTPUT0 = 0x0000011Bu, /* tr_group[13].output[0] */ + TRIG1_IN_TR_GROUP13_OUTPUT1 = 0x0000011Cu, /* tr_group[13].output[1] */ + TRIG1_IN_TR_GROUP13_OUTPUT2 = 0x0000011Du, /* tr_group[13].output[2] */ + TRIG1_IN_TR_GROUP13_OUTPUT3 = 0x0000011Eu, /* tr_group[13].output[3] */ + TRIG1_IN_TR_GROUP13_OUTPUT4 = 0x0000011Fu, /* tr_group[13].output[4] */ + TRIG1_IN_TR_GROUP13_OUTPUT5 = 0x00000120u, /* tr_group[13].output[5] */ + TRIG1_IN_TR_GROUP13_OUTPUT6 = 0x00000121u, /* tr_group[13].output[6] */ + TRIG1_IN_TR_GROUP13_OUTPUT7 = 0x00000122u, /* tr_group[13].output[7] */ + TRIG1_IN_TR_GROUP13_OUTPUT8 = 0x00000123u, /* tr_group[13].output[8] */ + TRIG1_IN_TR_GROUP13_OUTPUT9 = 0x00000124u, /* tr_group[13].output[9] */ + TRIG1_IN_TR_GROUP13_OUTPUT10 = 0x00000125u, /* tr_group[13].output[10] */ + TRIG1_IN_TR_GROUP13_OUTPUT11 = 0x00000126u, /* tr_group[13].output[11] */ + TRIG1_IN_TR_GROUP13_OUTPUT12 = 0x00000127u, /* tr_group[13].output[12] */ + TRIG1_IN_TR_GROUP13_OUTPUT13 = 0x00000128u, /* tr_group[13].output[13] */ + TRIG1_IN_TR_GROUP13_OUTPUT14 = 0x00000129u, /* tr_group[13].output[14] */ + TRIG1_IN_TR_GROUP13_OUTPUT15 = 0x0000012Au, /* tr_group[13].output[15] */ + TRIG1_IN_TR_GROUP14_OUTPUT0 = 0x0000012Bu, /* tr_group[14].output[0] */ + TRIG1_IN_TR_GROUP14_OUTPUT1 = 0x0000012Cu, /* tr_group[14].output[1] */ + TRIG1_IN_TR_GROUP14_OUTPUT2 = 0x0000012Du, /* tr_group[14].output[2] */ + TRIG1_IN_TR_GROUP14_OUTPUT3 = 0x0000012Eu, /* tr_group[14].output[3] */ + TRIG1_IN_TR_GROUP14_OUTPUT4 = 0x0000012Fu, /* tr_group[14].output[4] */ + TRIG1_IN_TR_GROUP14_OUTPUT5 = 0x00000130u, /* tr_group[14].output[5] */ + TRIG1_IN_TR_GROUP14_OUTPUT6 = 0x00000131u, /* tr_group[14].output[6] */ + TRIG1_IN_TR_GROUP14_OUTPUT7 = 0x00000132u /* tr_group[14].output[7] */ +} en_trig_input_grp1_t; + +/* Trigger Input Group 2 - TCPWM trigger inputs */ +typedef enum +{ + TRIG2_IN_CPUSS_ZERO = 0x00000200u, /* cpuss.zero */ + TRIG2_IN_TR_GROUP10_OUTPUT0 = 0x00000201u, /* tr_group[10].output[0] */ + TRIG2_IN_TR_GROUP10_OUTPUT1 = 0x00000202u, /* tr_group[10].output[1] */ + TRIG2_IN_TR_GROUP10_OUTPUT2 = 0x00000203u, /* tr_group[10].output[2] */ + TRIG2_IN_TR_GROUP10_OUTPUT3 = 0x00000204u, /* tr_group[10].output[3] */ + TRIG2_IN_TR_GROUP10_OUTPUT4 = 0x00000205u, /* tr_group[10].output[4] */ + TRIG2_IN_TR_GROUP10_OUTPUT5 = 0x00000206u, /* tr_group[10].output[5] */ + TRIG2_IN_TR_GROUP10_OUTPUT6 = 0x00000207u, /* tr_group[10].output[6] */ + TRIG2_IN_TR_GROUP10_OUTPUT7 = 0x00000208u, /* tr_group[10].output[7] */ + TRIG2_IN_TR_GROUP11_OUTPUT0 = 0x00000209u, /* tr_group[11].output[0] */ + TRIG2_IN_TR_GROUP11_OUTPUT1 = 0x0000020Au, /* tr_group[11].output[1] */ + TRIG2_IN_TR_GROUP11_OUTPUT2 = 0x0000020Bu, /* tr_group[11].output[2] */ + TRIG2_IN_TR_GROUP11_OUTPUT3 = 0x0000020Cu, /* tr_group[11].output[3] */ + TRIG2_IN_TR_GROUP11_OUTPUT4 = 0x0000020Du, /* tr_group[11].output[4] */ + TRIG2_IN_TR_GROUP11_OUTPUT5 = 0x0000020Eu, /* tr_group[11].output[5] */ + TRIG2_IN_TR_GROUP11_OUTPUT6 = 0x0000020Fu, /* tr_group[11].output[6] */ + TRIG2_IN_TR_GROUP11_OUTPUT7 = 0x00000210u, /* tr_group[11].output[7] */ + TRIG2_IN_TR_GROUP11_OUTPUT8 = 0x00000211u, /* tr_group[11].output[8] */ + TRIG2_IN_TR_GROUP11_OUTPUT9 = 0x00000212u, /* tr_group[11].output[9] */ + TRIG2_IN_TR_GROUP11_OUTPUT10 = 0x00000213u, /* tr_group[11].output[10] */ + TRIG2_IN_TR_GROUP11_OUTPUT11 = 0x00000214u, /* tr_group[11].output[11] */ + TRIG2_IN_TR_GROUP11_OUTPUT12 = 0x00000215u, /* tr_group[11].output[12] */ + TRIG2_IN_TR_GROUP11_OUTPUT13 = 0x00000216u, /* tr_group[11].output[13] */ + TRIG2_IN_TR_GROUP11_OUTPUT14 = 0x00000217u, /* tr_group[11].output[14] */ + TRIG2_IN_TR_GROUP11_OUTPUT15 = 0x00000218u, /* tr_group[11].output[15] */ + TRIG2_IN_TR_GROUP12_OUTPUT0 = 0x00000219u, /* tr_group[12].output[0] */ + TRIG2_IN_TR_GROUP12_OUTPUT1 = 0x0000021Au, /* tr_group[12].output[1] */ + TRIG2_IN_TR_GROUP12_OUTPUT2 = 0x0000021Bu, /* tr_group[12].output[2] */ + TRIG2_IN_TR_GROUP12_OUTPUT3 = 0x0000021Cu, /* tr_group[12].output[3] */ + TRIG2_IN_TR_GROUP12_OUTPUT4 = 0x0000021Du, /* tr_group[12].output[4] */ + TRIG2_IN_TR_GROUP12_OUTPUT5 = 0x0000021Eu, /* tr_group[12].output[5] */ + TRIG2_IN_TR_GROUP12_OUTPUT6 = 0x0000021Fu, /* tr_group[12].output[6] */ + TRIG2_IN_TR_GROUP12_OUTPUT7 = 0x00000220u, /* tr_group[12].output[7] */ + TRIG2_IN_TR_GROUP13_OUTPUT16 = 0x00000221u, /* tr_group[13].output[16] */ + TRIG2_IN_TR_GROUP13_OUTPUT17 = 0x00000222u, /* tr_group[13].output[17] */ + TRIG2_IN_TR_GROUP14_OUTPUT8 = 0x00000223u, /* tr_group[14].output[8] */ + TRIG2_IN_TR_GROUP14_OUTPUT9 = 0x00000224u, /* tr_group[14].output[9] */ + TRIG2_IN_TR_GROUP14_OUTPUT10 = 0x00000225u, /* tr_group[14].output[10] */ + TRIG2_IN_TR_GROUP14_OUTPUT11 = 0x00000226u, /* tr_group[14].output[11] */ + TRIG2_IN_TR_GROUP14_OUTPUT12 = 0x00000227u, /* tr_group[14].output[12] */ + TRIG2_IN_TR_GROUP14_OUTPUT13 = 0x00000228u, /* tr_group[14].output[13] */ + TRIG2_IN_TR_GROUP14_OUTPUT14 = 0x00000229u, /* tr_group[14].output[14] */ + TRIG2_IN_TR_GROUP14_OUTPUT15 = 0x0000022Au /* tr_group[14].output[15] */ +} en_trig_input_grp2_t; + +/* Trigger Input Group 3 - TCPWM trigger inputs */ +typedef enum +{ + TRIG3_IN_CPUSS_ZERO = 0x00000300u, /* cpuss.zero */ + TRIG3_IN_TR_GROUP10_OUTPUT0 = 0x00000301u, /* tr_group[10].output[0] */ + TRIG3_IN_TR_GROUP10_OUTPUT1 = 0x00000302u, /* tr_group[10].output[1] */ + TRIG3_IN_TR_GROUP10_OUTPUT2 = 0x00000303u, /* tr_group[10].output[2] */ + TRIG3_IN_TR_GROUP10_OUTPUT3 = 0x00000304u, /* tr_group[10].output[3] */ + TRIG3_IN_TR_GROUP10_OUTPUT4 = 0x00000305u, /* tr_group[10].output[4] */ + TRIG3_IN_TR_GROUP10_OUTPUT5 = 0x00000306u, /* tr_group[10].output[5] */ + TRIG3_IN_TR_GROUP10_OUTPUT6 = 0x00000307u, /* tr_group[10].output[6] */ + TRIG3_IN_TR_GROUP10_OUTPUT7 = 0x00000308u, /* tr_group[10].output[7] */ + TRIG3_IN_TR_GROUP11_OUTPUT0 = 0x00000309u, /* tr_group[11].output[0] */ + TRIG3_IN_TR_GROUP11_OUTPUT1 = 0x0000030Au, /* tr_group[11].output[1] */ + TRIG3_IN_TR_GROUP11_OUTPUT2 = 0x0000030Bu, /* tr_group[11].output[2] */ + TRIG3_IN_TR_GROUP11_OUTPUT3 = 0x0000030Cu, /* tr_group[11].output[3] */ + TRIG3_IN_TR_GROUP11_OUTPUT4 = 0x0000030Du, /* tr_group[11].output[4] */ + TRIG3_IN_TR_GROUP11_OUTPUT5 = 0x0000030Eu, /* tr_group[11].output[5] */ + TRIG3_IN_TR_GROUP11_OUTPUT6 = 0x0000030Fu, /* tr_group[11].output[6] */ + TRIG3_IN_TR_GROUP11_OUTPUT7 = 0x00000310u, /* tr_group[11].output[7] */ + TRIG3_IN_TR_GROUP11_OUTPUT8 = 0x00000311u, /* tr_group[11].output[8] */ + TRIG3_IN_TR_GROUP11_OUTPUT9 = 0x00000312u, /* tr_group[11].output[9] */ + TRIG3_IN_TR_GROUP11_OUTPUT10 = 0x00000313u, /* tr_group[11].output[10] */ + TRIG3_IN_TR_GROUP11_OUTPUT11 = 0x00000314u, /* tr_group[11].output[11] */ + TRIG3_IN_TR_GROUP11_OUTPUT12 = 0x00000315u, /* tr_group[11].output[12] */ + TRIG3_IN_TR_GROUP11_OUTPUT13 = 0x00000316u, /* tr_group[11].output[13] */ + TRIG3_IN_TR_GROUP11_OUTPUT14 = 0x00000317u, /* tr_group[11].output[14] */ + TRIG3_IN_TR_GROUP11_OUTPUT15 = 0x00000318u, /* tr_group[11].output[15] */ + TRIG3_IN_TR_GROUP12_OUTPUT0 = 0x00000319u, /* tr_group[12].output[0] */ + TRIG3_IN_TR_GROUP12_OUTPUT1 = 0x0000031Au, /* tr_group[12].output[1] */ + TRIG3_IN_TR_GROUP12_OUTPUT2 = 0x0000031Bu, /* tr_group[12].output[2] */ + TRIG3_IN_TR_GROUP12_OUTPUT3 = 0x0000031Cu, /* tr_group[12].output[3] */ + TRIG3_IN_TR_GROUP12_OUTPUT4 = 0x0000031Du, /* tr_group[12].output[4] */ + TRIG3_IN_TR_GROUP12_OUTPUT5 = 0x0000031Eu, /* tr_group[12].output[5] */ + TRIG3_IN_TR_GROUP12_OUTPUT6 = 0x0000031Fu, /* tr_group[12].output[6] */ + TRIG3_IN_TR_GROUP12_OUTPUT7 = 0x00000320u, /* tr_group[12].output[7] */ + TRIG3_IN_TR_GROUP13_OUTPUT16 = 0x00000321u, /* tr_group[13].output[16] */ + TRIG3_IN_TR_GROUP13_OUTPUT17 = 0x00000322u, /* tr_group[13].output[17] */ + TRIG3_IN_TR_GROUP14_OUTPUT8 = 0x00000323u, /* tr_group[14].output[8] */ + TRIG3_IN_TR_GROUP14_OUTPUT9 = 0x00000324u, /* tr_group[14].output[9] */ + TRIG3_IN_TR_GROUP14_OUTPUT10 = 0x00000325u, /* tr_group[14].output[10] */ + TRIG3_IN_TR_GROUP14_OUTPUT11 = 0x00000326u, /* tr_group[14].output[11] */ + TRIG3_IN_TR_GROUP14_OUTPUT12 = 0x00000327u, /* tr_group[14].output[12] */ + TRIG3_IN_TR_GROUP14_OUTPUT13 = 0x00000328u, /* tr_group[14].output[13] */ + TRIG3_IN_TR_GROUP14_OUTPUT14 = 0x00000329u, /* tr_group[14].output[14] */ + TRIG3_IN_TR_GROUP14_OUTPUT15 = 0x0000032Au /* tr_group[14].output[15] */ +} en_trig_input_grp3_t; + +/* Trigger Input Group 4 - PROFILE trigger multiplexer */ +typedef enum +{ + TRIG4_IN_CPUSS_ZERO = 0x00000400u, /* cpuss.zero */ + TRIG4_IN_TR_GROUP10_OUTPUT0 = 0x00000401u, /* tr_group[10].output[0] */ + TRIG4_IN_TR_GROUP10_OUTPUT1 = 0x00000402u, /* tr_group[10].output[1] */ + TRIG4_IN_TR_GROUP10_OUTPUT2 = 0x00000403u, /* tr_group[10].output[2] */ + TRIG4_IN_TR_GROUP10_OUTPUT3 = 0x00000404u, /* tr_group[10].output[3] */ + TRIG4_IN_TR_GROUP10_OUTPUT4 = 0x00000405u, /* tr_group[10].output[4] */ + TRIG4_IN_TR_GROUP10_OUTPUT5 = 0x00000406u, /* tr_group[10].output[5] */ + TRIG4_IN_TR_GROUP10_OUTPUT6 = 0x00000407u, /* tr_group[10].output[6] */ + TRIG4_IN_TR_GROUP10_OUTPUT7 = 0x00000408u, /* tr_group[10].output[7] */ + TRIG4_IN_TR_GROUP11_OUTPUT0 = 0x00000409u, /* tr_group[11].output[0] */ + TRIG4_IN_TR_GROUP11_OUTPUT1 = 0x0000040Au, /* tr_group[11].output[1] */ + TRIG4_IN_TR_GROUP11_OUTPUT2 = 0x0000040Bu, /* tr_group[11].output[2] */ + TRIG4_IN_TR_GROUP11_OUTPUT3 = 0x0000040Cu, /* tr_group[11].output[3] */ + TRIG4_IN_TR_GROUP11_OUTPUT4 = 0x0000040Du, /* tr_group[11].output[4] */ + TRIG4_IN_TR_GROUP11_OUTPUT5 = 0x0000040Eu, /* tr_group[11].output[5] */ + TRIG4_IN_TR_GROUP11_OUTPUT6 = 0x0000040Fu, /* tr_group[11].output[6] */ + TRIG4_IN_TR_GROUP11_OUTPUT7 = 0x00000410u, /* tr_group[11].output[7] */ + TRIG4_IN_TR_GROUP11_OUTPUT8 = 0x00000411u, /* tr_group[11].output[8] */ + TRIG4_IN_TR_GROUP11_OUTPUT9 = 0x00000412u, /* tr_group[11].output[9] */ + TRIG4_IN_TR_GROUP11_OUTPUT10 = 0x00000413u, /* tr_group[11].output[10] */ + TRIG4_IN_TR_GROUP11_OUTPUT11 = 0x00000414u, /* tr_group[11].output[11] */ + TRIG4_IN_TR_GROUP11_OUTPUT12 = 0x00000415u, /* tr_group[11].output[12] */ + TRIG4_IN_TR_GROUP11_OUTPUT13 = 0x00000416u, /* tr_group[11].output[13] */ + TRIG4_IN_TR_GROUP11_OUTPUT14 = 0x00000417u, /* tr_group[11].output[14] */ + TRIG4_IN_TR_GROUP11_OUTPUT15 = 0x00000418u, /* tr_group[11].output[15] */ + TRIG4_IN_TR_GROUP12_OUTPUT0 = 0x00000419u, /* tr_group[12].output[0] */ + TRIG4_IN_TR_GROUP12_OUTPUT1 = 0x0000041Au, /* tr_group[12].output[1] */ + TRIG4_IN_TR_GROUP12_OUTPUT2 = 0x0000041Bu, /* tr_group[12].output[2] */ + TRIG4_IN_TR_GROUP12_OUTPUT3 = 0x0000041Cu, /* tr_group[12].output[3] */ + TRIG4_IN_TR_GROUP12_OUTPUT4 = 0x0000041Du, /* tr_group[12].output[4] */ + TRIG4_IN_TR_GROUP12_OUTPUT5 = 0x0000041Eu, /* tr_group[12].output[5] */ + TRIG4_IN_TR_GROUP12_OUTPUT6 = 0x0000041Fu, /* tr_group[12].output[6] */ + TRIG4_IN_TR_GROUP12_OUTPUT7 = 0x00000420u, /* tr_group[12].output[7] */ + TRIG4_IN_TR_GROUP13_OUTPUT16 = 0x00000421u, /* tr_group[13].output[16] */ + TRIG4_IN_TR_GROUP13_OUTPUT17 = 0x00000422u, /* tr_group[13].output[17] */ + TRIG4_IN_TR_GROUP14_OUTPUT8 = 0x00000423u, /* tr_group[14].output[8] */ + TRIG4_IN_TR_GROUP14_OUTPUT9 = 0x00000424u, /* tr_group[14].output[9] */ + TRIG4_IN_TR_GROUP14_OUTPUT10 = 0x00000425u, /* tr_group[14].output[10] */ + TRIG4_IN_TR_GROUP14_OUTPUT11 = 0x00000426u, /* tr_group[14].output[11] */ + TRIG4_IN_TR_GROUP14_OUTPUT12 = 0x00000427u, /* tr_group[14].output[12] */ + TRIG4_IN_TR_GROUP14_OUTPUT13 = 0x00000428u, /* tr_group[14].output[13] */ + TRIG4_IN_TR_GROUP14_OUTPUT14 = 0x00000429u, /* tr_group[14].output[14] */ + TRIG4_IN_TR_GROUP14_OUTPUT15 = 0x0000042Au /* tr_group[14].output[15] */ +} en_trig_input_grp4_t; + +/* Trigger Input Group 5 - CPUSS.CTI trigger multiplexer */ +typedef enum +{ + TRIG5_IN_CPUSS_ZERO = 0x00000500u, /* cpuss.zero */ + TRIG5_IN_TR_GROUP10_OUTPUT0 = 0x00000501u, /* tr_group[10].output[0] */ + TRIG5_IN_TR_GROUP10_OUTPUT1 = 0x00000502u, /* tr_group[10].output[1] */ + TRIG5_IN_TR_GROUP10_OUTPUT2 = 0x00000503u, /* tr_group[10].output[2] */ + TRIG5_IN_TR_GROUP10_OUTPUT3 = 0x00000504u, /* tr_group[10].output[3] */ + TRIG5_IN_TR_GROUP10_OUTPUT4 = 0x00000505u, /* tr_group[10].output[4] */ + TRIG5_IN_TR_GROUP10_OUTPUT5 = 0x00000506u, /* tr_group[10].output[5] */ + TRIG5_IN_TR_GROUP10_OUTPUT6 = 0x00000507u, /* tr_group[10].output[6] */ + TRIG5_IN_TR_GROUP10_OUTPUT7 = 0x00000508u, /* tr_group[10].output[7] */ + TRIG5_IN_TR_GROUP11_OUTPUT0 = 0x00000509u, /* tr_group[11].output[0] */ + TRIG5_IN_TR_GROUP11_OUTPUT1 = 0x0000050Au, /* tr_group[11].output[1] */ + TRIG5_IN_TR_GROUP11_OUTPUT2 = 0x0000050Bu, /* tr_group[11].output[2] */ + TRIG5_IN_TR_GROUP11_OUTPUT3 = 0x0000050Cu, /* tr_group[11].output[3] */ + TRIG5_IN_TR_GROUP11_OUTPUT4 = 0x0000050Du, /* tr_group[11].output[4] */ + TRIG5_IN_TR_GROUP11_OUTPUT5 = 0x0000050Eu, /* tr_group[11].output[5] */ + TRIG5_IN_TR_GROUP11_OUTPUT6 = 0x0000050Fu, /* tr_group[11].output[6] */ + TRIG5_IN_TR_GROUP11_OUTPUT7 = 0x00000510u, /* tr_group[11].output[7] */ + TRIG5_IN_TR_GROUP11_OUTPUT8 = 0x00000511u, /* tr_group[11].output[8] */ + TRIG5_IN_TR_GROUP11_OUTPUT9 = 0x00000512u, /* tr_group[11].output[9] */ + TRIG5_IN_TR_GROUP11_OUTPUT10 = 0x00000513u, /* tr_group[11].output[10] */ + TRIG5_IN_TR_GROUP11_OUTPUT11 = 0x00000514u, /* tr_group[11].output[11] */ + TRIG5_IN_TR_GROUP11_OUTPUT12 = 0x00000515u, /* tr_group[11].output[12] */ + TRIG5_IN_TR_GROUP11_OUTPUT13 = 0x00000516u, /* tr_group[11].output[13] */ + TRIG5_IN_TR_GROUP11_OUTPUT14 = 0x00000517u, /* tr_group[11].output[14] */ + TRIG5_IN_TR_GROUP11_OUTPUT15 = 0x00000518u, /* tr_group[11].output[15] */ + TRIG5_IN_TR_GROUP12_OUTPUT0 = 0x00000519u, /* tr_group[12].output[0] */ + TRIG5_IN_TR_GROUP12_OUTPUT1 = 0x0000051Au, /* tr_group[12].output[1] */ + TRIG5_IN_TR_GROUP12_OUTPUT2 = 0x0000051Bu, /* tr_group[12].output[2] */ + TRIG5_IN_TR_GROUP12_OUTPUT3 = 0x0000051Cu, /* tr_group[12].output[3] */ + TRIG5_IN_TR_GROUP12_OUTPUT4 = 0x0000051Du, /* tr_group[12].output[4] */ + TRIG5_IN_TR_GROUP12_OUTPUT5 = 0x0000051Eu, /* tr_group[12].output[5] */ + TRIG5_IN_TR_GROUP12_OUTPUT6 = 0x0000051Fu, /* tr_group[12].output[6] */ + TRIG5_IN_TR_GROUP12_OUTPUT7 = 0x00000520u, /* tr_group[12].output[7] */ + TRIG5_IN_TR_GROUP13_OUTPUT16 = 0x00000521u, /* tr_group[13].output[16] */ + TRIG5_IN_TR_GROUP13_OUTPUT17 = 0x00000522u, /* tr_group[13].output[17] */ + TRIG5_IN_TR_GROUP14_OUTPUT8 = 0x00000523u, /* tr_group[14].output[8] */ + TRIG5_IN_TR_GROUP14_OUTPUT9 = 0x00000524u, /* tr_group[14].output[9] */ + TRIG5_IN_TR_GROUP14_OUTPUT10 = 0x00000525u, /* tr_group[14].output[10] */ + TRIG5_IN_TR_GROUP14_OUTPUT11 = 0x00000526u, /* tr_group[14].output[11] */ + TRIG5_IN_TR_GROUP14_OUTPUT12 = 0x00000527u, /* tr_group[14].output[12] */ + TRIG5_IN_TR_GROUP14_OUTPUT13 = 0x00000528u, /* tr_group[14].output[13] */ + TRIG5_IN_TR_GROUP14_OUTPUT14 = 0x00000529u, /* tr_group[14].output[14] */ + TRIG5_IN_TR_GROUP14_OUTPUT15 = 0x0000052Au /* tr_group[14].output[15] */ +} en_trig_input_grp5_t; + +/* Trigger Input Group 6 - PASS trigger multiplexer */ +typedef enum +{ + TRIG6_IN_CPUSS_ZERO = 0x00000600u, /* cpuss.zero */ + TRIG6_IN_TR_GROUP10_OUTPUT0 = 0x00000601u, /* tr_group[10].output[0] */ + TRIG6_IN_TR_GROUP10_OUTPUT1 = 0x00000602u, /* tr_group[10].output[1] */ + TRIG6_IN_TR_GROUP10_OUTPUT2 = 0x00000603u, /* tr_group[10].output[2] */ + TRIG6_IN_TR_GROUP10_OUTPUT3 = 0x00000604u, /* tr_group[10].output[3] */ + TRIG6_IN_TR_GROUP10_OUTPUT4 = 0x00000605u, /* tr_group[10].output[4] */ + TRIG6_IN_TR_GROUP10_OUTPUT5 = 0x00000606u, /* tr_group[10].output[5] */ + TRIG6_IN_TR_GROUP10_OUTPUT6 = 0x00000607u, /* tr_group[10].output[6] */ + TRIG6_IN_TR_GROUP10_OUTPUT7 = 0x00000608u, /* tr_group[10].output[7] */ + TRIG6_IN_TR_GROUP11_OUTPUT0 = 0x00000609u, /* tr_group[11].output[0] */ + TRIG6_IN_TR_GROUP11_OUTPUT1 = 0x0000060Au, /* tr_group[11].output[1] */ + TRIG6_IN_TR_GROUP11_OUTPUT2 = 0x0000060Bu, /* tr_group[11].output[2] */ + TRIG6_IN_TR_GROUP11_OUTPUT3 = 0x0000060Cu, /* tr_group[11].output[3] */ + TRIG6_IN_TR_GROUP11_OUTPUT4 = 0x0000060Du, /* tr_group[11].output[4] */ + TRIG6_IN_TR_GROUP11_OUTPUT5 = 0x0000060Eu, /* tr_group[11].output[5] */ + TRIG6_IN_TR_GROUP11_OUTPUT6 = 0x0000060Fu, /* tr_group[11].output[6] */ + TRIG6_IN_TR_GROUP11_OUTPUT7 = 0x00000610u, /* tr_group[11].output[7] */ + TRIG6_IN_TR_GROUP11_OUTPUT8 = 0x00000611u, /* tr_group[11].output[8] */ + TRIG6_IN_TR_GROUP11_OUTPUT9 = 0x00000612u, /* tr_group[11].output[9] */ + TRIG6_IN_TR_GROUP11_OUTPUT10 = 0x00000613u, /* tr_group[11].output[10] */ + TRIG6_IN_TR_GROUP11_OUTPUT11 = 0x00000614u, /* tr_group[11].output[11] */ + TRIG6_IN_TR_GROUP11_OUTPUT12 = 0x00000615u, /* tr_group[11].output[12] */ + TRIG6_IN_TR_GROUP11_OUTPUT13 = 0x00000616u, /* tr_group[11].output[13] */ + TRIG6_IN_TR_GROUP11_OUTPUT14 = 0x00000617u, /* tr_group[11].output[14] */ + TRIG6_IN_TR_GROUP11_OUTPUT15 = 0x00000618u, /* tr_group[11].output[15] */ + TRIG6_IN_TR_GROUP12_OUTPUT0 = 0x00000619u, /* tr_group[12].output[0] */ + TRIG6_IN_TR_GROUP12_OUTPUT1 = 0x0000061Au, /* tr_group[12].output[1] */ + TRIG6_IN_TR_GROUP12_OUTPUT2 = 0x0000061Bu, /* tr_group[12].output[2] */ + TRIG6_IN_TR_GROUP12_OUTPUT3 = 0x0000061Cu, /* tr_group[12].output[3] */ + TRIG6_IN_TR_GROUP12_OUTPUT4 = 0x0000061Du, /* tr_group[12].output[4] */ + TRIG6_IN_TR_GROUP12_OUTPUT5 = 0x0000061Eu, /* tr_group[12].output[5] */ + TRIG6_IN_TR_GROUP12_OUTPUT6 = 0x0000061Fu, /* tr_group[12].output[6] */ + TRIG6_IN_TR_GROUP12_OUTPUT7 = 0x00000620u, /* tr_group[12].output[7] */ + TRIG6_IN_TR_GROUP13_OUTPUT16 = 0x00000621u, /* tr_group[13].output[16] */ + TRIG6_IN_TR_GROUP13_OUTPUT17 = 0x00000622u, /* tr_group[13].output[17] */ + TRIG6_IN_TR_GROUP14_OUTPUT8 = 0x00000623u, /* tr_group[14].output[8] */ + TRIG6_IN_TR_GROUP14_OUTPUT9 = 0x00000624u, /* tr_group[14].output[9] */ + TRIG6_IN_TR_GROUP14_OUTPUT10 = 0x00000625u, /* tr_group[14].output[10] */ + TRIG6_IN_TR_GROUP14_OUTPUT11 = 0x00000626u, /* tr_group[14].output[11] */ + TRIG6_IN_TR_GROUP14_OUTPUT12 = 0x00000627u, /* tr_group[14].output[12] */ + TRIG6_IN_TR_GROUP14_OUTPUT13 = 0x00000628u, /* tr_group[14].output[13] */ + TRIG6_IN_TR_GROUP14_OUTPUT14 = 0x00000629u, /* tr_group[14].output[14] */ + TRIG6_IN_TR_GROUP14_OUTPUT15 = 0x0000062Au /* tr_group[14].output[15] */ +} en_trig_input_grp6_t; + +/* Trigger Input Group 7 - UDB general purpose trigger multiplexer */ +typedef enum +{ + TRIG7_IN_CPUSS_ZERO = 0x00000700u, /* cpuss.zero */ + TRIG7_IN_TR_GROUP10_OUTPUT0 = 0x00000701u, /* tr_group[10].output[0] */ + TRIG7_IN_TR_GROUP10_OUTPUT1 = 0x00000702u, /* tr_group[10].output[1] */ + TRIG7_IN_TR_GROUP10_OUTPUT2 = 0x00000703u, /* tr_group[10].output[2] */ + TRIG7_IN_TR_GROUP10_OUTPUT3 = 0x00000704u, /* tr_group[10].output[3] */ + TRIG7_IN_TR_GROUP10_OUTPUT4 = 0x00000705u, /* tr_group[10].output[4] */ + TRIG7_IN_TR_GROUP10_OUTPUT5 = 0x00000706u, /* tr_group[10].output[5] */ + TRIG7_IN_TR_GROUP10_OUTPUT6 = 0x00000707u, /* tr_group[10].output[6] */ + TRIG7_IN_TR_GROUP10_OUTPUT7 = 0x00000708u, /* tr_group[10].output[7] */ + TRIG7_IN_TR_GROUP11_OUTPUT0 = 0x00000709u, /* tr_group[11].output[0] */ + TRIG7_IN_TR_GROUP11_OUTPUT1 = 0x0000070Au, /* tr_group[11].output[1] */ + TRIG7_IN_TR_GROUP11_OUTPUT2 = 0x0000070Bu, /* tr_group[11].output[2] */ + TRIG7_IN_TR_GROUP11_OUTPUT3 = 0x0000070Cu, /* tr_group[11].output[3] */ + TRIG7_IN_TR_GROUP11_OUTPUT4 = 0x0000070Du, /* tr_group[11].output[4] */ + TRIG7_IN_TR_GROUP11_OUTPUT5 = 0x0000070Eu, /* tr_group[11].output[5] */ + TRIG7_IN_TR_GROUP11_OUTPUT6 = 0x0000070Fu, /* tr_group[11].output[6] */ + TRIG7_IN_TR_GROUP11_OUTPUT7 = 0x00000710u, /* tr_group[11].output[7] */ + TRIG7_IN_TR_GROUP11_OUTPUT8 = 0x00000711u, /* tr_group[11].output[8] */ + TRIG7_IN_TR_GROUP11_OUTPUT9 = 0x00000712u, /* tr_group[11].output[9] */ + TRIG7_IN_TR_GROUP11_OUTPUT10 = 0x00000713u, /* tr_group[11].output[10] */ + TRIG7_IN_TR_GROUP11_OUTPUT11 = 0x00000714u, /* tr_group[11].output[11] */ + TRIG7_IN_TR_GROUP11_OUTPUT12 = 0x00000715u, /* tr_group[11].output[12] */ + TRIG7_IN_TR_GROUP11_OUTPUT13 = 0x00000716u, /* tr_group[11].output[13] */ + TRIG7_IN_TR_GROUP11_OUTPUT14 = 0x00000717u, /* tr_group[11].output[14] */ + TRIG7_IN_TR_GROUP11_OUTPUT15 = 0x00000718u, /* tr_group[11].output[15] */ + TRIG7_IN_TR_GROUP12_OUTPUT0 = 0x00000719u, /* tr_group[12].output[0] */ + TRIG7_IN_TR_GROUP12_OUTPUT1 = 0x0000071Au, /* tr_group[12].output[1] */ + TRIG7_IN_TR_GROUP12_OUTPUT2 = 0x0000071Bu, /* tr_group[12].output[2] */ + TRIG7_IN_TR_GROUP12_OUTPUT3 = 0x0000071Cu, /* tr_group[12].output[3] */ + TRIG7_IN_TR_GROUP12_OUTPUT4 = 0x0000071Du, /* tr_group[12].output[4] */ + TRIG7_IN_TR_GROUP12_OUTPUT5 = 0x0000071Eu, /* tr_group[12].output[5] */ + TRIG7_IN_TR_GROUP12_OUTPUT6 = 0x0000071Fu, /* tr_group[12].output[6] */ + TRIG7_IN_TR_GROUP12_OUTPUT7 = 0x00000720u, /* tr_group[12].output[7] */ + TRIG7_IN_TR_GROUP13_OUTPUT16 = 0x00000721u, /* tr_group[13].output[16] */ + TRIG7_IN_TR_GROUP13_OUTPUT17 = 0x00000722u, /* tr_group[13].output[17] */ + TRIG7_IN_TR_GROUP14_OUTPUT8 = 0x00000723u, /* tr_group[14].output[8] */ + TRIG7_IN_TR_GROUP14_OUTPUT9 = 0x00000724u, /* tr_group[14].output[9] */ + TRIG7_IN_TR_GROUP14_OUTPUT10 = 0x00000725u, /* tr_group[14].output[10] */ + TRIG7_IN_TR_GROUP14_OUTPUT11 = 0x00000726u, /* tr_group[14].output[11] */ + TRIG7_IN_TR_GROUP14_OUTPUT12 = 0x00000727u, /* tr_group[14].output[12] */ + TRIG7_IN_TR_GROUP14_OUTPUT13 = 0x00000728u, /* tr_group[14].output[13] */ + TRIG7_IN_TR_GROUP14_OUTPUT14 = 0x00000729u, /* tr_group[14].output[14] */ + TRIG7_IN_TR_GROUP14_OUTPUT15 = 0x0000072Au /* tr_group[14].output[15] */ +} en_trig_input_grp7_t; + +/* Trigger Input Group 8 - Trigger multiplexer to pins */ +typedef enum +{ + TRIG8_IN_CPUSS_ZERO = 0x00000800u, /* cpuss.zero */ + TRIG8_IN_TR_GROUP10_OUTPUT0 = 0x00000801u, /* tr_group[10].output[0] */ + TRIG8_IN_TR_GROUP10_OUTPUT1 = 0x00000802u, /* tr_group[10].output[1] */ + TRIG8_IN_TR_GROUP10_OUTPUT2 = 0x00000803u, /* tr_group[10].output[2] */ + TRIG8_IN_TR_GROUP10_OUTPUT3 = 0x00000804u, /* tr_group[10].output[3] */ + TRIG8_IN_TR_GROUP10_OUTPUT4 = 0x00000805u, /* tr_group[10].output[4] */ + TRIG8_IN_TR_GROUP10_OUTPUT5 = 0x00000806u, /* tr_group[10].output[5] */ + TRIG8_IN_TR_GROUP10_OUTPUT6 = 0x00000807u, /* tr_group[10].output[6] */ + TRIG8_IN_TR_GROUP10_OUTPUT7 = 0x00000808u, /* tr_group[10].output[7] */ + TRIG8_IN_TR_GROUP11_OUTPUT0 = 0x00000809u, /* tr_group[11].output[0] */ + TRIG8_IN_TR_GROUP11_OUTPUT1 = 0x0000080Au, /* tr_group[11].output[1] */ + TRIG8_IN_TR_GROUP11_OUTPUT2 = 0x0000080Bu, /* tr_group[11].output[2] */ + TRIG8_IN_TR_GROUP11_OUTPUT3 = 0x0000080Cu, /* tr_group[11].output[3] */ + TRIG8_IN_TR_GROUP11_OUTPUT4 = 0x0000080Du, /* tr_group[11].output[4] */ + TRIG8_IN_TR_GROUP11_OUTPUT5 = 0x0000080Eu, /* tr_group[11].output[5] */ + TRIG8_IN_TR_GROUP11_OUTPUT6 = 0x0000080Fu, /* tr_group[11].output[6] */ + TRIG8_IN_TR_GROUP11_OUTPUT7 = 0x00000810u, /* tr_group[11].output[7] */ + TRIG8_IN_TR_GROUP11_OUTPUT8 = 0x00000811u, /* tr_group[11].output[8] */ + TRIG8_IN_TR_GROUP11_OUTPUT9 = 0x00000812u, /* tr_group[11].output[9] */ + TRIG8_IN_TR_GROUP11_OUTPUT10 = 0x00000813u, /* tr_group[11].output[10] */ + TRIG8_IN_TR_GROUP11_OUTPUT11 = 0x00000814u, /* tr_group[11].output[11] */ + TRIG8_IN_TR_GROUP11_OUTPUT12 = 0x00000815u, /* tr_group[11].output[12] */ + TRIG8_IN_TR_GROUP11_OUTPUT13 = 0x00000816u, /* tr_group[11].output[13] */ + TRIG8_IN_TR_GROUP11_OUTPUT14 = 0x00000817u, /* tr_group[11].output[14] */ + TRIG8_IN_TR_GROUP11_OUTPUT15 = 0x00000818u, /* tr_group[11].output[15] */ + TRIG8_IN_TR_GROUP12_OUTPUT0 = 0x00000819u, /* tr_group[12].output[0] */ + TRIG8_IN_TR_GROUP12_OUTPUT1 = 0x0000081Au, /* tr_group[12].output[1] */ + TRIG8_IN_TR_GROUP12_OUTPUT2 = 0x0000081Bu, /* tr_group[12].output[2] */ + TRIG8_IN_TR_GROUP12_OUTPUT3 = 0x0000081Cu, /* tr_group[12].output[3] */ + TRIG8_IN_TR_GROUP12_OUTPUT4 = 0x0000081Du, /* tr_group[12].output[4] */ + TRIG8_IN_TR_GROUP12_OUTPUT5 = 0x0000081Eu, /* tr_group[12].output[5] */ + TRIG8_IN_TR_GROUP12_OUTPUT6 = 0x0000081Fu, /* tr_group[12].output[6] */ + TRIG8_IN_TR_GROUP12_OUTPUT7 = 0x00000820u, /* tr_group[12].output[7] */ + TRIG8_IN_TR_GROUP13_OUTPUT16 = 0x00000821u, /* tr_group[13].output[16] */ + TRIG8_IN_TR_GROUP13_OUTPUT17 = 0x00000822u, /* tr_group[13].output[17] */ + TRIG8_IN_TR_GROUP14_OUTPUT8 = 0x00000823u, /* tr_group[14].output[8] */ + TRIG8_IN_TR_GROUP14_OUTPUT9 = 0x00000824u, /* tr_group[14].output[9] */ + TRIG8_IN_TR_GROUP14_OUTPUT10 = 0x00000825u, /* tr_group[14].output[10] */ + TRIG8_IN_TR_GROUP14_OUTPUT11 = 0x00000826u, /* tr_group[14].output[11] */ + TRIG8_IN_TR_GROUP14_OUTPUT12 = 0x00000827u, /* tr_group[14].output[12] */ + TRIG8_IN_TR_GROUP14_OUTPUT13 = 0x00000828u, /* tr_group[14].output[13] */ + TRIG8_IN_TR_GROUP14_OUTPUT14 = 0x00000829u, /* tr_group[14].output[14] */ + TRIG8_IN_TR_GROUP14_OUTPUT15 = 0x0000082Au /* tr_group[14].output[15] */ +} en_trig_input_grp8_t; + +/* Trigger Input Group 9 - Feedback mux to USB DMA interface */ +typedef enum +{ + TRIG9_IN_CPUSS_ZERO = 0x00000900u, /* cpuss.zero */ + TRIG9_IN_CPUSS_DW0_TR_OUT0 = 0x00000901u, /* cpuss.dw0_tr_out[0] */ + TRIG9_IN_CPUSS_DW0_TR_OUT1 = 0x00000902u, /* cpuss.dw0_tr_out[1] */ + TRIG9_IN_CPUSS_DW0_TR_OUT2 = 0x00000903u, /* cpuss.dw0_tr_out[2] */ + TRIG9_IN_CPUSS_DW0_TR_OUT3 = 0x00000904u, /* cpuss.dw0_tr_out[3] */ + TRIG9_IN_CPUSS_DW0_TR_OUT4 = 0x00000905u, /* cpuss.dw0_tr_out[4] */ + TRIG9_IN_CPUSS_DW0_TR_OUT5 = 0x00000906u, /* cpuss.dw0_tr_out[5] */ + TRIG9_IN_CPUSS_DW0_TR_OUT6 = 0x00000907u, /* cpuss.dw0_tr_out[6] */ + TRIG9_IN_CPUSS_DW0_TR_OUT7 = 0x00000908u, /* cpuss.dw0_tr_out[7] */ + TRIG9_IN_CPUSS_DW0_TR_OUT8 = 0x00000909u, /* cpuss.dw0_tr_out[8] */ + TRIG9_IN_CPUSS_DW0_TR_OUT9 = 0x0000090Au, /* cpuss.dw0_tr_out[9] */ + TRIG9_IN_CPUSS_DW0_TR_OUT10 = 0x0000090Bu, /* cpuss.dw0_tr_out[10] */ + TRIG9_IN_CPUSS_DW0_TR_OUT11 = 0x0000090Cu, /* cpuss.dw0_tr_out[11] */ + TRIG9_IN_CPUSS_DW0_TR_OUT12 = 0x0000090Du, /* cpuss.dw0_tr_out[12] */ + TRIG9_IN_CPUSS_DW0_TR_OUT13 = 0x0000090Eu, /* cpuss.dw0_tr_out[13] */ + TRIG9_IN_CPUSS_DW0_TR_OUT14 = 0x0000090Fu, /* cpuss.dw0_tr_out[14] */ + TRIG9_IN_CPUSS_DW0_TR_OUT15 = 0x00000910u, /* cpuss.dw0_tr_out[15] */ + TRIG9_IN_CPUSS_DW1_TR_OUT0 = 0x00000911u, /* cpuss.dw1_tr_out[0] */ + TRIG9_IN_CPUSS_DW1_TR_OUT1 = 0x00000912u, /* cpuss.dw1_tr_out[1] */ + TRIG9_IN_CPUSS_DW1_TR_OUT2 = 0x00000913u, /* cpuss.dw1_tr_out[2] */ + TRIG9_IN_CPUSS_DW1_TR_OUT3 = 0x00000914u, /* cpuss.dw1_tr_out[3] */ + TRIG9_IN_CPUSS_DW1_TR_OUT4 = 0x00000915u, /* cpuss.dw1_tr_out[4] */ + TRIG9_IN_CPUSS_DW1_TR_OUT5 = 0x00000916u, /* cpuss.dw1_tr_out[5] */ + TRIG9_IN_CPUSS_DW1_TR_OUT6 = 0x00000917u, /* cpuss.dw1_tr_out[6] */ + TRIG9_IN_CPUSS_DW1_TR_OUT7 = 0x00000918u, /* cpuss.dw1_tr_out[7] */ + TRIG9_IN_CPUSS_DW1_TR_OUT8 = 0x00000919u, /* cpuss.dw1_tr_out[8] */ + TRIG9_IN_CPUSS_DW1_TR_OUT9 = 0x0000091Au, /* cpuss.dw1_tr_out[9] */ + TRIG9_IN_CPUSS_DW1_TR_OUT10 = 0x0000091Bu, /* cpuss.dw1_tr_out[10] */ + TRIG9_IN_CPUSS_DW1_TR_OUT11 = 0x0000091Cu, /* cpuss.dw1_tr_out[11] */ + TRIG9_IN_CPUSS_DW1_TR_OUT12 = 0x0000091Du, /* cpuss.dw1_tr_out[12] */ + TRIG9_IN_CPUSS_DW1_TR_OUT13 = 0x0000091Eu, /* cpuss.dw1_tr_out[13] */ + TRIG9_IN_CPUSS_DW1_TR_OUT14 = 0x0000091Fu, /* cpuss.dw1_tr_out[14] */ + TRIG9_IN_CPUSS_DW1_TR_OUT15 = 0x00000920u /* cpuss.dw1_tr_out[15] */ +} en_trig_input_grp9_t; + +/* Trigger Input Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */ +typedef enum +{ + TRIG10_IN_CPUSS_ZERO = 0x00000A00u, /* cpuss.zero */ + TRIG10_IN_CPUSS_DW0_TR_OUT0 = 0x00000A01u, /* cpuss.dw0_tr_out[0] */ + TRIG10_IN_CPUSS_DW0_TR_OUT1 = 0x00000A02u, /* cpuss.dw0_tr_out[1] */ + TRIG10_IN_CPUSS_DW0_TR_OUT2 = 0x00000A03u, /* cpuss.dw0_tr_out[2] */ + TRIG10_IN_CPUSS_DW0_TR_OUT3 = 0x00000A04u, /* cpuss.dw0_tr_out[3] */ + TRIG10_IN_CPUSS_DW0_TR_OUT4 = 0x00000A05u, /* cpuss.dw0_tr_out[4] */ + TRIG10_IN_CPUSS_DW0_TR_OUT5 = 0x00000A06u, /* cpuss.dw0_tr_out[5] */ + TRIG10_IN_CPUSS_DW0_TR_OUT6 = 0x00000A07u, /* cpuss.dw0_tr_out[6] */ + TRIG10_IN_CPUSS_DW0_TR_OUT7 = 0x00000A08u, /* cpuss.dw0_tr_out[7] */ + TRIG10_IN_CPUSS_DW0_TR_OUT8 = 0x00000A09u, /* cpuss.dw0_tr_out[8] */ + TRIG10_IN_CPUSS_DW0_TR_OUT9 = 0x00000A0Au, /* cpuss.dw0_tr_out[9] */ + TRIG10_IN_CPUSS_DW0_TR_OUT10 = 0x00000A0Bu, /* cpuss.dw0_tr_out[10] */ + TRIG10_IN_CPUSS_DW0_TR_OUT11 = 0x00000A0Cu, /* cpuss.dw0_tr_out[11] */ + TRIG10_IN_CPUSS_DW0_TR_OUT12 = 0x00000A0Du, /* cpuss.dw0_tr_out[12] */ + TRIG10_IN_CPUSS_DW0_TR_OUT13 = 0x00000A0Eu, /* cpuss.dw0_tr_out[13] */ + TRIG10_IN_CPUSS_DW0_TR_OUT14 = 0x00000A0Fu, /* cpuss.dw0_tr_out[14] */ + TRIG10_IN_CPUSS_DW0_TR_OUT15 = 0x00000A10u, /* cpuss.dw0_tr_out[15] */ + TRIG10_IN_CPUSS_DW1_TR_OUT0 = 0x00000A11u, /* cpuss.dw1_tr_out[0] */ + TRIG10_IN_CPUSS_DW1_TR_OUT1 = 0x00000A12u, /* cpuss.dw1_tr_out[1] */ + TRIG10_IN_CPUSS_DW1_TR_OUT2 = 0x00000A13u, /* cpuss.dw1_tr_out[2] */ + TRIG10_IN_CPUSS_DW1_TR_OUT3 = 0x00000A14u, /* cpuss.dw1_tr_out[3] */ + TRIG10_IN_CPUSS_DW1_TR_OUT4 = 0x00000A15u, /* cpuss.dw1_tr_out[4] */ + TRIG10_IN_CPUSS_DW1_TR_OUT5 = 0x00000A16u, /* cpuss.dw1_tr_out[5] */ + TRIG10_IN_CPUSS_DW1_TR_OUT6 = 0x00000A17u, /* cpuss.dw1_tr_out[6] */ + TRIG10_IN_CPUSS_DW1_TR_OUT7 = 0x00000A18u, /* cpuss.dw1_tr_out[7] */ + TRIG10_IN_CPUSS_DW1_TR_OUT8 = 0x00000A19u, /* cpuss.dw1_tr_out[8] */ + TRIG10_IN_CPUSS_DW1_TR_OUT9 = 0x00000A1Au, /* cpuss.dw1_tr_out[9] */ + TRIG10_IN_CPUSS_DW1_TR_OUT10 = 0x00000A1Bu, /* cpuss.dw1_tr_out[10] */ + TRIG10_IN_CPUSS_DW1_TR_OUT11 = 0x00000A1Cu, /* cpuss.dw1_tr_out[11] */ + TRIG10_IN_CPUSS_DW1_TR_OUT12 = 0x00000A1Du, /* cpuss.dw1_tr_out[12] */ + TRIG10_IN_CPUSS_DW1_TR_OUT13 = 0x00000A1Eu, /* cpuss.dw1_tr_out[13] */ + TRIG10_IN_CPUSS_DW1_TR_OUT14 = 0x00000A1Fu, /* cpuss.dw1_tr_out[14] */ + TRIG10_IN_CPUSS_DW1_TR_OUT15 = 0x00000A20u /* cpuss.dw1_tr_out[15] */ +} en_trig_input_grp10_t; + +/* Trigger Input Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */ +typedef enum +{ + TRIG11_IN_CPUSS_ZERO = 0x00000B00u, /* cpuss.zero */ + TRIG11_IN_TCPWM0_TR_OVERFLOW0 = 0x00000B01u, /* tcpwm[0].tr_overflow[0] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW1 = 0x00000B02u, /* tcpwm[0].tr_overflow[1] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW2 = 0x00000B03u, /* tcpwm[0].tr_overflow[2] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW3 = 0x00000B04u, /* tcpwm[0].tr_overflow[3] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW4 = 0x00000B05u, /* tcpwm[0].tr_overflow[4] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW5 = 0x00000B06u, /* tcpwm[0].tr_overflow[5] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW6 = 0x00000B07u, /* tcpwm[0].tr_overflow[6] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW7 = 0x00000B08u, /* tcpwm[0].tr_overflow[7] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH0 = 0x00000B09u, /* tcpwm[0].tr_compare_match[0] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH1 = 0x00000B0Au, /* tcpwm[0].tr_compare_match[1] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH2 = 0x00000B0Bu, /* tcpwm[0].tr_compare_match[2] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH3 = 0x00000B0Cu, /* tcpwm[0].tr_compare_match[3] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH4 = 0x00000B0Du, /* tcpwm[0].tr_compare_match[4] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH5 = 0x00000B0Eu, /* tcpwm[0].tr_compare_match[5] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH6 = 0x00000B0Fu, /* tcpwm[0].tr_compare_match[6] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH7 = 0x00000B10u, /* tcpwm[0].tr_compare_match[7] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW0 = 0x00000B11u, /* tcpwm[0].tr_underflow[0] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW1 = 0x00000B12u, /* tcpwm[0].tr_underflow[1] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW2 = 0x00000B13u, /* tcpwm[0].tr_underflow[2] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW3 = 0x00000B14u, /* tcpwm[0].tr_underflow[3] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW4 = 0x00000B15u, /* tcpwm[0].tr_underflow[4] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW5 = 0x00000B16u, /* tcpwm[0].tr_underflow[5] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW6 = 0x00000B17u, /* tcpwm[0].tr_underflow[6] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW7 = 0x00000B18u, /* tcpwm[0].tr_underflow[7] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW0 = 0x00000B19u, /* tcpwm[1].tr_overflow[0] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW1 = 0x00000B1Au, /* tcpwm[1].tr_overflow[1] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW2 = 0x00000B1Bu, /* tcpwm[1].tr_overflow[2] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW3 = 0x00000B1Cu, /* tcpwm[1].tr_overflow[3] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW4 = 0x00000B1Du, /* tcpwm[1].tr_overflow[4] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW5 = 0x00000B1Eu, /* tcpwm[1].tr_overflow[5] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW6 = 0x00000B1Fu, /* tcpwm[1].tr_overflow[6] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW7 = 0x00000B20u, /* tcpwm[1].tr_overflow[7] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW8 = 0x00000B21u, /* tcpwm[1].tr_overflow[8] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW9 = 0x00000B22u, /* tcpwm[1].tr_overflow[9] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW10 = 0x00000B23u, /* tcpwm[1].tr_overflow[10] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW11 = 0x00000B24u, /* tcpwm[1].tr_overflow[11] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW12 = 0x00000B25u, /* tcpwm[1].tr_overflow[12] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW13 = 0x00000B26u, /* tcpwm[1].tr_overflow[13] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW14 = 0x00000B27u, /* tcpwm[1].tr_overflow[14] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW15 = 0x00000B28u, /* tcpwm[1].tr_overflow[15] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW16 = 0x00000B29u, /* tcpwm[1].tr_overflow[16] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW17 = 0x00000B2Au, /* tcpwm[1].tr_overflow[17] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW18 = 0x00000B2Bu, /* tcpwm[1].tr_overflow[18] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW19 = 0x00000B2Cu, /* tcpwm[1].tr_overflow[19] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW20 = 0x00000B2Du, /* tcpwm[1].tr_overflow[20] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW21 = 0x00000B2Eu, /* tcpwm[1].tr_overflow[21] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW22 = 0x00000B2Fu, /* tcpwm[1].tr_overflow[22] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW23 = 0x00000B30u, /* tcpwm[1].tr_overflow[23] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH0 = 0x00000B31u, /* tcpwm[1].tr_compare_match[0] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH1 = 0x00000B32u, /* tcpwm[1].tr_compare_match[1] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH2 = 0x00000B33u, /* tcpwm[1].tr_compare_match[2] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH3 = 0x00000B34u, /* tcpwm[1].tr_compare_match[3] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH4 = 0x00000B35u, /* tcpwm[1].tr_compare_match[4] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH5 = 0x00000B36u, /* tcpwm[1].tr_compare_match[5] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH6 = 0x00000B37u, /* tcpwm[1].tr_compare_match[6] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH7 = 0x00000B38u, /* tcpwm[1].tr_compare_match[7] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH8 = 0x00000B39u, /* tcpwm[1].tr_compare_match[8] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH9 = 0x00000B3Au, /* tcpwm[1].tr_compare_match[9] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH10 = 0x00000B3Bu, /* tcpwm[1].tr_compare_match[10] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH11 = 0x00000B3Cu, /* tcpwm[1].tr_compare_match[11] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH12 = 0x00000B3Du, /* tcpwm[1].tr_compare_match[12] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH13 = 0x00000B3Eu, /* tcpwm[1].tr_compare_match[13] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH14 = 0x00000B3Fu, /* tcpwm[1].tr_compare_match[14] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH15 = 0x00000B40u, /* tcpwm[1].tr_compare_match[15] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH16 = 0x00000B41u, /* tcpwm[1].tr_compare_match[16] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH17 = 0x00000B42u, /* tcpwm[1].tr_compare_match[17] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH18 = 0x00000B43u, /* tcpwm[1].tr_compare_match[18] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH19 = 0x00000B44u, /* tcpwm[1].tr_compare_match[19] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH20 = 0x00000B45u, /* tcpwm[1].tr_compare_match[20] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH21 = 0x00000B46u, /* tcpwm[1].tr_compare_match[21] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH22 = 0x00000B47u, /* tcpwm[1].tr_compare_match[22] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH23 = 0x00000B48u, /* tcpwm[1].tr_compare_match[23] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW0 = 0x00000B49u, /* tcpwm[1].tr_underflow[0] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW1 = 0x00000B4Au, /* tcpwm[1].tr_underflow[1] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW2 = 0x00000B4Bu, /* tcpwm[1].tr_underflow[2] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW3 = 0x00000B4Cu, /* tcpwm[1].tr_underflow[3] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW4 = 0x00000B4Du, /* tcpwm[1].tr_underflow[4] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW5 = 0x00000B4Eu, /* tcpwm[1].tr_underflow[5] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW6 = 0x00000B4Fu, /* tcpwm[1].tr_underflow[6] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW7 = 0x00000B50u, /* tcpwm[1].tr_underflow[7] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW8 = 0x00000B51u, /* tcpwm[1].tr_underflow[8] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW9 = 0x00000B52u, /* tcpwm[1].tr_underflow[9] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW10 = 0x00000B53u, /* tcpwm[1].tr_underflow[10] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW11 = 0x00000B54u, /* tcpwm[1].tr_underflow[11] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW12 = 0x00000B55u, /* tcpwm[1].tr_underflow[12] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW13 = 0x00000B56u, /* tcpwm[1].tr_underflow[13] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW14 = 0x00000B57u, /* tcpwm[1].tr_underflow[14] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW15 = 0x00000B58u, /* tcpwm[1].tr_underflow[15] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW16 = 0x00000B59u, /* tcpwm[1].tr_underflow[16] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW17 = 0x00000B5Au, /* tcpwm[1].tr_underflow[17] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW18 = 0x00000B5Bu, /* tcpwm[1].tr_underflow[18] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW19 = 0x00000B5Cu, /* tcpwm[1].tr_underflow[19] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW20 = 0x00000B5Du, /* tcpwm[1].tr_underflow[20] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW21 = 0x00000B5Eu, /* tcpwm[1].tr_underflow[21] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW22 = 0x00000B5Fu, /* tcpwm[1].tr_underflow[22] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW23 = 0x00000B60u /* tcpwm[1].tr_underflow[23] */ +} en_trig_input_grp11_t; + +/* Trigger Input Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */ +typedef enum +{ + TRIG12_IN_CPUSS_ZERO = 0x00000C00u, /* cpuss.zero */ + TRIG12_IN_PERI_TR_IO_INPUT0 = 0x00000C01u, /* peri.tr_io_input[0] */ + TRIG12_IN_PERI_TR_IO_INPUT1 = 0x00000C02u, /* peri.tr_io_input[1] */ + TRIG12_IN_PERI_TR_IO_INPUT2 = 0x00000C03u, /* peri.tr_io_input[2] */ + TRIG12_IN_PERI_TR_IO_INPUT3 = 0x00000C04u, /* peri.tr_io_input[3] */ + TRIG12_IN_PERI_TR_IO_INPUT4 = 0x00000C05u, /* peri.tr_io_input[4] */ + TRIG12_IN_PERI_TR_IO_INPUT5 = 0x00000C06u, /* peri.tr_io_input[5] */ + TRIG12_IN_PERI_TR_IO_INPUT6 = 0x00000C07u, /* peri.tr_io_input[6] */ + TRIG12_IN_PERI_TR_IO_INPUT7 = 0x00000C08u, /* peri.tr_io_input[7] */ + TRIG12_IN_PERI_TR_IO_INPUT8 = 0x00000C09u, /* peri.tr_io_input[8] */ + TRIG12_IN_PERI_TR_IO_INPUT9 = 0x00000C0Au, /* peri.tr_io_input[9] */ + TRIG12_IN_PERI_TR_IO_INPUT10 = 0x00000C0Bu, /* peri.tr_io_input[10] */ + TRIG12_IN_PERI_TR_IO_INPUT11 = 0x00000C0Cu, /* peri.tr_io_input[11] */ + TRIG12_IN_PERI_TR_IO_INPUT12 = 0x00000C0Du, /* peri.tr_io_input[12] */ + TRIG12_IN_PERI_TR_IO_INPUT13 = 0x00000C0Eu, /* peri.tr_io_input[13] */ + TRIG12_IN_PERI_TR_IO_INPUT14 = 0x00000C0Fu, /* peri.tr_io_input[14] */ + TRIG12_IN_PERI_TR_IO_INPUT15 = 0x00000C10u, /* peri.tr_io_input[15] */ + TRIG12_IN_PERI_TR_IO_INPUT16 = 0x00000C11u, /* peri.tr_io_input[16] */ + TRIG12_IN_PERI_TR_IO_INPUT17 = 0x00000C12u, /* peri.tr_io_input[17] */ + TRIG12_IN_PERI_TR_IO_INPUT18 = 0x00000C13u, /* peri.tr_io_input[18] */ + TRIG12_IN_PERI_TR_IO_INPUT19 = 0x00000C14u, /* peri.tr_io_input[19] */ + TRIG12_IN_PERI_TR_IO_INPUT20 = 0x00000C15u, /* peri.tr_io_input[20] */ + TRIG12_IN_PERI_TR_IO_INPUT21 = 0x00000C16u, /* peri.tr_io_input[21] */ + TRIG12_IN_PERI_TR_IO_INPUT22 = 0x00000C17u, /* peri.tr_io_input[22] */ + TRIG12_IN_PERI_TR_IO_INPUT23 = 0x00000C18u, /* peri.tr_io_input[23] */ + TRIG12_IN_PERI_TR_IO_INPUT24 = 0x00000C19u, /* peri.tr_io_input[24] */ + TRIG12_IN_PERI_TR_IO_INPUT25 = 0x00000C1Au, /* peri.tr_io_input[25] */ + TRIG12_IN_PERI_TR_IO_INPUT26 = 0x00000C1Bu, /* peri.tr_io_input[26] */ + TRIG12_IN_PERI_TR_IO_INPUT27 = 0x00000C1Cu /* peri.tr_io_input[27] */ +} en_trig_input_grp12_t; + +/* Trigger Input Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */ +typedef enum +{ + TRIG13_IN_CPUSS_ZERO = 0x00000D00u, /* cpuss.zero */ + TRIG13_IN_SCB0_TR_TX_REQ = 0x00000D01u, /* scb[0].tr_tx_req */ + TRIG13_IN_SCB0_TR_RX_REQ = 0x00000D02u, /* scb[0].tr_rx_req */ + TRIG13_IN_SCB1_TR_TX_REQ = 0x00000D03u, /* scb[1].tr_tx_req */ + TRIG13_IN_SCB1_TR_RX_REQ = 0x00000D04u, /* scb[1].tr_rx_req */ + TRIG13_IN_SCB2_TR_TX_REQ = 0x00000D05u, /* scb[2].tr_tx_req */ + TRIG13_IN_SCB2_TR_RX_REQ = 0x00000D06u, /* scb[2].tr_rx_req */ + TRIG13_IN_SCB3_TR_TX_REQ = 0x00000D07u, /* scb[3].tr_tx_req */ + TRIG13_IN_SCB3_TR_RX_REQ = 0x00000D08u, /* scb[3].tr_rx_req */ + TRIG13_IN_SCB4_TR_TX_REQ = 0x00000D09u, /* scb[4].tr_tx_req */ + TRIG13_IN_SCB4_TR_RX_REQ = 0x00000D0Au, /* scb[4].tr_rx_req */ + TRIG13_IN_SCB5_TR_TX_REQ = 0x00000D0Bu, /* scb[5].tr_tx_req */ + TRIG13_IN_SCB5_TR_RX_REQ = 0x00000D0Cu, /* scb[5].tr_rx_req */ + TRIG13_IN_SCB6_TR_TX_REQ = 0x00000D0Du, /* scb[6].tr_tx_req */ + TRIG13_IN_SCB6_TR_RX_REQ = 0x00000D0Eu, /* scb[6].tr_rx_req */ + TRIG13_IN_SCB7_TR_TX_REQ = 0x00000D0Fu, /* scb[7].tr_tx_req */ + TRIG13_IN_SCB7_TR_RX_REQ = 0x00000D10u, /* scb[7].tr_rx_req */ + TRIG13_IN_SCB8_TR_TX_REQ = 0x00000D11u, /* scb[8].tr_tx_req */ + TRIG13_IN_SCB8_TR_RX_REQ = 0x00000D12u, /* scb[8].tr_rx_req */ + TRIG13_IN_AUDIOSS_TR_PDM_RX_REQ = 0x00000D13u, /* audioss.tr_pdm_rx_req */ + TRIG13_IN_AUDIOSS_TR_I2S_TX_REQ = 0x00000D14u, /* audioss.tr_i2s_tx_req */ + TRIG13_IN_AUDIOSS_TR_I2S_RX_REQ = 0x00000D15u, /* audioss.tr_i2s_rx_req */ + TRIG13_IN_SMIF_TR_TX_REQ = 0x00000D16u, /* smif.tr_tx_req */ + TRIG13_IN_SMIF_TR_RX_REQ = 0x00000D17u, /* smif.tr_rx_req */ + TRIG13_IN_USB_DMA_REQ0 = 0x00000D18u, /* usb.dma_req[0] */ + TRIG13_IN_USB_DMA_REQ1 = 0x00000D19u, /* usb.dma_req[1] */ + TRIG13_IN_USB_DMA_REQ2 = 0x00000D1Au, /* usb.dma_req[2] */ + TRIG13_IN_USB_DMA_REQ3 = 0x00000D1Bu, /* usb.dma_req[3] */ + TRIG13_IN_USB_DMA_REQ4 = 0x00000D1Cu, /* usb.dma_req[4] */ + TRIG13_IN_USB_DMA_REQ5 = 0x00000D1Du, /* usb.dma_req[5] */ + TRIG13_IN_USB_DMA_REQ6 = 0x00000D1Eu, /* usb.dma_req[6] */ + TRIG13_IN_USB_DMA_REQ7 = 0x00000D1Fu, /* usb.dma_req[7] */ + TRIG13_IN_CSD_TR_ADC_DONE = 0x00000D20u, /* csd.tr_adc_done */ + TRIG13_IN_CSD_DSI_SENSE_OUT = 0x00000D21u /* csd.dsi_sense_out */ +} en_trig_input_grp13_t; + +/* Trigger Input Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */ +typedef enum +{ + TRIG14_IN_CPUSS_ZERO = 0x00000E00u, /* cpuss.zero */ + TRIG14_IN_UDB_TR_UDB0 = 0x00000E01u, /* udb.tr_udb[0] */ + TRIG14_IN_UDB_TR_UDB1 = 0x00000E02u, /* udb.tr_udb[1] */ + TRIG14_IN_UDB_TR_UDB2 = 0x00000E03u, /* udb.tr_udb[2] */ + TRIG14_IN_UDB_TR_UDB3 = 0x00000E04u, /* udb.tr_udb[3] */ + TRIG14_IN_UDB_TR_UDB4 = 0x00000E05u, /* udb.tr_udb[4] */ + TRIG14_IN_UDB_TR_UDB5 = 0x00000E06u, /* udb.tr_udb[5] */ + TRIG14_IN_UDB_TR_UDB6 = 0x00000E07u, /* udb.tr_udb[6] */ + TRIG14_IN_UDB_TR_UDB7 = 0x00000E08u, /* udb.tr_udb[7] */ + TRIG14_IN_UDB_TR_UDB8 = 0x00000E09u, /* udb.tr_udb[8] */ + TRIG14_IN_UDB_TR_UDB9 = 0x00000E0Au, /* udb.tr_udb[9] */ + TRIG14_IN_UDB_TR_UDB10 = 0x00000E0Bu, /* udb.tr_udb[10] */ + TRIG14_IN_UDB_TR_UDB11 = 0x00000E0Cu, /* udb.tr_udb[11] */ + TRIG14_IN_UDB_TR_UDB12 = 0x00000E0Du, /* udb.tr_udb[12] */ + TRIG14_IN_UDB_TR_UDB13 = 0x00000E0Eu, /* udb.tr_udb[13] */ + TRIG14_IN_UDB_TR_UDB14 = 0x00000E0Fu, /* udb.tr_udb[14] */ + TRIG14_IN_UDB_TR_UDB15 = 0x00000E10u, /* udb.tr_udb[15] */ + TRIG14_IN_UDB_DSI_OUT_TR0 = 0x00000E11u, /* udb.dsi_out_tr[0] */ + TRIG14_IN_UDB_DSI_OUT_TR1 = 0x00000E12u, /* udb.dsi_out_tr[1] */ + TRIG14_IN_CPUSS_CTI_TR_OUT0 = 0x00000E13u, /* cpuss.cti_tr_out[0] */ + TRIG14_IN_CPUSS_CTI_TR_OUT1 = 0x00000E14u, /* cpuss.cti_tr_out[1] */ + TRIG14_IN_PASS_TR_SAR_OUT = 0x00000E15u, /* pass.tr_sar_out */ + TRIG14_IN_PASS_TR_CTDAC_EMPTY = 0x00000E16u, /* pass.tr_ctdac_empty */ + TRIG14_IN_PASS_DSI_CTB_CMP0 = 0x00000E17u, /* pass.dsi_ctb_cmp0 */ + TRIG14_IN_PASS_DSI_CTB_CMP1 = 0x00000E18u, /* pass.dsi_ctb_cmp1 */ + TRIG14_IN_LPCOMP_DSI_COMP0 = 0x00000E19u, /* lpcomp.dsi_comp0 */ + TRIG14_IN_LPCOMP_DSI_COMP1 = 0x00000E1Au, /* lpcomp.dsi_comp1 */ + TRIG14_IN_SCB0_TR_I2C_SCL_FILTERED = 0x00000E1Bu, /* scb[0].tr_i2c_scl_filtered */ + TRIG14_IN_SCB1_TR_I2C_SCL_FILTERED = 0x00000E1Cu, /* scb[1].tr_i2c_scl_filtered */ + TRIG14_IN_SCB2_TR_I2C_SCL_FILTERED = 0x00000E1Du, /* scb[2].tr_i2c_scl_filtered */ + TRIG14_IN_SCB3_TR_I2C_SCL_FILTERED = 0x00000E1Eu, /* scb[3].tr_i2c_scl_filtered */ + TRIG14_IN_SCB4_TR_I2C_SCL_FILTERED = 0x00000E1Fu, /* scb[4].tr_i2c_scl_filtered */ + TRIG14_IN_SCB5_TR_I2C_SCL_FILTERED = 0x00000E20u, /* scb[5].tr_i2c_scl_filtered */ + TRIG14_IN_SCB6_TR_I2C_SCL_FILTERED = 0x00000E21u, /* scb[6].tr_i2c_scl_filtered */ + TRIG14_IN_SCB7_TR_I2C_SCL_FILTERED = 0x00000E22u, /* scb[7].tr_i2c_scl_filtered */ + TRIG14_IN_SCB8_TR_I2C_SCL_FILTERED = 0x00000E23u, /* scb[8].tr_i2c_scl_filtered */ + TRIG14_IN_CPUSS_TR_FAULT0 = 0x00000E24u, /* cpuss.tr_fault[0] */ + TRIG14_IN_CPUSS_TR_FAULT1 = 0x00000E25u /* cpuss.tr_fault[1] */ +} en_trig_input_grp14_t; + +/* Trigger Group Outputs */ +/* Trigger Output Group 0 - DMA Request Assignments */ +typedef enum +{ + TRIG0_OUT_CPUSS_DW0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ + TRIG0_OUT_CPUSS_DW0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ + TRIG0_OUT_CPUSS_DW0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ + TRIG0_OUT_CPUSS_DW0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ + TRIG0_OUT_CPUSS_DW0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ + TRIG0_OUT_CPUSS_DW0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ + TRIG0_OUT_CPUSS_DW0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ + TRIG0_OUT_CPUSS_DW0_TR_IN7 = 0x40000007u, /* cpuss.dw0_tr_in[7] */ + TRIG0_OUT_CPUSS_DW0_TR_IN8 = 0x40000008u, /* cpuss.dw0_tr_in[8] */ + TRIG0_OUT_CPUSS_DW0_TR_IN9 = 0x40000009u, /* cpuss.dw0_tr_in[9] */ + TRIG0_OUT_CPUSS_DW0_TR_IN10 = 0x4000000Au, /* cpuss.dw0_tr_in[10] */ + TRIG0_OUT_CPUSS_DW0_TR_IN11 = 0x4000000Bu, /* cpuss.dw0_tr_in[11] */ + TRIG0_OUT_CPUSS_DW0_TR_IN12 = 0x4000000Cu, /* cpuss.dw0_tr_in[12] */ + TRIG0_OUT_CPUSS_DW0_TR_IN13 = 0x4000000Du, /* cpuss.dw0_tr_in[13] */ + TRIG0_OUT_CPUSS_DW0_TR_IN14 = 0x4000000Eu, /* cpuss.dw0_tr_in[14] */ + TRIG0_OUT_CPUSS_DW0_TR_IN15 = 0x4000000Fu /* cpuss.dw0_tr_in[15] */ +} en_trig_output_grp0_t; + +/* Trigger Output Group 1 - DMA Request Assignments */ +typedef enum +{ + TRIG1_OUT_CPUSS_DW1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ + TRIG1_OUT_CPUSS_DW1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ + TRIG1_OUT_CPUSS_DW1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ + TRIG1_OUT_CPUSS_DW1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ + TRIG1_OUT_CPUSS_DW1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ + TRIG1_OUT_CPUSS_DW1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ + TRIG1_OUT_CPUSS_DW1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ + TRIG1_OUT_CPUSS_DW1_TR_IN7 = 0x40000107u, /* cpuss.dw1_tr_in[7] */ + TRIG1_OUT_CPUSS_DW1_TR_IN8 = 0x40000108u, /* cpuss.dw1_tr_in[8] */ + TRIG1_OUT_CPUSS_DW1_TR_IN9 = 0x40000109u, /* cpuss.dw1_tr_in[9] */ + TRIG1_OUT_CPUSS_DW1_TR_IN10 = 0x4000010Au, /* cpuss.dw1_tr_in[10] */ + TRIG1_OUT_CPUSS_DW1_TR_IN11 = 0x4000010Bu, /* cpuss.dw1_tr_in[11] */ + TRIG1_OUT_CPUSS_DW1_TR_IN12 = 0x4000010Cu, /* cpuss.dw1_tr_in[12] */ + TRIG1_OUT_CPUSS_DW1_TR_IN13 = 0x4000010Du, /* cpuss.dw1_tr_in[13] */ + TRIG1_OUT_CPUSS_DW1_TR_IN14 = 0x4000010Eu, /* cpuss.dw1_tr_in[14] */ + TRIG1_OUT_CPUSS_DW1_TR_IN15 = 0x4000010Fu /* cpuss.dw1_tr_in[15] */ +} en_trig_output_grp1_t; + +/* Trigger Output Group 2 - TCPWM trigger inputs */ +typedef enum +{ + TRIG2_OUT_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_in[0] */ + TRIG2_OUT_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_in[1] */ + TRIG2_OUT_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_in[2] */ + TRIG2_OUT_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_in[3] */ + TRIG2_OUT_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_in[4] */ + TRIG2_OUT_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_in[5] */ + TRIG2_OUT_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_in[6] */ + TRIG2_OUT_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_in[7] */ + TRIG2_OUT_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_in[8] */ + TRIG2_OUT_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_in[9] */ + TRIG2_OUT_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_in[10] */ + TRIG2_OUT_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_in[11] */ + TRIG2_OUT_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_in[12] */ + TRIG2_OUT_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_in[13] */ +} en_trig_output_grp2_t; + +/* Trigger Output Group 3 - TCPWM trigger inputs */ +typedef enum +{ + TRIG3_OUT_TCPWM1_TR_IN0 = 0x40000300u, /* tcpwm[1].tr_in[0] */ + TRIG3_OUT_TCPWM1_TR_IN1 = 0x40000301u, /* tcpwm[1].tr_in[1] */ + TRIG3_OUT_TCPWM1_TR_IN2 = 0x40000302u, /* tcpwm[1].tr_in[2] */ + TRIG3_OUT_TCPWM1_TR_IN3 = 0x40000303u, /* tcpwm[1].tr_in[3] */ + TRIG3_OUT_TCPWM1_TR_IN4 = 0x40000304u, /* tcpwm[1].tr_in[4] */ + TRIG3_OUT_TCPWM1_TR_IN5 = 0x40000305u, /* tcpwm[1].tr_in[5] */ + TRIG3_OUT_TCPWM1_TR_IN6 = 0x40000306u, /* tcpwm[1].tr_in[6] */ + TRIG3_OUT_TCPWM1_TR_IN7 = 0x40000307u, /* tcpwm[1].tr_in[7] */ + TRIG3_OUT_TCPWM1_TR_IN8 = 0x40000308u, /* tcpwm[1].tr_in[8] */ + TRIG3_OUT_TCPWM1_TR_IN9 = 0x40000309u, /* tcpwm[1].tr_in[9] */ + TRIG3_OUT_TCPWM1_TR_IN10 = 0x4000030Au, /* tcpwm[1].tr_in[10] */ + TRIG3_OUT_TCPWM1_TR_IN11 = 0x4000030Bu, /* tcpwm[1].tr_in[11] */ + TRIG3_OUT_TCPWM1_TR_IN12 = 0x4000030Cu, /* tcpwm[1].tr_in[12] */ + TRIG3_OUT_TCPWM1_TR_IN13 = 0x4000030Du /* tcpwm[1].tr_in[13] */ +} en_trig_output_grp3_t; + +/* Trigger Output Group 4 - PROFILE trigger multiplexer */ +typedef enum +{ + TRIG4_OUT_PROFILE_TR_START = 0x40000400u, /* profile.tr_start */ + TRIG4_OUT_PROFILE_TR_STOP = 0x40000401u /* profile.tr_stop */ +} en_trig_output_grp4_t; + +/* Trigger Output Group 5 - CPUSS.CTI trigger multiplexer */ +typedef enum +{ + TRIG5_OUT_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */ + TRIG5_OUT_CPUSS_CTI_TR_IN1 = 0x40000501u /* cpuss.cti_tr_in[1] */ +} en_trig_output_grp5_t; + +/* Trigger Output Group 6 - PASS trigger multiplexer */ +typedef enum +{ + TRIG6_OUT_PASS_TR_SAR_IN = 0x40000600u /* pass.tr_sar_in */ +} en_trig_output_grp6_t; + +/* Trigger Output Group 7 - UDB general purpose trigger multiplexer */ +typedef enum +{ + TRIG7_OUT_UDB_TR_IN0 = 0x40000700u, /* udb.tr_in[0] */ + TRIG7_OUT_UDB_TR_IN1 = 0x40000701u /* udb.tr_in[1] */ +} en_trig_output_grp7_t; + +/* Trigger Output Group 8 - Trigger multiplexer to pins */ +typedef enum +{ + TRIG8_OUT_PERI_TR_IO_OUTPUT0 = 0x40000800u, /* peri.tr_io_output[0] */ + TRIG8_OUT_PERI_TR_IO_OUTPUT1 = 0x40000801u /* peri.tr_io_output[1] */ +} en_trig_output_grp8_t; + +/* Trigger Output Group 9 - Feedback mux to USB DMA interface */ +typedef enum +{ + TRIG9_OUT_USB_DMA_BURSTEND0 = 0x40000900u, /* usb.dma_burstend[0] */ + TRIG9_OUT_USB_DMA_BURSTEND1 = 0x40000901u, /* usb.dma_burstend[1] */ + TRIG9_OUT_USB_DMA_BURSTEND2 = 0x40000902u, /* usb.dma_burstend[2] */ + TRIG9_OUT_USB_DMA_BURSTEND3 = 0x40000903u, /* usb.dma_burstend[3] */ + TRIG9_OUT_USB_DMA_BURSTEND4 = 0x40000904u, /* usb.dma_burstend[4] */ + TRIG9_OUT_USB_DMA_BURSTEND5 = 0x40000905u, /* usb.dma_burstend[5] */ + TRIG9_OUT_USB_DMA_BURSTEND6 = 0x40000906u, /* usb.dma_burstend[6] */ + TRIG9_OUT_USB_DMA_BURSTEND7 = 0x40000907u /* usb.dma_burstend[7] */ +} en_trig_output_grp9_t; + +/* Trigger Output Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */ +typedef enum +{ + TRIG10_OUT_UDB_TR_DW_ACK0 = 0x40000A00u, /* udb.tr_dw_ack[0] */ + TRIG10_OUT_TR_GROUP0_INPUT1 = 0x40000A00u, /* tr_group[0].input[1] */ + TRIG10_OUT_TR_GROUP1_INPUT1 = 0x40000A00u, /* tr_group[1].input[1] */ + TRIG10_OUT_TR_GROUP2_INPUT1 = 0x40000A00u, /* tr_group[2].input[1] */ + TRIG10_OUT_TR_GROUP3_INPUT1 = 0x40000A00u, /* tr_group[3].input[1] */ + TRIG10_OUT_TR_GROUP4_INPUT1 = 0x40000A00u, /* tr_group[4].input[1] */ + TRIG10_OUT_TR_GROUP5_INPUT1 = 0x40000A00u, /* tr_group[5].input[1] */ + TRIG10_OUT_TR_GROUP6_INPUT1 = 0x40000A00u, /* tr_group[6].input[1] */ + TRIG10_OUT_TR_GROUP7_INPUT1 = 0x40000A00u, /* tr_group[7].input[1] */ + TRIG10_OUT_TR_GROUP8_INPUT1 = 0x40000A00u, /* tr_group[8].input[1] */ + TRIG10_OUT_UDB_TR_DW_ACK1 = 0x40000A01u, /* udb.tr_dw_ack[1] */ + TRIG10_OUT_TR_GROUP0_INPUT2 = 0x40000A01u, /* tr_group[0].input[2] */ + TRIG10_OUT_TR_GROUP1_INPUT2 = 0x40000A01u, /* tr_group[1].input[2] */ + TRIG10_OUT_TR_GROUP2_INPUT2 = 0x40000A01u, /* tr_group[2].input[2] */ + TRIG10_OUT_TR_GROUP3_INPUT2 = 0x40000A01u, /* tr_group[3].input[2] */ + TRIG10_OUT_TR_GROUP4_INPUT2 = 0x40000A01u, /* tr_group[4].input[2] */ + TRIG10_OUT_TR_GROUP5_INPUT2 = 0x40000A01u, /* tr_group[5].input[2] */ + TRIG10_OUT_TR_GROUP6_INPUT2 = 0x40000A01u, /* tr_group[6].input[2] */ + TRIG10_OUT_TR_GROUP7_INPUT2 = 0x40000A01u, /* tr_group[7].input[2] */ + TRIG10_OUT_TR_GROUP8_INPUT2 = 0x40000A01u, /* tr_group[8].input[2] */ + TRIG10_OUT_UDB_TR_DW_ACK2 = 0x40000A02u, /* udb.tr_dw_ack[2] */ + TRIG10_OUT_TR_GROUP0_INPUT3 = 0x40000A02u, /* tr_group[0].input[3] */ + TRIG10_OUT_TR_GROUP1_INPUT3 = 0x40000A02u, /* tr_group[1].input[3] */ + TRIG10_OUT_TR_GROUP2_INPUT3 = 0x40000A02u, /* tr_group[2].input[3] */ + TRIG10_OUT_TR_GROUP3_INPUT3 = 0x40000A02u, /* tr_group[3].input[3] */ + TRIG10_OUT_TR_GROUP4_INPUT3 = 0x40000A02u, /* tr_group[4].input[3] */ + TRIG10_OUT_TR_GROUP5_INPUT3 = 0x40000A02u, /* tr_group[5].input[3] */ + TRIG10_OUT_TR_GROUP6_INPUT3 = 0x40000A02u, /* tr_group[6].input[3] */ + TRIG10_OUT_TR_GROUP7_INPUT3 = 0x40000A02u, /* tr_group[7].input[3] */ + TRIG10_OUT_TR_GROUP8_INPUT3 = 0x40000A02u, /* tr_group[8].input[3] */ + TRIG10_OUT_UDB_TR_DW_ACK3 = 0x40000A03u, /* udb.tr_dw_ack[3] */ + TRIG10_OUT_TR_GROUP0_INPUT4 = 0x40000A03u, /* tr_group[0].input[4] */ + TRIG10_OUT_TR_GROUP1_INPUT4 = 0x40000A03u, /* tr_group[1].input[4] */ + TRIG10_OUT_TR_GROUP2_INPUT4 = 0x40000A03u, /* tr_group[2].input[4] */ + TRIG10_OUT_TR_GROUP3_INPUT4 = 0x40000A03u, /* tr_group[3].input[4] */ + TRIG10_OUT_TR_GROUP4_INPUT4 = 0x40000A03u, /* tr_group[4].input[4] */ + TRIG10_OUT_TR_GROUP5_INPUT4 = 0x40000A03u, /* tr_group[5].input[4] */ + TRIG10_OUT_TR_GROUP6_INPUT4 = 0x40000A03u, /* tr_group[6].input[4] */ + TRIG10_OUT_TR_GROUP7_INPUT4 = 0x40000A03u, /* tr_group[7].input[4] */ + TRIG10_OUT_TR_GROUP8_INPUT4 = 0x40000A03u, /* tr_group[8].input[4] */ + TRIG10_OUT_UDB_TR_DW_ACK4 = 0x40000A04u, /* udb.tr_dw_ack[4] */ + TRIG10_OUT_TR_GROUP0_INPUT5 = 0x40000A04u, /* tr_group[0].input[5] */ + TRIG10_OUT_TR_GROUP1_INPUT5 = 0x40000A04u, /* tr_group[1].input[5] */ + TRIG10_OUT_TR_GROUP2_INPUT5 = 0x40000A04u, /* tr_group[2].input[5] */ + TRIG10_OUT_TR_GROUP3_INPUT5 = 0x40000A04u, /* tr_group[3].input[5] */ + TRIG10_OUT_TR_GROUP4_INPUT5 = 0x40000A04u, /* tr_group[4].input[5] */ + TRIG10_OUT_TR_GROUP5_INPUT5 = 0x40000A04u, /* tr_group[5].input[5] */ + TRIG10_OUT_TR_GROUP6_INPUT5 = 0x40000A04u, /* tr_group[6].input[5] */ + TRIG10_OUT_TR_GROUP7_INPUT5 = 0x40000A04u, /* tr_group[7].input[5] */ + TRIG10_OUT_TR_GROUP8_INPUT5 = 0x40000A04u, /* tr_group[8].input[5] */ + TRIG10_OUT_UDB_TR_DW_ACK5 = 0x40000A05u, /* udb.tr_dw_ack[5] */ + TRIG10_OUT_TR_GROUP0_INPUT6 = 0x40000A05u, /* tr_group[0].input[6] */ + TRIG10_OUT_TR_GROUP1_INPUT6 = 0x40000A05u, /* tr_group[1].input[6] */ + TRIG10_OUT_TR_GROUP2_INPUT6 = 0x40000A05u, /* tr_group[2].input[6] */ + TRIG10_OUT_TR_GROUP3_INPUT6 = 0x40000A05u, /* tr_group[3].input[6] */ + TRIG10_OUT_TR_GROUP4_INPUT6 = 0x40000A05u, /* tr_group[4].input[6] */ + TRIG10_OUT_TR_GROUP5_INPUT6 = 0x40000A05u, /* tr_group[5].input[6] */ + TRIG10_OUT_TR_GROUP6_INPUT6 = 0x40000A05u, /* tr_group[6].input[6] */ + TRIG10_OUT_TR_GROUP7_INPUT6 = 0x40000A05u, /* tr_group[7].input[6] */ + TRIG10_OUT_TR_GROUP8_INPUT6 = 0x40000A05u, /* tr_group[8].input[6] */ + TRIG10_OUT_UDB_TR_DW_ACK6 = 0x40000A06u, /* udb.tr_dw_ack[6] */ + TRIG10_OUT_TR_GROUP0_INPUT7 = 0x40000A06u, /* tr_group[0].input[7] */ + TRIG10_OUT_TR_GROUP1_INPUT7 = 0x40000A06u, /* tr_group[1].input[7] */ + TRIG10_OUT_TR_GROUP2_INPUT7 = 0x40000A06u, /* tr_group[2].input[7] */ + TRIG10_OUT_TR_GROUP3_INPUT7 = 0x40000A06u, /* tr_group[3].input[7] */ + TRIG10_OUT_TR_GROUP4_INPUT7 = 0x40000A06u, /* tr_group[4].input[7] */ + TRIG10_OUT_TR_GROUP5_INPUT7 = 0x40000A06u, /* tr_group[5].input[7] */ + TRIG10_OUT_TR_GROUP6_INPUT7 = 0x40000A06u, /* tr_group[6].input[7] */ + TRIG10_OUT_TR_GROUP7_INPUT7 = 0x40000A06u, /* tr_group[7].input[7] */ + TRIG10_OUT_TR_GROUP8_INPUT7 = 0x40000A06u, /* tr_group[8].input[7] */ + TRIG10_OUT_UDB_TR_DW_ACK7 = 0x40000A07u, /* udb.tr_dw_ack[7] */ + TRIG10_OUT_TR_GROUP0_INPUT8 = 0x40000A07u, /* tr_group[0].input[8] */ + TRIG10_OUT_TR_GROUP1_INPUT8 = 0x40000A07u, /* tr_group[1].input[8] */ + TRIG10_OUT_TR_GROUP2_INPUT8 = 0x40000A07u, /* tr_group[2].input[8] */ + TRIG10_OUT_TR_GROUP3_INPUT8 = 0x40000A07u, /* tr_group[3].input[8] */ + TRIG10_OUT_TR_GROUP4_INPUT8 = 0x40000A07u, /* tr_group[4].input[8] */ + TRIG10_OUT_TR_GROUP5_INPUT8 = 0x40000A07u, /* tr_group[5].input[8] */ + TRIG10_OUT_TR_GROUP6_INPUT8 = 0x40000A07u, /* tr_group[6].input[8] */ + TRIG10_OUT_TR_GROUP7_INPUT8 = 0x40000A07u, /* tr_group[7].input[8] */ + TRIG10_OUT_TR_GROUP8_INPUT8 = 0x40000A07u /* tr_group[8].input[8] */ +} en_trig_output_grp10_t; + +/* Trigger Output Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */ +typedef enum +{ + TRIG11_OUT_TR_GROUP0_INPUT9 = 0x40000B00u, /* tr_group[0].input[9] */ + TRIG11_OUT_TR_GROUP1_INPUT9 = 0x40000B00u, /* tr_group[1].input[9] */ + TRIG11_OUT_TR_GROUP2_INPUT9 = 0x40000B00u, /* tr_group[2].input[9] */ + TRIG11_OUT_TR_GROUP3_INPUT9 = 0x40000B00u, /* tr_group[3].input[9] */ + TRIG11_OUT_TR_GROUP4_INPUT9 = 0x40000B00u, /* tr_group[4].input[9] */ + TRIG11_OUT_TR_GROUP5_INPUT9 = 0x40000B00u, /* tr_group[5].input[9] */ + TRIG11_OUT_TR_GROUP6_INPUT9 = 0x40000B00u, /* tr_group[6].input[9] */ + TRIG11_OUT_TR_GROUP7_INPUT9 = 0x40000B00u, /* tr_group[7].input[9] */ + TRIG11_OUT_TR_GROUP8_INPUT9 = 0x40000B00u, /* tr_group[8].input[9] */ + TRIG11_OUT_TR_GROUP0_INPUT10 = 0x40000B01u, /* tr_group[0].input[10] */ + TRIG11_OUT_TR_GROUP1_INPUT10 = 0x40000B01u, /* tr_group[1].input[10] */ + TRIG11_OUT_TR_GROUP2_INPUT10 = 0x40000B01u, /* tr_group[2].input[10] */ + TRIG11_OUT_TR_GROUP3_INPUT10 = 0x40000B01u, /* tr_group[3].input[10] */ + TRIG11_OUT_TR_GROUP4_INPUT10 = 0x40000B01u, /* tr_group[4].input[10] */ + TRIG11_OUT_TR_GROUP5_INPUT10 = 0x40000B01u, /* tr_group[5].input[10] */ + TRIG11_OUT_TR_GROUP6_INPUT10 = 0x40000B01u, /* tr_group[6].input[10] */ + TRIG11_OUT_TR_GROUP7_INPUT10 = 0x40000B01u, /* tr_group[7].input[10] */ + TRIG11_OUT_TR_GROUP8_INPUT10 = 0x40000B01u, /* tr_group[8].input[10] */ + TRIG11_OUT_TR_GROUP0_INPUT11 = 0x40000B02u, /* tr_group[0].input[11] */ + TRIG11_OUT_TR_GROUP1_INPUT11 = 0x40000B02u, /* tr_group[1].input[11] */ + TRIG11_OUT_TR_GROUP2_INPUT11 = 0x40000B02u, /* tr_group[2].input[11] */ + TRIG11_OUT_TR_GROUP3_INPUT11 = 0x40000B02u, /* tr_group[3].input[11] */ + TRIG11_OUT_TR_GROUP4_INPUT11 = 0x40000B02u, /* tr_group[4].input[11] */ + TRIG11_OUT_TR_GROUP5_INPUT11 = 0x40000B02u, /* tr_group[5].input[11] */ + TRIG11_OUT_TR_GROUP6_INPUT11 = 0x40000B02u, /* tr_group[6].input[11] */ + TRIG11_OUT_TR_GROUP7_INPUT11 = 0x40000B02u, /* tr_group[7].input[11] */ + TRIG11_OUT_TR_GROUP8_INPUT11 = 0x40000B02u, /* tr_group[8].input[11] */ + TRIG11_OUT_TR_GROUP0_INPUT12 = 0x40000B03u, /* tr_group[0].input[12] */ + TRIG11_OUT_TR_GROUP1_INPUT12 = 0x40000B03u, /* tr_group[1].input[12] */ + TRIG11_OUT_TR_GROUP2_INPUT12 = 0x40000B03u, /* tr_group[2].input[12] */ + TRIG11_OUT_TR_GROUP3_INPUT12 = 0x40000B03u, /* tr_group[3].input[12] */ + TRIG11_OUT_TR_GROUP4_INPUT12 = 0x40000B03u, /* tr_group[4].input[12] */ + TRIG11_OUT_TR_GROUP5_INPUT12 = 0x40000B03u, /* tr_group[5].input[12] */ + TRIG11_OUT_TR_GROUP6_INPUT12 = 0x40000B03u, /* tr_group[6].input[12] */ + TRIG11_OUT_TR_GROUP7_INPUT12 = 0x40000B03u, /* tr_group[7].input[12] */ + TRIG11_OUT_TR_GROUP8_INPUT12 = 0x40000B03u, /* tr_group[8].input[12] */ + TRIG11_OUT_TR_GROUP0_INPUT13 = 0x40000B04u, /* tr_group[0].input[13] */ + TRIG11_OUT_TR_GROUP1_INPUT13 = 0x40000B04u, /* tr_group[1].input[13] */ + TRIG11_OUT_TR_GROUP2_INPUT13 = 0x40000B04u, /* tr_group[2].input[13] */ + TRIG11_OUT_TR_GROUP3_INPUT13 = 0x40000B04u, /* tr_group[3].input[13] */ + TRIG11_OUT_TR_GROUP4_INPUT13 = 0x40000B04u, /* tr_group[4].input[13] */ + TRIG11_OUT_TR_GROUP5_INPUT13 = 0x40000B04u, /* tr_group[5].input[13] */ + TRIG11_OUT_TR_GROUP6_INPUT13 = 0x40000B04u, /* tr_group[6].input[13] */ + TRIG11_OUT_TR_GROUP7_INPUT13 = 0x40000B04u, /* tr_group[7].input[13] */ + TRIG11_OUT_TR_GROUP8_INPUT13 = 0x40000B04u, /* tr_group[8].input[13] */ + TRIG11_OUT_TR_GROUP0_INPUT14 = 0x40000B05u, /* tr_group[0].input[14] */ + TRIG11_OUT_TR_GROUP1_INPUT14 = 0x40000B05u, /* tr_group[1].input[14] */ + TRIG11_OUT_TR_GROUP2_INPUT14 = 0x40000B05u, /* tr_group[2].input[14] */ + TRIG11_OUT_TR_GROUP3_INPUT14 = 0x40000B05u, /* tr_group[3].input[14] */ + TRIG11_OUT_TR_GROUP4_INPUT14 = 0x40000B05u, /* tr_group[4].input[14] */ + TRIG11_OUT_TR_GROUP5_INPUT14 = 0x40000B05u, /* tr_group[5].input[14] */ + TRIG11_OUT_TR_GROUP6_INPUT14 = 0x40000B05u, /* tr_group[6].input[14] */ + TRIG11_OUT_TR_GROUP7_INPUT14 = 0x40000B05u, /* tr_group[7].input[14] */ + TRIG11_OUT_TR_GROUP8_INPUT14 = 0x40000B05u, /* tr_group[8].input[14] */ + TRIG11_OUT_TR_GROUP0_INPUT15 = 0x40000B06u, /* tr_group[0].input[15] */ + TRIG11_OUT_TR_GROUP1_INPUT15 = 0x40000B06u, /* tr_group[1].input[15] */ + TRIG11_OUT_TR_GROUP2_INPUT15 = 0x40000B06u, /* tr_group[2].input[15] */ + TRIG11_OUT_TR_GROUP3_INPUT15 = 0x40000B06u, /* tr_group[3].input[15] */ + TRIG11_OUT_TR_GROUP4_INPUT15 = 0x40000B06u, /* tr_group[4].input[15] */ + TRIG11_OUT_TR_GROUP5_INPUT15 = 0x40000B06u, /* tr_group[5].input[15] */ + TRIG11_OUT_TR_GROUP6_INPUT15 = 0x40000B06u, /* tr_group[6].input[15] */ + TRIG11_OUT_TR_GROUP7_INPUT15 = 0x40000B06u, /* tr_group[7].input[15] */ + TRIG11_OUT_TR_GROUP8_INPUT15 = 0x40000B06u, /* tr_group[8].input[15] */ + TRIG11_OUT_TR_GROUP0_INPUT16 = 0x40000B07u, /* tr_group[0].input[16] */ + TRIG11_OUT_TR_GROUP1_INPUT16 = 0x40000B07u, /* tr_group[1].input[16] */ + TRIG11_OUT_TR_GROUP2_INPUT16 = 0x40000B07u, /* tr_group[2].input[16] */ + TRIG11_OUT_TR_GROUP3_INPUT16 = 0x40000B07u, /* tr_group[3].input[16] */ + TRIG11_OUT_TR_GROUP4_INPUT16 = 0x40000B07u, /* tr_group[4].input[16] */ + TRIG11_OUT_TR_GROUP5_INPUT16 = 0x40000B07u, /* tr_group[5].input[16] */ + TRIG11_OUT_TR_GROUP6_INPUT16 = 0x40000B07u, /* tr_group[6].input[16] */ + TRIG11_OUT_TR_GROUP7_INPUT16 = 0x40000B07u, /* tr_group[7].input[16] */ + TRIG11_OUT_TR_GROUP8_INPUT16 = 0x40000B07u, /* tr_group[8].input[16] */ + TRIG11_OUT_TR_GROUP0_INPUT17 = 0x40000B08u, /* tr_group[0].input[17] */ + TRIG11_OUT_TR_GROUP1_INPUT17 = 0x40000B08u, /* tr_group[1].input[17] */ + TRIG11_OUT_TR_GROUP2_INPUT17 = 0x40000B08u, /* tr_group[2].input[17] */ + TRIG11_OUT_TR_GROUP3_INPUT17 = 0x40000B08u, /* tr_group[3].input[17] */ + TRIG11_OUT_TR_GROUP4_INPUT17 = 0x40000B08u, /* tr_group[4].input[17] */ + TRIG11_OUT_TR_GROUP5_INPUT17 = 0x40000B08u, /* tr_group[5].input[17] */ + TRIG11_OUT_TR_GROUP6_INPUT17 = 0x40000B08u, /* tr_group[6].input[17] */ + TRIG11_OUT_TR_GROUP7_INPUT17 = 0x40000B08u, /* tr_group[7].input[17] */ + TRIG11_OUT_TR_GROUP8_INPUT17 = 0x40000B08u, /* tr_group[8].input[17] */ + TRIG11_OUT_TR_GROUP0_INPUT18 = 0x40000B09u, /* tr_group[0].input[18] */ + TRIG11_OUT_TR_GROUP1_INPUT18 = 0x40000B09u, /* tr_group[1].input[18] */ + TRIG11_OUT_TR_GROUP2_INPUT18 = 0x40000B09u, /* tr_group[2].input[18] */ + TRIG11_OUT_TR_GROUP3_INPUT18 = 0x40000B09u, /* tr_group[3].input[18] */ + TRIG11_OUT_TR_GROUP4_INPUT18 = 0x40000B09u, /* tr_group[4].input[18] */ + TRIG11_OUT_TR_GROUP5_INPUT18 = 0x40000B09u, /* tr_group[5].input[18] */ + TRIG11_OUT_TR_GROUP6_INPUT18 = 0x40000B09u, /* tr_group[6].input[18] */ + TRIG11_OUT_TR_GROUP7_INPUT18 = 0x40000B09u, /* tr_group[7].input[18] */ + TRIG11_OUT_TR_GROUP8_INPUT18 = 0x40000B09u, /* tr_group[8].input[18] */ + TRIG11_OUT_TR_GROUP0_INPUT19 = 0x40000B0Au, /* tr_group[0].input[19] */ + TRIG11_OUT_TR_GROUP1_INPUT19 = 0x40000B0Au, /* tr_group[1].input[19] */ + TRIG11_OUT_TR_GROUP2_INPUT19 = 0x40000B0Au, /* tr_group[2].input[19] */ + TRIG11_OUT_TR_GROUP3_INPUT19 = 0x40000B0Au, /* tr_group[3].input[19] */ + TRIG11_OUT_TR_GROUP4_INPUT19 = 0x40000B0Au, /* tr_group[4].input[19] */ + TRIG11_OUT_TR_GROUP5_INPUT19 = 0x40000B0Au, /* tr_group[5].input[19] */ + TRIG11_OUT_TR_GROUP6_INPUT19 = 0x40000B0Au, /* tr_group[6].input[19] */ + TRIG11_OUT_TR_GROUP7_INPUT19 = 0x40000B0Au, /* tr_group[7].input[19] */ + TRIG11_OUT_TR_GROUP8_INPUT19 = 0x40000B0Au, /* tr_group[8].input[19] */ + TRIG11_OUT_TR_GROUP0_INPUT20 = 0x40000B0Bu, /* tr_group[0].input[20] */ + TRIG11_OUT_TR_GROUP1_INPUT20 = 0x40000B0Bu, /* tr_group[1].input[20] */ + TRIG11_OUT_TR_GROUP2_INPUT20 = 0x40000B0Bu, /* tr_group[2].input[20] */ + TRIG11_OUT_TR_GROUP3_INPUT20 = 0x40000B0Bu, /* tr_group[3].input[20] */ + TRIG11_OUT_TR_GROUP4_INPUT20 = 0x40000B0Bu, /* tr_group[4].input[20] */ + TRIG11_OUT_TR_GROUP5_INPUT20 = 0x40000B0Bu, /* tr_group[5].input[20] */ + TRIG11_OUT_TR_GROUP6_INPUT20 = 0x40000B0Bu, /* tr_group[6].input[20] */ + TRIG11_OUT_TR_GROUP7_INPUT20 = 0x40000B0Bu, /* tr_group[7].input[20] */ + TRIG11_OUT_TR_GROUP8_INPUT20 = 0x40000B0Bu, /* tr_group[8].input[20] */ + TRIG11_OUT_TR_GROUP0_INPUT21 = 0x40000B0Cu, /* tr_group[0].input[21] */ + TRIG11_OUT_TR_GROUP1_INPUT21 = 0x40000B0Cu, /* tr_group[1].input[21] */ + TRIG11_OUT_TR_GROUP2_INPUT21 = 0x40000B0Cu, /* tr_group[2].input[21] */ + TRIG11_OUT_TR_GROUP3_INPUT21 = 0x40000B0Cu, /* tr_group[3].input[21] */ + TRIG11_OUT_TR_GROUP4_INPUT21 = 0x40000B0Cu, /* tr_group[4].input[21] */ + TRIG11_OUT_TR_GROUP5_INPUT21 = 0x40000B0Cu, /* tr_group[5].input[21] */ + TRIG11_OUT_TR_GROUP6_INPUT21 = 0x40000B0Cu, /* tr_group[6].input[21] */ + TRIG11_OUT_TR_GROUP7_INPUT21 = 0x40000B0Cu, /* tr_group[7].input[21] */ + TRIG11_OUT_TR_GROUP8_INPUT21 = 0x40000B0Cu, /* tr_group[8].input[21] */ + TRIG11_OUT_TR_GROUP0_INPUT22 = 0x40000B0Du, /* tr_group[0].input[22] */ + TRIG11_OUT_TR_GROUP1_INPUT22 = 0x40000B0Du, /* tr_group[1].input[22] */ + TRIG11_OUT_TR_GROUP2_INPUT22 = 0x40000B0Du, /* tr_group[2].input[22] */ + TRIG11_OUT_TR_GROUP3_INPUT22 = 0x40000B0Du, /* tr_group[3].input[22] */ + TRIG11_OUT_TR_GROUP4_INPUT22 = 0x40000B0Du, /* tr_group[4].input[22] */ + TRIG11_OUT_TR_GROUP5_INPUT22 = 0x40000B0Du, /* tr_group[5].input[22] */ + TRIG11_OUT_TR_GROUP6_INPUT22 = 0x40000B0Du, /* tr_group[6].input[22] */ + TRIG11_OUT_TR_GROUP7_INPUT22 = 0x40000B0Du, /* tr_group[7].input[22] */ + TRIG11_OUT_TR_GROUP8_INPUT22 = 0x40000B0Du, /* tr_group[8].input[22] */ + TRIG11_OUT_TR_GROUP0_INPUT23 = 0x40000B0Eu, /* tr_group[0].input[23] */ + TRIG11_OUT_TR_GROUP1_INPUT23 = 0x40000B0Eu, /* tr_group[1].input[23] */ + TRIG11_OUT_TR_GROUP2_INPUT23 = 0x40000B0Eu, /* tr_group[2].input[23] */ + TRIG11_OUT_TR_GROUP3_INPUT23 = 0x40000B0Eu, /* tr_group[3].input[23] */ + TRIG11_OUT_TR_GROUP4_INPUT23 = 0x40000B0Eu, /* tr_group[4].input[23] */ + TRIG11_OUT_TR_GROUP5_INPUT23 = 0x40000B0Eu, /* tr_group[5].input[23] */ + TRIG11_OUT_TR_GROUP6_INPUT23 = 0x40000B0Eu, /* tr_group[6].input[23] */ + TRIG11_OUT_TR_GROUP7_INPUT23 = 0x40000B0Eu, /* tr_group[7].input[23] */ + TRIG11_OUT_TR_GROUP8_INPUT23 = 0x40000B0Eu, /* tr_group[8].input[23] */ + TRIG11_OUT_TR_GROUP0_INPUT24 = 0x40000B0Fu, /* tr_group[0].input[24] */ + TRIG11_OUT_TR_GROUP1_INPUT24 = 0x40000B0Fu, /* tr_group[1].input[24] */ + TRIG11_OUT_TR_GROUP2_INPUT24 = 0x40000B0Fu, /* tr_group[2].input[24] */ + TRIG11_OUT_TR_GROUP3_INPUT24 = 0x40000B0Fu, /* tr_group[3].input[24] */ + TRIG11_OUT_TR_GROUP4_INPUT24 = 0x40000B0Fu, /* tr_group[4].input[24] */ + TRIG11_OUT_TR_GROUP5_INPUT24 = 0x40000B0Fu, /* tr_group[5].input[24] */ + TRIG11_OUT_TR_GROUP6_INPUT24 = 0x40000B0Fu, /* tr_group[6].input[24] */ + TRIG11_OUT_TR_GROUP7_INPUT24 = 0x40000B0Fu, /* tr_group[7].input[24] */ + TRIG11_OUT_TR_GROUP8_INPUT24 = 0x40000B0Fu /* tr_group[8].input[24] */ +} en_trig_output_grp11_t; + +/* Trigger Output Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */ +typedef enum +{ + TRIG12_OUT_TR_GROUP2_INPUT25 = 0x40000C00u, /* tr_group[2].input[25] */ + TRIG12_OUT_TR_GROUP3_INPUT25 = 0x40000C00u, /* tr_group[3].input[25] */ + TRIG12_OUT_TR_GROUP4_INPUT25 = 0x40000C00u, /* tr_group[4].input[25] */ + TRIG12_OUT_TR_GROUP5_INPUT25 = 0x40000C00u, /* tr_group[5].input[25] */ + TRIG12_OUT_TR_GROUP6_INPUT25 = 0x40000C00u, /* tr_group[6].input[25] */ + TRIG12_OUT_TR_GROUP7_INPUT25 = 0x40000C00u, /* tr_group[7].input[25] */ + TRIG12_OUT_TR_GROUP8_INPUT25 = 0x40000C00u, /* tr_group[8].input[25] */ + TRIG12_OUT_TR_GROUP2_INPUT26 = 0x40000C01u, /* tr_group[2].input[26] */ + TRIG12_OUT_TR_GROUP3_INPUT26 = 0x40000C01u, /* tr_group[3].input[26] */ + TRIG12_OUT_TR_GROUP4_INPUT26 = 0x40000C01u, /* tr_group[4].input[26] */ + TRIG12_OUT_TR_GROUP5_INPUT26 = 0x40000C01u, /* tr_group[5].input[26] */ + TRIG12_OUT_TR_GROUP6_INPUT26 = 0x40000C01u, /* tr_group[6].input[26] */ + TRIG12_OUT_TR_GROUP7_INPUT26 = 0x40000C01u, /* tr_group[7].input[26] */ + TRIG12_OUT_TR_GROUP8_INPUT26 = 0x40000C01u, /* tr_group[8].input[26] */ + TRIG12_OUT_TR_GROUP2_INPUT27 = 0x40000C02u, /* tr_group[2].input[27] */ + TRIG12_OUT_TR_GROUP3_INPUT27 = 0x40000C02u, /* tr_group[3].input[27] */ + TRIG12_OUT_TR_GROUP4_INPUT27 = 0x40000C02u, /* tr_group[4].input[27] */ + TRIG12_OUT_TR_GROUP5_INPUT27 = 0x40000C02u, /* tr_group[5].input[27] */ + TRIG12_OUT_TR_GROUP6_INPUT27 = 0x40000C02u, /* tr_group[6].input[27] */ + TRIG12_OUT_TR_GROUP7_INPUT27 = 0x40000C02u, /* tr_group[7].input[27] */ + TRIG12_OUT_TR_GROUP8_INPUT27 = 0x40000C02u, /* tr_group[8].input[27] */ + TRIG12_OUT_TR_GROUP2_INPUT28 = 0x40000C03u, /* tr_group[2].input[28] */ + TRIG12_OUT_TR_GROUP3_INPUT28 = 0x40000C03u, /* tr_group[3].input[28] */ + TRIG12_OUT_TR_GROUP4_INPUT28 = 0x40000C03u, /* tr_group[4].input[28] */ + TRIG12_OUT_TR_GROUP5_INPUT28 = 0x40000C03u, /* tr_group[5].input[28] */ + TRIG12_OUT_TR_GROUP6_INPUT28 = 0x40000C03u, /* tr_group[6].input[28] */ + TRIG12_OUT_TR_GROUP7_INPUT28 = 0x40000C03u, /* tr_group[7].input[28] */ + TRIG12_OUT_TR_GROUP8_INPUT28 = 0x40000C03u, /* tr_group[8].input[28] */ + TRIG12_OUT_TR_GROUP2_INPUT29 = 0x40000C04u, /* tr_group[2].input[29] */ + TRIG12_OUT_TR_GROUP3_INPUT29 = 0x40000C04u, /* tr_group[3].input[29] */ + TRIG12_OUT_TR_GROUP4_INPUT29 = 0x40000C04u, /* tr_group[4].input[29] */ + TRIG12_OUT_TR_GROUP5_INPUT29 = 0x40000C04u, /* tr_group[5].input[29] */ + TRIG12_OUT_TR_GROUP6_INPUT29 = 0x40000C04u, /* tr_group[6].input[29] */ + TRIG12_OUT_TR_GROUP7_INPUT29 = 0x40000C04u, /* tr_group[7].input[29] */ + TRIG12_OUT_TR_GROUP8_INPUT29 = 0x40000C04u, /* tr_group[8].input[29] */ + TRIG12_OUT_TR_GROUP2_INPUT30 = 0x40000C05u, /* tr_group[2].input[30] */ + TRIG12_OUT_TR_GROUP3_INPUT30 = 0x40000C05u, /* tr_group[3].input[30] */ + TRIG12_OUT_TR_GROUP4_INPUT30 = 0x40000C05u, /* tr_group[4].input[30] */ + TRIG12_OUT_TR_GROUP5_INPUT30 = 0x40000C05u, /* tr_group[5].input[30] */ + TRIG12_OUT_TR_GROUP6_INPUT30 = 0x40000C05u, /* tr_group[6].input[30] */ + TRIG12_OUT_TR_GROUP7_INPUT30 = 0x40000C05u, /* tr_group[7].input[30] */ + TRIG12_OUT_TR_GROUP8_INPUT30 = 0x40000C05u, /* tr_group[8].input[30] */ + TRIG12_OUT_TR_GROUP2_INPUT31 = 0x40000C06u, /* tr_group[2].input[31] */ + TRIG12_OUT_TR_GROUP3_INPUT31 = 0x40000C06u, /* tr_group[3].input[31] */ + TRIG12_OUT_TR_GROUP4_INPUT31 = 0x40000C06u, /* tr_group[4].input[31] */ + TRIG12_OUT_TR_GROUP5_INPUT31 = 0x40000C06u, /* tr_group[5].input[31] */ + TRIG12_OUT_TR_GROUP6_INPUT31 = 0x40000C06u, /* tr_group[6].input[31] */ + TRIG12_OUT_TR_GROUP7_INPUT31 = 0x40000C06u, /* tr_group[7].input[31] */ + TRIG12_OUT_TR_GROUP8_INPUT31 = 0x40000C06u, /* tr_group[8].input[31] */ + TRIG12_OUT_TR_GROUP2_INPUT32 = 0x40000C07u, /* tr_group[2].input[32] */ + TRIG12_OUT_TR_GROUP3_INPUT32 = 0x40000C07u, /* tr_group[3].input[32] */ + TRIG12_OUT_TR_GROUP4_INPUT32 = 0x40000C07u, /* tr_group[4].input[32] */ + TRIG12_OUT_TR_GROUP5_INPUT32 = 0x40000C07u, /* tr_group[5].input[32] */ + TRIG12_OUT_TR_GROUP6_INPUT32 = 0x40000C07u, /* tr_group[6].input[32] */ + TRIG12_OUT_TR_GROUP7_INPUT32 = 0x40000C07u, /* tr_group[7].input[32] */ + TRIG12_OUT_TR_GROUP8_INPUT32 = 0x40000C07u, /* tr_group[8].input[32] */ + TRIG12_OUT_TR_GROUP0_INPUT25 = 0x40000C08u, /* tr_group[0].input[25] */ + TRIG12_OUT_TR_GROUP1_INPUT25 = 0x40000C08u, /* tr_group[1].input[25] */ + TRIG12_OUT_TR_GROUP0_INPUT26 = 0x40000C09u, /* tr_group[0].input[26] */ + TRIG12_OUT_TR_GROUP1_INPUT26 = 0x40000C09u /* tr_group[1].input[26] */ +} en_trig_output_grp12_t; + +/* Trigger Output Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */ +typedef enum +{ + TRIG13_OUT_TR_GROUP0_INPUT27 = 0x40000D00u, /* tr_group[0].input[27] */ + TRIG13_OUT_TR_GROUP1_INPUT27 = 0x40000D00u, /* tr_group[1].input[27] */ + TRIG13_OUT_TR_GROUP0_INPUT28 = 0x40000D01u, /* tr_group[0].input[28] */ + TRIG13_OUT_TR_GROUP1_INPUT28 = 0x40000D01u, /* tr_group[1].input[28] */ + TRIG13_OUT_TR_GROUP0_INPUT29 = 0x40000D02u, /* tr_group[0].input[29] */ + TRIG13_OUT_TR_GROUP1_INPUT29 = 0x40000D02u, /* tr_group[1].input[29] */ + TRIG13_OUT_TR_GROUP0_INPUT30 = 0x40000D03u, /* tr_group[0].input[30] */ + TRIG13_OUT_TR_GROUP1_INPUT30 = 0x40000D03u, /* tr_group[1].input[30] */ + TRIG13_OUT_TR_GROUP0_INPUT31 = 0x40000D04u, /* tr_group[0].input[31] */ + TRIG13_OUT_TR_GROUP1_INPUT31 = 0x40000D04u, /* tr_group[1].input[31] */ + TRIG13_OUT_TR_GROUP0_INPUT32 = 0x40000D05u, /* tr_group[0].input[32] */ + TRIG13_OUT_TR_GROUP1_INPUT32 = 0x40000D05u, /* tr_group[1].input[32] */ + TRIG13_OUT_TR_GROUP0_INPUT33 = 0x40000D06u, /* tr_group[0].input[33] */ + TRIG13_OUT_TR_GROUP1_INPUT33 = 0x40000D06u, /* tr_group[1].input[33] */ + TRIG13_OUT_TR_GROUP0_INPUT34 = 0x40000D07u, /* tr_group[0].input[34] */ + TRIG13_OUT_TR_GROUP1_INPUT34 = 0x40000D07u, /* tr_group[1].input[34] */ + TRIG13_OUT_TR_GROUP0_INPUT35 = 0x40000D08u, /* tr_group[0].input[35] */ + TRIG13_OUT_TR_GROUP1_INPUT35 = 0x40000D08u, /* tr_group[1].input[35] */ + TRIG13_OUT_TR_GROUP0_INPUT36 = 0x40000D09u, /* tr_group[0].input[36] */ + TRIG13_OUT_TR_GROUP1_INPUT36 = 0x40000D09u, /* tr_group[1].input[36] */ + TRIG13_OUT_TR_GROUP0_INPUT37 = 0x40000D0Au, /* tr_group[0].input[37] */ + TRIG13_OUT_TR_GROUP1_INPUT37 = 0x40000D0Au, /* tr_group[1].input[37] */ + TRIG13_OUT_TR_GROUP0_INPUT38 = 0x40000D0Bu, /* tr_group[0].input[38] */ + TRIG13_OUT_TR_GROUP1_INPUT38 = 0x40000D0Bu, /* tr_group[1].input[38] */ + TRIG13_OUT_TR_GROUP0_INPUT39 = 0x40000D0Cu, /* tr_group[0].input[39] */ + TRIG13_OUT_TR_GROUP1_INPUT39 = 0x40000D0Cu, /* tr_group[1].input[39] */ + TRIG13_OUT_TR_GROUP0_INPUT40 = 0x40000D0Du, /* tr_group[0].input[40] */ + TRIG13_OUT_TR_GROUP1_INPUT40 = 0x40000D0Du, /* tr_group[1].input[40] */ + TRIG13_OUT_TR_GROUP0_INPUT41 = 0x40000D0Eu, /* tr_group[0].input[41] */ + TRIG13_OUT_TR_GROUP1_INPUT41 = 0x40000D0Eu, /* tr_group[1].input[41] */ + TRIG13_OUT_TR_GROUP0_INPUT42 = 0x40000D0Fu, /* tr_group[0].input[42] */ + TRIG13_OUT_TR_GROUP1_INPUT42 = 0x40000D0Fu, /* tr_group[1].input[42] */ + TRIG13_OUT_TR_GROUP2_INPUT33 = 0x40000D10u, /* tr_group[2].input[33] */ + TRIG13_OUT_TR_GROUP3_INPUT33 = 0x40000D10u, /* tr_group[3].input[33] */ + TRIG13_OUT_TR_GROUP4_INPUT33 = 0x40000D10u, /* tr_group[4].input[33] */ + TRIG13_OUT_TR_GROUP5_INPUT33 = 0x40000D10u, /* tr_group[5].input[33] */ + TRIG13_OUT_TR_GROUP6_INPUT33 = 0x40000D10u, /* tr_group[6].input[33] */ + TRIG13_OUT_TR_GROUP7_INPUT33 = 0x40000D10u, /* tr_group[7].input[33] */ + TRIG13_OUT_TR_GROUP8_INPUT33 = 0x40000D10u, /* tr_group[8].input[33] */ + TRIG13_OUT_TR_GROUP2_INPUT34 = 0x40000D11u, /* tr_group[2].input[34] */ + TRIG13_OUT_TR_GROUP3_INPUT34 = 0x40000D11u, /* tr_group[3].input[34] */ + TRIG13_OUT_TR_GROUP4_INPUT34 = 0x40000D11u, /* tr_group[4].input[34] */ + TRIG13_OUT_TR_GROUP5_INPUT34 = 0x40000D11u, /* tr_group[5].input[34] */ + TRIG13_OUT_TR_GROUP6_INPUT34 = 0x40000D11u, /* tr_group[6].input[34] */ + TRIG13_OUT_TR_GROUP7_INPUT34 = 0x40000D11u, /* tr_group[7].input[34] */ + TRIG13_OUT_TR_GROUP8_INPUT34 = 0x40000D11u /* tr_group[8].input[34] */ +} en_trig_output_grp13_t; + +/* Trigger Output Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */ +typedef enum +{ + TRIG14_OUT_TR_GROUP0_INPUT43 = 0x40000E00u, /* tr_group[0].input[43] */ + TRIG14_OUT_TR_GROUP1_INPUT43 = 0x40000E00u, /* tr_group[1].input[43] */ + TRIG14_OUT_TR_GROUP0_INPUT44 = 0x40000E01u, /* tr_group[0].input[44] */ + TRIG14_OUT_TR_GROUP1_INPUT44 = 0x40000E01u, /* tr_group[1].input[44] */ + TRIG14_OUT_TR_GROUP0_INPUT45 = 0x40000E02u, /* tr_group[0].input[45] */ + TRIG14_OUT_TR_GROUP1_INPUT45 = 0x40000E02u, /* tr_group[1].input[45] */ + TRIG14_OUT_TR_GROUP0_INPUT46 = 0x40000E03u, /* tr_group[0].input[46] */ + TRIG14_OUT_TR_GROUP1_INPUT46 = 0x40000E03u, /* tr_group[1].input[46] */ + TRIG14_OUT_TR_GROUP0_INPUT47 = 0x40000E04u, /* tr_group[0].input[47] */ + TRIG14_OUT_TR_GROUP1_INPUT47 = 0x40000E04u, /* tr_group[1].input[47] */ + TRIG14_OUT_TR_GROUP0_INPUT48 = 0x40000E05u, /* tr_group[0].input[48] */ + TRIG14_OUT_TR_GROUP1_INPUT48 = 0x40000E05u, /* tr_group[1].input[48] */ + TRIG14_OUT_TR_GROUP0_INPUT49 = 0x40000E06u, /* tr_group[0].input[49] */ + TRIG14_OUT_TR_GROUP1_INPUT49 = 0x40000E06u, /* tr_group[1].input[49] */ + TRIG14_OUT_TR_GROUP0_INPUT50 = 0x40000E07u, /* tr_group[0].input[50] */ + TRIG14_OUT_TR_GROUP1_INPUT50 = 0x40000E07u, /* tr_group[1].input[50] */ + TRIG14_OUT_TR_GROUP2_INPUT35 = 0x40000E08u, /* tr_group[2].input[35] */ + TRIG14_OUT_TR_GROUP3_INPUT35 = 0x40000E08u, /* tr_group[3].input[35] */ + TRIG14_OUT_TR_GROUP4_INPUT35 = 0x40000E08u, /* tr_group[4].input[35] */ + TRIG14_OUT_TR_GROUP5_INPUT35 = 0x40000E08u, /* tr_group[5].input[35] */ + TRIG14_OUT_TR_GROUP6_INPUT35 = 0x40000E08u, /* tr_group[6].input[35] */ + TRIG14_OUT_TR_GROUP7_INPUT35 = 0x40000E08u, /* tr_group[7].input[35] */ + TRIG14_OUT_TR_GROUP8_INPUT35 = 0x40000E08u, /* tr_group[8].input[35] */ + TRIG14_OUT_TR_GROUP2_INPUT36 = 0x40000E09u, /* tr_group[2].input[36] */ + TRIG14_OUT_TR_GROUP3_INPUT36 = 0x40000E09u, /* tr_group[3].input[36] */ + TRIG14_OUT_TR_GROUP4_INPUT36 = 0x40000E09u, /* tr_group[4].input[36] */ + TRIG14_OUT_TR_GROUP5_INPUT36 = 0x40000E09u, /* tr_group[5].input[36] */ + TRIG14_OUT_TR_GROUP6_INPUT36 = 0x40000E09u, /* tr_group[6].input[36] */ + TRIG14_OUT_TR_GROUP7_INPUT36 = 0x40000E09u, /* tr_group[7].input[36] */ + TRIG14_OUT_TR_GROUP8_INPUT36 = 0x40000E09u, /* tr_group[8].input[36] */ + TRIG14_OUT_TR_GROUP2_INPUT37 = 0x40000E0Au, /* tr_group[2].input[37] */ + TRIG14_OUT_TR_GROUP3_INPUT37 = 0x40000E0Au, /* tr_group[3].input[37] */ + TRIG14_OUT_TR_GROUP4_INPUT37 = 0x40000E0Au, /* tr_group[4].input[37] */ + TRIG14_OUT_TR_GROUP5_INPUT37 = 0x40000E0Au, /* tr_group[5].input[37] */ + TRIG14_OUT_TR_GROUP6_INPUT37 = 0x40000E0Au, /* tr_group[6].input[37] */ + TRIG14_OUT_TR_GROUP7_INPUT37 = 0x40000E0Au, /* tr_group[7].input[37] */ + TRIG14_OUT_TR_GROUP8_INPUT37 = 0x40000E0Au, /* tr_group[8].input[37] */ + TRIG14_OUT_TR_GROUP2_INPUT38 = 0x40000E0Bu, /* tr_group[2].input[38] */ + TRIG14_OUT_TR_GROUP3_INPUT38 = 0x40000E0Bu, /* tr_group[3].input[38] */ + TRIG14_OUT_TR_GROUP4_INPUT38 = 0x40000E0Bu, /* tr_group[4].input[38] */ + TRIG14_OUT_TR_GROUP5_INPUT38 = 0x40000E0Bu, /* tr_group[5].input[38] */ + TRIG14_OUT_TR_GROUP6_INPUT38 = 0x40000E0Bu, /* tr_group[6].input[38] */ + TRIG14_OUT_TR_GROUP7_INPUT38 = 0x40000E0Bu, /* tr_group[7].input[38] */ + TRIG14_OUT_TR_GROUP8_INPUT38 = 0x40000E0Bu, /* tr_group[8].input[38] */ + TRIG14_OUT_TR_GROUP2_INPUT39 = 0x40000E0Cu, /* tr_group[2].input[39] */ + TRIG14_OUT_TR_GROUP3_INPUT39 = 0x40000E0Cu, /* tr_group[3].input[39] */ + TRIG14_OUT_TR_GROUP4_INPUT39 = 0x40000E0Cu, /* tr_group[4].input[39] */ + TRIG14_OUT_TR_GROUP5_INPUT39 = 0x40000E0Cu, /* tr_group[5].input[39] */ + TRIG14_OUT_TR_GROUP6_INPUT39 = 0x40000E0Cu, /* tr_group[6].input[39] */ + TRIG14_OUT_TR_GROUP7_INPUT39 = 0x40000E0Cu, /* tr_group[7].input[39] */ + TRIG14_OUT_TR_GROUP8_INPUT39 = 0x40000E0Cu, /* tr_group[8].input[39] */ + TRIG14_OUT_TR_GROUP2_INPUT40 = 0x40000E0Du, /* tr_group[2].input[40] */ + TRIG14_OUT_TR_GROUP3_INPUT40 = 0x40000E0Du, /* tr_group[3].input[40] */ + TRIG14_OUT_TR_GROUP4_INPUT40 = 0x40000E0Du, /* tr_group[4].input[40] */ + TRIG14_OUT_TR_GROUP5_INPUT40 = 0x40000E0Du, /* tr_group[5].input[40] */ + TRIG14_OUT_TR_GROUP6_INPUT40 = 0x40000E0Du, /* tr_group[6].input[40] */ + TRIG14_OUT_TR_GROUP7_INPUT40 = 0x40000E0Du, /* tr_group[7].input[40] */ + TRIG14_OUT_TR_GROUP8_INPUT40 = 0x40000E0Du, /* tr_group[8].input[40] */ + TRIG14_OUT_TR_GROUP2_INPUT41 = 0x40000E0Eu, /* tr_group[2].input[41] */ + TRIG14_OUT_TR_GROUP3_INPUT41 = 0x40000E0Eu, /* tr_group[3].input[41] */ + TRIG14_OUT_TR_GROUP4_INPUT41 = 0x40000E0Eu, /* tr_group[4].input[41] */ + TRIG14_OUT_TR_GROUP5_INPUT41 = 0x40000E0Eu, /* tr_group[5].input[41] */ + TRIG14_OUT_TR_GROUP6_INPUT41 = 0x40000E0Eu, /* tr_group[6].input[41] */ + TRIG14_OUT_TR_GROUP7_INPUT41 = 0x40000E0Eu, /* tr_group[7].input[41] */ + TRIG14_OUT_TR_GROUP8_INPUT41 = 0x40000E0Eu, /* tr_group[8].input[41] */ + TRIG14_OUT_TR_GROUP2_INPUT42 = 0x40000E0Fu, /* tr_group[2].input[42] */ + TRIG14_OUT_TR_GROUP3_INPUT42 = 0x40000E0Fu, /* tr_group[3].input[42] */ + TRIG14_OUT_TR_GROUP4_INPUT42 = 0x40000E0Fu, /* tr_group[4].input[42] */ + TRIG14_OUT_TR_GROUP5_INPUT42 = 0x40000E0Fu, /* tr_group[5].input[42] */ + TRIG14_OUT_TR_GROUP6_INPUT42 = 0x40000E0Fu, /* tr_group[6].input[42] */ + TRIG14_OUT_TR_GROUP7_INPUT42 = 0x40000E0Fu, /* tr_group[7].input[42] */ + TRIG14_OUT_TR_GROUP8_INPUT42 = 0x40000E0Fu /* tr_group[8].input[42] */ +} en_trig_output_grp14_t; + +/* Level or edge detection setting for a trigger mux */ +typedef enum +{ + /* The trigger is a simple level output */ + TRIGGER_TYPE_LEVEL = 0u, + /* The trigger is synchronized to the consumer blocks clock + and a two cycle pulse is generated on this clock */ + TRIGGER_TYPE_EDGE = 1u +} en_trig_type_t; + +/* Trigger Type Defines */ +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE +/* CSD Trigger Types */ +#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +/* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE +/* AUDIOSS Trigger Types */ +#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE +/* UDB Trigger Types */ +#define TRIGGER_TYPE_UDB_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_DW_ACK__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_DW_ACK__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_UDB__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_UDB__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_DSI_OUT_TR__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_DSI_OUT_TR__EDGE TRIGGER_TYPE_EDGE +/* PROFILE Trigger Types */ +#define TRIGGER_TYPE_PROFILE_TR_START TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PROFILE_TR_STOP TRIGGER_TYPE_EDGE +/* TR_GROUP Trigger Types */ +#define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE + +/* Monitor Signal Defines */ +typedef enum +{ + PROFILE_ONE = 0, /* profile.one */ + CPUSS_MONITOR_CM0 = 1, /* cpuss.monitor_cm0 */ + CPUSS_MONITOR_CM4 = 2, /* cpuss.monitor_cm4 */ + CPUSS_MONITOR_FLASH = 3, /* cpuss.monitor_flash */ + CPUSS_MONITOR_DW0_AHB = 4, /* cpuss.monitor_dw0_ahb */ + CPUSS_MONITOR_DW1_AHB = 5, /* cpuss.monitor_dw1_ahb */ + CPUSS_MONITOR_CRYPTO = 6, /* cpuss.monitor_crypto */ + USB_MONITOR_AHB = 7, /* usb.monitor_ahb */ + SCB0_MONITOR_AHB = 8, /* scb[0].monitor_ahb */ + SCB1_MONITOR_AHB = 9, /* scb[1].monitor_ahb */ + SCB2_MONITOR_AHB = 10, /* scb[2].monitor_ahb */ + SCB3_MONITOR_AHB = 11, /* scb[3].monitor_ahb */ + SCB4_MONITOR_AHB = 12, /* scb[4].monitor_ahb */ + SCB5_MONITOR_AHB = 13, /* scb[5].monitor_ahb */ + SCB6_MONITOR_AHB = 14, /* scb[6].monitor_ahb */ + SCB7_MONITOR_AHB = 15, /* scb[7].monitor_ahb */ + SCB8_MONITOR_AHB = 16, /* scb[8].monitor_ahb */ + UDB_MONITOR_UDB0 = 17, /* udb.monitor_udb[0] */ + UDB_MONITOR_UDB1 = 18, /* udb.monitor_udb[1] */ + UDB_MONITOR_UDB2 = 19, /* udb.monitor_udb[2] */ + UDB_MONITOR_UDB3 = 20, /* udb.monitor_udb[3] */ + SMIF_MONITOR_SMIF_SPI_SELECT0 = 21, /* smif.monitor_smif_spi_select[0] */ + SMIF_MONITOR_SMIF_SPI_SELECT1 = 22, /* smif.monitor_smif_spi_select[1] */ + SMIF_MONITOR_SMIF_SPI_SELECT2 = 23, /* smif.monitor_smif_spi_select[2] */ + SMIF_MONITOR_SMIF_SPI_SELECT3 = 24, /* smif.monitor_smif_spi_select[3] */ + SMIF_MONITOR_SMIF_SPI_SELECT_ANY = 25, /* smif.monitor_smif_spi_select_any */ + BLESS_EXT_LNA_RX_CTL_OUT = 26, /* bless.ext_lna_rx_ctl_out */ + BLESS_EXT_PA_TX_CTL_OUT = 27 /* bless.ext_pa_tx_ctl_out */ +} en_ep_mon_sel_t; + +/* Total count of Energy Profiler monitor signal connections */ +#define EP_MONITOR_COUNT 28u + +/* Bus masters */ +typedef enum +{ + CPUSS_MS_ID_CM0 = 0, + CPUSS_MS_ID_CRYPTO = 1, + CPUSS_MS_ID_DW0 = 2, + CPUSS_MS_ID_DW1 = 3, + CPUSS_MS_ID_CM4 = 14, + CPUSS_MS_ID_TC = 15 +} en_prot_master_t; + +/* Parameter Defines */ +/* Number of regulator modules instantiated within SRSS */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 1u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 1u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 5u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 5u +/* Number of PWR_HIB_DATA registers */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 2u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 1u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* Width of MCWDT Subcounters 0 and 1. Applies to all MCWDT. */ +#define SRSS_MCWDT_CTR_WIDTH 32u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 9u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of PWR/GND MONITOR CELLs in the device */ +#define IOSS_HSIOM_MONITOR_NR 0u +/* Number of PWR/GND MONITOR CELLs in range 0..31 */ +#define IOSS_HSIOM_MONITOR_NR_0_31 0u +/* Number of PWR/GND MONITOR CELLs in range 32..63 */ +#define IOSS_HSIOM_MONITOR_NR_32_63 0u +/* Number of PWR/GND MONITOR CELLs in range 64..95 */ +#define IOSS_HSIOM_MONITOR_NR_64_95 0u +/* Number of PWR/GND MONITOR CELLs in range 96..127 */ +#define IOSS_HSIOM_MONITOR_NR_96_127 0u +/* Indicates the presence of alternate JTAG interface */ +#define IOSS_HSIOM_ALTJTAG_PRESENT 0u +/* Number of GPIO ports in range 0..31 */ +#define IOSS_GPIO_GPIO_PORT_NR_0_31 15u +/* Number of GPIO ports in range 32..63 */ +#define IOSS_GPIO_GPIO_PORT_NR_32_63 0u +/* Number of GPIO ports in range 64..95 */ +#define IOSS_GPIO_GPIO_PORT_NR_64_95 0u +/* Number of GPIO ports in range 96..127 */ +#define IOSS_GPIO_GPIO_PORT_NR_96_127 0u +/* Number of ports in device */ +#define IOSS_GPIO_GPIO_PORT_NR 15u +/* Mask of SMARTIO instances presence */ +#define IOSS_SMARTIO_SMARTIO_MASK 768u +/* The number of protection contexts ([2, 16]). */ +#define PERI_PC_NR 8u +/* Master interface presence mask (4 bits) */ +#define PERI_MS_PRESENT 15u +/* Master interface PPU combinatorial (1) or registerd (0) */ +#define PERI_MS_PPU_COMBINATORIAL 1u +/* The number of programmable PPU structures for PERI (all peripherals) */ +#define PERI_MS_PPU_PROG_STRUCT_NR 16u +/* Number of programmable clocks (outputs) */ +#define PERI_CLOCK_NR 59u +/* Number of 8.0 dividers */ +#define PERI_DIV_8_NR 8u +/* Number of 16.0 dividers */ +#define PERI_DIV_16_NR 16u +/* Number of 16.5 (fractional) dividers */ +#define PERI_DIV_16_5_NR 4u +/* Number of 24.5 (fractional) dividers */ +#define PERI_DIV_24_5_NR 1u +/* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ +#define PERI_DIV_ADDR_WIDTH 4u +/* Trigger module present (0=No, 1=Yes) */ +#define PERI_TR 1u +/* Number of trigger groups */ +#define PERI_TR_GROUP_NR 15u +/* The number of protection contexts minus 1 ([1, 15]). */ +#define PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1 7u +/* The number of protection contexts minus 1 ([1, 15]). */ +#define PERI_PPU_PROG_STRUCT_PC_NR_MINUS1 7u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 288u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 9u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 32u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 256u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 16u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 128u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 1024u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 32u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output size (in Bytes) */ +#define CPUSS_FLASHC_WORD_SIZE 16u +/* Flash row address width */ +#define CPUSS_FLASHC_ROW_ADDR_WIDTH 12u +/* Flash column address width */ +#define CPUSS_FLASHC_COL_ADDR_WIDTH 5u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_IRQ_NR 147u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_DPSLP_IRQ_NR 41u +/* Number of DeepSleep wakeup interrupt inputs to CM0+ (product configuration) */ +#define CPUSS_CM0_DPSLP_IRQ_NR 8u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 + for trace level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 16u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 1u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 8u +/* Width of the TPIU interface in bits ([1,32]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 256u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 16u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 16u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* AES cipher support (0 = no support, 1 = support */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support (0 = no support, 1 = support */ +#define CPUSS_CRYPTO_DES 1u +/* Pseudo random number generation support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA support included */ +#define CPUSS_CRYPTO_SHA 1u +/* SHA1 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA256 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA256 1u +/* SHA512 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA512 1u +/* Cyclic Redundancy Check support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_CRC 1u +/* Vector unit support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_VU 1u +/* True random number generation support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_TR 1u +/* String support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_STR 1u +/* AHB-Lite master interface support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_MASTER_IF 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 7u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* Number of channels in each DataWire controller (must be the same for now) */ +#define CPUSS_DW_CH_NR 16u +/* Number of profiling counters. Legal range [1, 32] */ +#define PROFILE_PRFL_CNT_NR 8u +/* Number of monitor event signals. Legal range [1, 128] */ +#define PROFILE_PRFL_MONITOR_NR 128u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* Number of UDB Interrupts */ +#define UDB_NUMINT 16u +/* Number of triggers */ +#define UDB_NUMTR 16u +/* Number of UDB array rows (must be multiple of 2) */ +#define UDB_NUMROW 2u +/* Number of UDB array columns */ +#define UDB_NUMCOL 6u +/* DSI on bottom (1) or on bottom and top (2) of UDB array */ +#define UDB_DSISIDES 2u +/* Number of UDBs = NUMROW * NUMCOL */ +#define UDB_NUMUDB 12u +/* Number of UDB pairs = NUMUDB / 2 */ +#define UDB_NUMUDBPAIR 6u +/* Number of DSIs = NUMCOL * DSISIDES */ +#define UDB_NUMDSI 12u +/* Number of quad clocks */ +#define UDB_NUMQCLK 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB0_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB0_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB0_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB0_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB0_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB0_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB0_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB0_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB0_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB0_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB0_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB0_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB0_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB0_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB0_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB0_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB0_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB0_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB0_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB0_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB0_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB0_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB0_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB1_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB1_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB1_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB1_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB1_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB1_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB1_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB1_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB1_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB1_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB1_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB1_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB1_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB1_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB1_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB1_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB1_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB1_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB1_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB1_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB1_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB1_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB1_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB2_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB2_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB2_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB2_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB2_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB2_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB2_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB2_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB2_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB2_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB2_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB2_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB2_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB2_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB2_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB2_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB2_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB2_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB2_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB2_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB2_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB2_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB2_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB3_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB3_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB3_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB3_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB3_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB3_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB3_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB3_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB3_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB3_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB3_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB3_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB3_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB3_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB3_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB3_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB3_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB3_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB3_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB3_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB3_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB3_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB3_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB4_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB4_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB4_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB4_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB4_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB4_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB4_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB4_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB4_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB4_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB4_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB4_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB4_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB4_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB4_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB4_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB4_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB4_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB4_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB4_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB4_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB4_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB4_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB5_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB5_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB5_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB5_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB5_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB5_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB5_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB5_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB5_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB5_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB5_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB5_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB5_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB5_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB5_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB5_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB5_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB5_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB5_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB5_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB5_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB5_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB5_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB6_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB6_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB6_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB6_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB6_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB6_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB6_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB6_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB6_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB6_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB6_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB6_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB6_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB6_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB6_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB6_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB6_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB6_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB6_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB6_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB6_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB6_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB6_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB7_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB7_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB7_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB7_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB7_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB7_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB7_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB7_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB7_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB7_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB7_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB7_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB7_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB7_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB7_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB7_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB7_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB7_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB7_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB7_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB7_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB7_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB7_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB8_DEEPSLEEP 1u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB8_EC 1u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB8_I2C_M 0u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB8_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB8_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB8_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB8_I2C_EC 1u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB8_I2C_M_S 0u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB8_I2C_S_EC 1u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB8_SPI_M 0u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB8_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB8_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB8_SPI_EC 1u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB8_SPI_S_EC 1u +/* UART support? ('0': no, '1': yes) */ +#define SCB8_UART 0u +/* SPI or UART (SPI | UART) */ +#define SCB8_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB8_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB8_CMD_RESP 1u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB8_EZ 1u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB8_EZ_CMD_RESP 1u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB8_I2C_S_EZ 1u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB8_SPI_S_EZ 1u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB8_I2C_FAST_PLUS 1u +/* Number of counters per IP (1..8) */ +#define TCPWM0_CNT_NR 8u +/* Counter width (in number of bits) */ +#define TCPWM0_CNT_CNT_WIDTH 32u +/* Number of counters per IP (1..8) */ +#define TCPWM1_CNT_NR 24u +/* Counter width (in number of bits) */ +#define TCPWM1_CNT_CNT_WIDTH 16u +/* Max number of LCD commons supported */ +#define LCD_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_PIN_NR 62u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 1u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 1u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 1u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 1u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u +#define PASS_CTBM_CTDAC_PRESENT 1u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]) */ +#define SMIF_MASTER_WIDTH 8u +/* Base address of the SMIF XIP memory region. This address must be a multiple of + the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This + address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP + memory region should NOT overlap with other memory regions. */ +#define SMIF_SMIF_XIP_ADDR 402653184u +/* Capacity of the SMIF XIP memory region. The more significant bits of this + parameter must be '1' and the lesser significant bits of this paramter must + be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are + {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, + 0xffe0:0000, ..., 0xe000:0000}. */ +#define SMIF_SMIF_XIP_MASK 4160749568u +/* Cryptography (AES) support ('0' = no support, '1' = support) */ +#define SMIF_CRYPTO 1u +/* Number of external devices supported ([1,4]) */ +#define SMIF_DEVICE_NR 4u +/* External device write support. This is a 4-bit field. Each external device has + a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */ +#define SMIF_DEVICE_WR_EN 15u +/* Set to 1 if IP will instantiate spares (0=None, 1=Max, 2=Min) */ +#define SMIF_SPARE_EN 1u +/* I2S capable? (0=No,1=Yes) */ +#define AUDIOSS_I2S 1u +/* PDM capable? (0=No,1=Yes) */ +#define AUDIOSS_PDM 1u + +#endif /* _PSOC63_CONFIG_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/psoc6ble_config.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/psoc6ble_config.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/TARGET_PSoC6_CY8C_CM0p/device/psoc6ble_config.h rename to targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/psoc6ble_config.h diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/system_psoc63.h b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/system_psoc63.h new file mode 100644 index 0000000000..b4d44c1618 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/TARGET_CY8C63XX/device/system_psoc63.h @@ -0,0 +1,494 @@ +/***************************************************************************//** +* \file system_psoc63.h +* \version 2.0 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC63_H_ +#define _SYSTEM_PSOC63_H_ + +/** +* \defgroup group_system_config System Configuration Files (Startup) +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - See \ref group_system_config_device_memory_definition for the: +* * \ref group_system_config_device_memory_dual_core_definition +* * \ref group_system_config_device_memory_single_core_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - Default interrupt handlers definition +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The physical flash and RAM memory is shared between the CPU cores. The flash +* and RAM allocation for each +* CPU is defined by the linker scripts. +* +* \subsubsection group_system_config_device_memory_dual_core_definition Dual-Core Devices +* By default, the flash and RAM memory is equally divided between two cores. +* This proportion can be changed by editing +* the linker configuration files. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for +* example, 'cy8c6x7_cm0plus.ld' and 'cy8c6x7_cm4_dual.ld'. +* Note: if the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* The flash and RAM sizes can be changed by editing the LENGTH value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* * \code rom (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 \endcode +* * \code ram_cm0p (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* * \code rom (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 \endcode +* * \code ram_cm4 (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00024000 \endcode +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for +* example, 'cy8c6x7_cm0plus.scat' and 'cy8c6x7_cm4_dual.scat'. +* Note: if the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* The flash and RAM sizes can be changed by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* * \code #define FLASH_START 0x10000000 \endcode +* * \code #define FLASH_SIZE 0x00080000 \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* * \code #define FLASH_START 0x10080000 \endcode +* * \code #define FLASH_SIZE 0x00080000 \endcode +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for +* example, 'cy8c6x7_cm0plus.icf' and 'cy8c6x7_cm4_dual.icf'. +* Note: if the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* The flash and RAM sizes can be changed by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* * \code define symbol __ICFEDIT_region_IROM_start__ = 0x10000000; \endcode +* * \code define symbol __ICFEDIT_region_IROM_end__ = 0x10080000; \endcode +* * \code define symbol __ICFEDIT_region_IRAM_CM0P_start__ = 0x08000000; \endcode +* * \code define symbol __ICFEDIT_region_IRAM_CM0P_end__ = 0x08024000; \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* * \code define symbol __ICFEDIT_region_IROM_start__ = 0x10080000; \endcode +* * \code define symbol __ICFEDIT_region_IROM_end__ = 0x10100000; \endcode +* * \code define symbol __ICFEDIT_region_IRAM_CM4_start__ = 0x08024000; \endcode +* * \code define symbol __ICFEDIT_region_IRAM_CM4_end__ = 0x08048000; \endcode +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* * \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* * \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsubsection group_system_config_device_memory_single_core_definition Single-Core Devices +* For single-core devices, 8 KB of flash and RAM are reserved for the pre-build +* Cortex-M0+ application that is loaded for the hidden Cortex-M0+. +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Cortex-M0+ pre-built application image handles setup of the CM0+ core and +* starts the Cortex-M4 core. +* +* CM0+ NVIC IRQn channels 26-31 are reserved for system use. Other IRQn channels +* are available to the user application. The pre-built application configures: +* * IRQn 26-27 for the IPC driver +* * IRQn 28-30 for the Crypto driver +* * IRQn 31 for system communication +* +* The Cortex-M0+ application image performs the following tasks: +* * Enables global interrupts on the Cortex-M0+ core. +* * Starts the crypto server. See [Cryptography (Crypto)](\ref group_crypto) for details. +* * Enables the Cortex-M4 core by calling \ref Cy_SysEnableCM4(). +* * Requests Deep Sleep mode entry with wakeup on interrupt in the infinite loop. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files: +* 'startup_xx_yy.S', where 'xx' is the device family, and 'yy' is the target CPU; +* for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s. +* Change the heap and stack sizes by modifying the following lines:\n +* * \code .equ Stack_Size, 0x00001000 \endcode +* * \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* * \code -D __STACK_SIZE=0x000000400 \endcode +* * \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files: +* 'startup_xx_yy.s', where 'xx' is the device family, and 'yy' is the target +* CPU; for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s. +* Change the heap and stack sizes by modifying the following lines:\n +* * \code Stack_Size EQU 0x00001000 \endcode +* * \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* * \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* * \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6x7_cm0plus.icf and cy8c6x7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* * \code Stack_Size EQU 0x00001000 \endcode +* * \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* * \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* * \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* - \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cypdlelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cypdlelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6x7_cm0plus.ld and cy8c6x7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files: 'startup_xx_yy.S', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, startup_psoc63_cm0plus.S and +* startup_psoc63_cm4.S. The code in these files copies the vector table from +* Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6x7_cm0plus.scat and +* cy8c6x7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files: 'startup_xx_yy.s', where 'xx' is the device family, and 'yy' is the +* target CPU; for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s. +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6x7_cm0plus.icf and cy8c6x7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files: 'startup_xx_yy.s', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, startup_psoc63_cm0plus.s and +* startup_psoc63_cm4.s. The code in these files copies the vector table +* from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* The drivers violates the following MISRA-C:2004 rules: +* +* +* +* +* +* +* +* +*
    MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
    +* +* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +*
    VersionChangesReason for Change
    1.0Initial version
    +* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#define CY_CORTEX_M4_APPL_ADDR (0x10080000UL) /* <<< 512 KB reserved for the Cortex-M0+ application */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0Eu) & 0x3FFFu) << 18u)) +#endif + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0Fu) & 0x3FFFu) << 18u)) +#endif + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); +extern uint32_t Cy_SaveIRQ(void); +extern void Cy_RestoreIRQ(uint32_t saved); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3u) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0u) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2u) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1u) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC63_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto.h new file mode 100644 index 0000000000..59f8f484fa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto.h @@ -0,0 +1,1678 @@ +/***************************************************************************//** +* \file cy_crypto.h +* \version 2.0 +* +* \brief +* This file provides the public interface for the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_crypto Cryptography (Crypto) +* \{ +* The Crypto driver provides a public API to perform cryptographic and hash +* operations, as well as generate both true and pseudo random numbers +* (TRNG, PRNG). It uses a hardware IP block to accelerate operations. The driver +* supports these standards: DES, TDES, AES (128, 192, 256 bits), CMAC-AES, SHA, +* HMAC, PRNG, TRNG, CRC, and RSA. +* +* This document contains the following topics: +* - \ref group_crypto_overview +* - \ref group_crypto_configuration_considerations +* - \ref group_crypto_server_init +* - \ref group_crypto_client_init +* - \ref group_crypto_irq_implements +* - \ref group_crypto_rsa_considerations +* - \ref group_crypto_definitions +* - \ref group_crypto_more_information +* +* \section group_crypto_overview Overview +* The Crypto driver uses a client-server architecture. +* +* Firmware initializes and starts the Crypto server. The server runs only on the +* CM0+ core, and works with the Crypto hardware. The Crypto server is implemented +* as a secure block. It performs all cryptographic operations for the client. +* Access to the server is through the Inter Process Communication (IPC) driver. +* Direct access is not allowed. +* +* The Crypto client can run on either core. Firmware initializes and starts the +* client. The firmware then provides the configuration data required for the +* desired cryptographic technique, and requests that the server run the +* cryptographic operation. +* +* \image html crypto_architecture.png +* +* Firmware sets up a cryptographic operation using configuration structures, or +* by passing in required data as parameters in function calls. +* +* Most Crypto functions require one or more contexts. A context is a data +* structure that the driver uses for its operations. Firmware declares the +* context (allocates memory) but does not write or read the values in the +* context. In effect the context is a scratch pad you provide to the driver. +* The driver uses the context to store and manipulate data during cryptographic +* operations. +* +* There is a common context shared by all cryptographic methods. Several methods +* require an additional context unique to the particular cryptographic technique. +* The Crypto driver header files declare all the required structures for both +* configuration and context. +* +* IPC communication between the client and server is completely transparent. +* Default PDL source files configure the IPC channel. Using IPC for communication +* provides a simple synchronization mechanism to handle concurrent requests from +* different cores. +* +* The Crypto driver (both client and server) is provided as compiled binary +* libraries, not as source code. Header files define the API and required data +* structures. +* +* The Crypto driver uses: +* - One IPC channel for data exchange between client and server +* - Three interrupts: an IPC notify interrupt, an IPC release interrupt, +* and an interrupt for error handling +* +* The \ref group_crypto_definitions section provides more information on cryptographic terms of +* art, and the particular supported encryption standards. +* +* \section group_crypto_configuration_considerations Configuration Considerations +* +* IPC communication for the Crypto driver is handled transparently. The +* cy_crytpo_config files set up the IPC channel, and configure the required +* notify, release, and error interrupts. +* +* Initialization routines \ref Cy_Crypto_Server_Start (server) and +* \ref Cy_Crypto_Init (client) use separate instances of the same +* cy_stc_crypto_config_t configuration structure. Some fields should be the same, +* and some are set specifically by either the server or client. See the +* cy_crypto_config files for the default implementation. The table lists each +* field in the config structure, which initialization routine sets the value, +* and the default MACRO that defines the value. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    FieldWhichMACRO / FunctionNotes
    \link cy_stc_crypto_config_t::ipcChannel ipcChannel\endlinkServer and ClientCY_IPC_CHAN_CRYPTOIPC Channel, same for both
    \link cy_stc_crypto_config_t::acquireNotifierChannel acquireNotifierChannel\endlinkServer and ClientCY_CRYPTO_IPC_INTR_NOTIFY_NUMNotify interrupt number, same for both
    \link cy_stc_crypto_config_t::releaseNotifierChannel releaseNotifierChannel\endlinkServer and ClientCY_CRYPTO_IPC_INTR_RELEASE_NUMRelease interrupt number, same for both
    \link cy_stc_crypto_config_t::userCompleteCallback userCompleteCallback\endlinkClientUser-defined callback for the Release interrupt handler; can be NULLSee Implementing Crypto Interrupts
    \link cy_stc_crypto_config_t::releaseNotifierConfig releaseNotifierConfig \endlinkClientSource: CY_CRYPTO_IPC_INTR_RELEASE_NUM; Priority: \ref CY_CRYPTO_RELEASE_INTR_PRconfiguration for the interrupt
    \link cy_stc_crypto_config_t::userGetDataHandler userGetDataHandler\endlinkServerUser-defined function to override default interrupt handler; NULL = use defaultISR for the Notify interrupt
    \link cy_stc_crypto_config_t::acquireNotifierConfig acquireNotifierConfig\endlinkServerSource: \ref CY_CRYPTO_CM0_NOTIFY_INTR_NR; Priority: \ref CY_CRYPTO_NOTIFY_INTR_PRconfiguration for the interrupt
    \link cy_stc_crypto_config_t::userErrorHandler userErrorHandler\endlinkServerUser-defined function to override default interrupt handler; NULL = use defaultISR for a server error
    \link cy_stc_crypto_config_t::cryptoErrorIntrConfig cryptoErrorIntrConfig\endlinkServerSource: \ref CY_CRYPTO_CM0_ERROR_INTR_NR; Priority: \ref CY_CRYPTO_ERROR_INTR_PRconfiguration for the interrupt
    +* +* On the CM0+, the error, release, and notify interrupts are assigned to +* NVIC IRQn 28-30 respectively. Do not modify these values. +* See System Interrupt (SysInt) for background on CM0+ interrupts. +* +* \section group_crypto_server_init Server Initialization +* +* Use \ref Cy_Crypto_Server_Start. This call must be made from the CM0+ core only. +* Provide the configuration parameters (cy_stc_crypto_config_t) and a pointer +* to the server context (cy_stc_crypto_server_context_t). +* Do not fill in the values for the context structure. +* +* Because the two cores operate asynchronously, ensure that server +* initialization is complete before initializing the client. +* There are several ways to do this: +* +* - Use \ref Cy_Crypto_Sync as a blocking call, before initializing the client. +* - Enable the CM4 core (\ref Cy_SysEnableCM4) after +* \ref Cy_Crypto_Server_Start executes successfully. +* - Check the return status from calls to \ref Cy_Crypto_Init or +* \ref Cy_Crypto_Enable to ensure \ref CY_CRYPTO_SUCCESS. +* +* All crypto operations are asynchronous. To ensure that any crypto operation +* is complete and the result is valid, use \ref Cy_Crypto_Sync. +* Use the \ref CY_CRYPTO_SYNC_NON_BLOCKING parameter to check status. +* Use \ref CY_CRYPTO_SYNC_BLOCKING to wait for the operation to complete. +* +* \section group_crypto_client_init Client initialization +* +* Use \ref Cy_Crypto_Init to initialize the Crypto client with the configuration +* parameters (cy_stc_crypto_config_t) and a pointer to the context +* (cy_stc_crypto_context_t). Do not fill in the values for the context structure. +* +* Then call \ref Cy_Crypto_Enable to enable the Crypto hardware IP block. +* After this, the Crypto driver is ready to execute crypto functions. +* These calls must be made on the client side. +* Firmware can implement the client on either core. +* +* Some encryption techniques require additional initialization specific to the +* technique. If there is an Init function, you must call it before using any +* other function for that technique, and reinitialize after you use a different +* encryption technique. +* +* For example, use \ref Cy_Crypto_Aes_Init to configure an AES encryption +* operation with the encryption key, and key length. +* Provide pointers to two context structures. You can then call AES Run functions. +* If later on you use DES, you must re-initialize AES encryption before using +* it again. +* +* See the documentation for details about each Cy_Crypto_XXX_Init function. +* +* \section group_crypto_irq_implements Implementing Crypto Interrupts +* +* The Crypto driver uses three interrupts: +* - A notify interrupt when data is ready for a cryptographic operation +* - A release interrupt when a cryptographic operation is complete +* - An error interrupt if the server encounters a hardware error +* +* You can modify default behavior for each interrupt. +* +* Notify Interrupt: the Crypto server has a default ISR to handle this +* interrupt, \ref Cy_Crypto_Server_GetDataHandler. The default ISR clears the +* interrupt, retrieves the data from the IPC channel, and dispatches control to +* the desired cryptographic operation. +* +* To use the default handler, set the \link +* cy_stc_crypto_config_t::userGetDataHandler userGetDataHandler \endlink field +* of the cy_stc_crypto_config_t structure to NULL. To override, populate this +* field with your ISR. Then call \ref Cy_Crypto_Server_Start. +* Your ISR can perform additional tasks required by your application logic, +* but must also call \ref Cy_Crypto_Server_GetDataHandler to dispatch the data +* to the correct cryptographic operation. +* +* Release Interrupt: The Crypto driver includes a handler for this +* interrupt. The interrupt handler clears the interrupt and calls a user-provided +* callback routine. You cannot override this interrupt handler. +* By default the interrupt is disabled. +* +* To use default behavior (interrupt disabled), set the \link +* cy_stc_crypto_config_t::userCompleteCallback userCompleteCallback \endlink +* field of the cy_stc_crypto_config_t structure to NULL. +* To enable the interrupt, populate this field with your callback function. +* Then call \ref Cy_Crypto_Init. If the callback function is not NULL, the Init +* function enables the interrupt, and default behavior calls your routine. +* +* When performing cryptographic operations, firmware must ensure the operation +* is complete before acting on the results. If the release interrupt is disabled, +* typically calls to \ref Cy_Crypto_Sync should be blocking. If the interrupt is +* enabled, your callback function is called when the operation is complete. +* This lets you avoid blocking calls to \ref Cy_Crypto_Sync. +* +* Error Interrupt: The Crypto server has a default ISR to handle this +* interrupt. It clears the interrupt and sets an internal flag that an error +* has occurred. +* +* To use the default handler, set the userErrorHandler field of the +* cy_stc_crypto_config_t structure to NULL. To override, populate this field +* with your ISR. Then call \ref Cy_Crypto_Server_Start. +* +* Your ISR must call \ref Cy_Crypto_Server_ErrorHandler, and can perform any +* additional tasks required by your application logic. +* +* \section group_crypto_rsa_considerations RSA Usage Considerations +* +* General RSA encryption and decryption is supported. +* \ref Cy_Crypto_Rsa_Proc encrypts or decrypts data based on the parameters +* passed to the function. If you pass in plain text and a public key, the output +* is encrypted (cipher text). If you pass in cipher text and a private key, the +* output is decrypted (plain text). +* +* One parameter for this function call is a structure that defines the key: +* cy_stc_crypto_rsa_pub_key_t. The four modulus and exponent fields are +* mandatory, and represent the data for either the public or private key as +* appropriate. +* +* The remaining fields represent three pre-calculated coefficients that can +* reduce execution time by up to 5x. The fields are: coefficient for Barrett +* reduction, binary inverse of the modulus, and the result of +* (2^moduloLength mod modulo). These fields are optional, and can be set to NULL. +* +* Calculate these coefficients with \ref Cy_Crypto_Rsa_CalcCoefs. +* Pass in the address of the key structure with the modulus and exponent values +* for the key. The function returns the coefficients for the key in the key +* structure, replacing any previous values. +* +* The RSA functionality also implements functions to decrypt a signature using +* a public key. This signature must follow the RSASSA-PKCS-v1_5 standard. +* The signature must contain a SHA digest (hash). +* MD2, MD4, and MD5 message digests are not supported. +* +* An encrypted signature is stored as big-endian data. It must be inverted for +* RSA processing. To use the provided signature decryption, firmware must +* -# Calculate the SHA digest of the data to be verified with +* \ref Cy_Crypto_Sha_Run. +* -# Ensure that the RSA signature is in little-endian format. +* Use \ref Cy_Crypto_Rsa_InvertEndianness. +* -# Decrypt the RSA signature with a public key, by calling +* \ref Cy_Crypto_Rsa_Proc. +* -# Invert the byte order of the output, to return to big-endian format. +* Use \ref Cy_Crypto_Rsa_InvertEndianness. +* -# Call \ref Cy_Crypto_Rsa_Verify (which requires data in big-endian format). +* +* \section group_crypto_definitions Definitions +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    TermDefinition
    PlaintextAn unencrypted message
    CiphertextAn encrypted message
    Block CipherAn encryption function for fixed-size blocks of data. +* This function takes a fixed-size key and a block of plaintext data from +* the message and encrypts it to generate ciphertext. Block ciphers are +* reversible. The function performed on a block of encrypted data will +* decrypt it.
    Block Cipher ModeA mode of encrypting a message using block ciphers for messages of +* arbitrary length. The message is padded so that its length is an integer +* multiple of the block size. ECB (Electronic Code Book), CBC (Cipher Block +* Chaining), and CFB (Cipher Feedback) are all modes of using block ciphers +* to create an encrypted message of arbitrary length.
    Data Encryption Standard (DES)Is a symmetric-key algorithm for the encryption of electronic data. +* It uses a 56-bit key and a 64-bit message block size.
    Triple DES (3DES or TDES)Is a symmetric-key block cipher, which applies the Data Encryption +* Standard (DES) cipher algorithm three times to each data block. +* It uses three 56-bit keys. The block size is 64-bits.
    Advanced Encryption Standard (AES)The standard specifies the Rijndael algorithm, a symmetric block +* cipher that can process data blocks of 128 bits, using cipher keys with +* lengths of 128, 192, and 256 bits. Rijndael was designed to handle +* additional block sizes and key lengths, however they are not adopted in +* this standard. AES is also used for message authentication.
    Cipher-based Message Authentication Code (CMAC)This is a block cipher-based message authentication code algorithm. +* It computes the MAC value using the AES block cipher algorithm.
    Secure Hash Algorithm (SHA)Is a cryptographic hash function. +* This function takes a message of the arbitrary length and reduces it to a +* fixed-length residue or message digest after performing a series of +* mathematically defined operations that practically guarantee that any +* change in the message will change the hash value. It is used for message +* authentication by transmitting a message with a hash value appended to it +* and recalculating the message hash value using the same algorithm at the +* recipient's end. If the hashes differ, then the message is corrupted.
    Message Authentication Code (MAC)MACs are used to verify that a received message has not been altered. +* This is done by first computing a MAC value at the sender's end and +* appending it to the transmitted message. When the message is received, +* the MAC is computed again and checked against the MAC value transmitted +* with the message. If they do not match, the message has been altered. +* Either a Hash algorithm (such as SHA) or a block cipher (such as AES) can +* be used to produce the MAC value. Keyed MAC schemes use a Secret Key +* along with the message, thus the Key value must be known to be able to +* compute the MAC value.
    Hash Message Authentication Code (HMAC)Is a specific type of message authentication code (MAC) involving a +* cryptographic hash function and a secret cryptographic key. +* It computes the MAC value using a Hash algorithm.
    Pseudo Random Number Generator (PRNG)Is a Linear Feedback Shift Registers-based algorithm for generating a +* sequence of numbers starting from a non-zero seed.
    True Random Number Generator (TRNG)A block that generates a number that is statistically random and based +* on some physical random variation. The number cannot be duplicated by +* running the process again.
    Symmetric Key CryptographyUses a common, known key to encrypt and decrypt messages (a shared +* secret between sender and receiver). An efficient method used for +* encrypting and decrypting messages after the authenticity of the other +* party has been established. DES (now obsolete), 3DES, and AES (currently +* used) are well-known symmetric cryptography methods.
    Asymmetric Key CryptographyAlso referred to as Public Key encryption. Someone who wishes to +* receive a message, publishes a very large public key (up to 4096 bits +* currently), which is one of two prime factors of a very large number. The +* other prime factor is the private key of the recipient and a secret. +* Someone wishing to send a message to the publisher of the public key +* encrypts the message with the public key. This message can now be +* decrypted only with the private key (the other prime factor held secret by +* the recipient). The message is now sent over any channel to the recipient +* who can decrypt it with the private, secret, key. The same process is used +* to send messages to the sender of the original message. The asymmetric +* cryptography relies on the mathematical impracticality (usually related to +* the processing power available at any given time) of factoring the keys. +* Common, computationally intensive, asymmetric algorithms are RSA and ECC. +* The public key is described by the pair (n, e) where n is a product of two +* randomly chosen primes p and q. The exponent e is a random integer +* 1 < e < Q where Q = (p-1) (q-1). The private key d is uniquely defined +* by the integer 1 < d < Q such that ed congruent to 1 (mod Q ).
    +* +* \section group_crypto_more_information More Information +* +* RSASSA-PKCS1-v1_5 described here, page 31: +* http://www.emc.com/collateral/white-papers/h11300-pkcs-1v2-2-rsa-cryptography-standard-wp.pdf* +* +* See the Cryptographic Function Block chapter of the Technical Reference Manual. +* +* \section group_crypto_MISRA MISRA-C Compliance +* This driver does not contains any driver-specific MISRA violations. +* +* \section group_crypto_changelog Changelog +* +* +* +* +* +* +* +*
    VersionChangesReason for Change
    1.0Initial version
    +* +* +* \defgroup group_crypto_common Configuration +* \{ +* \defgroup group_crypto_config_macros Macros +* \defgroup group_crypto_config_structure Structure +* \} +* +* \defgroup group_crypto_client Crypto Client +* \{ +* \defgroup group_crypto_macros Macros +* \defgroup group_crypto_enums Enumerated Types +* \defgroup group_crypto_cli_data_structures Data Structures +* \defgroup group_crypto_cli_functions Functions +* \} +* +* \defgroup group_crypto_server Crypto Server +* \{ +* \defgroup group_crypto_srv_data_structures Data Structures +* \defgroup group_crypto_srv_functions Functions +* \} +*/ + +#if !defined(CY_CRYPTO_H) +#define CY_CRYPTO_H + + +#include +#include +#include "cy_device_headers.h" +#include "crypto/cy_crypto_common.h" + +#if (CPUSS_CRYPTO_PRESENT == 1) + + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** \cond INTERNAL */ + +cy_en_crypto_status_t Cy_Crypto_GetLibraryInfo(cy_en_crypto_lib_info_t *cryptoInfo); + +/** \endcond */ + +/** +* \addtogroup group_crypto_cli_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_Crypto_Init +****************************************************************************//** +* +* This function initializes the Crypto context buffer and +* configures the Crypto driver. Must be called at first. +* +* To start working with Crypto methods after Crypto_Init(), +* call Crypto_Enable() to turn-on the Crypto Hardware. +* +* \param config +* The pointer to the Crypto configuration structure. +* Could be used with default values from cy_crypto_config.h +* +* \param context +* The pointer to the \ref cy_stc_crypto_context_t instance of structure +* that stores the Crypto driver common context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Init(cy_stc_crypto_config_t const *config, cy_stc_crypto_context_t *context); + +/******************************************************************************* +* Function Name: Cy_Crypto_DeInit +****************************************************************************//** +* +* This function de-initializes the Crypto driver. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_DeInit(void); + +/******************************************************************************* +* Function Name: Cy_Crypto_Enable +****************************************************************************//** +* +* This function enables (turns on) the Crypto hardware. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Enable(void); + +/******************************************************************************* +* Function Name: Cy_Crypto_Disable +****************************************************************************//** +* +* This function disables (turns off) the Crypto hardware. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Disable(void); + +/******************************************************************************* +* Function Name: Cy_Crypto_Sync +****************************************************************************//** +* +* This function waits or just checks (depending on the parameter) +* for the Crypto operation to complete. +* +* \param isBlocking +* Set whether Crypto_Sync is blocking: +* True - is blocking. +* False - is not blocking. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Sync(bool isBlocking); + +/******************************************************************************* +* Function Name: Cy_Crypto_GetErrorStatus +****************************************************************************//** +* +* This function returns a cause of a Crypto hardware error. +* It is independent of the Crypto previous state. +* +* \param hwErrorCause +* \ref cy_stc_crypto_hw_error_t. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_GetErrorStatus(cy_stc_crypto_hw_error_t *hwErrorCause); + +#if (CPUSS_CRYPTO_PR == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Prng_Init +****************************************************************************//** +* +* This function initializes parameters of the PRNG. +* +* Call to initialize this encryption technique before using any associated +* functions. You must initialize this technique again after using any other +* encryption technique. +* Invoking this function resets the pseudo random sequence. +* +* \param lfsr32InitState +* A non-zero seed value for the first LFSR. + +* \param lfsr31InitState +* A non-zero seed value for the second LFSR. + +* \param lfsr29InitState +* A non-zero seed value for the third LFSR. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_prng_t structure that stores +* the Crypto function context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Prng_Init(uint32_t lfsr32InitState, + uint32_t lfsr31InitState, + uint32_t lfsr29InitState, + cy_stc_crypto_context_prng_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Prng_Generate +****************************************************************************//** +* +* This function generates 32-bit the Pseudo Random Number. +* It depends on Cy_Crypto_Prng_Init that should be called before. +* +* \param max +* The maximum value of a random number. +* +* \param randomNum +* The pointer to a variable to store the generated pseudo random number. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_prng_t structure that stores +* the Crypto function context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Prng_Generate(uint32_t max, + uint32_t *randomNum, + cy_stc_crypto_context_prng_t *cfContext); +#endif /* #if (CPUSS_CRYPTO_PR == 1) */ + +#if (CPUSS_CRYPTO_AES == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Init +****************************************************************************//** +* +* This function initializes the AES operation by setting key and key length. +* +* Call to initialize this encryption technique before using any associated +* functions. You must initialize this technique again after using any other +* encryption technique. +* +* \param key +* The pointer to the encryption/decryption key. +* +* \param keyLength +* \ref cy_en_crypto_aes_key_length_t +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure that stores all internal variables +* the Crypto driver requires. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Init(uint32_t *key, + cy_en_crypto_aes_key_length_t keyLength, + cy_stc_crypto_context_aes_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Ecb_Run +****************************************************************************//** +* +* This function performs AES operation on one block. +* The key must be set before by invoking Cy_Crypto_Aes_Init(). +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT (\ref cy_en_crypto_dir_mode_t). +* +* \param srcBlock +* The pointer to a source block. +* +* \param dstBlock +* The pointer to a destination cipher block. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_aes_t instance of structure +* that stores all AES internal variables. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Ecb_Run(cy_en_crypto_dir_mode_t dirMode, + uint32_t *dstBlock, + uint32_t *srcBlock, + cy_stc_crypto_context_aes_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Cbc_Run +****************************************************************************//** +* +* This function performs AES operation on a plain text with Cipher Block Chaining (CBC). +* The key must be set before by invoking Cy_Crypto_Aes_Init(). +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT (\ref cy_en_crypto_dir_mode_t) +* +* \param srcSize +* The size of the source plain text. +* +* \param ivPtr +* The pointer to the initial vector. +* +* \param dst +* The pointer to a destination cipher text. +* +* \param src +* The pointer to a source plain text. Must be 4-Byte aligned. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure that stores all internal variables +* the Crypto driver requires. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Cbc_Run(cy_en_crypto_dir_mode_t dirMode, + uint32_t srcSize, + uint32_t *ivPtr, + uint32_t *dst, + uint32_t *src, + cy_stc_crypto_context_aes_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Cfb_Run +****************************************************************************//** +* +* This function performs AES operation on a plain text with Cipher Feedback mode (CFB). +* The key must be set before by invoking Cy_Crypto_Aes_Init(). +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT (\ref cy_en_crypto_dir_mode_t) +* +* \param srcSize +* The size of the source plain text. +* +* \param ivPtr +* The pointer to the initial vector. +* +* \param dst +* The pointer to a destination cipher text. +* +* \param src +* The pointer to a source plain text. Must be 4-Byte aligned. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure that stores all internal variables +* the Crypto driver requires. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Cfb_Run(cy_en_crypto_dir_mode_t dirMode, + uint32_t srcSize, + uint32_t *ivPtr, + uint32_t *dst, + uint32_t *src, + cy_stc_crypto_context_aes_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Ctr_Run +****************************************************************************//** +* +* This function performs AES operation on a plain text with Cipher Block Counter mode (CTR). +* NOTE: preparation of the unique nonceCounter for each block is +* the user's responsibility. This function is dependent on +* the key being set before invoking \ref Cy_Crypto_Aes_Init(). +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT (\ref cy_en_crypto_dir_mode_t) +* +* \param srcSize +* The size of a source plain text. +* +* \param srcOffset +* The size of an offset within the current block stream for resuming within the current cipher stream. +* +* \param nonceCounter +* The 128-bit nonce and counter. +* +* \param streamBlock +* The saved stream-block for resuming. Is over-written by the function. +* +* \param dst +* The pointer to a destination cipher text. +* +* \param src +* The pointer to a source plain text. Must be 4-Byte aligned. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure that stores all internal variables +* the Crypto driver requires. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Ctr_Run(cy_en_crypto_dir_mode_t dirMode, + uint32_t srcSize, + uint32_t *srcOffset, + uint32_t nonceCounter[CY_CRYPTO_AES_BLOCK_SIZE / 8u], + uint32_t streamBlock[CY_CRYPTO_AES_BLOCK_SIZE / 8u], + uint32_t *dst, + uint32_t *src, + cy_stc_crypto_context_aes_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Aes_Cmac_Run +****************************************************************************//** +* +* This function performs the cipher-block chaining-message authentication-code. +* +* There is no Init function. Provide the required parameters and the pointer to +* the context structure when making this function call. +* +* \param src +* The pointer to a source plain text. Must be 4-Byte aligned. +* +* \param srcSize +* The size of a source plain text. +* +* \param key +* The pointer to the encryption key. +* +* \param keyLength +* \ref cy_en_crypto_aes_key_length_t +* +* \param cmacPtr +* The pointer to the calculated CMAC. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_aes_t structure that stores all +* internal variables the Crypto driver requires. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Aes_Cmac_Run(uint32_t *src, + uint32_t srcSize, + uint32_t *key, + cy_en_crypto_aes_key_length_t keyLength, + uint32_t *cmacPtr, + cy_stc_crypto_context_aes_t *cfContext); +#endif /* #if (CPUSS_CRYPTO_AES == 1) */ + +#if (CPUSS_CRYPTO_SHA == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Sha_Run +****************************************************************************//** +* +* This function performs the SHA Hash function. +* There is no Init function. Provide the required parameters and the pointer +* to the context structure when making this function call. +* It is independent of the previous Crypto state because it already contains +* preparation, calculation, and finalization steps. +* +* \param mode +* \ref cy_en_crypto_sha_mode_t +* +* \param message +* The pointer to a message whose hash value is being computed. +* +* \param messageSize +* The size of a message. +* +* \param digest +* The pointer to the hash digest. +* +* \param cfContext +* the pointer to the \ref cy_stc_crypto_context_sha_t structure that stores all +* internal variables for Crypto driver. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Sha_Run(uint32_t *message, + uint32_t messageSize, + uint32_t *digest, + cy_en_crypto_sha_mode_t mode, + cy_stc_crypto_context_sha_t *cfContext); +#endif /* #if (CPUSS_CRYPTO_SHA == 1) */ + +#if (CPUSS_CRYPTO_SHA == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Hmac_Run +****************************************************************************//** +* +* This function performs HMAC calculation. +* There is no Init function. Provide the required parameters and the pointer +* to the context structure when making this function call. +* It is independent of the previous Crypto state because it already contains +* preparation, calculation, and finalization steps. +* +* \param hmac +* The pointer to the calculated HMAC. +* +* \param message +* The pointer to a message whose hash value is being computed. +* +* \param messageSize +* The size of a message. +* +* \param key +* The pointer to the key. +* +* \param keyLength +* The length of the key. +* +* \param mode +* \ref cy_en_crypto_sha_mode_t +* +* \param cfContext +* the pointer to the \ref cy_stc_crypto_context_sha_t structure that stores all internal variables +* for the Crypto driver. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Hmac_Run(uint32_t *hmac, + uint32_t *message, + uint32_t messageSize, + uint32_t *key, + uint32_t keyLength, + cy_en_crypto_sha_mode_t mode, + cy_stc_crypto_context_sha_t *cfContext); +#endif /* #if (CPUSS_CRYPTO_SHA == 1) */ + +#if (CPUSS_CRYPTO_STR == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Str_MemCpy +****************************************************************************//** +* +* This function copy memory block. It operates data in the user SRAM and doesn't +* use Crypto internal SRAM. +* +* \note Memory blocks should not overlap. +* +* There is no alignment restriction. +* This function is independent of the previous Crypto state. +* +* \param dst +* The pointer to the destination of MemCpy. +* +* \param src +* The pointer to the source of MemCpy. +* +* \param size +* The size in bytes of the copy operation. Maximum size is 65535 Bytes. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_str_t structure that stores all internal variables +* for the Crypto driver. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Str_MemCpy(void *dst, + void const *src, + uint16_t size, + cy_stc_crypto_context_str_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Str_MemSet +****************************************************************************//** +* +* This function sets the memory block. It operates data in the user SRAM and +* doesn't use Crypto internal SRAM. +* +* There is no alignment restriction. +* This function is independent from the previous Crypto state. +* +* \param dst +* The pointer to the destination of MemSet. +* +* \param data +* The value to be set. +* +* \param size +* The size in bytes of the set operation. Maximum size is 65535 Bytes. +* +* \param cfContext +* the pointer to the \ref cy_stc_crypto_context_str_t structure that stores all internal variables +* for the Crypto driver. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Str_MemSet(void *dst, + uint8_t data, + uint16_t size, + cy_stc_crypto_context_str_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Str_MemCmp +****************************************************************************//** +* +* This function compares memory blocks. It operates data in the user SRAM and +* doesn't use Crypto internal SRAM. +* +* There is no alignment restriction. +* This function is independent from the previous Crypto state. +* +* \param src0 +* The pointer to the first source of MemCmp. +* +* \param src1 +* The pointer to the second source of MemCmp. +* +* \param size +* The size in bytes of the compare operation. Maximum size is 65535 Bytes. +* +* \param resultPtr +* The pointer to the result of compare: +* - 0 - if Source 1 equal Source 2 +* - 1 - if Source 1 not equal Source 2 +* +* \param cfContext +* the pointer to the \ref cy_stc_crypto_context_str_t structure that stores all internal variables +* for the Crypto driver. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Str_MemCmp(void const *src0, + void const *src1, + uint16_t size, + uint32_t *resultPtr, + cy_stc_crypto_context_str_t *cfContext); + +/******************************************************************************* +* Function Name: Crypto_Str_MemXor +****************************************************************************//** +* +* This function calculate XOR of two memory blocks. It operates data in the user +* SRAM and doesn't use Crypto internal SRAM. +* +* \note Memory structures should not overlap. +* +* There is no alignment restriction. +* This function is independent from the previous Crypto state. +* +* \param src0 +* The pointer to the first source of MemXor. + +* \param src1 +* The pointer to the second source of MemXor. + +* \param dst +* The pointer to the destination of MemXor. +* +* \param size +* The size in bytes of the compare operation. Maximum size is 65535 Bytes. +* +* \param cfContext +* the pointer to the \ref cy_stc_crypto_context_str_t structure that stores all internal variables +* for the Crypto driver. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Str_MemXor(void const *src0, + void const *src1, + void *dst, + uint16_t size, + cy_stc_crypto_context_str_t *cfContext); +#endif /* #if (CPUSS_CRYPTO_STR == 1) */ + +#if (CPUSS_CRYPTO_CRC == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Crc_Init +****************************************************************************//** +* +* This function performs CRC initialization. +* +* Call to initialize this encryption technique before using any associated +* functions. You must initialize this technique again after using any other +* encryption technique. +* +* One peculiar of the CRC hardware block is that for some polynomials +* calculated, CRC is MSB aligned and others are LSB aligned. +* Below is the table with known polynomials and their +* calculated CRCs from the string "123456789". +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    CRC modes and parameters
    NameWidthPolyInitData RevData XORRem RevRem XORExpected CRCOutput of the CRC block
    CRC-3 / ROHC30x30x71010x00x60x00000006
    CRC-4 / ITU40x30x01010x00x70x00000007
    CRC-5 / EPC50x90x90000x00x00x00000000
    CRC-5 / ITU50x150x01010x00x70x00000007
    CRC-5 / USB50x50x1F1010x1F0x190x00000019
    CRC-6 / CDMA2000-A60x270x3F0000x00xD0xD0000000
    CRC-6 / CDMA2000-B60x70x3F0000x00x3B0x3B000000
    CRC-6 / DARC60x190x01010x00x260x00000026
    CRC-6 / ITU60x30x01010x00x60x00000006
    CRC-770x90x00000x00x750x75000000
    CRC-7 / ROHC70x4F0x7F1010x00x530x00000053
    CRC-880x70x00000x00xF40xF4000000
    CRC-8 / CDMA200080x9B0xFF0000x00xDA0xDA000000
    CRC-8 / DARC80x390x01010x00x150x00000015
    CRC-8 / DVB-S280xD50x00000x00xBC0xBC000000
    CRC-8 / EBU80x1D0xFF1010x00x970x00000097
    CRC-8 / I-CODE80x1D0xFD0000x00x7E0x7E000000
    CRC-8 / ITU80x70x00000x550xA10xA1000000
    CRC-8 / MAXIM80x310x01010x00xA10x000000A1
    CRC-8 / ROHC80x70xFF1010x00xD00x000000D0
    CRC-8 / WCDMA80x9B0x01010x00x250x00000025
    CRC-10100x2330x00000x00x1990x19900000
    CRC-10 / CDMA2000100x3D90x3FF0000x00x2330x23300000
    CRC-11110x3850x1A0000x00x5A30x5A300000
    CRC-12 / 3GPP120x80F0x00010x00xDAF0x00000DAF
    CRC-12 / CDMA2000120xF130xFFF0000x00xD4D0xD4D00000
    CRC-12 / DECT120x80F0x00000x00xF5B0xF5B00000
    CRC-13 / BBC130x1CF50x00000x00x4FA0x4FA00000
    CRC-14 / DARC140x8050x01010x00x82D0x0000082D
    CRC-15150x45990x00000x00x59E0x59E00000
    CRC-15 / MPT1327150x68150x00000x10x25660x25660000
    CRC-24240x0864CFB0x00B704CE0000x00x21CF020x21CF0200
    CRC-24 / FLEXRAY-A240x05D6DCB0x00FEDCBA0000x00x7979BD0x7979BD00
    CRC-24 / FLEXRAY-B240x05D6DCB0x00ABCDEF0000x00x1F23B80x1F23B800
    CRC-31 / PHILIPS310x4C11DB70x7FFFFFFF0000x7FFFFFFF0xCE9E46C0xCE9E46C0
    CRC-16 / ARC160x80050x00001010x00000xBB3D0x0000BB3D
    CRC-16 / AUG-CCITT160x10210x1D0F0000x00000xE5CC0xE5CC0000
    CRC-16 / BUYPASS160x80050x00000000x00000xFEE80xFEE80000
    CRC-16 / CCITT-0160x10210xFFFF0000x00000x29B10x29B10000
    CRC-16 / CDMA2000160xC8670xFFFF0000x00000x4C060x4C060000
    CRC-16 / DDS-110160x80050x800D0000x00000x9ECF0x9ECF0000
    CRC-16 / DECT-R160x05890x00000000x00010x007E0x007E0000
    CRC-16 / DECT-X160x05890x00000000x00000x007F0x007F0000
    CRC-16 / DNP160x3D650x00001010xFFFF0xEA820x0000EA82
    CRC-16 / EN-13757160x3D650x00000000xFFFF0xC2B70xC2B70000
    CRC-16 / GENIBUS160x10210xFFFF0000xFFFF0xD64E0xD64E0000
    CRC-16 / MAXIM160x80050x00001010xFFFF0x44C20x000044C2
    CRC-16 / MCRF4XX160x10210xFFFF1010x00000x6F910x00006F91
    CRC-16 / RIELLO160x10210xB2AA1010x00000x63D00x000063D0
    CRC-16 / T10-DIF160x8BB70x00000000x00000xD0DB0xD0DB0000
    CRC-16 / TELEDISK160xA0970x00000000x00000x0FB30x0FB30000
    CRC-16 / TMS37157160x10210x89EC1010x00000x26B10x000026B1
    CRC-16 / USB160x80050xFFFF1010xFFFF0xB4C80x0000B4C8
    CRC-A160x10210xC6C61010x00000xBF050x0000BF05
    CRC-16 / KERMIT160x10210x00001010x00000x21890x00002189
    CRC-16 / MODBUS160x80050xFFFF1010x00000x4B370x00004B37
    CRC-16 / X-25160x10210xFFFF1010xFFFF0x906E0x0000906E
    CRC-16 / XMODEM160x10210x00000000x00000x31C30x31C30000
    CRC-32320x04C11DB70xFFFFFFFF1010xFFFFFFFF0xCBF439260xCBF43926
    CRC-32 / BZIP2320x04C11DB70xFFFFFFFF0000xFFFFFFFF0xFC8919180xFC891918
    CRC-32C320x1EDC6F410xFFFFFFFF1010xFFFFFFFF0xE30692830xE3069283
    CRC-32D320xA833982B0xFFFFFFFF1010xFFFFFFFF0x873155760x87315576
    CRC-32 / MPEG-2320x04C11DB70xFFFFFFFF0000x000000000x0376E6E70x0376E6E7
    CRC-32 / POSIX320x04C11DB70x000000000000xFFFFFFFF0x765E76800x765E7680
    CRC-32Q320x814141AB0x000000000000x000000000x3010BF7F0x3010BF7F
    CRC-32 / JAMCRC320x04C11DB70xFFFFFFFF1010x000000000x340BC6D90x340BC6D9
    CRC-32 / XFER320x000000AF0x000000000000x000000000xBD0BE3380xBD0BE338
    +* +* +* \param polynomial +* The polynomial (specified using 32 bits) used in the computing CRC. +* +* \param dataReverse +* The order in which data bytes are processed. 0 - MSB first; 1- LSB first. +* +* \param dataXor +* The byte mask for XORing data +* +* \param remReverse +* A reminder reverse: 0 means the remainder is not reversed. 1 means reversed. +* +* \param remXor +* Specifies a mask with which the LFSR32 register is XORed to produce a remainder. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_crc_t structure that stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Crc_Init(uint32_t polynomial, + uint8_t dataReverse, + uint8_t dataXor, + uint8_t remReverse, + uint32_t remXor, + cy_stc_crypto_context_crc_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Crc_Run +****************************************************************************//** +* +* This function performs CRC calculation on a message. +* It depends on \ref Cy_Crypto_Crc_Init(), +* which should be called before. +* +* \param data +* The pointer to the message whose CRC is being computed. +* +* \param dataSize +* The size of a message in bytes. +* +* \param crc +* The pointer to a computed CRC value. +* +* \param lfsrInitState +* The initial state of the LFSR. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_crc_t structure that stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Crc_Run(void *data, + uint16_t dataSize, + uint32_t *crc, + uint32_t lfsrInitState, + cy_stc_crypto_context_crc_t *cfContext); +#endif /* #if (CPUSS_CRYPTO_CRC == 1) */ + +#if (CPUSS_CRYPTO_TR == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Trng_Generate +****************************************************************************//** +* +* This function generates a 32-bit True Random Number. +* +* \param GAROPol; +* The polynomial for the programmable Galois ring oscillator. +* +* \param FIROPol; +* The polynomial for the programmable Fibonacci ring oscillator. +* +* \param max +* The maximum length of a random number, in the range [0, 32] bits. +* +* \param randomNum +* The pointer to a generated true random number. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_trng_t structure that stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Trng_Generate(uint32_t GAROPol, + uint32_t FIROPol, + uint32_t max, + uint32_t *randomNum, + cy_stc_crypto_context_trng_t *cfContext); +#endif /* #if (CPUSS_CRYPTO_TR == 1) */ + +#if (CPUSS_CRYPTO_DES == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Des_Run +****************************************************************************//** +* +* This function performs DES operation on a Single Block. All addresses must be +* 4-Byte aligned. +* Ciphertext (dstBlock) may overlap with plaintext (srcBlock) +* There is no Init function. Provide the required parameters and the pointer +* to the context structure when making this function call. +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT (\ref cy_en_crypto_dir_mode_t) +* +* \param key +* The pointer to the encryption/decryption key. +* +* \param srcBlock +* The pointer to a source block. Must be 4-byte aligned. +* +* \param dstBlock +* The pointer to a destination cipher block. +* +* \param cfContext +* The pointer to the cy_stc_crypto_context_des_t structure that stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Des_Run(cy_en_crypto_dir_mode_t dirMode, + uint32_t *key, + uint32_t *dstBlock, + uint32_t *srcBlock, + cy_stc_crypto_context_des_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Tdes_Run +****************************************************************************//** +* +* This function performs the TDES operation on a single block. All addresses +* must be 4-byte aligned. +* Ciphertext (dstBlock) may overlap with plaintext (srcBlock). +* There is no Init function. Provide the required parameters and the pointer +* to the context structure when making this function call. +* +* \param dirMode +* Can be CRYPTO_ENCRYPT or CRYPTO_DECRYPT (\ref cy_en_crypto_dir_mode_t) +* +* \param key +* The pointer to the encryption/decryption key. +* +* \param srcBlock +* The pointer to a source block. Must be 4-vyte aligned. +* +* \param dstBlock +* The pointer to a destination cipher block. +* +* \param cfContext +* The pointer to the cy_stc_crypto_context_des_t structure that stores +* the Crypto driver context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Tdes_Run(cy_en_crypto_dir_mode_t dirMode, + uint32_t *key, + uint32_t *dstBlock, + uint32_t *srcBlock, + cy_stc_crypto_context_des_t *cfContext); +#endif /* #if (CPUSS_CRYPTO_DES == 1) */ + +#if (CPUSS_CRYPTO_VU == 1) +/******************************************************************************* +* Function Name: Cy_Crypto_Rsa_Proc +****************************************************************************//** +* +* This function calculates (m^e mod modulo) where m is Message (Signature), e - public exponent +* using a public key in the next representation, it contains: +* modulo, +* public exponent, +* coefficient for Barrett reduction, +* binary inverse of the modulo, and +* result of (2^moduloLength mod modulo). +* +* Not all fields in a key must be given. Modulo and public exponents are mandatory; +* Barrett coefficient, inverse modulo, and r-bar are optional. +* If they don't exist, their according pointers should be NULL. These coefficients +* could be calculated by \ref Cy_Crypto_Rsa_CalcCoefs. +* Their presence accelerates performance by five times. +* Approximate performance for 1024-bit modulo is 41.6 ms; for 2048-bit modulo is 142 ms +* when using a 25 MHz clock for Crypto HW. These numbers just for reference. +* They depend on many factors (compiler, optimization level, etc.). +* +* Returns the processed value and a success value. +* +* \note Incoming message and result processed message are little-endianess big +* integer values. To convert it from (to) binary (octet) strings use the \ref +* Cy_Crypto_Rsa_InvertEndianness function. +* +* +* \param pubKey +* The pointer to the \ref cy_stc_crypto_rsa_pub_key_t structure that stores +* public key. +* +* \param message +* The pointer to the message to be processed. +* +* \param messageSize +* The length of the message to be processed. +* +* \param processedMessage +* The pointer to processed message. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_rsa_t structure that stores +* the RSA context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Rsa_Proc(cy_stc_crypto_rsa_pub_key_t const *pubKey, + uint32_t const *message, + uint32_t messageSize, + uint32_t *processedMessage, + cy_stc_crypto_context_rsa_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Rsa_CalcCoefs +****************************************************************************//** +* +* This function calculates constant coefficients (which is dependent only on modulo +* and independent on message). With this pre-calculated coefficients calculations +* speed-up by five times. +* +* These coefficients are: +* coefficient for Barrett reduction, +* binary inverse of the modulo, +* result of (2^moduloLength mod modulo) +* +* Calculated coefficients will be placed by addresses provided in the +* pubKey structure for according coefficients. +* Function overwrites previous values. +* Approximate performance for 1024-bit modulo is 33.2 ms; for 2048-bit modulo is 113 ms +* when using a 25 MHz clock for Crypto HW. These numbers are just for reference. +* They depend on many factors (compiler, optimization level, etc.). +* +* \param pubKey +* The pointer to the \ref cy_stc_crypto_rsa_pub_key_t structure that stores a +* public key. +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_rsa_t structure that stores +* the RSA context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Rsa_CalcCoefs(cy_stc_crypto_rsa_pub_key_t const *pubKey, + cy_stc_crypto_context_rsa_t *cfContext); +#endif /* #if (CPUSS_CRYPTO_VU == 1) */ + +/******************************************************************************* +* Function Name: Cy_Crypto_Rsa_Verify +****************************************************************************//** +* +* This function does an RSA verification with checks for content, paddings, and +* signature format. +* The SHA digest of the message and decrypted message should be calculated first. +* Supports only PKCS1-v1_5 format. Inside of this format supported padding +* using only SHA. Cases with MD2 and MD5 are not supported. +* +* PKCS1-v1_5 described here, page 31: +* http://www.emc.com/collateral/white-papers/h11300-pkcs-1v2-2-rsa-cryptography-standard-wp.pdf +* +* Returns the verification result \ref cy_en_crypto_rsa_ver_result_t. +* +* \param verResult +* The pointer to the verification result \ref cy_en_crypto_rsa_ver_result_t. +* +* \param digestType +* SHA mode used for hash calculation \ref cy_en_crypto_sha_mode_t. +* +* \param digest +* The pointer to the hash of the message whose signature is to be verified. +* +* \param decryptedSignature +* The pointer to the decrypted signature to be verified. +* +* \param decryptedSignatureLength +* The length of the decrypted signature to be verified (in bytes) +* +* \param cfContext +* The pointer to the \ref cy_stc_crypto_context_rsa_ver_t structure that stores +* the RSA context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Rsa_Verify(cy_en_crypto_rsa_ver_result_t *verResult, + cy_en_crypto_sha_mode_t digestType, + uint32_t const *digest, + uint32_t const *decryptedSignature, + uint32_t decryptedSignatureLength, + cy_stc_crypto_context_rsa_ver_t *cfContext); + +/******************************************************************************* +* Function Name: Cy_Crypto_Rsa_InvertEndianness +****************************************************************************//** +* +* This function reverts byte-array memory block, like:
    +* inArr[0] <---> inArr[n]
    +* inArr[1] <---> inArr[n-1]
    +* inArr[2] <---> inArr[n-2]
    +* ........................
    +* inArr[n/2] <---> inArr[n/2-1]
    +* +* Odd or even byteSize are acceptable. +* +* \param inArrPtr +* The pointer to the memory whose endianness is to be inverted. +* +* \param byteSize +* The length of the memory array whose endianness is to be inverted (in bytes) +* +*******************************************************************************/ +void Cy_Crypto_Rsa_InvertEndianness(void *inArrPtr, uint32_t byteSize); + + +/** \} group_crypto_cli_functions */ + + +#if defined(__cplusplus) +} +#endif + +#endif /* #if (CPUSS_CRYPTO_PRESENT == 1) */ + +#endif /* (CY_CRYPTO_H) */ + +/** \} group_crypto */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_common.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_common.h new file mode 100644 index 0000000000..d723e03be3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_common.h @@ -0,0 +1,727 @@ +/***************************************************************************//** +* \file cy_crypto_common.h +* \version 2.0 +* +* \brief +* This file provides common constants and parameters +* for the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_CRYPTO_COMMON_H) +#define CY_CRYPTO_COMMON_H + +#include +#include +#include "cy_device_headers.h" +#include "sysint/cy_sysint.h" +#include "syslib/cy_syslib.h" + +#ifndef CY_IP_MXCRYPTO + #error "The CRYPTO driver is not supported on this device" +#endif + +#if (CPUSS_CRYPTO_PRESENT == 1) + +#define CY_CRYPTO_CORE_ENABLE (1) + +/** Driver major version */ +#define CY_CRYPTO_DRV_VERSION_MAJOR 2 + +/** Driver minor version */ +#define CY_CRYPTO_DRV_VERSION_MINOR 0 + +/** Defines the Crypto notify interrupt number */ +#define CY_CRYPTO_IPC_INTR_NOTIFY_NUM CY_IPC_INTR_CRYPTO_SRV + +/** Defines the Crypto release interrupt number */ +#define CY_CRYPTO_IPC_INTR_RELEASE_NUM CY_IPC_INTR_CRYPTO_CLI + +/** +* \addtogroup group_crypto_macros +* \{ +*/ + +/** Defines Crypto_Sync blocking execution type parameter */ +#define CY_CRYPTO_SYNC_BLOCKING (true) + +/** Defines Crypto_Sync non-blocking execution type parameter */ +#define CY_CRYPTO_SYNC_NON_BLOCKING (false) + +/** Defines the Crypto DES key size (in bytes) */ +#define CY_CRYPTO_DES_KEY_SIZE (8u) + +/** Defines the Crypto TDES key size (in bytes) */ +#define CY_CRYPTO_TDES_KEY_SIZE (24u) + +/** Defines the Crypto AES block size (in bytes) */ +#define CY_CRYPTO_AES_BLOCK_SIZE (16u) + +/** Defines the Crypto AES key maximum size (in bytes) */ +#define CY_CRYPTO_AES_128_KEY_SIZE (16u) + +/** Defines the Crypto AES key maximum size (in bytes) */ +#define CY_CRYPTO_AES_192_KEY_SIZE (24u) + +/** Defines the Crypto AES key maximum size (in bytes) */ +#define CY_CRYPTO_AES_256_KEY_SIZE (32u) + +/** Defines size of the AES block, in four-byte words */ +#define CY_CRYPTO_AES_BLOCK_SIZE_U32 (uint32_t)(CY_CRYPTO_AES_BLOCK_SIZE / 4ul) + +#if (CPUSS_CRYPTO_SHA == 1) + +/** Hash size for the SHA1 mode (in bytes) */ +#define CY_CRYPTO_SHA1_DIGEST_SIZE (20u) +/** Hash size for the SHA224 mode (in bytes) */ +#define CY_CRYPTO_SHA224_DIGEST_SIZE (28u) +/** Hash size for the SHA256 mode (in bytes) */ +#define CY_CRYPTO_SHA256_DIGEST_SIZE (32u) +/** Hash size for the SHA384 mode (in bytes) */ +#define CY_CRYPTO_SHA384_DIGEST_SIZE (48u) +/** Hash size for the SHA512 mode (in bytes) */ +#define CY_CRYPTO_SHA512_DIGEST_SIZE (64u) +/** Hash size for the SHA512_224 mode (in bytes) */ +#define CY_CRYPTO_SHA512_224_DIGEST_SIZE (28u) +/** Hash size for the SHA512_256 mode (in bytes) */ +#define CY_CRYPTO_SHA512_256_DIGEST_SIZE (32u) + +#endif /* #if (CPUSS_CRYPTO_SHA == 1) */ + + +#if (CPUSS_CRYPTO_VU == 1) + +/** Processed message size for the RSA 1024Bit mode (in bytes) */ +#define CY_CRYPTO_RSA1024_MESSAGE_SIZE (128) +/** Processed message size for the RSA 1536Bit mode (in bytes) */ +#define CY_CRYPTO_RSA1536_MESSAGE_SIZE (192) +/** Processed message size for the RSA 2048Bit mode (in bytes) */ +#define CY_CRYPTO_RSA2048_MESSAGE_SIZE (256) + +#endif /* #if (CPUSS_CRYPTO_VU == 1) */ + + +/** Crypto Driver PDL ID */ +#define CY_CRYPTO_ID CY_PDL_DRV_ID(0x0Cu) + +/** \} group_crypto_macros */ + +/** +* \addtogroup group_crypto_config_structure +* \{ +*/ + +/** The Crypto user callback function type. + Callback is called at the end of Crypto calculation. */ +typedef void (*cy_crypto_callback_ptr_t)(void); + +/** The Crypto configuration structure. */ +typedef struct +{ + /** Defines the IPC channel used for client-server data exchange */ + uint32_t ipcChannel; + + /** Specifies the IPC notifier channel (IPC interrupt structure number) + to notify server that data for the operation is prepared */ + uint32_t acquireNotifierChannel; + + /** Specifies the IPC notifier channel (IPC interrupt structure number) + to notify client that operation is complete and data is valid */ + uint32_t releaseNotifierChannel; + + /** Specifies the release notifier interrupt configuration. It used for + internal purposes and user doesn't fill it. */ + cy_stc_sysint_t releaseNotifierConfig; + + /** User callback function. + If this field is NOT NULL, it called when Crypto operation + is complete. */ + cy_crypto_callback_ptr_t userCompleteCallback; + +#if (CY_CRYPTO_CORE_ENABLE) + /** Server-side user IRQ handler function, called when data for the + operation is prepared to process. + - If this field is NULL, server will use own interrupt handler + to get data. + - If this field is not NULL, server will call this interrupt handler. + This interrupt handler must call the + \ref Cy_Crypto_Server_GetDataHandler to get data to process. + + Note: In the second case user should process data separately and + clear interrupt by calling \ref Cy_Crypto_Server_Process. + This model is used in the + multitasking environment (e.g. CyOS). */ + cy_israddress userGetDataHandler; + + /** Server-side user IRQ handler function, called when a Crypto hardware + error occurs (interrupt was raised). + - If this field is NULL - server will use own interrupt handler + for error processing. + - If this field is not NULL - server will call this interrupt handler. + This interrupt handler must call the + \ref Cy_Crypto_Server_ErrorHandler to clear the interrupt. */ + cy_israddress userErrorHandler; + + /** Specifies the prepared data notifier interrupt configuration. It used + for internal purposes and user doesn't fill it. */ + cy_stc_sysint_t acquireNotifierConfig; + + /** Specifies the hardware error processing interrupt configuration. It used + for internal purposes and user doesn't fill it. */ + cy_stc_sysint_t cryptoErrorIntrConfig; +#endif /* (CY_CRYPTO_CORE_ENABLE) */ + +} cy_stc_crypto_config_t; + +/** \} group_crypto_config_structure */ + +/** +* \addtogroup group_crypto_cli_data_structures +* \{ +*/ + +#if (CPUSS_CRYPTO_VU == 1) +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the RSA public key and + * additional coefficients to accelerate RSA calculation. + * + * RSA key contained from two fields: + * - n - modulus part of the key + * - e - exponent part of the key. + * + * Other fields are accelerating coefficients and can be calculated by + * \ref Cy_Crypto_Rsa_CalcCoefs. +*/ +typedef struct +{ + /** The pointer to the modulus part of public key. */ + uint8_t *moduloPtr; + /** The modulus length, in bits, maximum supported size is 2048Bit */ + uint32_t moduloLength; + + /** The pointer to the exponent part of public key */ + uint8_t *pubExpPtr; + /** The exponent length, in bits, maximum supported size is 256Bit */ + uint32_t pubExpLength; + + /** The pointer to the Barrett coefficient. Memory for it should be + allocated by user with size moduloLength + 1. */ + uint8_t *barretCoefPtr; + + /** The pointer to the binary inverse of the modulo. Memory for it + should be allocated by user with size moduloLength. */ + uint8_t *inverseModuloPtr; + + /** The pointer to the (2^moduloLength mod modulo). Memory for it should + be allocated by user with size moduloLength */ + uint8_t *rBarPtr; +} cy_stc_crypto_rsa_pub_key_t; + +#endif /* #if (CPUSS_CRYPTO_VU == 1) */ + +/** Structure for storing a description of a Crypto hardware error */ +typedef struct +{ + /** + Captures error description information: + for INSTR_OPC_ERROR: - violating the instruction. + for INSTR_CC_ERROR : - violating the instruction condition code. + for BUS_ERROR : - violating the transfer address. */ + uint32_t errorStatus0; + + /** + [31] - Specifies if ERROR_STATUS0 and ERROR_STATUS1 capture valid + error-information. + [26..24] - The error source: + "0": INSTR_OPC_ERROR - an instruction decoder error. + "1": INSTR_CC_ERROR - an instruction condition code-error. + "2": BUS_ERROR - a bus master interface AHB-Lite bus-error. + "3": TR_AP_DETECT_ERROR. + [23..0] - Captures error description information. + For BUS_ERROR: + - violating the transfer, read the attribute (DATA23[0]). + - violating the transfer, the size attribute (DATA23[5:4]). + "0": an 8-bit transfer; + "1": 16 bits transfer; + "2": 32-bit transfer. */ + uint32_t errorStatus1; +} cy_stc_crypto_hw_error_t; + +/** \} group_crypto_cli_data_structures */ + + +/** The Crypto library functionality level. */ +typedef enum +{ + CY_CRYPTO_NO_LIBRARY = 0x00u, + CY_CRYPTO_BASE_LIBRARY = 0x01u, + CY_CRYPTO_EXTRA_LIBRARY = 0x02u, + CY_CRYPTO_FULL_LIBRARY = 0x03u, +} cy_en_crypto_lib_info_t; + + +/** +* \addtogroup group_crypto_enums +* \{ +*/ + +#if (CPUSS_CRYPTO_AES == 1) +/** The key length options for the AES method. */ +typedef enum +{ + CY_CRYPTO_KEY_AES_128 = 0x00u, /**< The AES key size is 128 bits */ + CY_CRYPTO_KEY_AES_192 = 0x01u, /**< The AES key size is 192 bits */ + CY_CRYPTO_KEY_AES_256 = 0x02u /**< The AES key size is 256 bits */ +} cy_en_crypto_aes_key_length_t; +#endif /* #if (CPUSS_CRYPTO_AES == 1) */ + +/** Defines the direction of the Crypto methods */ +typedef enum +{ + /** The forward mode, plain text will be encrypted into cipher text */ + CY_CRYPTO_ENCRYPT = 0x00u, + /** The reverse mode, cipher text will be decrypted into plain text */ + CY_CRYPTO_DECRYPT = 0x01u +} cy_en_crypto_dir_mode_t; + +#if (CPUSS_CRYPTO_SHA == 1) +/** Defines modes of SHA method */ +typedef enum +{ +#if (CPUSS_CRYPTO_SHA1 == 1) + CY_CRYPTO_MODE_SHA1 = 0x00u, /**< Sets the SHA1 mode */ +#endif /* #if (CPUSS_CRYPTO_SHA1 == 1) */ + +#if (CPUSS_CRYPTO_SHA256 == 1) + CY_CRYPTO_MODE_SHA224 = 0x11u, /**< Sets the SHA224 mode */ + CY_CRYPTO_MODE_SHA256 = 0x01u, /**< Sets the SHA256 mode */ +#endif /* #if (CPUSS_CRYPTO_SHA256 == 1) */ + +#if (CPUSS_CRYPTO_SHA512 == 1) + CY_CRYPTO_MODE_SHA384 = 0x12u, /**< Sets the SHA384 mode */ + CY_CRYPTO_MODE_SHA512 = 0x02u, /**< Sets the SHA512 mode */ + CY_CRYPTO_MODE_SHA512_256 = 0x22u, /**< Sets the SHA512/256 mode */ + CY_CRYPTO_MODE_SHA512_224 = 0x32u /**< Sets the SHA512/224 mode */ +#endif /* #if (CPUSS_CRYPTO_SHA512 == 1) */ +} cy_en_crypto_sha_mode_t; +#endif /* #if (CPUSS_CRYPTO_SHA == 1) */ + +/** Signature verification status */ +typedef enum +{ + CY_CRYPTO_RSA_VERIFY_SUCCESS = 0x00u, /**< PKCS1-v1.5 verify SUCCESS */ + CY_CRYPTO_RSA_VERIFY_FAIL = 0x01u /**< PKCS1-v1.5 verify FAILED */ +} cy_en_crypto_rsa_ver_result_t; + +/** Errors of the Crypto block */ +typedef enum +{ + /** Operation completed successfully. */ + CY_CRYPTO_SUCCESS = 0x00u, + + /** A hardware error occurred, detailed information is in stc_crypto_hw_error_t. */ + CY_CRYPTO_HW_ERROR = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x01u, + + /** The size of input data is not multiple of 16. */ + CY_CRYPTO_SIZE_NOT_X16 = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x02u, + + /** The key for the DES method is weak. */ + CY_CRYPTO_DES_WEAK_KEY = CY_CRYPTO_ID | CY_PDL_STATUS_WARNING | 0x03u, + + /** Communication between the client and server via IPC is broken. */ + CY_CRYPTO_COMM_FAIL = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x04u, + + /** The Crypto server is not started. */ + CY_CRYPTO_SERVER_NOT_STARTED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x06u, + + /** The Crypto server in process state. */ + CY_CRYPTO_SERVER_BUSY = CY_CRYPTO_ID | CY_PDL_STATUS_INFO | 0x07u, + + /** The Crypto driver is not initialized. */ + CY_CRYPTO_NOT_INITIALIZED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x08u, + + /** The Crypto hardware is not enabled. */ + CY_CRYPTO_HW_NOT_ENABLED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x09u, + + /** The Crypto operation is not supported. */ + CY_CRYPTO_NOT_SUPPORTED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x0Au + +} cy_en_crypto_status_t; + +/** \} group_crypto_enums */ + +/** \cond INTERNAL */ + +/** Instruction to communicate between Client and Server */ +typedef enum +{ + CY_CRYPTO_INSTR_UNKNOWN = 0x00u, + CY_CRYPTO_INSTR_ENABLE = 0x01u, + CY_CRYPTO_INSTR_DISABLE = 0x02u, + +#if (CPUSS_CRYPTO_PR == 1) + CY_CRYPTO_INSTR_PRNG_INIT = 0x03u, + CY_CRYPTO_INSTR_PRNG = 0x04u, +#endif /* #if (CPUSS_CRYPTO_PR == 1) */ + +#if (CPUSS_CRYPTO_TR == 1) + CY_CRYPTO_INSTR_TRNG_INIT = 0x05u, + CY_CRYPTO_INSTR_TRNG = 0x06u, +#endif /* #if (CPUSS_CRYPTO_PR == 1) */ + +#if (CPUSS_CRYPTO_AES == 1) + CY_CRYPTO_INSTR_AES_INIT = 0x07u, + CY_CRYPTO_INSTR_AES_ECB = 0x08u, + CY_CRYPTO_INSTR_AES_CBC = 0x09u, + CY_CRYPTO_INSTR_AES_CFB = 0x0Au, + CY_CRYPTO_INSTR_AES_CTR = 0x0Bu, + CY_CRYPTO_INSTR_CMAC = 0x0Cu, +#endif /* #if (CPUSS_CRYPTO_AES == 1) */ + +#if (CPUSS_CRYPTO_SHA == 1) + CY_CRYPTO_INSTR_SHA = 0x0Du, +#endif /* #if (CPUSS_CRYPTO_SHA == 1) */ + +#if (CPUSS_CRYPTO_SHA == 1) + CY_CRYPTO_INSTR_HMAC = 0x0Eu, +#endif /* #if (CPUSS_CRYPTO_SHA == 1) */ + +#if (CPUSS_CRYPTO_STR == 1) + CY_CRYPTO_INSTR_MEM_CPY = 0x0Fu, + CY_CRYPTO_INSTR_MEM_SET = 0x10u, + CY_CRYPTO_INSTR_MEM_CMP = 0x11u, + CY_CRYPTO_INSTR_MEM_XOR = 0x12u, +#endif /* #if (CPUSS_CRYPTO_STR == 1) */ + +#if (CPUSS_CRYPTO_CRC == 1) + CY_CRYPTO_INSTR_CRC_INIT = 0x13u, + CY_CRYPTO_INSTR_CRC = 0x14u, +#endif /* #if (CPUSS_CRYPTO_CRC == 1) */ + +#if (CPUSS_CRYPTO_DES == 1) + CY_CRYPTO_INSTR_DES = 0x15u, + CY_CRYPTO_INSTR_3DES = 0x16u, +#endif /* #if (CPUSS_CRYPTO_DES == 1) */ + +#if (CPUSS_CRYPTO_VU == 1) + CY_CRYPTO_INSTR_RSA_PROC = 0x17u, + CY_CRYPTO_INSTR_RSA_COEF = 0x18u, +#endif /* #if (CPUSS_CRYPTO_VU == 1) */ + +#if (CPUSS_CRYPTO_SHA == 1) + CY_CRYPTO_INSTR_RSA_VER = 0x19u, +#endif /* #if (CPUSS_CRYPTO_SHA == 1) */ + + CY_CRYPTO_INSTR_SRV_INFO = 0x55u +} cy_en_crypto_comm_instr_t; + +/** \endcond */ + +/** +* \addtogroup group_crypto_cli_data_structures +* \{ +*/ + +#if (CPUSS_CRYPTO_AES == 1) +/** Structure for storing the AES state */ +typedef struct +{ + /** Pointer to AES key */ + uint32_t *key; + /** Pointer to AES inversed key */ + uint32_t *invKey; + /** AES key length */ + cy_en_crypto_aes_key_length_t keyLength; + /** AES processed block index (for CMAC, SHA operations) */ + uint32_t blockIdx; +} cy_stc_crypto_aes_state_t; +#endif /* #if (CPUSS_CRYPTO_AES == 1) */ + +/** \} group_crypto_cli_data_structures */ + +/************************************************************* +* Structures used for communication between Client and Server +***************************************************************/ + +/** +* \addtogroup group_crypto_srv_data_structures +* \{ +*/ + +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the server + * context. + */ +typedef struct +{ + /** IPC communication channel number */ + uint32_t ipcChannel; + /** IPC acquire interrupt channel number */ + uint32_t acquireNotifierChannel; + /** IPC release interrupt channel number */ + cy_israddress getDataHandlerPtr; + /** Crypto hardware errors interrupt handler */ + cy_israddress errorHandlerPtr; + /** Acquire notifier interrupt configuration */ + cy_stc_sysint_t acquireNotifierConfig; + /** Crypto hardware errors interrupt configuration */ + cy_stc_sysint_t cryptoErrorIntrConfig; + /** Hardware error occurrence flag */ + bool isHwErrorOccured; +} cy_stc_crypto_server_context_t; + +/** \} group_crypto_srv_data_structures */ + +/** +* \addtogroup group_crypto_cli_data_structures +* \{ +*/ + +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the global + * context. + */ +typedef struct +{ + /** Operation instruction code */ + cy_en_crypto_comm_instr_t instr; + /** Response from executed crypto function */ + cy_en_crypto_status_t resp; + /** Hardware processing errors */ + cy_stc_crypto_hw_error_t hwErrorStatus; + /** IPC communication channel number */ + uint32_t ipcChannel; + /** IPC acquire interrupt channel number */ + uint32_t acquireNotifierChannel; + /** IPC release interrupt channel number */ + uint32_t releaseNotifierChannel; + /** User callback for Crypto HW calculation complete event */ + cy_crypto_callback_ptr_t userCompleteCallback; + /** Release notifier interrupt configuration */ + cy_stc_sysint_t releaseNotifierConfig; + /** Pointer to the crypto function specific context data */ + void *xdata; +} cy_stc_crypto_context_t; + + +#if (CPUSS_CRYPTO_DES == 1) +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the DES operational + * context. + */ +typedef struct +{ + /** Operation direction (Encrypt / Decrypt) */ + cy_en_crypto_dir_mode_t dirMode; + /** Pointer to key data */ + uint32_t *key; + /** Pointer to data destination block */ + uint32_t *dst; + /** Pointer to data source block */ + uint32_t *src; +} cy_stc_crypto_context_des_t; +#endif /* #if (CPUSS_CRYPTO_DES == 1) */ + +#if (CPUSS_CRYPTO_AES == 1) +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the AES operational + * context. + */ +typedef struct +{ + /** AES state data */ + cy_stc_crypto_aes_state_t aesState; + /** Operation direction (Encrypt / Decrypt) */ + cy_en_crypto_dir_mode_t dirMode; + /** Operation data size */ + uint32_t srcSize; + /** Size of the last non-complete block (for CTR mode only) */ + uint32_t *srcOffset; + /** Initialization vector, in the CTR mode is used as nonceCounter */ + uint32_t *ivPtr; + /** AES processed block pointer (for CTR mode only) */ + uint32_t *streamBlock; + /** Pointer to data destination block */ + uint32_t *dst; + /** Pointer to data source block */ + uint32_t *src; +} cy_stc_crypto_context_aes_t; +#endif /* #if (CPUSS_CRYPTO_AES == 1) */ + +#if (CPUSS_CRYPTO_SHA == 1) +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the SHA operational + * context. + */ +typedef struct +{ + /** Pointer to data source block */ + uint32_t *message; + /** Operation data size */ + uint32_t messageSize; + /** Pointer to data destination block */ + uint32_t *dst; + /** SHA mode */ + cy_en_crypto_sha_mode_t mode; + /** Pointer to key data (for HMAC only) */ + uint32_t *key; + /** Key data length (for HMAC only) */ + uint32_t keyLength; +} cy_stc_crypto_context_sha_t; +#endif /* #if (CPUSS_CRYPTO_SHA == 1) */ + +#if (CPUSS_CRYPTO_PR == 1) +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the PRNG operational + * context. + */ +typedef struct +{ + uint32_t lfsr32InitState; /**< lfsr32 initialization data */ + uint32_t lfsr31InitState; /**< lfsr31 initialization data */ + uint32_t lfsr29InitState; /**< lfsr29 initialization data */ + uint32_t max; /**< Maximum of the generated value */ + uint32_t *prngNum; /**< Pointer to generated value */ +} cy_stc_crypto_context_prng_t; +#endif /* #if (CPUSS_CRYPTO_PR == 1) */ + +#if (CPUSS_CRYPTO_TR == 1) +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the TRNG operational + * context. + */ +typedef struct +{ + /** + The polynomial for the programmable Galois ring oscillator (TR_GARO_CTL). + The polynomial is represented WITHOUT the high order bit (this bit is + always assumed '1'). + The polynomial should be aligned so that more significant bits + (bit 30 and down) contain the polynomial and less significant bits + (bit 0 and up) contain padding '0's. */ + uint32_t GAROPol; + + /** + The polynomial for the programmable Fibonacci ring oscillator(TR_FIRO_CTL). + The polynomial is represented WITHOUT the high order bit (this bit is + always assumed '1'). + The polynomial should be aligned so that more significant bits + (bit 30 and down) contain the polynomial and less significant bits + (bit 0 and up) contain padding '0's. */ + uint32_t FIROPol; + /** Maximum of the generated value */ + uint32_t max; + /** Pointer to generated value */ + uint32_t *trngNum; +} cy_stc_crypto_context_trng_t; +#endif /* #if (CPUSS_CRYPTO_TR == 1) */ + +#if (CPUSS_CRYPTO_STR == 1) +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the STR operational + * context. + */ +typedef struct +{ + void const *src0; /**< Pointer to 1-st string source */ + void const *src1; /**< Pointer to 2-nd string source */ + void *dst; /**< Pointer to string destination */ + uint32_t dataSize; /**< Operation data size */ + uint32_t data; /**< Operation data value (for memory setting) */ +} cy_stc_crypto_context_str_t; +#endif /* #if (CPUSS_CRYPTO_STR == 1) */ + +#if (CPUSS_CRYPTO_CRC == 1) +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the CRC operational + * context. + */ +typedef struct +{ + void* srcData; /**< Pointer to data source block */ + uint32_t dataSize; /**< Operation data size */ + uint32_t *crc; /**< Pointer to CRC destination variable */ + uint32_t polynomial; /**< Polynomial for CRC calculate */ + uint32_t lfsrInitState; /**< CRC calculation initial value */ + uint32_t dataReverse; /**< Input data reverse flag */ + uint32_t dataXor; /**< Input data XOR flag */ + uint32_t remReverse; /**< Output data reverse flag */ + uint32_t remXor; /**< Output data XOR flag */ +} cy_stc_crypto_context_crc_t; +#endif /* #if (CPUSS_CRYPTO_CRC == 1) */ + +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the RSA verifying + * context. + */ +typedef struct +{ + /** Pointer to verification result /ref cy_en_crypto_rsa_ver_result_t */ + cy_en_crypto_rsa_ver_result_t *verResult; + /** SHA digest type, used with SHA calculation of the message */ + cy_en_crypto_sha_mode_t digestType; + /** SHA digest of the message, calculated with digestType */ + uint32_t const *hash; + /** Previously decrypted RSA signature */ + uint32_t const *decryptedSignature; + /** Length of the decrypted RSA signature */ + uint32_t decryptedSignatureLength; +} cy_stc_crypto_context_rsa_ver_t; + +#if (CPUSS_CRYPTO_VU == 1) +/** + * Firmware allocates memory and provides a pointer to this structure in + * function calls. Firmware does not write or read values in this structure. + * The driver uses this structure to store and manipulate the RSA operational + * context. + */ +typedef struct +{ + /** Pointer to key data */ + cy_stc_crypto_rsa_pub_key_t const *key; + /** Pointer to data source block */ + uint32_t const *message; + /** Operation data size */ + uint32_t messageSize; + /** Pointer to data destination block */ + uint32_t *result; +} cy_stc_crypto_context_rsa_t; +#endif /* #if (CPUSS_CRYPTO_VU == 1) */ + +/** \} group_crypto_cli_data_structures */ + +#endif /* (CPUSS_CRYPTO_PRESENT == 1) */ + +#endif /* #if !defined(CY_CRYPTO_COMMON_H) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_config.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_config.c new file mode 100644 index 0000000000..99532a4a23 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_config.c @@ -0,0 +1,69 @@ +/***************************************************************************//** +* \file +* \version 2.0 +* +* Description: +* This C file is not intended to be part of the Crypto driver. It is the code +* required to configure the crypto driver by user. +* +******************************************************************************** +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_crypto_config.h" + +#include "ipc/cy_ipc_drv.h" +#include "sysint/cy_sysint.h" + + +/** The Crypto configuration structure. */ +const cy_stc_crypto_config_t cryptoConfig = +{ + /* .ipcChannel */ CY_IPC_CHAN_CRYPTO, + /* .acquireNotifierChannel */ CY_CRYPTO_IPC_INTR_NOTIFY_NUM, + /* .releaseNotifierChannel */ CY_CRYPTO_IPC_INTR_RELEASE_NUM, + + /* .releaseNotifierConfig */ { +#if (CY_CPU_CORTEX_M0P) + /* .intrSrc */ CY_CRYPTO_CM0_RELEASE_INTR_NR, + /* .cm0pSrc */ (cy_en_intr_t)CY_IPC_INTR_NUM_TO_VECT((int32_t)CY_CRYPTO_IPC_INTR_RELEASE_NUM), +#else + /* .intrSrc */ (IRQn_Type)CY_IPC_INTR_NUM_TO_VECT((int32_t)CY_CRYPTO_IPC_INTR_RELEASE_NUM), +#endif + /* .intrPriority */ CY_CRYPTO_RELEASE_INTR_PR, + }, + /* .userCompleteCallback */ NULL + +#if (CY_CRYPTO_CORE_ENABLE) + , + /* .userGetDataHandler */ NULL, + /* .userErrorHandler */ NULL, + + /* .acquireNotifierConfig */ { +#if (CY_CPU_CORTEX_M0P) + /* .intrSrc */ CY_CRYPTO_CM0_NOTIFY_INTR_NR, + /* .cm0pSrc */ (cy_en_intr_t)CY_IPC_INTR_NUM_TO_VECT((int32_t)CY_CRYPTO_IPC_INTR_NOTIFY_NUM), +#else + /* .intrSrc */ (IRQn_Type)CY_IPC_INTR_NUM_TO_VECT((int32_t)CY_CRYPTO_IPC_INTR_NOTIFY_NUM), +#endif + /* .intrPriority */ CY_CRYPTO_NOTIFY_INTR_PR, + }, + /* .cryptoErrorIntrConfig */ { +#if (CY_CPU_CORTEX_M0P) + /* .intrSrc */ CY_CRYPTO_CM0_ERROR_INTR_NR, + /* .cm0pSrc */ cpuss_interrupt_crypto_IRQn, +#else + /* .intrSrc */ cpuss_interrupt_crypto_IRQn, +#endif + /* .intrPriority */ CY_CRYPTO_ERROR_INTR_PR, + } +#endif + +}; + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_config.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_config.h new file mode 100644 index 0000000000..d99a8e61a5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_config.h @@ -0,0 +1,57 @@ +/***************************************************************************//** +* \file cy_crypto_config.h +* \version 2.0 +* +* \brief +* This file provides user parameters for the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CRYPTO_CONFIG_H) +#define CY_CRYPTO_CONFIG_H + +#include "cy_device_headers.h" +#include "crypto/cy_crypto_common.h" + +/* Defines to configure Crypto driver */ +extern const cy_stc_crypto_config_t cryptoConfig; + +/** +* \addtogroup group_crypto_config_macros +* \{ +* +* These constants defines an interrupts settings for IPC channel used for the +* client-server communications. +* +* On the CM4 core crypto driver uses IPC hardware depended interrupt sources. +* +* For CM0+ core user must define the multiplexed interrupt sources by yourself. +*/ + +/** Number of Crypto Notify interrupt mapped to CM0+ */ +#define CY_CRYPTO_CM0_NOTIFY_INTR_NR (NvicMux2_IRQn) +/** Priority of Crypto Notify interrupt, equal to CM0+ and CM4 cores */ +#define CY_CRYPTO_NOTIFY_INTR_PR (2u) + +/** Number of Crypto Release interrupt mapped to CM0+ */ +#define CY_CRYPTO_CM0_RELEASE_INTR_NR (NvicMux30_IRQn) +/** Priority of Crypto Release interrupt, equal to CM0+ and CM4 cores */ +#define CY_CRYPTO_RELEASE_INTR_PR (2u) + +/** Number of Crypto Error interrupt mapped to CM0+ */ +#define CY_CRYPTO_CM0_ERROR_INTR_NR (NvicMux31_IRQn) +/** Priority of Crypto Error interrupt mapped to CM0+ */ +#define CY_CRYPTO_ERROR_INTR_PR (2u) + +/** \} group_crypto_config_macros */ + +#endif /* #if !defined(CY_CRYPTO_CONFIG_H) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_server.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_server.h new file mode 100644 index 0000000000..9fc2dc6721 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/crypto/cy_crypto_server.h @@ -0,0 +1,125 @@ +/***************************************************************************//** +* \file cy_crypto_server.h +* \version 2.0 +* +* \brief +* This file provides the prototypes for common API +* in the Crypto driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#if !defined(CY_CRYPTO_SERVER_H) +#define CY_CRYPTO_SERVER_H + +#include "crypto/cy_crypto_common.h" +#include "syslib/cy_syslib.h" + +#if (CY_CRYPTO_CORE_ENABLE) + +#if (CPUSS_CRYPTO_PRESENT == 1) + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_crypto_srv_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_Start +****************************************************************************//** +* +* This function starts the Crypto server on the CM0+ core, sets up an interrupt +* for the IPC Crypto channel on the CM0+ core, sets up an interrupt +* to catch Crypto HW errors. Should be invoked only on CM0. +* +* This function available for CM0+ core only. +* +* \param config +* The Crypto configuration structure. +* +* \param context +* The pointer to the \ref cy_stc_crypto_server_context_t structure that stores +* the Crypto server context. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Server_Start(cy_stc_crypto_config_t const *config, + cy_stc_crypto_server_context_t *context); + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_Stop +****************************************************************************//** +* +* This function stops the Crypto server by disabling the IPC notify interrupt +* and Crypto error interrupt. Should be invoked only on CM0. +* +* This function available for CM0+ core only. +* +* \return +* A Crypto status \ref cy_en_crypto_status_t. +* +*******************************************************************************/ +cy_en_crypto_status_t Cy_Crypto_Server_Stop(void); + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_Process +****************************************************************************//** +* +* This function parses input data received from the Crypto Client, +* runs the appropriate Crypto function and releases the Crypto IPC channel. +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +void Cy_Crypto_Server_Process(void); + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_GetDataHandler +****************************************************************************//** +* +* This function is a IPC Crypto channel notify interrupt-routine. +* It receives information from the Crypto client, +* runs the process if user not setup own handler. +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +void Cy_Crypto_Server_GetDataHandler(void); + +/******************************************************************************* +* Function Name: Cy_Crypto_Server_ErrorHandler +****************************************************************************//** +* +* This function is a routine to handle an interrupt caused by the Crypto hardware error. +* +* This function available for CM0+ core only. +* +*******************************************************************************/ +void Cy_Crypto_Server_ErrorHandler(void); + +/** \} group_crypto_srv_functions */ + +#if defined(__cplusplus) +} +#endif + +#endif /* #if (CPUSS_CRYPTO_PRESENT == 1) */ + +#endif /* #if (CY_CRYPTO_CORE_ENABLE) */ + +#endif /* #if !defined(CY_CRYPTO_SERVER_H) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctb/cy_ctb.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctb/cy_ctb.c new file mode 100644 index 0000000000..3755204f1f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctb/cy_ctb.c @@ -0,0 +1,1311 @@ +/***************************************************************************//** +* \file cy_ctb.c +* \version 1.0 +* +* \brief +* Provides the public functions for the CTB driver. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ctb/cy_ctb.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Fast Config Selections +***************************************/ +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Unused = +{ + /*.oa0Power */ CY_CTB_POWER_OFF, + /*.oa0Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa0SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_COMP, + /*.oa0SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa0SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp10x = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa0SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Diffamp = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_POS_PIN0_MASK | (uint32_t) CY_CTB_SW_OA0_NEG_PIN1_MASK, + /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK, + /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out_SH = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK, + /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Unused = +{ + /*.oa1Power */ CY_CTB_POWER_OFF, + /*.oa1Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa1SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Comp = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_COMP, + /*.oa1SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp1x = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa1SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp10x = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa1SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Diffamp = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_POS_PIN7_MASK | (uint32_t) CY_CTB_SW_OA1_NEG_PIN4_MASK, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA1_POS_AREF_MASK, + /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_REF_OA1_OUT_MASK, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA1_POS_PIN5_MASK, + /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_REF_OA1_OUT_MASK, +}; + +/******************************************************************************* +* Function Name: Cy_CTB_Init +****************************************************************************//** +* +* Initializes or restores the CTB and both Opamps according to the +* provided settings. Parameters are usually set only once, at initialization. +* +* \param base +* Pointer to structure describing registers +* +* \param config +* Pointer to structure containing configuration data +* +* \return cy_en_ctb_status_t +* Status of initialization, CY_CTB_SUCCESS or CY_CTB_BAD_PARAM +* +*******************************************************************************/ +cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config) +{ + CY_ASSERT_L1(NULL != base); + CY_ASSERT_L1(NULL != config); + + cy_en_ctb_status_t result; + + if ((NULL == base) || (NULL == config)) + { + result = CY_CTB_BAD_PARAM; + } + else + { + CY_ASSERT_L3(CY_CTB_DEEPSLEEP(config->deepSleep)); + + /* Enum checks for Opamp0 config */ + CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa0Power)); + CY_ASSERT_L3(CY_CTB_OAMODE(config->oa0Mode)); + CY_ASSERT_L3(CY_CTB_OAPUMP(config->oa0Pump)); + CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oa0CompEdge)); + CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oa0CompLevel)); + CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oa0CompBypass)); + CY_ASSERT_L3(CY_CTB_COMPHYST(config->oa0CompHyst)); + + /* Enum checks for Opamp0 config */ + CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa1Power)); + CY_ASSERT_L3(CY_CTB_OAMODE(config->oa1Mode)); + CY_ASSERT_L3(CY_CTB_OAPUMP(config->oa1Pump)); + CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oa1CompEdge)); + CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oa1CompLevel)); + CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oa1CompBypass)); + CY_ASSERT_L3(CY_CTB_COMPHYST(config->oa1CompHyst)); + + /* Boundary checks for analog routing switch masks */ + CY_ASSERT_L2(CY_CTB_OA0SWITCH(config->oa0SwitchCtrl)); + CY_ASSERT_L2(CY_CTB_OA1SWITCH(config->oa1SwitchCtrl)); + CY_ASSERT_L2(CY_CTB_CTDSWITCH(config->ctdSwitchCtrl)); + + base->CTB_CTRL = (uint32_t) config->deepSleep; + base->OA_RES0_CTRL = (uint32_t) config->oa0Power \ + | (uint32_t) config->oa0Mode \ + | (uint32_t) config->oa0Pump \ + | (uint32_t) config->oa0CompEdge \ + | (uint32_t) config->oa0CompLevel \ + | (uint32_t) config->oa0CompBypass \ + | (uint32_t) config->oa0CompHyst \ + | ((CY_CTB_MODE_OPAMP1X == config->oa0Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); + + base->OA_RES1_CTRL = (uint32_t) config->oa1Power \ + | (uint32_t) config->oa1Mode \ + | (uint32_t) config->oa1Pump \ + | (uint32_t) config->oa1CompEdge \ + | (uint32_t) config->oa1CompLevel \ + | (uint32_t) config->oa1CompBypass \ + | (uint32_t) config->oa1CompHyst \ + | ((CY_CTB_MODE_OPAMP1X == config->oa1Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); + + base->INTR_MASK = (config->oa0CompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT) \ + | (config->oa1CompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT); + + base->OA0_COMP_TRIM = (uint32_t) ((config->oa0Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + base->OA1_COMP_TRIM = (uint32_t) ((config->oa1Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + + if (config->configRouting) + { + base->OA0_SW = config->oa0SwitchCtrl; + base->OA1_SW = config->oa1SwitchCtrl; + base->CTD_SW = config->ctdSwitchCtrl; + } + + if (config->enable) + { + Cy_CTB_Enable(base); + } + + result = CY_CTB_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpampInit +****************************************************************************//** +* +* Initializes each Opamp separately without impacting analog routing. +* Intended for use by automatic analog routing and configuration tools +* to configure each Opamp without having to integrate the settings with +* those of the other Opamp first. +* +* Can also be used to configure both Opamps to have the same settings. +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \param config +* Pointer to structure containing configuration data +* +* \return cy_en_ctb_status_t +* Status of initialization, CY_CTB_SUCCESS or CY_CTB_BAD_PARAM +* +*******************************************************************************/ +cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, const cy_stc_ctb_opamp_config_t *config) +{ + CY_ASSERT_L1(NULL != base); + CY_ASSERT_L1(NULL != config); + + cy_en_ctb_status_t result; + uint32_t oaResCtrl; + + if ((NULL == base) || (NULL == config)) + { + result = CY_CTB_BAD_PARAM; + } + else + { + CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum)); + CY_ASSERT_L3(CY_CTB_DEEPSLEEP(config->deepSleep)); + CY_ASSERT_L3(CY_CTB_OAPOWER(config->oaPower)); + CY_ASSERT_L3(CY_CTB_OAMODE(config->oaMode)); + CY_ASSERT_L3(CY_CTB_OAPUMP(config->oaPump)); + CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oaCompEdge)); + CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oaCompLevel)); + CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oaCompBypass)); + CY_ASSERT_L3(CY_CTB_COMPHYST(config->oaCompHyst)); + + base->CTB_CTRL = (uint32_t) config->deepSleep; + + /* The two Opamp control registers are symmetrical */ + oaResCtrl = (uint32_t) config->oaPower \ + | (uint32_t) config->oaMode \ + | (uint32_t) config->oaPump \ + | (uint32_t) config->oaCompEdge \ + | (uint32_t) config->oaCompLevel \ + | (uint32_t) config->oaCompBypass \ + | (uint32_t) config->oaCompHyst \ + | ((CY_CTB_MODE_OPAMP1X == config->oaMode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); + + if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA_RES0_CTRL = oaResCtrl; + base->OA0_COMP_TRIM = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + + /* The INTR_MASK register is shared between the two Opamps */ + base->INTR_MASK |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT); + } + + if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA_RES1_CTRL = oaResCtrl; + base->OA1_COMP_TRIM = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + + /* The INTR_MASK register is shared between the two Opamps */ + base->INTR_MASK |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT); + } + + if (config->enable) + { + Cy_CTB_Enable(base); + } + + + result = CY_CTB_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTB_DeInit +****************************************************************************//** +* +* Reset CTB registers back to power on reset defaults. +* +* \param base +* Pointer to structure describing registers +* +* \param deInitRouting +* If true, all analog routing switches are reset to their default state. +* If false, analog switch registers are untouched. +* +* \return cy_en_ctb_status_t +* Status of initialization, CY_CTB_SUCCESS or CY_CTB_BAD_PARAM +* +*******************************************************************************/ +cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting) +{ + CY_ASSERT_L1(NULL != base); + + cy_en_ctb_status_t result; + + if (NULL == base) + { + result = CY_CTB_BAD_PARAM; + } + else + { + base->CTB_CTRL = CY_CTB_DEINIT; + base->OA_RES0_CTRL = CY_CTB_DEINIT; + base->OA_RES1_CTRL = CY_CTB_DEINIT; + base->INTR_MASK = CY_CTB_DEINIT; + + if (deInitRouting) + { + base->OA0_SW_CLEAR = CY_CTB_DEINIT_OA0_SW; + base->OA1_SW_CLEAR = CY_CTB_DEINIT_OA1_SW; + base->CTD_SW_CLEAR = CY_CTB_DEINIT_CTD_SW; + } + + result = CY_CTB_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTB_FastInit +****************************************************************************//** +* +* Initializes each Opamp of the CTB to one of the common use modes. +* These provide a quick and easy method of configuring the CTB when using +* the PDL driver for device configuration. Only routing switches required for +* the selected mode are configured, leaving final input and output connections +* to the user. Additional use modes are provided. These correspond with VDAC +* driver modes to support easy configuration of VDAC output buffer and input +* reference buffer options when used with the VDAC PDL driver. +* +* Other configuration options are set to: +* - .oaPump = CY_CTB_PUMP_ENABLE +* - .oaCompEdge = CY_CTB_COMP_EDGE_BOTH +* - .oaCompLevel = CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE +* - .oaCompBypass = CY_CTB_COMP_BYPASS_SYNC +* - .oaCompHyst = CY_CTB_COMP_HYST_10MV +* - .oaCompIntrEn = true + +* \param base +* Pointer to structure describing registers +* +* \param config0 +* Pointer to structure containing configuration data for quick initialization +* of Opamp0. Use one of the provided structures or define your own. +* - \ref Cy_CTB_Fast_Opamp0_Unused +* - \ref Cy_CTB_Fast_Opamp0_Comp +* - \ref Cy_CTB_Fast_Opamp0_Opamp1x +* - \ref Cy_CTB_Fast_Opamp0_Opamp10x +* - \ref Cy_CTB_Fast_Opamp0_Diffamp +* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out +* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH +* +* \param config1 +* Pointer to structure containing configuration data for quick initialization +* of Opamp1. Use one of the provided structures or define your own. +* - \ref Cy_CTB_Fast_Opamp1_Unused +* - \ref Cy_CTB_Fast_Opamp1_Comp +* - \ref Cy_CTB_Fast_Opamp1_Opamp1x +* - \ref Cy_CTB_Fast_Opamp1_Opamp10x +* - \ref Cy_CTB_Fast_Opamp1_Diffamp +* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref +* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 +* +* \return cy_en_ctb_status_t +* Status of initialization, CY_CTB_SUCCESS or CY_CTB_BAD_PARAM +* +*******************************************************************************/ +cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config_oa0_t *config0, const cy_stc_ctb_fast_config_oa1_t *config1) +{ + CY_ASSERT_L1(NULL != base); + CY_ASSERT_L1(NULL != config0); + CY_ASSERT_L1(NULL != config1); + + cy_en_ctb_status_t result; + + if ((NULL == base) || (NULL == config0) || (NULL == config1)) + { + result = CY_CTB_BAD_PARAM; + } + else + { + /* Enum and boundary checks for config0 */ + CY_ASSERT_L3(CY_CTB_OAPOWER(config0->oa0Power)); + CY_ASSERT_L3(CY_CTB_OAMODE(config0->oa0Mode)); + CY_ASSERT_L2(CY_CTB_OA0SWITCH(config0->oa0SwitchCtrl)); + CY_ASSERT_L2(CY_CTB_CTDSWITCH(config0->ctdSwitchCtrl)); + + /* Enum and boundary checks for config1 */ + CY_ASSERT_L3(CY_CTB_OAPOWER(config1->oa1Power)); + CY_ASSERT_L3(CY_CTB_OAMODE(config1->oa1Mode)); + CY_ASSERT_L2(CY_CTB_OA1SWITCH(config1->oa1SwitchCtrl)); + CY_ASSERT_L2(CY_CTB_CTDSWITCH(config1->ctdSwitchCtrl)); + + base->CTB_CTRL = (uint32_t) CY_CTB_DEEPSLEEP_DISABLE; + + base->OA_RES0_CTRL = (uint32_t) config0->oa0Power \ + | (uint32_t) config0->oa0Mode \ + | (uint32_t) CY_CTB_PUMP_ENABLE \ + | (uint32_t) CY_CTB_COMP_EDGE_BOTH \ + | (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE \ + | (uint32_t) CY_CTB_COMP_BYPASS_SYNC \ + | (uint32_t) CY_CTB_COMP_HYST_10MV \ + | ((CY_CTB_MODE_OPAMP1X == config0->oa0Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); + + base->OA_RES1_CTRL = (uint32_t) config1->oa1Power \ + | (uint32_t) config1->oa1Mode \ + | (uint32_t) CY_CTB_PUMP_ENABLE \ + | (uint32_t) CY_CTB_COMP_EDGE_BOTH \ + | (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE \ + | (uint32_t) CY_CTB_COMP_BYPASS_SYNC \ + | (uint32_t) CY_CTB_COMP_HYST_10MV \ + | ((CY_CTB_MODE_OPAMP1X == config1->oa1Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); + + base->INTR_MASK = CTBM_INTR_MASK_COMP0_MASK_Msk | CTBM_INTR_MASK_COMP1_MASK_Msk; + + base->OA0_COMP_TRIM = (uint32_t) ((config0->oa0Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + base->OA1_COMP_TRIM = (uint32_t) ((config1->oa1Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + + base->OA0_SW = config0->oa0SwitchCtrl; + base->OA1_SW = config1->oa1SwitchCtrl; + base->CTD_SW = config0->ctdSwitchCtrl | config1->ctdSwitchCtrl; + + result = CY_CTB_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetCurrentMode +****************************************************************************//** +* +* High level API function for configuring the current modes of the Opamps. +* This API configures all Opamps of the CTB to the same current mode. +* These modes are differentiated by the IPTAT current level, the Opamp +* input range, and the Deep Sleep mode operation. +* +* - The reference current level is set using \ref Cy_CTB_SetIptatLevel +* - When 1 uA current level is used in Deep Sleep, +* - All generators in the AREF must be enabled in Deep Sleep. That is, +* \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF. +* - When 100 nA current level is used, +* - \ref Cy_CTB_EnableRedirect is called to route the AREF IPTAT reference +* to the Opamp IZTAT and disable the Opamps IPTAT. +* - The IPTAT generator is enabled in Deep Sleep. That is, +* \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_2 +* unless it is already configured for CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF. +* +* Note that the IPTAT level is a chip wide configuration so multiple +* Opamps cannot operate at different IPTAT levels. +* When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device, +* it should be called for all other CTB instances as well. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    Current ModeIPTAT LevelInput RangeDeep Sleep Operation
    CY_CTB_CURRENT_HIGH_ACTIVE1 uARail-to-Rail (charge pump enabled)Disabled in Deep Sleep
    CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP1 uA0 - VDDA-1.5 V (charge pump disabled)Enabled in Deep Sleep
    CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP100 nA0 - VDDA-1.5 V (charge pump disabled)Enabled in Deep Sleep
    +* +* NOTE: The output range of the Opamp is 0.2 V to VDDA-0.2 V (depending on output load). +* +* \param base +* Pointer to structure describing registers +* +* \param currentMode +* Enable or disable CTB in Deep Sleep. +* +* \return None +* +*******************************************************************************/ +void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode) +{ + CY_ASSERT_L3(CY_CTB_CURRENTMODE(currentMode)); + + cy_en_sysanalog_deep_sleep_t arefDeepSleep; + + switch(currentMode) + { + case CY_CTB_CURRENT_HIGH_ACTIVE: + + /* Does not disable AREF for Deep Sleep in case the AREF is used by other blocks */ + + /* Use a 1 uA IPTAT level and disable redirection */ + Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL); + Cy_CTB_DisableRedirect(); + + /* Disable Deep Sleep mode for the CTB - not Opamp specific */ + Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_DISABLE); + + /* Enable Opamp0 pump */ + base->OA_RES0_CTRL |= CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk; + + /* Enable Opamp1 pump */ + base->OA_RES1_CTRL |= CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk; + + break; + case CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP: + + /* All generators (IPTAT, IZTAT, and VREF) of the AREF block must be enabled for Deep Sleep */ + Cy_SysAnalog_SetDeepSleepMode(CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF); + + /* Use a 1 uA IPTAT level and disable redirection */ + Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL); + Cy_CTB_DisableRedirect(); + + /* Enable Deep Sleep mode for the CTB - not Opamp specific */ + Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE); + + /* Disable Opamp0 pump */ + base->OA_RES0_CTRL &= ~CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk; + + /* Disable Opamp1 pump */ + base->OA_RES1_CTRL &= ~CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk; + + break; + case CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP: + default: + + /* The AREF IPTAT output for the Opamps must be enabled in Deep Sleep. + * This means a minimum Deep Sleep mode setting of CY_SYSANALOG_DEEPSLEEP_IPTAT_2. */ + arefDeepSleep = Cy_SysAnalog_GetDeepSleepMode(); + if ((arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_DISABLE) || (arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_IPTAT_1)) + { + Cy_SysAnalog_SetDeepSleepMode(CY_SYSANALOG_DEEPSLEEP_IPTAT_2); + } + + /* Use a 100 nA IPTAT level and enable redirection */ + Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_LOW); + Cy_CTB_EnableRedirect(); + + /* Enable Deep Sleep mode for the CTB - not Opamp specific */ + Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE); + + /* Disable Opamp0 pump */ + base->OA_RES0_CTRL &= ~CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk; + + /* Disable Opamp1 pump */ + base->OA_RES1_CTRL &= ~CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk; + break; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetDeepSleepMode +****************************************************************************//** +* +* Sets whether to allow the CTB to continue to stay powered in Deep Sleep mode. +* +* If enabled, the AREF block must also be enabled for Deep Sleep (see +* \ref Cy_SysAnalog_SetDeepSleepMode). +* Also, if any of the COS, CA0, CHD, CH6, COB, COR, CRS, or CRD switches +* are used in Deep Sleep, the CTDAC must also be enabled for Deep Sleep (see +* \ref Cy_CTDAC_SetDeepSleepMode). +* +* See the \ref group_ctb_dependencies section for more information. +* +* Note that in Deep Sleep mode, the charge pump is disabled so the input +* range is reduced to 0 - VDDA-1.5 V. +* +* \param base +* Pointer to structure describing registers +* +* \param deepSleep +* Enable or disable CTB in Deep Sleep. +* +* \return None +* +*******************************************************************************/ +void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep) +{ + CY_ASSERT_L3(CY_CTB_DEEPSLEEP(deepSleep)); + + uint32_t ctbCtrl; + + ctbCtrl = base->CTB_CTRL & ~CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk; + + base->CTB_CTRL = ctbCtrl | (uint32_t)deepSleep; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetOutputMode +****************************************************************************//** +* +* Sets the Opamp output mode to 1x drive, 10x drive, or comparator mode. +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \param mode +* Opamp mode selection +* +* \return None +* +*******************************************************************************/ +void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_mode_t mode) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum)); + CY_ASSERT_L3(CY_CTB_OAMODE(mode)); + + uint32_t oaCtrlReg; + + if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + + /* Clear the three affected bits before setting them */ + oaCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk | CTBM_OA_RES0_CTRL_OA0_COMP_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk); + base->OA_RES0_CTRL = oaCtrlReg | (uint32_t) mode | ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_BOOST_DISABLE : CY_CTB_OPAMP_BOOST_ENABLE); + base->OA0_COMP_TRIM = (uint32_t) ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + } + + if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + oaCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk | CTBM_OA_RES1_CTRL_OA1_COMP_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Msk); + base->OA_RES1_CTRL = oaCtrlReg | (uint32_t) mode | ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_BOOST_DISABLE : CY_CTB_OPAMP_BOOST_ENABLE); + base->OA1_COMP_TRIM = (uint32_t) ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetPower +****************************************************************************//** +* +* Sets the Opamp power mode to one of three levels to trade off power for +* gain bandwidth. Also enable or disable voltage pump to increase input +* range to supply rails. +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \param power +* Power mode selection +* +* \param pump +* Enable or disable the charge pump for increased input range +* +* \return None +* +*******************************************************************************/ +void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_power_t power, cy_en_ctb_pump_t pump) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum)); + CY_ASSERT_L3(CY_CTB_OAPOWER(power)); + CY_ASSERT_L3(CY_CTB_OAPUMP(pump)); + + uint32_t oaCtrlReg; + + if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + + /* Clear the two affected bits before setting them */ + oaCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Msk | CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk); + base->OA_RES0_CTRL = oaCtrlReg | (uint32_t) power | (uint32_t) pump; + } + + if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + oaCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Msk | CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk); + base->OA_RES1_CTRL = oaCtrlReg | (uint32_t) power | (uint32_t) pump; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_DACSampleAndHold +****************************************************************************//** +* +* Performs sampling and holding of the CTDAC output. +* To perform a sample or a hold, a preparation step must first be executed to +* open the required switches. Because of this, each sample or hold +* requires three function calls: +* +* -# Call this function to prepare for a sample or hold +* -# Enable or disable the CTDAC output +* -# Call this function again to perform a sample or hold +* +* For example, +* +* To sample the CTDAC output voltage: +* -# Cy_CTB_DACSampleAndHold(CTBM0, CY_CTB_SH_PREPARE_SAMPLE); +* -# Cy_CTDAC_SetOutputMode(CTDAC0, CY_CTDAC_OUTPUT_VALUE); +* -# Cy_CTB_DACSampleAndHold(CTBM0, CY_CTB_SH_SAMPLE); +* -# Cy_SysLib_DelayUs(10); +* +* It takes 10 us to perform a sample of the CTDAC output to provide +* time for the capacitor to settle to the new value. +* +* To hold the CTDAC output voltage: +* -# Cy_CTB_DACSampleAndHold(CTBM0, CY_CTB_SH_PREPARE_HOLD); +* -# Cy_CTDAC_SetOutputMode(CTDAC0, CY_CTDAC_OUTPUT_HIGHZ); +* -# Cy_CTB_DACSampleAndHold(CTBM0, CY_CTB_SH_HOLD); +* +* \param base +* Pointer to structure describing registers +* +* \param mode +* Mode to prepare or perform a sample or hold, or disable the ability +* +* \return None +* +*******************************************************************************/ +void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode) +{ + CY_ASSERT_L3(CY_CTB_SAMPLEHOLD(mode)); + + switch(mode) + { + case CY_CTB_SH_DISABLE: + base->CTD_SW_CLEAR = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Open COB switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK /* Open CIS switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK /* Open ILR switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK; /* Open CHD switch */ + base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK; /* Close COS switch */ + break; + case CY_CTB_SH_PREPARE_SAMPLE: + base->CTD_SW_CLEAR = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Open COB switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK /* Open CIS switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK; /* Open ILR switch */ + base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK; /* Close CHD switch */ + break; + case CY_CTB_SH_SAMPLE: + base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK; /* Close COS switch */ + break; + case CY_CTB_SH_PREPARE_HOLD: + base->CTD_SW_CLEAR = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK /* Open COS switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK; /* Open CIS switch */ + break; + case CY_CTB_SH_HOLD: + default: + base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Close COB switch to reduce leakage through COS switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK; /* Close ILR switch to reduce leakage through CIS switch */ + break; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpampSetOffset +****************************************************************************//** +* +* Overrides the CTB opamp offset factory trim. +* The trim is a six bit value and the MSB is a direction bit. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    Bit 5Bits 4:0Note
    000000Negative trim direction - minimum setting
    011111Negative trim direction - maximum setting
    100000Positive trim direction - minimum setting
    111111Positive trim direction - maximum setting
    +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \param trim +* Trim value from 0 to 63 +* +* \return None +* +*******************************************************************************/ +void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum)); + CY_ASSERT_L2(CY_CTB_TRIM(trim)); + + if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA0_OFFSET_TRIM = (trim << CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos) & CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk; + } + + if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA1_OFFSET_TRIM = (trim << CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos) & CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpampGetOffset +****************************************************************************//** +* +* Returns the current CTB Opamp offset trim value. +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* CY_CTB_OPAMP_0 or CY_CTB_OPAMP_1 +* +* \return Offset trim value +* +*******************************************************************************/ +uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(opampNum)); + + uint32_t trimReg; + + if (opampNum == CY_CTB_OPAMP_0) + { + trimReg = base->OA0_OFFSET_TRIM; + } + else + { + trimReg = base->OA1_OFFSET_TRIM; + } + + return trimReg; +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpampSetSlope +****************************************************************************//** +* +* Override the CTB Opamp slope factory trim. +* The offset of the Opamp will vary across temperature. +* This trim compensates for the slope of the offset across temperature. +* This compensation uses a bias current from the Analaog Reference block. +* To disable it, set the trim to 0. +* +* The trim is a six bit value and the MSB is a direction bit. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    Bit 5Bits 4:0Note
    000000Negative trim direction - minimum setting
    011111Negative trim direction - maximum setting
    100000Positive trim direction - minimum setting
    111111Positive trim direction - maximum setting
    +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \param trim +* Trim value from 0 to 63 +* +* \return None +* +*******************************************************************************/ +void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum)); + CY_ASSERT_L2(CY_CTB_TRIM(trim)); + + if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA0_SLOPE_OFFSET_TRIM = (trim << CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos) & CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk; + } + + if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA1_SLOPE_OFFSET_TRIM = (trim << CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos) & CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpampGetSlope +****************************************************************************//** +* +* Returns the current CTB Opamp slope trim value. +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* CY_CTB_OPAMP_0 or CY_CTB_OPAMP_1 +* +* \return Slope trim value +* +*******************************************************************************/ +uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(opampNum)); + + uint32_t trimReg; + + if (opampNum == CY_CTB_OPAMP_0) + { + trimReg = base->OA0_SLOPE_OFFSET_TRIM; + } + else + { + trimReg = base->OA1_SLOPE_OFFSET_TRIM; + } + + return trimReg; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetAnalogSwitch +****************************************************************************//** +* +* Provides firmware control of the CTB switches. Each call to this function +* can open a set of switches or close a set of switches in one register. +* +* \param base +* Pointer to structure describing registers +* +* \param switchSelect +* A value of the enum \ref cy_en_ctb_switch_register_sel_t to select the switch +* register +* +* \param switchMask +* The mask of the switches to either open or close. +* The switch masks can be found in the following enums: \ref cy_en_ctb_oa0_switches_t, +* \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t. +* +* \param state +* CY_CTB_SWITCH_OPEN or CY_CTB_SWITCH_CLOSE +* +* For example, to route the non-inverting input of opamp0 to Pin 0 of the CTB port, +* and the inverting input of opamp0 to Pin 1: +* switchSelect = CY_CTB_SWITCH_OA0_SW; +* switchMask = CY_CTB_SW_OA0_POS_PIN0_MASK | CY_CTB_SW_OA0_NEG_PIN1_MASK; +* state = CY_CTB_SWITCH_CLOSE; +* +* \return None +* +*******************************************************************************/ +void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state) +{ + CY_ASSERT_L3(CY_CTB_SWITCHSELECT(switchSelect)); + CY_ASSERT_L2(CY_CTB_SWITCHMASK(switchSelect, switchMask)); + CY_ASSERT_L3(CY_CTB_SWITCHSTATE(state)); + + __IOM uint32_t *switchReg; + __IOM uint32_t *switchClearReg; + + switch(switchSelect) + { + case CY_CTB_SWITCH_OA0_SW: + switchReg = &base->OA0_SW; + switchClearReg = &base->OA0_SW_CLEAR; + break; + case CY_CTB_SWITCH_OA1_SW: + switchReg = &base->OA1_SW; + switchClearReg = &base->OA1_SW_CLEAR; + break; + case CY_CTB_SWITCH_CTD_SW: + default: + switchReg = &base->CTD_SW; + switchClearReg = &base->CTD_SW_CLEAR; + break; + } + + switch(state) + { + case CY_CTB_SWITCH_CLOSE: + *switchReg = switchMask; + break; + case CY_CTB_SWITCH_OPEN: + default: + *switchClearReg = switchMask; + break; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_GetAnalogSwitch +****************************************************************************//** +* +* Returns the open or closed state of the specified analog switch. +* +* \param base +* Pointer to structure describing registers +* +* \param switchSelect +* A value of the enum \ref cy_en_ctb_switch_register_sel_t to select the switch +* register +* +* \return uint32_t +* Compare this value to the switch masks in the following enums: +* \ref cy_en_ctb_oa0_switches_t, \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t. +* +*******************************************************************************/ +uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect) +{ + CY_ASSERT_L3(CY_CTB_SWITCHSELECT(switchSelect)); + + uint32_t switchRegValue; + + switch(switchSelect) + { + case CY_CTB_SWITCH_OA0_SW: + switchRegValue = base->OA0_SW; + break; + case CY_CTB_SWITCH_OA1_SW: + switchRegValue = base->OA1_SW; + break; + case CY_CTB_SWITCH_CTD_SW: + default: + switchRegValue = base->CTD_SW; + break; + } + + return switchRegValue; +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpenAllSwitches +****************************************************************************//** +* +* Open all the switches and disable all hardware control of the switches. +* Primarily used as a quick method of reconfiguring all analog connections +* that are sparsely closed. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +void Cy_CTB_OpenAllSwitches(CTBM_Type *base) +{ + base->OA0_SW_CLEAR = CY_CTB_DEINIT_OA0_SW; + base->OA1_SW_CLEAR = CY_CTB_DEINIT_OA1_SW; + base->CTD_SW_CLEAR = CY_CTB_DEINIT_CTD_SW; + base->CTB_SW_DS_CTRL = CY_CTB_DEINIT; + base->CTB_SW_SQ_CTRL = CY_CTB_DEINIT; +} + +/******************************************************************************* +* Function Name: Cy_CTB_CompSetConfig +****************************************************************************//** +* +* Configures the CTB comparator for pulse or level output, to bypass clock +* synchronization, and to enable hysteresis. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \param level +* Configure output to produce a pulse or level output signal + +* \param bypass +* Configure output to be clock synchronized or unsynchronized + +* \param hyst +* Enable or disable input hysteresis + +* \return None +* +*******************************************************************************/ +void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_bypass_t bypass, cy_en_ctb_comp_hyst_t hyst) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + CY_ASSERT_L3(CY_CTB_COMPLEVEL(level)); + CY_ASSERT_L3(CY_CTB_COMPBYPASS(bypass)); + CY_ASSERT_L3(CY_CTB_COMPHYST(hyst)); + + uint32_t opampCtrlReg; + + if ((compNum == CY_CTB_OPAMP_0) || (compNum == CY_CTB_OPAMP_BOTH)) + { + opampCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk); + base->OA_RES0_CTRL = opampCtrlReg | (uint32_t) level |(uint32_t) bypass | (uint32_t) hyst; + } + + if ((compNum == CY_CTB_OPAMP_1) || (compNum == CY_CTB_OPAMP_BOTH)) + { + opampCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk); + base->OA_RES1_CTRL = opampCtrlReg | (uint32_t) level |(uint32_t) bypass | (uint32_t) hyst; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_CompGetConfig +****************************************************************************//** +* +* Returns the CTB comparator operating configuration. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* CY_CTB_OPAMP_0 or CY_CTB_OPAMP_1 +* +* \return comparator status +* Compare the register value with the masks in \ref cy_en_ctb_comp_level_t, +* \ref cy_en_ctb_comp_bypass_t, and \ref cy_en_ctb_comp_hyst_t. +* +*******************************************************************************/ +uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(compNum)); + + uint32_t config; + + if (compNum == CY_CTB_OPAMP_0) + { + config = base->OA_RES0_CTRL & (CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk); + } + else + { + config = base->OA_RES1_CTRL & (CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk); + } + + return config; +} + +/******************************************************************************* +* Function Name: Cy_CTB_CompSetInterruptEdgeType +****************************************************************************//** +* +* Configures the type of edge that will trigger a comparator interrupt. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \param edge +* Edge type +* +* \return None +* +*******************************************************************************/ +void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + CY_ASSERT_L3(CY_CTB_COMPEDGE(edge)); + + uint32_t opampCtrlReg; + + if ((compNum == CY_CTB_OPAMP_0) || (compNum == CY_CTB_OPAMP_BOTH)) + { + opampCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_COMPINT_Msk); + base->OA_RES0_CTRL = opampCtrlReg | (uint32_t) edge; + } + + if ((compNum == CY_CTB_OPAMP_1) || (compNum == CY_CTB_OPAMP_BOTH)) + { + opampCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_COMPINT_Msk); + base->OA_RES1_CTRL = opampCtrlReg | (uint32_t) edge; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_CompGetStatus +****************************************************************************//** +* +* Returns status of the indicated comparator output. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* CY_CTB_OPAMP_0 or CY_CTB_OPAMP_1 +* +* \return comparator status +* 0 - Comparator output low +* 1 - Comparator output high +* +* A value of 0 is returned if compNum is an invalid value, CY_CTB_OPAMP_NONE +* or CY_CTB_OPAMP_BOTH. +* +*******************************************************************************/ +uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(compNum)); + + uint32_t compStatusResult; + + if (CY_CTB_OPAMP_0 == compNum) + { + compStatusResult = (base->COMP_STAT & CTBM_COMP_STAT_OA0_COMP_Msk) >> CTBM_COMP_STAT_OA0_COMP_Pos; + } + else if (CY_CTB_OPAMP_1 == compNum) + { + compStatusResult = (base->COMP_STAT & CTBM_COMP_STAT_OA1_COMP_Msk) >> CTBM_COMP_STAT_OA1_COMP_Pos; + } + else + { + compStatusResult = 0uL; + } + + return compStatusResult; +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctb/cy_ctb.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctb/cy_ctb.h new file mode 100644 index 0000000000..4e8903d590 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctb/cy_ctb.h @@ -0,0 +1,1334 @@ +/***************************************************************************//** +* \file cy_ctb.h +* \version 1.0 +* +* Header file for the CTB driver +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_ctb Continuous Time Block (CTB) +* \{ +* This driver provides API functions to configure and use the analog CTB. +* The CTB comprises two identical Opamps, a switch routing matrix, +* and a sample and hold circuit. The high level features are: +* +* - Two highly configurable Opamps +* - Each Opamp has programmable power and output drive strength +* - Each Opamp can be configured as a voltage follower using internal routing +* - Each Opamp can be configured as a comparator with optional 10 mV hysteresis +* - Flexible input and output routing +* - Works as a buffer or amplifier for SAR ADC inputs +* - Works as a buffer, amplifier, or sample-and-hold for the CTDAC output +* - Can operate in Deep Sleep power mode +* +* Each Opamp, marked OA0 and OA1, has one input and three output stages, +* all of which share the common input stage. +* Note that only one output stage can be selected at a time. +* The output stage can operate as a low-drive strength Opamp (1X), a high-drive strength +* Opamp (10X), or a comparator. +* +* The input range of the Opamp can be rail-to-rail if the charge pump is enabled. +* Without the charge pump, the input range is 0 - VDDA-1.5 V. The output range +* of the Opamp is 0.2 V to VDDA-0.2 V, but this depends on the load. See the +* device datasheet for more detail. +* +* Using the switching matrix, the Opamp inputs and outputs +* can be connected to dedicated general-purpose I/Os or other internal analog +* blocks. See the device datasheet for the dedicated CTB port. +* +* \image html ctb_block_diagram.png +* \image latex ctb_block_diagram.png +* +* \section group_ctb_init Initialization +* +* Before enabling the CTB, set up any external components (such as resistors) +* that are needed for the design. To configure the entire hardware block, call \ref Cy_CTB_Init. +* The base address of the CTB hardware can be found in the device specific header file. +* Alternatively, to configure only one opamp without any routing, call \ref Cy_CTB_OpampInit. +* The driver also provides a \ref Cy_CTB_FastInit function for fast and easy initialization of the CTB +* based on commonly used configurations. They are pre-defined in the driver as: +* +* Opamp0 +* - \ref Cy_CTB_Fast_Opamp0_Unused +* - \ref Cy_CTB_Fast_Opamp0_Comp +* - \ref Cy_CTB_Fast_Opamp0_Opamp1x +* - \ref Cy_CTB_Fast_Opamp0_Opamp10x +* - \ref Cy_CTB_Fast_Opamp0_Diffamp +* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out +* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH +* +* Opamp1 +* - \ref Cy_CTB_Fast_Opamp1_Unused +* - \ref Cy_CTB_Fast_Opamp1_Comp +* - \ref Cy_CTB_Fast_Opamp1_Opamp1x +* - \ref Cy_CTB_Fast_Opamp1_Opamp10x +* - \ref Cy_CTB_Fast_Opamp1_Diffamp +* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref +* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 +* +* After initialization, call \ref Cy_CTB_Enable to enable the hardware. +* +* \section group_ctb_comparator Comparator Mode +* +* Each Opamp can be configured as a comparator. Note that when used as a +* comparator, the hardware shuts down the 1X and 10X output drivers. +* Specific to the comparator mode, there is an optional 10 mV input hysteresis +* and configurable edge detection interrupt handling. +* The comparator output is connected to an edge detector +* block, which is used to detect the edge (rising, falling, both, or disabled) +* for interrupt generation. +* +* \section group_ctb_sample_hold Sample and Hold Mode +* +* The CTB has a sample and hold (S/H) circuit at the non-inverting input of Opamp0. +* The circuit includes a hold capacitor, Chold, with a firmware controlled switch, CHD. +* Sampling and holding the source voltage is performed +* by closing and opening appropriate switches in the CTB using firmware. +* If the S/H circuit is used for the CTDAC, the \ref Cy_CTB_DACSampleAndHold function +* should be called. +* +* \image html ctb_fast_config_vdac_sh.png +* \image latex ctb_fast_config_vdac_sh.png +* +* \section group_ctb_dependencies Configuration Dependencies +* +* The CTB relies on other blocks to function properly. The dependencies +* are documented here. +* +*Charge Pump Configuration +* +* Each Opamp of the CTB has a charge pump that when enabled increases the +* input range to the supply rails. When disabled, the Opamp input range is 0 - VDDA - 1.5 V. +* When enabled, the pump requires a clock. +* Call the \ref Cy_CTB_SetClkPumpSource function in the \ref group_sysanalog driver to +* set the clock source for all CTBs. This clock can come from one of two sources: +* +* -# A dedicated clock divider from one of the CLK_PATH in the SRSS +* +* Call the following functions to configure the pump clock from the SRSS: +* - \ref Cy_SysClk_ClkPumpSetSource +* - \ref Cy_SysClk_ClkPumpSetDivider +* - \ref Cy_SysClk_ClkPumpEnable +* -# One of the Peri Clock dividers +* +* Call the following functions to configure a Peri Clock divider as the +* pump clock: +* - \ref Cy_SysClk_PeriphAssignDivider with the IP block set to PCLK_PASS_CLOCK_PUMP_PERI +* - \ref Cy_SysClk_PeriphSetDivider +* - \ref Cy_SysClk_PeriphEnableDivider +* +* When the charge pump is enabled, the clock frequency should be set as follows: +* +* +* +* +* +* +* +* +* +* +* +*
    Opamp PowerPump Clock Freq
    Low or Medium8 - 24 MHz
    High24 MHz
    +* +* The High power level of the Opamp requires a 24 MHz pump clock. +* In Deep Sleep mode, all high frequency clocks are +* disabled and the charge pump will be disabled. +* +* Note that the same pump clock is used by all Opamps on the device. Be aware of this +* when configuring different Opamps to different power levels. +* +* Reference Current Configurations +* +* The CTB uses two reference current generators, IPTAT and IZTAT, from +* the AREF block (see \ref group_sysanalog driver). The IPTAT current is +* used to trim the slope of the Opamp offset across temperature. +* The AREF must be initialized and enabled for the CTB to function properly. +* +* If the CTB is configured to operate in Deep Sleep mode, +* the appropriate reference current generators from the AREF block must be enabled in Deep Sleep. +* When waking up from Deep Sleep, +* the AREF block has a wakeup time that must be +* considered. Note that configurations in the AREF block +* are chip wide and affect all CTBs on the device. +* +* The following reference current configurations are supported: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    Reference Current LevelSupported ModeInput Range
    1 uAActive/Low PowerRail-to-Rail (charge pump enabled)
    1 uAActive/Low Power/Deep Sleep0 - VDDA-1.5 V (charge pump disabled)
    100 nAActive/Low Power/Deep Sleep0 - VDDA-1.5 V (charge pump disabled)
    +* +* The first configuration provides low offset and drift with maximum input range +* while consuming the most current. +* For Deep Sleep operation, use the other two configurations with the charge pump disabled. +* For ultra low power, use the 100 nA current level. +* To configure the Opamps to operate in one of these options, call \ref Cy_CTB_SetCurrentMode. +* +* Sample and Hold Switch Control +* +* The following eight switches that are contained in the CTB are enabled by the CTDAC IP +* block: +* +* - COS, CA0, CHD, CH6, COB, COR, CRS and CRD +* +* If any of the above switches are used, the \ref Cy_CTDAC_Enable function must be called. +* Additionally, if any of the switches are used in Deep Sleep mode, the CTDAC must also +* be configured to operate in Deep Sleep (see \ref Cy_CTDAC_SetDeepSleepMode). +* +* \section group_ctb_code_example Complete Code Example +* +* The following example code demonstrates how to configure Opamp0 +* as a comparator and Opamp1 as a voltage follower. The terminals +* are routed to external pins by closing the switches shown. +* +* \image html ctb_code_example.png +* \image latex ctb_code_example.png +* +* The example code also shows how to handle the comparator interrupt. +* +* \code +* #include "ctb/cy_ctb.h" +* #include "sysanalog/cy_sysanalog.h" +* #include "sysint/cy_sysint.h" +* #include "gpio/cy_gpio.h" +* \endcode +* +* \snippet ctb_sut_01.cydsn/main_cm0p.c CTB_CODE_EXAMPLE +* +* \section group_ctb_more_information More Information +* +* Refer to technical reference manual (TRM) and the device datasheet. +* +* \section group_ctb_MISRA MISRA-C Compliance] +* +* This driver does not have any specific deviations. +* +* \section group_ctb_changelog Changelog +* +* +* +* +* +* +* +*
    VersionChangesReason for Change
    1.0Initial version
    +* +* \defgroup group_ctb_macros Macros +* \defgroup group_ctb_functions Functions +* \{ +* \defgroup group_ctb_functions_init Initialization Functions +* \defgroup group_ctb_functions_basic Basic Configuration Functions +* \defgroup group_ctb_functions_comparator Comparator Functions +* \defgroup group_ctb_functions_sample_hold Sample and Hold Functions +* \defgroup group_ctb_functions_interrupts Interrupt Functions +* \defgroup group_ctb_functions_switches Switch Control Functions +* \defgroup group_ctb_functions_trim Offset and Slope Trim Functions +* \defgroup group_ctb_functions_aref Reference Current Mode Functions +* \} +* \defgroup group_ctb_globals Global Variables +* \defgroup group_ctb_data_structures Data structures +* \defgroup group_ctb_enums Enumerated Types +*/ + +#if !defined(CY_CTB_H) +#define CY_CTB_H + +#include +#include +#include +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" +#include "sysanalog/cy_sysanalog.h" + +#ifndef CY_IP_MXS40PASS_CTB + #error "The CTB driver is not supported on this device" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_ctb_macros +* \{ +*/ + +/** Driver major version */ +#define CY_CTB_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_CTB_DRV_VERSION_MINOR 0 + +/** CTB driver identifier*/ +#define CY_CTB_ID CY_PDL_DRV_ID(0x0Bu) + +/** \cond INTERNAL */ + +/**< De-init value for most CTB registers */ +#define CY_CTB_DEINIT (0uL) + +/**< De-init value for the opamp0 switch control register */ +#define CY_CTB_DEINIT_OA0_SW (CTBM_OA0_SW_CLEAR_OA0P_A00_Msk \ + | CTBM_OA0_SW_CLEAR_OA0P_A20_Msk \ + | CTBM_OA0_SW_CLEAR_OA0P_A30_Msk \ + | CTBM_OA0_SW_CLEAR_OA0M_A11_Msk \ + | CTBM_OA0_SW_CLEAR_OA0M_A81_Msk \ + | CTBM_OA0_SW_CLEAR_OA0O_D51_Msk \ + | CTBM_OA0_SW_CLEAR_OA0O_D81_Msk) + +/**< De-init value for the opamp1 switch control register */ +#define CY_CTB_DEINIT_OA1_SW (CTBM_OA1_SW_CLEAR_OA1P_A03_Msk \ + | CTBM_OA1_SW_CLEAR_OA1P_A13_Msk \ + | CTBM_OA1_SW_CLEAR_OA1P_A43_Msk \ + | CTBM_OA1_SW_CLEAR_OA1P_A73_Msk \ + | CTBM_OA1_SW_CLEAR_OA1M_A22_Msk \ + | CTBM_OA1_SW_CLEAR_OA1M_A82_Msk \ + | CTBM_OA1_SW_CLEAR_OA1O_D52_Msk \ + | CTBM_OA1_SW_CLEAR_OA1O_D62_Msk \ + | CTBM_OA1_SW_CLEAR_OA1O_D82_Msk) + +/**< De-init value for the CTDAC switch control register */ +#define CY_CTB_DEINIT_CTD_SW (CTBM_CTD_SW_CLEAR_CTDD_CRD_Msk \ + | CTBM_CTD_SW_CLEAR_CTDS_CRS_Msk \ + | CTBM_CTD_SW_CLEAR_CTDS_COR_Msk \ + | CTBM_CTD_SW_CLEAR_CTDO_C6H_Msk \ + | CTBM_CTD_SW_CLEAR_CTDO_COS_Msk \ + | CTBM_CTD_SW_CLEAR_CTDH_COB_Msk \ + | CTBM_CTD_SW_CLEAR_CTDH_CHD_Msk \ + | CTBM_CTD_SW_CLEAR_CTDH_CA0_Msk \ + | CTBM_CTD_SW_CLEAR_CTDH_CIS_Msk \ + | CTBM_CTD_SW_CLEAR_CTDH_ILR_Msk) + +#define CY_CTB_TRIM_VALUE_MAX (63uL) + +/**< Macros for conditions used by CY_ASSERT calls */ + +#define CY_CTB_OPAMPNUM(num) (((num) == CY_CTB_OPAMP_0) || ((num) == CY_CTB_OPAMP_1) || ((num) == CY_CTB_OPAMP_BOTH)) +#define CY_CTB_OPAMPNUM_0_1(num) (((num) == CY_CTB_OPAMP_0) || ((num) == CY_CTB_OPAMP_1)) +#define CY_CTB_OPAMPNUM_ALL(num) (((num) == CY_CTB_OPAMP_NONE) \ + || ((num) == CY_CTB_OPAMP_0) \ + || ((num) == CY_CTB_OPAMP_1) \ + || ((num) == CY_CTB_OPAMP_BOTH)) +#define CY_CTB_IPTAT(iptat) (((iptat) == CY_CTB_IPTAT_NORMAL) || ((iptat) == CY_CTB_IPTAT_LOW)) +#define CY_CTB_CLKPUMP(clkPump) (((clkPump) == CY_CTB_CLK_PUMP_SRSS) || ((clkPump) == CY_CTB_CLK_PUMP_PERI)) +#define CY_CTB_DEEPSLEEP(deepSleep) (((deepSleep) == CY_CTB_DEEPSLEEP_DISABLE) || ((deepSleep) == CY_CTB_DEEPSLEEP_ENABLE)) +#define CY_CTB_OAPOWER(power) ((power) <= CY_CTB_POWER_HIGH) +#define CY_CTB_OAMODE(mode) (((mode) == CY_CTB_MODE_OPAMP1X) \ + || ((mode) == CY_CTB_MODE_OPAMP10X) \ + || ((mode) == CY_CTB_MODE_COMP)) +#define CY_CTB_OAPUMP(pump) (((pump) == CY_CTB_PUMP_DISABLE) || ((pump) == CY_CTB_PUMP_ENABLE)) +#define CY_CTB_COMPEDGE(edge) (((edge) == CY_CTB_COMP_EDGE_DISABLE) \ + || ((edge) == CY_CTB_COMP_EDGE_RISING) \ + || ((edge) == CY_CTB_COMP_EDGE_FALLING) \ + || ((edge) == CY_CTB_COMP_EDGE_BOTH)) +#define CY_CTB_COMPLEVEL(level) (((level) == CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE) || ((level) == CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL)) +#define CY_CTB_COMPBYPASS(bypass) (((bypass) == CY_CTB_COMP_BYPASS_SYNC) || ((bypass) == CY_CTB_COMP_BYPASS_NO_SYNC)) +#define CY_CTB_COMPHYST(hyst) (((hyst) == CY_CTB_COMP_HYST_DISABLE) || ((hyst) == CY_CTB_COMP_HYST_10MV)) +#define CY_CTB_CURRENTMODE(mode) (((mode) == CY_CTB_CURRENT_HIGH_ACTIVE) \ + || ((mode) == CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP) \ + || ((mode) == CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP)) +#define CY_CTB_SAMPLEHOLD(mode) ((mode) <= CY_CTB_SH_HOLD) +#define CY_CTB_TRIM(trim) ((trim) <= CY_CTB_TRIM_VALUE_MAX) +#define CY_CTB_SWITCHSELECT(select) (((select) == CY_CTB_SWITCH_OA0_SW) \ + || ((select) == CY_CTB_SWITCH_OA1_SW) \ + || ((select) == CY_CTB_SWITCH_CTD_SW)) +#define CY_CTB_SWITCHSTATE(state) (((state) == CY_CTB_SWITCH_OPEN) || ((state) == CY_CTB_SWITCH_CLOSE)) +#define CY_CTB_OA0SWITCH(mask) (((mask) & (~CY_CTB_DEINIT_OA0_SW)) == 0uL) +#define CY_CTB_OA1SWITCH(mask) (((mask) & (~CY_CTB_DEINIT_OA1_SW)) == 0uL) +#define CY_CTB_CTDSWITCH(mask) (((mask) & (~CY_CTB_DEINIT_CTD_SW)) == 0uL) +#define CY_CTB_SWITCHMASK(select,mask) (((select) == CY_CTB_SWITCH_OA0_SW) ? (((mask) & (~CY_CTB_DEINIT_OA0_SW)) == 0uL) : \ + (((select) == CY_CTB_SWITCH_OA1_SW) ? (((mask) & (~CY_CTB_DEINIT_OA1_SW)) == 0uL) : \ + (((mask) & (~CY_CTB_DEINIT_CTD_SW)) == 0uL))) + +/** \endcond */ + +/** \} group_ctb_macros */ + +/*************************************** +* Enumerated Types +***************************************/ + +/** +* \addtogroup group_ctb_enums +* \{ +*/ + +/** +* Most functions allow you to configure a single opamp or both opamps at once. +* The \ref Cy_CTB_SetInterruptMask function can be called with CY_CTB_OPAMP_NONE +* and interrupts will be disabled. +*/ +typedef enum{ + CY_CTB_OPAMP_NONE = 0, /**< For disabling interrupts for both opamps. Used with \ref Cy_CTB_SetInterruptMask */ + CY_CTB_OPAMP_0 = CTBM_INTR_COMP0_Msk, /**< For configuring Opamp0 */ + CY_CTB_OPAMP_1 = CTBM_INTR_COMP1_Msk, /**< For configuring Opamp1 */ + CY_CTB_OPAMP_BOTH = CTBM_INTR_COMP0_Msk | CTBM_INTR_COMP1_Msk, /**< For configuring both Opamp0 and Opamp1 */ +}cy_en_ctb_opamp_sel_t; + +/** Enable or disable CTB while in Deep Sleep mode. +*/ +typedef enum { + CY_CTB_DEEPSLEEP_DISABLE = 0u, /**< CTB is disabled during Deep Sleep power mode */ + CY_CTB_DEEPSLEEP_ENABLE = CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk, /**< CTB remains enabled during Deep Sleep power mode */ +}cy_en_ctb_deep_sleep_t; + +/** +* Configure the power mode of each opamp. Each power setting +* consumes different levels of current and supports a different +* input range and gain bandwidth. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    Opamp PowerIDDGain bandwidth
    OFF0NA
    LOW350 uA1 MHz
    MEDIUM600 uA3 MHz for 1X, 2.5 MHz for 10x
    HIGH1.5 mA8 MHz for 1X, 6 MHz for 10x
    +* +*/ +typedef enum { + CY_CTB_POWER_OFF = 0u, /**< Opamp is off */ + CY_CTB_POWER_LOW = 1u, /**< Low power: IDD = 350 uA, GBW = 1 MHz for both 1x and 10x */ + CY_CTB_POWER_MEDIUM = 2u, /**< Medium power: IDD = 600 uA, GBW = 3 MHz for 1x and 2.5 MHz for 10x */ + CY_CTB_POWER_HIGH = 3u, /**< High power: IDD = 1500 uA, GBW = 8 MHz for 1x and 6 MHz for 10x */ +}cy_en_ctb_power_t; + +/** +* The output stage of each Opamp can be configured for low-drive strength (1X) to drive internal circuits, +* for high-drive strength (10X) to drive external circuits, or as a comparator. +*/ +typedef enum { + CY_CTB_MODE_OPAMP1X = 0u, /**< Configure Opamp for low drive strength (1x) */ + CY_CTB_MODE_OPAMP10X = 1u << CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos, /**< Configure Opamp high drive strength (10x) */ + CY_CTB_MODE_COMP = 1u << CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos, /**< Configure Opamp as a comparator */ +}cy_en_ctb_mode_t; + +/** +* Each Opamp has a charge pump to increase the input range to the rails. +* When the charge pump is enabled, the input range is 0 to VDDA. +* When disabled, the input range is 0 to VDDA - 1.5 V. +* +** +* +* +* +* +* +* +* +* +* +*
    Charge PumpInput Range (V)
    OFF0 to VDDA-1.5
    ON0 to VDDA
    +* +* Note that in Deep Sleep mode, the charge pump is disabled so the input +* range is reduced. +*/ +typedef enum{ + CY_CTB_PUMP_DISABLE = 0u, /**< Charge pump is disabled for an input range of 0 to VDDA - 1.5 V */ + CY_CTB_PUMP_ENABLE = CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk, /**< Charge pump is enabled for an input range of 0 to VDDA */ +}cy_en_ctb_pump_t; + +/** +* Configure the type of edge that will trigger a comparator interrupt or +* disable the interrupt entirely. +*/ +typedef enum +{ + CY_CTB_COMP_EDGE_DISABLE = 0u, /**< Disabled, no interrupts generated */ + CY_CTB_COMP_EDGE_RISING = 1u << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Rising edge generates an interrupt */ + CY_CTB_COMP_EDGE_FALLING = 2u << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Falling edge generates an interrupt */ + CY_CTB_COMP_EDGE_BOTH = 3u << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Both edges generate an interrupt */ +}cy_en_ctb_comp_edge_t; + +/** Configure the comparator DSI trigger output level when output is synchronized. */ +typedef enum +{ + CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE = 0u, /**< Send pulse on DSI for each edge of comparator output */ + CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL = CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk, /**< DSI output is synchronized version of comparator output */ +}cy_en_ctb_comp_level_t; + +/** Bypass the comparator output synchronization for DSI trigger. */ +typedef enum +{ + CY_CTB_COMP_BYPASS_SYNC = 0u, /**< Comparator output is synchronized for DSI trigger */ + CY_CTB_COMP_BYPASS_NO_SYNC = CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk, /**< Comparator output is not synchronized for DSI trigger */ +}cy_en_ctb_comp_bypass_t; + +/** Disable or enable the 10 mV hysteresis for the comparator. */ +typedef enum +{ + CY_CTB_COMP_HYST_DISABLE = 0u, /**< Disable hysteresis */ + CY_CTB_COMP_HYST_10MV = CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk, /**< Enable the 10 mV hysteresis */ +}cy_en_ctb_comp_hyst_t; + +/** Switch state, either open or closed, to be used in \ref Cy_CTB_SetAnalogSwitch. */ +typedef enum +{ + CY_CTB_SWITCH_OPEN = 0uL, /**< Open the switch */ + CY_CTB_SWITCH_CLOSE = 1uL /**< Close the switch */ +}cy_en_ctb_switch_state_t; + +/** +* The switch register to be used in \ref Cy_CTB_SetAnalogSwitch. +* The CTB has three registers for configuring the switch routing matrix. +* */ +typedef enum +{ + CY_CTB_SWITCH_OA0_SW = 0u, /**< Switch register for Opamp0 */ + CY_CTB_SWITCH_OA1_SW = 1u, /**< Switch register for Opamp1 */ + CY_CTB_SWITCH_CTD_SW = 2u, /**< Switch register for CTDAC routing */ +}cy_en_ctb_switch_register_sel_t; + +/** +* Switch masks for Opamp0 to be used in \ref Cy_CTB_SetAnalogSwitch. +*/ +typedef enum +{ + CY_CTB_SW_OA0_POS_AMUXBUSA_MASK = CTBM_OA0_SW_OA0P_A00_Msk, /**< Switch A00: Opamp0 non-inverting input to AMUXBUS A */ + CY_CTB_SW_OA0_POS_PIN0_MASK = CTBM_OA0_SW_OA0P_A20_Msk, /**< Switch A20: Opamp0 non-inverting input to Pin 0 of CTB device port */ + CY_CTB_SW_OA0_POS_PIN6_MASK = CTBM_OA0_SW_OA0P_A30_Msk, /**< Switch A30: Opamp0 non-inverting input to Pin 6 of CTB device port */ + CY_CTB_SW_OA0_NEG_PIN1_MASK = CTBM_OA0_SW_OA0M_A11_Msk, /**< Switch A11: Opamp0 inverting input to Pin 1 of CTB device port */ + CY_CTB_SW_OA0_NEG_OUT_MASK = CTBM_OA0_SW_OA0M_A81_Msk, /**< Switch A81: Opamp0 inverting input to Opamp0 output */ + CY_CTB_SW_OA0_OUT_SARBUS0_MASK = CTBM_OA0_SW_OA0O_D51_Msk, /**< Switch D51: Opamp0 output to sarbus0 */ + CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK = CTBM_OA0_SW_OA0O_D81_Msk, /**< Switch D81: Short Opamp0 1x with 10x outputs */ +}cy_en_ctb_oa0_switches_t; + +/** +* Switch masks for Opamp1 to be used in \ref Cy_CTB_SetAnalogSwitch. +*/ +typedef enum +{ + CY_CTB_SW_OA1_POS_AMUXBUSB_MASK = CTBM_OA1_SW_OA1P_A03_Msk, /**< Switch A03: Opamp1 non-inverting input to AMUXBUS B */ + CY_CTB_SW_OA1_POS_PIN5_MASK = CTBM_OA1_SW_OA1P_A13_Msk, /**< Switch A13: Opamp1 non-inverting input to Pin 5 of CTB device port */ + CY_CTB_SW_OA1_POS_PIN7_MASK = CTBM_OA1_SW_OA1P_A43_Msk, /**< Switch A43: Opamp1 non-inverting input to Pin 7 of CTB device port */ + CY_CTB_SW_OA1_POS_AREF_MASK = CTBM_OA1_SW_OA1P_A73_Msk, /**< Switch A73: Opamp1 non-inverting input to device Analog Reference (AREF) */ + CY_CTB_SW_OA1_NEG_PIN4_MASK = CTBM_OA1_SW_OA1M_A22_Msk, /**< Switch A22: Opamp1 inverting input to Pin 4 of CTB device port */ + CY_CTB_SW_OA1_NEG_OUT_MASK = CTBM_OA1_SW_OA1M_A82_Msk, /**< switch A82: Opamp1 inverting input to Opamp1 output */ + CY_CTB_SW_OA1_OUT_SARBUS0_MASK = CTBM_OA1_SW_OA1O_D52_Msk, /**< Switch D52: Opamp1 output to sarbus0 */ + CY_CTB_SW_OA1_OUT_SARBUS1_MASK = CTBM_OA1_SW_OA1O_D62_Msk, /**< Switch D62: Opamp1 output to sarbus1 */ + CY_CTB_SW_OA1_OUT_SHORT_1X_10X_MASK = CTBM_OA1_SW_OA1O_D82_Msk, /**< Switch D82: Short Opamp1 1x with 10x outputs */ +}cy_en_ctb_oa1_switches_t; + +/** +* Switch masks for CTDAC routing to be used in \ref Cy_CTB_SetAnalogSwitch. +* +* Eight of the 10 switches are enabled by the CTDAC IP block. That is, +* \ref Cy_CTDAC_Enable must also be called to close these switches. +* The CTDAC output should be high-z in order to not interfere with the CTB. +* +* The two switches that do not require the CTDAC are: +* - CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK (switch CIS) +* - CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK (switch ILR) +*/ +typedef enum +{ + CY_CTB_SW_CTD_REF_OA1_OUT_MASK = CTBM_CTD_SW_CTDD_CRD_Msk, /**< Switch CRD: Opamp1 output to CTDAC reference. CTDAC must be enabled */ + CY_CTB_SW_CTD_REFSENSE_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_CRS_Msk, /**< Switch CRS: CTDAC reference sense to Opamp1 inverting input. CTDAC must be enabled */ + CY_CTB_SW_CTD_OUT_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_COR_Msk, /**< Switch COR: CTDAC output to Opamp1 inverting input. CTDAC must be enabled */ + CY_CTB_SW_CTD_OUT_PIN6_MASK = CTBM_CTD_SW_CTDO_C6H_Msk, /**< Switch C6H: CTDAC output to P6 of CTB device port. CTDAC must be enabled */ + CY_CTB_SW_CTD_OUT_CHOLD_MASK = CTBM_CTD_SW_CTDO_COS_Msk, /**< Switch COS: CTDAC output to hold cap (deglitch capable). CTDAC must be enabled */ + CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK = CTBM_CTD_SW_CTDH_COB_Msk, /**< Switch COB: Drive CTDAC output with opamp0 1x output during hold mode. CTDAC must be enabled */ + CY_CTB_SW_CTD_CHOLD_CONNECT_MASK = CTBM_CTD_SW_CTDH_CHD_Msk, /**< Switch CHD: Hold cap connection. CTDAC must be enabled */ + CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK = CTBM_CTD_SW_CTDH_CA0_Msk, /**< Switch CA0: Hold cap to Opamp0 non-inverting input. CTDAC must be enabled */ + CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK = CTBM_CTD_SW_CTDH_CIS_Msk, /**< Switch CIS: Opamp0 non-inverting input isolation (for hold cap) */ + CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK = CTBM_CTD_SW_CTDH_ILR_Msk, /**< Switch ILR: Hold cap leakage reduction (drives far side of isolation switch CIS) */ +}cy_en_ctb_ctd_switches_t; + +/** +* Each Opamp also has a programmable compensation capacitor block, +* that optimizes the stability of the Opamp performance based on output load. +* The compensation cap will be set by the driver based on the Opamp drive strength (1x or 10x) selection. +*/ +typedef enum +{ + CY_CTB_OPAMP_COMPENSATION_CAP_OFF = 0u, /**< No compensation */ + CY_CTB_OPAMP_COMPENSATION_CAP_MIN = 1u, /**< Minimum compensation - for 1x drive*/ + CY_CTB_OPAMP_COMPENSATION_CAP_MED = 2u, /**< Medium compensation */ + CY_CTB_OPAMP_COMPENSATION_CAP_MAX = 3u, /**< Maximum compensation - for 10x drive */ +}cy_en_ctb_compensation_cap_t; + +/** Enable or disable the gain booster. +* The gain booster will be set by the driver based on the Opamp drive strength (1x or 10x) selection. +*/ +typedef enum +{ + CY_CTB_OPAMP_BOOST_DISABLE = 0u, /**< Disable gain booster - for 10x drive */ + CY_CTB_OPAMP_BOOST_ENABLE = CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk, /**< Enable gain booster - for 1x drive */ +}cy_en_ctb_boost_en_t; + +/** Sample and hold modes for firmware sampling of the CTDAC output. +* +* To perform a sample or a hold, a preparation step must first be executed to +* open the required switches. +* +* -# Call \ref Cy_CTB_DACSampleAndHold with CY_CTB_SH_PREPARE_SAMPLE or CY_CTB_SH_PREPARE_HOLD +* -# Enable or disable CTDAC output +* -# Call \ref Cy_CTB_DACSampleAndHold with CY_CTB_SH_SAMPLE or CY_CTB_SH_HOLD +*/ +typedef enum +{ + CY_CTB_SH_DISABLE = 0u, /**< The hold capacitor is not connected - this disables sample and hold */ + CY_CTB_SH_PREPARE_SAMPLE = 1u, /**< Prepares the required switches for a following sample */ + CY_CTB_SH_SAMPLE = 2u, /**< Performs a sample of the voltage */ + CY_CTB_SH_PREPARE_HOLD = 3u, /**< Prepares the required switches for a following hold */ + CY_CTB_SH_HOLD = 4u, /**< Performs a hold of the previously sampled voltage */ +}cy_en_ctb_sample_hold_mode_t; + +/** AREF IPTAT bias current output for the CTB +* +* The CTB bias current can be 1 uA (normal) or 100 nA (low current). +*/ +typedef enum +{ + CY_CTB_IPTAT_NORMAL = 0u, /**< 1 uA bias current to the CTB */ + CY_CTB_IPTAT_LOW = 1u << PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Pos, /**< 100 nA bias current to the CTB */ +}cy_en_ctb_iptat_t; + +/** CTB charge pump clock sources +* +* The CTB pump clock can come from: +* - a dedicated divider clock in the SRSS +* - one of the CLK_PERI dividers +*/ +typedef enum +{ + CY_CTB_CLK_PUMP_SRSS = 0u, /**< Use the dedicated pump clock from SRSSp */ + CY_CTB_CLK_PUMP_PERI = 1u << PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos, /**< Use one of the CLK_PERI dividers */ +}cy_en_ctb_clk_pump_source_t; + +/** High level opamp current modes */ +typedef enum +{ + CY_CTB_CURRENT_HIGH_ACTIVE = 0u, /**< Uses 1 uA reference current with charge pump enabled. Available in Active and Low Power */ + CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP = 1u, /**< Uses 1 uA reference current with charge pump disabled. Available in all power modes */ + CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP = 2u, /**< Uses 100 nA reference current with charge pump disabled. Available in all power modes */ +}cy_en_ctb_current_mode_t; + +/** Return states for \ref Cy_CTB_Init, \ref Cy_CTB_OpampInit, \ref Cy_CTB_DeInit, and \ref Cy_CTB_FastInit */ +typedef enum { + CY_CTB_SUCCESS = 0x00uL, /**< Initialization completed successfully */ + CY_CTB_BAD_PARAM = CY_CTB_ID | CY_PDL_STATUS_ERROR | 0x01uL, /**< Input pointers were NULL and initialization could not be completed */ +}cy_en_ctb_status_t; + +/** \} group_ctb_enums */ + +/*************************************** +* Configuration Structures +***************************************/ + +/** +* \addtogroup group_ctb_data_structures +* \{ +*/ + +/** +* Configuration structure to set up the entire CTB to be used with \ref Cy_CTB_Init. +*/ +typedef struct { + cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTDAC during Deep Sleep */ + bool enable; /**< Enable hardware after initialization. If disabled, call \ref Cy_CTB_Enable after initialization */ + + /* Opamp0 configuration */ + cy_en_ctb_power_t oa0Power; /**< Opamp0 power mode: off, low, medium, or high */ + cy_en_ctb_mode_t oa0Mode; /**< Opamp0 usage mode: 1x drive, 10x drive, or as a comparator */ + cy_en_ctb_pump_t oa0Pump; /**< Opamp0 charge pump: enable to increase input range for rail-to-rail operation */ + cy_en_ctb_comp_edge_t oa0CompEdge; /**< Opamp0 comparator edge detection: disable, rising, falling, or both */ + cy_en_ctb_comp_level_t oa0CompLevel; /**< Opamp0 comparator DSI (trigger) output: pulse or level */ + cy_en_ctb_comp_bypass_t oa0CompBypass; /**< Opamp0 comparator DSI (trigger) output synchronization */ + cy_en_ctb_comp_hyst_t oa0CompHyst; /**< Opamp0 comparator hysteresis: enable for 10 mV hysteresis */ + bool oa0CompIntrEn; /**< Opamp0 comparator interrupt enable */ + + /* Opamp1 configuration */ + cy_en_ctb_power_t oa1Power; /**< Opamp1 power mode: off, low, medium, or high */ + cy_en_ctb_mode_t oa1Mode; /**< Opamp1 usage mode: 1x drive, 10x drive, or as a comparator */ + cy_en_ctb_pump_t oa1Pump; /**< Opamp1 charge pump: enable to increase input range for rail-to-rail operation */ + cy_en_ctb_comp_edge_t oa1CompEdge; /**< Opamp1 comparator edge detection: disable, rising, falling, or both */ + cy_en_ctb_comp_level_t oa1CompLevel; /**< Opamp1 comparator DSI (trigger) output: pulse or level */ + cy_en_ctb_comp_bypass_t oa1CompBypass; /**< Opamp1 comparator DSI (trigger) output synchronization */ + cy_en_ctb_comp_hyst_t oa1CompHyst; /**< Opamp1 comparator hysteresis: enable for 10 mV hysteresis */ + bool oa1CompIntrEn; /**< Opamp1 comparator interrupt enable */ + + /* Switch analog routing configuration */ + bool configRouting; /**< Configure or ignore routing related registers */ + uint32_t oa0SwitchCtrl; /**< Opamp0 routing control */ + uint32_t oa1SwitchCtrl; /**< Opamp1 routing control */ + uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */ +}cy_stc_ctb_config_t; + +/** +* This configuration structure is used to initialize only one Opamp of the CTB +* without impacting analog routing. This structure is used with \ref Cy_CTB_OpampInit. +*/ +typedef struct { + cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTDAC during Deep Sleep */ + bool enable; /**< Enable hardware after initialization. If disabled, call \ref Cy_CTB_Enable after initialization */ + + /* Opamp configuration */ + cy_en_ctb_power_t oaPower; /**< Opamp power mode: off, low, medium, or high */ + cy_en_ctb_mode_t oaMode; /**< Opamp usage mode: 1x drive, 10x drive, or as a comparator */ + cy_en_ctb_pump_t oaPump; /**< Opamp charge pump: enable to increase input range for rail-to-rail operation */ + cy_en_ctb_comp_edge_t oaCompEdge; /**< Opamp comparator edge detection: disable, rising, falling, or both */ + cy_en_ctb_comp_level_t oaCompLevel; /**< Opamp comparator DSI (trigger) output: pulse or level */ + cy_en_ctb_comp_bypass_t oaCompBypass; /**< Opamp comparator DSI (trigger) output synchronization */ + cy_en_ctb_comp_hyst_t oaCompHyst; /**< Opamp comparator hysteresis: enable for 10 mV hysteresis */ + bool oaCompIntrEn; /**< Opamp comparator interrupt enable */ +}cy_stc_ctb_opamp_config_t; + +/** This configuration structure is used to quickly initialize Opamp0 for the most commonly used configurations. +* +* Other configuration options are set to: +* - .oa0Pump = CY_CTB_PUMP_ENABLE +* - .oa0CompEdge = CY_CTB_COMP_EDGE_BOTH +* - .oa0CompLevel = CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE +* - .oa0CompBypass = CY_CTB_COMP_BYPASS_SYNC +* - .oa0CompHyst = CY_CTB_COMP_HYST_10MV +* - .oa0CompIntrEn = true +*/ +typedef struct +{ + cy_en_ctb_power_t oa0Power; /**< Opamp0 power mode: off, low, medium, or high */ + cy_en_ctb_mode_t oa0Mode; /**< Opamp0 usage mode: 1x drive, 10x drive, or as a comparator */ + uint32_t oa0SwitchCtrl; /**< Opamp0 routing control */ + uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */ +}cy_stc_ctb_fast_config_oa0_t; + +/** This configuration structure is used to quickly initialize Opamp1 for the most commonly used configurations. +* +* Other configuration options are set to: +* - .oa1Pump = CY_CTB_PUMP_ENABLE +* - .oa1CompEdge = CY_CTB_COMP_EDGE_BOTH +* - .oa1CompLevel = CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE +* - .oa1CompBypass = CY_CTB_COMP_BYPASS_SYNC +* - .oa1CompHyst = CY_CTB_COMP_HYST_10MV +* - .oa1CompIntrEn = true +*/ +typedef struct +{ + cy_en_ctb_power_t oa1Power; /**< Opamp1 power mode: off, low, medium, or high */ + cy_en_ctb_mode_t oa1Mode; /**< Opamp1 usage mode: 1x drive, 10x drive, or as a comparator */ + uint32_t oa1SwitchCtrl; /**< Opamp1 routing control */ + uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */ +}cy_stc_ctb_fast_config_oa1_t; + +/** \} group_ctb_data_structures */ + + +/** \addtogroup group_ctb_globals +* \{ +* The \ref Cy_CTB_FastInit function allows for fast and easy initialization of the CTB +* based on commonly used configurations. Only routing switches required for +* the selected mode are configured, leaving final input and output connections +* to the user. Additional use modes are provided to easily configure the CTB as +* an output buffer or reference buffer for the CTDAC. These modes are used +* along with the CTDAC PDL driver. +*/ +/*************************************** +* Global Variables +***************************************/ + +/** Configure Opamp0 as unused - powered down. See \ref Cy_CTB_FastInit. */ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Unused; + +/** Configure Opamp0 as a comparator. No routing is configured. +* +* \image html ctb_fast_config_comp.png +* \image latex ctb_fast_config_comp.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp; + +/** Configure Opamp0 as an Opamp with 1x drive. No routing is configured. +* +* \image html ctb_fast_config_opamp1x.png +* \image latex ctb_fast_config_opamp1x.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x; + +/** Configure Opamp0 as an Opamp with 10x drive. No routing is configured. +* +* \image html ctb_fast_config_opamp10x.png +* \image latex ctb_fast_config_opamp10x.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp10x; + +/** Configure Opamp0 as one stage of a differential amplifier. +* The Opamp is in 10x drive and the switches shown are closed. +* +* \image html ctb_fast_config_oa0_diffamp.png +* \image latex ctb_fast_config_oa0_diffamp.png width=100px +* +* See the device datasheet for the dedicated CTB port. +* +* To be used with \ref Cy_CTB_FastInit and \ref Cy_CTB_Fast_Opamp1_Diffamp. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Diffamp; + +/** Configure Opamp0 as a buffer for the CTDAC output. +* The buffer is in 10x drive and the switches shown are closed. +* Configure the CTDAC for output buffer mode by calling \ref Cy_CTDAC_FastInit +* with \ref Cy_CTDAC_Fast_VddaRef_BufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut. +* +* \image html ctb_fast_config_vdac_output.png +* \image latex ctb_fast_config_vdac_output.png +* +* See the device datasheet for the dedicated CTB port. +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out; + +/** Configure Opamp0 as a buffer for the CTDAC output with the sample and hold capacitor connected. +* The buffer is in 10x drive and the switches shown are closed. +* Configure the CTDAC for output buffer mode by calling \ref Cy_CTDAC_FastInit +* with \ref Cy_CTDAC_Fast_VddaRef_BufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut. + +* \image html ctb_fast_config_vdac_sh.png +* \image latex ctb_fast_config_vdac_sh.png +* +* See the device datasheet for the dedicated CTB port. +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out_SH; + +/** Configure Opamp1 as unused - powered down. See \ref Cy_CTB_FastInit.*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Unused; + +/** Configure Opamp1 as a comparator. No routing is configured. +* +* \image html ctb_fast_config_comp.png +* \image latex ctb_fast_config_comp.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Comp; + +/** Configure Opamp1 as an Opamp with 1x drive. No routing is configured. +* +* \image html ctb_fast_config_opamp1x.png +* \image latex ctb_fast_config_opamp1x.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp1x; + +/** Configure Opamp1 as an opamp with 10x drive. No routing is configured. +* +* \image html ctb_fast_config_opamp10x.png +* \image latex ctb_fast_config_opamp10x.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp10x; + +/** Configure Opamp1 as one stage of a differential amplifier. +* The Opamp is in 10x drive and the switches shown are closed. +* +* \image html ctb_fast_config_oa1_diffamp.png +* \image latex ctb_fast_config_oa1_diffamp.png width=100px +* +* See the device datasheet for the dedicated CTB port. +* +* To be used with \ref Cy_CTB_FastInit and \ref Cy_CTB_Fast_Opamp0_Diffamp. +* +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Diffamp; + +/** Configure Opamp1 as a buffer for the CTDAC reference. The reference comes from the +* internal analog reference block (AREF). +* The buffer is in 1x drive and the switches shown are closed. +* Configure the CTDAC to use the buffered reference by calling \ref Cy_CTDAC_FastInit +* with \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut. +* +* \image html ctb_fast_config_vdac_aref.png +* \image latex ctb_fast_config_vdac_aref.png +* +* See \ref Cy_CTB_FastInit. +* +* Note the AREF block needs to be configured using a separate driver. +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref; + +/** Configure Opamp1 as a buffer for the CTDAC reference. The reference comes from Pin 5. +* The buffer is in 1x drive and the switches shown are closed. +* Configure the CTDAC to use the buffered reference by calling \ref Cy_CTDAC_FastInit +* with \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut. +* +* \image html ctb_fast_config_vdac_pin5.png +* \image latex ctb_fast_config_vdac_pin5.png +* +* See the device datasheet for the dedicated CTB port. +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5; + +/** \} group_ctb_globals */ + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_ctb_functions +* \{ +*/ + +/** +* \addtogroup group_ctb_functions_init +* This set of functions are for initializing, enabling, and disabling the CTB. +* \{ +*/ +cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config); +cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, const cy_stc_ctb_opamp_config_t *config); +cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting); +cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config_oa0_t *config0, const cy_stc_ctb_fast_config_oa1_t *config1); +__STATIC_INLINE void Cy_CTB_Enable(CTBM_Type *base); +__STATIC_INLINE void Cy_CTB_Disable(CTBM_Type *base); +/** \} */ + +/** +* \addtogroup group_ctb_functions_basic +* This set of functions are for configuring basic usage of the CTB. +* \{ +*/ +void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep); +void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_mode_t mode); +void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_power_t power, cy_en_ctb_pump_t pump); +/** \} */ + +/** +* \addtogroup group_ctb_functions_sample_hold +* This function enables sample and hold of the CTDAC output. +* \{ +*/ +void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode); +/** \} */ + +/** +* \addtogroup group_ctb_functions_comparator +* This set of functions are specific to the comparator mode +* \{ +*/ +void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_bypass_t bypass, cy_en_ctb_comp_hyst_t hyst); +uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge); +uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +/** \} */ + +/** +* \addtogroup group_ctb_functions_trim +* These are advanced functions for trimming the offset and slope of the Opamps. +* Most users do not need to call these functions and can use the factory trimmed values. +* \{ +*/ +void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim); +uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum); +void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim); +uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum); +/** \} */ + +/** +* \addtogroup group_ctb_functions_switches +* This set of functions is for controlling routing switches. +* \{ +*/ +void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state); +uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect); +void Cy_CTB_OpenAllSwitches(CTBM_Type *base); +/** \} */ + +/** +* \addtogroup group_ctb_functions_interrupts +* This set of functions is related to the comparator interrupts. +* \{ +*/ +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +__STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +__STATIC_INLINE void Cy_CTB_SetSwInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +__STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +/** \} */ + +/** +* \addtogroup group_ctb_functions_aref +* This set of functions impacts all Opamps on the chip. +* Notice how some of these functions do not take a base address input. +* When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device, +* it should be called for all other CTB instances as well. This is because +* there is only one IPTAT level (1 uA or 100 nA) chip wide. +* \{ +*/ +void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode); +__STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat); +__STATIC_INLINE void Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump); +__STATIC_INLINE void Cy_CTB_EnableRedirect(void); +__STATIC_INLINE void Cy_CTB_DisableRedirect(void); +/** \} */ + +/** +* \addtogroup group_ctb_functions_init +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_CTB_Enable +****************************************************************************//** +* +* Powers up the hardware block necessary for the operation of the CTB. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_Enable(CTBM_Type *base) +{ + base->CTB_CTRL |= CTBM_CTB_CTRL_ENABLED_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTB_Disable +****************************************************************************//** +* +* Powers down the hardware block necessary for the operation of the CTB. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_Disable(CTBM_Type *base) +{ + base->CTB_CTRL &= (~CTBM_CTB_CTRL_ENABLED_Msk); +} + +/** \} */ + +/** +* \addtogroup group_ctb_functions_interrupts +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_CTB_GetInterruptStatus +****************************************************************************//** +* +* Returns status of the interrupt that happens when the configured comparator +* edge is detected. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \return Interrupt status +* 0 - Edge was not detected +* Non-zero - Configured edge type was detected +* +* If compNum is CY_CTB_OPAMP_BOTH, cast the returned status +* to cy_en_ctb_opamp_sel_t to determine which comparator edge (or both) +* was detected. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + + return base->INTR & (uint32_t) compNum; +} + +/******************************************************************************* +* Function Name: Cy_CTB_ClearInterrupt +****************************************************************************//** +* +* Clears the CTB comparator triggered interrupt. +* The interrupt must be cleared with this function so that the hardware +* can set subsequent interrupts and those interrupts can be forwarded +* to the interrupt controller, if enabled. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + + base->INTR = (uint32_t) compNum; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetSwInterrupt +****************************************************************************//** +* +* Forces the CTB interrupt to trigger using software. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_SetSwInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + + base->INTR_SET = (uint32_t) compNum; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetInterruptMask +****************************************************************************//** +* +* Configure the CTB comparator edge interrupt to be forwarded to the +* CPU interrupt controller. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* CY_CTB_OPAMP_NONE, CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* Calling this function with CY_CTB_OPAMP_NONE will disable all +* interrupt requests. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM_ALL(compNum)); + + base->INTR_MASK = (uint32_t) compNum; +} + +/******************************************************************************* +* Function Name: Cy_CTB_GetInterruptMask +****************************************************************************//** +* +* Returns whether the CTB comparator edge interrupt output is +* forwarded to the CPU interrupt controller as configured by +* \ref Cy_CTB_SetInterruptMask. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \return Interrupt mask +* 0 - Interrupt output not forwarded to interrupt controller +* Non-zero - Interrupt output forwarded to interrupt controller +* +* If compNum is CY_CTB_OPAMP_BOTH, cast the returned mask +* to cy_en_ctb_opamp_sel_t to determine which comparator interrupt +* output (or both) is forwarded. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + + return base->INTR_MASK & (uint32_t) compNum; +} + +/******************************************************************************* +* Function Name: Cy_CTB_GetInterruptStatusMasked +****************************************************************************//** +* +* Returns the CTB comparator edge output interrupt state after being masked. +* This is the bitwise AND of \ref Cy_CTB_GetInterruptStatus and \ref Cy_CTB_GetInterruptMask. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* CY_CTB_OPAMP_0, CY_CTB_OPAMP_1, or CY_CTB_OPAMP_BOTH +* +* \return Interrupt masked +* 0 - Edge not detected or not masked +* Non-zero - Configured edge type detected and masked +* +* If compNum is CY_CTB_OPAMP_BOTH, cast the returned value +* to cy_en_ctb_opamp_sel_t to determine which comparator interrupt +* output (or both) is detected and masked. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + + return base->INTR_MASKED & (uint32_t) compNum; +} +/** \} */ + +/** +* \addtogroup group_ctb_functions_aref +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_CTB_SetIptatLevel +****************************************************************************//** +* +* Set the IPTAT level to 1uA or 100nA. The IPTAT generator is used by the CTB +* for slope offset drift. +* +* \param iptat +* Value from enum \ref cy_en_ctb_iptat_t +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat) +{ + CY_ASSERT_L3(CY_CTB_IPTAT(iptat)); + + PASS_AREF->AREF_CTRL = (PASS_AREF->AREF_CTRL & ~PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Msk) | (uint32_t) iptat; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetClkPumpSource +****************************************************************************//** +* +* Set the clock source for the CTB charge pump. The clock can come from: +* - a dedicated divider off of one of the CLK_PATH in the SRSS +* Call the following functions to configure the pump clock from the SRSS: +* - \ref Cy_SysClk_ClkPumpSetSource +* - \ref Cy_SysClk_ClkPumpSetDivider +* - \ref Cy_SysClk_ClkPumpEnable +* - one of the Peri Clock dividers +* Call the following functions to configure a Peri Clock divider as the +* pump clock: +* - \ref Cy_SysClk_PeriphAssignDivider with the IP block set to PCLK_PASS_CLOCK_PUMP_PERI +* - \ref Cy_SysClk_PeriphSetDivider +* - \ref Cy_SysClk_PeriphEnableDivider +* +* \param clkPump +* Value from enum \ref cy_en_ctb_clk_pump_source_t +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump) +{ + CY_ASSERT_L3(CY_CTB_CLKPUMP(clkPump)); + + PASS_AREF->AREF_CTRL = (PASS_AREF->AREF_CTRL & ~PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk) | (uint32_t) clkPump; +} + +/******************************************************************************* +* Function Name: Cy_CTB_EnableRedirect +****************************************************************************//** +* +* Normally, the AREF IZTAT is routed to the CTB IZTAT and the AREF IPTAT +* is routed to the CTB IPTAT: +* +* - CTB.IZTAT = AREF.IZTAT +* - CTB.IPTAT = AREF.IPTAT +* +* However, the AREF IPTAT can be redirected to the CTB IZTAT and the CTB IPTAT +* is off. +* +* - CTB.IZTAT = AREF.IPTAT +* - CTB.IPTAT = HiZ +* +* The redirection applies to all opamps on the device and +* should be used when the IPTAT bias level is set to 100 nA +* (see \ref Cy_CTB_SetIptatLevel). +* +* Without the IPTAT reference, the CTB cannot compensate for the slope of +* the offset across temperature. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_EnableRedirect(void) +{ + PASS_AREF->AREF_CTRL |= PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTB_DisableRedirect +****************************************************************************//** +* +* Disable the redirection of the AREF IPTAT to the CTB IZTAT for all opamps +* on the device as enabled by \ref Cy_CTB_EnableRedirect. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_DisableRedirect(void) +{ + PASS_AREF->AREF_CTRL &= ~(PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk); +} + +/** \} */ + +/** \} group_ctb_functions */ + +#if defined(__cplusplus) +} +#endif + +#endif /** !defined(CY_CTB_H) */ + +/** \} group_ctb */ + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctdac/cy_ctdac.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctdac/cy_ctdac.c new file mode 100644 index 0000000000..796094d797 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctdac/cy_ctdac.c @@ -0,0 +1,656 @@ +/***************************************************************************//** +* \file cy_ctdac.c +* \version 1.0 +* +* Provides the public functions for the API for the CTDAC driver. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ctdac/cy_ctdac.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** Static function to configure the clock */ +static void Cy_CTDAC_ConfigureClock(cy_en_ctdac_update_t updateMode, cy_en_divider_types_t dividerType, + uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue); + +const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_UnbufferedOut = +{ + /*.refSource */ CY_CTDAC_REFSOURCE_VDDA, + /*.outputBuffer */ CY_CTDAC_OUTPUT_UNBUFFERED, +}; + +const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_BufferedOut = +{ + /*.refSource */ CY_CTDAC_REFSOURCE_VDDA, + /*.outputBuffer */ CY_CTDAC_OUTPUT_BUFFERED, +}; + +const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_UnbufferedOut = +{ + /*.refSource */ CY_CTDAC_REFSOURCE_EXTERNAL, + /*.outputBuffer */ CY_CTDAC_OUTPUT_UNBUFFERED, +}; + +const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_BufferedOut = +{ + /*.refSource */ CY_CTDAC_REFSOURCE_EXTERNAL, + /*.outputBuffer */ CY_CTDAC_OUTPUT_BUFFERED, +}; + +/******************************************************************************* +* Function Name: Cy_CTDAC_Init +****************************************************************************//** +* +* Initialize all CTDAC configuration registers +* +* \param base +* Pointer to structure describing registers +* +* \param config +* Pointer to structure containing configuration data +* +* \return cy_en_ctdac_status_t +* Status of initialization, CY_CTDAC_SUCCESS or CY_CTDAC_BAD_PARAM +* +*******************************************************************************/ +cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config) +{ + CY_ASSERT_L1(NULL != base); + CY_ASSERT_L1(NULL != config); + + cy_en_ctdac_status_t result; + uint32_t ctdacCtrl = CY_CTDAC_DEINIT; + uint32_t setSwitch = CY_CTDAC_DEINIT; + uint32_t clearSwitch = CY_CTDAC_DEINIT; + + if ((NULL == base) || (NULL == config)) + { + result = CY_CTDAC_BAD_PARAM; + } + else + { + + CY_ASSERT_L3(CY_CTDAC_REFSOURCE(config->refSource)); + CY_ASSERT_L3(CY_CTDAC_FORMAT(config->formatMode)); + CY_ASSERT_L3(CY_CTDAC_UPDATE(config->updateMode)); + CY_ASSERT_L3(CY_CTDAC_DEGLITCH(config->deglitchMode)); + CY_ASSERT_L3(CY_CTDAC_OUTPUTMODE(config->outputMode)); + CY_ASSERT_L3(CY_CTDAC_OUTPUTBUFFER(config->outputBuffer)); + CY_ASSERT_L3(CY_CTDAC_DEEPSLEEP(config->deepSleep)); + CY_ASSERT_L2(CY_CTDAC_DEGLITCHCYCLES(config->deglitchCycles)); + + /* Handle the deglitch counts */ + ctdacCtrl |= (config->deglitchCycles << CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos) & CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk; + + /* Handle the deglitch mode */ + ctdacCtrl |= (uint32_t)config->deglitchMode; + + /* Handle the update mode */ + if ((config->updateMode == CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE) \ + || (config->updateMode == CY_CTDAC_UPDATE_STROBE_EDGE_SYNC) \ + || (config->updateMode == CY_CTDAC_UPDATE_STROBE_LEVEL)) + { + ctdacCtrl |= CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Msk; + } + + if (config->updateMode == CY_CTDAC_UPDATE_STROBE_LEVEL) + { + ctdacCtrl |= CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Msk; + } + + /* Handle the sign format */ + ctdacCtrl |= (uint32_t)config->formatMode; + + /* Handle the Deep Sleep mode */ + ctdacCtrl |= (uint32_t)config->deepSleep; + + /* Handle the output mode */ + ctdacCtrl |= (uint32_t)config->outputMode; + + /* Handle enable bit */ + ctdacCtrl |= ((uint32_t)config->enable) << CTDAC_CTDAC_CTRL_ENABLED_Pos; + + /* Handle the reference source */ + switch(config->refSource) + { + case CY_CTDAC_REFSOURCE_VDDA: + + /* Close the CVD switch to use Vdda as the reference source */ + setSwitch |= CTDAC_CTDAC_SW_CTDD_CVD_Msk; + break; + case CY_CTDAC_REFSOURCE_EXTERNAL: + default: + clearSwitch |= CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk; + break; + } + + /* Handle the output buffer switch CO6 */ + switch(config->outputBuffer) + { + case CY_CTDAC_OUTPUT_UNBUFFERED: + + /* Close the CO6 switch to send output to a direct pin unbuffered */ + setSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk; + break; + case CY_CTDAC_OUTPUT_BUFFERED: + default: + clearSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk; + break; + } + + base->INTR_MASK = (uint32_t)config->enableInterrupt << CTDAC_INTR_VDAC_EMPTY_Pos; + base->CTDAC_SW = setSwitch; + base->CTDAC_SW_CLEAR = clearSwitch; + base->CTDAC_VAL = (((uint32_t)config->value) << CTDAC_CTDAC_VAL_VALUE_Pos) & CTDAC_CTDAC_VAL_VALUE_Msk; + base->CTDAC_VAL_NXT = (((uint32_t)config->nextValue) << CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk; + + if (config->configClock) + { + Cy_CTDAC_ConfigureClock(config->updateMode, config->dividerType, config->dividerNum, config->dividerIntValue, config->dividerFracValue); + } + + base->CTDAC_CTRL = ctdacCtrl; + result = CY_CTDAC_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_DeInit +****************************************************************************//** +* +* Reset CTDAC registers back to power on reset defaults. +* +* Does not disable or configure the clock. Call \ref Cy_CTDAC_Init or \ref Cy_CTDAC_FastInit +* to configure the CTDAC and clock. +* +* \param base +* Pointer to structure describing registers +* +* \param deInitRouting +* If true, all switches are reset to their default state. +* If false, switch registers are untouched. +* +* \return cy_en_ctdac_status_t +* Status of initialization, CY_CTDAC_SUCCESS, or CY_CTDAC_BAD_PARAM +* +*******************************************************************************/ +cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting) +{ + CY_ASSERT_L1(NULL != base); + + cy_en_ctdac_status_t result; + + if (NULL == base) + { + result = CY_CTDAC_BAD_PARAM; + } + else + { + base->CTDAC_CTRL = CY_CTDAC_DEINIT; + base->INTR_MASK = CY_CTDAC_DEINIT; + base->CTDAC_VAL = CY_CTDAC_DEINIT; + base->CTDAC_VAL_NXT = CY_CTDAC_DEINIT; + + if (deInitRouting) + { + base->CTDAC_SW_CLEAR = CY_CTDAC_DEINIT; + } + + result = CY_CTDAC_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_FastInit +****************************************************************************//** +* +* Initializes the CTDAC to one of the common use modes. +* These provide a quick and easy method of configuring the CTDAC when using +* the PDL driver for device configuration. +* +* The other configuration options are set to: +* - .formatMode = CY_CTDAC_FORMAT_UNSIGNED +* - .updateMode = CY_CTDAC_UPDATE_BUFFERED_WRITE +* - .deglitchMode = CY_CTDAC_DEGLITCHMODE_NONE +* - .outputMode = CY_CTDAC_OUTPUT_VALUE +* - .deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE +* - .deglitchCycles = CY_CTDAC_DEINIT +* - .value = CY_CTDAC_UNSIGNED_MID_CODE_VALUE +* - .nextValue = CY_CTDAC_UNSIGNED_MID_CODE_VALUE +* - .enableInterrupt = true +* - .configClock = true +* - .dividerType = CY_CTDAC_FAST_CLKCFG_TYPE +* - .dividerNum = CY_CTDAC_FAST_CLKCFG_NUM +* - .dividerInitValue = CY_CTDAC_FAST_CLKCFG_DIV +* - .dividerFracValue = CY_CTDAC_DEINIT +* +* \param base +* Pointer to structure describing registers +* +* \param config +* Pointer to structure containing configuration data for quick initialization +* Use one of the provided structures or define your own. +* - \ref Cy_CTDAC_Fast_VddaRef_UnbufferedOut +* - \ref Cy_CTDAC_Fast_VddaRef_BufferedOut +* - \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut +* - \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut +* +* \return cy_en_ctdac_status_t +* Status of initialization, CY_CTDAC_SUCCESS or CY_CTDAC_BAD_PARAM +* +*******************************************************************************/ +cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast_config_t *config) +{ + CY_ASSERT_L1(NULL != base); + CY_ASSERT_L1(NULL != config); + + cy_en_ctdac_status_t result; + uint32_t ctdacCtrl; + uint32_t setSwitch = CY_CTDAC_DEINIT; + uint32_t clearSwitch = CY_CTDAC_DEINIT; + + if ((NULL == base) || (NULL == config)) + { + result = CY_CTDAC_BAD_PARAM; + } + else + { + CY_ASSERT_L3(CY_CTDAC_REFSOURCE(config->refSource)); + CY_ASSERT_L3(CY_CTDAC_OUTPUTBUFFER(config->outputBuffer)); + + ctdacCtrl = (uint32_t) CY_CTDAC_DEGLITCHMODE_NONE \ + | (uint32_t) CY_CTDAC_UPDATE_BUFFERED_WRITE \ + | (uint32_t) CY_CTDAC_FORMAT_UNSIGNED \ + | (uint32_t) CY_CTDAC_DEEPSLEEP_DISABLE \ + | (uint32_t) CY_CTDAC_OUTPUT_VALUE; + + /* Handle the reference source */ + switch(config->refSource) + { + case CY_CTDAC_REFSOURCE_VDDA: + + /* Close the CVD switch to use Vdda as the reference source */ + setSwitch |= CTDAC_CTDAC_SW_CTDD_CVD_Msk; + break; + case CY_CTDAC_REFSOURCE_EXTERNAL: + default: + clearSwitch |= CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk; + break; + } + + /* Handle the output buffer switch CO6 */ + switch(config->outputBuffer) + { + case CY_CTDAC_OUTPUT_UNBUFFERED: + + /* Close the CO6 switch to send output to a direct pin unbuffered */ + setSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk; + break; + case CY_CTDAC_OUTPUT_BUFFERED: + default: + clearSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk; + break; + } + + base->INTR_MASK = CTDAC_INTR_VDAC_EMPTY_Msk; + base->CTDAC_SW = setSwitch; + base->CTDAC_SW_CLEAR = clearSwitch; + base->CTDAC_VAL = CY_CTDAC_UNSIGNED_MID_CODE_VALUE; + base->CTDAC_VAL_NXT = CY_CTDAC_UNSIGNED_MID_CODE_VALUE; + + /* For fast configuration, the DAC clock is the Peri clock divided by 100 */ + Cy_CTDAC_ConfigureClock(CY_CTDAC_UPDATE_BUFFERED_WRITE, CY_CTDAC_FAST_CLKCFG_TYPE, CY_CTDAC_FAST_CLKCFG_NUM, CY_CTDAC_FAST_CLKCFG_DIV, CY_CTDAC_DEINIT); + + base->CTDAC_CTRL = ctdacCtrl; + result = CY_CTDAC_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_ConfigureClock +****************************************************************************//** +* +* Private function for configuring the CTDAC clock based on the desired +* update mode. This function is called by \ref Cy_CTDAC_Init. +* +* \param updateMode +* Update mode value. See \ref cy_en_ctdac_update_t for values. +* +* \return None +* +*******************************************************************************/ +static void Cy_CTDAC_ConfigureClock(cy_en_ctdac_update_t updateMode, cy_en_divider_types_t dividerType, + uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue) +{ + if (updateMode == CY_CTDAC_UPDATE_DIRECT_WRITE) + { /* In direct mode, there is not a clock */ + } + else if(updateMode == CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE) + { + + /* In this mode, the Peri Clock is divided by 1 to give a constant logic high on the CTDAC clock. */ + (void)Cy_SysClk_PeriphDisableDivider(dividerType, dividerNum); + + (void)Cy_SysClk_PeriphAssignDivider(PCLK_PASS_CLOCK_CTDAC, dividerType, dividerNum); + + if ((dividerType == CY_SYSCLK_DIV_8_BIT) || (dividerType == CY_SYSCLK_DIV_16_BIT)) + { + (void)Cy_SysClk_PeriphSetDivider(dividerType, dividerNum, CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV); + } + else + { + (void)Cy_SysClk_PeriphSetFracDivider(dividerType, dividerNum, CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV, CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV_FRAC); + } + + (void)Cy_SysClk_PeriphEnableDivider(dividerType, dividerNum); + } + else + { + + /* All other modes, require a CTDAC clock configured to the desired user frequency */ + (void)Cy_SysClk_PeriphDisableDivider(dividerType, dividerNum); + + (void)Cy_SysClk_PeriphAssignDivider(PCLK_PASS_CLOCK_CTDAC, dividerType, dividerNum); + + if ((dividerType == CY_SYSCLK_DIV_8_BIT) || (dividerType == CY_SYSCLK_DIV_16_BIT)) + { + (void)Cy_SysClk_PeriphSetDivider(dividerType, dividerNum, dividerIntValue); + } + else + { + (void)Cy_SysClk_PeriphSetFracDivider(dividerType, dividerNum, dividerIntValue, dividerFracValue); + } + (void)Cy_SysClk_PeriphEnableDivider(dividerType, dividerNum); + } + +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetSignMode +****************************************************************************//** +* +* Sets whether to interpret the DAC value as signed or unsigned. +* In unsigned mode, the DAC value register is used without any decoding. +* In signed mode, the MSB is inverted by adding 0x800 to the DAC value. +* This converts the lowest signed number, 0x800, to the lowest unsigned +* number, 0x000. +* +* \param base +* Pointer to structure describing registers +* +* \param formatMode +* Mode can be signed or unsigned. See \ref cy_en_ctdac_format_t for values. +* +* \return None +* +*******************************************************************************/ +void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode) +{ + CY_ASSERT_L3(CY_CTDAC_FORMAT(formatMode)); + + uint32_t ctdacCtrl; + + /* Clear the CTDAC_MODE bits */ + ctdacCtrl = base->CTDAC_CTRL & ~CTDAC_CTDAC_CTRL_CTDAC_MODE_Msk; + + base->CTDAC_CTRL = ctdacCtrl | (uint32_t)formatMode; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetDeepSleepMode +****************************************************************************//** +* +* Sets whether to allow the DAC hardware to continue to stay powered in +* Deep Sleep mode. +* +* \param base +* Pointer to structure describing registers +* +* \param deepSleep +* Enabled or disabled. See \ref cy_en_ctdac_deep_sleep_t for values. +* +* \return None +* +*******************************************************************************/ +void Cy_CTDAC_SetDeepSleepMode(CTDAC_Type *base, cy_en_ctdac_deep_sleep_t deepSleep) +{ + CY_ASSERT_L3(CY_CTDAC_DEEPSLEEP(deepSleep)); + + uint32_t ctdacCtrl; + + ctdacCtrl = base->CTDAC_CTRL & ~CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk; + + base->CTDAC_CTRL = ctdacCtrl | (uint32_t)deepSleep; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetOutputMode +****************************************************************************//** +* +* Set the output mode to one of the supported options. +* +* \param base +* Pointer to structure describing registers +* +* \param outputMode +* Output drive mode. See \ref cy_en_ctdac_output_mode_t for values. +* +* \return None +* +*******************************************************************************/ +void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMode) +{ + CY_ASSERT_L3(CY_CTDAC_OUTPUTMODE(outputMode)); + + uint32_t ctdacCtrl; + + /* Clear out the three affected bits */ + ctdacCtrl = base->CTDAC_CTRL & ~(CTDAC_CTDAC_CTRL_OUT_EN_Msk | CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk | CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk); + + base->CTDAC_CTRL = ctdacCtrl | (uint32_t)outputMode; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetDeglitchMode +****************************************************************************//** +* +* Set the deglitch mode or disable deglitching completely. +* +* \param base +* Pointer to structure describing registers +* +* \param deglitchMode +* Deglitching mode selection. See \ref cy_en_ctdac_deglitch_t for values. +* +* \return None +* +*******************************************************************************/ +void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchMode) +{ + CY_ASSERT_L3(CY_CTDAC_DEGLITCH(deglitchMode)); + + uint32_t ctdacCtrl; + + /* Clear out DEGLITCH_CO6 and DEGLITCH_C0S bits */ + ctdacCtrl = base->CTDAC_CTRL & ~(CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk | CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk); + + base->CTDAC_CTRL = ctdacCtrl | (uint32_t)deglitchMode; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetDeglitchCycles +****************************************************************************//** +* +* Set the number of deglitch cycles (0 to 63) that will be used. +* To calculate the deglitch time, (DEGLITCH_CNT + 1) / PERI_CLOCK_FREQ. +* The optimal deglitch time is 700 ns. +* +* \param base +* Pointer to structure describing registers +* +* \param deglitchCycles +* Number of cycles to deglitch +* +* \return None +* +*******************************************************************************/ +void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles) +{ + CY_ASSERT_L2(CY_CTDAC_DEGLITCHCYCLES(deglitchCycles)); + + uint32_t ctdacCtrl; + + ctdacCtrl = (base->CTDAC_CTRL) & ~CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk; + + base->CTDAC_CTRL = ctdacCtrl | ((deglitchCycles << CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos) & CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk); +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetRef +****************************************************************************//** +* +* Set the CTDAC reference source to Vdda or an external reference. +* The external reference must come from Opamp1 of the CTB. +* +* \param base +* Pointer to structure describing registers +* +* \param refSource +* The reference source. See \ref cy_en_ctdac_ref_source_t for values. +* +* \return None +* +*******************************************************************************/ +void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource) +{ + CY_ASSERT_L3(CY_CTDAC_REFSOURCE(refSource)); + + switch(refSource) + { + case CY_CTDAC_REFSOURCE_VDDA: + + /* Close the CVD switch to use Vdda as the reference source */ + base->CTDAC_SW |= CTDAC_CTDAC_SW_CTDD_CVD_Msk; + break; + case CY_CTDAC_REFSOURCE_EXTERNAL: + default: + base->CTDAC_SW_CLEAR = CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk; + break; + } +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetAnalogSwitch +****************************************************************************//** +* +* Provides firmware control of the CTDAC switches. Each call to this function +* can open a set of switches or close a set of switches. +* +* This is an advanced function. The switches will be managed by the reference +* source and output mode selections when initializing the hardware. +* +* \param base +* Pointer to structure describing registers +* +* \param switchMask +* The mask of the switches to either open or close. +* The switches can be found in the \ref cy_en_ctdac_switches_t enum. +* +* For example, to close both CVD and CO6 switches: +* switchMask = CY_CTDAC_SWITCH_CVD_MASK | CY_CTDAC_SWITCH_CO6_MASK; +* +* \param state +* Open or close the switches, see enum \ref cy_en_ctdac_switch_state_t. +* +* \return None +* +*******************************************************************************/ +void Cy_CTDAC_SetAnalogSwitch(CTDAC_Type *base, uint32_t switchMask, cy_en_ctdac_switch_state_t state) +{ + CY_ASSERT_L2(CY_CTDAC_SWITCHMASK(switchMask)); + CY_ASSERT_L3(CY_CTDAC_SWITCHSTATE(state)); + + switch(state) + { + case CY_CTDAC_SWITCH_CLOSE: + base->CTDAC_SW |= switchMask; + break; + case CY_CTDAC_SWITCH_OPEN: + default: + + /* Unlike the close case, do not OR the register. Set 1 to clear.*/ + base->CTDAC_SW_CLEAR = switchMask; + break; + } +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_DeepSleepCallback +****************************************************************************//** +* +* Callback to prepare the CTDAC before entering and after exiting Deep Sleep +* mode. If deglitching is used, it is disabled before entering Deep Sleep +* to ensure the deglitch switches are closed. This is needed only +* if the CTDAC will be enabled in DeepSleep. Upon wakeup, deglitching will +* be re-enabled if it was previously used. +* +* \param callbackParams +* Pointer to structure of type \ref cy_stc_syspm_callback_params_t +* +* \return cy_en_syspm_status_t +* See \ref cy_en_syspm_status_t +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams) +{ + /** Static variable preserved between function calls. + * Tracks the state of the deglitch mode before sleep so that it can be re-enabled after wakeup */ + static uint32_t deglitchModeBeforeSleep; + + cy_en_syspm_status_t returnValue = CY_SYSPM_SUCCESS; + + CTDAC_Type *ctdacBase = (CTDAC_Type *)callbackParams->base; + + if (CY_SYSPM_BEFORE_TRANSITION == callbackParams->mode) + { /* Actions that should be done before entering the Deep Sleep mode */ + + /* Store the state of the deglitch switches before turning deglitch off */ + deglitchModeBeforeSleep = ctdacBase->CTDAC_CTRL & (CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk | CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk); + + /* Turn deglitch off before entering Deep Sleep */ + ctdacBase->CTDAC_CTRL &= ~(CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk | CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk); + } + else if (CY_SYSPM_AFTER_TRANSITION == callbackParams->mode) + { /* Actions that should be done after exiting the Deep Sleep mode */ + + /* Re-enable the deglitch mode that was configured before Deep Sleep entry */ + ctdacBase->CTDAC_CTRL |= deglitchModeBeforeSleep; + } + else + { /* Does nothing in other modes */ + } + + return returnValue; +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctdac/cy_ctdac.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctdac/cy_ctdac.h new file mode 100644 index 0000000000..09ad23cc3a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ctdac/cy_ctdac.h @@ -0,0 +1,891 @@ +/***************************************************************************//** +* \file cy_ctdac.h +* \version 1.0 +* +* Header file for the CTDAC driver +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_ctdac Continuous Time Digital to Analog Converter (CTDAC) +* \{ +* The CTDAC driver provides APIs to configure the 12-bit Continuous-Time DAC. +* The CTDAC generates a 12-bit DAC output voltage from the reference. +* The DAC reference can come from VDDA or from any signal buffered through Opamp0 +* of the CTB. This can be an external signal through a GPIO or from the internal +* AREF. The CTDAC is closely integrated with the CTB block, +* which provides easy buffering of the DAC output voltage, +* buffered input reference voltage, and sample and hold for the DAC output. +* The CTDAC control interface provides control of the DAC output through CPU or DMA. +* This includes a double-buffered DAC voltage control register, clock input for programmable +* update rate, interrupt on DAC buffer empty, and trigger to DMA. +* +* \image html ctdac_block_diagram.png +* \image latex ctdac_block_diagram.png +* +* Features +* +* - 12-bit continuous time output +* - 2 us settling time for a 25 pF load +* - Can be enabled in Deep Sleep power mode +* - Selectable voltage reference: +* - VDDA +* - Internal analog reference buffered through Opamp1 of CTB +* - External reference buffered through Opamp1 of CTB +* - Selectable output paths: +* - Direct DAC output to a pin +* - Buffered DAC output through Opamp0 of CTB +* - Sample and hold output path through Opamp0 of CTB +* - Selectable input modes: +* - Unsigned 12-bit mode +* - Virtual signed 12-bit mode +* - Configurable update rate using clock or strobe signal +* - Double buffered DAC voltage control register +* - Interrupt and DMA trigger on DAC buffer empty +* - Configurable as PGA along with Opamp1 of the CTB +* +* The CTDAC has two switches, CO6 for configuring the output path and +* CVD for the reference source. +* +* \image html ctdac_switches.png +* \image latex ctdac_switches.png +* +* \section group_ctdac_init Initialization +* +* Configure the CTDAC hardware block by calling \ref Cy_CTDAC_Init. +* The base address of the CTDAC hardware can be found in the device-specific header file. +* If the buffers in the CTB are used for the reference source or the output, +* initialize the CTB hardware block. After both blocks are initialized, +* enable the CTB block before enabling the CTDAC block. +* +* The driver also provides a \ref Cy_CTDAC_FastInit function for fast and easy initialization of the CTDAC. +* There are four configurations that cover the four combinations of the reference and output buffers. +* +* - \ref Cy_CTDAC_Fast_VddaRef_UnbufferedOut +* - \ref Cy_CTDAC_Fast_VddaRef_BufferedOut +* - \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut +* - \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut +* +* \section group_ctdac_updatemode Update Modes +* The CTDAC contains two registers: +* -# CTDAC_VAL +* +* For direct firmware writes to update the current DAC value immediately. +* This register is written with \ref Cy_CTDAC_SetValue. +* -# CTDAC_VAL_NXT +* +* For buffered writes that can be configured to update the DAC at a +* selected periodic rate or with a strobe trigger. +* This register is written with \ref Cy_CTDAC_SetValueBuffered. +* +* The update mode is +* selected during initialization with the \ref cy_stc_ctdac_config_t.updateMode. +* Four of these modes require a dedicated clock resource and the driver +* can configure the clock during initialization (see \ref cy_stc_ctdac_config_t). +* +* Three of these modes use a strobe signal through the digital signal interface (DSI). +* This allows control of the buffered update timing from an external source, for example, by another +* chip peripheral or from an off-chip source. +* +* Direct write +* +* In this mode, this user writes directly into the CTDAC_VAL register +* using \ref Cy_CTDAC_SetValue. The action of writing to this register +* will update the DAC output. This mode does not generate an interrupt +* or trigger signal. +* In this mode, a clock must not be configured. Additionally, calling \ref +* Cy_CTDAC_SetValueBuffered does not update the DAC output. +* +* \image html ctdac_update_mode_direct_write.png +* \image latex ctdac_update_mode_direct_write.png +* +* Buffered write +* +* In this mode, the user writes to the CTDAC_VAL_NXT register using +* \ref Cy_CTDAC_SetValueBuffered. The rising edge of the clock +* will update the DAC output and generate the interrupt and trigger signals. +* +* Whenever data is transferred from the CTDAC_VAL_NXT register, +* an interrupt is asserted the same time as the trigger. But while +* the trigger is automatically cleared after two Peri Clock cycles, the +* user must clear the interrupt with \ref Cy_CTDAC_ClearInterrupt. +* +* \image html ctdac_update_mode_buffered_write.png +* \image latex ctdac_update_mode_buffered_write.png +* +* Strobe edge sync +* +* In this mode, the user writes to the CTDAC_VAL_NXT register using +* \ref Cy_CTDAC_SetValueBuffered. +* Each rising edge of the DSI strobe input enables +* one subsequent update from the next rising edge of the clock. The DSI +* input must remain high for two Peri Clock cycles and go low for +* another two Peri Clock cycles to allow for the next update. +* This restricts the DSI strobe input frequency to the PeriClk frequency divided by four. +* +* \image html ctdac_update_mode_strobe_edge_sync.png +* \image latex ctdac_update_mode_strobe_edge_sync.png +* +* Strobe edge immediate +* +* In this mode, the user writes to the CTDAC_VAL_NXT register using +* \ref Cy_CTDAC_SetValueBuffered. +* The clock resource is used but set to a logic high. +* Therefore, each rising edge of the DSI strobe input immediately +* updates the DAC output. +* +* \image html ctdac_update_mode_strobe_edge_immediate.png +* \image latex ctdac_update_mode_strobe_edge_immediate.png +* +* Strobe level +* +* In this mode, the user writes to the CTDAC_VAL_NXT register using +* \ref Cy_CTDAC_SetValueBuffered. +* The DSI strobe input acts as a hardware enable signal. +* While the DSI strobe input is high, the mode behaves +* like the Buffered write mode. When the DSI strobe input is low, +* updates are disabled. +* +* \image html ctdac_update_mode_strobe_level.png +* \image latex ctdac_update_mode_strobe_level.png +* +* \section group_ctdac_trigger DMA Trigger +* When data is transferred from the CTDAC_VAL_NXT to the CTDAC_VAL register +* an interrupt and an output trigger signal are generated. +* The trigger signal can be routed to DMA using the \ref group_trigmux. +* When making the required \ref Cy_TrigMux_Connect calls, use the pre-defined enums, TRIG14_IN_PASS_TR_CTDAC_EMPTY +* and TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY. For example, +* +* \code +* (void)Cy_TrigMux_Connect(TRIG14_IN_PASS_TR_CTDAC_EMPTY, TRIG14_OUT_TR_GROUP0_INPUT50, CY_TR_MUX_TR_INV_DISABLE, TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY); +* (void)Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT7, TRIG0_OUT_CPUSS_DW0_TR_IN1, CY_TR_MUX_TR_INV_DISABLE, TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL); +* \endcode +* +* \section group_ctdac_code_example Complete Code Example +* +* The following example code demonstrates how to generate a continuous +* sine wave using the CTDAC. The CTDAC uses both Opamps of the CTB +* to buffer the analog reference and to buffer the output to an external Pin 2. +* +* \image html ctdac_code_example.png +* \image latex ctdac_code_example.png +* +* \code +* #include "ctdac/cy_ctdac.h" +* #include "ctb/cy_ctb.h" +* #include "sysanalog/cy_sysanalog.h" +* #include "sysint/cy_sysint.h" +* \endcode +* +* \snippet ctdac_sut_01.cydsn/main_cm0p.c CTDAC_CODE_EXAMPLE +* +* \section group_ctdac_more_information More Information +* +* Refer to the technical reference manual (TRM) and the device datasheet. +* +* \section group_ctdac_MISRA MISRA-C Compliance] +* +* This driver has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
    11.4AdvisoryA cast should not be performed between a pointer to object type and a different pointer to object type.The cy_syspm driver defines the pointer to void in the \ref cy_stc_syspm_callback_params_t.base field. +* This CTDAC driver implements a Deep Sleep callback conforming to the cy_syspm driver requirements. +* When the callback is called, the base is cast to a pointer to CTDAC_Type. +*
    +* +* \section group_ctdac_changelog Changelog +* +* +* +* +* +* +* +*
    VersionChangesReason for Change
    1.0Initial version
    +* +* \defgroup group_ctdac_macros Macros +* \defgroup group_ctdac_functions Functions +* \{ +* \defgroup group_ctdac_functions_switches Switch Control Functions +* \defgroup group_ctdac_functions_interrupts Interrupt Functions +* \defgroup group_ctdac_functions_syspm_callback SysPm Deep Sleep Callback +* \} +* \defgroup group_ctdac_globals Global Variables +* \defgroup group_ctdac_data_structures Data structures +* \defgroup group_ctdac_enums Enumerated Types +*/ + +#if !defined(CY_CTDAC_H) +#define CY_CTDAC_H + +#include +#include +#include +#include "cy_device_headers.h" +#include "syspm/cy_syspm.h" +#include "syslib/cy_syslib.h" +#include "sysclk/cy_sysclk.h" + +#ifndef CY_IP_MXS40PASS_CTDAC + #error "The CTDAC driver is not supported on this device" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_ctdac_macros +* \{ +*/ + +/** Driver major version */ +#define CY_CTDAC_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_CTDAC_DRV_VERSION_MINOR 0 + +/** CTDAC driver identifier */ +#define CY_CTDAC_ID CY_PDL_DRV_ID(0x19u) + +/** \cond INTERNAL */ +#define CY_CTDAC_DEINIT (0uL) /**< De-init value for CTDAC registers */ +#define CY_CTDAC_DEINT_CTDAC_SW (CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk | CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Msk) /**< Mask for de-initializing the CTDAC switch control register */ +#define CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV (0uL) /**< Clock divider value for the Strobe Edge Immediate update mode */ +#define CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV_FRAC (0uL) /**< Clock fractional divider value for the Strobe Edge Immediate update mode */ +#define CY_CTDAC_FAST_CLKCFG_TYPE CY_SYSCLK_DIV_8_BIT /**< Clock divider type for quick clock setup */ +#define CY_CTDAC_FAST_CLKCFG_NUM (0uL) /**< Clock divider number for quick clock setup */ +#define CY_CTDAC_FAST_CLKCFG_DIV (99uL) /**< Clock divider integer value for quick clock setup. Divides PERI clock by 100. */ +#define CY_CTDAC_UNSIGNED_MID_CODE_VALUE (0x800uL) /**< Middle code value for unsigned values */ +#define CY_CTDAC_UNSIGNED_MAX_CODE_VALUE (0xFFFuL) /**< Maximum code value for unsigned values */ +#define CY_CTDAC_DEGLITCH_CYCLES_MAX (63uL) + +/**< Macros for conditions used by CY_ASSERT calls */ +#define CY_CTDAC_REFSOURCE(source) (((source) == CY_CTDAC_REFSOURCE_EXTERNAL) || ((source) == CY_CTDAC_REFSOURCE_VDDA)) +#define CY_CTDAC_FORMAT(mode) (((mode) == CY_CTDAC_FORMAT_UNSIGNED) || ((mode) == CY_CTDAC_FORMAT_SIGNED)) +#define CY_CTDAC_UPDATE(mode) ((mode) <= CY_CTDAC_UPDATE_STROBE_LEVEL) +#define CY_CTDAC_DEGLITCH(mode) (((mode) == CY_CTDAC_DEGLITCHMODE_NONE) \ + || ((mode) == CY_CTDAC_DEGLITCHMODE_UNBUFFERED) \ + || ((mode) == CY_CTDAC_DEGLITCHMODE_BUFFERED) \ + || ((mode) == CY_CTDAC_DEGLITCHMODE_BOTH)) +#define CY_CTDAC_OUTPUTMODE(mode) (((mode) == CY_CTDAC_OUTPUT_HIGHZ) \ + || ((mode) == CY_CTDAC_OUTPUT_VALUE) \ + || ((mode) == CY_CTDAC_OUTPUT_VALUE_PLUS1) \ + || ((mode) == CY_CTDAC_OUTPUT_VSSA) \ + || ((mode) == CY_CTDAC_OUTPUT_VREF)) +#define CY_CTDAC_OUTPUTBUFFER(buffer) (((buffer) == CY_CTDAC_OUTPUT_UNBUFFERED) || ((buffer) == CY_CTDAC_OUTPUT_BUFFERED)) +#define CY_CTDAC_DEEPSLEEP(deepSleep) (((deepSleep) == CY_CTDAC_DEEPSLEEP_DISABLE) || ((deepSleep) == CY_CTDAC_DEEPSLEEP_ENABLE)) +#define CY_CTDAC_DEGLITCHCYCLES(cycles) ((cycles) <= CY_CTDAC_DEGLITCH_CYCLES_MAX) +#define CY_CTDAC_SWITCHMASK(mask) ((mask) <= (uint32_t) (CY_CTDAC_SWITCH_CVD_MASK | CY_CTDAC_SWITCH_CO6_MASK)) +#define CY_CTDAC_SWITCHSTATE(state) (((state) == CY_CTDAC_SWITCH_OPEN) || ((state) == CY_CTDAC_SWITCH_CLOSE)) +#define CY_CTDAC_INTRMASK(mask) (((mask) == 0uL) || ((mask) == 1uL)) +/** \endcond */ + +/** \} group_ctdac_macros */ + +/*************************************** +* Enumerated Types +***************************************/ + +/** +* \addtogroup group_ctdac_enums +* \{ +*/ + +/** +* Configure the mode for how the DAC value is updated. +* All the modes require a CTDAC clock except for CY_CTDAC_UPDATE_DIRECT_WRITE. +*/ +typedef enum { + CY_CTDAC_UPDATE_DIRECT_WRITE = 0uL, /**< DAC value is updated with a direct write by calling to \ref Cy_CTDAC_SetValue */ + CY_CTDAC_UPDATE_BUFFERED_WRITE = 1uL, /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on the next CTDAC clock edge */ + CY_CTDAC_UPDATE_STROBE_EDGE_SYNC = 2uL, /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on the next CTDAC clock edge after a rising edge of the strobe */ + CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE = 3uL, /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on the rising edge of the strobe input */ + CY_CTDAC_UPDATE_STROBE_LEVEL = 4uL /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on every CTDAC clock edge while the strobe line is high */ +}cy_en_ctdac_update_t; + +/** +* Configure the format in which the DAC value register is decoded. +*/ +typedef enum { + CY_CTDAC_FORMAT_UNSIGNED = 0uL, /**< Unsigned 12-bit DAC. No value decoding */ + CY_CTDAC_FORMAT_SIGNED = 1uL << CTDAC_CTDAC_CTRL_CTDAC_MODE_Pos /**< Virtual signed. Add 0x800 to the 12-bit DAC value */ +}cy_en_ctdac_format_t; + +/** +* Enable or disable the CTDAC hardware during Deep Sleep. +*/ +typedef enum { + CY_CTDAC_DEEPSLEEP_DISABLE = 0uL, /**< DAC is disabled during Deep Sleep power mode */ + CY_CTDAC_DEEPSLEEP_ENABLE = CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk /**< DAC remains enabled during Deep Sleep power mode */ +}cy_en_ctdac_deep_sleep_t; + +/** +* Configure the output state of the CTDAC. +*/ +typedef enum { + CY_CTDAC_OUTPUT_HIGHZ = 0uL, /**< DAC output is tri-state */ + CY_CTDAC_OUTPUT_VALUE = CTDAC_CTDAC_CTRL_OUT_EN_Msk, /**< DAC Output is enabled and drives the programmed value */ + CY_CTDAC_OUTPUT_VALUE_PLUS1 = CTDAC_CTDAC_CTRL_OUT_EN_Msk \ + | CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk, /**< DAC Output enabled and drives the programmed value plus 1 */ + CY_CTDAC_OUTPUT_VSSA = CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk, /**< Output is pulled to Vssa through a 1.1 MOhm (typ) resistor */ + CY_CTDAC_OUTPUT_VREF = CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk \ + | CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk /**< Output is pulled to Vref through a 1.1 MOhm (typ) resistor */ +}cy_en_ctdac_output_mode_t; + +/** +* The CTDAC provides an option to deglitch the output value every time it is updated. +* This prevents small glitches in the DAC output during an update to propagate to +* the pin or Opamp input. When deglitch is enabled, a switch on the output path +* is forced open for a configurable number of Peri Clock cycles. To calculate the deglitch +* time, (DEGLITCH_CNT + 1) / PERI_CLOCK_FREQ. +* +* There are two switches used for deglitching. +* - Switch COS in the CTB between the DAC output and the Opamp0 input +* - Switch CO6 in the CTDAC between the DAC output and external pin +* +* Match the deglitch path with the output buffer selection. +* If the output is buffered through the CTB, select CY_CTDAC_DEGLITCHMODE_BUFFERED. +* If the output is unbuffered to a direct pin, select CY_CTDAC_DEGLITCHMODE_UNBUFFERED. +*/ +typedef enum { + CY_CTDAC_DEGLITCHMODE_NONE = 0uL, /**< Disable deglitch */ + CY_CTDAC_DEGLITCHMODE_UNBUFFERED = CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk, /**< Deglitch through the CO6 switch */ + CY_CTDAC_DEGLITCHMODE_BUFFERED = CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk, /**< Deglitch through the CTB COS switch */ + CY_CTDAC_DEGLITCHMODE_BOTH = CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk \ + | CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk /**< Deglitch through both CO6 and CTB COS switches */ +}cy_en_ctdac_deglitch_t; + +/** +* Configure the reference source for the CTDAC +* +* The CVD switch is closed when Vdda is the reference source. +*/ +typedef enum { + CY_CTDAC_REFSOURCE_EXTERNAL = 0uL, /**< Use an external source as the reference. CVD switch is open. */ + CY_CTDAC_REFSOURCE_VDDA = 1uL /**< Use Vdda as the reference. CVD switch is closed. */ +}cy_en_ctdac_ref_source_t; + +/** Configure the output to be buffered or unbuffered +* +* The CO6 switch is closed when the output is unbuffered to Pin 6 of the CTDAC port. +* See the device datasheet for the CTDAC port. +*/ +typedef enum { + CY_CTDAC_OUTPUT_BUFFERED = 0uL, /**< Buffer the output through the CTB OA0 */ + CY_CTDAC_OUTPUT_UNBUFFERED = 1uL /**< Send output to a direct pin */ +}cy_en_ctdac_output_buffer_t; + +/** Switch state, either open or closed, to be used in \ref Cy_CTDAC_SetAnalogSwitch. */ +typedef enum +{ + CY_CTDAC_SWITCH_OPEN = 0uL, /**< Open the switch */ + CY_CTDAC_SWITCH_CLOSE = 1uL /**< Close the switch */ +}cy_en_ctdac_switch_state_t; + +/** Switch mask to be used in \ref Cy_CTDAC_SetAnalogSwitch */ +typedef enum +{ + CY_CTDAC_SWITCH_CVD_MASK = CTDAC_CTDAC_SW_CTDD_CVD_Msk, /**< Switch for the reference source, Vdda or external */ + CY_CTDAC_SWITCH_CO6_MASK = CTDAC_CTDAC_SW_CTDO_CO6_Msk /**< Switch for the output, buffered or direct */ +}cy_en_ctdac_switches_t; + +/** Return states for \ref Cy_CTDAC_Init, \ref Cy_CTDAC_DeInit, and \ref Cy_CTDAC_FastInit */ +typedef enum { + CY_CTDAC_SUCCESS = 0x00uL, /**< Initialization completed successfully */ + CY_CTDAC_BAD_PARAM = CY_CTDAC_ID | CY_PDL_STATUS_ERROR | 0x01uL /**< Input pointers were NULL and Initialization could not be completed */ +}cy_en_ctdac_status_t; + +/** \} group_ctdac_enums */ + +/*************************************** +* Configuration Structures +***************************************/ + +/** +* \addtogroup group_ctdac_data_structures +* \{ +*/ + +/** Configuration structure to set up the entire CTDAC block to be used with \ref Cy_CTDAC_Init +*/ +typedef struct +{ + cy_en_ctdac_ref_source_t refSource; /**< Reference source: Vdda or externally through Opamp1 of CTB */ + cy_en_ctdac_format_t formatMode; /**< Format of DAC value: signed or unsigned */ + cy_en_ctdac_update_t updateMode; /**< Update mode: direct or buffered writes or hardware, edge or level */ + cy_en_ctdac_deglitch_t deglitchMode; /**< Deglitch mode: disabled, buffered, unbuffered, or both */ + cy_en_ctdac_output_mode_t outputMode; /**< Output mode: enabled (value or value + 1), high-z, Vssa, or Vdda */ + cy_en_ctdac_output_buffer_t outputBuffer; /**< Output path: Buffered through Opamp0 of CTB or connected directly to Pin 6 */ + cy_en_ctdac_deep_sleep_t deepSleep; /**< Enable or disable the CTDAC during Deep Sleep */ + uint32_t deglitchCycles; /**< Number of deglitch cycles from 0 to 63 */ + int32_t value; /**< Current DAC value */ + int32_t nextValue; /**< Next DAC value for double buffering */ + bool enableInterrupt; /**< If true, enable interrupt when next value register is transferred to value register */ + bool enable; /**< Enable or disable hardware after initialization */ + + /* Configuring the clock */ + bool configClock; /**< Configure or ignore clock information */ + cy_en_divider_types_t dividerType; /**< Specifies which type of divider to use. Can be integer or fractional divider. Not used if updateMode is CY_CTDAC_UPDATE_DIRECT_WRITE */ + uint32_t dividerNum; /**< Specifies which divider of the selected type to configure. Not used if updateMode is CY_CTDAC_UPDATE_DIRECT_WRITE */ + uint32_t dividerIntValue; /**< The integer divider value. The divider value causes integer division of (divider value + 1). Not used if updateMode is CY_CTDAC_UPDATE_DIRECT_WRITE or CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE */ + uint32_t dividerFracValue; /**< The fractional divider value if using a fractional clock. Not used if updateMode is CY_CTDAC_UPDATE_DIRECT_WRITE or CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE */ +}cy_stc_ctdac_config_t; + +/** Configuration structure to quickly set up the CTDAC to be used with \ref Cy_CTDAC_FastInit +* This structure provides a selection for the CTDAC reference source and output path. +* +* The other configuration options are set to: +* - .formatMode = CY_CTDAC_FORMAT_UNSIGNED +* - .updateMode = CY_CTDAC_UPDATE_BUFFERED_WRITE +* - .deglitchMode = CY_CTDAC_DEGLITCHMODE_NONE +* - .outputMode = CY_CTDAC_OUTPUT_VALUE +* - .deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE +* - .deglitchCycles = CY_CTDAC_DEINIT +* - .value = CY_CTDAC_UNSIGNED_MID_CODE_VALUE +* - .nextValue = CY_CTDAC_UNSIGNED_MID_CODE_VALUE +* - .enableInterrupt = true +* - .configClock = true +* - .dividerType = CY_CTDAC_FAST_CLKCFG_TYPE +* - .dividerNum = CY_CTDAC_FAST_CLKCFG_NUM +* - .dividerInitValue = CY_CTDAC_FAST_CLKCFG_DIV +* - .dividerFracValue = CY_CTDAC_DEINIT +*/ +typedef struct +{ + cy_en_ctdac_ref_source_t refSource; /**< Reference source: Vdda or externally through Opamp1 of CTB */ + cy_en_ctdac_output_buffer_t outputBuffer; /**< Output path: Buffered through Opamp0 of CTB or connected directly to Pin 6 */ +}cy_stc_ctdac_fast_config_t; + +/** \} group_ctdac_data_structures */ + +/** \addtogroup group_ctdac_globals +* \{ +*/ +/*************************************** +* Global Variables +***************************************/ + +/** Configure CTDAC to use Vdda reference and output unbuffered. See \ref Cy_CTDAC_FastInit. */ +extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_UnbufferedOut; + +/** Configure CTDAC to use Vdda reference and output buffered through Opamp0 of CTB. See \ref Cy_CTDAC_FastInit. +* +* To quickly configure Opamp0, call with \ref Cy_CTB_FastInit +* with \ref Cy_CTB_Fast_Opamp0_Vdac_Out or \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH. +*/ +extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_BufferedOut; + +/** Configure CTDAC to use a buffered reference from Opamp1 of CTB +* and output unbuffered. See \ref Cy_CTDAC_FastInit. +* +* To use the reference from the Analog Reference (AREF), +* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref. +* +* To use an external reference from a GPIO, +* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 +* for Pin 5 on the CTB port. +*/ +extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_UnbufferedOut; + +/** Configure CTDAC to use a buffered reference from Opamp1 of CTB +* and output buffered through Opamp0 of CTB. See \ref Cy_CTDAC_FastInit. +* +* To quickly configure Opamp0, call with \ref Cy_CTB_FastInit +* with \ref Cy_CTB_Fast_Opamp0_Vdac_Out or \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH. +* +* To use the reference from the Analog Reference (AREF), +* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref. +* +* To use an external reference from a GPIO, +* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 +* for Pins 5 on the CTB port. +*/ +extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_BufferedOut; + +/** \} group_ctdac_globals */ + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_ctdac_functions +* \{ +*/ +cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config); +cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting); +cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast_config_t *config); +__STATIC_INLINE void Cy_CTDAC_Enable(CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_Disable(CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value); +__STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value); +void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode); +void Cy_CTDAC_SetDeepSleepMode(CTDAC_Type *base, cy_en_ctdac_deep_sleep_t deepSleep); +void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMode); +void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchMode); +void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles); +void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource); + +/** \addtogroup group_ctdac_functions_switches +* +* This set of functions is for controlling the two CTDAC analog switches, CVD, and CO6. +* These are advanced functions. The switches will be managed by the reference +* source and output mode selections when initializing the hardware. +* \{ +*/ +void Cy_CTDAC_SetAnalogSwitch(CTDAC_Type *base, uint32_t switchMask, cy_en_ctdac_switch_state_t state); +__STATIC_INLINE uint32_t Cy_CTDAC_GetAnalogSwitch(const CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_SetSwitchCO6(CTDAC_Type *base, cy_en_ctdac_switch_state_t state); +__STATIC_INLINE void Cy_CTDAC_OpenAllSwitches(CTDAC_Type *base); +/** \} */ + +/** \addtogroup group_ctdac_functions_interrupts +* This set of functions is related to the VDAC_EMPTY interrupt +* \{ +*/ +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_SetSwInterrupt(CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask); +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base); +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *base); +/** \} */ + +/** \addtogroup group_ctdac_functions_syspm_callback +* This driver supports one SysPm callback for Deep Sleep transition. +* \{ +*/ +cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams); +/** \} */ + +/******************************************************************************* +* Function Name: Cy_CTDAC_Enable +****************************************************************************//** +* +* Powers up the CTDAC hardware block +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_Enable(CTDAC_Type *base) +{ + base->CTDAC_CTRL |= CTDAC_CTDAC_CTRL_ENABLED_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_Disable +****************************************************************************//** +* +* Turn off the hardware block. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_Disable(CTDAC_Type *base) +{ + base->CTDAC_CTRL &= ~CTDAC_CTDAC_CTRL_ENABLED_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetValue +****************************************************************************//** +* +* Set the CTDAC_VAL register (DAC hardware is +* updated on the next Peri clock cycle). Only the least significant 12 bits +* have an effect. Sign extension of negative values is unnecessary and is +* ignored by the hardware. The way in which the CTDAC interprets the 12-bit +* data is controlled by \ref Cy_CTDAC_SetSignMode. +* +* \param base +* Pointer to structure describing registers +* +* \param value +* Value to write into the CTDAC_VAL register +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value) +{ + base->CTDAC_VAL = (((uint32_t)value) << CTDAC_CTDAC_VAL_VALUE_Pos) & CTDAC_CTDAC_VAL_VALUE_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetValueBuffered +****************************************************************************//** +* +* Set the CTDAC_VAL_NEXT register. The value is transferred +* to the CTDAC_VAL register on the next edge of the CTDAC clock. +* Only the least significant 12 bits +* have an effect. Sign extension of negative values is unnecessary and is +* ignored by the hardware. The way in which the CTDAC interprets the 12-bit +* data is controlled by \ref Cy_CTDAC_SetSignMode. +* +* \param base +* Pointer to structure describing registers +* +* \param value +* Value to write into the CTDAC_VAL_NEXT register +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value){ + base->CTDAC_VAL_NXT = (((uint32_t)value) << CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk; +} + +/** +* \addtogroup group_ctdac_functions_switches +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_CTDAC_GetAnalogSwitch +****************************************************************************//** +* +* Gets the state (open or close) of CTDAC switches as a uint32_t value. +* +* This is an advanced function. The switches will be managed by the reference +* source and output mode selections when initializing the hardware. + +* \param base +* Pointer to structure describing registers +* +* \return uint32_t +* Compare the value to the switch masks found in \ref cy_en_ctdac_switches_t. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTDAC_GetAnalogSwitch(const CTDAC_Type *base) +{ + return base->CTDAC_SW; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetSwitchCO6 +****************************************************************************//** +* +* Open or close switch CO6 that controls whether the output gets routed +* directly to a pin or through Opamp0 of the CTB. +* +* Note that this switch will temporarily +* be opened for deglitching if DEGLITCHMODE_UNBUFFERED or DEGLITCHMODE_BOTH +* is set in \ref Cy_CTDAC_SetDeglitchMode. +* +* This is an advanced function. The switches will be managed by the reference +* source and output mode selections when initializing the hardware. +* +* \param base +* Pointer to structure describing registers +* +* \param state +* State of the switch, open or close. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_SetSwitchCO6(CTDAC_Type *base, cy_en_ctdac_switch_state_t state) +{ + Cy_CTDAC_SetAnalogSwitch(base, (uint32_t) CY_CTDAC_SWITCH_CO6_MASK, state); +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_OpenAllSwitches +****************************************************************************//** +* +* Open all switches. +* +* This is an advanced function. The switches will be managed by the reference +* source and output mode selections when initializing the hardware. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_OpenAllSwitches(CTDAC_Type *base) +{ + base->CTDAC_SW_CLEAR = CY_CTDAC_DEINT_CTDAC_SW; +} + +/** \} */ + +/** +* \addtogroup group_ctdac_functions_interrupts +* \{ +*/ +/******************************************************************************* +* Function Name: Cy_CTDAC_GetInterruptStatus +****************************************************************************//** +* +* Returns the interrupt status which gets set by the hardware +* when the CTDAC_VAL_NXT register value is transferred to the CTDAC_VAL register. +* Once set, the CTDAC_VAL_NXT register is ready to accept a new value. +* +* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. +* +* \param base +* Pointer to structure describing registers +* +* \return +* 0 = Value not moved from CTDAC_VAL_NXT to CTDAC_VAL +* 1 = Value moved from CTDAC_VAL_NXT to CTDAC_VAL +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base) +{ + return (base->INTR & CTDAC_INTR_VDAC_EMPTY_Msk) >> CTDAC_INTR_VDAC_EMPTY_Pos; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_ClearInterrupt +****************************************************************************//** +* +* Clears the interrupt that was set by the hardware when the +* CTDAC_VAL_NXT register value is transferred to the CTDAC_VAL register. +* The interrupt must be cleared with this function so that +* the hardware can set subsequent interrupts and those interrupts +* can be forwarded to the interrupt controller, if enabled. +* +* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base) +{ + base->INTR = CTDAC_INTR_VDAC_EMPTY_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetSwInterrupt +****************************************************************************//** +* +* Forces the CTDAC interrupt to trigger using software. +* +* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_SetSwInterrupt(CTDAC_Type *base) +{ + base->INTR_SET = CTDAC_INTR_SET_VDAC_EMPTY_SET_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetInterruptMask +****************************************************************************//** +* +* Configure the CTDAC interrupt to be forwarded to the CPU interrupt +* controller. +* +* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. +* +* \param base +* Pointer to structure describing registers +* +* \param mask +* 0: Disable CTDAC interrupt request (will not be forwarded to CPU interrupt controller) +* 1: Enable CTDAC interrupt request (will be forwarded to CPU interrupt controller) +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask) +{ + CY_ASSERT_L2(CY_CTDAC_INTRMASK(mask)); + + base->INTR_MASK = mask & CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_GetInterruptMask +****************************************************************************//** +* +* Returns whether the CTDAC interrupt is +* forwarded to the CPU interrupt controller +* as configured by \ref Cy_CTDAC_SetInterruptMask. +* +* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. +* +* \param base +* Pointer to structure describing registers +* +* \return +* 0 = Interrupt output not forwarded to CPU interrupt controller +* 1 = Interrupt output forwarded to CPU interrupt controller +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base) +{ + return (base->INTR_MASK & CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk) >> CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Pos; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_GetInterruptStatusMasked +****************************************************************************//** +* +* Returns the bitwise AND of \ref Cy_CTDAC_GetInterruptStatus and +* \ref Cy_CTDAC_SetInterruptMask. When high, the DAC interrupt is +* asserted and the interrupt is forwarded to the CPU interrupt +* controller. +* +* Interrupts are available in all update modes except \ref CY_CTDAC_UPDATE_DIRECT_WRITE. +* +* \param base +* Pointer to structure describing registers +* +* \return +* 0 = Value not moved from CTDAC_VAL_NXT to CTDAC_VAL or not masked +* 1 = Value moved from CTDAC_VAL_NXT to CTDAC_VAL and masked +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *base){ + return (base->INTR_MASKED & CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Msk) >> CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Pos; +} + +/** \} */ + +/** \} group_ctdac_functions */ + +#if defined(__cplusplus) +} +#endif + +#endif /** !defined(CY_CTDAC_H) */ + +/** \} group_ctdac */ + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/dma/cy_dma.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/dma/cy_dma.c new file mode 100644 index 0000000000..2b50f08363 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/dma/cy_dma.c @@ -0,0 +1,318 @@ +/***************************************************************************//** +* \file cy_dma.c +* \version 2.0 +* +* \brief +* The source code file for the DMA driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_dma.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_Init +****************************************************************************//** +* +* Initializes descriptor structure in SRAM from a pre-initialized +* configuration structure. +* This function initializes only the descriptor and not the channel. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param config +* This is a configuration structure that has all initialization information for +* the descriptor. +* +* \return +* The status /ref cy_en_dma_status_t. +* +*******************************************************************************/ +cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor, const cy_stc_dma_descriptor_config_t * config) +{ + cy_en_dma_status_t retVal = CY_DMA_BAD_PARAM; + + if ((NULL != descriptor) && (NULL != config)) + { + CY_ASSERT_L3(CY_DMA_IS_RETRIGGER_VALID(config->retrigger)); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->interruptType)); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->triggerOutType)); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->triggerInType)); + CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(config->srcTransferSize)); + CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(config->dstTransferSize)); + CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(config->channelState)); + CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(config->dataSize)); + CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(config->descriptorType)); + + descriptor->ctl = + _VAL2FLD(CY_DMA_CTL_RETRIG, config->retrigger) | + _VAL2FLD(CY_DMA_CTL_INTR_TYPE, config->interruptType) | + _VAL2FLD(CY_DMA_CTL_TR_OUT_TYPE, config->triggerOutType) | + _VAL2FLD(CY_DMA_CTL_TR_IN_TYPE, config->triggerInType) | + _VAL2FLD(CY_DMA_CTL_SRC_SIZE, config->srcTransferSize) | + _VAL2FLD(CY_DMA_CTL_DST_SIZE, config->dstTransferSize) | + _VAL2FLD(CY_DMA_CTL_CH_DISABLE, config->channelState) | + _VAL2FLD(CY_DMA_CTL_DATA_SIZE, config->dataSize) | + _VAL2FLD(CY_DMA_CTL_TYPE, config->descriptorType); + + descriptor->src = (uint32_t)config->srcAddress; + + descriptor->dst = (uint32_t)config->dstAddress; + + switch(config->descriptorType) + { + case CY_DMA_SINGLE_TRANSFER: + { + descriptor->xCtl = (uint32_t)config->nextDescriptor; + break; + } + case CY_DMA_1D_TRANSFER: + { + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcXincrement)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstXincrement)); + CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->xCount)); + + descriptor->xCtl = + _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) | + _VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL); + + descriptor->yCtl = (uint32_t)config->nextDescriptor; + break; + } + case CY_DMA_2D_TRANSFER: + { + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcXincrement)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstXincrement)); + CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->xCount)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcYincrement)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstYincrement)); + CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->yCount)); + + descriptor->xCtl = + _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) | + _VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL); + + descriptor->yCtl = + _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcYincrement) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstYincrement) | + _VAL2FLD(CY_DMA_CTL_COUNT, config->yCount - 1UL); + + descriptor->nextPtr = (uint32_t)config->nextDescriptor; + break; + } + default: + { + /* Unsupported type of descriptor */ + break; + } + } + + retVal = CY_DMA_SUCCESS; + } + + return retVal; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_DeInit +****************************************************************************//** +* +* Clears all the content of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +*******************************************************************************/ +void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor) +{ + descriptor->ctl = 0UL; + descriptor->src = 0UL; + descriptor->dst = 0UL; + descriptor->xCtl = 0UL; + descriptor->yCtl = 0UL; + descriptor->nextPtr = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_Init +****************************************************************************//** +* +* Initializes the DMA channel with a descriptor and other parameters. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +* \param channelConfig +* A structure that has the initialization information for the +* channel. +* +* \return +* The status /ref cy_en_dma_status_t. +* +*******************************************************************************/ +cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_dma_channel_config_t const * channelConfig) +{ + cy_en_dma_status_t retVal = CY_DMA_BAD_PARAM; + + if (((CY_DMA_IS_DW_CH_NR_VALID(base, channel)) && (NULL != channelConfig) && (NULL != channelConfig->descriptor))) + { + uint32_t regVal; + + CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(channelConfig->priority)); + + /* Set current descriptor */ + base->CH_STRUCT[channel].CH_CURR_PTR = (uint32_t)channelConfig->descriptor; + + /* Set if the channel is preemtable */ + regVal = base->CH_STRUCT[channel].CH_CTL & ((uint32_t) ~(DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk | + DW_CH_STRUCT_CH_CTL_PRIO_Msk | + DW_CH_STRUCT_CH_CTL_ENABLED_Msk)); + + base->CH_STRUCT[channel].CH_CTL = regVal | _BOOL2FLD(DW_CH_STRUCT_CH_CTL_PREEMPTABLE, channelConfig->preemptable) | + _VAL2FLD(DW_CH_STRUCT_CH_CTL_PRIO, channelConfig->priority) | + _BOOL2FLD(DW_CH_STRUCT_CH_CTL_ENABLED, channelConfig->enable); + + retVal = CY_DMA_SUCCESS; + } + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_DeInit +****************************************************************************//** +* +* Clears all the content of registers corresponding to the channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +*******************************************************************************/ +void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + base->CH_STRUCT[channel].CH_CTL = 0UL; + base->CH_STRUCT[channel].CH_IDX = 0UL; + base->CH_STRUCT[channel].CH_CURR_PTR = 0UL; + base->CH_STRUCT[channel].INTR_MASK = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetNextDescriptor +****************************************************************************//** +* +* Sets a Next Descriptor parameter for the specified descriptor. +* +* Based on descriptor type the offset of address for the next descriptor may +* vary. For a single transfer descriptor type, this register is at offset 0x0c. +* For a 1D transfer descriptor type, this register is at offset 0x10. For a 2D +* transfer descriptor type, this register is at offset 0x14. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param nextDescriptor +* The pointer to the next descriptor. +* +*******************************************************************************/ +void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + switch((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl)) + { + case CY_DMA_SINGLE_TRANSFER: + descriptor->xCtl = (uint32_t)nextDescriptor; + break; + + case CY_DMA_1D_TRANSFER: + descriptor->yCtl = (uint32_t)nextDescriptor; + break; + + case CY_DMA_2D_TRANSFER: + descriptor->nextPtr = (uint32_t)nextDescriptor; + break; + + default: + /* Unsupported type of descriptor */ + break; + } +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetNextDescriptor +****************************************************************************//** +* +* Returns a next descriptor address of the specified descriptor. +* +* Based on descriptor type the offset of address for the next descriptor may +* vary. For a single transfer descriptor type, this register is at offset 0x0c. +* For a 1D transfer descriptor type, this register is at offset 0x10. For a 2D +* transfer descriptor type, this register is at offset 0x14. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The pointer to the next descriptor. +* +*******************************************************************************/ +cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descriptor_t const * descriptor) +{ + cy_stc_dma_descriptor_t * retVal = NULL; + + CY_ASSERT_L1(NULL != descriptor); + + switch((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl)) + { + case CY_DMA_SINGLE_TRANSFER: + retVal = (cy_stc_dma_descriptor_t*) descriptor->xCtl; + break; + + case CY_DMA_1D_TRANSFER: + retVal = (cy_stc_dma_descriptor_t*) descriptor->yCtl; + break; + + case CY_DMA_2D_TRANSFER: + retVal = (cy_stc_dma_descriptor_t*) descriptor->nextPtr; + break; + + default: + /* Unsupported type of descriptor */ + break; + } + + return (retVal); +} + + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/dma/cy_dma.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/dma/cy_dma.h new file mode 100644 index 0000000000..e13a8c6bdc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/dma/cy_dma.h @@ -0,0 +1,1811 @@ +/***************************************************************************//** +* \file cy_dma.h +* \version 2.0 +* +* \brief +* The header file of the DMA driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_dma Direct Memory Access (DMA) +* \{ +* Configures a DMA channel and its descriptor(s). +* +* The DMA Channel component can be used in any project that needs to transfer data +* without CPU intervention, based on a hardware trigger signal from another component. +* +* A device may support more than one DMA hardware block. Each block has a set of +* registers, and a base hardware address. Each block also supports multiple channels. +* Many API functions for the DMA driver require the base hardware address and the +* channel number. Ensure that you use the correct hardware address for the DMA block in use. +* +* Features: +* * Devices support up to two DMA hardware blocks +* * Each DMA block supports up to 16 DMA channels +* * Supports channel descriptors in SRAM +* * Four Priority Levels for each channel +* * Byte, Half-word (2 byte), and Word (4 byte) transfers +* * Configurable source and destination addresses +* +* \section group_dma_configuration Configuration Considerations +* +* To set up a DMA driver you initialize a descriptor, +* intialize and enable a channel, and enable the DMA block. +* +* To set up the descriptor, provide the configuration parameters for the +* descriptor in the \ref cy_stc_dma_descriptor_config_t structure. Then call the +* \ref Cy_DMA_Descriptor_Init function to initialize the descriptor in SRAM. You can +* modify the source and destination addresses dynamically by calling +* \ref Cy_DMA_Descriptor_SetSrcAddress and \ref Cy_DMA_Descriptor_SetDstAddress. +* +* To set up the DMA channel, provide a filled \ref cy_stc_dma_channel_config_t +* structure. Call the \ref Cy_DMA_Channel_Init function, specifying the channel +* number. Use \ref Cy_DMA_Channel_Enable to enable the configured DMA channel. +* +* Call \ref Cy_DMA_Channel_Enable for each DMA channel in use. +* +* The following is a simplified structure of the DMA driver API interdependences +* in a typical user application: +* \image html dma.png +* +* NOTE: Even if a DMA channel is enabled, it is not operational until +* the DMA block is enabled using function \ref Cy_DMA_Enable.\n +* NOTE: If the DMA descriptor is configured to generate an interrupt, +* the interrupt must be enabled using the \ref Cy_DMA_Channel_SetInterruptMask +* function for each DMA channel. +* +* For example: +* \snippet dma/dma_v2_0_sut_00.cydsn/main_cm4.c Cy_DMA_Snippet +* +* \section group_dma_more_information More Information. +* +* See the DMA Component datasheet. +* See also the DMA chapter of the device technical reference manual (TRM). +* +* \section group_dma_MISRA MISRA-C Compliance +* The DMA driver has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
    10.3RA composite expression of 'essentially unsigned' type is being +* cast to a different type category.The value got from the bitfield physically can't exceed the enumeration +* that describes this bitfield. So the code is safety by design.
    14.2RAll non-null statements shall either: +* a) have at least one side effect however executed +* b) cause control flow to changeA result of a read operation is ignored when this read is just intended + to ensure the previous write operation is flushed out to the hardware.
    +* +* \section group_dma_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    VersionChangesReason for Change
    1.0Initial version
    2.0* All the API is refactored to be consistent within itself and with the +* rest of the PDL content. +* * The descriptor API is update in the next manner: +* The \ref Cy_DMA_Descriptor_Init function sets whole the bunch of descriptor +* settings, and all the rest of descriptor API is the get/set interface +* to the each of descriptor settings. +* * There is a bunch of macros to support a backward compatibility with most +* of the driver version 1.0 API, however it is strongly recommended to use +* the new v2.0 interface in new designs (do not just copy-paste from old +* projects). To enable the backward compatibility support the CY_DMA_BWC +* definition should be changed to "true".
    +* + +* \defgroup group_dma_macros Macros +* \defgroup group_dma_functions Functions +* \{ +* \defgroup group_dma_block_functions Block Functions +* \defgroup group_dma_descriptor_functions Descriptor Functions +* \defgroup group_dma_channel_functions Channel Functions +* \} +* \defgroup group_dma_data_structures Data structures +* \defgroup group_dma_enums Enumerated types +*/ + +#if !defined(CY_DMA_H) +#define CY_DMA_H + +#include +#include +#include +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" + +#ifndef CY_IP_M4CPUSS_DMA + #error "The DMA driver is not supported on this device" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** + * Macro definitions * + ******************************************************************************/ + +/** +* \addtogroup group_dma_macros +* \{ +*/ + +/** Driver major version */ +#define CY_DMA_DRV_VERSION_MAJOR 2 + +/** Driver minor version */ +#define CY_DMA_DRV_VERSION_MINOR 0 + +/** DMA driver identifier */ +#define CY_DMA_ID (CY_PDL_DRV_ID(0x13U)) + +/** DMA channel interrupt mask */ +#define CY_DMA_INTR_MASK (0x01UL) + +/** Backward compatibility flag. It enables a bunch of macros which provide +* a backward compatibility with most of DMA driver version 1.0 interface. */ +#ifndef CY_DMA_BWC + #define CY_DMA_BWC (false) +#endif + +/** \} group_dma_macros */ + + +/** +* \addtogroup group_dma_enums +* \{ +*/ + +/** Contains the possible interrupt cause values */ +typedef enum +{ + CY_DMA_INTR_CAUSE_NO_INTR = 0U, /**< No interrupt */ + CY_DMA_INTR_CAUSE_COMPLETION = 1U, /**< Completion */ + CY_DMA_INTR_CAUSE_SRC_BUS_ERROR = 2U, /**< Source bus error */ + CY_DMA_INTR_CAUSE_DST_BUS_ERROR = 3U, /**< Destination bus error */ + CY_DMA_INTR_CAUSE_SRC_MISAL = 4U, /**< Source address is not aligned */ + CY_DMA_INTR_CAUSE_DST_MISAL = 5U, /**< Destination address is not aligned */ + CY_DMA_INTR_CAUSE_CURR_PTR_NULL = 6U, /**< Current descripror pointer is NULL */ + CY_DMA_INTR_CAUSE_ACTIVE_CH_DISABLED = 7U, /**< Active channel is disabled */ + CY_DMA_INTR_CAUSE_DESCR_BUS_ERROR = 8U /**< Descriptor bus error */ +} cy_en_dma_intr_cause_t; + +/** Contains the options for the descriptor type */ +typedef enum +{ + CY_DMA_SINGLE_TRANSFER = 0UL, /**< Single transfer. */ + CY_DMA_1D_TRANSFER = 1UL, /**< 1D transfer. */ + CY_DMA_2D_TRANSFER = 2UL /**< 2D transfer. */ +} cy_en_dma_descriptor_type_t; + +/** Contains the options for the interrupt, trig-in and trig-out type parameters of the descriptor */ +typedef enum +{ + CY_DMA_1ELEMENT = 0UL, /**< One element transfer. */ + CY_DMA_X_LOOP = 1UL, /**< One X loop transfer. */ + CY_DMA_DESCR = 2UL, /**< One descriptor transfer. */ + CY_DMA_DESCR_CHAIN = 3UL /**< Entire descriptor chain transfer. */ +} cy_en_dma_trigger_type_t; + +/** This enum has the options for the data size */ +typedef enum +{ + CY_DMA_BYTE = 0UL, /**< One byte */ + CY_DMA_HALFWORD = 1UL, /**< Half word (two bytes) */ + CY_DMA_WORD = 2UL /**< Full word (four bytes) */ +} cy_en_dma_data_size_t; + +/** This enum has the options for descriptor retriggering */ +typedef enum +{ + CY_DMA_RETDIG_IM = 0UL, /**< Retrigger immidiatelly */ + CY_DMA_RETDIG_4CYC = 1UL, /**< Retrigger after 4 SYSCLK */ + CY_DMA_RETDIG_16CYC = 2UL, /**< Retrigger after 16 SYSCLK */ + CY_DMA_WAIT_FOR_REACT = 3UL /**< Wait for trigger reactivation */ +} cy_en_dma_retrigger_t; + +/** This enum has the options for the transfer size */ +typedef enum +{ + CY_DMA_TRANSFER_SIZE_DATA = 0UL, /**< As specified by dataSize. */ + CY_DMA_TRANSFER_SIZE_WORD = 1UL, /**< A full word (four bytes). */ +} cy_en_dma_transfer_size_t; + +/** This enum has the options for the state of the channel when the descriptor is completed */ +typedef enum +{ + CY_DMA_CHANNEL_ENABLED = 0UL, /**< Channel stays enabled */ + CY_DMA_CHANNEL_DISABLED = 1UL /**< Channel is disabled */ +} cy_en_dma_channel_state_t; + +/** This enum has the return values of the DMA driver */ +typedef enum +{ + CY_DMA_SUCCESS = 0x00UL, /**< Success. */ + CY_DMA_BAD_PARAM = CY_DMA_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< Input parameters passed to DMA API are not valid. */ +} cy_en_dma_status_t; + +/** \} group_dma_enums */ + + +/** \cond Macros for conditions used by CY_ASSERT calls */ + +#define CY_DMA_IS_COUNT_VALID(count) (((count) >= 1UL) && ((count) <= 256UL)) +#define CY_DMA_IS_INCR_VALID(incr) (((incr) >= -2048L) && ((incr) <= 2047L)) +#define CY_DMA_IS_PRIORITY_VALID(prio) ((prio) <= 3UL) +#define CY_DMA_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_DMA_INTR_MASK))) + +#define CY_DMA_IS_RETRIGGER_VALID(retrigger) ((CY_DMA_RETDIG_IM == (retrigger)) || \ + (CY_DMA_RETDIG_4CYC == (retrigger)) || \ + (CY_DMA_RETDIG_16CYC == (retrigger)) || \ + (CY_DMA_WAIT_FOR_REACT == (retrigger))) + +#define CY_DMA_IS_TRIG_TYPE_VALID(trigType) ((CY_DMA_1ELEMENT == (trigType)) || \ + (CY_DMA_X_LOOP == (trigType)) || \ + (CY_DMA_DESCR == (trigType)) || \ + (CY_DMA_DESCR_CHAIN == (trigType))) + +#define CY_DMA_IS_XFER_SIZE_VALID(xferSize) ((CY_DMA_TRANSFER_SIZE_DATA == (xferSize)) || \ + (CY_DMA_TRANSFER_SIZE_WORD == (xferSize))) + +#define CY_DMA_IS_CHANNEL_STATE_VALID(state) ((CY_DMA_CHANNEL_ENABLED == (state)) || \ + (CY_DMA_CHANNEL_DISABLED == (state))) + +#define CY_DMA_IS_DATA_SIZE_VALID(dataSize) ((CY_DMA_BYTE == (dataSize)) || \ + (CY_DMA_HALFWORD == (dataSize)) || \ + (CY_DMA_WORD == (dataSize))) + +#define CY_DMA_IS_TYPE_VALID(descrType) ((CY_DMA_SINGLE_TRANSFER == (descrType)) || \ + (CY_DMA_1D_TRANSFER == (descrType)) || \ + (CY_DMA_2D_TRANSFER == (descrType))) + +#define CY_DMA_IS_DW_CH_NR_VALID(dwNr, chNr) (((0U != CPUSS_DW0_PRESENT) && (DW0 == (dwNr)) && ((chNr) < CPUSS_DW0_CH_NR)) || \ + ((0U != CPUSS_DW1_PRESENT) && (DW1 == (dwNr)) && ((chNr) < CPUSS_DW1_CH_NR))) + +/* Descriptor structure bitfiled definitions */ +#define CY_DMA_CTL_RETRIG_Pos 0UL +#define CY_DMA_CTL_RETRIG_Msk 0x3UL +#define CY_DMA_CTL_INTR_TYPE_Pos 2UL +#define CY_DMA_CTL_INTR_TYPE_Msk 0xCUL +#define CY_DMA_CTL_TR_OUT_TYPE_Pos 4UL +#define CY_DMA_CTL_TR_OUT_TYPE_Msk 0x30UL +#define CY_DMA_CTL_TR_IN_TYPE_Pos 6UL +#define CY_DMA_CTL_TR_IN_TYPE_Msk 0xC0UL +#define CY_DMA_CTL_CH_DISABLE_Pos 24UL +#define CY_DMA_CTL_CH_DISABLE_Msk 0x1000000UL +#define CY_DMA_CTL_SRC_SIZE_Pos 26UL +#define CY_DMA_CTL_SRC_SIZE_Msk 0x4000000UL +#define CY_DMA_CTL_DST_SIZE_Pos 27UL +#define CY_DMA_CTL_DST_SIZE_Msk 0x8000000UL +#define CY_DMA_CTL_DATA_SIZE_Pos 28UL +#define CY_DMA_CTL_DATA_SIZE_Msk 0x30000000UL +#define CY_DMA_CTL_TYPE_Pos 30UL +#define CY_DMA_CTL_TYPE_Msk 0xC0000000UL + +#define CY_DMA_CTL_SRC_INCR_Pos 0UL +#define CY_DMA_CTL_SRC_INCR_Msk 0xFFFUL +#define CY_DMA_CTL_DST_INCR_Pos 12UL +#define CY_DMA_CTL_DST_INCR_Msk 0xFFF000UL +#define CY_DMA_CTL_COUNT_Pos 24UL +#define CY_DMA_CTL_COUNT_Msk 0xFF000000UL + +/** \endcond */ + + +/** +* \addtogroup group_dma_data_structures +* \{ +*/ + +/** +* DMA descriptor structure type. It is a user/component-declared structure which is +* allocated in RAM and just a pointer to which is needed for DMA HW to work with it. +* +* For advanced users: the descriptor can be allocated even in Flash, but in this +* case user should manually predefine all the structure items with constants, +* bacause most of driver's API (especially those functions which are modifying +* descriptors, including \ref Cy_DMA_Descriptor_Init()) can't work with +* read-only descriptors. +*/ +typedef struct +{ + uint32_t ctl; /*!< 0x00000000 Descriptor control */ + uint32_t src; /*!< 0x00000004 Descriptor source */ + uint32_t dst; /*!< 0x00000008 Descriptor destination */ + uint32_t xCtl; /*!< 0x0000000C Descriptor X loop control */ + uint32_t yCtl; /*!< 0x00000010 Descriptor Y loop control */ + uint32_t nextPtr; /*!< 0x00000014 Descriptor next pointer */ +} cy_stc_dma_descriptor_t; + +/** +* This structure is a configuration structure pre-initialized by the user and +* passed as a parameter to the \ref Cy_DMA_Descriptor_Init(). +* It can be allocated in RAM/Flash (on user's choice). +* In case of RAM allocation there is a possibility to reinitialize a descriptor in runtime. +* This structure has all the parameters of the descriptor as separate parameters. +* Most of these parameters are represented in the \ref cy_stc_dma_descriptor_t structure as bit fields. +*/ +typedef struct +{ + cy_en_dma_retrigger_t retrigger; /**< Specifies whether the DW controller should wait for the input trigger to be deactivated. */ + cy_en_dma_trigger_type_t interruptType; /**< Sets the event that triggers an interrupt, see \ref cy_en_dma_trigger_type_t. */ + cy_en_dma_trigger_type_t triggerOutType; /**< Sets the event that triggers an output, see \ref cy_en_dma_trigger_type_t. */ + cy_en_dma_channel_state_t channelState; /**< Specifies if the channel is enabled or disabled on completion of descriptor see \ref cy_en_dma_channel_state_t. */ + cy_en_dma_trigger_type_t triggerInType; /**< Sets what type of transfer is triggered, see \ref cy_en_dma_trigger_type_t. */ + cy_en_dma_data_size_t dataSize; /**< The size of the data bus for transfer, see \ref cy_en_dma_data_size_t. */ + cy_en_dma_transfer_size_t srcTransferSize; /**< The source transfer size. */ + cy_en_dma_transfer_size_t dstTransferSize; /**< The destination transfer size. */ + cy_en_dma_descriptor_type_t descriptorType; /**< The type of the descriptor see \ref cy_en_dma_descriptor_type_t. */ + void * srcAddress; /**< The source address of the transfer. */ + void * dstAddress; /**< The destination address of the transfer. */ + int32_t srcXincrement; /**< The address increment of the source after each X-loop transfer. Valid range is -2048...2047. */ + int32_t dstXincrement; /**< The address increment of the destination after each X-loop transfer. Valid range is -2048...2047. */ + uint32_t xCount; /**< The number of transfers in an X-loop. Valid range is 1...256. */ + int32_t srcYincrement; /**< The address increment of the source after each Y-loop transfer. Valid range is -2048...2047. */ + int32_t dstYincrement; /**< The address increment of the destination after each Y-loop transfer. Valid range is -2048...2047. */ + uint32_t yCount; /**< The number of X-loops in the Y-loop. Valid range is 1...256. */ + cy_stc_dma_descriptor_t * nextDescriptor; /**< The next descriptor to chain after completion, a NULL value will signify no chaining. */ +} cy_stc_dma_descriptor_config_t; + +/** This structure holds the initialization values for the DMA channel */ +typedef struct +{ + cy_stc_dma_descriptor_t * descriptor; /**< The DMA descriptor associated with the channel being initialized */ + bool preemptable; /**< Specifies if the channel is preemptable by another higher-priority channel */ + uint32_t priority; /**< This parameter specifies the channel's priority */ + bool enable; /**< This parameter specifies if the channel is enabled after initializing */ +} cy_stc_dma_channel_config_t; + +/** \} group_dma_data_structures */ + + +/** +* \addtogroup group_dma_functions +* \{ +*/ + +__STATIC_INLINE void Cy_DMA_Enable (DW_Type * base); +__STATIC_INLINE void Cy_DMA_Disable (DW_Type * base); +__STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel (DW_Type const * base); +__STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type const * base); +__STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base); + + +/** +* \addtogroup group_dma_descriptor_functions +* \{ +*/ + + cy_en_dma_status_t Cy_DMA_Descriptor_Init (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_config_t const * config); + void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor); + + void Cy_DMA_Descriptor_SetNextDescriptor (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor); +__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress (cy_stc_dma_descriptor_t * descriptor, void const * srcAddress); +__STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress (cy_stc_dma_descriptor_t * descriptor, void const * dstAddress); +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t xCount); +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t yCount); +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement); +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement); +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement); +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement); +__STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType); +__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType); +__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType); +__STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize); +__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize); +__STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize); +__STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger); +__STATIC_INLINE void Cy_DMA_Descriptor_SetDescriptorType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType); +__STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState); + + cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState (cy_stc_dma_descriptor_t const * descriptor); + +/** \} group_dma_descriptor_functions */ + + +/** +* \addtogroup group_dma_channel_functions +* \{ +*/ + + cy_en_dma_status_t Cy_DMA_Channel_Init (DW_Type * base, uint32_t channel, cy_stc_dma_channel_config_t const * channelConfig); + void Cy_DMA_Channel_DeInit (DW_Type * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE void Cy_DMA_Channel_Enable (DW_Type * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_Disable (DW_Type * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_SetPriority (DW_Type * base, uint32_t channel, uint32_t priority); +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority (DW_Type const * base, uint32_t channel); +__STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel); +__STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel); + +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus (DW_Type const * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt (DW_Type * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_SetInterrupt (DW_Type * base, uint32_t channel); +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask (DW_Type const * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask (DW_Type * base, uint32_t channel, uint32_t interrupt); +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel); + +/** \} group_dma_channel_functions */ + + +/*************************************** +* In-line Function Implementation +***************************************/ + + +/** +* \addtogroup group_dma_block_functions +* \{ +*/ + + +/******************************************************************************* +* Function Name: Cy_DMA_Enable +****************************************************************************//** +* +* Enables the DMA block. +* +* \param base +* A pointer to the hardware DMA block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Enable(DW_Type * base) +{ + base->CTL |= DW_CTL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Disable +****************************************************************************//** +* +* Disables the DMA block. +* +* \param base +* A pointer to the hardware DMA block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Disable(DW_Type * base) +{ + base->CTL &= (uint32_t) ~DW_CTL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_GetActiveChannel +****************************************************************************//** +* +* Returns the status of the active/pending channels. +* the DMA block. +* +* \param base +* A pointer to the hardware DMA block. +* +* \return +* Returns a bit-field with all of the currently active/pending channels in the +* DMA block. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel(DW_Type const * base) +{ + return(_FLD2VAL(DW_STATUS_CH_IDX, base->STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_GetActiveSrcAddress +****************************************************************************//** +* +* Returns the source address that is being used for current transfer. +* +* \param base +* A pointer to the hardware DMA block. +* +* \return +* Returns a pointer to the source of transfer. +* +*******************************************************************************/ +__STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type const * base) +{ + return ((void *)base->ACT_DESCR_SRC); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_GetActiveDstAddress +****************************************************************************//** +* +* Returns the destination address that is being used for the current transfer. +* +* \param base +* A pointer to the hardware DMA block. +* +* \return +* Returns a pointer to the destination of transfer. +* +*******************************************************************************/ +__STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base) +{ + return ((void *) base->ACT_DESCR_DST); +} + +/** \} group_dma_block_functions */ + + +/** +* \addtogroup group_dma_descriptor_functions +* \{ +*/ + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetSrcAddress +****************************************************************************//** +* +* Sets the source address parameter for the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param srcAddress +* The source address value for the descriptor. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * descriptor, void const * srcAddress) +{ + descriptor->src = (uint32_t) srcAddress; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetSrcAddress +****************************************************************************//** +* +* Returns the source address parameter of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The source address value of the descriptor. +* +*******************************************************************************/ +__STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t const * descriptor) +{ + return ((void *) descriptor->src); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetDstAddress +****************************************************************************//** +* +* Sets the destination address parameter for the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param dstAddress +* The destination address value for the descriptor. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * descriptor, void const * dstAddress) +{ + descriptor->dst = (uint32_t) dstAddress; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetDstAddress +****************************************************************************//** +* +* Returns the destination address parameter of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The destination address value of the descriptor. +* +*******************************************************************************/ +__STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t const * descriptor) +{ + return ((void *) descriptor->dst); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetInterruptType +****************************************************************************//** +* +* Sets the interrupt type parameter for the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param interruptType +* The interrupt type set for the descriptor. \ref cy_en_dma_trigger_type_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(interruptType)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_INTR_TYPE, interruptType); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetInterruptType +****************************************************************************//** +* +* Returns the Interrupt Type of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The Interrupt Type \ref cy_en_dma_trigger_type_t. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_INTR_TYPE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetTriggerInType +****************************************************************************//** +* +* Sets the Trigger In Type parameter for the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param triggerInType +* The Trigger In Type parameter \ref cy_en_dma_trigger_type_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerInType)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TR_IN_TYPE, triggerInType); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetTriggerInType +****************************************************************************//** +* +* Returns the Trigger In Type of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The Trigger In Type \ref cy_en_dma_trigger_type_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_IN_TYPE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetTriggerOutType +****************************************************************************//** +* +* Sets the trigger-out-type parameter for the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param triggerOutType +* The trigger-out-type set for the descriptor. \ref cy_en_dma_trigger_type_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerOutType)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TR_OUT_TYPE, triggerOutType); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetTriggerOutType +****************************************************************************//** +* +* Returns the Trigger Out Type parameter of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The Trigger Out Type parameter \ref cy_en_dma_trigger_type_t. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_OUT_TYPE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetDataSize +****************************************************************************//** +* +* Sets the data element size for the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param dataSize +* Data element size \ref cy_en_dma_data_size_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(dataSize)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_DATA_SIZE, dataSize); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetDataSize +****************************************************************************//** +* +* Returns the data element size of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* Data element size \ref cy_en_dma_data_size_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_data_size_t) _FLD2VAL(CY_DMA_CTL_DATA_SIZE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetSrcTransferSize +****************************************************************************//** +* +* Sets the source transfer size for the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param srcTransferSize +* This parameter provides the source transfer size parameters of the descriptor. +* \ref cy_en_dma_transfer_size_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(srcTransferSize)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_SRC_SIZE, srcTransferSize); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetSrcTransferSize +****************************************************************************//** +* +* Returns the source transfer size of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* Source Transfer Size \ref cy_en_dma_transfer_size_t. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_SRC_SIZE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetDstTransferSize +****************************************************************************//** +* +* Sets the Destination Transfer Size for the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param dstTransferSize +* A Destination Transfer Size \ref cy_en_dma_transfer_size_t. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(dstTransferSize)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_DST_SIZE, dstTransferSize); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetDstTransferSize +****************************************************************************//** +* +* Returns the Destination Transfer Size of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The Destination Transfer Size \ref cy_en_dma_transfer_size_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_DST_SIZE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetRetrigger +****************************************************************************//** +* +* Sets the retrigger value which specifies whether the controller should +* wait for the input trigger to be deactivated. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param retrigger +* A \ref cy_en_dma_retrigger_t parameter specifies whether the controller +* should wait for the input trigger to be deactivated. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_RETRIGGER_VALID(retrigger)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_RETRIG, retrigger); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetRetrigger +****************************************************************************//** +* +* Returns a value which specifies whether the controller should +* wait for the input trigger to be deactivated. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The Retrigger setting \ref cy_en_dma_retrigger_t. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_retrigger_t) _FLD2VAL(CY_DMA_CTL_RETRIG, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetDescriptorType +****************************************************************************//** +* +* Sets the descriptor's type for the specified descriptor. +* During the descriptor's type changing the Next Descriptor parameter should be +* properly replaced by \ref Cy_DMA_Descriptor_GetNextDescriptor +* (before reconfiguration) and \ref Cy_DMA_Descriptor_SetNextDescriptor (before +* reconfiguration) API functions. +* +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param descriptorType +* A Descriptor Type \ref cy_en_dma_descriptor_type_t. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetDescriptorType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(descriptorType)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TYPE, descriptorType); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetDescriptorType +****************************************************************************//** +* +* Returns the descriptor's type of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The descriptor type \ref cy_en_dma_descriptor_type_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetChannelState +****************************************************************************//** +* +* Sets the channel state on completion of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param channelState +* The Channel State \ref cy_en_dma_channel_state_t. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(channelState)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_CH_DISABLE, channelState); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetChannelState +****************************************************************************//** +* +* Returns the channel state on completion of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The Channel State setting \ref cy_en_dma_channel_state_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_channel_state_t) _FLD2VAL(CY_DMA_CTL_CH_DISABLE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetXloopDataCount +****************************************************************************//** +* +* Sets the number of data elements to transfer in the X loop +* for the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param xCount +* A number of data elements to transfer in the X loop. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t xCount) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(xCount)); + + descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_COUNT, xCount - 1UL); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetXloopDataCount +****************************************************************************//** +* +* Returns the number of data elements for the X loop of the specified +* descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The number of data elements to transfer in the X loop. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->xCtl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetXloopSrcIncrement +****************************************************************************//** +* +* Sets the source increment parameter for the X loop of the specified +* descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param srcXincrement +* A value of source increment. Valid range is -2048 ... 2047. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(srcXincrement)); + + descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_SRC_INCR, srcXincrement); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetXloopSrcIncrement +****************************************************************************//** +* +* Returns the source increment parameter for the X loop of the specified +* descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The value of source increment. +* +*******************************************************************************/ +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->xCtl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetXloopDstIncrement +****************************************************************************//** +* +* Sets the destination increment parameter for the X loop for the specified +* descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param dstXincrement +* A value of destination increment. Valid range is -2048 ... 2047. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(dstXincrement)); + + descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_DST_INCR, dstXincrement); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetXloopDstIncrement +****************************************************************************//** +* +* Returns the destination increment parameter for the X loop of the specified +* descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The value of destination increment. +* +*******************************************************************************/ +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->xCtl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetYloopDataCount +****************************************************************************//** +* +* Sets the number of data elements for the Y loop of the specified descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param yCount +* A number of X loops to execute in the Y loop. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t yCount) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(yCount)); + + descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_COUNT, yCount - 1UL); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetYloopDataCount +****************************************************************************//** +* +* Returns the number of X loops to execute in the Y loop of the specified +* descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The number of X loops to execute in the Y loop. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->yCtl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetYloopSrcIncrement +****************************************************************************//** +* +* Sets the source increment parameter for the Y loop for the specified +* descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param srcYincrement +* A value of source increment. Valid range is -2048 ... 2047. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(srcYincrement)); + + descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_SRC_INCR, srcYincrement); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetYloopSrcIncrement +****************************************************************************//** +* +* Returns the source increment parameter for the outer Y of the specified +* descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The value of source increment. +* +*******************************************************************************/ +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->yCtl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetYloopDstIncrement +****************************************************************************//** +* +* Sets the destination increment parameter for the Y loop of the specified +* descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \param dstYincrement +* A value of destination increment. Valid range is -2048 ... 2047. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(dstYincrement)); + + descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_DST_INCR, dstYincrement); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetYloopDstIncrement +****************************************************************************//** +* +* Returns the destination increment parameter for the Y loop of the specified +* descriptor. +* +* \param descriptor +* A descriptor structure instance declared by user/component. +* +* \return +* The value of destination increment. +* +*******************************************************************************/ +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->yCtl)); +} + + +/** \} group_dma_descriptor_functions */ + + +/** +* \addtogroup group_dma_channel_functions +* \{ +*/ + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_SetDescriptor +****************************************************************************//** +* +* Sets a descriptor as current for specified DMA channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +* \param descriptor +* This is the descriptor which will be associated with the channel. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + CY_ASSERT_L1(NULL != descriptor); + + base->CH_STRUCT[channel].CH_CURR_PTR = (uint32_t)descriptor; + base->CH_STRUCT[channel].CH_IDX &= (uint32_t) ~(DW_CH_STRUCT_CH_IDX_X_IDX_Msk | DW_CH_STRUCT_CH_IDX_Y_IDX_Msk); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_Enable +****************************************************************************//** +* +* The function is used to enable a DMA channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + base->CH_STRUCT[channel].CH_CTL |= DW_CH_STRUCT_CH_CTL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_Disable +****************************************************************************//** +* +* The function is used to disable a DMA channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + base->CH_STRUCT[channel].CH_CTL &= (uint32_t) ~DW_CH_STRUCT_CH_CTL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_SetPriority +****************************************************************************//** +* +* The function is used to set a priority for the DMA channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +* \param priority +* The priority to be set for the DMA channel. The allowed values are 0,1,2,3. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel, uint32_t priority) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(priority)); + + base->CH_STRUCT[channel].CH_CTL = _CLR_SET_FLD32U(base->CH_STRUCT[channel].CH_CTL, DW_CH_STRUCT_CH_CTL_PRIO, priority); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetPriority +****************************************************************************//** +* +* Returns the priority of DMA channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +* \return +* The priority of the channel. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return ((uint32_t) _FLD2VAL(DW_CH_STRUCT_CH_CTL_PRIO, base->CH_STRUCT[channel].CH_CTL)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetCurrentDescriptor +****************************************************************************//** +* +* Returns the descriptor that is active in the channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +* \return +* The pointer to the descriptor that assocaited with the channel. +* +*******************************************************************************/ +__STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return ((cy_stc_dma_descriptor_t*)(base->CH_STRUCT[channel].CH_CURR_PTR)); +} + + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetInterruptStatus +****************************************************************************//** +* +* Returns the interrupt status of the specified channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +* \return +* The status of an interrupt for specified channel. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return (base->CH_STRUCT[channel].INTR); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetStatus +****************************************************************************//** +* +* Returns the interrupt reason of the specified channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +* \return +* A cause \ref cy_en_dma_intr_cause_t of an interrupt. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return ((cy_en_dma_intr_cause_t) _FLD2VAL(DW_CH_STRUCT_CH_STATUS_INTR_CAUSE, base->CH_STRUCT[channel].CH_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_ClearInterrupt +****************************************************************************//** +* +* Clears the interrupt status of the specified channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + base->CH_STRUCT[channel].INTR = CY_DMA_INTR_MASK; + (void) base->CH_STRUCT[channel].INTR; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_SetInterrupt +****************************************************************************//** +* +* Sets the interrupt for the specified channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + base->CH_STRUCT[channel].INTR_SET = CY_DMA_INTR_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetInterruptMask +****************************************************************************//** +* +* Returns interrupt mask value of the specified channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +* \return +* The interrupt mask value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return (base->CH_STRUCT[channel].INTR_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_SetInterruptMask +****************************************************************************//** +* +* Sets interrupt mask value for the specified channel. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +* \param interrupt +* An interrupt mask: +* CY_DMA_INTR_MASK to enable interrupt or 0UL to disable interrupt. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t channel, uint32_t interrupt) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + CY_ASSERT_L2(CY_DMA_IS_INTR_MASK_VALID(interrupt)); + base->CH_STRUCT[channel].INTR_MASK = interrupt; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetInterruptStatusMasked +****************************************************************************//** +* +* Returns logical AND of corresponding INTR and INTR_MASK fields +* in a single load operation. +* +* \param base +* A pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return (base->CH_STRUCT[channel].INTR_MASKED); +} + +/** \} group_dma_channel_functions */ + +/** \} group_dma_functions */ + + +/** \cond Definitions to support backward compatibility, they are strongly not recommended to use in new designs */ + +#if(CY_DMA_BWC) + + /* typedefs */ + #define cy_stc_dma_chnl_config_t cy_stc_dma_channel_config_t + #define cy_stc_dma_descr_t cy_stc_dma_descriptor_t + #define cy_stc_dma_descr_config_t cy_stc_dma_descriptor_config_t + #define cy_en_dma_trig_type_t cy_en_dma_trigger_type_t + + /* structure items */ + #define DMA_Descriptor descriptor + #define deact retrigger + #define intrType interruptType + #define chStateAtCmplt channelState + #define srcTxfrSize srcTransferSize + #define destTxfrSize dstTransferSize + #define trigoutType triggerOutType + #define triginType triggerInType + #define descrType descriptorType + #define srcAddr srcAddress + #define destAddr dstAddress + #define srcXincr srcXincrement + #define srcYincr srcYincrement + #define destXincr dstXincrement + #define destYincr dstYincrement + #define descrNext nextDescriptor + + /* constants */ + #define CY_DMA_CH_DISABLED (CY_DMA_CHANNEL_DISABLED) + #define CY_DMA_CH_ENABLED (CY_DMA_CHANNEL_ENABLED) + + #define CY_DMA_TXFR_SIZE_DATA_SIZE (CY_DMA_TRANSFER_SIZE_DATA) + #define CY_DMA_TXFR_SIZE_WORD (CY_DMA_TRANSFER_SIZE_WORD) + + #define CY_DMA_INTR_1ELEMENT_CMPLT (CY_DMA_1ELEMENT) + #define CY_DMA_INTR_X_LOOP_CMPLT (CY_DMA_X_LOOP) + #define CY_DMA_INTR_DESCR_CMPLT (CY_DMA_DESCR) + #define CY_DMA_INTR_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN) + + #define CY_DMA_TRIGOUT_1ELEMENT_CMPLT (CY_DMA_1ELEMENT) + #define CY_DMA_TRIGOUT_X_LOOP_CMPLT (CY_DMA_X_LOOP) + #define CY_DMA_TRIGOUT_DESCR_CMPLT (CY_DMA_DESCR) + #define CY_DMA_TRIGOUT_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN) + + #define CY_DMA_TRIGIN_1ELEMENT (CY_DMA_1ELEMENT) + #define CY_DMA_TRIGIN_XLOOP (CY_DMA_X_LOOP) + #define CY_DMA_TRIGIN_DESCR (CY_DMA_DESCR) + #define CY_DMA_TRIGIN_DESCRCHAIN (CY_DMA_DESCR_CHAIN) + + #define CY_DMA_INVALID_INPUT_PARAMETERS (CY_DMA_BAD_PARAM) + + /* descr struct items */ + #define DESCR_CTL ctl + #define DESCR_SRC src + #define DESCR_DST dst + #define DESCR_X_CTL xCtl + #define DESCR_Y_CTL yCtl + #define DESCR_NEXT_PTR nextPtr + + /* descr struct bitfields */ + #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL + #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL + #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Pos 2UL + #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Msk 0xCUL + #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Pos 4UL + #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL + #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Pos 6UL + #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL + #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Pos 24UL + #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL + #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL + #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL + #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL + #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL + #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Pos 28UL + #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk 0x30000000UL + #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Pos 30UL + #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Msk 0xC0000000UL + #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Pos 0UL + #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL + #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Pos 0UL + #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Msk 0xFFFFFFFFUL + #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Pos 0UL + #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Msk 0xFFFUL + #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Pos 12UL + #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Msk 0xFFF000UL + #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Pos 24UL + #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Msk 0xFF000000UL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Pos 0UL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Msk 0xFFFUL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Pos 12UL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Msk 0xFFF000UL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Pos 24UL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Msk 0xFF000000UL + #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Pos 2UL + #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL + + /* functions */ + #define Cy_DMA_GetActiveChnl Cy_DMA_GetActiveChannel + #define Cy_DMA_GetActiveSrcAddr Cy_DMA_GetActiveSrcAddress + #define Cy_DMA_GetActiveDstAddr Cy_DMA_GetActiveDstAddress + #define Cy_DMA_Descr_Init Cy_DMA_Descriptor_Init + #define Cy_DMA_Descr_DeInit Cy_DMA_Descriptor_DeInit + #define Cy_DMA_Descr_SetSrcAddr Cy_DMA_Descriptor_SetSrcAddress + #define Cy_DMA_Descr_SetDestAddr Cy_DMA_Descriptor_SetDstAddress + #define Cy_DMA_Descr_SetNxtDescr Cy_DMA_Descriptor_SetNextDescriptor + #define Cy_DMA_Descr_SetIntrType Cy_DMA_Descriptor_SetInterruptType + #define Cy_DMA_Descr_SetTrigInType Cy_DMA_Descriptor_SetTriggerInType + #define Cy_DMA_Descr_SetTrigOutType Cy_DMA_Descriptor_SetTriggerOutType + #define Cy_DMA_Chnl_Init Cy_DMA_Channel_Init + #define Cy_DMA_Chnl_DeInit Cy_DMA_Channel_DeInit + #define Cy_DMA_Chnl_SetDescr Cy_DMA_Channel_SetDescriptor + #define Cy_DMA_Chnl_Enable Cy_DMA_Channel_Enable + #define Cy_DMA_Chnl_Disable Cy_DMA_Channel_Disable + #define Cy_DMA_Chnl_GetCurrentDescr Cy_DMA_Channel_GetCurrentDescriptor + #define Cy_DMA_Chnl_SetPriority Cy_DMA_Channel_SetPriority + #define Cy_DMA_Chnl_GetPriority Cy_DMA_Channel_GetPriority + #define Cy_DMA_Chnl_GetInterruptStatus Cy_DMA_Channel_GetInterruptStatus + #define Cy_DMA_Chnl_GetInterruptCause Cy_DMA_Channel_GetStatus + #define Cy_DMA_Chnl_ClearInterrupt Cy_DMA_Channel_ClearInterrupt + #define Cy_DMA_Chnl_SetInterrupt Cy_DMA_Channel_SetInterrupt + #define Cy_DMA_Chnl_GetInterruptMask Cy_DMA_Channel_GetInterruptMask + #define Cy_DMA_Chnl_GetInterruptStatusMasked Cy_DMA_Channel_GetInterruptStatusMasked + #define Cy_DMA_Chnl_SetInterruptMask(base, channel) (Cy_DMA_Channel_SetInterruptMask(base, channel, CY_DMA_INTR_MASK)) + + +/******************************************************************************* +* Function Name: Cy_DMA_Descr_SetTxfrWidth +****************************************************************************//** +* This is a legacy API function, it is left here just for backward compatibility +* It is strongly not recommended to use in new designs. +*******************************************************************************/ + __STATIC_INLINE void Cy_DMA_Descr_SetTxfrWidth(cy_stc_dma_descr_t * descriptor, + uint32_t dataElementSize, + uint32_t srcTxfrWidth, + uint32_t dstTxfrWidth) + { + uint32_t regValue; + regValue = descriptor->ctl & ((uint32_t)(~(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk | + DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk | + DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk))); + + descriptor->ctl = regValue | + _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE, dataElementSize) | + _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE, srcTxfrWidth) | + _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE, dstTxfrWidth); + } + +#endif /* CY_DMA_BWC */ + +/** \endcond */ + + +#if defined(__cplusplus) +} +#endif + +#endif /* (CY_DMA_H) */ + +/** \} group_dma */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/flash/cy_flash.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/flash/cy_flash.c new file mode 100644 index 0000000000..3dc80147a8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/flash/cy_flash.c @@ -0,0 +1,886 @@ +/***************************************************************************//** +* \file cy_flash.c +* \version 2.0 +* +* \brief +* Provides the public functions for the API for the PSoC 6 Flash Driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_flash.h" + + +/** \cond INTERNAL */ +/** Slow control register */ +#define CY_FLASH_TST_DDFT_SLOW_CTL_REG (*(reg32 *) 0x40260108U) +/** Slow control register */ +#define CY_FLASH_TST_DDFT_FAST_CTL_REG (*(reg32 *) 0x40260104U) +/** Slow output register */ +#define CY_FLASH_CLK_OUTPUT_SLOW_REG (*(reg32 *) 0x40260518U) +/** Slow clock calibration register */ +#define CY_FLASH_CLK_CAL_CNT1_REG (*(reg32 *) 0x4026051CU) +/** Define to set the IMO to perform a delay after the flash operation started */ +#define CY_FLASH_TST_DDFT_SLOW_CTL_MASK (0x40001F1EU) +/** Slow output register */ +#define CY_FLASH_CLK_OUTPUT_SLOW_MASK (0x06U) +/** Define to indicate that clock is finished counting */ +#define CY_FLASH_CLK_CAL_CNT1_DONE ((uint32_t) ((uint32_t) 1U << CY_FLASH_CLK_CAL_CNT1_DONE_POS)) +/** Define to indicate that clock is finished counting */ +#define CY_FLASH_CLK_CAL_CNT1_DONE_POS (31U) +/* Calculates the time in microseconds to wait for the number of the CM0P ticks */ +#define CY_FLASH_DEL_CORRECTIVE(ticks) ((((uint32)Cy_SysClk_ClkPeriGetDivider() + 1UL) * (Cy_SysClk_ClkSlowGetDivider() + 1UL) * (ticks) * 1000UL)\ + / ((uint32_t)cy_Hfclk0FreqHz / 1000UL)) +/* Number of the CM0P ticks for StartWrite function delay corrective time */ +#define CY_FLASH_START_WRITE_DEL_TICKS (19000UL) +/* Number of the CM0P ticks for StartProgram function delay corrective time */ +#define CY_FLASH_START_PROGRAM_DEL_TICKS (5250UL) +/* Number of the CM0P ticks for StartErase function delay corrective time */ +#define CY_FLASH_START_ERASE_DEL_TICKS (8500UL) +/* Delay time for StartWrite function in us */ +#define CY_FLASH_START_WRITE_DEL_TIME (9800UL) +/* Delay time for StartProgram function in us */ +#define CY_FLASH_START_PROGRAM_DEL_TIME (120UL) +/* Delay time for StartErase function in us */ +#define CY_FLASH_START_ERASE_DEL_TIME (1000UL) +/** Delay time for Start Write function in us with corrective time */ +#define CY_FLASH_START_WRITE_DELAY (uint32_t)(CY_FLASH_START_WRITE_DEL_TIME +\ + CY_FLASH_DEL_CORRECTIVE(CY_FLASH_START_WRITE_DEL_TICKS)) +/** Delay time for Start Program function in us with corrective time */ +#define CY_FLASH_START_PROGRAM_DELAY (uint32_t)(CY_FLASH_START_PROGRAM_DEL_TIME +\ + CY_FLASH_DEL_CORRECTIVE(CY_FLASH_START_PROGRAM_DEL_TICKS)) +/** Delay time fot Start Erase function in uS with corrective time */ +#define CY_FLASH_START_ERASE_DELAY (uint32_t)(CY_FLASH_START_ERASE_DEL_TIME +\ + CY_FLASH_DEL_CORRECTIVE(CY_FLASH_START_ERASE_DEL_TICKS)) +/** Number of ticks to wait 1 uS */ +#define CY_FLASH_TICKS_FOR_1US (8U) +/** Disable delay */ +#define CY_FLASH_NO_DELAY (0U) +/** Slow control register */ +#define CY_FLASH_TST_DDFT_FAST_CTL_MASK (62U) +/** Command completed with no errors */ +#define CY_FLASH_ROMCODE_SUCCESS (0xA0000000UL) +/** Invalid device protection state */ +#define CY_FLASH_ROMCODE_INVALID_PROTECTION (0xF0000001UL) +/** Invalid flash page latch address */ +#define CY_FLASH_ROMCODE_INVALID_FM_PL (0xF0000003UL) +/** Invalid flash address */ +#define CY_FLASH_ROMCODE_INVALID_FLASH_ADDR (0xF0000004UL) +/** Row is write protected */ +#define CY_FLASH_ROMCODE_ROW_PROTECTED (0xF0000005UL) +/** Comparison between Page Latches and FM row failed */ +#define CY_FLASH_ROMCODE_PL_ROW_COMP_FA (0xF0000022UL) +/** Command in progress; no error */ +#define CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR (0xA0000009UL) +/** Flash operation is successfully initiated */ +#define CY_FLASH_IS_OPERATION_STARTED (0x00000010UL) +/** Flash is under operation */ +#define CY_FLASH_IS_BUSY (0x00000040UL) +/** IPC structure is already locked by another process */ +#define CY_FLASH_IS_IPC_BUSY (0x00000080UL) +/** Input parameters passed to Flash API are not valid */ +#define CY_FLASH_IS_INVALID_INPUT_PARAMETERS (0x00000100UL) +/** Result mask */ +#define CY_FLASH_RESULT_MASK (0xFFFFFFFUL) +/** Error shift */ +#define CY_FLASH_ERROR_SHIFT (28UL) +/** No error */ +#define CY_FLASH_ERROR_NO_ERROR (0xAUL) +/** CM4 Flash Proxy address */ +#define CY_FLASH_CM4_FLASH_PROXY_ADDR (0x00007001UL) + +#if (CY_CPU_CORTEX_M0P) +#define IS_CY_PIPE_FREE(...) (!Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_INTR_CYPIPE_EP1))) +#define NOTIFY_PEER_CORE(a) Cy_IPC_Pipe_SendMessage(CY_IPC_EP_CYPIPE_CM4_ADDR, CY_IPC_EP_CYPIPE_CM0_ADDR, a, NULL) +#else +#define IS_CY_PIPE_FREE(...) (!Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_INTR_CYPIPE_EP0))) +#define NOTIFY_PEER_CORE(a) Cy_IPC_Pipe_SendMessage(CY_IPC_EP_CYPIPE_CM0_ADDR, CY_IPC_EP_CYPIPE_CM4_ADDR, a, NULL) +#endif +/** \endcond */ + +/* Static functions */ +static bool Cy_Flash_BoundsCheck(uint32_t flashAddr); +static uint32_t Cy_Flash_PrepareContext(uint32_t rowAddr, const uint32_t *data, uint32_t blocking); +static cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode); +static cy_en_flashdrv_status_t Cy_Flash_OperationStatus(void); +static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microseconds); +static void Cy_Flash_RAMDelay(uint32_t microseconds); +static cy_stc_flash_context_t context; + +/** \cond INTERNAL */ +CY_ALIGN(4) static IPC_MSG ipcWaitMessage = +{ + /* .clientID */ CY_FLASH_IPC_CLIENT_ID, + /* .pktType */ CY_FLASH_ENTER_WAIT_LOOP, + /* .intrRelMask */ 0 +}; +/** \endcond */ + +/******************************************************************************* +* Function Name: Cy_Flash_SendCmd +****************************************************************************//** +* +* Sends a command to the SROM via the IPC channel. The function is placed to the +* SRAM memory to guarantee successful operation. After an IPC message is sent, +* the function waits for a defined time before exiting the function. +* +* \param mode Sets the blocking or non-blocking Flash operation. +* +* \param microseconds The number of microseconds to wait before exiting the functions. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +#if defined (__ICCARM__) + __ramfunc +#else + CY_SECTION(".cy_ramfunc") +#endif +static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microseconds) +{ + uint32_t intr; + cy_en_flashdrv_status_t result = CY_FLASH_DRV_IPC_BUSY; + + if (IS_CY_PIPE_FREE()) + { + if (CY_IPC_SEMA_STATUS_LOCKED != Cy_IPC_Sema_Status(CY_FLASH_WAIT_SEMA)) + { + if (CY_IPC_PIPE_SUCCESS == NOTIFY_PEER_CORE(&ipcWaitMessage)) + { + /* Wait for SEMA lock by peer core */ + while(CY_IPC_SEMA_STATUS_LOCKED != Cy_IPC_Sema_Status(CY_FLASH_WAIT_SEMA)) + { + } + + intr = Cy_SysLib_EnterCriticalSection(); + + /* Tries to acquire the IPC structure and pass the arguments to SROM API */ + if (Cy_IPC_Drv_SendMsgPtr(CY_FLASH_IPC_STRUCT, CY_FLASH_IPC_NOTIFY_STRUCT0, (void*)&context) == CY_IPC_DRV_SUCCESS) + { + if (mode == CY_FLASH_NON_BLOCKING_MODE) + { + Cy_Flash_RAMDelay(microseconds); + + /* The Flash operation is successfully initiated */ + result = CY_FLASH_DRV_OPERATION_STARTED; + } + else + { + /* Polls whether the IPC is released and the Flash operation is performed */ + do + { + result = Cy_Flash_IsWriteComplete(); + } + while (result == CY_FLASH_DRV_OPCODE_BUSY); + } + } + else + { + /* The IPC structure is already locked by another process */ + result = CY_FLASH_DRV_IPC_BUSY; + } + + while ( CY_IPC_SEMA_SUCCESS != Cy_IPC_Sema_Clear(CY_FLASH_WAIT_SEMA, false)) + { + } + + Cy_SysLib_ExitCriticalSection(intr); + } + } + } + + return (result); +} + +/******************************************************************************* +* Function Name: Cy_Flash_EraseRow +****************************************************************************//** +* +* This function erases a single row of flash. Reports success or +* a reason for failure. Does not return until the Write operation is +* complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in +* the case when another process is writing to flash or erasing the row. +* User firmware should not enter the hibernate mode until flash erase is +* complete. The Flash operation is allowed in Sleep and Deep-sleep modes. +* During the Flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage +* detect circuits should be configured to generate an interrupt instead of a +* reset. Otherwise, portions of flash may undergo unexpected changes. +* +* \param rowAddr Address of the flash row number. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* Address must match row start address. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +* \sideeffect If this function is called by the CM4 the user code on CM0P and +* the user code on CM4 are blocked until erase flash row operation is finished. +* If this function is called by the CM0P the user code on CM4 is not blocked and +* the user code on CM0P is blocked until erase flash row operation is finished. +* Plan your task allocation accordingly. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr) +{ + cy_en_flashdrv_status_t result; + + /* Prepares arguments to be passed to SROM API */ + if (Cy_Flash_BoundsCheck(rowAddr) != false) + { + context.opcode = CY_FLASH_OPCODE_ERASE_ROW | CY_FLASH_BLOCKING_MODE; + context.arg1 = rowAddr; + context.arg2 = 0UL; + context.arg3 = 0UL; + +#if (CY_CPU_CORTEX_M0P) + result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_NO_DELAY); +#else + Cy_Flash_Proxy Cy_Flash_Cm4Proxy; + Cy_Flash_Cm4Proxy = (Cy_Flash_Proxy)CY_FLASH_CM4_FLASH_PROXY_ADDR; + result = Cy_Flash_Cm4Proxy(&context); + result = Cy_Flash_ProcessOpcode((uint32_t)result); + +#endif /* (CY_CPU_CORTEX_M0P) */ + } + else + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_WriteRow +****************************************************************************//** +* +* This function writes an array of data to a single row of flash. +* Reports success or a reason for failure. Does not return until the Write +* operation is complete. +* Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case +* when another process is writing to flash. User firmware should not enter the +* hibernate mode until flash Write is complete. The Flash operation is allowed +* in Sleep and Deep-sleep modes. During the Flash operation, the device should +* not be reset, including the XRES pin, a software reset, and watchdog reset +* sources. Also, low-voltage detect circuits should be configured to generate +* an interrupt instead of a reset. Otherwise, portions of flash may undergo +* unexpected changes. +* +* \param rowAddr Address of the flash row number. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* Address must match row start address. +* +* \param data The pointer to the data which has to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +* \sideeffect If this function is called by the CM4 the user code on CM0P and +* the user code on CM4 are blocked until erase flash row operation is finished. +* If this function is called by the CM0P the user code on CM4 is not blocked and +* the user code on CM0P is blocked until erase flash row operation is finished. +* Plan your task allocation accordingly. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data) +{ + cy_en_flashdrv_status_t result; + +#if (CY_CPU_CORTEX_M0P) + /* Checks whether the input parameters are valid */ + if (Cy_Flash_PrepareContext(rowAddr, data, CY_FLASH_BLOCKING_MODE) != (uint32_t)CY_FLASH_DRV_INVALID_INPUT_PARAMETERS) + { + result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_NO_DELAY); + } + else + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + +#else + if (Cy_Flash_PrepareContext(rowAddr, data, CY_FLASH_BLOCKING_MODE) != (uint32_t)CY_FLASH_DRV_INVALID_INPUT_PARAMETERS) + { + Cy_Flash_Proxy Cy_Flash_Cm4Proxy; + Cy_Flash_Cm4Proxy = (Cy_Flash_Proxy)CY_FLASH_CM4_FLASH_PROXY_ADDR; + result = Cy_Flash_Cm4Proxy(&context); + result = Cy_Flash_ProcessOpcode((uint32_t)result); + } + else + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } +#endif /* (CY_CPU_CORTEX_M0P) */ + + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_StartWrite +****************************************************************************//** +* +* Starts writing an array of data to a single row of flash. Returns immediately +* and reports a successful start or reason for failure. Returns immediately and +* reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when another process is writing +* to flash. User firmware should not enter the hibernate mode until flash Write +* is complete. The Flash operation is allowed in Sleep and Deep-sleep modes. +* During the flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage +* detect circuits should be configured to generate an interrupt instead of a reset. +* Otherwise, portions of flash may undergo unexpected changes. +* \note Before reading data from previously programmed/erased flash rows, the +* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* function. +* +* \param rowAddr Address of the flash row number. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* Address must match row start address. +* +* \param data The pointer to the data to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data) +{ + cy_en_flashdrv_status_t result; + + /* Checks whether the input parameters are valid */ + if (Cy_Flash_PrepareContext(rowAddr, data, CY_FLASH_NON_BLOCKING_MODE) != (uint32_t)CY_FLASH_DRV_INVALID_INPUT_PARAMETERS) + { + result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_WRITE_DELAY); + } + else + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_IsWriteComplete +****************************************************************************//** +* +* Reports a successful Write, reason of failure or busy status +* ( \ref CY_FLASH_DRV_OPCODE_BUSY ). +* +* \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_IsWriteComplete(void) +{ + return (Cy_Flash_OperationStatus()); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_StartErase +****************************************************************************//** +* +* Starts erasing a single row of flash. Returns immediately +* and reports a successful start or reason for failure. Returns immediately and +* reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when IPC structure is locked +* by another process. User firmware should not enter the hibernate mode until +* flash Erase is complete. The Flash operation is allowed in Sleep and Deep-sleep modes. +* During the flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage +* detect circuits should be configured to generate an interrupt instead of a reset. +* Otherwise, portions of flash may undergo unexpected changes. +* \note Before reading data from previously programmed/erased flash rows, the +* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* function. +* +* \param rowAddr Address of the flash row number. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash erase operation is +* performing. Refer to the device datasheet for the details. +* Address must match row start address. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_StartErase(uint32_t rowAddr) +{ + cy_en_flashdrv_status_t retVal; + + /* Prepares arguments to be passed to SROM API */ + if (Cy_Flash_BoundsCheck(rowAddr) != false) + { + context.opcode = CY_FLASH_OPCODE_ERASE_ROW; + context.arg1 = rowAddr; + context.arg2 = 0UL; + context.arg3 = 0UL; + retVal = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY); + } + else + { + retVal = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_IsEraseComplete +****************************************************************************//** +* +* Reports a successful Erase, reason of failure or busy status +* ( \ref CY_FLASH_DRV_OPCODE_BUSY ). +* +* \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_IsEraseComplete(void) +{ + return (Cy_Flash_OperationStatus()); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_StartProgram +****************************************************************************//** +* Starts writing an array of data to a single row of flash. Returns immediately +* and reports a successful start or reason for failure. Returns immediately and +* reports a \ref CY_FLASH_DRV_IPC_BUSY error if another process is writing +* to flash. The user firmware should not enter Hibernate mode until flash Write +* is complete. The Flash operation is allowed in Sleep and Deep-Sleep modes. +* During the Flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage +* detect circuits should be configured to generate an interrupt instead of a reset. +* Otherwise, portions of flash may undergo unexpected changes.\n +* Before calling this function, the target flash region must be erased by +* the StartErase/EraseRow function.\n +* Data to be programmed must be located in the SRAM memory region. +* \note Before reading data from previously programmed/erased flash rows, the +* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* function. +* +* \param rowAddr The address of the flash row number. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the Flash Write operation is +* performing. Refer to the device datasheet for the details. +* The address must match the row start address. +* +* \param data The pointer to the data to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data) +{ + cy_en_flashdrv_status_t result; + + /* Prepares arguments to be passed to SROM API */ + if (Cy_Flash_BoundsCheck(rowAddr) != false) + { + context.opcode = CY_FLASH_OPCODE_PROGRAM_ROW | CY_FLASH_NON_BLOCKING_MODE; + context.arg1 = CY_FLASH_CONFIG_DATASIZE | CY_FLASH_DATA_LOC_SRAM; + context.arg2 = rowAddr; + context.arg3 = (uint32_t)data; + + result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_PROGRAM_DELAY); + } + else + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_IsProgramComplete +****************************************************************************//** +* +* Reports a successful program operation, failure or busy status +* ( \ref CY_FLASH_DRV_OPCODE_BUSY ). +* +* \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_IsProgramComplete(void) +{ + return (Cy_Flash_OperationStatus()); +} + +/******************************************************************************* +* Function Name: Cy_Flash_RowChecksum +****************************************************************************//** +* +* Returns a checksum value of the specified flash row. +* +* \param rowNum The Checksum is calculated to the flash row. +* +* \param checksumPtr The pointer to the address where checksum is to be stored +* +* \return Returns the status of the Flash operation. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_RowChecksum (uint32_t rowNum, uint32_t* checksumPtr) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + uint32_t resTmp; + + /* Checks whether the input parameters are valid */ + if (rowNum < CY_FLASH_NUMBER_ROWS) + { + /* Prepares arguments to be passed to SROM API */ + context.opcode = CY_FLASH_OPCODE_CHECKSUM | (rowNum << CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT); + + /* Tries to acquire the IPC structure and pass the arguments to SROM API */ + if (Cy_IPC_Drv_SendMsgPtr(CY_FLASH_IPC_STRUCT, CY_FLASH_IPC_NOTIFY_STRUCT0, (void*)&context) == CY_IPC_DRV_SUCCESS) + { + /* Polls whether IPC is released and the Flash operation is performed */ + while (Cy_IPC_Drv_IsLockAcquired(CY_FLASH_IPC_STRUCT) != false) + { + /* Wait till IPC is released */ + } + + resTmp = context.opcode; + + if((resTmp >> CY_FLASH_ERROR_SHIFT) == CY_FLASH_ERROR_NO_ERROR) + { + result = CY_FLASH_DRV_SUCCESS; + *checksumPtr = context.opcode & CY_FLASH_RESULT_MASK; + } + } + else + { + /* The IPC structure is already locked by another process */ + result = CY_FLASH_DRV_IPC_BUSY; + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_CalculateHash +****************************************************************************//** +* +* Returns a hash value of the specified region of flash. +* +* \param data Start the data address. +* +* \param numberOfBytes The hash value is calculated for the number of bytes after the +* start data address (0 - 1 byte, 1- 2 bytes etc). +* +* \param hashPtr The pointer to the address where hash is to be stored +* +* \return Returns the status of the Flash operation. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_CalculateHash (const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + volatile uint32_t resTmp; + + /* Checks whether the input parameters are valid */ + if (data != NULL) + { + /* Prepares arguments to be passed to SROM API */ + context.opcode = CY_FLASH_OPCODE_HASH; + context.arg1 = (uint32_t)data; + context.arg2 = numberOfBytes; + + /* Tries to acquire the IPC structure and pass the arguments to SROM API */ + if (Cy_IPC_Drv_SendMsgPtr(CY_FLASH_IPC_STRUCT, CY_FLASH_IPC_NOTIFY_STRUCT0, (void*)&context) == CY_IPC_DRV_SUCCESS) + { + /* Polls whether IPC is released and the Flash operation is performed */ + while (Cy_IPC_Drv_IsLockAcquired(CY_FLASH_IPC_STRUCT) != false) + { + /* Wait till IPC is released */ + } + + resTmp = context.opcode; + + if((resTmp >> CY_FLASH_ERROR_SHIFT) == CY_FLASH_ERROR_NO_ERROR) + { + result = CY_FLASH_DRV_SUCCESS; + *hashPtr = context.opcode & CY_FLASH_RESULT_MASK; + } + } + else + { + /* The IPC structure is already locked by another process */ + result = CY_FLASH_DRV_IPC_BUSY; + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_BoundsCheck +****************************************************************************//** +* +* Returns false if Flash address is out of boundary, otherwise returns true. +* +* \param flashAddr Address to be checked +* +* \return false - out of bound, true - in flash bounds +* +*******************************************************************************/ +static bool Cy_Flash_BoundsCheck(uint32_t flashAddr) +{ + bool result = true; + + if ((flashAddr < CY_FLASH_BASE) || (flashAddr >= (CY_FLASH_BASE + CY_FLASH_SIZE))) + { + if ((flashAddr < CY_WFLASH_BASE) || (flashAddr >= (CY_WFLASH_BASE + CY_WFLASH_SIZE))) + { + if ((flashAddr < SFLASH_BASE) || (flashAddr >= (SFLASH_BASE + SFLASH_SECTION_SIZE))) + { + result = false; + } + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_PrepareContext +****************************************************************************//** +* +* Returns 1 if parameters are correct and initialises context, otherwise returns +* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS. +* +* \param rowAddr Address of the flash row number. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* Address must match row start address. +* +* \param data The pointer to the data which has to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \param blocking The parameter of how the context will be executed. +* * 1 - blocking, If this function is called by the CM4 the user code on CM0P +* and the user code on CM4 are blocked until flash write operation is finished. +* If this function is called by the CM0P the user code on CM4 is not blocked +* and the user code on CM0P is blocked until flash write operation is finished. +* * 0 - non-blocking, the user code is not blocked while flash write operation +* is executed. +* +* \return 1 - Context ready, CY_FLASH_DRV_INVALID_INPUT_PARAMETERS - Wrong +* arguments +* +*******************************************************************************/ +static uint32_t Cy_Flash_PrepareContext(uint32_t rowAddr, const uint32_t* data, uint32_t blocking) +{ + uint32_t result; + + if ((Cy_Flash_BoundsCheck(rowAddr) == false) || (NULL == data)) + { + result = (uint32_t)CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + else + { + if ((rowAddr%CY_FLASH_SIZEOF_ROW) != 0UL) + { + result = (uint32_t)CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + } + else + { + /* Prepares arguments to be passed to SROM API */ + context.opcode = CY_FLASH_OPCODE_WRITE_ROW | blocking; + context.arg1 = CY_FLASH_CONFIG_DATASIZE; + context.arg2 = rowAddr; + context.arg3 = (uint32_t)data; + + result = 1UL; + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_ProcessOpcode +****************************************************************************//** +* +* Converts System Call returns to the Flash driver return defines. +* +* \param opcode The value returned by the System Call. +* +* \return Flash driver return. +* +*******************************************************************************/ +static cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode) +{ + cy_en_flashdrv_status_t retVal; + + switch (opcode) + { + case 0UL: + { + retVal = CY_FLASH_DRV_SUCCESS; + break; + } + case CY_FLASH_ROMCODE_SUCCESS: + { + retVal = CY_FLASH_DRV_SUCCESS; + break; + } + case CY_FLASH_ROMCODE_INVALID_PROTECTION: + { + retVal = CY_FLASH_DRV_INV_PROT; + break; + } + case CY_FLASH_ROMCODE_INVALID_FM_PL: + { + retVal = CY_FLASH_DRV_INVALID_FM_PL; + break; + } + case CY_FLASH_ROMCODE_INVALID_FLASH_ADDR: + { + retVal = CY_FLASH_DRV_INVALID_FLASH_ADDR; + break; + } + case CY_FLASH_ROMCODE_ROW_PROTECTED: + { + retVal = CY_FLASH_DRV_ROW_PROTECTED; + break; + } + case CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR: + { + retVal = CY_FLASH_DRV_PROGRESS_NO_ERROR; + break; + } + case (uint32_t)CY_FLASH_DRV_INVALID_INPUT_PARAMETERS: + { + retVal = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + break; + } + case CY_FLASH_IS_OPERATION_STARTED : + { + retVal = CY_FLASH_DRV_OPERATION_STARTED; + break; + } + case CY_FLASH_IS_BUSY : + { + retVal = CY_FLASH_DRV_OPCODE_BUSY; + break; + } + case CY_FLASH_IS_IPC_BUSY : + { + retVal = CY_FLASH_DRV_IPC_BUSY; + break; + } + case CY_FLASH_IS_INVALID_INPUT_PARAMETERS : + { + retVal = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + break; + } + default: + { + retVal = CY_FLASH_DRV_ERR_UNC; + break; + } + } + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_OperationStatus +****************************************************************************//** +* +* Checks the status of the Flash Operation, and returns it. +* +* \return Returns the status of the Flash operation +* (see \ref cy_en_flashdrv_status_t). +* +*******************************************************************************/ +static cy_en_flashdrv_status_t Cy_Flash_OperationStatus(void) +{ + cy_en_flashdrv_status_t retVal = CY_FLASH_DRV_OPCODE_BUSY; + + /* Checks if the IPC structure is not locked */ + if (Cy_IPC_Drv_IsLockAcquired(CY_FLASH_IPC_STRUCT) == false) + { + /* The result of SROM API calling is returned to the driver context */ + retVal = Cy_Flash_ProcessOpcode(context.opcode); + } + + return (retVal); +} + +/******************************************************************************* +* Function Name: Cy_Flash_RAMDelay +****************************************************************************//** +* +* Wait for a defined time in the SRAM memory region. +* +*******************************************************************************/ +#if defined (__ICCARM__) + __ramfunc +#else + CY_SECTION(".cy_ramfunc") +#endif +static void Cy_Flash_RAMDelay(uint32_t microseconds) +{ + uint32_t ticks = microseconds * CY_FLASH_TICKS_FOR_1US; + if (ticks != CY_FLASH_NO_DELAY) + { + CY_FLASH_TST_DDFT_SLOW_CTL_REG = CY_FLASH_TST_DDFT_SLOW_CTL_MASK; + CY_FLASH_CLK_OUTPUT_SLOW_REG = CY_FLASH_CLK_OUTPUT_SLOW_MASK; + CY_FLASH_TST_DDFT_FAST_CTL_REG = CY_FLASH_TST_DDFT_FAST_CTL_MASK; + + /* Load the down-counter */ + CY_FLASH_CLK_CAL_CNT1_REG = ticks; + + /* Make sure that the counter is started */ + (void) CY_FLASH_CLK_CAL_CNT1_REG; + + while(0U == (CY_FLASH_CLK_CAL_CNT1_REG & CY_FLASH_CLK_CAL_CNT1_DONE)) + { + /* Wait until the counter stops counting */ + } + } +} + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/flash/cy_flash.h similarity index 57% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.h rename to targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/flash/cy_flash.h index c9cb738718..a200f8dcef 100644 --- a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/flash/cy_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/flash/cy_flash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_flash.h -* \version 1.0 +* \version 2.0 * * Provides the API declarations of the Flash driver. * @@ -45,10 +45,19 @@ * Use different flash sectors for code and data storage. The flash is divided * into four equal sectors. * +* \warning If the CM0 core triggers the Flash operation, another core must be in +* Active mode and interrupts must be enabled in both cores. +* +* \note "Warning[Ta023]: Call to a non __ramfunc function." - The warning may +* appear during the build process while using IAR IDE. The reason - some +* functions in RAM memory that use the __ramfunc keyword, may invoke +* functions located in the ROM memory. You can ignore this warning or +* disable it by adding the --diag_suppress=Ta023 option to the compiler. +* * \section group_flash_configuration Configuration Considerations * -* There are no specific configuration parameters for the flash operations -* outside the driver API input parameters. +* Note that to be able to perform FLASH writes, the VCCD should be more than 0.99 V. +* For more information see the technical reference manual (TRM). * * \section group_flash_more_information More Information * @@ -56,20 +65,28 @@ * * \section group_flash_MISRA MISRA-C Compliance * -* The Flash driver has the following specific deviations: -* * * * * * -* +* * * -* -* -* -* +* +* +* +* +* +* +* +* +* +* * *
    MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)Description of Deviation(s)
    19.7AA function shall be used in preference to a function-like macroMacro is used because of performance reasons5.6RNo identifier in one name space can have the same spelling as an identifier in another name space, with the +* exception of structure member and union member names.The "context" is used as a structure/union member; they are a label, tag or ordinary +* identifier.
    8.7RObjects shall be defined at block scope if they are only accessed +* from within a single function.The driver defines an internal variable that can be accessed by +* any core through the IPC hardware.
    * @@ -82,120 +99,97 @@ * Initial version * * +* +* 2.0 +* Added non-blocking erase functions ( Cy_Flash_StartErase() and +* Cy_Flash_IsEraseComplete() ). Removed the clear cache function +* call. +* The clear cache operation is removed from the blocking Write/Erase +* function because in this case it is performed by the hardware. +* Otherwise it is documented that it is the user's responsibility to +* clear the cache after executing the non-blocking Write/Erase flash +* operation. +* * * -* \defgroup group_flash_macro Macro +* \defgroup group_flash_macros Macros * \defgroup group_flash_functions Functions * \defgroup group_flash_data_structure Data Structures +* \defgroup group_flash_enumerated_types Enumerated Types */ #include -#include #include +#include +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif /*************************************** * Macro definitions ***************************************/ /** -* \addtogroup group_flash_macro +* \addtogroup group_flash_macros * \{ */ /** Driver major version */ -#define CY_FLASH_DRV_VERSION_MAJOR 1 +#define CY_FLASH_DRV_VERSION_MAJOR 2 /** Driver minor version */ #define CY_FLASH_DRV_VERSION_MINOR 0 -/** -* \defgroup group_flash_returns Flash return values -* \{ -* Specifies return values meaning -*/ -#define CY_FLASH_ID (CY_PDL_DRV_ID(0x14u)) /**< FLASH PDL ID */ +#define CY_FLASH_ID (CY_PDL_DRV_ID(0x14UL)) /**< FLASH PDL ID */ #define CY_FLASH_ID_INFO (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_INFO ) /**< Return prefix for FLASH driver function status codes */ #define CY_FLASH_ID_WARNING (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_WARNING) /**< Return prefix for FLASH driver function warning return values */ #define CY_FLASH_ID_ERROR (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_ERROR) /**< Return prefix for FLASH driver function error return values */ -/** This enum has the return values of the Flash driver */ -typedef enum -{ - CY_FLASH_DRV_SUCCESS = 0x00ul, /**< Success */ - CY_FLASH_DRV_INV_PROT = ( CY_FLASH_ID_ERROR + 0ul), /**< Invalid device protection state */ - CY_FLASH_DRV_INVALID_FM_PL = ( CY_FLASH_ID_ERROR + 1ul), /**< Invalid flash page latch address */ - CY_FLASH_DRV_INVALID_FLASH_ADDR = ( CY_FLASH_ID_ERROR + 2ul), /**< Invalid flash address */ - CY_FLASH_DRV_ROW_PROTECTED = ( CY_FLASH_ID_ERROR + 3ul), /**< Row is write protected */ - CY_FLASH_DRV_IPC_BUSY = ( CY_FLASH_ID_ERROR + 5ul), /**< IPC structure is already locked by another process */ - CY_FLASH_DRV_INVALID_INPUT_PARAMETERS = ( CY_FLASH_ID_ERROR + 6ul), /**< Input parameters passed to Flash API are not valid */ - CY_FLASH_DRV_ERR_UNC = ( CY_FLASH_ID_ERROR + 0xFul),/**< Unknown error */ - CY_FLASH_DRV_PROGRESS_NO_ERROR = ( CY_FLASH_ID_INFO + 0ul), /**< Command in progress; no error */ - CY_FLASH_DRV_OPERATION_STARTED = ( CY_FLASH_ID_INFO + 1ul), /**< Flash operation is successfully initiated */ - CY_FLASH_DRV_OPCODE_BUSY = ( CY_FLASH_ID_INFO + 2ul), /**< Flash is under operation */ -} cy_en_flashdrv_status_t; - -/** \} group_flash_returns */ - /** \cond INTERNAL */ -/** Command completed with no errors */ -#define CY_FLASH_ROMCODE_SUCCESS (0xA0000000UL) -/** Invalid device protection state */ -#define CY_FLASH_ROMCODE_INVALID_PROTECTION (0xF0000001UL) -/** Invalid flash page latch address */ -#define CY_FLASH_ROMCODE_INVALID_FM_PL (0xF0000003UL) -/** Invalid flash address */ -#define CY_FLASH_ROMCODE_INVALID_FLASH_ADDR (0xF0000004UL) -/** Row is write protected */ -#define CY_FLASH_ROMCODE_ROW_PROTECTED (0xF0000005UL) -/** Command in progress; no error */ -#define CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR (0xA0000009UL) -/** Flash operation is successfully initiated */ -#define CY_FLASH_IS_OPERATION_STARTED (0x00000010UL) -/** Flash is under operation */ -#define CY_FLASH_IS_BUSY (0x00000040UL) -/** IPC structure is already locked by another process */ -#define CY_FLASH_IS_IPC_BUSY (0x00000080UL) -/** Input parameters passed to Flash API are not valid */ -#define CY_FLASH_IS_INVALID_INPUT_PARAMETERS (0x00000100UL) - -/** Result mask */ -#define CY_FLASH_RESULT_MASK (0xFFFFFFFUL) -/** Error shift */ -#define CY_FLASH_ERROR_SHIFT (28UL) -/** No error */ -#define CY_FLASH_ERROR_NO_ERROR (0xAUL) +#define CY_FLASH_ENTER_WAIT_LOOP 0xFFU +#define CY_FLASH_IPC_CLIENT_ID 2U +/** Semaphore number reserved for flash driver */ +#define CY_FLASH_WAIT_SEMA 0UL /** \endcond */ - /** -* \addtogroup group_flash_config_macro Flash configuration +* \addtogroup group_flash_config_macros Flash configuration * \{ * Specifies the parameter values passed to SROM API */ -/** SROM API opcode for flash write operation */ -#if (CY_CPU_CORTEX_M0P) && (!defined(CY8C622PSVP) && !defined(CY8C622PSVP_DUAL)) - #define CY_FLASH_OPCODE_WRITE_ROW (((0x05UL) << 24u) | ((0x01UL) << 8UL)) -#else - #define CY_FLASH_OPCODE_WRITE_ROW ((0x05UL) << 24u) -#endif +/** Set SROM API in blocking mode */ +#define CY_FLASH_BLOCKING_MODE ((0x01UL) << 8UL) +/** Set SROM API in non blocking mode */ +#define CY_FLASH_NON_BLOCKING_MODE (0UL) +/** SROM API opcode for flash write operation */ +#define CY_FLASH_OPCODE_WRITE_ROW ((0x05UL) << 24UL) +/** SROM API opcode for flash program operation */ +#define CY_FLASH_OPCODE_PROGRAM_ROW ((0x06UL) << 24UL) +/** SROM API opcode for row erase operation */ +#define CY_FLASH_OPCODE_ERASE_ROW ((0x1CUL) << 24UL) /** SROM API opcode for flash checksum operation */ -#define CY_FLASH_OPCODE_CHECKSUM ((0x0BUL) << 24u) +#define CY_FLASH_OPCODE_CHECKSUM ((0x0BUL) << 24UL) /** SROM API opcode for flash hash operation */ -#define CY_FLASH_OPCODE_HASH ((0x0DUL) << 24u) +#define CY_FLASH_OPCODE_HASH ((0x0DUL) << 24UL) /** SROM API flash row shift for flash checksum operation */ -#define CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT (8u) +#define CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT (8UL) /** SROM API flash data size parameter for flash write operation */ #define CY_FLASH_CONFIG_DATASIZE (0x06UL) +/** Data to be programmed to flash is located in SRAM memory region */ +#define CY_FLASH_DATA_LOC_SRAM (0x100UL) /** SROM API flash verification option for flash write operation */ #define CY_FLASH_CONFIG_VERIFICATION_EN ((0x01UL) << 16u) -/** \} group_flash_config_macro */ +/** \} group_flash_config_macros */ /** -* \addtogroup group_flash_general_macro Flash general parameters +* \addtogroup group_flash_general_macros Flash general parameters * \{ * Provides general information about flash and IPC */ @@ -206,23 +200,40 @@ typedef enum #define CY_FLASH_NUMBER_ROWS (CY_FLASH_SIZE / CY_FLASH_SIZEOF_ROW) /** Long words flash row size */ #define CY_FLASH_SIZEOF_ROW_LONG_UNITS (CY_FLASH_SIZEOF_ROW / sizeof(uint32_t)) -/** Calculates the flash address for a given row of flash */ -#define CY_CALCULATE_FLASH_ADDRESS(rowNum) (CY_FLASH_BASE + ((rowNum) * CY_FLASH_SIZEOF_ROW)) /** IPC channel to be used */ #define CY_FLASH_IPC_STRUCT ((IPC_STRUCT_Type*) &IPC->STRUCT[CY_IPC_CHAN_SYSCALL]) /** IPC notify bit for IPC_STRUCT0 (dedicated to flash operation) */ -#define CY_FLASH_IPC_NOTIFY_STRUCT0 (0x1UL) -/** \cond INTERNAL */ -#define CY_FLASH_CM4_FLASH_PROXY_ADDR (0x16001101UL) -/** \endcond */ +#define CY_FLASH_IPC_NOTIFY_STRUCT0 (0x1UL << CY_IPC_INTR_SYSCALL1) +/** IPC notify interrupt structure number */ +#define CY_FLASH_IPC_INTR_CM0_NOTIFY (0x1UL << CY_IPC_INTR_FLASH_NOTIFY) -/** \} group_flash_general_macro */ +/** \} group_flash_general_macros */ -/** \} group_flash_macro */ +/** \} group_flash_macros */ -#if defined(__cplusplus) -extern "C" { -#endif +/** +* \addtogroup group_flash_enumerated_types +* \{ +*/ + +/** This enum has the return values of the Flash driver */ +typedef enum +{ + CY_FLASH_DRV_SUCCESS = 0x00UL, /**< Success */ + CY_FLASH_DRV_INV_PROT = ( CY_FLASH_ID_ERROR + 0x0UL), /**< Invalid device protection state */ + CY_FLASH_DRV_INVALID_FM_PL = ( CY_FLASH_ID_ERROR + 0x1UL), /**< Invalid flash page latch address */ + CY_FLASH_DRV_INVALID_FLASH_ADDR = ( CY_FLASH_ID_ERROR + 0x2UL), /**< Invalid flash address */ + CY_FLASH_DRV_ROW_PROTECTED = ( CY_FLASH_ID_ERROR + 0x3UL), /**< Row is write protected */ + CY_FLASH_DRV_IPC_BUSY = ( CY_FLASH_ID_ERROR + 0x5UL), /**< IPC structure is already locked by another process */ + CY_FLASH_DRV_INVALID_INPUT_PARAMETERS = ( CY_FLASH_ID_ERROR + 0x6UL), /**< Input parameters passed to Flash API are not valid */ + CY_FLASH_DRV_PL_ROW_COMP_FA = ( CY_FLASH_ID_ERROR + 0x22UL), /**< Comparison between Page Latches and FM row failed */ + CY_FLASH_DRV_ERR_UNC = ( CY_FLASH_ID_ERROR + 0xFFUL), /**< Unknown error */ + CY_FLASH_DRV_PROGRESS_NO_ERROR = ( CY_FLASH_ID_INFO + 0x0UL), /**< Command in progress; no error */ + CY_FLASH_DRV_OPERATION_STARTED = ( CY_FLASH_ID_INFO + 0x1UL), /**< Flash operation is successfully initiated */ + CY_FLASH_DRV_OPCODE_BUSY = ( CY_FLASH_ID_INFO + 0x2UL) /**< Flash is under operation */ +} cy_en_flashdrv_status_t; + +/** \} group_flash_enumerated_types */ /*************************************** * Data Structure definitions @@ -253,17 +264,25 @@ typedef struct * \addtogroup group_flash_functions * \{ */ -cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data, cy_stc_flash_context_t* contextPtr); -cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data, cy_stc_flash_context_t* contextPtr); -cy_en_flashdrv_status_t Cy_Flash_IsWriteComplete(const cy_stc_flash_context_t* contextPtr); -cy_en_flashdrv_status_t Cy_Flash_RowChecksum (uint32_t rowNum, cy_stc_flash_context_t* contextPtr, uint32_t* cheksumPtr); -cy_en_flashdrv_status_t Cy_Flash_CalculateHash (const uint32_t* data, uint32 numberOfBytes, cy_stc_flash_context_t* contextPtr, uint32_t* hashPtr); +cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr); +cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data); +cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data); +cy_en_flashdrv_status_t Cy_Flash_IsWriteComplete(void); +cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data); +cy_en_flashdrv_status_t Cy_Flash_IsProgramComplete(void); +cy_en_flashdrv_status_t Cy_Flash_StartErase(uint32_t rowAddr); +cy_en_flashdrv_status_t Cy_Flash_IsEraseComplete(void); +cy_en_flashdrv_status_t Cy_Flash_RowChecksum(uint32_t rowNum, uint32_t* checksumPtr); +cy_en_flashdrv_status_t Cy_Flash_CalculateHash(const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr); /** \cond INTERNAL */ -uint32_t Cy_Flash_BoundsCheck(uint32_t flashAddr); -uint32_t Cy_Flash_PrepeareContext(uint32_t rowAddr, const uint32_t* data, cy_stc_flash_context_t *contextPtr); -cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode); +typedef cy_en_flashdrv_status_t (*Cy_Flash_Proxy)(cy_stc_flash_context_t *context); -typedef cy_en_flashdrv_status_t (*Cy_Flash_Proxy)(cy_stc_flash_context_t *contextPtr); +typedef struct _IPC_MSG +{ + uint8_t clientID; + uint8_t pktType; + uint16_t intrRelMask; +} IPC_MSG; /** \endcond */ /** \} group_flash_functions */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/gpio/cy_gpio.c similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.c rename to targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/gpio/cy_gpio.c index 43c939f4da..95dcb3e33f 100644 --- a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.c +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/gpio/cy_gpio.c @@ -36,9 +36,9 @@ extern "C" { * Pointer to the pin config structure base address * * \return -* void +* Initialization status * -* \note +* \note * This function modifies port registers in read-modify-write operations. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -78,7 +78,7 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const { status = CY_GPIO_BAD_PARAM; } - + return(status); } @@ -96,7 +96,7 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const * Pointer to the pin config structure base address * * \return -* void +* Initialization status * *******************************************************************************/ cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config) @@ -124,7 +124,7 @@ cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt { status = CY_GPIO_BAD_PARAM; } - + return(status); } diff --git a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/gpio/cy_gpio.h similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.h rename to targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/gpio/cy_gpio.h index f25c54beeb..e806024627 100644 --- a/targets/TARGET_Cypress/TARGET_PSoC6_CY8C/device/driver_periph/gpio/cy_gpio.h +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/gpio/cy_gpio.h @@ -22,21 +22,21 @@ * * Initialization can be performed either at the port level or by configuring the * individual pins. For efficient use of code space, port -* configuration should be used in the field. Refer to the product device header files +* configuration should be used in the field. Refer to the product device header files * for the list of supported ports and pins. -* -* - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit +* +* - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit * (provide specific values) or \ref Cy_GPIO_Pin_Init (provide a filled * cy_stc_gpio_pin_config_t structure). -* - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled -* cy_stc_gpio_prt_config_t structure. The values in the structure are +* - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled +* cy_stc_gpio_prt_config_t structure. The values in the structure are * bitfields representing the desired value for each pin in the port. * - Pin configuration and management is based on the port address and pin number. * \ref Cy_GPIO_PortToAddr function can optionally be used to calculate the port * address from the port number at run-time. * -* Once the pin/port initialization is complete, each pin can be accessed by -* specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API +* Once the pin/port initialization is complete, each pin can be accessed by +* specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API * functions. * * \section group_gpio_configuration Configuration Considerations @@ -50,32 +50,21 @@ * registers. These functions are not thread safe and care must be taken when * called by the application. * +* The whole gpio port can be updated using the port mask by direct port +* register writing. The code example below shows the different ways of +* manipulating Port#1 using the Port output data register, +* the Port output data set register, and the Port output data clear register: +* +* \snippet gpio_sut_01.cydsn/main_cm4.c Cy_GPIO_Snippet +* +* * \section group_gpio_more_information More Information * * Refer to the technical reference manual (TRM) and the device datasheet. * * \section group_gpio_MISRA MISRA-C Compliance] -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
    MISRA ruleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
    14.1RStatic Function '' is not used within this translation unit.
    16.7RThe object addressed by the pointer parameter 'base' is not modified -* and so the pointer could be of type 'pointer to const'.
    +* +* The gpio driver does not have any specific deviations. * * \section group_gpio_changelog Changelog * @@ -87,7 +76,7 @@ * *
    * -* \defgroup group_gpio_macro Macro +* \defgroup group_gpio_macros Macros * \defgroup group_gpio_functions Functions * \{ * \defgroup group_gpio_functions_init Initialization Functions @@ -110,7 +99,7 @@ extern "C" { #endif -/** \addtogroup group_gpio_macro +/** \addtogroup group_gpio_macros * \{ */ @@ -123,7 +112,7 @@ extern "C" { /** GPIO driver ID */ #define CY_GPIO_ID CY_PDL_DRV_ID(0x16u) -/** \} group_gpio_macro */ +/** \} group_gpio_macros */ /*************************************** @@ -137,7 +126,7 @@ extern "C" { /** * GPIO Driver error codes */ -typedef enum +typedef enum { CY_GPIO_SUCCESS = 0x00u, /**< Returned successful */ CY_GPIO_BAD_PARAM = CY_GPIO_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */ @@ -246,7 +235,7 @@ typedef struct { ***************************************/ /** -* \addtogroup group_gpio_macro +* \addtogroup group_gpio_macros * \{ */ @@ -366,7 +355,7 @@ typedef struct { #define CY_SIO_VOH_4_16 (0x07UL) /**< \brief Voh = 4.16 x Reference */ /** \} */ -/** \} group_gpio_macro */ +/** \} group_gpio_macros */ /*************************************** * Function Prototypes @@ -449,25 +438,30 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t __STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value); __STATIC_INLINE uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base); -#if (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) +#if (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) || defined (CY_DOXYGEN) __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void); #endif /* (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) */ -#if (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) +#if (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) || defined (CY_DOXYGEN) __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void); #endif /* (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) */ -#if (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) +#if (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) || defined (CY_DOXYGEN) __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void); #endif /* (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) */ -#if (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) +#if (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) || defined (CY_DOXYGEN) __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void); #endif /* (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) */ /** \} group_gpio_functions_interrupt */ +/** +* \addtogroup group_gpio_functions_init +* \{ +*/ + /******************************************************************************* * Function Name: Cy_GPIO_Pin_FastInit ****************************************************************************//** @@ -494,7 +488,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void); * \return * void * -* \note +* \note * This function modifies port registers in read-modify-write operations. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -583,7 +577,7 @@ __STATIC_INLINE void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base) * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -683,6 +677,12 @@ __STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum) return (base); } +/** \} group_gpio_functions_init */ + +/** +* \addtogroup group_gpio_functions_gpio +* \{ +*/ /******************************************************************************* * Function Name: Cy_GPIO_Read @@ -863,7 +863,7 @@ __STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum) * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -919,7 +919,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinN * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -973,7 +973,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum) * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1027,7 +1027,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNu * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1064,6 +1064,12 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNu return (base->CFG_OUT >> (pinNum + CY_GPIO_CFG_OUT_DRIVE_OFFSET)) & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK; } +/** \} group_gpio_functions_gpio */ + +/** +* \addtogroup group_gpio_functions_sio +* \{ +*/ /******************************************************************************* * Function Name: Cy_GPIO_SetVregEn @@ -1085,7 +1091,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNu * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1145,7 +1151,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum) * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1205,7 +1211,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNu * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1265,7 +1271,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNu * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1328,7 +1334,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1367,6 +1373,12 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum) return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT)) & CY_GPIO_VOH_SEL_MASK; } +/** \} group_gpio_functions_sio */ + +/** +* \addtogroup group_gpio_functions_interrupt +* \{ +*/ /******************************************************************************* * Function Name: Cy_GPIO_GetInterruptStatus @@ -1438,7 +1450,7 @@ __STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1539,7 +1551,7 @@ __STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1592,7 +1604,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t * \return * void * -* \note +* \note * This function modifies a port register in a read-modify-write operation. It is * not thread safe as the resource is shared among multiple pins on a port. * @@ -1705,8 +1717,9 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void) #endif -/** \} group_gpio_functions */ +/** \} group_gpio_functions_interrupt */ +/** \} group_gpio_functions */ #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/i2s/cy_i2s.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/i2s/cy_i2s.c new file mode 100644 index 0000000000..0c58856dc7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/i2s/cy_i2s.c @@ -0,0 +1,275 @@ +/***************************************************************************//** +* \file cy_i2s.c +* \version 2.0 +* +* The source code file for the I2S driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_i2s.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_I2S_Init +****************************************************************************//** +* +* Initializes the I2S module in accordance with a configuration structure. +* +* \pre If the I2S module is initialized previously, the \ref Cy_I2S_DeInit() +* must be called before calling this function. +* +* \param base The pointer to the I2S instance address. +* \param config The pointer to a configuration structure. +* \return error / status code. See \ref cy_en_i2s_status_t. +* +*******************************************************************************/ +cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config) +{ + cy_en_i2s_status_t ret = CY_I2S_BAD_PARAM; + cy_en_i2s_ws_pw_t wsPulseWidth; + uint32_t channels, clockDiv; + cy_en_i2s_len_t channelLength; + + if((NULL != base) && (NULL != config)) + { + ret = CY_I2S_SUCCESS; + + /* Clock setting */ + clockDiv = (uint32_t)config->clkDiv - 1U; + + CY_ASSERT_L2(CY_I2S_IS_CLK_DIV_VALID(clockDiv)); + + base->CLOCK_CTL = _VAL2FLD(I2S_CLOCK_CTL_CLOCK_DIV, clockDiv) | + _BOOL2FLD(I2S_CLOCK_CTL_CLOCK_SEL, config->extClk); + + /* Tx setting */ + if(config->txEnabled) + { + CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->txAlignment)); + CY_ASSERT_L3(CY_I2S_IS_OVHDATA_VALID(config->txOverheadValue)); + + if((CY_I2S_TDM_MODE_A == config->txAlignment) || (CY_I2S_TDM_MODE_B == config->txAlignment)) + { + channels = (uint32_t)config->txChannels - 1UL; + wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH; + channelLength = CY_I2S_LEN32; + + CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels)); + CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->txWordLength)); + } + else + { + channels = 1UL; + wsPulseWidth = config->txWsPulseWidth; + channelLength = config->txChannelLength; + + CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth)); + CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->txWordLength)); + } + + CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->txFifoTriggerLevel, channels)); + + base->TX_WATCHDOG = config->txWatchdogValue; + + base->TX_CTL = _VAL2FLD(I2S_TX_CTL_I2S_MODE, config->txAlignment) | + _BOOL2FLD(I2S_TX_CTL_B_CLOCK_INV, config->txSdoLatchingTime) | + _VAL2FLD(I2S_TX_CTL_CH_NR, channels) | + _BOOL2FLD(I2S_TX_CTL_MS, config->txMasterMode) | + _VAL2FLD(I2S_TX_CTL_WS_PULSE, wsPulseWidth) | + _BOOL2FLD(I2S_TX_CTL_WD_EN, config->txWatchdogEnable) | + _BOOL2FLD(I2S_TX_CTL_SCKO_POL, config->txSckoInversion) | + _BOOL2FLD(I2S_TX_CTL_SCKI_POL, config->txSckiInversion) | + _VAL2FLD(I2S_TX_CTL_CH_LEN, channelLength) | + _VAL2FLD(I2S_TX_CTL_WORD_LEN, config->txWordLength) | + _VAL2FLD(I2S_TX_CTL_OVHDATA, config->txOverheadValue); + } + + /* Rx setting */ + if(config->rxEnabled) + { + CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->rxAlignment)); + + if((CY_I2S_TDM_MODE_A == config->rxAlignment) || (CY_I2S_TDM_MODE_B == config->rxAlignment)) + { + channels = (uint32_t)config->rxChannels - 1UL; + wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH; + channelLength = CY_I2S_LEN32; + + CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels)); + CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->rxWordLength)); + } + else + { + channels = 1UL; + wsPulseWidth = config->rxWsPulseWidth; + channelLength = config->rxChannelLength; + + CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth)); + CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->rxWordLength)); + } + + CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->rxFifoTriggerLevel, channels)); + + base->RX_WATCHDOG = config->rxWatchdogValue; + + base->RX_CTL = _VAL2FLD(I2S_RX_CTL_I2S_MODE, config->rxAlignment) | + _BOOL2FLD(I2S_RX_CTL_B_CLOCK_INV, config->rxSdiLatchingTime) | + _VAL2FLD(I2S_RX_CTL_CH_NR, channels) | + _BOOL2FLD(I2S_RX_CTL_MS, config->rxMasterMode) | + _VAL2FLD(I2S_RX_CTL_WS_PULSE, wsPulseWidth) | + _BOOL2FLD(I2S_RX_CTL_WD_EN, config->rxWatchdogEnable) | + _BOOL2FLD(I2S_RX_CTL_SCKO_POL, config->rxSckoInversion) | + _BOOL2FLD(I2S_RX_CTL_SCKI_POL, config->rxSckiInversion) | + _VAL2FLD(I2S_RX_CTL_CH_LEN, channelLength) | + _VAL2FLD(I2S_RX_CTL_WORD_LEN, config->rxWordLength) | + _BOOL2FLD(I2S_RX_CTL_BIT_EXTENSION, config->rxSignExtension); + } + + /* I2S enable setting */ + if(config->txEnabled) + { + base->CTL |= I2S_CTL_TX_ENABLED_Msk; + } + + if(config->rxEnabled) + { + base->CTL |= I2S_CTL_RX_ENABLED_Msk; + } + + /* FIFO setting */ + if(config->txEnabled) + { + base->TX_FIFO_CTL = _VAL2FLD(I2S_TX_FIFO_CTL_TRIGGER_LEVEL, config->txFifoTriggerLevel); + + base->TR_CTL |= _BOOL2FLD(I2S_TR_CTL_TX_REQ_EN, config->txDmaTrigger); + } + + if(config->rxEnabled) + { + base->RX_FIFO_CTL = _VAL2FLD(I2S_RX_FIFO_CTL_TRIGGER_LEVEL, config->rxFifoTriggerLevel); + + base->TR_CTL |= _BOOL2FLD(I2S_TR_CTL_RX_REQ_EN, config->rxDmaTrigger); + } + } + + return (ret); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_DeInit +****************************************************************************//** +* +* Uninitializes the I2S module (reverts default register values). +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +void Cy_I2S_DeInit(I2S_Type * base) +{ + base->INTR_MASK = 0UL; /* Disable interrupts prior to stopping the operation */ + base->CMD = 0UL; + base->TR_CTL = 0UL; + base->TX_FIFO_CTL = 0UL; + base->RX_FIFO_CTL = 0UL; + base->CTL = 0UL; + base->TX_CTL = CY_I2S_TX_CTL_DEFAULT; + base->RX_CTL = CY_I2S_RX_CTL_DEFAULT; + base->TX_WATCHDOG = 0UL; + base->RX_WATCHDOG = 0UL; + base->CLOCK_CTL = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_DeepSleepCallback +****************************************************************************//** +* +* This is a callback function that can be used at the application layer to +* manage an I2S operation before entering into/after exiting from the Deep Sleep +* mode. +* +* \param +* callbackParams - A pointer to the callback parameters structure, +* see \ref cy_stc_syspm_callback_params_t. +* +* \return the SysPm callback status \ref cy_en_syspm_status_t. +* +* \note Use the \ref cy_stc_i2s_context_t data type for definition of the +* *context element of the \ref cy_stc_syspm_callback_params_t strusture. +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams) +{ + cy_en_syspm_status_t ret = CY_SYSPM_SUCCESS; + CY_ASSERT_L1(NULL != callbackParams->context); + I2S_Type * locBase = (I2S_Type*) callbackParams->base; + uint32_t * locInterruptMask = (uint32_t*) &(((cy_stc_i2s_context_t*)(callbackParams->context))->interruptMask); + uint32_t * locState = (uint32_t*) &(((cy_stc_i2s_context_t*)(callbackParams->context))->enableState); + + switch(callbackParams->mode) + { + case CY_SYSPM_CHECK_READY: + case CY_SYSPM_CHECK_FAIL: + break; + + case CY_SYSPM_BEFORE_TRANSITION: + *locInterruptMask = Cy_I2S_GetInterruptMask(locBase); /* Store I2S interrupts */ + Cy_I2S_SetInterruptMask(locBase, 0UL); /* Disable I2S interrupts */ + *locState = Cy_I2S_GetCurrentState(locBase); /* Store I2S state */ + if(0UL != (*locState & I2S_CMD_TX_START_Msk)) + { + Cy_I2S_DisableTx(locBase); /* Stop TX operation */ + } + if(0UL != (*locState & I2S_CMD_RX_START_Msk)) + { + Cy_I2S_DisableRx(locBase); /* Stop RX operation */ + } + /* Unload FIFOs to do not lost any data (if needed) */ + break; + + case CY_SYSPM_AFTER_TRANSITION: + if(0UL != (*locState & I2S_CMD_RX_START_Msk)) + { + Cy_I2S_ClearRxFifo (locBase); /* Clear RX FIFO */ + Cy_I2S_EnableRx (locBase); /* Start RX operation */ + } + if(0UL != (*locState & I2S_CMD_TX_START_Msk)) + { + Cy_I2S_ClearTxFifo (locBase); /* Clear TX FIFO */ + Cy_I2S_WriteTxData (locBase, 0UL); /* Fill first TX frame */ + Cy_I2S_WriteTxData (locBase, 0UL); + if(0UL != (*locState & I2S_CMD_TX_PAUSE_Msk)) + { + Cy_I2S_PauseTx(locBase); /* Restore TX paused state */ + } + Cy_I2S_EnableTx(locBase); /* Start TX operation */ + } + Cy_I2S_SetInterruptMask (locBase, *locInterruptMask); /* Restore I2S interrupts */ + break; + + default: + ret = CY_SYSPM_FAIL; + break; + } + + return(ret); +} + + +#ifdef __cplusplus +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/i2s/cy_i2s.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/i2s/cy_i2s.h new file mode 100644 index 0000000000..a124832a33 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/i2s/cy_i2s.h @@ -0,0 +1,974 @@ +/***************************************************************************//** +* \file cy_i2s.h +* \version 2.0 +* +* The header file of the I2S driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_i2s Inter-IC Sound (I2S) +* \{ +* The I2S driver provides a function API to manage Inter-IC Sound. I2S is used +* to send digital audio streaming data to external I2S devices, such as audio +* codecs or simple DACs. It can also receive digital audio streaming data. +* +* Features: +* * An industry-standard NXP I2S interface +* * Supports master/slave TX/RX operation +* * Programmable Channel/Word Lengths +* * Supports External Clock operation +* +* The I2S bus is an industry standard. The hardware interface was +* developed by Philips Semiconductors (now NXP Semiconductors). +* +* \section group_i2s_configuration_considerations Configuration Considerations +* +* To set up an I2S, provide the configuration parameters in the +* \ref cy_stc_i2s_config_t structure. +* +* For example, for TX configuration, set txEnabled to true, configure +* txDmaTrigger (depending on whether DMA is going to be used or not), set +* extClk (if an external clock is used), provide clkDiv, txMasterMode, +* txAlignment, txChannels (only 2 is supported in I2S and Left Justified modes) +* txSdoLatchingTime (for slave mode only), txChannelLength, txWordLength, +* txWsPulseWidth (for TMD modes only), txWatchdogEnable and txWatchdogValue +* (both for slave mode only, and when the watchdog interrupt will be used), +* either txSckoInversion or txSckiInversion (based on txMasterMode setting), +* txFifoTriggerLevel (when the Trig interrupt will be used) and txOverheadValue +* (only when word length is less than channel length). +* The similar setup is for RX configuration. +* +* To initialize the I2S block, call the \ref Cy_I2S_Init function, providing the +* filled \ref cy_stc_i2s_config_t structure. +* Before starting the transmission, clear the FIFO \ref Cy_I2S_ClearTxFifo, then +* fill the first TX data frame by calling \ref Cy_I2S_WriteTxData once for each +* channel (e.g. twice for I2S mode with only two channels) with zero data. Then +* call the \ref Cy_I2S_EnableTx itself. +* For the reception the sequence is the same except of filling the first data +* frame, just RX FIFO clearing is enough. +* +* For example: +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c Cy_I2S_Snippet +* +* If you use DMA, the DMA channel should be previously configured. I2S interrupts +* (if applicable) can be enabled by calling \ref Cy_I2S_SetInterruptMask. +* +* For example, if the trigger interrupt is used, during operation the ISR +* should call the \ref Cy_I2S_WriteTxData as many times as required for your +* FIFO payload, but not more than FIFO size. Then call \ref Cy_I2S_ClearInterrupt +* with appropriate parameters. +* +* The I2S/Left Justified data formats always contains two data channels. +* They are ordered one-by-one in the FIFOs, left always goes first. +* So in case of mono audio stream transmission, each sample can be put twice +* into the TX FIFO (in this case both channels will sound the same), +* or combined with zeroes: sample1-zero-sample2-zero (in this case only the +* left channel will finally sound, for right-only case zero should go first). +* The TDM frame word order in FIFOs is similar, one-by-one. +* +* If DMA is used and a DMA channel is properly configured - no CPU activity +* (or any application code) is needed for I2S operation. +* +* The I2S frame looks like the next: +* \image html i2s_frame.png +* This is an example for channel length = 32. The similar is for all the rest +* channel lengths, with only limitation: the word length could be less or equal +* to the channel length. See the device Technical Reference Manual (TRM) +* for more details. +* +* \section group_i2s_more_information More Information +* See the the I2S chapter of the device technical reference manual (TRM). +* Also, see I2S_PDL Component datasheet. +* +* \section group_i2s_MISRA MISRA-C Compliance +* The I2S driver has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
    11.4AA cast should not be performed between a pointer to object type and +* a different pointer to object type.The function \ref Cy_I2S_DeepSleepCallback is a callback of +* \ref cy_en_syspm_status_t type. The cast operation safety in this +* function becomes the user responsibility because pointer are +* initialized when callback is registered in SysPm driver.
    +* +* \section group_i2s_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +*
    VersionChangesReason for Change
    1.0Initial version
    2.0The slave operation is added, Left Justified and TDM modes are added
    +* +* \defgroup group_i2s_macros Macros +* \defgroup group_i2s_functions Functions +* \defgroup group_i2s_data_structures Data Structures +* \defgroup group_i2s_enums Enumerated types +*/ + + +#if !defined CY_I2S_H +#define CY_I2S_H + +#include +#include +#include "syslib/cy_syslib.h" +#include "syspm/cy_syspm.h" + +#ifndef CY_IP_MXAUDIOSS + #error "The I2S driver is not supported on this device" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** \addtogroup group_i2s_macros +* \{ +*/ + +/** Driver major version */ +#define CY_I2S_DRV_VERSION_MAJOR 2 + +/** Driver minor version */ +#define CY_I2S_DRV_VERSION_MINOR 0 + +/** I2S driver identifier */ +#define CY_I2S_ID (CY_PDL_DRV_ID(0x20U)) + +/** +* \defgroup group_i2s_macros_intrerrupt_masks Interrupt Masks +* \{ +*/ + +/** Bit 0: Less entries in the TX FIFO than specified by Trigger Level. */ +#define CY_I2S_INTR_TX_TRIGGER (I2S_INTR_TX_TRIGGER_Msk) +/** Bit 1: TX FIFO is not full. */ +#define CY_I2S_INTR_TX_NOT_FULL (I2S_INTR_TX_NOT_FULL_Msk) +/** Bit 4: TX FIFO is empty, i.e. it has 0 entries. */ +#define CY_I2S_INTR_TX_EMPTY (I2S_INTR_TX_EMPTY_Msk) +/** Bit 5: Attempt to write to a full TX FIFO. */ +#define CY_I2S_INTR_TX_OVERFLOW (I2S_INTR_TX_OVERFLOW_Msk) +/** Bit 6: Attempt to read from an empty TX FIFO. +* This happens when the IP is ready to transfer data and TX_EMPTY is '1'. */ +#define CY_I2S_INTR_TX_UNDERFLOW (I2S_INTR_TX_UNDERFLOW_Msk) +/** Bit 8: Tx watchdog event occurs. */ +#define CY_I2S_INTR_TX_WD (I2S_INTR_TX_WD_Msk) +/** Bit 16: More entries in the RX FIFO than specified by Trigger Level. */ +#define CY_I2S_INTR_RX_TRIGGER (I2S_INTR_RX_TRIGGER_Msk) +/** Bit 18: RX FIFO is not empty. */ +#define CY_I2S_INTR_RX_NOT_EMPTY (I2S_INTR_RX_NOT_EMPTY_Msk) +/** Bit 19: RX FIFO is full. */ +#define CY_I2S_INTR_RX_FULL (I2S_INTR_RX_FULL_Msk) +/** Bit 21: Attempt to write to a full RX FIFO. */ +#define CY_I2S_INTR_RX_OVERFLOW (I2S_INTR_RX_OVERFLOW_Msk) +/** Bit 22: Attempt to read from an empty RX FIFO. */ +#define CY_I2S_INTR_RX_UNDERFLOW (I2S_INTR_RX_UNDERFLOW_Msk) +/** Bit 24: Rx watchdog event occurs. */ +#define CY_I2S_INTR_RX_WD (I2S_INTR_RX_WD_Msk) + +/** \} group_i2s_macros_intrerrupt_masks */ + + +/** +* \defgroup group_i2s_macros_current_state Current State +* \{ +*/ + +/** Transmission is active */ +#define CY_I2S_TX_START (I2S_CMD_TX_START_Msk) +/** Transmission is paused */ +#define CY_I2S_TX_PAUSE (I2S_CMD_TX_PAUSE_Msk) +/** Reception is active */ +#define CY_I2S_RX_START (I2S_CMD_RX_START_Msk) + +/** \} group_i2s_macros_current_state */ + +/** \} group_i2s_macros */ + +/** +* \addtogroup group_i2s_enums +* \{ +*/ + +/** +* I2S status definitions. +*/ + +typedef enum +{ + CY_I2S_SUCCESS = 0x00UL, /**< Successful. */ + CY_I2S_BAD_PARAM = CY_I2S_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< One or more invalid parameters. */ +} cy_en_i2s_status_t; + + +/** +* I2S data alignment. +*/ +typedef enum +{ + CY_I2S_LEFT_JUSTIFIED = 0U, /**< Left justified. */ + CY_I2S_I2S_MODE = 1U, /**< I2S mode. */ + CY_I2S_TDM_MODE_A = 2U, /**< TDM mode A. */ + CY_I2S_TDM_MODE_B = 3U /**< TDM mode B. */ +} cy_en_i2s_alignment_t; + +/** +* I2S channel/word length. +*/ +typedef enum +{ + CY_I2S_LEN8 = 0U, /**< Channel/word length: 8 bit. */ + CY_I2S_LEN16 = 1U, /**< Channel/Word length: 16 bit. */ + CY_I2S_LEN18 = 2U, /**< Channel/Word length: 18 bit. */ + CY_I2S_LEN20 = 3U, /**< Channel/Word length: 20 bit. */ + CY_I2S_LEN24 = 4U, /**< Channel/Word length: 24 bit. */ + CY_I2S_LEN32 = 5U /**< Channel/Word length: 32 bit. */ +} cy_en_i2s_len_t; + +/** +* I2S TX overhead value. +*/ +typedef enum +{ + CY_I2S_OVHDATA_ZERO = 0U, /**< Fill overhead bits by zeroes. */ + CY_I2S_OVHDATA_ONE = 1U, /**< Fill overhead bits by ones. */ +} cy_en_i2s_overhead_t; + +/** +* I2S WS pulse width. +*/ +typedef enum +{ + CY_I2S_WS_ONE_SCK_CYCLE = 0U, /**< WS pulse width is one SCK cycle. */ + CY_I2S_WS_ONE_CHANNEL_LENGTH = 1U, /**< WS pulse width is one channel length. */ +} cy_en_i2s_ws_pw_t; + +/** \} group_i2s_enums */ + +/** +* \addtogroup group_i2s_data_structures +* \{ +*/ + +/** +* I2S initialization configuration. +*/ +typedef struct +{ + bool txEnabled; /**< Enables the I2S TX component: 'false': disabled. 'true': enabled. */ + bool rxEnabled; /**< Enables the I2S RX component: 'false': disabled. 'true': enabled. */ + bool txDmaTrigger; /**< 'false': TX DMA trigger disable, 'true': TX DMA trigger enable. */ + bool rxDmaTrigger; /**< 'false': RX DMA trigger disable, 'true': RX DMA trigger enable. */ + uint8_t clkDiv; /**< CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, ..., 64: 1/64. */ + bool extClk; /**< 'false': internal clock, 'true': external clock. */ + bool txMasterMode; /**< 'false': TX in slave mode, 'true': TX in master mode. */ + cy_en_i2s_alignment_t txAlignment; /**< TX data alignment, see: #cy_en_i2s_alignment_t. */ + cy_en_i2s_ws_pw_t txWsPulseWidth; /**< TX Word Select pulse width. + The value of this parameter is ignored in TDM modes - the WS pulse + width is always "one channel length" is these modes. */ + bool txWatchdogEnable; /**< 'false': TX watchdog disabled, 'true': TX watchdog enabled. */ + uint32_t txWatchdogValue; /**< TX watchdog counter value (32 bit). */ + bool txSdoLatchingTime; /**< 'false': SDO bit starts at falling edge (accordingly to the I2S + Standard, if txSckoInversion is false), + 'true': SDO bit starts at rising edge which goes before the above + mentioned falling edge, i.e. the SDO signal is advanced by 0.5 SCK + period (if txSckoInversion is false). + If txSckoInversion is true - the rising/falling edges just swaps + in above explanations. + Effective only in slave mode, must be false in master mode.*/ + bool txSckoInversion; /**< TX SCKO polarity: + 'false': When transmitter is in master mode, serial data is + transmitted off the falling bit clock edge (accordingly to + the I2S Standard); + 'true': When transmitter is in master mode, serial data is + transmitted off the rising bit clock edge. + Effective only in master mode. */ + bool txSckiInversion; /**< TX SCKI polarity: + 'false': When transmitter is in slave mode, serial data is + transmitted off the falling bit clock edge (accordingly to + the I2S Standard); + 'true': When transmitter is in slave mode, serial data is + transmitted off the rising bit clock edge. + Effective only in slave mode. */ + uint8_t txChannels; /**< Number of TX channels, valid range is 1...8 for TDM modes. + In the I2S and Left Justified modes the value of this parameter is + ignored - the real number of channels is always 2 in these modes. */ + cy_en_i2s_len_t txChannelLength; /**< TX channel length, see #cy_en_i2s_len_t, + the value of this parameter is ignored in TDM modes, the real + channel length is 32 bit in these modes. */ + cy_en_i2s_len_t txWordLength; /**< TX word length, see #cy_en_i2s_len_t, + must be less or equal to txChannelLength. */ + cy_en_i2s_overhead_t txOverheadValue; /**< TX overhead bits value + when the word length is less than the channel length. */ + uint8_t txFifoTriggerLevel; /**< TX FIFO interrupt trigger level (0, 1, ..., 255). */ + bool rxMasterMode; /**< 'false': RX in slave mode, 'true': RX in master mode. */ + cy_en_i2s_alignment_t rxAlignment; /**< RX data alignment, see: #cy_en_i2s_alignment_t. */ + cy_en_i2s_ws_pw_t rxWsPulseWidth; /**< RX Word Select pulse width. + The value of this parameter is ignored in TDM modes - the WS pulse + width is always "one channel length" is these modes. */ + bool rxWatchdogEnable; /**< 'false': RX watchdog disabled, 'true': RX watchdog enabled. */ + uint32_t rxWatchdogValue; /**< RX watchdog counter value (32 bit). */ + bool rxSdiLatchingTime; /**< 'false': SDI bit starts at falling edge (accordingly to the I2S + Standard if rxSckoInversion is false), + 'true': SDI bit starts at rising edge which goes after the above + mentioned falling edge, i.e. the SDI signal is delayed by 0.5 SCK + period (if rxSckoInversion is false). + If rxSckoInversion is true - the rising/falling edges just swaps + in above explanations. + Effective only in master mode, must be false in slave mode. */ + bool rxSckoInversion; /**< RX SCKO polarity: + 'false': When receiver is in master mode, serial data is + captured by the rising bit clock edge (accordingly to the + I2S Standard); + 'true': When receiver is in master mode, serial data is + captured by the falling bit clock edge. + Effective only in master mode. */ + bool rxSckiInversion; /**< RX SCKI polarity: + 'false': When receiver is in slave mode, serial data is + captured by the rising bit clock edge (accordingly to the + I2S Standard); + 'true': When receiver is in slave mode, serial data is + captured by the falling bit clock edge. + Effective only in slave mode. */ + uint8_t rxChannels; /**< Number of RX channels, valid range is 1...8 for TDM modes. + In the I2S and Left Justified modes the value of this parameter is + ignored - the real number of channels is always 2 in these modes. */ + cy_en_i2s_len_t rxChannelLength; /**< RX channel length, see #cy_en_i2s_len_t, + the value of this parameter is ignored in TDM modes, the real + channel length is 32 bit in these modes. */ + cy_en_i2s_len_t rxWordLength; /**< RX word length, see #cy_en_i2s_len_t, + must be less or equal to rxChannelLength. */ + bool rxSignExtension; /**< RX value sign extension (when the word length is less than 32 bits), + 'false': all MSB are filled by zeroes, + 'true': all MSB are filled by the original sign bit value. */ + uint8_t rxFifoTriggerLevel; /**< RX FIFO interrupt trigger level + (0, 1, ..., (255 - (number of channels))). */ +} cy_stc_i2s_config_t; + + +/** + * I2S backup structure type to be used for SysPm callback + * \ref Cy_I2S_DeepSleepCallback context definition. + * + * \cond Also can be used for another purposes to store the current TX/RX + * operation state and interrupt settings - the factors that are usually + * being changed on the fly. \endcond + */ +typedef struct +{ + uint32_t enableState; /**< Stores I2S state */ + uint32_t interruptMask; /**< Stores I2S interrupt mask */ +} cy_stc_i2s_context_t; + +/** \} group_i2s_data_structures */ + +/** \cond INTERNAL */ +/****************************************************************************** + * Local definitions +*******************************************************************************/ + +#define CY_I2S_INTR_MASK (CY_I2S_INTR_TX_TRIGGER | \ + CY_I2S_INTR_TX_NOT_FULL | \ + CY_I2S_INTR_TX_EMPTY | \ + CY_I2S_INTR_TX_OVERFLOW | \ + CY_I2S_INTR_TX_UNDERFLOW | \ + CY_I2S_INTR_TX_WD | \ + CY_I2S_INTR_RX_TRIGGER | \ + CY_I2S_INTR_RX_NOT_EMPTY | \ + CY_I2S_INTR_RX_FULL | \ + CY_I2S_INTR_RX_OVERFLOW | \ + CY_I2S_INTR_RX_UNDERFLOW | \ + CY_I2S_INTR_RX_WD) + +/* Non-zero default values */ +#define CY_I2S_TX_CTL_CH_NR_DEFAULT (0x1U) +#define CY_I2S_TX_CTL_I2S_MODE_DEFAULT (0x2U) +#define CY_I2S_TX_CTL_WS_PULSE_DEFAULT (0x1U) +#define CY_I2S_TX_CTL_CH_LEN_DEFAULT (0x4U) +#define CY_I2S_TX_CTL_WORD_LEN_DEFAULT (0x4U) + +#define CY_I2S_TX_CTL_DEFAULT (_VAL2FLD(I2S_TX_CTL_CH_NR, CY_I2S_TX_CTL_CH_NR_DEFAULT) | \ + _VAL2FLD(I2S_TX_CTL_I2S_MODE, CY_I2S_TX_CTL_I2S_MODE_DEFAULT) | \ + _VAL2FLD(I2S_TX_CTL_WS_PULSE, CY_I2S_TX_CTL_WS_PULSE_DEFAULT) | \ + _VAL2FLD(I2S_TX_CTL_CH_LEN, CY_I2S_TX_CTL_CH_LEN_DEFAULT) | \ + _VAL2FLD(I2S_TX_CTL_WORD_LEN, CY_I2S_TX_CTL_WORD_LEN_DEFAULT)) + +#define CY_I2S_RX_CTL_CH_NR_DEFAULT (0x1U) +#define CY_I2S_RX_CTL_I2S_MODE_DEFAULT (0x2U) +#define CY_I2S_RX_CTL_WS_PULSE_DEFAULT (0x1U) +#define CY_I2S_RX_CTL_CH_LEN_DEFAULT (0x4U) +#define CY_I2S_RX_CTL_WORD_LEN_DEFAULT (0x4U) + +#define CY_I2S_RX_CTL_DEFAULT (_VAL2FLD(I2S_RX_CTL_CH_NR, CY_I2S_RX_CTL_CH_NR_DEFAULT) | \ + _VAL2FLD(I2S_RX_CTL_I2S_MODE, CY_I2S_RX_CTL_I2S_MODE_DEFAULT) | \ + _VAL2FLD(I2S_RX_CTL_WS_PULSE, CY_I2S_RX_CTL_WS_PULSE_DEFAULT) | \ + _VAL2FLD(I2S_RX_CTL_CH_LEN, CY_I2S_RX_CTL_CH_LEN_DEFAULT) | \ + _VAL2FLD(I2S_RX_CTL_WORD_LEN, CY_I2S_RX_CTL_WORD_LEN_DEFAULT)) + +/* Macros for conditions used by CY_ASSERT calls */ +#define CY_I2S_IS_ALIGNMENT_VALID(alignment) ((CY_I2S_LEFT_JUSTIFIED == (alignment)) || \ + (CY_I2S_I2S_MODE == (alignment)) || \ + (CY_I2S_TDM_MODE_A == (alignment)) || \ + (CY_I2S_TDM_MODE_B == (alignment))) + +#define CY_I2S_IS_LEN_VALID(length) ((CY_I2S_LEN8 == (length)) || \ + (CY_I2S_LEN16 == (length)) || \ + (CY_I2S_LEN18 == (length)) || \ + (CY_I2S_LEN20 == (length)) || \ + (CY_I2S_LEN24 == (length)) || \ + (CY_I2S_LEN32 == (length))) + +#define CY_I2S_IS_OVHDATA_VALID(overhead) ((CY_I2S_OVHDATA_ZERO == (overhead)) || \ + (CY_I2S_OVHDATA_ONE == (overhead))) + +#define CY_I2S_IS_WSPULSE_VALID(wsPulse) ((CY_I2S_WS_ONE_SCK_CYCLE == (wsPulse)) || \ + (CY_I2S_WS_ONE_CHANNEL_LENGTH == (wsPulse))) + +#define CY_I2S_IS_CLK_DIV_VALID(clkDiv) ((clkDiv) <= 63U) +#define CY_I2S_IS_CHANNELS_VALID(channels) ((channels) <= 7UL) +#define CY_I2S_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_I2S_INTR_MASK))) + +#define CY_I2S_IS_CHAN_WORD_VALID(channel, word) ((CY_I2S_IS_LEN_VALID(channel)) && \ + (CY_I2S_IS_LEN_VALID(word)) && \ + ((channel) >= (word))) +#define CY_I2S_IS_TRIG_LEVEL_VALID(trigLevel, channels) ((trigLevel) <= (255U - (channels))) + +/** \endcond */ + + +/** +* \addtogroup group_i2s_functions +* \{ +*/ + + cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config); + void Cy_I2S_DeInit(I2S_Type * base); +cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams); + +__STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base); +__STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base); + +__STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base); +__STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base); +__STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data); +__STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base); +__STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base); +__STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base); + +__STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base); +__STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base); +__STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base); +__STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base); +__STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base); +__STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base); +__STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base); + +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base); +__STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt); +__STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt); +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base); +__STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt); +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base); + +/******************************************************************************* +* Function Name: Cy_I2S_EnableTx +****************************************************************************//** +* +* Starts an I2S transmission. Interrupts enabling (by the +* \ref Cy_I2S_SetInterruptMask) is required after this function call, in case +* if any I2S interrupts are used in the application. +* +* \pre Cy_I2S_Init() must be called before. +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base) +{ + base->CMD |= I2S_CMD_TX_START_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_PauseTx +****************************************************************************//** +* +* Pauses an I2S transmission. +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base) +{ + base->CMD |= I2S_CMD_TX_PAUSE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ResumeTx +****************************************************************************//** +* +* Resumes an I2S transmission. +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base) +{ + base->CMD &= (uint32_t) ~I2S_CMD_TX_PAUSE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_DisableTx +****************************************************************************//** +* +* Stops an I2S transmission. +* +* \pre TX interrupts disabling (by the \ref Cy_I2S_SetInterruptMask) is required +* prior to this function call, in case if any TX I2S interrupts are used. +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base) +{ + base->CMD &= (uint32_t) ~I2S_CMD_TX_START_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_EnableRx +****************************************************************************//** +* +* Starts an I2S reception. Interrupts enabling (by the +* \ref Cy_I2S_SetInterruptMask) is required after this function call, in case +* if any I2S interrupts are used in the application. +* +* \pre \ref Cy_I2S_Init() must be called before. +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base) +{ + base->CMD |= I2S_CMD_RX_START_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_DisableRx +****************************************************************************//** +* +* Stops an I2S reception. +* +* \pre RX interrupts disabling (by the \ref Cy_I2S_SetInterruptMask) is required +* prior to this function call, in case if any RX I2S interrupts are used. +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base) +{ + base->CMD &= (uint32_t) ~I2S_CMD_RX_START_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetCurrentState +****************************************************************************//** +* +* Returns the current I2S state (TX/RX running/paused/stopped). +* +* \param base The pointer to the I2S instance address. +* \return The current state \ref group_i2s_macros_current_state. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base) +{ + return (base->CMD & (I2S_CMD_TX_START_Msk | I2S_CMD_TX_PAUSE_Msk | I2S_CMD_RX_START_Msk)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ClearTxFifo +****************************************************************************//** +* +* Clears TX FIFO (resets the Read/Write FIFO pointers). +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base) +{ + base->TX_FIFO_CTL |= I2S_TX_FIFO_CTL_CLEAR_Msk; + base->TX_FIFO_CTL &= (uint32_t) ~I2S_TX_FIFO_CTL_CLEAR_Msk; + (void) base->TX_FIFO_CTL; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetNumInTxFifo +****************************************************************************//** +* +* Gets the number of used words in the TX FIFO. +* +* \param base The pointer to the I2S instance address. +* \return The current number of used words in rge TX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base) +{ + return (_FLD2VAL(I2S_TX_FIFO_STATUS_USED, base->TX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_WriteTxData +****************************************************************************//** +* +* Writes data to the TX FIFO. Increases the TX FIFO level. +* +* \param base The pointer to the I2S instance address. +* \param data Data to be written to the TX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data) +{ + base->TX_FIFO_WR = data; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetTxReadPointer +****************************************************************************//** +* +* Gets the TX FIFO Read pointer. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* \return The current TX Read pointer value. +* +*******************************************************************************/ +__STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base) +{ + return ((uint8_t) _FLD2VAL(I2S_TX_FIFO_STATUS_RD_PTR, base->TX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetTxWritePointer +****************************************************************************//** +* +* Gets the TX FIFO Write pointer. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* \return The current TX Write pointer value. +* +*******************************************************************************/ +__STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base) +{ + return ((uint8_t) _FLD2VAL(I2S_TX_FIFO_STATUS_WR_PTR, base->TX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_FreezeTxFifo +****************************************************************************//** +* +* Freezes the TX FIFO. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base) +{ + base->TX_FIFO_CTL |= I2S_TX_FIFO_CTL_FREEZE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_UnfreezeTxFifo +****************************************************************************//** +* +* Unfreezes the TX FIFO. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base) +{ + base->TX_FIFO_CTL &= (uint32_t) ~I2S_TX_FIFO_CTL_FREEZE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ClearRxFifo +****************************************************************************//** +* +* Clears the RX FIFO (resets the Read/Write FIFO pointers). +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base) +{ + base->RX_FIFO_CTL |= I2S_RX_FIFO_CTL_CLEAR_Msk; + base->RX_FIFO_CTL &= (uint32_t) ~I2S_RX_FIFO_CTL_CLEAR_Msk; + (void) base->RX_FIFO_CTL; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetNumInRxFifo +****************************************************************************//** +* +* Gets the number of used words in the RX FIFO. +* +* \param base The pointer to the I2S instance address. +* \return The current number of used words in rge RX FIFO. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base) +{ + return (_FLD2VAL(I2S_RX_FIFO_STATUS_USED, base->RX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ReadRxData +****************************************************************************//** +* +* Reads data from the RX FIFO. Decreases the TX FIFO level. +* +* \param base The pointer to the I2S instance address. +* \return The read data. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base) +{ + return (base->RX_FIFO_RD); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ReadRxDataSilent +****************************************************************************//** +* +* Reads data from the RX FIFO without updating the RX FIFO read pointer. +* This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* \return The read data. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base) +{ + return (base->RX_FIFO_RD_SILENT); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetRxReadPointer +****************************************************************************//** +* +* Gets the RX FIFO Read pointer. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* \return The current RX Read pointer value. +* +*******************************************************************************/ +__STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base) +{ + return ((uint8_t) _FLD2VAL(I2S_RX_FIFO_STATUS_RD_PTR, base->RX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetRxWritePointer +****************************************************************************//** +* +* Gets the RX FIFO Write pointer. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* \return The current RX Write pointer value. +* +*******************************************************************************/ +__STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base) +{ + return ((uint8_t) _FLD2VAL(I2S_RX_FIFO_STATUS_WR_PTR, base->RX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_FreezeRxFifo +****************************************************************************//** +* +* Freezes the RX FIFO. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base) +{ + base->RX_FIFO_CTL |= I2S_RX_FIFO_CTL_FREEZE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_UnfreezeRxFifo +****************************************************************************//** +* +* Unfreezes the RX FIFO. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base) +{ + base->RX_FIFO_CTL &= (uint32_t) ~I2S_RX_FIFO_CTL_FREEZE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetInterruptStatus +****************************************************************************//** +* +* Gets an interrupt status (returns a content of the INTR register). +* +* \param base The pointer to the I2S instance address. +* \return The interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base) +{ + return (base->INTR); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ClearInterrupt +****************************************************************************//** +* +* Clears one or more interrupt factors (sets the INTR register). +* +* \param base The pointer to the I2S instance address. +* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt)); + base->INTR = interrupt; + (void) base->INTR; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_SetInterrupt +****************************************************************************//** +* +* Sets one or more interrupt factors (sets the INTR_SET register). +* +* \param base The pointer to the I2S instance address. +* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt)); + base->INTR_SET = interrupt; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetInterruptMask +****************************************************************************//** +* +* Returns the interrupt mask (a content of the INTR_MASK register). +* +* \param base The pointer to the I2S instance address. +* \return The interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base) +{ + return (base->INTR_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_SetInterruptMask +****************************************************************************//** +* +* Sets one or more interrupt factor masks (the INTR_MASK register). +* +* \param base The pointer to the I2S instance address. +* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt)); + base->INTR_MASK = interrupt; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetInterruptStatusMasked +****************************************************************************//** +* +* Returns the interrupt status masked (a content of the INTR_MASKED register). +* +* \param base The pointer to the I2S instance address. +* \return The interrupt bit mask(s) \ref group_i2s_macros_intrerrupt_masks. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base) +{ + return (base->INTR_MASKED); +} + +/** \} group_i2s_functions */ + +#ifdef __cplusplus +} +#endif + +#endif /* CY_I2S_H */ + + +/** \} group_i2s */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_config.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_config.c new file mode 100644 index 0000000000..d2ebdd9a52 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_config.c @@ -0,0 +1,143 @@ +/***************************************************************************//** +* \file cy_ipc_config.c +* \version 1.10 +* +* Description: +* This C file is not intended to be part of the IPC driver. It is the code +* required to configure the device specific IPC channels for semaphores +* and pipes. +* +******************************************************************************** +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "flash/cy_flash.h" +#include "ipc/cy_ipc_drv.h" +#include "ipc/cy_ipc_pipe.h" +#include "ipc/cy_ipc_sema.h" +#include "sysint/cy_sysint.h" + +#include "cy_ipc_config.h" + +static void Cy_Flash_NotifyHandler(uint32_t * msgPtr); + +/* Create an array of endpoint structures */ +static cy_stc_ipc_pipe_ep_t cy_ipc_pipe_sysEpArray[CY_IPC_MAX_ENDPOINTS]; + +#define CY_CYPIPE_DEFAULT_CONFIG \ +{\ + /* .ep0ConfigData */ {\ + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,\ + /* .ipcNotifierPriority */ CY_IPC_INTR_CYPIPE_PRIOR_EP0,\ + /* .ipcNotifierMuxNumber */ CY_IPC_INTR_CYPIPE_MUX_EP0,\ + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,\ + /* .epConfig */ CY_IPC_CYPIPE_CONFIG_EP0\ + },\ + /* .ep1ConfigData */ {\ + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,\ + /* .ipcNotifierPriority */ CY_IPC_INTR_CYPIPE_PRIOR_EP1,\ + /* .ipcNotifierMuxNumber */ 0u,\ + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,\ + /* .epConfig */ CY_IPC_CYPIPE_CONFIG_EP1\ + },\ + /* .endpointClientsCount */ CY_IPC_CYPIPE_CLIENT_CNT,\ + /* .endpointsCallbacksArray */ cy_ipc_pipe_sysCbArray,\ + /* .userPipeIsrHandler */ &Cy_IPC_SystemPipeIsr\ +} + +/******************************************************************************* +* Function Name: Cy_IPC_SystemSemaInit +****************************************************************************//** +* +* Initializes the system semaphores. +* +*******************************************************************************/ +void Cy_IPC_SystemSemaInit(void) +{ +/* Create array used for semaphores */ +#if !(CY_CPU_CORTEX_M0P) + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#else + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); +#endif +} + +/******************************************************************************* +* Function Name: Cy_IPC_SystemPipeInit +****************************************************************************//** +* +* Initializes the system pipes. The system pipes are used by BLE. +* \note The function should be called on all CPUs. +* +*******************************************************************************/ +void Cy_IPC_SystemPipeInit(void) +{ + uint32_t intr; + + intr = Cy_SysLib_EnterCriticalSection(); + + static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_sysCbArray[CY_IPC_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemPipeConfig = CY_CYPIPE_DEFAULT_CONFIG; + + Cy_IPC_Pipe_Config(cy_ipc_pipe_sysEpArray); + + Cy_IPC_Pipe_Init(&systemPipeConfig); + + (void)Cy_IPC_Pipe_RegisterCallback(CY_IPC_EP_CYPIPE_ADDR, &Cy_Flash_NotifyHandler, (uint32_t)CY_FLASH_IPC_CLIENT_ID); + + Cy_SysLib_ExitCriticalSection(intr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_SystemPipeIsr +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_IPC_SystemPipeIsr(void) +{ + Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_CYPIPE_ADDR]); +} + +/******************************************************************************* +* Function Name: Cy_Flash_NotifyHandler +****************************************************************************//** +* +* This is the interrupt service routine for the pipe notifications. +* +*******************************************************************************/ +#if defined (__ICCARM__) + __ramfunc +#else + CY_SECTION(".cy_ramfunc") +#endif +static void Cy_Flash_NotifyHandler(uint32_t * msgPtr) +{ + uint32_t intr; + + IPC_MSG *ipcMsgPtr = (IPC_MSG *)msgPtr; + + if (CY_FLASH_ENTER_WAIT_LOOP == ipcMsgPtr->pktType) + { + intr = Cy_SysLib_EnterCriticalSection(); + + /* Notification to the Flash driver to start the current operation */ + (void) Cy_IPC_Sema_Set(CY_FLASH_WAIT_SEMA, true); + + /* Notification to me about the end of the operation */ + while (CY_IPC_SEMA_STATUS_LOCKED == Cy_IPC_Sema_Status(CY_FLASH_WAIT_SEMA)) + { + } + + Cy_SysLib_ExitCriticalSection(intr); + } +} + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_config.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_config.h new file mode 100644 index 0000000000..97be5db9ee --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_config.h @@ -0,0 +1,137 @@ +/***************************************************************************//** +* \file cy_ipc_config.h +* \version 1.10 +* +* \brief +* This header file is not intended to be part of the IPC driver since it defines +* a device specific configuration for the IPC channels and pipes. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef CY_IPC_CONFIG_H +#define CY_IPC_CONFIG_H + +/* IPC Resources */ +#define CY_IPC_CHANNELS (uint32_t)(CPUSS_IPC_IPC_NR) +#define CY_IPC_INTERRUPTS (uint32_t)(CPUSS_IPC_IPC_IRQ_NR) + +/* IPC channel definitions */ +#define CY_IPC_CHAN_SYSCALL_CM0 (0u) /* System calls for the CM0 processor */ +#define CY_IPC_CHAN_SYSCALL_CM4 (1u) /* System calls for the 1st non-CM0 processor */ +#if (CY_CPU_CORTEX_M0P) + #define CY_IPC_CHAN_SYSCALL CY_IPC_CHAN_SYSCALL_CM0 + #define Cy_IPC_SystemPipeIsr NvicMux1_IRQHandler +#else + #define CY_IPC_CHAN_SYSCALL CY_IPC_CHAN_SYSCALL_CM4 + #define Cy_IPC_SystemPipeIsr cpuss_interrupts_ipc_4_IRQHandler +#endif /* (CY_CPU_CORTEX_M0P) */ + +#define CY_IPC_CHAN_SYSCALL_DAP (uint32_t)(2u) /**< System calls for the DAP */ +#define CY_IPC_CHAN_CRYPTO (uint32_t)(3u) /**< IPC data channel for the Crypto */ +#define CY_IPC_CHAN_SEMA (uint32_t)(4u) /**< IPC data channel for the Semaphores */ + +#define CY_IPC_CHAN_CYPIPE_EP0 (uint32_t)(5u) /**< IPC data channel for CYPIPE EP0 */ +#define CY_IPC_CHAN_CYPIPE_EP1 (uint32_t)(6u) /**< IPC data channel for CYPIPE EP1 */ + +/* IPC Notify interrupts definitions */ +#define CY_IPC_INTR_SYSCALL1 (uint32_t)(0u) + +#define CY_IPC_INTR_CRYPTO_SRV (uint32_t)(1u) /**< IPC interrupt structure for the Crypto server */ +#define CY_IPC_INTR_CRYPTO_CLI (uint32_t)(2u) /**< IPC interrupt structure for the Crypto client */ + +#define CY_IPC_INTR_SPARE (uint32_t)(7u) + +/* IPC Semaphores allocation + This will allow 128 (4*32) semaphores */ +#define CY_IPC_SEMA_COUNT (uint32_t)(128u) + +/* System IPC Notify Masks */ +#define CY_IPC_SEMA_NOTIFY_MASK (uint32_t)(0x0001ul << CY_IPC_CHAN_SEMA) + +/* System IPC channel release Masks */ +#define CY_IPC_SEM_RELEASE_MASK (uint32_t)(0x0001ul << CY_IPC_CHAN_SEMA) + +/* IPC Pipe definitions */ +#define CY_IPC_MAX_ENDPOINTS (uint32_t)(8u) + +/******************************************************************************* +** CY_PIPE default configuration +*******************************************************************************/ +#define CY_IPC_CYPIPE_CLIENT_CNT (uint32_t)(8u) +#define CY_IPC_USRPIPE_CLIENT_CNT (uint32_t)(8u) + +#if (CY_CPU_CORTEX_M0P) + #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM0_ADDR +#else + #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM4_ADDR +#endif /* (CY_CPU_CORTEX_M0P) */ + +#define CY_IPC_INTR_CYPIPE_MUX_EP0 (uint32_t)(1u) /* IPC CYPRESS PIPE */ +#define CY_IPC_INTR_CYPIPE_EP0 (uint32_t)(3u) /* Notifier EP0 */ +#define CY_IPC_INTR_CYPIPE_PRIOR_EP0 (uint32_t)(1u) /* Notifier Priority */ + +#define CY_IPC_INTR_CYPIPE_EP1 (uint32_t)(4u) /* Notifier EP1 */ +#define CY_IPC_INTR_CYPIPE_PRIOR_EP1 (uint32_t)(1u) /* Notifier Priority */ + +#define CY_IPC_CYPIPE_CHAN_MASK_EP0 (uint32_t)(0x0001ul << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_IPC_CYPIPE_CHAN_MASK_EP1 (uint32_t)(0x0001ul << CY_IPC_CHAN_CYPIPE_EP1) + +/* Endpoint indexes in the pipe array */ +#define CY_IPC_EP_CYPIPE_CM0_ADDR (uint32_t)(0u) +#define CY_IPC_EP_CYPIPE_CM4_ADDR (uint32_t)(1u) + +/******************************************************************************/ + +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_IPC_CYPIPE_CONFIG_EP0 (uint32_t)( (CY_IPC_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_IPC_CYPIPE_CONFIG_EP1 (uint32_t)( (CY_IPC_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) +#define CY_IPC_CYPIPE_INTR_MASK (uint32_t)( CY_IPC_CYPIPE_CHAN_MASK_EP0 | CY_IPC_CYPIPE_CHAN_MASK_EP1 ) + +/******************************************************************************/ +#define CY_IPC_CHAN_USRPIPE_CM0 (uint32_t)(8u) +#define CY_IPC_CHAN_USRPIPE_CM4 (uint32_t)(9u) + +#define CY_IPC_INTR_USRPIPE_CM0 (uint32_t)(8u) +#define CY_IPC_INTR_USRPIPE_CM4 (uint32_t)(9u) + +#define CY_IPC_EP_USRPIPE_ADDR_EP0 (uint32_t)(2u) +#define CY_IPC_EP_USRPIPE_ADDR_EP1 (uint32_t)(3u) + +#ifdef __cplusplus +extern "C" { +#endif + +void Cy_IPC_SystemSemaInit(void); +void Cy_IPC_SystemPipeInit(void); +void Cy_IPC_SystemPipeIsr(void); + +#ifdef __cplusplus +} +#endif + +#endif /* CY_IPC_CONFIG_H */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_drv.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_drv.c new file mode 100644 index 0000000000..b1d73a4778 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_drv.c @@ -0,0 +1,172 @@ +/***************************************************************************//** +* \file cy_ipc_drv.c +* \version 1.10 +* +* \breif +* IPC Driver - This source file contains the low-level driver code for +* the IPC hardware. +* +******************************************************************************** +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_ipc_drv.h" + + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_LockRelease +****************************************************************************//** +* +* The function is used to release an IPC channel from the locked state. +* The function also has a way to specify through a parameter which IPC +* interrupts must be notified during the release event. +* +* This function is internal and should not be called directly by user software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param releaseEventIntr +* Bit encoded list of IPC interrupt lines that are triggered by a release event. +* +* \return Status of the operation +* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC channel +* was released. +* \retval CY_IPC_DRV_ERROR: The IPC channel was not acquired before the +* function call. +* +*******************************************************************************/ +#if defined (__ICCARM__) + __ramfunc +#else + CY_SECTION(".cy_ramfunc") +#endif +cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t releaseEventIntr) +{ + cy_en_ipcdrv_status_t retStatus; + + /* Check to make sure the IPC is Acquired */ + if( Cy_IPC_Drv_IsLockAcquired(base) ) + { + /* The IPC was acquired, release the IPC channel */ + Cy_IPC_Drv_ReleaseNotify(base, releaseEventIntr); + + retStatus = CY_IPC_DRV_SUCCESS; + } + else /* The IPC channel was already released (not acquired) */ + { + retStatus = CY_IPC_DRV_ERROR; + } + + return (retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_SendMsgWord +****************************************************************************//** +* +* This function is used to send a 32-bit word message through an IPC channel. +* The function also has an associated notification field that will let the +* message notify one or multiple IPC interrupts. The IPC channel is locked and +* remains locked after the function returns. The receiver of the message should +* release the channel. +* +* This function is internal and should not be called directly by user software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt lines that are triggered by a notification. +* +* \param message +* The message word that is the data placed in the IPC data register. +* +* \return Status of the operation: +* \retval CY_IPC_DRV_SUCCESS: The send operation was successful. +* \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because it is already locked. +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, uint32_t message) +{ + cy_en_ipcdrv_status_t retStatus; + + if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire(base) ) + { + /* If the channel was acquired, send the message. */ + Cy_IPC_Drv_WriteDataValue(base, message); + + Cy_IPC_Drv_AcquireNotify(base, notifyEventIntr); + + retStatus = CY_IPC_DRV_SUCCESS; + } + else + { + /* Channel was already acquired, return Error */ + retStatus = CY_IPC_DRV_ERROR; + } + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ReadMsgWord +****************************************************************************//** +* +* This function is used to read a 32-bit word message through an IPC channel. +* This function assumes that the channel is locked (for a valid message). +* If the channel is not locked, the message is invalid. The user must call +* Cy_IPC_Drv_Release() function after reading the message to release the +* IPC channel. +* +* This function is internal and should not be called directly by user software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param message +* A variable where the read data is copied. +* +* \return Status of the operation +* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC +* was acquired. +* \retval CY_IPC_DRV_ERROR: The function encountered an error because the IPC +* channel was already in a released state, meaning the data +* may be invalid. +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message) +{ + cy_en_ipcdrv_status_t retStatus; + + CY_ASSERT_L1(NULL != message); + + if ( Cy_IPC_Drv_IsLockAcquired(base) ) + { + /* The channel is locked; message is valid. */ + *message = Cy_IPC_Drv_ReadDataValue(base); + + retStatus = CY_IPC_DRV_SUCCESS; + } + else + { + /* The channel is not locked so channel is invalid. */ + retStatus = CY_IPC_DRV_ERROR; + } + return(retStatus); +} + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_drv.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_drv.h new file mode 100644 index 0000000000..9c41d9f626 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_drv.h @@ -0,0 +1,900 @@ +/***************************************************************************//** +* \file cy_ipc_drv.h +* \version 1.10 +* +* Provides an API declaration of the IPC driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef CY_IPC_DRV_H +#define CY_IPC_DRV_H + + +/** +* \defgroup group_ipc Inter Process Communication (IPC) +* \{ +* The inter-processor communication (IPC) driver provides a safe and reliable +* method to transfer data between CPUs. Hardware locking ensures that only one +* device can acquire and transfer data at a time so no data is lost or +* overwritten by asynchronous processes or CPUs. +* +* There are three parts to the API: +* - Driver-level (DRV) API - used internally by Semaphore and Pipe levels +* - Pipe-level (PIPE) API - establishes a communication channel between +* processors +* - Semaphore-level (SEMA) API - enables users to set and clear flags to +* synchronize operations. +* +* Firmware does not need to use the DRV API. It can implement IPC functionality +* entirely with the PIPE and SEMA APIs. +* +* \note "Warning[Ta023]: Call to a non __ramfunc function." - The warning may +* appear during the build process while using IAR IDE. The reason - some +* functions in RAM memory that use the __ramfunc keyword, may invoke +* functions located in the ROM memory. You can ignore this warning or +* disable it by adding the --diag_suppress=Ta023 option to the compiler. +* +* \section group_ipc_background Background +* +* IPC is implemented in hardware as a collection of individual communication +* channels, each with a set of 32-bit registers. The IPC design implements a set +* of interrupts that enable each processor to notify the other that data is +* available, or has been processed. There is also a locking mechanism that +* allows only one CPU to gain access at a time. +* +* The Driver-level API manages each channel's registers to implement IPC +* functionality. For information on the IPC registers, see the IPC chapter of +* the Technical Reference Manual (TRM). +* +* At the hardware level, communication is a five-step process. +* -# The sending processor acquires a channel +* -# It puts data into the channel +* -# The sender generates a notify event (interrupt) +* -# The receiving processor identifies the sender and retrieves the data +* -# The receiving processor generates a release event (interrupt) +* +* \image html ipc_driver.png +* +* These transactions are handled transparently by the DRV-level API. Use the +* PIPE and SEMA layers of the API to implement communication in your application. +* The data transferred is limited to a single 32-bit value. As implemented by +* the PIPE API, that value is a pointer to a data structure of arbitrary size +* and complexity. +* +* \section group_ipc_overview Overview +* +* The Pipe is the key element in the PDL design. A pipe is typically a +* full-duplex communication channel between CPU cores. A pipe allows a single +* conduit to transfer messages or data to and from multiple processes or CPUs. +* +* A pipe has two endpoints, one on each core. Each endpoint contains a dedicated +* IPC channel and an interrupt. IPC channels 0-7 and IPC interrupts 0-7 are +* reserved for system use. +* +* The pipe also contains the number of clients it supports, and for each client +* a callback function. So the pipe can service a number of clients, each with a +* separate callback function, on either endpoint. The number of clients a pipe +* supports is the sum of each endpoint's clients. +* +* This design enables any number of processes on the sending core to put +* arbitrary data into a single pipe. The first element of that data is the +* client ID of the client that should handle the data. +* +* An interrupt notifies the receiving core that data is available. The receiving +* core parses the data to identify the client, and then dispatches the event to +* the appropriate client via the client callback function. An interrupt notifies +* the sending core that the receiver is finished. In this way a single pipe can +* manage arbitrary data transfers between cores with data flowing in either +* direction. +* +* \image html ipc_ints.png +* +* The application can use semaphores to control access to shared resources, as +* required by the application's logic. +* +* The PDL provides two specific files that set up default IPC functionality. +* They are cy_ipc_config.h and cy_ipc_config.c. You can modify these files based +* on the requirements of your design. If you use PSoC Creator as a development +* environment, it will not overwrite your changes when you generate the +* application or build your code. +* +* \section group_ipc_pipe_layer PIPE layer +* +* A pipe is a communication channel between two endpoints. PSoC 6 devices support +* 16 IPC channels, and 16 IPC interrupts, each numbered 0-15. IPC Channels 0-7 +* and IPC interrupts 0-7 are reserved for system use. Channels 8-15 and +* interrupts 8-15 are available for application use. +* +* A full duplex pipe uses two IPC channels, one per endpoint. Each endpoint +* specifies all the information required to process a message (either sent or +* received). Each endpoint is configured to use an IPC channel, and an IPC +* interrupt. Common practice is to use the interrupt with the same number as +* the IPC channel. However, IPC Interrupts are not directly associated with the +* IPC channels, so any channel can use any interrupt. Any IPC channel can +* trigger 0, 1 or all the IPC interrupts at once, depending on the Notify or +* Release masks used. +* +* It is also possible to set up a one-directional pipe, using a single IPC +* channel. In this design one processor is always the sender, and the other is +* always the receiver. However, there are still two endpoints. +* +* A pipe supports an arbitrary number of clients with an array of callback +* functions, one per client. The client ID is the index number into the array +* for the client. After a pipe is configured and initialized, the application +* calls Cy_IPC_Pipe_RegisterCallback() once per client to register each client's +* callback function. Multiple clients can use the same callback function. The +* endpoints in a pipe share the callback array. +* +* Use Cy_IPC_Pipe_SendMessage() to send data. You specify both the "to" and +* "from" endpoints, and a callback function to be used when the data transfer is +* complete. The data is a 32-bit void pointer. The data pointed to is arbitrary, +* and can be an array, a structure, or a location in memory. The only limitation +* is that the first element of the data must be a 32-bit unsigned word containing +* a client ID number. The ID number is the index into the callback array. +* +* When a message is sent, the receiving endpoint's interrupt handler is called. +* The ISR can perform any task required by the design. However, as part of its +* function it calls \ref Cy_IPC_Pipe_ExecCallback. This function retrieves the +* client ID from the data and calls the associated callback function. +* The user-supplied callback function handles the data in whatever way is +* appropriate based on the application logic. +* +* After the callback function is returned by the receiver, it invokes the release +* callback function defined by the sender of the message. +* +* \section group_ipc_sema_layer SEMA Layer +* +* A semaphore is a flag the application uses to control access to a shared +* resource. The SEMA-level API uses an IPC channel to implement +* semaphores. Startup code sets up a default semaphore system. The +* default system creates an array of 128 semaphores (four 32-bit values). +* Semaphores 0-15 are reserved for system use. See +* Configuration Considerations - SEMA. +* +* Functions are available to initialize the semaphore system, to set or +* clear a semaphore, or to get the semaphore's current status. Application +* logic uses SEMA functions to relate a particular semaphore to a particular +* shared resource, and set, clear, or check the flag when accessing the +* shared resource. +* +* \section group_ipc_configuration_cypipe Configuration Considerations - CYPIPE +* +* There are none. The cy_ipc_config files set up the required CYPIPE for system +* use. Do not modify the CYPIPE. It uses IPC channels 5 and 6 to implement full +* duplex communication between cores. On the CM0+ the notify interrupt is +* assigned to NVIC IRQn 27. See System Interrupt (SysInt) for background. +* +* \section group_ipc_configuration_sema Configuration Considerations - SEMA +* +* Startup code calls Cy_IPC_SystemSemaInit (in cy_ipc_config.c) to set up +* semaphore functionality. This function calls the PDL init function +* Cy_IPC_Sema_Init() with default values. By default the semaphore system +* uses IPC channel 4, and creates 128 semaphores. Do not change the IPC +* channel. You can change the number of semaphores. +* +* To change the number of semaphores, modify this line of code in cy_ipc_config.h. +* +* \code +* #define CY_IPC_SEMA_COUNT (uint32_t)(128u) +* \endcode +* +* The file cy_ipc_config.c declares array ipcSemaArray to hold the semaphore +* flags based on the size defined for this symbol. Use increments of 32. You +* must have at least 32 semaphores. Semaphores 0-15 are reserved for +* system use. Your application can use semaphores greater than 15. +* +* \section group_ipc_more_information More Information +* +* See the technical reference manual(TRM) for more information on the IPC. +* +* \section group_ipc_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
    10.3RThe value of a complex expression of integer type shall be cast +* only to a type of the same signedness that is no wider than the underlying +* type of the expression.The cast from integer to enumeration value is used to calculate +* the interrupt vector source from the integer number of the IPC interrupt +* structure, so there is no way to avoid this cast.
    11.4AA cast should not be performed between a pointer to the void to a +* pointer to the object type.The cast from the void to pointer and vice versa is used to transmit +* data via the \ref group_ipc channel by exchanging the pointer. We +* exchange only one pointer, so there is no way to avoid this cast.
    +* +* \defgroup group_ipc_drv IPC driver layer (IPC_DRV) +* \{ +* The functions of this layer are used in the higher IPC levels +* (Semaphores and Pipes). +* Users should not call any of these IPC functions directly. +* +* \defgroup group_ipc_macros Macros +* Macro definitions are used in the driver +* +* \defgroup group_ipc_functions Functions +* Functions are used in the driver +* +* \defgroup group_ipc_data_structures Data Structures +* Data structures are used in the driver +* +* \defgroup group_ipc_enums Enumerated Types +* Enumerations are used in the driver +* \} +* +* \defgroup group_ipc_sema IPC semaphores layer (IPC_SEMA) +* \defgroup group_ipc_pipe IPC pipes layer (IPC_PIPE) +* +*/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" +#include "cy_ipc_config.h" +#include + +/** +* \addtogroup group_ipc_macros +* \{ +*/ + +/** Driver major version */ +#define CY_IPC_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_IPC_DRV_VERSION_MINOR 10 + +/** Defines a value to indicate that no notification events are needed */ +#define CY_IPC_NO_NOTIFICATION (uint32_t)(0x00000000ul) + +/* Error Code constants */ +#define CY_IPC_ID CY_PDL_DRV_ID(0x22u) /**< Software PDL driver ID for IPC */ + +/** Return prefix for IPC driver function status codes */ +#define CY_IPC_ID_INFO (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_INFO ) +/** Return prefix for IPC driver function warning return values */ +#define CY_IPC_ID_WARNING (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_WARNING) +/** Return prefix for IPC driver function error return values */ +#define CY_IPC_ID_ERROR (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_ERROR) + +/** Converts the IPC interrupt channel number to interrupt vector */ +#define CY_IPC_INTR_NUM_TO_VECT(x) ((int32_t)cpuss_interrupts_ipc_0_IRQn + (x)) + +/** \} group_ipc_macros */ + +/* end of definition in device.h */ + + +/** +* \addtogroup group_ipc_enums +* \{ +*/ + +/** +* This is a list of ENUMs used for function return status. +*/ +typedef enum +{ + /** Function was successfully executed */ + CY_IPC_DRV_SUCCESS = (0x00u), + /** Function was not executed due to an error. + Typical conditions for the error explained + in the function description */ + CY_IPC_DRV_ERROR = ( CY_IPC_ID_ERROR + 1ul), +} cy_en_ipcdrv_status_t; + +/** \} group_ipc_enums */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** \cond INTERNAL */ + +__STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint32_t dataValue); +__STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base); +__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr); + +__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractAcquireMask (uint32_t intMask); +__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask); + +/** \endcond */ + +/** +* \addtogroup group_ipc_functions +* \{ +*/ + +__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex); +__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex); + +__STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type * base, uint32_t notifyEventIntr); + +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base); +cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type * base, uint32_t releaseEventIntr); +__STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base); +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base); + +cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type * base, uint32_t notifyEventIntr, uint32_t message); +cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message); +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr); +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr); + +__STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type * base, + uint32_t ipcReleaseMask, uint32_t ipcNotifyMask); +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask (IPC_INTR_STRUCT_Type const * base); +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base); +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus (IPC_INTR_STRUCT_Type const * base); +__STATIC_INLINE void Cy_IPC_Drv_SetInterrupt (IPC_INTR_STRUCT_Type * base, + uint32_t ipcReleaseMask, uint32_t ipcNotifyMask); +__STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt (IPC_INTR_STRUCT_Type * base, + uint32_t ipcReleaseMask, uint32_t ipcNotifyMask); + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetIpcBaseAddress +****************************************************************************//** +* +* This function takes an IPC channel index as a parameter and returns the base +* address the IPC registers corresponding to the IPC channel. +* +* This function is internal and should not be called directly by user +* software. +* +* \note The user is responsible for ensuring that ipcIndex does not exceed the +* limits. +* +* \param ipcIndex +* Represents the number of IPC structure. This is converted to the base address of +* the IPC channel registers. +* +* \return +* Returns a pointer to the base of the IPC registers. +* +*******************************************************************************/ +__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex) +{ + CY_ASSERT_L1((uint32_t)CY_IPC_CHANNELS > ipcIndex); + return ( (IPC_STRUCT_Type*) ( &IPC->STRUCT[ipcIndex] ) ); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetIntrBaseAddr +****************************************************************************//** +* +* This function takes an IPC interrupt structure index and returns the base +* address of the IPC interrupt registers corresponding to the IPC Interrupt. +* +* This function is internal and should not be called directly by user +* software. +* +* \note The user is responsible for ensuring that ipcIntrIndex does not exceed the +* limits. +* +* \param ipcIntrIndex +* Represents the number of IPC interrupt structure. This is converted to the +* base address of the IPC interrupt registers. +* +* \return +* Returns a pointer to the base of the IPC interrupt registers. +* +*******************************************************************************/ +__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex) +{ + CY_ASSERT_L1((uint32_t)CY_IPC_INTERRUPTS > ipcIntrIndex); + return ( (IPC_INTR_STRUCT_Type*) ( &IPC->INTR_STRUCT[ipcIntrIndex] ) ); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_SetInterruptMask +****************************************************************************//** +* +* This function is used to set the interrupt mask for an IPC Interrupt. +* The mask sets release or acquire notification events for all IPC channels. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from the +* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \param ipcReleaseMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* release event. +* +* \param ipcNotifyMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* notify event. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type* base, + uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) +{ + CY_ASSERT_L1(0ul == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); + CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk))); + base->INTR_MASK = _VAL2FLD( IPC_INTR_STRUCT_INTR_MASK_NOTIFY, ipcNotifyMask) | + _VAL2FLD( IPC_INTR_STRUCT_INTR_MASK_RELEASE, ipcReleaseMask); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetInterruptMask +****************************************************************************//** +* +* This function is used to read the interrupt mask. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from +* the IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \return +* The return value is encoded as follows +* +*
    Interrupt sources Value +*
    Ipc_PORTX_RELEASE Xth bit set +*
    Ipc_PORTX_NOTIFY X+16th bit set +*
    +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask(IPC_INTR_STRUCT_Type const * base) +{ + return (base->INTR_MASK); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetInterruptStatusMasked +****************************************************************************//** +* +* This function is used to read the active unmasked interrupt. This function +* can be used in the interrupt service routine to find which source triggered +* the interrupt. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from the +* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \return +* The return value is encoded as follows +* +*
    Interrupt sources Value +*
    Ipc_PORTX_RELEASE Xth bit set +*
    Ipc_PORTX_NOTIFY X+16th bit set +*
    +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base) +{ + return (base->INTR_MASKED); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetInterruptStatus +****************************************************************************//** +* +* This function is used to read the pending interrupts. Note that this read is +* an unmasked read of the interrupt status. Interrupt sources read as active by +* this function would generate interrupts only if they were not masked. + +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from the +* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \return +* The return value is encoded as follows +* +*
    Interrupt sources Value +*
    Ipc_PORTX_RELEASE Xth bit set +*
    Ipc_PORTX_NOTIFY X+16th bit set +*
    +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus(IPC_INTR_STRUCT_Type const * base) +{ + return (base->INTR); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_SetInterrupt +****************************************************************************//** +* +* This function is used to set the interrupt source. This function can be used +* to activate interrupts through software. +* \note That interrupt sources set using this interrupt would generate interrupts +* only if they are not masked. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from the +* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \param ipcReleaseMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* release event. +* +* \param ipcNotifyMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* notify event. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_SetInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) +{ + CY_ASSERT_L1(0ul == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); + CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk))); + base->INTR_SET = _VAL2FLD( IPC_INTR_STRUCT_INTR_NOTIFY, ipcNotifyMask ) | + _VAL2FLD( IPC_INTR_STRUCT_INTR_RELEASE, ipcReleaseMask ); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ClearInterrupt +****************************************************************************//** +* +* This function is used to clear the interrupt source. Use this function to clear +* a pending interrupt source in the interrupt status. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from the +* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \param ipcReleaseMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* release event. +* +* \param ipcNotifyMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* notify event. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) +{ + CY_ASSERT_L1(0ul == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); + CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk))); + base->INTR = _VAL2FLD(IPC_INTR_STRUCT_INTR_NOTIFY, ipcNotifyMask) | + _VAL2FLD(IPC_INTR_STRUCT_INTR_RELEASE, ipcReleaseMask); + (void)base->INTR; /* Read the register to flush the cache */ +} + +/** \} group_ipc_functions */ + +/** \} group_ipc */ + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_AcquireNotify +****************************************************************************//** +* +* The function generates a notify event by IPC interrupt structures. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt structures that are triggered +* by a notification. Bit number correspond to number of the IPC interrupt +* structure. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr) +{ + CY_ASSERT_L1(0ul == (notifyEventIntr & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); + base->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, notifyEventIntr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ReleaseNotify +****************************************************************************//** +* +* The function generates a notify event to an IPC interrupt structure. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt lines that are triggered by a notification. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr) +{ + CY_ASSERT_L1(0ul == (notifyEventIntr & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); + base->RELEASE = _VAL2FLD(IPC_INTR_STRUCT_INTR_RELEASE, notifyEventIntr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_WriteDataValue +****************************************************************************//** +* +* The function writes a value to the DATA register of the IPC channel. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param dataValue +* Value to be written. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint32_t dataValue) +{ + base->DATA = dataValue; +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ReadDataValue +****************************************************************************//** +* +* The function reads a value from the DATA register of the IPC channel. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \return +* Value from DATA register. +* +*******************************************************************************/ +#if defined (__ICCARM__) + __ramfunc +#else + CY_SECTION(".cy_ramfunc") +#endif +__STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base) +{ + return (base->DATA); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_IsLockAcquired +****************************************************************************//** +* +* The function is used to test the status of an IPC channel. The function +* tells the reader if the IPC channel was in the locked or released state. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \return +* Status for the function: +* true: The IPC channel is in the Locked state. +* false: The IPC channel is in the Released state. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base) +{ + return ( 0u != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, base->LOCK_STATUS) ); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetLockStatus +****************************************************************************//** +* +* The function is used to get the status of an IPC channel. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \return +* Value from LOCK_STATUS register. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base) +{ + return (base->LOCK_STATUS); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ExtractAcquireMask +****************************************************************************//** +* +* The function extracts an Acquire mask part from full interrupt mask value. +* +* This function is internal and should not be called directly by user +* software. +* +* \param intMask +* Interrupt mask value to be processed. +* +* \return +* Acquire mask value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractAcquireMask (uint32_t intMask) +{ + return _FLD2VAL(IPC_INTR_STRUCT_INTR_MASK_NOTIFY, intMask); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ExtractReleaseMask +****************************************************************************//** +* +* The function extracts a Release mask part from full interrupt mask value. +* +* This function is internal and should not be called directly by user +* software. +* +* \param intMask +* Interrupt mask value to be processed. +* +* \return +* Release mask value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask) +{ + return _FLD2VAL(IPC_INTR_STRUCT_INTR_MASK_RELEASE, intMask); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_SendMsgPtr +****************************************************************************//** +* +* This function is used to send a message pointer through an IPC channel. +* The message structure may hold a generic pointer that may contain the address +* of any user data type or structure. This parameter could be a pointer to a 32-bit +* integer, an array, or even a data structure defined in the user code. This +* function acts as a transfer engine for sending the pointer. Any memory +* management of the pointer allocation and deallocation is up to the application +* code. +* The function also has an associated notification field that will let the +* message notify one or multiple interrupts. +* +* This function is internal and should not be called directly by user software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt lines that are triggered during the release +* action. +* +* \param msgPtr +* The message pointer that is being sent over the IPC channel. +* +* \return Status of the operation: +* \retval CY_IPC_DRV_SUCCESS: The send operation was successful. +* \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because +* it is already locked. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr) +{ + CY_ASSERT_L1(NULL != msgPtr); + return Cy_IPC_Drv_SendMsgWord(base, notifyEventIntr, (uint32_t)msgPtr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ReadMsgPtr +****************************************************************************//** +* +* This function is used to read a 32-bit pointer message through an IPC channel. +* +* This function is internal and should not be called directly by user software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param msgPtr +* Pointer variable to hold the data pointer that is being read from the IPC +* channel. +* +* +* \return Status of the operation +* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC +* was acquired. +* \retval CY_IPC_DRV_ERROR: The function encountered an error because the IPC +* channel was already in a released state meaning the data +* in it is invalid. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr) +{ + CY_ASSERT_L1(NULL != msgPtr); + return Cy_IPC_Drv_ReadMsgWord(base, (uint32_t *)msgPtr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_LockAcquire +****************************************************************************//** +* +* This function is used to acquire the IPC channel. +* +* This function is internal and should not be called directly by user software +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress +* +* \return Status of the operation +* \retval CY_IPC_DRV_SUCCESS: The IPC was successfully acquired +* \retval CY_IPC_DRV_ERROR: The IPC was not acquired because it was already acquired +* by another master +* +*******************************************************************************/ +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base) +{ + return ( 0ul != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, base->ACQUIRE)) ? CY_IPC_DRV_SUCCESS : CY_IPC_DRV_ERROR; +} + +#ifdef __cplusplus +} +#endif + +#endif /* !defined(CY_IPC_DRV_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c new file mode 100644 index 0000000000..96617a3db1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c @@ -0,0 +1,515 @@ +/***************************************************************************//** +* \file cy_ipc_pipe.c +* \version 1.10 +* +* Description: +* IPC Pipe Driver - This source file includes code for the Pipe layer on top +* of the IPC driver. +* +******************************************************************************** +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_ipc_pipe.h" + +/* Define a pointer to array of endPoints. */ +static cy_stc_ipc_pipe_ep_t * cy_ipc_pipe_epArray = NULL; + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_Config +****************************************************************************//** +* +* This function stores a copy of a pointer to the array of endpoints. All +* access to endpoints will be via the index of the endpoint in this array. +* +* \param theEpArray +* This is the pointer to an array of endpoint structures that the designer +* created and will be used to reference all endpoints. +* +*******************************************************************************/ +void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray) +{ + /* Keep copy of this endpoint */ + if (cy_ipc_pipe_epArray == NULL) + { + cy_ipc_pipe_epArray = theEpArray; + } +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_Init +****************************************************************************//** +* +* Initializes the system pipes. The system pipes are used by BLE. +* \note The function should be called on all CPUs. +* +* \param config +* This is the pointer to the pipe configuration structure +* +*******************************************************************************/ +void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config) +{ + /* Create the interrupt structures and arrays needed */ + + cy_stc_sysint_t ipc_intr_cypipeConfig; + + cy_stc_ipc_pipe_ep_config_t epConfigDataA; + cy_stc_ipc_pipe_ep_config_t epConfigDataB; + + /* Parameters checking begin */ + CY_ASSERT_L1(NULL != config); + #if (CY_CPU_CORTEX_M0P) + CY_ASSERT_L2((uint32_t)(1UL << __NVIC_PRIO_BITS) > config->ep0ConfigData.ipcNotifierPriority); + #else + CY_ASSERT_L2((uint32_t)(1UL << __NVIC_PRIO_BITS) > config->ep1ConfigData.ipcNotifierPriority); + #endif + CY_ASSERT_L1(NULL != config->endpointsCallbacksArray); + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > config->ep0ConfigData.epAddress); + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > config->ep1ConfigData.epAddress); + CY_ASSERT_L1(NULL != config->userPipeIsrHandler); + /* Parameters checking end */ + +#if (CY_CPU_CORTEX_M0P) + + /* Receiver endpoint = EP0, Sender endpoint = EP1 */ + epConfigDataA = config->ep0ConfigData; + epConfigDataB = config->ep1ConfigData; + + /* Configure CM0 interrupts */ + ipc_intr_cypipeConfig.intrSrc = (IRQn_Type)epConfigDataA.ipcNotifierMuxNumber; + ipc_intr_cypipeConfig.cm0pSrc = (cy_en_intr_t)((int32_t)cpuss_interrupts_ipc_0_IRQn + (int32_t)epConfigDataA.ipcNotifierNumber); + ipc_intr_cypipeConfig.intrPriority = epConfigDataA.ipcNotifierPriority; + +#else + + /* Receiver endpoint = EP1, Sender endpoint = EP0 */ + epConfigDataA = config->ep1ConfigData; + epConfigDataB = config->ep0ConfigData; + + /* Configure interrupts */ + ipc_intr_cypipeConfig.intrSrc = (IRQn_Type)(cpuss_interrupts_ipc_0_IRQn + epConfigDataA.ipcNotifierNumber); + ipc_intr_cypipeConfig.intrPriority = epConfigDataA.ipcNotifierPriority; + +#endif + + /* Initialize the pipe endpoints */ + Cy_IPC_Pipe_EndpointInit(epConfigDataA.epAddress, + config->endpointsCallbacksArray, + config->endpointClientsCount, + epConfigDataA.epConfig, + &ipc_intr_cypipeConfig); + + /* Create the endpoints for the CM4 just for reference */ + Cy_IPC_Pipe_EndpointInit(epConfigDataB.epAddress, NULL, 0ul, epConfigDataB.epConfig, NULL); + + (void)Cy_SysInt_Init(&ipc_intr_cypipeConfig, config->userPipeIsrHandler); + + /* Enable the interrupts */ + NVIC_EnableIRQ(ipc_intr_cypipeConfig.intrSrc); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_EndpointInit +****************************************************************************//** +* +* This function initializes the endpoint of a pipe for the current CPU. The +* current CPU is the CPU that is executing the code. An endpoint of a pipe +* is for the IPC channel that receives a message for the current CPU. +* +* After this function is called, the callbackArray needs to be populated +* with the callback functions for that endpoint using the +* Cy_IPC_Pipe_RegisterCallback() function. +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint you want to initialize. +* +* \param cbArray +* This is a pointer to the callback function array. Based on the client ID, one +* of the functions in this array is called to process the message. +* +* \param cbCnt +* This is the size of the callback array, or the number of defined clients. +* +* \param epConfig +* This value defines the IPC channel, IPC interrupt number, and the interrupt +* mask for the entire pipe. +* The format of the endpoint configuration +* Bits[31:16] Interrupt Mask +* Bits[15:8 ] IPC interrupt +* Bits[ 7:0 ] IPC channel +* +* \param epInterrupt +* This is a pointer to the endpoint interrupt description structure. +* +*******************************************************************************/ +void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray, + uint32_t cbCnt, uint32_t epConfig, cy_stc_sysint_t const *epInterrupt) +{ + cy_stc_ipc_pipe_ep_t * endpoint; + + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); + + endpoint = &cy_ipc_pipe_epArray[epAddr]; + + /* Extract the channel, interrupt and interrupt mask */ + endpoint->ipcChan = _FLD2VAL(CY_IPC_PIPE_CFG_CHAN, epConfig); + endpoint->intrChan = _FLD2VAL(CY_IPC_PIPE_CFG_INTR, epConfig); + endpoint->pipeIntMask = _FLD2VAL(CY_IPC_PIPE_CFG_IMASK, epConfig); + + /* Assign IPC channel to this endpoint */ + endpoint->ipcPtr = Cy_IPC_Drv_GetIpcBaseAddress (endpoint->ipcChan); + + /* Assign interrupt structure to endpoint and Initialize the interrupt mask for this endpoint */ + endpoint->ipcIntrPtr = Cy_IPC_Drv_GetIntrBaseAddr(endpoint->intrChan); + + /* Only allow notify and release interrupts from endpoints in this pipe. */ + Cy_IPC_Drv_SetInterruptMask(endpoint->ipcIntrPtr, endpoint->pipeIntMask, endpoint->pipeIntMask); + + /* Save the Client count and the callback array pointer */ + endpoint->clientCount = cbCnt; + endpoint->callbackArray = cbArray; + endpoint->busy = CY_IPC_PIPE_ENDPOINT_NOTBUSY; + + if (NULL != epInterrupt) + { + endpoint->pipeIntrSrc = epInterrupt->intrSrc; + } +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_SendMessage +****************************************************************************//** +* +* This function is used to send a message from one endpoint to another. It +* generates an interrupt on the endpoint that receives the message and a +* release interrupt to the sender to acknowledge the message has been processed. +* +* \param toAddr +* This parameter is the address (or index in the array of endpoint structures) +* of the endpoint to which you are sending the message. +* +* \param fromAddr +* This parameter is the address (or index in the array of endpoint structures) +* of the endpoint from which the message is being sent. +* +* \param msgPtr +* Pointer to the message structure to be sent. +* +* \param callBackPtr +* Pointer to the Release callback function. +* +* \return +* CY_IPC_PIPE_SUCCESS: Message was sent to the other end of the pipe +* CY_IPC_PIPE_ERROR_BAD_HANDLE: The handle provided for the pipe was not valid +* CY_IPC_PIPE_ERROR_SEND_BUSY: The pipe is already busy sending a message +* +*******************************************************************************/ +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr, + void * msgPtr, cy_ipc_pipe_relcallback_ptr_t callBackPtr) +{ + cy_en_ipc_pipe_status_t returnStatus; + uint32_t releaseMask; + uint32_t notifyMask; + + cy_stc_ipc_pipe_ep_t * fromEp; + cy_stc_ipc_pipe_ep_t * toEp; + + CY_ASSERT_L1(NULL != msgPtr); + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > toAddr); + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > fromAddr); + + toEp = &(cy_ipc_pipe_epArray[toAddr]); + fromEp = &cy_ipc_pipe_epArray[fromAddr]; + + /* Create the release mask for the "fromAddr" channel's interrupt channel */ + releaseMask = (uint32_t)(1ul << (fromEp->intrChan)); + + /* Shift into position */ + releaseMask = _VAL2FLD(CY_IPC_PIPE_MSG_RELEASE, releaseMask); + + /* Create the notify mask for the "toAddr" channel's interrupt channel */ + notifyMask = (uint32_t)(1ul << (toEp->intrChan)); + + /* Check if IPC channel valid */ + if( toEp->ipcPtr != NULL) + { + if(fromEp->busy == CY_IPC_PIPE_ENDPOINT_NOTBUSY) + { + /* Attempt to acquire the channel */ + if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire(toEp->ipcPtr) ) + { + /* Mask out the release mask area */ + * (uint32_t *) msgPtr &= ~(CY_IPC_PIPE_MSG_RELEASE_Msk); + + * (uint32_t *) msgPtr |= releaseMask; + + /* If the channel was acquired, write the message. */ + Cy_IPC_Drv_WriteDataValue(toEp->ipcPtr, (uint32_t) msgPtr); + + /* Set the busy flag. The ISR clears this after the release */ + fromEp->busy = CY_IPC_PIPE_ENDPOINT_BUSY; + + /* Setup release callback function */ + fromEp->releaseCallbackPtr = callBackPtr; + + /* Cause notify event/interrupt */ + Cy_IPC_Drv_AcquireNotify(toEp->ipcPtr, notifyMask); + + returnStatus = CY_IPC_PIPE_SUCCESS; + } + else + { + /* Channel was already acquired, return Error */ + returnStatus = CY_IPC_PIPE_ERROR_SEND_BUSY; + } + } + else + { + /* Channel may not be acquired, but the release interrupt has not executed yet */ + returnStatus = CY_IPC_PIPE_ERROR_SEND_BUSY; + } + } + else + { + /* Null pipe handle. */ + returnStatus = CY_IPC_PIPE_ERROR_BAD_HANDLE; + } + return (returnStatus); +} + + + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_RegisterCallback +****************************************************************************//** +* +* This function registers a callback that is called when a message is received +* on a pipe. +* The client_ID is the same as the index of the callback function array. +* The callback may be a real function pointer or NULL if no callback is required. +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint to which you want to add callback functions. +* +* \param callBackPtr +* Pointer to the callback function called when the endpoint has received a message. +* +* \param clientId +* The index in the callback array (Client ID) where the function pointer is saved. +* +* \return +* CY_IPC_PIPE_SUCCESS: Callback registered successfully +* CY_IPC_PIPE_ERROR_BAD_CLIENT: Client ID out of range, callback not registered. +*******************************************************************************/ +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId) +{ + cy_en_ipc_pipe_status_t returnStatus; + cy_stc_ipc_pipe_ep_t * thisEp; + + CY_ASSERT_L1(NULL != callBackPtr); + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); + + thisEp = &cy_ipc_pipe_epArray[epAddr]; + + /* Check if clientId is between 0 and less than client count */ + if (clientId < thisEp->clientCount) + { + /* Copy callback function into callback function pointer array */ + thisEp->callbackArray[clientId] = callBackPtr; + + returnStatus = CY_IPC_PIPE_SUCCESS; + } + else + { + returnStatus = CY_IPC_PIPE_ERROR_BAD_CLIENT; + } + return (returnStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_RegisterCallbackRel +****************************************************************************//** +* +* This function registers a default callback if a release interrupt +* is generated but the current release callback function is null. +* +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint to which you want to add a release callback function. +* +* \param callBackPtr +* Pointer to the callback executed when the endpoint has received a message. +* +* \return +* None +*******************************************************************************/ +void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr) +{ + cy_stc_ipc_pipe_ep_t * endpoint; + + CY_ASSERT_L1(NULL != callBackPtr); + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); + + endpoint = &cy_ipc_pipe_epArray[epAddr]; + + /* Copy callback function into callback function pointer array */ + endpoint->defaultReleaseCallbackPtr = callBackPtr; +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_ExecCallback +****************************************************************************//** +* +* This function is called by the ISR for a given pipe endpoint to dispatch +* the appropriate callback function based on the client ID for that endpoint. +* +* \param endpoint +* Pointer to endpoint structure. +* +* \return +* None +*******************************************************************************/ +void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint) +{ + uint32_t *msgPtr = NULL; + uint32_t clientID; + uint32_t shadowIntr; + uint32_t releaseMask = (uint32_t)0; + + cy_ipc_pipe_callback_ptr_t callbackPtr; + + /* Parameters checking begin */ + CY_ASSERT_L1(NULL != endpoint); + CY_ASSERT_L1(NULL != endpoint->ipcPtr); + CY_ASSERT_L1(NULL != endpoint->ipcIntrPtr); + CY_ASSERT_L1(NULL != endpoint->callbackArray); + /* Parameters checking end */ + + shadowIntr = Cy_IPC_Drv_GetInterruptStatusMasked(endpoint->ipcIntrPtr); + + /* Check to make sure the interrupt was a notify interrupt */ + if (0ul != Cy_IPC_Drv_ExtractAcquireMask(shadowIntr)) + { + /* Clear the notify interrupt. */ + Cy_IPC_Drv_ClearInterrupt(endpoint->ipcIntrPtr, CY_IPC_NO_NOTIFICATION, Cy_IPC_Drv_ExtractAcquireMask(shadowIntr)); + + if ( Cy_IPC_Drv_IsLockAcquired (endpoint->ipcPtr) ) + { + /* Extract Client ID */ + if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_ReadMsgPtr (endpoint->ipcPtr, (void **)&msgPtr)) + { + /* Get release mask */ + releaseMask = _FLD2VAL(CY_IPC_PIPE_MSG_RELEASE, *msgPtr); + clientID = _FLD2VAL(CY_IPC_PIPE_MSG_CLIENT, *msgPtr); + + /* Make sure client ID is within valid range */ + if (endpoint->clientCount > clientID) + { + callbackPtr = endpoint->callbackArray[clientID]; /* Get the callback function */ + + if (callbackPtr != NULL) + { + callbackPtr(msgPtr); /* Call the function pointer for "clientID" */ + } + } + } + + /* Must always release the IPC channel */ + (void)Cy_IPC_Drv_LockRelease (endpoint->ipcPtr, releaseMask); + } + } + + /* Check to make sure the interrupt was a release interrupt */ + if (0ul != Cy_IPC_Drv_ExtractReleaseMask(shadowIntr)) /* Check for a Release interrupt */ + { + /* Clear the release interrupt */ + Cy_IPC_Drv_ClearInterrupt(endpoint->ipcIntrPtr, Cy_IPC_Drv_ExtractReleaseMask(shadowIntr), CY_IPC_NO_NOTIFICATION); + + if (endpoint->releaseCallbackPtr != NULL) + { + endpoint->releaseCallbackPtr(); + + /* Clear the pointer after it was called */ + endpoint->releaseCallbackPtr = NULL; + } + else + { + if (endpoint->defaultReleaseCallbackPtr != NULL) + { + endpoint->defaultReleaseCallbackPtr(); + } + } + + /* Clear the busy flag when release is detected */ + endpoint->busy = CY_IPC_PIPE_ENDPOINT_NOTBUSY; + } + + (void)Cy_IPC_Drv_GetInterruptStatus(endpoint->ipcIntrPtr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_EndpointPause +****************************************************************************//** +* +* This function sets the receiver endpoint to paused state. +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint to pause. +* +* \return +* CY_IPC_PIPE_SUCCESS: Callback registered successfully +* +*******************************************************************************/ +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr) +{ + cy_stc_ipc_pipe_ep_t * endpoint; + + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); + + endpoint = &cy_ipc_pipe_epArray[epAddr]; + + /* Disable the interrupts */ + NVIC_DisableIRQ(endpoint->pipeIntrSrc); + + return (CY_IPC_PIPE_SUCCESS); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_EndpointResume +****************************************************************************//** +* +* This function sets the receiver endpoint to active state. +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint to resume. +* +* \return +* CY_IPC_PIPE_SUCCESS: Callback registered successfully +* +*******************************************************************************/ +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr) +{ + cy_stc_ipc_pipe_ep_t * endpoint; + + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); + + endpoint = &cy_ipc_pipe_epArray[epAddr]; + + /* Enable the interrupts */ + NVIC_EnableIRQ(endpoint->pipeIntrSrc); + + return (CY_IPC_PIPE_SUCCESS); +} + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h new file mode 100644 index 0000000000..5656d357f0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h @@ -0,0 +1,266 @@ +/***************************************************************************//** +* \file cy_ipc_pipe.h +* \version 1.10 +* +* Description: +* IPC Pipe Driver - This header file contains all the function prototypes, +* structure definitions, pipe constants, and pipe endpoint address definitions. +* +******************************************************************************** +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifndef CY_IPC_PIPE_H +#define CY_IPC_PIPE_H + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ipc/cy_ipc_drv.h" +#include "syslib/cy_syslib.h" +#include "sysint/cy_sysint.h" + +/** +* \addtogroup group_ipc_pipe IPC pipes layer (IPC_PIPE) +* \{ +* The Pipe functions provide a method to transfer one or more words of data +* between CPUs or tasks. The data can be defined as a single 32-bit unsigned +* word, an array of data, or a user-defined structure. The only limitation is +* that the first word in the array or structure must be a 32-bit unsigned word +* in which a client ID number is passed. The client ID dictates the callback +* function that will be called by the receiver of the message. After the +* callback function returns by the receiver, it will invoke a release callback +* function defined by the sender of the message. +* +* A User Pipe is provided for the user to transfer data between CPUs and +* tasks. +* +* \defgroup group_ipc_pipe_macros Macros +* Macro definitions are used in the driver +* +* \defgroup group_ipc_pipe_functions Functions +* Functions are used in the driver +* +* \defgroup group_ipc_pipe_data_structures Data Structures +* Data structures are used in the driver +* +* \defgroup group_ipc_pipe_enums Enumerated Types +* Enumerations are used in the driver +* \} +* +*/ + +/* + * This section defines the system level constants required to define + * callback arrays for the Cypress pipe and the user pipe. These defines + * are used for both the max callback count and maximum clients. +*/ + +/** Typedef for pipe callback function pointer */ +typedef void (* cy_ipc_pipe_callback_ptr_t)(uint32_t * msgPtr); + +/** Typedef for a pipe release callback function pointer */ +typedef void (* cy_ipc_pipe_relcallback_ptr_t)(void); + +/** Typedef for array of callback function pointers */ +typedef cy_ipc_pipe_callback_ptr_t *cy_ipc_pipe_callback_array_ptr_t; + + +/** +* \addtogroup group_ipc_pipe_macros +* \{ +*/ + +/* + * The System pipe address is what is used to send a message to one of the + * endpoints of a pipe. Currently the Cypress pipe and the User pipe + * are supported. For parts with extra IPC channels users may create + * their own custom pipes and create their own pipe addresses. + * + * The format of the endpoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ +#define CY_IPC_PIPE_CFG_IMASK_Pos (16UL) /**< Interrupts shift value for endpoint address */ +#define CY_IPC_PIPE_CFG_IMASK_Msk (0xFFFF0000UL) /**< Interrupts mask for endpoint address */ +#define CY_IPC_PIPE_CFG_INTR_Pos (8UL) /**< IPC Interrupt shift value for endpoint address */ +#define CY_IPC_PIPE_CFG_INTR_Msk (0x0000FF00UL) /**< IPC Interrupt mask for endpoint address */ +#define CY_IPC_PIPE_CFG_CHAN_Pos (0UL) /**< IPC Channel shift value for endpoint address */ +#define CY_IPC_PIPE_CFG_CHAN_Msk (0x000000FFUL) /**< IPC Channel mask for endpoint address */ + + + +#define CY_IPC_PIPE_MSG_CLIENT_Msk (0x000000FFul) /**< Client mask for first word of Pipe message */ +#define CY_IPC_PIPE_MSG_CLIENT_Pos (0ul) /**< Client shift for first word of Pipe message */ +#define CY_IPC_PIPE_MSG_USR_Msk (0x0000FF00ul) /**< User data mask for first word of Pipe message */ +#define CY_IPC_PIPE_MSG_USR_Pos (8ul) /**< User data shift for first word of Pipe message */ +#define CY_IPC_PIPE_MSG_RELEASE_Msk (0xFFFF0000ul) /**< Mask for message release mask */ +#define CY_IPC_PIPE_MSG_RELEASE_Pos (16UL) /**< Shift require to line up mask to LSb */ + +/** Use to set the busy flag when waiting for a release interrupt */ +#define CY_IPC_PIPE_ENDPOINT_BUSY (1UL) +/** Denotes that a release interrupt is not pending */ +#define CY_IPC_PIPE_ENDPOINT_NOTBUSY (0UL) + +/** \} group_ipc_pipe_macros */ + +/** +* \addtogroup group_ipc_pipe_data_structures +* \{ +*/ + +/** +* This is the definition of a pipe endpoint. There is one endpoint structure +* for each CPU in a pipe. It contains all the information to process a message +* send to other CPUs in the pipe. +*/ +typedef struct +{ + uint32_t ipcChan; /**< IPC channel number used for this endpoint to receive messages */ + uint32_t intrChan; /**< IPC interrupt channel number used for this endpoint to receive interrupts */ + uint32_t pipeIntMask; /**< Release/Notify interrupt mask that includes all endpoints on pipe */ + IRQn_Type pipeIntrSrc; /**< Interrupt vector number that includes all endpoints on pipe */ + + IPC_STRUCT_Type *ipcPtr; /**< Pointer to receive IPC channel ( If ipcPtr == NULL, cannot receive ) */ + IPC_INTR_STRUCT_Type *ipcIntrPtr; /**< Pointer to IPC interrupt, needed to clear the interrupt */ + uint32_t busy; /**< Endpoint busy flag. If sent no messages can be sent from this endpoint */ + uint32_t clientCount; /**< Client count and size of MsgCallback array */ + + cy_ipc_pipe_callback_array_ptr_t callbackArray; /**< Pointer to array of callback functions, one for each Client */ + cy_ipc_pipe_relcallback_ptr_t releaseCallbackPtr; /**< Pointer to release callback function */ + cy_ipc_pipe_relcallback_ptr_t defaultReleaseCallbackPtr; /**< Pointer to default release callback function */ +} cy_stc_ipc_pipe_ep_t; + +/** The Pipe endpoint configuration structure. */ +typedef struct +{ + uint32_t ipcNotifierNumber; /**< Notifier */ + uint32_t ipcNotifierPriority; /**< Notifier Priority */ + uint32_t ipcNotifierMuxNumber; /**< CM0+ interrupt multiplexer number */ + + uint32_t epAddress; /**< Index in the array of endpoint structure */ + uint32_t epConfig; /**< Configuration mask, contains IPC channel, IPC interrupt number, + and the interrupt mask */ +} cy_stc_ipc_pipe_ep_config_t; + +/** The Pipe channel configuration structure. */ +typedef struct +{ + /** Specifies the notify interrupt number for the first endpoint */ + cy_stc_ipc_pipe_ep_config_t ep0ConfigData; + + /** Specifies the notify interrupt number for the second endpoint */ + cy_stc_ipc_pipe_ep_config_t ep1ConfigData; + + /** Client count and size of MsgCallback array */ + uint32_t endpointClientsCount; + + /** Pipes callback function array. */ + cy_ipc_pipe_callback_array_ptr_t endpointsCallbacksArray; + + /** User IRQ handler function that is called when IPC receive data to process (interrupt was raised). */ + cy_israddress userPipeIsrHandler; +} cy_stc_ipc_pipe_config_t; + +/** \} goup_ipc_pipe_data_structures */ + +/** +* \addtogroup group_ipc_pipe_macros +* \{ +*/ +/* Status and error types */ +#define CY_IPC_PIPE_RTN (0x0200ul) /**< Software PDL driver ID for IPC pipe functions */ +#define CY_IPC_PIPE_ID_INFO (uint32_t)( CY_IPC_ID_INFO | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function status codes */ +#define CY_IPC_PIPE_ID_WARNING (uint32_t)( CY_IPC_ID_WARNING | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function warning return values */ +#define CY_IPC_PIPE_ID_ERROR (uint32_t)( CY_IPC_ID_ERROR | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function error return values */ + +/** \} group_ipc_pipe_macros */ + +/** +* \addtogroup group_ipc_pipe_enums +* \{ +*/ + +/** Return constants for IPC pipe functions. */ +typedef enum +{ + CY_IPC_PIPE_SUCCESS =(uint32_t)(0x00u), /**< Pipe API return for no error */ + CY_IPC_PIPE_ERROR_NO_IPC =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 1ul), /**< Pipe API return for no valid IPC channel */ + CY_IPC_PIPE_ERROR_NO_INTR =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 2ul), /**< Pipe API return for no valid interrupt */ + CY_IPC_PIPE_ERROR_BAD_PRIORITY =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 3ul), /**< Pipe API return for bad priority parameter */ + CY_IPC_PIPE_ERROR_BAD_HANDLE =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 4ul), /**< Pipe API return for bad pipe handle */ + CY_IPC_PIPE_ERROR_BAD_ID =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 5ul), /**< Pipe API return for bad pipe ID */ + CY_IPC_PIPE_ERROR_DIR_ERROR =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 6ul), /**< Pipe API return for invalid direction (Not used at this time) */ + CY_IPC_PIPE_ERROR_SEND_BUSY =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 7ul), /**< Pipe API return for pipe is currently busy */ + CY_IPC_PIPE_ERROR_NO_MESSAGE =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 8ul), /**< Pipe API return for no message indicated */ + CY_IPC_PIPE_ERROR_BAD_CPU =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 9ul), /**< Pipe API return for invalid CPU value */ + CY_IPC_PIPE_ERROR_BAD_CLIENT =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 10ul) /**< Pipe API return for client out of range */ +} cy_en_ipc_pipe_status_t; + +/** \} group_ipc_pipe_enums */ + +/** +* \addtogroup group_ipc_pipe_data_structures +* \{ +*/ + +/** \cond +* NOTE: This doxygen comment must be placed before some code entity, or else +* it will belong to a random entity that follows it, e.g. group_ipc_functions +* +* Client identifier for a message. +* For a given pipe, traffic across the pipe can be multiplexed with multiple +* senders on one end and multiple receivers on the other end. +* +* The first 32-bit word of the message is used to identify the client that owns +* the message. +* +* The upper 16 bits are the client ID. +* +* The lower 16 bits are for use by the client in any way desired. +* +* The lower 16 bits are preserved (not modified) and not interpreted in any way. +* \endcond +*/ + +/** \} group_ipc_pipe_data_structures */ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +/** +* \addtogroup group_ipc_pipe_functions +* \{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray, + uint32_t cbCnt, uint32_t epConfig, cy_stc_sysint_t const *epInterrupt); +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr, void *msgPtr, + cy_ipc_pipe_relcallback_ptr_t callBackPtr); +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, + cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId); +void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint); +void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr); +void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray); +void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config); + +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr); +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr); + +#ifdef __cplusplus +} +#endif + +/** \} group_ipc_pipe_functions */ + +#endif /* CY_IPC_PIPE_H */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_sema.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_sema.c new file mode 100644 index 0000000000..a7a1e036e3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_sema.c @@ -0,0 +1,369 @@ +/***************************************************************************//** +* \file cy_ipc_sema.c +* \version 1.10 +* +* Description: +* IPC Semaphore Driver - This source file contains the source code for the +* semaphore level APIs for the IPC interface. +* +******************************************************************************** +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ipc/cy_ipc_drv.h" +#include "ipc/cy_ipc_sema.h" +#include "syslib/cy_syslib.h" +#include /* The memset() definition */ + +/* Defines a mask to Check if semaphore count is a multiple of 32 */ +#define CY_IPC_SEMA_PER_WORD_MASK (CY_IPC_SEMA_PER_WORD - 1ul) + +/* Pointer to IPC structure used for semaphores */ +static IPC_STRUCT_Type* cy_semaIpcStruct; + +/* +* Internal IPC semaphore control data structure. +*/ +typedef struct { + uint32_t maxSema; /* Maximum semaphores in system */ + uint32_t *arrayPtr; /* Pointer to semaphores array */ +} cy_stc_ipc_sema_t; + +/******************************************************************************* +* Function Name: Cy_IPC_Sema_Init +****************************************************************************//** +* +* This function initializes the semaphores subsystem. The user must create an +* array of unsigned 32-bit words to hold the semaphore bits. The number +* of semaphores will be the size of the array * 32. The total semaphores count +* will always be a multiple of 32. +* +* \note In a multi-CPU system this init function should be called with all +* initialized parameters on one CPU only to provide a pointer to SRAM that can +* be shared between all the CPUs in the system that will use semaphores. +* On other CPUs user must specify the IPC semaphores channel and pass 0 / NULL +* to count and memPtr parameters correspondingly. +* +* \param ipcChannel +* The IPC channel number used for semaphores +* +* \param count +* The maximum number of semaphores to be supported (multiple of 32). +* +* \param memPtr +* This points to the array of (count/32) words that contain the semaphore data. +* +* \return +* \retval CY_IPC_SEMA_SUCCESS: Successfully initialized +* \retval CY_IPC_SEMA_BAD_PARAM: Memory pointer is NULL and count is not zero, +* or count not multiple of 32 +* \retval CY_IPC_SEMA_ERROR_LOCKED: Could not acquire semaphores IPC channel +* +*******************************************************************************/ +cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel, + uint32_t count, uint32_t memPtr[]) +{ + /* Structure containing semaphores control data */ + static cy_stc_ipc_sema_t cy_semaData; + + cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_BAD_PARAM; + + if (ipcChannel >= CY_IPC_CHANNELS) + { + retStatus = CY_IPC_SEMA_BAD_PARAM; + } + else + { + if( (NULL == memPtr) && (0u == count)) + { + cy_semaIpcStruct = Cy_IPC_Drv_GetIpcBaseAddress(ipcChannel); + + retStatus = CY_IPC_SEMA_SUCCESS; + } + + /* Check for non Null pointers and count value */ + else if ((NULL != memPtr) && (0u != count)) + { + /* Check if semaphore count is a multiple of 32 */ + if( 0ul == (count & CY_IPC_SEMA_PER_WORD_MASK)) + { + cy_semaIpcStruct = Cy_IPC_Drv_GetIpcBaseAddress(ipcChannel); + + cy_semaData.maxSema = count; + cy_semaData.arrayPtr = memPtr; + + /* Initialize all semaphores to released */ + (void)memset(cy_semaData.arrayPtr, 0, (count /8u)); + + /* Make sure semaphores start out released. */ + /* Ignore the return value since it is OK if it was already released. */ + (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION); + + /* Set the IPC Data with the pointer to the array. */ + if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_SendMsgPtr (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION, &cy_semaData)) + { + if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION)) + { + retStatus = CY_IPC_SEMA_SUCCESS; + } + else + { + /* IPC channel not released, still semaphored */ + retStatus = CY_IPC_SEMA_ERROR_LOCKED; + } + } + else + { + /* Could not acquire semaphore channel */ + retStatus = CY_IPC_SEMA_ERROR_LOCKED; + } + } + else + { + retStatus = CY_IPC_SEMA_BAD_PARAM; + } + } + else + { + retStatus = CY_IPC_SEMA_BAD_PARAM; + } + } + + return(retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Sema_Set +****************************************************************************//** +* +* This function tries to acquire a semaphore. If the +* semaphore is not available, this function returns immediately with +* CY_IPC_SEMA_LOCKED. +* +* It first acquires the IPC channel that is used for all the semaphores, sets +* the semaphore if it is cleared, then releases the IPC channel used for the semaphore. +* +* \param semaNumber +* The semaphore number to acquire. +* +* \param preemptable +* When this parameter is enabled the function can be preempted by another +* task or other forms of context switching in an RTOS environment. +* +* \return +* \retval CY_IPC_SEMA_SUCCESS: The semaphore was set successfully +* \retval CY_IPC_SEMA_LOCKED: The semaphore channel is busy or locked +* by another process +* \retval CY_IPC_SEMA_NOT_ACQUIRED: Semaphore was already set +* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid +* +* +*******************************************************************************/ +cy_en_ipcsema_status_t Cy_IPC_Sema_Set(uint32_t semaNumber, bool preemptable) +{ + uint32_t semaIndex; + uint32_t semaMask; + uint32_t interruptState = 0ul; + + cy_stc_ipc_sema_t *semaStruct; + cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_LOCKED; + + /* Get pointer to structure */ + semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct); + + if (semaNumber < semaStruct->maxSema) + { + semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD; + semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) )); + + if (!preemptable) + { + interruptState = Cy_SysLib_EnterCriticalSection(); + } + + /* Check to make sure the IPC channel is released + If so, check if specific channel can be locked. */ + if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire (cy_semaIpcStruct)) + { + if((semaStruct->arrayPtr[semaIndex] & semaMask) == 0ul) + { + semaStruct->arrayPtr[semaIndex] |= semaMask; + retStatus = CY_IPC_SEMA_SUCCESS; + } + else + { + retStatus = CY_IPC_SEMA_NOT_ACQUIRED; + } + + /* Release, but do not trigger a release event */ + (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION); + } + + if (!preemptable) + { + Cy_SysLib_ExitCriticalSection(interruptState); + } + } + else + { + retStatus = CY_IPC_SEMA_OUT_OF_RANGE; + } + + return(retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Sema_Clear +****************************************************************************//** +* +* This functions tries to releases a semaphore. +* +* It first acquires the IPC channel that is used for all the semaphores, clears +* the semaphore if it is set, then releases the IPC channel used for the semaphores. +* +* \param semaNumber +* The index of the semaphore to release. +* +* \param preemptable +* When this parameter is enabled the function can be preempted by another +* task or other forms of context switching in an RTOS environment. +* +* \return +* \retval CY_IPC_SEMA_SUCCESS: The semaphore was cleared successfully +* \retval CY_IPC_SEMA_NOT_ACQUIRED: The semaphore was already cleared +* \retval CY_IPC_SEMA_LOCKED: The semaphore channel was semaphored or busy +* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid +* +* +*******************************************************************************/ +cy_en_ipcsema_status_t Cy_IPC_Sema_Clear(uint32_t semaNumber, bool preemptable) +{ + uint32_t semaIndex; + uint32_t semaMask; + uint32_t interruptState = 0ul; + + cy_stc_ipc_sema_t *semaStruct; + cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_LOCKED; + + /* Get pointer to structure */ + semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct); + + if (semaNumber < semaStruct->maxSema) + { + semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD; + semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) )); + + if (!preemptable) + { + interruptState = Cy_SysLib_EnterCriticalSection(); + } + + /* Check to make sure the IPC channel is released + If so, check if specific channel can be locked. */ + if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire (cy_semaIpcStruct)) + { + if((semaStruct->arrayPtr[semaIndex] & semaMask) != 0ul) + { + semaStruct->arrayPtr[semaIndex] &= ~semaMask; + retStatus = CY_IPC_SEMA_SUCCESS; + } + else + { + retStatus = CY_IPC_SEMA_NOT_ACQUIRED; + } + + /* Release, but do not trigger a release event */ + (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION); + } + + if (!preemptable) + { + Cy_SysLib_ExitCriticalSection(interruptState); + } + } + else + { + retStatus = CY_IPC_SEMA_OUT_OF_RANGE; + } + return(retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Sema_Status +****************************************************************************//** +* +* This function returns the status of the semaphore. +* +* \param semaNumber +* The index of the semaphore to return status. +* +* \return +* \retval CY_IPC_SEMA_STATUS_LOCKED: The semaphore is in the set state. +* \retval CY_IPC_SEMA_STATUS_UNLOCKED: The semaphore is in the cleared state. +* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid +* +* +*******************************************************************************/ +#if defined (__ICCARM__) + __ramfunc +#else + CY_SECTION(".cy_ramfunc") +#endif +cy_en_ipcsema_status_t Cy_IPC_Sema_Status(uint32_t semaNumber) +{ + cy_en_ipcsema_status_t retStatus; + uint32_t semaIndex; + uint32_t semaMask; + cy_stc_ipc_sema_t *semaStruct; + + /* Get pointer to structure */ + semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct); + + if (semaNumber < semaStruct->maxSema) + { + /* Get the index into the semaphore array and calculate the mask */ + semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD; + semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) )); + + if((semaStruct->arrayPtr[semaIndex] & semaMask) != 0ul) + { + retStatus = CY_IPC_SEMA_STATUS_LOCKED; + } + else + { + retStatus = CY_IPC_SEMA_STATUS_UNLOCKED; + } + } + else + { + retStatus = CY_IPC_SEMA_OUT_OF_RANGE; + } + return(retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Sema_GetMaxSems +****************************************************************************//** +* +* This function returns the number of semaphores in the semaphores subsystem. +* +* \return +* Returns the semaphores quantity. +* +*******************************************************************************/ +uint32_t Cy_IPC_Sema_GetMaxSems(void) +{ + cy_stc_ipc_sema_t *semaStruct; + + /* Get pointer to structure */ + semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct); + + return (semaStruct->maxSema); +} + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_sema.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_sema.h new file mode 100644 index 0000000000..f2a202d1d2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/ipc/cy_ipc_sema.h @@ -0,0 +1,116 @@ +/***************************************************************************//** +* \file cy_ipc_sema.h +* \version 1.10 +* +* \brief +* Header file for IPC SEM functions +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef CY_IPC_SEMA_H +#define CY_IPC_SEMA_H + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "cy_ipc_drv.h" +#include + +/** +* \addtogroup group_ipc_sema IPC semaphores layer (IPC_SEMA) +* \{ +* The semaphores layer functions made use of a single IPC channel to allow +* multiple semaphores that can be used by system or user function calls. +* By default there are 128 semaphores provided, although the user may modify +* the default value to any number, limited only by SRAM. +* +* \defgroup group_ipc_sema_macros Macros +* Macro definitions are used in the driver +* +* \defgroup group_ipc_sema_functions Functions +* Functions are used in the driver +* +* \defgroup group_ipc_sema_enums Enumerated Types +* Enumerations are used in the driver +* \} +* +* \addtogroup group_ipc_sema_macros +* \{ +*/ + +/** Software PDL driver ID for IPC semaphore functions */ +#define CY_IPC_SEMA_RTN (0x0100ul) +/** Return prefix for IPC semaphore function status codes */ +#define CY_IPC_SEMA_ID_INFO (uint32_t)( CY_IPC_ID_INFO | CY_IPC_SEMA_RTN) +/** Return prefix for IPC semaphore function warning return values */ +#define CY_IPC_SEMA_ID_WARNING (uint32_t)( CY_IPC_ID_WARNING | CY_IPC_SEMA_RTN) +/** Return prefix for IPC semaphore function error return values */ +#define CY_IPC_SEMA_ID_ERROR (uint32_t)( CY_IPC_ID_ERROR | CY_IPC_SEMA_RTN) + +#define CY_IPC_SEMA_PER_WORD (uint32_t)32u /**< 32 semaphores per word */ + +/** \} group_ipc_sema_macros */ + +/** +* \addtogroup group_ipc_sema_enums +* \{ +*/ + +/** Return constants for IPC semaphores functions. */ +typedef enum +{ + /** No error has occurred */ + CY_IPC_SEMA_SUCCESS = (uint32_t)(0ul), + /** Semaphores IPC channel has already been locked */ + CY_IPC_SEMA_ERROR_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 1ul), + /** Semaphores IPC channel is unlocked */ + CY_IPC_SEMA_ERROR_UNLOCKED = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 2ul), + /** Semaphore API bad parameter */ + CY_IPC_SEMA_BAD_PARAM = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 3ul), + /** Semaphore API return when semaphore number is out of the range */ + CY_IPC_SEMA_OUT_OF_RANGE = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 4ul), + + /** Semaphore API return when IPC channel was not acquired */ + CY_IPC_SEMA_NOT_ACQUIRED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 2ul), + /** Semaphore API return status when semaphore channel is busy or locked +* by another process */ + CY_IPC_SEMA_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 3ul), + /** Semaphore status return that the semaphore is set */ + CY_IPC_SEMA_STATUS_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 1ul), + /** Semaphore status return that the semaphore is cleared */ + CY_IPC_SEMA_STATUS_UNLOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 0ul) +} cy_en_ipcsema_status_t; + +/** \} group_ipc_sema_enums */ + +/** +* \addtogroup group_ipc_sema_functions +* \{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +cy_en_ipcsema_status_t Cy_IPC_Sema_Init (uint32_t ipcChannel, uint32_t count, uint32_t memPtr[]); +cy_en_ipcsema_status_t Cy_IPC_Sema_Set (uint32_t semaNumber, bool preemptable); +cy_en_ipcsema_status_t Cy_IPC_Sema_Clear (uint32_t semaNumber, bool preemptable); +cy_en_ipcsema_status_t Cy_IPC_Sema_Status (uint32_t semaNumber); +uint32_t Cy_IPC_Sema_GetMaxSems(void); + +#ifdef __cplusplus +} +#endif + +/** \} group_ipc_sema_functions */ + +#endif /* CY_IPC_SEMA_H */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c new file mode 100644 index 0000000000..655f83c97d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c @@ -0,0 +1,545 @@ +/******************************************************************************* +* \file cy_lpcomp.c +* \version 1.10 +* +* \brief +* This file provides the driver code to the API for the Low Power Comparator +* component. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#include "cy_lpcomp.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_LPComp_Init +****************************************************************************//** +* +* Initializes LPCOMP and returns the LPCOMP register address. +* +* \param *base +* LPCOMP registers structure pointer. +* +* \param *config +* The pointer to the configuration structure for PDL. +* +* \param channel +* The LPCOMP channel index. +* +* \return cy_en_lpcomp_status_t +* *base checking result. If the pointer is NULL, returns error. +* +*******************************************************************************/ +cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, const cy_stc_lpcomp_config_t* config) +{ + cy_en_lpcomp_status_t ret = CY_LPCOMP_BAD_PARAM; + + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(config->outputMode)); + CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(config->hysteresis)); + + if ((base != NULL) && (config != NULL)) + { + Cy_LPComp_GlobalEnable(base); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_CTRL = _VAL2FLD(LPCOMP_CMP0_CTRL_HYST0, (uint32_t)config->hysteresis) | + _VAL2FLD(LPCOMP_CMP0_CTRL_DSI_BYPASS0, (uint32_t)config->outputMode) | + _VAL2FLD(LPCOMP_CMP0_CTRL_DSI_LEVEL0, (uint32_t)config->outputMode >> 1u); + } + else + { + base->CMP1_CTRL = _VAL2FLD(LPCOMP_CMP1_CTRL_HYST1, (uint32_t)config->hysteresis) | + _VAL2FLD(LPCOMP_CMP1_CTRL_DSI_BYPASS1, (uint32_t)config->outputMode) | + _VAL2FLD(LPCOMP_CMP1_CTRL_DSI_LEVEL1, (uint32_t)config->outputMode >> 1u); + } + + ret = CY_LPCOMP_SUCCESS; + } + + return (ret); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetInterruptTriggerMode +****************************************************************************//** +* +* Sets the interrupt edge-detect mode. +* This also controls the value provided on the output. +* Note: Interrupts can be enabled after the block is enabled and the appropriate +* start-up time has elapsed: +* 3 us for the normal power mode; +* 6 us for the LP mode; +* 50 us for the ULP mode. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \param intType +* Interrupt edge trigger selection +* CY_LPCOMP_INTR_DISABLE (=0) - Disabled, no interrupt will be detected +* CY_LPCOMP_INTR_RISING (=1) - Rising edge +* CY_LPCOMP_INTR_FALLING (=2) - Falling edge +* CY_LPCOMP_INTR_BOTH (=3) - Both rising and falling edges. +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_int_t intType) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_INTR_MODE_VALID(intType)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, LPCOMP_CMP0_CTRL_INTTYPE0, (uint32_t)intType); + } + else + { + base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, LPCOMP_CMP1_CTRL_INTTYPE1, (uint32_t)intType); + } +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetPower +****************************************************************************//** +* +* Sets the drive power and speeds to one of the four settings. +* Note: The comparator interrupt should be enabled after enabling of the +* comparator itself. Otherwise, unexpected interrupts events can occur. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \param power +* The power setting sets an operation mode of the component: +* CY_LPCOMP_OFF_POWER (=0) - Off power +* CY_LPCOMP_MODE_ULP (=1) - Slow/ultra low power +* CY_LPCOMP_MODE_LP (=2) - Medium/low power +* CY_LPCOMP_MODE_NORMAL(=3) - Fast/normal power +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_SetPower(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_pwr_t power) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_POWER_VALID(power)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, LPCOMP_CMP0_CTRL_MODE0, (uint32_t)power); + } + else + { + base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, LPCOMP_CMP1_CTRL_MODE1, (uint32_t)power); + } +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetHysteresis +****************************************************************************//** +* +* Adds the 30mV hysteresis to the comparator. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \param hysteresis +* Sets an operation mode of the component +* CY_LPCOMP_HYST_ENABLE (=1) - Enables HYST +* CY_LPCOMP_HYST_DISABLE(=0) - Disable HYST. +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_hyst_t hysteresis) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(hysteresis)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, LPCOMP_CMP0_CTRL_HYST0, (uint32_t)hysteresis); + } + else + { + base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL , LPCOMP_CMP1_CTRL_HYST1, (uint32_t)hysteresis); + } +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetInputs +****************************************************************************//** +* +* Sets the comparator input sources. The comparator inputs can be connected +* to the dedicated GPIO pins or AMUXBUSA/AMUXBUSB. Additionally, the negative +* comparator input can be connected to the local VREF. +* At least one unconnected input causes a comparator undefined output. +* +* Note: Connection to AMUXBUSA/AMUXBUSB requires closing the additional +* switches which are a part of the IO system. These switches can be configured +* using the HSIOM->AMUX_SPLIT_CTL[3] register. +* Refer to the appropriate Technical Reference Manual (TRM) of a device +* for a detailed description. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \param inputP +* Positive input selection +* CY_LPCOMP_SW_GPIO (0x01u) +* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode +* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in the hibernate mode. +* +* \param inputN +* Negative input selection +* CY_LPCOMP_SW_GPIO (0x01u) +* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode +* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in hibernate mode +* CY_LPCOMP_SW_LOCAL_VREF (0x08u) - the negative input only for a crude REF. +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_SetInputs(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_inputs_t inputP, cy_en_lpcomp_inputs_t inputN) +{ + uint32_t input; + + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_INPUT_P_VALID(inputP)); + CY_ASSERT_L3(CY_LPCOMP_IS_INPUT_N_VALID(inputN)); + + switch(inputP) + { + case CY_LPCOMP_SW_AMUXBUSA: + { + input = (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_AP0_Msk : LPCOMP_CMP1_SW_CMP1_AP1_Msk; + HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR, 3u); + break; + } + case CY_LPCOMP_SW_AMUXBUSB: + { + input = (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_BP0_Msk : LPCOMP_CMP1_SW_CMP1_BP1_Msk; + HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR, 3u); + break; + } + default: + { + input = (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_IP0_Msk : LPCOMP_CMP1_SW_CMP1_IP1_Msk; + break; + } + } + + switch(inputN) + { + case CY_LPCOMP_SW_AMUXBUSA: + { + input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_AN0_Msk : LPCOMP_CMP1_SW_CMP1_AN1_Msk; + HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR, 3u); + break; + } + case CY_LPCOMP_SW_AMUXBUSB: + { + input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_BN0_Msk : LPCOMP_CMP1_SW_CMP1_BN1_Msk; + HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR, 3u); + break; + } + case CY_LPCOMP_SW_LOCAL_VREF: + { + input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_VN0_Msk : LPCOMP_CMP1_SW_CMP1_VN1_Msk; + break; + } + default: + { + input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_IN0_Msk : LPCOMP_CMP1_SW_CMP1_IN1_Msk; + break; + } + } + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_SW_CLEAR = CY_LPCOMP_CMP0_SW_POS_Msk | CY_LPCOMP_CMP0_SW_NEG_Msk; + base->CMP0_SW = input; + } + else + { + base->CMP1_SW_CLEAR = CY_LPCOMP_CMP1_SW_POS_Msk | CY_LPCOMP_CMP1_SW_NEG_Msk; + base->CMP1_SW = input; + } +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetOutputMode +****************************************************************************//** +* +* Sets the type of the comparator DSI output. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \param outType +* Interrupt edge trigger selection +* CY_LPCOMP_OUT_PULSE (=0) - the DSI output with the pulse option, no bypass +* CY_LPCOMP_OUT_DIRECT (=1) - the bypass mode, the direct output of the comparator +* CY_LPCOMP_OUT_SYNC (=2) - DSI output with the level option, it is similar to the +* bypass mode but it is 1 cycle slow than the bypass. +* [DSI_LEVELx : DSI_BYPASSx] = [Bit11 : Bit10] +* 0 : 0 = 0x00 -> Pulse (PULSE) +* 1 : 0 = 0x02 -> Level (SYNC) +* x : 1 = 0x01 -> Bypass (Direct). +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_SetOutputMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_out_t outType) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(outType)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, CY_LPCOMP_CMP0_OUTPUT_CONFIG, (uint32_t)outType); + } + else + { + base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, CY_LPCOMP_CMP1_OUTPUT_CONFIG, (uint32_t)outType); + } +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_DeepSleepCallback +****************************************************************************//** +* +* This function checks the current power mode of LPComp and then disables the +* LPComp block if there is no wake-up source from LPComp in the deep-sleep mode. +* It stores the state of the LPComp enable and then disables the LPComp block +* before going to the low power modes, and recovers the LPComp power state after +* wake-up using the stored value. +* The function attribution has a weak linkage, so the user can override this +* function for a custom lower-power callback. +* +* \param *callbackParams +* The \ref cy_stc_syspm_callback_params_t structure with the callback +* parameters which consists of mode, base and context fields: +* *base - LPComp register structure pointer; +* *context - Context for the call-back function; +* mode +* CY_SYSPM_CHECK_READY - No action for this state. +* CY_SYSPM_CHECK_FAIL - No action for this state. +* CY_SYSPM_BEFORE_TRANSITION - Checks the LPComp interrupt mask and the power +* mode, and then disables or enables the LPComp block +* according to the condition. +* Stores the LPComp state to recover the state after +* wake up. +* CY_SYSPM_AFTER_TRANSITION - Enables the LPComp block, if it was disabled +* before the sleep mode. +* +* \return +* \ref cy_en_syspm_status_t +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams) +{ + cy_en_syspm_status_t ret = CY_SYSPM_FAIL; + LPCOMP_Type *locBase = (LPCOMP_Type *) (callbackParams->base); + static uint32_t enabled_status; + + switch(callbackParams->mode) + { + case CY_SYSPM_CHECK_READY: + { + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_CHECK_FAIL: + { + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_BEFORE_TRANSITION: + { + /* Save the LPComp the enabled/disabled status. */ + enabled_status = _FLD2VAL(LPCOMP_CONFIG_ENABLED, locBase->CONFIG); + + if (0u != enabled_status) + { + /* Disable the LPComp block when there is no wake-up source from any channel. */ + if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, locBase->CMP0_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) && + _FLD2BOOL(LPCOMP_INTR_MASK_COMP0_MASK, locBase->INTR_MASK)) || + ((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, locBase->CMP1_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) && + _FLD2BOOL(LPCOMP_INTR_MASK_COMP1_MASK, locBase->INTR_MASK))) ) + + { + /* Disable the LPComp block to avoid leakage. */ + Cy_LPComp_GlobalDisable(locBase); + } + else + { + /* Set LPComp the status to the not changed state. */ + enabled_status = 0u; + } + } + else + { + /* The LPComp block was already disabled and + * the system is allowed to go to the low power mode. + */ + } + + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_AFTER_TRANSITION: + { + /* Enable LPComp to operate if it was enabled + * before entering to the low power mode. + */ + if (0u != enabled_status) + { + Cy_LPComp_GlobalEnable(locBase); + } + else + { + /* The LPComp block was disabled before calling this API + * with mode = CY_SYSPM_CHECK_READY. + */ + } + + ret = CY_SYSPM_SUCCESS; + } + break; + + default: + break; + } + + return (ret); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_HibernateCallback +****************************************************************************//** +* +* This function checks the current power mode of LPComp and then disable the +* LPComp block, if there is no wake-up source from LPComp in the hibernate mode. +* The function attribution has a weak linkage, so the user can override this +* function for a custom lower-power callback. +* +* \param *callbackParams +* The \ref cy_stc_syspm_callback_params_t structure with the callback +* parameters which consists of mode, base and context fields: +* *base - LPComp register structure pointer; +* *context - Context for the call-back function; +* mode +* CY_SYSPM_CHECK_READY - No action for this state. +* CY_SYSPM_CHECK_FAIL - No action for this state. +* CY_SYSPM_BEFORE_TRANSITION - Checks the wake-up source from the hibernate mode +* of the LPComp block, and then disables or enables +* the LPComp block according to the condition. +* +* \return +* \ref cy_en_syspm_status_t +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams) +{ + cy_en_syspm_status_t ret = CY_SYSPM_FAIL; + LPCOMP_Type *locBase = (LPCOMP_Type *) (callbackParams->base); + static uint32_t enabled_status; + + switch(callbackParams->mode) + { + case CY_SYSPM_CHECK_READY: + { + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_CHECK_FAIL: + { + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_BEFORE_TRANSITION: + { + /* Save the LPComp the enabled/disabled status. */ + enabled_status = _FLD2VAL(LPCOMP_CONFIG_ENABLED, locBase->CONFIG); + + if (0u != enabled_status) + { + /* Disable the LPComp block when there is no wake-up source from any channel. */ + if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, locBase->CMP0_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) && + _FLD2BOOL(CY_LPCOMP_WAKEUP_PIN0, SRSS->PWR_HIBERNATE)) || + ((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, locBase->CMP1_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) && + _FLD2BOOL(CY_LPCOMP_WAKEUP_PIN1, SRSS->PWR_HIBERNATE))) ) + + { + /* Disable the LPComp block to avoid leakage. */ + Cy_LPComp_GlobalDisable(locBase); + } + else + { + /* Set LPComp the status to the not changed state. */ + enabled_status = 0u; + } + } + else + { + /* The LPComp block was already disabled and + * the system is allowed to go to the low power mode. + */ + } + + ret = CY_SYSPM_SUCCESS; + } + break; + + default: + break; + } + + return (ret); +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h new file mode 100644 index 0000000000..4d781123aa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h @@ -0,0 +1,687 @@ +/***************************************************************************//** +* \file cy_lpcomp.h +* \version 1.10 +* +* This file provides constants and parameter values for the Low Power Comparator driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \defgroup group_lpcomp Low Power Comparator (LPComp) +* \{ +* Provides access to the low-power comparators implemented using the fixed-function +* LP comparator block that is present in PSoC 6. +* +* These comparators can perform fast analog signal comparison of internal +* and external analog signals in all system power modes. Low-power comparator +* output can be inspected by the CPU, used as an interrupt/wakeup source to the +* CPU when in low-power mode (Sleep, Low-Power Sleep, or Deep-Sleep), used as +* a wakeup source to system resources when in Hibernate mode, or fed to DSI as +* an asynchronous or synchronous signal (level or pulse). +* +* \section group_lpcomp_section_Configuration_Considerations Configuration Considerations +* To set up an LPComp, the inputs, the output, the mode, the interrupts and +* other configuration parameters should be configured. Power the LPComp to operate. +* +* The sequence recommended for the LPComp operation: +* +* 1) To initialize the driver, call the Cy_LPComp_Init() function providing +* the filled cy_stc_lpcomp_config_t structure, the LPComp channel number, +* and the LPCOMP registers structure pointer. +* +* 2) Optionally, configure the interrupt requests if the interrupt event +* triggering is needed. Use the Cy_LPComp_SetInterruptMask() function with +* the parameter for the mask available in the configuration file. +* Additionally, enable the Global interrupts and initialize the referenced +* interrupt by setting the priority and the interrupt vector using +* the \ref Cy_SysInt_Init() function of the sysint driver. +* +* 3) Configure the inputs and the output using the \ref Cy_GPIO_Pin_Init() +* functions of the GPIO driver. +* The High Impedance Analog drive mode is for the inputs and +* the Strong drive mode is for the output. +* Use the Cy_LPComp_SetInputs() function to connect the comparator inputs +* to the dedicated IO pins, AMUXBUSA/AMUXBUSB or Vref: +* \image html lpcomp_inputs.png +* +* 4) Power on the comparator using the Cy_LPComp_SetPower() function. +* +* 5) Optionally, enable the comparator interrupt using +* Cy_LPComp_SetInterruptTriggerMode() with the corresponding parameter +* for the interrupt mode (Rising edge, Falling edge, or Both edges). +* +* 6) The comparator output can be monitored using +* the Cy_LPComp_GetCompare() function or using the LPComp interrupt +* (if the interrupt is enabled). +* +* NOTE 1: To prevent false triggering, a delay before enabling +* the comparator interrupt is required. The recommended delay is +* 10 us for the Normal power mode and 50 us for the Ultra low-power mode. +* +* NOTE 2: The interrupt is not cleared automatically. +* It is the user's responsibility to do that. +* The interrupt is cleared by writing a 1 in the corresponding interrupt +* register bit position. The preferred way to clear interrupt sources +* is using the Cy_LPComp_ClearInterrupt() function. +* +* NOTE 3: Individual comparator interrupt outputs are ORed together +* as a single asynchronous interrupt source before it is sent out and +* used to wake up the system in the low-power mode. +* For PSoC 6 devices, the individual comparator interrupt is masked +* by the INTR_MASK register. The masked result is captured in +* the INTR_MASKED register. +* Writing a 1 to the INTR register bit will clear the interrupt. +* +* \section group_lpcomp_more_information More Information +* +* Refer to the appropriate device technical reference manual (TRM) for +* a detailed description of the registers. +* +* \section group_lpcomp_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
    11.4AA cast should not be performed between a pointer to object type and +* a different pointer to object type. +* The pointer to the buffer memory is void to allow handling different +* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). +* The cast operation is safe because the configuration is verified +* before operation is performed. +* The function \ref Cy_LPComp_DeepSleepCallback is a callback of +* the \ref cy_en_syspm_status_t type. The cast operation safety in this +* function becomes the user's responsibility because the pointers are +* initialized when a callback is registered in the SysPm driver.
    +* +* \section group_lpcomp_Changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +*
    VersionChangesReason for Change
    1.0Initial version
    1.10The CY_WEAK keyword is removed from Cy_LPComp_DeepSleepCallback() +* and Cy_LPComp_HibernateCallback() functions
    +* Added input parameter validation to the API functions.
    +* +* \defgroup group_lpcomp_macros Macros +* \defgroup group_lpcomp_functions Functions +* \defgroup group_lpcomp_data_structures Data structures +* \defgroup group_lpcomp_enums Enumerated Types +*/ + +#ifndef CY_LPCOMP_PDL_H +#define CY_LPCOMP_PDL_H + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include +#include +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" +#include "syspm/cy_syspm.h" + +#ifndef CY_IP_MXLPCOMP + #error "The LPCOMP driver is not supported on this device" +#endif + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \addtogroup group_lpcomp_macros +* \{ +*/ + +/** Driver major version */ +#define CY_LPCOMP_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_LPCOMP_DRV_VERSION_MINOR 10 + +/****************************************************************************** +* API Constants +******************************************************************************/ + +/**< LPCOMP PDL ID */ +#define CY_LPCOMP_ID CY_PDL_DRV_ID(0x23u) + +/** The LPCOMP's number of channels. */ +#define CY_LPCOMP_MAX_CHANNEL_NUM (2u) + +/** LPCOMP's comparator 1 interrupt mask. */ +#define CY_LPCOMP_COMP0 (0x01u) +/** LPCOMP's comparator 2 interrupt mask. */ +#define CY_LPCOMP_COMP1 (0x02u) + +/** \cond INTERNAL_MACROS */ + + +/****************************************************************************** +* Registers Constants +******************************************************************************/ + +#define CY_LPCOMP_MODE_ULP_Pos (0x0uL) +#define CY_LPCOMP_MODE_ULP_Msk (0x1uL) + +#define CY_LPCOMP_INTR_Pos (LPCOMP_INTR_COMP0_Pos) +#define CY_LPCOMP_INTR_Msk (LPCOMP_INTR_COMP0_Msk | LPCOMP_INTR_COMP1_Msk) + +#define CY_LPCOMP_CMP0_SW_POS_Msk (LPCOMP_CMP0_SW_CMP0_IP0_Msk | \ + LPCOMP_CMP0_SW_CMP0_AP0_Msk | \ + LPCOMP_CMP0_SW_CMP0_BP0_Msk) +#define CY_LPCOMP_CMP0_SW_NEG_Msk (LPCOMP_CMP0_SW_CMP0_IN0_Msk | \ + LPCOMP_CMP0_SW_CMP0_AN0_Msk | \ + LPCOMP_CMP0_SW_CMP0_BN0_Msk | \ + LPCOMP_CMP0_SW_CMP0_VN0_Msk) +#define CY_LPCOMP_CMP1_SW_POS_Msk (LPCOMP_CMP1_SW_CMP1_IP1_Msk | \ + LPCOMP_CMP1_SW_CMP1_AP1_Msk | \ + LPCOMP_CMP1_SW_CMP1_BP1_Msk) +#define CY_LPCOMP_CMP1_SW_NEG_Msk (LPCOMP_CMP1_SW_CMP1_IN1_Msk | \ + LPCOMP_CMP1_SW_CMP1_AN1_Msk | \ + LPCOMP_CMP1_SW_CMP1_BN1_Msk | \ + LPCOMP_CMP1_SW_CMP1_VN1_Msk) + +#define CY_LPCOMP_CMP0_OUTPUT_CONFIG_Pos LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos +#define CY_LPCOMP_CMP1_OUTPUT_CONFIG_Pos LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos + +#define CY_LPCOMP_CMP0_OUTPUT_CONFIG_Msk (LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk | \ + LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk) + +#define CY_LPCOMP_CMP1_OUTPUT_CONFIG_Msk (LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk | \ + LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk) + +#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR_Pos HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos + +#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR_Msk (HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | \ + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk) + +#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR_Pos HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos + +#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR_Msk (HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | \ + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk) + +#define CY_LPCOMP_REF_CONNECTED (1u) + +#define CY_LPCOMP_WAKEUP_PIN0_Msk CY_SYSPM_WAKEUP_LPCOMP0 +#define CY_LPCOMP_WAKEUP_PIN1_Msk CY_SYSPM_WAKEUP_LPCOMP1 + +/** \endcond */ +/** \} group_lpcomp_macros */ + +/** +* \addtogroup group_lpcomp_enums +* \{ +*/ + +/****************************************************************************** + * Enumerations + *****************************************************************************/ +/** The LPCOMP output modes. */ +typedef enum +{ + CY_LPCOMP_OUT_PULSE = 0u, /**< The LPCOMP DSI output with the pulse option, no bypass. */ + CY_LPCOMP_OUT_DIRECT = 1u, /**< The LPCOMP bypass mode, the direct output of a comparator. */ + CY_LPCOMP_OUT_SYNC = 2u /**< The LPCOMP DSI output with the level option, it is similar + to the bypass mode but it is 1 cycle slow than the bypass. */ +} cy_en_lpcomp_out_t; + +/** The LPCOMP hysteresis modes. */ +typedef enum +{ + CY_LPCOMP_HYST_ENABLE = 1u, /**< The LPCOMP enable hysteresis. */ + CY_LPCOMP_HYST_DISABLE = 0u /**< The LPCOMP disable hysteresis. */ +} cy_en_lpcomp_hyst_t; + +/** The LPCOMP's channel number. */ +typedef enum +{ + CY_LPCOMP_CHANNEL_0 = 0x1u, /**< The LPCOMP Comparator 0. */ + CY_LPCOMP_CHANNEL_1 = 0x2u /**< The LPCOMP Comparator 1. */ +} cy_en_lpcomp_channel_t; + +/** The LPCOMP interrupt modes. */ +typedef enum +{ + CY_LPCOMP_INTR_DISABLE = 0u, /**< The LPCOMP interrupt disabled, no interrupt will be detected. */ + CY_LPCOMP_INTR_RISING = 1u, /**< The LPCOMP interrupt on the rising edge. */ + CY_LPCOMP_INTR_FALLING = 2u, /**< The LPCOMP interrupt on the falling edge. */ + CY_LPCOMP_INTR_BOTH = 3u /**< The LPCOMP interrupt on both rising and falling edges. */ +} cy_en_lpcomp_int_t; + +/** The LPCOMP power-mode selection. */ +typedef enum +{ + CY_LPCOMP_MODE_OFF = 0u, /**< The LPCOMP's channel power-off. */ + CY_LPCOMP_MODE_ULP = 1u, /**< The LPCOMP's channel ULP mode. */ + CY_LPCOMP_MODE_LP = 2u, /**< The LPCOMP's channel LP mode. */ + CY_LPCOMP_MODE_NORMAL = 3u /**< The LPCOMP's channel normal mode. */ +} cy_en_lpcomp_pwr_t; + +/** The LPCOMP inputs. */ +typedef enum +{ + CY_LPCOMP_SW_GPIO = 0x01u, /**< The LPCOMP input connects to GPIO pin. */ + CY_LPCOMP_SW_AMUXBUSA = 0x02u, /**< The LPCOMP input connects to AMUXBUSA. */ + CY_LPCOMP_SW_AMUXBUSB = 0x04u, /**< The LPCOMP input connects to AMUXBUSB. */ + CY_LPCOMP_SW_LOCAL_VREF = 0x08u /**< The LPCOMP input connects to local VREF. */ +} cy_en_lpcomp_inputs_t; + +/** The LPCOMP error codes. */ +typedef enum +{ + CY_LPCOMP_SUCCESS = 0x00u, /**< Successful */ + CY_LPCOMP_BAD_PARAM = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */ + CY_LPCOMP_TIMEOUT = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x02u, /**< Operation timed out */ + CY_LPCOMP_INVALID_STATE = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x03u, /**< Operation not setup or is in an improper state */ + CY_LPCOMP_UNKNOWN = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0xFFu, /**< Unknown failure */ +} cy_en_lpcomp_status_t; + +/** \} group_lpcomp_enums */ + +/** +* \addtogroup group_lpcomp_data_structures +* \{ +*/ + +/****************************************************************************** + * Structures + *****************************************************************************/ + +/** The LPCOMP configuration structure. */ +typedef struct { + cy_en_lpcomp_out_t outputMode; /**< The LPCOMP's outputMode: Direct output, + Synchronized output or Pulse output */ + cy_en_lpcomp_hyst_t hysteresis; /**< Enables or disables the LPCOMP's hysteresis */ +} cy_stc_lpcomp_config_t; + +/** \} group_lpcomp_data_structures */ + +/** \cond INTERNAL_MACROS */ + +/****************************************************************************** + * Macros + *****************************************************************************/ +#define CY_LPCOMP_IS_CHANNEL_VALID(channel) (((channel) == CY_LPCOMP_CHANNEL_0) || \ + ((channel) == CY_LPCOMP_CHANNEL_1)) +#define CY_LPCOMP_IS_OUT_MODE_VALID(mode) (((mode) == CY_LPCOMP_OUT_PULSE) || \ + ((mode) == CY_LPCOMP_OUT_DIRECT) || \ + ((mode) == CY_LPCOMP_OUT_SYNC)) +#define CY_LPCOMP_IS_HYSTERESIS_VALID(hyst) (((hyst) == CY_LPCOMP_HYST_ENABLE) || \ + ((hyst) == CY_LPCOMP_HYST_DISABLE)) +#define CY_LPCOMP_IS_INTR_MODE_VALID(intr) (((intr) == CY_LPCOMP_INTR_DISABLE) || \ + ((intr) == CY_LPCOMP_INTR_RISING) || \ + ((intr) == CY_LPCOMP_INTR_FALLING) || \ + ((intr) == CY_LPCOMP_INTR_BOTH)) +#define CY_LPCOMP_IS_POWER_VALID(power) (((power) == CY_LPCOMP_MODE_OFF) || \ + ((power) == CY_LPCOMP_MODE_ULP) || \ + ((power) == CY_LPCOMP_MODE_LP) || \ + ((power) == CY_LPCOMP_MODE_NORMAL)) +#define CY_LPCOMP_IS_INTR_VALID(intr) (((intr) == CY_LPCOMP_COMP0) || \ + ((intr) == CY_LPCOMP_COMP1) || \ + ((intr) == (CY_LPCOMP_COMP0 | CY_LPCOMP_COMP1))) +#define CY_LPCOMP_IS_INPUT_P_VALID(input) (((input) == CY_LPCOMP_SW_GPIO) || \ + ((input) == CY_LPCOMP_SW_AMUXBUSA) || \ + ((input) == CY_LPCOMP_SW_AMUXBUSB)) +#define CY_LPCOMP_IS_INPUT_N_VALID(input) (((input) == CY_LPCOMP_SW_GPIO) || \ + ((input) == CY_LPCOMP_SW_AMUXBUSA) || \ + ((input) == CY_LPCOMP_SW_AMUXBUSB) || \ + ((input) == CY_LPCOMP_SW_LOCAL_VREF)) + +/** \endcond */ + +/** +* \addtogroup group_lpcomp_functions +* \{ +*/ + +/****************************************************************************** +* Functions +*******************************************************************************/ + +cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel, const cy_stc_lpcomp_config_t *config); +__STATIC_INLINE void Cy_LPComp_GlobalEnable(LPCOMP_Type *base); +__STATIC_INLINE void Cy_LPComp_GlobalDisable(LPCOMP_Type *base); +__STATIC_INLINE void Cy_LPComp_UlpReferenceEnable(LPCOMP_Type *base); +__STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base); +__STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lpcomp_channel_t channel); +void Cy_LPComp_SetPower(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_pwr_t power); +void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_hyst_t hysteresis); +void Cy_LPComp_SetInputs(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_inputs_t inputP, cy_en_lpcomp_inputs_t inputN); +void Cy_LPComp_SetOutputMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_out_t outType); +void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_int_t intType); +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatus(LPCOMP_Type const * base); +__STATIC_INLINE void Cy_LPComp_ClearInterrupt(LPCOMP_Type* base, uint32_t interrupt); +__STATIC_INLINE void Cy_LPComp_SetInterrupt(LPCOMP_Type* base, uint32_t interrupt); +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base); +__STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t interrupt); +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const * base); +__STATIC_INLINE void Cy_LPComp_ConnectULPReference(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel); +cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams); +cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams); + + +/******************************************************************************* +* Function Name: Cy_LPComp_GlobalEnable +****************************************************************************//** +* +* Activates the IP of the LPCOMP hardware block. This API should be enabled +* before operating any channel of comparators. +* Note: Interrupts can be enabled after the block is enabled and the appropriate +* start-up time has elapsed: +* 3 us for the normal power mode; +* 6 us for the LP mode; +* 50 us for the ULP mode. +* +* \param *base +* The structure of the channel pointer. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_GlobalEnable(LPCOMP_Type* base) +{ + base->CONFIG |= LPCOMP_CONFIG_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_GlobalDisable +****************************************************************************//** +* +* Deactivates the IP of the LPCOMP hardware block. +* (Analog in power down, open all switches, all clocks off). +* +* \param *base +* The structure of the channel pointer. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_GlobalDisable(LPCOMP_Type *base) +{ + base->CONFIG &= (uint32_t) ~LPCOMP_CONFIG_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_UlpReferenceEnable +****************************************************************************//** +* +* Enables the local reference-generator circuit. +* +* \param *base +* The structure of the channel pointer. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_UlpReferenceEnable(LPCOMP_Type *base) +{ + base->CONFIG |= LPCOMP_CONFIG_LPREF_EN_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_UlpReferenceDisable +****************************************************************************//** +* +* Disables the local reference-generator circuit. +* +* \param *base +* The structure of the channel pointer. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base) +{ + base->CONFIG &= (uint32_t) ~LPCOMP_CONFIG_LPREF_EN_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_GetCompare +****************************************************************************//** +* +* This function returns a nonzero value when the voltage connected to the +* positive input is greater than the negative input voltage. +* This function reads the direct (unflopped) comparator output, which can +* also be metastable (since it may result in incorrect data). +* +* \param *base +* The LPComp register structure pointer. +* +* \param channel +* The LPComp channel index. +* +* \return LPComp compare result. +* The value is a nonzero value when the voltage connected to the positive +* input is greater than the negative input voltage. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lpcomp_channel_t channel) +{ + uint32_t result; + + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + result = _FLD2VAL(LPCOMP_STATUS_OUT0, base->STATUS); + } + else + { + result = _FLD2VAL(LPCOMP_STATUS_OUT1, base->STATUS); + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetInterruptMask +****************************************************************************//** +* +* Configures which bits of the interrupt request register will trigger an +* interrupt event. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param interrupt +* uint32_t interruptMask: Bit Mask of interrupts to set. +* Bit 0: COMP0 Interrupt Mask +* Bit 1: COMP1 Interrupt Mask +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt)); + + base->INTR_MASK |= interrupt; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_GetInterruptMask +****************************************************************************//** +* +* Returns an interrupt mask. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \return bit mapping information +* Bit 0: COMP0 Interrupt Mask +* Bit 1: COMP1 Interrupt Mask +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base) +{ + return (base->INTR_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_GetInterruptStatusMasked +****************************************************************************//** +* +* Returns an interrupt request register masked by an interrupt mask. +* Returns the result of the bitwise AND operation between the corresponding +* interrupt request and mask bits. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \return bit mapping information +* Bit 0: COMP0 Interrupt Masked +* Bit 1: COMP1 Interrupt Masked +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const * base) +{ + return (base->INTR_MASKED); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_GetInterruptStatus +****************************************************************************//** +* +* Returns the status of 2 different LPCOMP interrupt requests. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \return bit mapping information +* Bit 0: COMP0 Interrupt status +* Bit 1: COMP1 Interrupt status +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatus(LPCOMP_Type const * base) +{ + return (_FLD2VAL(CY_LPCOMP_INTR, base->INTR)); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_ClearInterrupt +****************************************************************************//** +* +* Clears LPCOMP interrupts by setting each bit. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param interrupt +* Bit 0: COMP0 Interrupt status +* Bit 1: COMP1 Interrupt status +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_ClearInterrupt(LPCOMP_Type* base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt)); + base->INTR |= interrupt; + (void) LPCOMP->INTR; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetInterrupt +****************************************************************************//** +* +* Sets a software interrupt request. +* This function is used in the case of combined interrupt signal from the global +* signal reference. This function from either component instance can be used +* to trigger either or both software interrupts. It sets the INTR_SET interrupt mask. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param interrupt +* Bit 0: COMP0 Interrupt status +* Bit 1: COMP1 Interrupt status +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_SetInterrupt(LPCOMP_Type* base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt)); + base->INTR_SET = interrupt; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_ConnectULPReference +****************************************************************************//** +* +* Connects the local reference generator output to the comparator negative input. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_ConnectULPReference(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_SW_CLEAR = CY_LPCOMP_CMP0_SW_NEG_Msk; + base->CMP0_SW = _CLR_SET_FLD32U(base->CMP0_SW, LPCOMP_CMP0_SW_CMP0_VN0, CY_LPCOMP_REF_CONNECTED); + } + else + { + base->CMP1_SW_CLEAR = CY_LPCOMP_CMP1_SW_NEG_Msk; + base->CMP1_SW = _CLR_SET_FLD32U(base->CMP1_SW, LPCOMP_CMP1_SW_CMP1_VN1, CY_LPCOMP_REF_CONNECTED); + } +} + +/** \} group_lpcomp_functions */ + +#ifdef __cplusplus +} +#endif + +#endif /* CY_LPCOMP_PDL_H */ + +/** \} group_lpcomp */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lvd/cy_lvd.c b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lvd/cy_lvd.c new file mode 100644 index 0000000000..ea524c97b5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lvd/cy_lvd.c @@ -0,0 +1,64 @@ +/***************************************************************************//** +* \file cy_lvd.c +* \version 1.0 +* +* The source code file for the LVD driver. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_lvd.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_LVD_DeepSleepCallback +****************************************************************************//** +* +* When this function is registered by \ref Cy_SysPm_RegisterCallback - it +* automatically enables the LVD after wake up from DeepSleep mode. +* +* \param callbackParams a pointer to the callback parameters structure, +* see \ref cy_stc_syspm_callback_params_t. +* +* \return the SysPm callback status \ref cy_en_syspm_status_t. +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams) +{ + cy_en_syspm_status_t ret = CY_SYSPM_SUCCESS; + + switch(callbackParams->mode) + { + case CY_SYSPM_CHECK_READY: + case CY_SYSPM_CHECK_FAIL: + case CY_SYSPM_BEFORE_TRANSITION: + break; + + case CY_SYSPM_AFTER_TRANSITION: + Cy_LVD_Enable(); + break; + + default: + ret = CY_SYSPM_FAIL; + break; + } + + return(ret); +} + + +#ifdef __cplusplus +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lvd/cy_lvd.h b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lvd/cy_lvd.h new file mode 100644 index 0000000000..4bef5308d4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSoC6/device/drivers/peripheral/lvd/cy_lvd.h @@ -0,0 +1,423 @@ +/***************************************************************************//** +* \file cy_lvd.h +* \version 1.0 +* +* The header file of the LVD driver. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** +* \addtogroup group_lvd +* \{ +* The LVD driver provides an API to manage the Low Voltage Detection block. +* The LVD block provides a status of currently observed VDDD voltage +* and triggers an interrupt when the observed voltage crosses an adjusted +* threshold. +* +* \section group_lvd_configuration_considerations Configuration Considerations +* To set up an LVD, configure the voltage threshold by the +* \ref Cy_LVD_SetThreshold function, ensure that the LVD block itself and LVD +* interrupt are disabled (by the \ref Cy_LVD_Disable and +* \ref Cy_LVD_ClearInterruptMask functions correspondingly) before changing the +* threshold to prevent propagating a false interrupt. +* Then configure interrupts by the \ref Cy_LVD_SetInterruptConfig function, do +* not forget to initialise an interrupt handler (the interrupt source number +* is srss_interrupt_IRQn). +* Then enable LVD by the \ref Cy_LVD_Enable function, then wait for at least 8us +* to get the circuit stabilized and clear the possible false interrupts by the +* \ref Cy_LVD_ClearInterrupt, and finally the LVD interrupt can be enabled by +* the \ref Cy_LVD_SetInterruptMask function. +* +* For example: +* \snippet lvd_1_0_sut_00.cydsn/main_cm4.c Cy_LVD_Snippet +* +* Note that the LVD circuit is available only in Active, LPACTIVE, Sleep, and +* LPSLEEP power modes. If an LVD is required in Deep-Sleep mode, then the device +* should be configured to periodically wake up from deep sleep using a +* Deep-Sleep wakeup source. This makes sure a LVD check is performed during +* Active/LPACTIVE mode. +* +* \section group_lvd_more_information More Information +* See the LVD chapter of the device technical reference manual (TRM). +* +* \section group_lvd_MISRA MISRA-C Compliance +* The LVD driver has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
    MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
    10.3RA composite expression of 'essentially unsigned' type (%1s) is being +* cast to a different type category, '%2s'.The value got from the bitfield physically can't exceed the enumeration +* that describes this bitfield. So the code is safety by design.
    16.7AThe object addressed by the pointer parameter '%s' is not modified and +* so the pointer could be of type 'pointer to const'.The pointer parameter is not used or modified, as there is no need +* to do any actions with it. However, such parameter is +* required to be presented in the function, because the +* \ref Cy_LVD_DeepSleepCallback is a callback +* of \ref cy_en_syspm_status_t type. +* The SysPM driver callback function type requires implementing the +* function with the next parameters and return value:
    +* cy_en_syspm_status_t (*Cy_SysPmCallback) +* (cy_stc_syspm_callback_params_t *callbackParams);
    +* +* \section group_lvd_changelog Changelog +* +* +* +* +* +* +* +*
    VersionChangesReason of Change
    1.0Initial Version
    +* +* \defgroup group_lvd_macros Macros +* \defgroup group_lvd_functions Functions +* \defgroup group_lvd_enums Enumerated types +*/ + + +#if !defined CY_LVD_H +#define CY_LVD_H + +#include "syspm/cy_syspm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \addtogroup group_lvd_macros +* \{ +*/ + +/** Driver major version */ +#define CY_LVD_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_LVD_DRV_VERSION_MINOR 0 + +/** LVD driver identifier */ +#define CY_LVD_ID (CY_PDL_DRV_ID(0x39U)) + +/** Interrupt mask for \ref Cy_LVD_GetInterruptStatus(), + \ref Cy_LVD_GetInterruptMask() and + \ref Cy_LVD_GetInterruptStatusMasked() */ +#define CY_LVD_INTR (SRSS_SRSS_INTR_HVLVD1_Msk) + +/** \} group_lvd_macros */ + + +/** \addtogroup group_lvd_enums +* \{ +*/ + + +/** + * LVD reference voltage select. + */ +typedef enum +{ + CY_LVD_THRESHOLD_1_2_V = 0x0U, /**

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