diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CY8C63XX/Psoc6BLE.cpp b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CY8C63XX/Psoc6BLE.cpp new file mode 100644 index 0000000000..9b47662b31 --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CY8C63XX/Psoc6BLE.cpp @@ -0,0 +1,117 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hci_api.h" +#include "bstream.h" +#include "driver/CordioHCIDriver.h" +#include "drivers/IPCPipeTransportDriver.h" +#include "psoc6_utils.h" + +using namespace ble::vendor::cordio; +using namespace ble::vendor::cypress; + +const uint16_t HCI_VEND_SET_BD_ADDR = 0xfda0; +const uint8_t HCI_VEND_SET_BD_ADDR_LEN = 7; /* MAC address + address type */ + +class Psoc6HCIDriver : public CordioHCIDriver +{ +public: + Psoc6HCIDriver(IPCPipeTransportDriver& transport_driver) : + CordioHCIDriver(transport_driver) + { + } + + +private: + + struct BdAddress { + uint8_t mac_address[6]; + uint8_t addr_type; + + BdAddress() : addr_type(0) {} + }; + + /** + * Initialize the chip. + * The transport is up at that time. + */ + virtual void do_initialize(); + + /** + * Terminate the driver + */ + virtual void do_terminate() {} + + virtual void handle_reset_sequence(uint8_t *pMsg); + +private: + BdAddress bd_address; +}; + + +void Psoc6HCIDriver::do_initialize() +{ + cy_get_bd_mac_address(bd_address.mac_address); +} + + +void Psoc6HCIDriver::handle_reset_sequence(uint8_t *pMsg) { + + uint16_t opcode; + + /* if event is a command complete event */ + if (*pMsg == HCI_CMD_CMPL_EVT) { + /* parse parameters */ + uint8_t *pMsg2 = pMsg + HCI_EVT_HDR_LEN; + pMsg2++; /* skip num packets */ + BSTREAM_TO_UINT16(opcode, pMsg2); + pMsg2 -= 2; + /* decode opcode */ + switch (opcode) { + case HCI_OPCODE_RESET: + /* send next command in sequence */ + HciVendorSpecificCmd(HCI_VEND_SET_BD_ADDR, + HCI_VEND_SET_BD_ADDR_LEN, + reinterpret_cast(&bd_address)); + break; + + case HCI_VEND_SET_BD_ADDR: + /* pretend we have just completed reset */ + UINT16_TO_BSTREAM(pMsg2, HCI_OPCODE_RESET); + CordioHCIDriver::handle_reset_sequence(pMsg); + break; + + default: + /* pass to parent */ + CordioHCIDriver::handle_reset_sequence(pMsg); + } + } +} + + +CordioHCIDriver& ble_cordio_get_hci_driver() { + static IPCPipeTransportDriver transport_driver; + + static Psoc6HCIDriver hci_driver( + transport_driver /* other hci driver parameters */ + ); + + return hci_driver; +} + + diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CY8C63XX/drivers/IPCPipeTransportDriver.cpp b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CY8C63XX/drivers/IPCPipeTransportDriver.cpp new file mode 100644 index 0000000000..a7cfa94f99 --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CY8C63XX/drivers/IPCPipeTransportDriver.cpp @@ -0,0 +1,75 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "IPCPipeTransportDriver.h" +#include "ipcpipe_transport.h" +#include "mbed_assert.h" +#include "mbed_error.h" + +namespace ble { +namespace vendor { +namespace cypress { + + +void dump_buffer(uint8_t *buffer, uint32_t len) +{ + + while (len > 0) { + printf(" %02x", *buffer++); + --len; + } + printf("\n"); +} + +void ipc_h4_receive(uint32_t *ptr) +{ + IpcPipeMessage *message = (IpcPipeMessage *)ptr; + + // We don't expect header to be received from M0+ core. + MBED_ASSERT(message->header_length == 0); + +// printf("BLE received: "); +// h4_dump_buffer(buffer->message.data, buffer->message.length); + cordio::CordioHCITransportDriver::on_data_received(message->data, message->data_length); +} + +IPCPipeTransportDriver::IPCPipeTransportDriver() +{ } + +void IPCPipeTransportDriver::initialize() +{ +// printf("H4 Transport driver initialization.\n"); + ipcpipe_transport_start(IPCPIPE_CLIENT_H4, ipc_h4_receive, NULL); +} + +void IPCPipeTransportDriver::terminate() +{ + ipcpipe_transport_stop(IPCPIPE_CLIENT_H4); +} + +uint16_t IPCPipeTransportDriver::write(uint8_t type, uint16_t len, uint8_t *pData) +{ +// printf("BLE sending T<%02x>:", type); +// dump_buffer(pData, len); + ipcpipe_write_data(IPCPIPE_CLIENT_H4, &type, 1, pData, len); + return len; +} + +} // namespace cypress +} // namespace vendor +} // namespace ble diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CY8C63XX/drivers/IPCPipeTransportDriver.h b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CY8C63XX/drivers/IPCPipeTransportDriver.h new file mode 100644 index 0000000000..7707e0de15 --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CY8C63XX/drivers/IPCPipeTransportDriver.h @@ -0,0 +1,72 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSOC6_IPCPIPE_TRANSPORT_DRIVER_H_ +#define PSOC6_IPCPIPE_TRANSPORT_DRIVER_H_ + +#include +#include "mbed.h" +#include "CordioHCITransportDriver.h" + + +namespace ble { +namespace vendor { +namespace cypress { + +using namespace ble::vendor; + +/** + * Implementation of the H4 driver over PSoC6 IPC pipe. + */ +class IPCPipeTransportDriver : public cordio::CordioHCITransportDriver { +public: + /** + * Initialize the transport driver. + * + */ + IPCPipeTransportDriver(); + + /** + * Destructor + */ + virtual ~IPCPipeTransportDriver() { } + + /** + * @see CordioHCITransportDriver::initialize + */ + virtual void initialize(); + + /** + * @see CordioHCITransportDriver::terminate + */ + virtual void terminate(); + + /** + * @see CordioHCITransportDriver::write + */ + virtual uint16_t write(uint8_t type, uint16_t len, uint8_t *pData); + +private: + +}; + +} // namespace cypress +} // namespace vendor +} // namespace ble + +#endif /* PSOC6_IPCPIPE_TRANSPORT_DRIVER_H_ */ diff --git a/features/storage/nvstore/mbed_lib.json b/features/storage/nvstore/mbed_lib.json index d13cdbd4b2..a7f72acad0 100644 --- a/features/storage/nvstore/mbed_lib.json +++ b/features/storage/nvstore/mbed_lib.json @@ -27,5 +27,19 @@ "macro_name": "NVSTORE_AREA_2_SIZE", "help": "Area 2 size" } + }, + "target_overrides": { + "FUTURE_SEQUANA": { + "area_1_address": "0x100F8000", + "area_1_size": 16384, + "area_2_address": "0x100FC000", + "area_2_size": 16384 + }, + "FUTURE_SEQUANA_M0": { + "area_1_address": "0x10078000", + "area_1_size": 16384, + "area_2_address": "0x1007C000", + "area_2_size": 16384 + } } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/PeripheralNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/PeripheralNames.h new file mode 100644 index 0000000000..836df4692c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/PeripheralNames.h @@ -0,0 +1,109 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)SCB0_BASE, + UART_1 = (int)SCB1_BASE, + UART_2 = (int)SCB2_BASE, + UART_3 = (int)SCB3_BASE, + UART_4 = (int)SCB4_BASE, + UART_5 = (int)SCB5_BASE, + UART_6 = (int)SCB6_BASE, + UART_7 = (int)SCB7_BASE, +} UARTName; + + +typedef enum { + SPI_0 = (int)SCB0_BASE, + SPI_1 = (int)SCB1_BASE, + SPI_2 = (int)SCB2_BASE, + SPI_3 = (int)SCB3_BASE, + SPI_4 = (int)SCB4_BASE, + SPI_5 = (int)SCB5_BASE, + SPI_6 = (int)SCB6_BASE, + SPI_7 = (int)SCB7_BASE, +} SPIName; + +typedef enum { + I2C_0 = (int)SCB0_BASE, + I2C_1 = (int)SCB1_BASE, + I2C_2 = (int)SCB2_BASE, + I2C_3 = (int)SCB3_BASE, + I2C_4 = (int)SCB4_BASE, + I2C_5 = (int)SCB5_BASE, + I2C_6 = (int)SCB6_BASE, + I2C_7 = (int)SCB7_BASE, +} I2CName; + +typedef enum { + PWM_32b_0 = TCPWM0_BASE, + PWM_32b_1, + PWM_32b_2, + PWM_32b_3, + PWM_32b_4, + PWM_32b_5, + PWM_32b_6, + PWM_32b_7, + PWM_16b_0 = TCPWM1_BASE, + PWM_16b_1, + PWM_16b_2, + PWM_16b_3, + PWM_16b_4, + PWM_16b_5, + PWM_16b_6, + PWM_16b_7, + PWM_16b_8, + PWM_16b_9, + PWM_16b_10, + PWM_16b_11, + PWM_16b_12, + PWM_16b_13, + PWM_16b_14, + PWM_16b_15, + PWM_16b_16, + PWM_16b_17, + PWM_16b_18, + PWM_16b_19, + PWM_16b_20, + PWM_16b_21, + PWM_16b_22, + PWM_16b_23, +} PWMName; + +typedef enum { + ADC_0 = (int)SAR_BASE, +} ADCName; + +typedef enum { + DAC_0 = (int)CTDAC0_BASE, +} DACName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/PeripheralPins.h b/targets/TARGET_Cypress/TARGET_PSOC6/PeripheralPins.h new file mode 100644 index 0000000000..07237af517 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/PeripheralPins.h @@ -0,0 +1,62 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + + +// //*** I2C *** +#if DEVICE_I2C +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; +#endif + +//*** PWM *** +#if DEVICE_PWMOUT +extern const PinMap PinMap_PWM_OUT[]; +#endif + +//*** SERIAL *** +#ifdef DEVICE_SERIAL +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif + +//*** SPI *** +#ifdef DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif + +//*** ADC *** +#ifdef DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +#endif + +//*** DAC *** +#ifdef DEVICE_ANALOGOUT +extern const PinMap PinMap_DAC[]; +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h b/targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h new file mode 100644 index 0000000000..559e3cc2c3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/PinNamesTypes.h @@ -0,0 +1,84 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PINNAMESTYPES_H +#define MBED_PINNAMESTYPES_H + +#include "cmsis.h" + +typedef enum { + PIN_INPUT = 0, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrainDriveLow = 3, + OpenDrainDriveHigh = 4, + OpenDrain = OpenDrainDriveLow, + PushPull = 5, + AnalogMode = 6, + PullDefault = PullNone +} PinMode; + +typedef struct { + en_hsiom_sel_t hsiom : 8; + en_clk_dst_t clock : 8; + PinMode mode : 4; + PinDirection dir : 1; +} PinFunction; + +// Encode pin function. +// Output function +#define CY_PIN_FUNCTION(hsiom, clock, mode, dir) (int)(((dir) << 20) | ((mode) << 16) | ((clock) << 8) | (hsiom)) +#define CY_PIN_OUT_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, PushPull, PIN_OUTPUT) +#define CY_PIN_OD_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, OpenDrain, PIN_OUTPUT) +#define CY_PIN_IN_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, PullDefault, PIN_INPUT) +#define CY_PIN_PULLUP_FUNCTION(hsiom, clock) CY_PIN_FUNCTION(hsiom, clock, PullUp, PIN_INPUT) +#define CY_PIN_ANALOG_FUNCTION(clock) CY_PIN_FUNCTION(HSIOM_SEL_GPIO, clock, AnalogMode, 0) + +// Create unique name to force 32-bit PWM usage on a pin. +#define CY_PIN_FORCE_PWM_32(pin) ((uint32_t)(pin) + 0x8000) + +static inline en_hsiom_sel_t CY_PIN_HSIOM(int function) +{ + return (en_hsiom_sel_t)(function & 0xFF); +} + +static inline en_clk_dst_t CY_PIN_CLOCK(int function) +{ + return (en_clk_dst_t)((function >> 8) & 0xFF); +} + +static inline PinMode CY_PIN_MODE(int function) +{ + return (PinMode)((function >> 16) & 0x0F); +} + +static inline PinDirection CY_PIN_DIRECTION(int function) +{ + return (PinDirection)((function >> 20) & 1); +} + +static inline int CY_PERIPHERAL_BASE(int peripheral) +{ + return peripheral & 0xffff0000; +} + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/PortNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/PortNames.h new file mode 100644 index 0000000000..e30039df79 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/PortNames.h @@ -0,0 +1,47 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// Port[15-0] +typedef enum { + Port0 = 0x0, + Port1 = 0x1, + Port2 = 0x2, + Port3 = 0x3, + Port4 = 0x4, + Port5 = 0x5, + Port6 = 0x6, + Port7 = 0x7, + Port8 = 0x8, + Port9 = 0x9, + Port10 = 0xA, + Port11 = 0xB, + Port12 = 0xC, + Port13 = 0xD, + Port14 = 0xE +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/PeripheralPins.c new file mode 100644 index 0000000000..0de9f5e995 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/PeripheralPins.c @@ -0,0 +1,364 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralNames.h" +#include "PeripheralPins.h" +#include "pinmap.h" + +#if DEVICE_SERIAL +//*** SERIAL *** +const PinMap PinMap_UART_RX[] = { + {P0_2, UART_0, CY_PIN_IN_FUNCTION( P0_2_SCB0_UART_RX, PCLK_SCB0_CLOCK)}, + {P1_0, UART_7, CY_PIN_IN_FUNCTION( P1_0_SCB7_UART_RX, PCLK_SCB7_CLOCK)}, + {P5_0, UART_5, CY_PIN_IN_FUNCTION( P5_0_SCB5_UART_RX, PCLK_SCB5_CLOCK)}, + {P6_0, UART_3, CY_PIN_IN_FUNCTION( P6_0_SCB3_UART_RX, PCLK_SCB3_CLOCK)}, + {P6_4, UART_6, CY_PIN_IN_FUNCTION( P6_4_SCB6_UART_RX, PCLK_SCB6_CLOCK)}, + {P7_0, UART_4, CY_PIN_IN_FUNCTION( P7_0_SCB4_UART_RX, PCLK_SCB4_CLOCK)}, + {P8_0, UART_4, CY_PIN_IN_FUNCTION( P8_0_SCB4_UART_RX, PCLK_SCB4_CLOCK)}, + {P9_0, UART_2, CY_PIN_IN_FUNCTION( P9_0_SCB2_UART_RX, PCLK_SCB2_CLOCK)}, + {P10_0, UART_1, CY_PIN_IN_FUNCTION( P10_0_SCB1_UART_RX, PCLK_SCB1_CLOCK)}, + {P11_0, UART_5, CY_PIN_IN_FUNCTION( P11_0_SCB5_UART_RX, PCLK_SCB5_CLOCK)}, + {P12_0, UART_6, CY_PIN_IN_FUNCTION( P12_0_SCB6_UART_RX, PCLK_SCB6_CLOCK)}, + {P13_0, UART_6, CY_PIN_IN_FUNCTION( P13_0_SCB6_UART_RX, PCLK_SCB6_CLOCK)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_TX[] = { + {P0_3, UART_0, CY_PIN_OUT_FUNCTION( P0_3_SCB0_UART_TX, PCLK_SCB0_CLOCK)}, + {P1_1, UART_7, CY_PIN_OUT_FUNCTION( P1_1_SCB7_UART_TX, PCLK_SCB7_CLOCK)}, + {P5_1, UART_5, CY_PIN_OUT_FUNCTION( P5_1_SCB5_UART_TX, PCLK_SCB5_CLOCK)}, + {P6_1, UART_3, CY_PIN_OUT_FUNCTION( P6_1_SCB3_UART_TX, PCLK_SCB3_CLOCK)}, + {P6_5, UART_6, CY_PIN_OUT_FUNCTION( P6_5_SCB6_UART_TX, PCLK_SCB6_CLOCK)}, + {P7_1, UART_4, CY_PIN_OUT_FUNCTION( P7_1_SCB4_UART_TX, PCLK_SCB4_CLOCK)}, + {P8_1, UART_4, CY_PIN_OUT_FUNCTION( P8_1_SCB4_UART_TX, PCLK_SCB4_CLOCK)}, + {P9_1, UART_2, CY_PIN_OUT_FUNCTION( P9_1_SCB2_UART_TX, PCLK_SCB2_CLOCK)}, + {P10_1, UART_1, CY_PIN_OUT_FUNCTION( P10_1_SCB1_UART_TX, PCLK_SCB1_CLOCK)}, + {P11_1, UART_5, CY_PIN_OUT_FUNCTION( P11_1_SCB5_UART_TX, PCLK_SCB5_CLOCK)}, + {P12_1, UART_6, CY_PIN_OUT_FUNCTION( P12_1_SCB6_UART_TX, PCLK_SCB6_CLOCK)}, + {P13_1, UART_6, CY_PIN_OUT_FUNCTION( P13_1_SCB6_UART_TX, PCLK_SCB6_CLOCK)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_RTS[] = { + {P0_4, UART_0, CY_PIN_OUT_FUNCTION( P0_4_SCB0_UART_RTS, PCLK_SCB0_CLOCK)}, + {P1_2, UART_7, CY_PIN_OUT_FUNCTION( P1_2_SCB7_UART_RTS, PCLK_SCB7_CLOCK)}, + {P5_2, UART_5, CY_PIN_OUT_FUNCTION( P5_2_SCB5_UART_RTS, PCLK_SCB5_CLOCK)}, + {P6_2, UART_3, CY_PIN_OUT_FUNCTION( P6_2_SCB3_UART_RTS, PCLK_SCB3_CLOCK)}, + {P6_6, UART_6, CY_PIN_OUT_FUNCTION( P6_6_SCB6_UART_RTS, PCLK_SCB6_CLOCK)}, + {P7_2, UART_4, CY_PIN_OUT_FUNCTION( P7_2_SCB4_UART_RTS, PCLK_SCB4_CLOCK)}, + {P8_2, UART_4, CY_PIN_OUT_FUNCTION( P8_2_SCB4_UART_RTS, PCLK_SCB4_CLOCK)}, + {P9_2, UART_2, CY_PIN_OUT_FUNCTION( P9_2_SCB2_UART_RTS, PCLK_SCB2_CLOCK)}, + {P10_2, UART_1, CY_PIN_OUT_FUNCTION( P10_2_SCB1_UART_RTS, PCLK_SCB1_CLOCK)}, + {P11_2, UART_5, CY_PIN_OUT_FUNCTION( P11_2_SCB5_UART_RTS, PCLK_SCB5_CLOCK)}, + {P12_2, UART_6, CY_PIN_OUT_FUNCTION( P12_2_SCB6_UART_RTS, PCLK_SCB6_CLOCK)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_CTS[] = { + {P0_5, UART_0, CY_PIN_IN_FUNCTION( P0_5_SCB0_UART_CTS, PCLK_SCB0_CLOCK)}, + {P1_3, UART_7, CY_PIN_IN_FUNCTION( P1_3_SCB7_UART_CTS, PCLK_SCB7_CLOCK)}, + {P5_3, UART_5, CY_PIN_IN_FUNCTION( P5_3_SCB5_UART_CTS, PCLK_SCB5_CLOCK)}, + {P6_3, UART_3, CY_PIN_IN_FUNCTION( P6_3_SCB3_UART_CTS, PCLK_SCB3_CLOCK)}, + {P6_7, UART_6, CY_PIN_IN_FUNCTION( P6_7_SCB6_UART_CTS, PCLK_SCB6_CLOCK)}, + {P7_3, UART_4, CY_PIN_IN_FUNCTION( P7_3_SCB4_UART_CTS, PCLK_SCB4_CLOCK)}, + {P8_3, UART_4, CY_PIN_IN_FUNCTION( P8_3_SCB4_UART_CTS, PCLK_SCB4_CLOCK)}, + {P9_3, UART_2, CY_PIN_IN_FUNCTION( P9_3_SCB2_UART_CTS, PCLK_SCB2_CLOCK)}, + {P10_3, UART_1, CY_PIN_IN_FUNCTION( P10_3_SCB1_UART_CTS, PCLK_SCB1_CLOCK)}, + {P11_3, UART_5, CY_PIN_IN_FUNCTION( P11_3_SCB5_UART_CTS, PCLK_SCB5_CLOCK)}, + {P12_3, UART_6, CY_PIN_IN_FUNCTION( P12_3_SCB6_UART_CTS, PCLK_SCB6_CLOCK)}, + {NC, NC, 0} +}; +#endif // DEVICE_SERIAL + + +#if DEVICE_I2C +//*** I2C *** +const PinMap PinMap_I2C_SCL[] = { + {P0_2, I2C_0, CY_PIN_OD_FUNCTION( P0_2_SCB0_I2C_SCL, PCLK_SCB0_CLOCK)}, + {P1_0, I2C_7, CY_PIN_OD_FUNCTION( P1_0_SCB7_I2C_SCL, PCLK_SCB7_CLOCK)}, + {P5_0, I2C_5, CY_PIN_OD_FUNCTION( P5_0_SCB5_I2C_SCL, PCLK_SCB5_CLOCK)}, + {P6_0, I2C_3, CY_PIN_OD_FUNCTION( P6_0_SCB3_I2C_SCL, PCLK_SCB3_CLOCK)}, + {P6_4, I2C_6, CY_PIN_OD_FUNCTION( P6_4_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)}, + {P7_0, I2C_4, CY_PIN_OD_FUNCTION( P7_0_SCB4_I2C_SCL, PCLK_SCB4_CLOCK)}, + {P8_0, I2C_4, CY_PIN_OD_FUNCTION( P8_0_SCB4_I2C_SCL, PCLK_SCB4_CLOCK)}, + {P9_0, I2C_2, CY_PIN_OD_FUNCTION( P9_0_SCB2_I2C_SCL, PCLK_SCB2_CLOCK)}, + {P10_0, I2C_1, CY_PIN_OD_FUNCTION( P10_0_SCB1_I2C_SCL, PCLK_SCB1_CLOCK)}, + {P11_0, I2C_5, CY_PIN_OD_FUNCTION( P11_0_SCB5_I2C_SCL, PCLK_SCB5_CLOCK)}, + {P12_0, I2C_6, CY_PIN_OD_FUNCTION( P12_0_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)}, + {P13_0, I2C_6, CY_PIN_OD_FUNCTION( P13_0_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)}, + {NC, NC, 0} +}; +const PinMap PinMap_I2C_SDA[] = { + {P0_3, I2C_0, CY_PIN_OD_FUNCTION( P0_3_SCB0_I2C_SDA, PCLK_SCB0_CLOCK)}, + {P1_1, I2C_7, CY_PIN_OD_FUNCTION( P1_1_SCB7_I2C_SDA, PCLK_SCB7_CLOCK)}, + {P5_1, I2C_5, CY_PIN_OD_FUNCTION( P5_1_SCB5_I2C_SDA, PCLK_SCB5_CLOCK)}, + {P6_1, I2C_3, CY_PIN_OD_FUNCTION( P6_1_SCB3_I2C_SDA, PCLK_SCB3_CLOCK)}, + {P6_5, I2C_6, CY_PIN_OD_FUNCTION( P6_5_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)}, + {P7_1, I2C_4, CY_PIN_OD_FUNCTION( P7_1_SCB4_I2C_SDA, PCLK_SCB4_CLOCK)}, + {P8_1, I2C_4, CY_PIN_OD_FUNCTION( P8_1_SCB4_I2C_SDA, PCLK_SCB4_CLOCK)}, + {P9_1, I2C_2, CY_PIN_OD_FUNCTION( P9_1_SCB2_I2C_SDA, PCLK_SCB2_CLOCK)}, + {P10_1, I2C_1, CY_PIN_OD_FUNCTION( P10_1_SCB1_I2C_SDA, PCLK_SCB1_CLOCK)}, + {P11_1, I2C_5, CY_PIN_OD_FUNCTION( P11_1_SCB5_I2C_SDA, PCLK_SCB5_CLOCK)}, + {P12_1, I2C_6, CY_PIN_OD_FUNCTION( P12_1_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)}, + {P13_1, I2C_6, CY_PIN_OD_FUNCTION( P13_1_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)}, + {NC, NC, 0} +}; +#endif // DEVICE_I2C + +#if DEVICE_SPI +//*** SPI *** +const PinMap PinMap_SPI_MOSI[] = { + {P0_2, SPI_0, CY_PIN_OUT_FUNCTION( P0_2_SCB0_SPI_MOSI, PCLK_SCB0_CLOCK)}, + {P1_0, SPI_7, CY_PIN_OUT_FUNCTION( P1_0_SCB7_SPI_MOSI, PCLK_SCB7_CLOCK)}, + {P5_0, SPI_5, CY_PIN_OUT_FUNCTION( P5_0_SCB5_SPI_MOSI, PCLK_SCB5_CLOCK)}, + {P6_0, SPI_3, CY_PIN_OUT_FUNCTION( P6_0_SCB3_SPI_MOSI, PCLK_SCB3_CLOCK)}, + {P6_4, SPI_6, CY_PIN_OUT_FUNCTION( P6_4_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)}, + {P7_0, SPI_4, CY_PIN_OUT_FUNCTION( P7_0_SCB4_SPI_MOSI, PCLK_SCB4_CLOCK)}, + {P8_0, SPI_4, CY_PIN_OUT_FUNCTION( P8_0_SCB4_SPI_MOSI, PCLK_SCB4_CLOCK)}, + {P9_0, SPI_2, CY_PIN_OUT_FUNCTION( P9_0_SCB2_SPI_MOSI, PCLK_SCB2_CLOCK)}, + {P10_0, SPI_1, CY_PIN_OUT_FUNCTION( P10_0_SCB1_SPI_MOSI, PCLK_SCB1_CLOCK)}, + {P11_0, SPI_5, CY_PIN_OUT_FUNCTION( P11_0_SCB5_SPI_MOSI, PCLK_SCB5_CLOCK)}, + {P12_0, SPI_6, CY_PIN_OUT_FUNCTION( P12_0_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)}, + {P13_0, SPI_6, CY_PIN_OUT_FUNCTION( P13_0_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_MISO[] = { + {P0_3, SPI_0, CY_PIN_IN_FUNCTION( P0_3_SCB0_SPI_MISO, PCLK_SCB0_CLOCK)}, + {P1_1, SPI_7, CY_PIN_IN_FUNCTION( P1_1_SCB7_SPI_MISO, PCLK_SCB7_CLOCK)}, + {P5_1, SPI_5, CY_PIN_IN_FUNCTION( P5_1_SCB5_SPI_MISO, PCLK_SCB5_CLOCK)}, + {P6_1, SPI_3, CY_PIN_IN_FUNCTION( P6_1_SCB3_SPI_MISO, PCLK_SCB3_CLOCK)}, + {P6_5, SPI_6, CY_PIN_IN_FUNCTION( P6_5_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)}, + {P7_1, SPI_4, CY_PIN_IN_FUNCTION( P7_1_SCB4_SPI_MISO, PCLK_SCB4_CLOCK)}, + {P8_1, SPI_4, CY_PIN_IN_FUNCTION( P8_1_SCB4_SPI_MISO, PCLK_SCB4_CLOCK)}, + {P9_1, SPI_2, CY_PIN_IN_FUNCTION( P9_1_SCB2_SPI_MISO, PCLK_SCB2_CLOCK)}, + {P10_1, SPI_1, CY_PIN_IN_FUNCTION( P10_1_SCB1_SPI_MISO, PCLK_SCB1_CLOCK)}, + {P11_1, SPI_5, CY_PIN_IN_FUNCTION( P11_1_SCB5_SPI_MISO, PCLK_SCB5_CLOCK)}, + {P12_1, SPI_6, CY_PIN_IN_FUNCTION( P12_1_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)}, + {P13_1, SPI_6, CY_PIN_IN_FUNCTION( P13_1_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SCLK[] = { + {P0_4, SPI_0, CY_PIN_OUT_FUNCTION( P0_4_SCB0_SPI_CLK, PCLK_SCB0_CLOCK)}, + {P1_2, SPI_7, CY_PIN_OUT_FUNCTION( P1_2_SCB7_SPI_CLK, PCLK_SCB7_CLOCK)}, + {P5_2, SPI_5, CY_PIN_OUT_FUNCTION( P5_2_SCB5_SPI_CLK, PCLK_SCB5_CLOCK)}, + {P6_2, SPI_3, CY_PIN_OUT_FUNCTION( P6_2_SCB3_SPI_CLK, PCLK_SCB3_CLOCK)}, + {P6_6, SPI_6, CY_PIN_OUT_FUNCTION( P6_6_SCB6_SPI_CLK, PCLK_SCB6_CLOCK)}, + {P7_2, SPI_4, CY_PIN_OUT_FUNCTION( P7_2_SCB4_SPI_CLK, PCLK_SCB4_CLOCK)}, + + {P8_2, SPI_4, CY_PIN_OUT_FUNCTION( P8_2_SCB4_SPI_CLK, PCLK_SCB4_CLOCK)}, + {P9_2, SPI_2, CY_PIN_OUT_FUNCTION( P9_2_SCB2_SPI_CLK, PCLK_SCB2_CLOCK)}, + {P10_2, SPI_1, CY_PIN_OUT_FUNCTION( P10_2_SCB1_SPI_CLK, PCLK_SCB1_CLOCK)}, + {P11_2, SPI_5, CY_PIN_OUT_FUNCTION( P11_2_SCB5_SPI_CLK, PCLK_SCB5_CLOCK)}, + {P12_2, SPI_6, CY_PIN_OUT_FUNCTION( P12_2_SCB6_SPI_CLK, PCLK_SCB6_CLOCK)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SSEL[] = { + {P0_5, SPI_0, CY_PIN_OUT_FUNCTION( P0_5_SCB0_SPI_SELECT0, PCLK_SCB0_CLOCK)}, + {P1_3, SPI_7, CY_PIN_OUT_FUNCTION( P1_3_SCB7_SPI_SELECT0, PCLK_SCB7_CLOCK)}, + {P5_3, SPI_5, CY_PIN_OUT_FUNCTION( P5_3_SCB5_SPI_SELECT0, PCLK_SCB5_CLOCK)}, + {P6_3, SPI_3, CY_PIN_OUT_FUNCTION( P6_3_SCB3_SPI_SELECT0, PCLK_SCB3_CLOCK)}, + {P6_7, SPI_6, CY_PIN_OUT_FUNCTION( P6_7_SCB6_SPI_SELECT0, PCLK_SCB6_CLOCK)}, + {P7_3, SPI_4, CY_PIN_OUT_FUNCTION( P7_3_SCB4_SPI_SELECT0, PCLK_SCB4_CLOCK)}, + {P8_3, SPI_4, CY_PIN_OUT_FUNCTION( P8_3_SCB4_SPI_SELECT0, PCLK_SCB4_CLOCK)}, + {P9_3, SPI_2, CY_PIN_OUT_FUNCTION( P9_3_SCB2_SPI_SELECT0, PCLK_SCB2_CLOCK)}, + {P10_3, SPI_1, CY_PIN_OUT_FUNCTION( P10_3_SCB1_SPI_SELECT0, PCLK_SCB1_CLOCK)}, + {P11_3, SPI_5, CY_PIN_OUT_FUNCTION( P11_3_SCB5_SPI_SELECT0, PCLK_SCB5_CLOCK)}, + {P12_3, SPI_6, CY_PIN_OUT_FUNCTION( P12_3_SCB6_SPI_SELECT0, PCLK_SCB6_CLOCK)}, + {NC, NC, 0} +}; +#endif // DEVICE_SPI + +#if DEVICE_PWMOUT +//*** PWM *** +const PinMap PinMap_PWM_OUT[] = { + // 16-bit PWM outputs + {P0_0, PWM_16b_0, CY_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)}, + {P0_2, PWM_16b_1, CY_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)}, + {P0_4, PWM_16b_2, CY_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)}, + {P1_0, PWM_16b_3, CY_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3, PCLK_TCPWM1_CLOCKS3)}, + {P1_2, PWM_16b_12, CY_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12, PCLK_TCPWM1_CLOCKS12)}, + {P1_4, PWM_16b_13, CY_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13, PCLK_TCPWM1_CLOCKS13)}, + {P5_0, PWM_16b_4, CY_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4, PCLK_TCPWM1_CLOCKS4)}, + {P5_2, PWM_16b_5, CY_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5, PCLK_TCPWM1_CLOCKS5)}, + {P5_4, PWM_16b_6, CY_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6, PCLK_TCPWM1_CLOCKS6)}, + {P5_6, PWM_16b_7, CY_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7, PCLK_TCPWM1_CLOCKS7)}, + {P6_0, PWM_16b_8, CY_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8, PCLK_TCPWM1_CLOCKS8)}, + {P6_2, PWM_16b_9, CY_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9, PCLK_TCPWM1_CLOCKS9)}, + {P6_4, PWM_16b_10, CY_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10, PCLK_TCPWM1_CLOCKS10)}, + {P6_6, PWM_16b_11, CY_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11, PCLK_TCPWM1_CLOCKS11)}, + {P7_0, PWM_16b_12, CY_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12, PCLK_TCPWM1_CLOCKS12)}, + {P7_2, PWM_16b_13, CY_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13, PCLK_TCPWM1_CLOCKS13)}, + {P7_4, PWM_16b_14, CY_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14, PCLK_TCPWM1_CLOCKS14)}, + {P7_6, PWM_16b_15, CY_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15, PCLK_TCPWM1_CLOCKS15)}, + {P8_0, PWM_16b_16, CY_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16, PCLK_TCPWM1_CLOCKS16)}, + {P8_2, PWM_16b_17, CY_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17, PCLK_TCPWM1_CLOCKS17)}, + {P8_4, PWM_16b_18, CY_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18, PCLK_TCPWM1_CLOCKS18)}, + {P8_6, PWM_16b_19, CY_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19, PCLK_TCPWM1_CLOCKS19)}, + {P9_0, PWM_16b_20, CY_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20, PCLK_TCPWM1_CLOCKS20)}, + {P9_2, PWM_16b_21, CY_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21, PCLK_TCPWM1_CLOCKS21)}, + {P9_4, PWM_16b_0, CY_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)}, + {P9_6, PWM_16b_1, CY_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)}, + {P10_0, PWM_16b_22, CY_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22, PCLK_TCPWM1_CLOCKS22)}, + {P10_2, PWM_16b_23, CY_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23, PCLK_TCPWM1_CLOCKS23)}, + {P10_4, PWM_16b_0, CY_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)}, + {P10_6, PWM_16b_2, CY_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)}, + {P11_0, PWM_16b_1, CY_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)}, + {P11_2, PWM_16b_2, CY_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)}, + {P11_4, PWM_16b_3, CY_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3, PCLK_TCPWM1_CLOCKS3)}, + {P12_0, PWM_16b_4, CY_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4, PCLK_TCPWM1_CLOCKS4)}, + {P12_2, PWM_16b_5, CY_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5, PCLK_TCPWM1_CLOCKS5)}, + {P12_4, PWM_16b_6, CY_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6, PCLK_TCPWM1_CLOCKS6)}, + {P12_6, PWM_16b_7, CY_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7, PCLK_TCPWM1_CLOCKS7)}, + {P13_0, PWM_16b_8, CY_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8, PCLK_TCPWM1_CLOCKS8)}, + {P13_6, PWM_16b_11, CY_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11, PCLK_TCPWM1_CLOCKS11)}, + // 16-bit PWM inverted outputs + {P0_1, PWM_16b_0, CY_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)}, + {P0_3, PWM_16b_1, CY_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)}, + {P0_5, PWM_16b_2, CY_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)}, + {P1_1, PWM_16b_3, CY_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3, PCLK_TCPWM1_CLOCKS3)}, + {P1_3, PWM_16b_12, CY_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12, PCLK_TCPWM1_CLOCKS12)}, + {P1_5, PWM_16b_14, CY_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14, PCLK_TCPWM1_CLOCKS14)}, + {P5_1, PWM_16b_4, CY_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4, PCLK_TCPWM1_CLOCKS4)}, + {P5_3, PWM_16b_5, CY_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5, PCLK_TCPWM1_CLOCKS5)}, + {P5_5, PWM_16b_6, CY_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6, PCLK_TCPWM1_CLOCKS6)}, + {P6_1, PWM_16b_8, CY_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8, PCLK_TCPWM1_CLOCKS8)}, + {P6_3, PWM_16b_9, CY_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9, PCLK_TCPWM1_CLOCKS9)}, + {P6_5, PWM_16b_10, CY_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10, PCLK_TCPWM1_CLOCKS10)}, + {P6_7, PWM_16b_11, CY_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11, PCLK_TCPWM1_CLOCKS11)}, + {P7_1, PWM_16b_12, CY_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12, PCLK_TCPWM1_CLOCKS12)}, + {P7_3, PWM_16b_13, CY_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13, PCLK_TCPWM1_CLOCKS13)}, + {P7_5, PWM_16b_14, CY_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14, PCLK_TCPWM1_CLOCKS14)}, + {P7_7, PWM_16b_15, CY_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15, PCLK_TCPWM1_CLOCKS15)}, + {P8_1, PWM_16b_16, CY_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16, PCLK_TCPWM1_CLOCKS16)}, + {P8_3, PWM_16b_17, CY_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17, PCLK_TCPWM1_CLOCKS17)}, + {P8_5, PWM_16b_18, CY_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18, PCLK_TCPWM1_CLOCKS18)}, + {P8_7, PWM_16b_19, CY_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19, PCLK_TCPWM1_CLOCKS19)}, + {P9_1, PWM_16b_20, CY_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20, PCLK_TCPWM1_CLOCKS20)}, + {P9_3, PWM_16b_21, CY_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21, PCLK_TCPWM1_CLOCKS21)}, + {P9_5, PWM_16b_0, CY_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)}, + {P9_7, PWM_16b_1, CY_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)}, + {P10_1, PWM_16b_22, CY_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22, PCLK_TCPWM1_CLOCKS22)}, + {P10_3, PWM_16b_23, CY_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23, PCLK_TCPWM1_CLOCKS23)}, + {P10_5, PWM_16b_0, CY_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)}, + {P11_1, PWM_16b_1, CY_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)}, + {P11_3, PWM_16b_2, CY_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)}, + {P11_5, PWM_16b_3, CY_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3, PCLK_TCPWM1_CLOCKS3)}, + {P12_1, PWM_16b_4, CY_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4, PCLK_TCPWM1_CLOCKS4)}, + {P12_3, PWM_16b_5, CY_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5, PCLK_TCPWM1_CLOCKS5)}, + {P12_5, PWM_16b_6, CY_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6, PCLK_TCPWM1_CLOCKS6)}, + {P12_7, PWM_16b_7, CY_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7, PCLK_TCPWM1_CLOCKS7)}, + {P13_1, PWM_16b_8, CY_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8, PCLK_TCPWM1_CLOCKS8)}, + {P13_7, PWM_16b_11, CY_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11, PCLK_TCPWM1_CLOCKS11)}, + // 32-bit PWM outputs + {PWM32(P0_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P0_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)}, + {PWM32(P0_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)}, + {PWM32(P1_0), PWM_32b_3, CY_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)}, + {PWM32(P1_2), PWM_32b_4, CY_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)}, + {PWM32(P1_4), PWM_32b_5, CY_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)}, + {PWM32(P5_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)}, + {PWM32(P5_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)}, + {PWM32(P5_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)}, + {PWM32(P5_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)}, + {PWM32(P6_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P6_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)}, + {PWM32(P6_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)}, + {PWM32(P6_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)}, + {PWM32(P7_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)}, + {PWM32(P7_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)}, + {PWM32(P7_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)}, + {PWM32(P7_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)}, + {PWM32(P8_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P8_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)}, + {PWM32(P8_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)}, + {PWM32(P8_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)}, + {PWM32(P9_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)}, + {PWM32(P9_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)}, + {PWM32(P9_4), PWM_32b_7, CY_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)}, + {PWM32(P9_6), PWM_32b_0, CY_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P10_0), PWM_32b_6, CY_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)}, + {PWM32(P10_2), PWM_32b_7, CY_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)}, + {PWM32(P10_4), PWM_32b_0, CY_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P10_6), PWM_32b_1, CY_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)}, + {PWM32(P11_0), PWM_32b_1, CY_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)}, + {PWM32(P11_2), PWM_32b_2, CY_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)}, + {PWM32(P11_4), PWM_32b_3, CY_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)}, + {PWM32(P12_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)}, + {PWM32(P12_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)}, + {PWM32(P12_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)}, + {PWM32(P12_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)}, + {PWM32(P13_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P13_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)}, + // 32-bit PWM inverted outputs + {PWM32(P0_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P0_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)}, + {PWM32(P0_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)}, + {PWM32(P1_1), PWM_32b_3, CY_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)}, + {PWM32(P1_3), PWM_32b_4, CY_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)}, + {PWM32(P1_5), PWM_32b_5, CY_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)}, + {PWM32(P5_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)}, + {PWM32(P5_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)}, + {PWM32(P5_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)}, + {PWM32(P6_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P6_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)}, + {PWM32(P6_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)}, + {PWM32(P6_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)}, + {PWM32(P7_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)}, + {PWM32(P7_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)}, + {PWM32(P7_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)}, + {PWM32(P7_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)}, + {PWM32(P8_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P8_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)}, + {PWM32(P8_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)}, + {PWM32(P8_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)}, + {PWM32(P9_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)}, + {PWM32(P9_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)}, + {PWM32(P9_5), PWM_32b_7, CY_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)}, + {PWM32(P9_7), PWM_32b_0, CY_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P10_1), PWM_32b_6, CY_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)}, + {PWM32(P10_3), PWM_32b_7, CY_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)}, + {PWM32(P10_5), PWM_32b_0, CY_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P11_1), PWM_32b_1, CY_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)}, + {PWM32(P11_3), PWM_32b_2, CY_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)}, + {PWM32(P11_5), PWM_32b_3, CY_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)}, + {PWM32(P12_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)}, + {PWM32(P12_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)}, + {PWM32(P12_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)}, + {PWM32(P12_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)}, + {PWM32(P13_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, + {PWM32(P13_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)}, + {NC, NC, 0} +}; +#endif // DEVICE_PWMOUT + +#if DEVICE_ANALOGIN +const PinMap PinMap_ADC[] = { + {P10_0, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_1, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_2, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_3, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_4, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_5, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_6, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {P10_7, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN + +#if DEVICE_ANALOGOUT +const PinMap PinMap_DAC[] = { + {P9_6, DAC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_CTDAC)}, + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/PDL_Version.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/PDL_Version.txt new file mode 100644 index 0000000000..9cac515901 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/PDL_Version.txt @@ -0,0 +1,2 @@ +version 3.0.1 + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/README.md new file mode 100644 index 0000000000..c1a197bfb5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/README.md @@ -0,0 +1,5 @@ +README for Cypress Peripheral Driver Library +============================================ + +This folder tree contains parts (binary-only libraries and M0/M4 core specific files) of Cypress Peripheral Driver Library (PDL) necessary to support PSoC 6 MCUs. Library names have been changed (vs. standard PDL version) by prepending a "lib" prefix to fit Mbed OS build system conventions. +See [Cypress PDL page](http://www.cypress.com/documentation/software-and-drivers/peripheral-driver-library-pdl) for details. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm0plus.sct new file mode 100644 index 0000000000..603c453ebd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm0plus.sct @@ -0,0 +1,207 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm0plus.scat +;* \version 2.10 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* SPDX-License-Identifier: Apache-2.0 +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00010000 +; Flash +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00078000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +LR_IROM1 FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm0plus.S new file mode 100644 index 0000000000..53ac4e4a1d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm0plus.S @@ -0,0 +1,279 @@ +;/**************************************************************************//** +; * @file startup_psoc63_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +__initial_sp EQU 0x08010000 + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CM0 + NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0 + NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0 + NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0 + NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0 + NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0 + NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0 + NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0 + NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0 + NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0 + NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0 + NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0 + NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0 + NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0 + NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0 + NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0 + NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0 + NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0 + NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0 + NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0 + NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0 + NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0 + NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0 + NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0 + NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0 + NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0 + NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0 + NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0 + NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0 + NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0 + NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0 + NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0 + NVIC Mux input 31 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Saves and disables the interrupts +Cy_SaveIRQ PROC + EXPORT Cy_SaveIRQ + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + + +; Restores the interrupts +Cy_RestoreIRQ PROC + EXPORT Cy_RestoreIRQ + MSR PRIMASK, r0 + BX LR + ENDP + + +; Weak function for startup customization +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT NvicMux8_IRQHandler [WEAK] + EXPORT NvicMux9_IRQHandler [WEAK] + EXPORT NvicMux10_IRQHandler [WEAK] + EXPORT NvicMux11_IRQHandler [WEAK] + EXPORT NvicMux12_IRQHandler [WEAK] + EXPORT NvicMux13_IRQHandler [WEAK] + EXPORT NvicMux14_IRQHandler [WEAK] + EXPORT NvicMux15_IRQHandler [WEAK] + EXPORT NvicMux16_IRQHandler [WEAK] + EXPORT NvicMux17_IRQHandler [WEAK] + EXPORT NvicMux18_IRQHandler [WEAK] + EXPORT NvicMux19_IRQHandler [WEAK] + EXPORT NvicMux20_IRQHandler [WEAK] + EXPORT NvicMux21_IRQHandler [WEAK] + EXPORT NvicMux22_IRQHandler [WEAK] + EXPORT NvicMux23_IRQHandler [WEAK] + EXPORT NvicMux24_IRQHandler [WEAK] + EXPORT NvicMux25_IRQHandler [WEAK] + EXPORT NvicMux26_IRQHandler [WEAK] + EXPORT NvicMux27_IRQHandler [WEAK] + EXPORT NvicMux28_IRQHandler [WEAK] + EXPORT NvicMux29_IRQHandler [WEAK] + EXPORT NvicMux30_IRQHandler [WEAK] + EXPORT NvicMux31_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +NvicMux8_IRQHandler +NvicMux9_IRQHandler +NvicMux10_IRQHandler +NvicMux11_IRQHandler +NvicMux12_IRQHandler +NvicMux13_IRQHandler +NvicMux14_IRQHandler +NvicMux15_IRQHandler +NvicMux16_IRQHandler +NvicMux17_IRQHandler +NvicMux18_IRQHandler +NvicMux19_IRQHandler +NvicMux20_IRQHandler +NvicMux21_IRQHandler +NvicMux22_IRQHandler +NvicMux23_IRQHandler +NvicMux24_IRQHandler +NvicMux25_IRQHandler +NvicMux26_IRQHandler +NvicMux27_IRQHandler +NvicMux28_IRQHandler +NvicMux29_IRQHandler +NvicMux30_IRQHandler +NvicMux31_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld new file mode 100644 index 0000000000..d7a54e4af2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld @@ -0,0 +1,393 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm0plus.ld +* \version 2.10 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x10000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x78000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + + /* To copy multiple ROM to RAM sections, + * uncomment copy table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc63_cm4.S */ + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + + /* To clear multiple BSS sections, + * uncomment zero table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc63_cm4.S */ + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm0plus.S new file mode 100644 index 0000000000..00178a1aad --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm0plus.S @@ -0,0 +1,415 @@ +/**************************************************************************//** + * @file startup_psoc63_cm0plus.s + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */ + .long NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */ + .long NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */ + .long NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */ + .long NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */ + .long NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */ + .long NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */ + .long NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */ + .long NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */ + .long NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */ + .long NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */ + .long NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */ + .long NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */ + .long NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */ + .long NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */ + .long NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */ + .long NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */ + .long NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */ + .long NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */ + .long NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */ + .long NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */ + .long NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */ + .long NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */ + .long NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */ + .long NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */ + .long NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */ + .long NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */ + .long NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */ + .long NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */ + .long NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */ + .long NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */ + .long NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function +Cy_OnResetUser: + + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Saves and disables the interrupts */ + .global Cy_SaveIRQ + .func Cy_SaveIRQ, Cy_SaveIRQ + .type Cy_SaveIRQ, %function +Cy_SaveIRQ: + mrs r0, PRIMASK + cpsid i + bx lr + .size Cy_SaveIRQ, . - Cy_SaveIRQ + .endfunc + + /* Restores the interrupts */ + .global Cy_RestoreIRQ + .func Cy_RestoreIRQ, Cy_RestoreIRQ + .type Cy_RestoreIRQ, %function +Cy_RestoreIRQ: + msr PRIMASK, r0 + bx lr + .size Cy_RestoreIRQ, . - Cy_RestoreIRQ + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + bl Cy_OnResetUser + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + + + .type Fault_Handler, %function +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CM0 + NVIC Mux input 0 */ + def_irq_handler NvicMux1_IRQHandler /* CM0 + NVIC Mux input 1 */ + def_irq_handler NvicMux2_IRQHandler /* CM0 + NVIC Mux input 2 */ + def_irq_handler NvicMux3_IRQHandler /* CM0 + NVIC Mux input 3 */ + def_irq_handler NvicMux4_IRQHandler /* CM0 + NVIC Mux input 4 */ + def_irq_handler NvicMux5_IRQHandler /* CM0 + NVIC Mux input 5 */ + def_irq_handler NvicMux6_IRQHandler /* CM0 + NVIC Mux input 6 */ + def_irq_handler NvicMux7_IRQHandler /* CM0 + NVIC Mux input 7 */ + def_irq_handler NvicMux8_IRQHandler /* CM0 + NVIC Mux input 8 */ + def_irq_handler NvicMux9_IRQHandler /* CM0 + NVIC Mux input 9 */ + def_irq_handler NvicMux10_IRQHandler /* CM0 + NVIC Mux input 10 */ + def_irq_handler NvicMux11_IRQHandler /* CM0 + NVIC Mux input 11 */ + def_irq_handler NvicMux12_IRQHandler /* CM0 + NVIC Mux input 12 */ + def_irq_handler NvicMux13_IRQHandler /* CM0 + NVIC Mux input 13 */ + def_irq_handler NvicMux14_IRQHandler /* CM0 + NVIC Mux input 14 */ + def_irq_handler NvicMux15_IRQHandler /* CM0 + NVIC Mux input 15 */ + def_irq_handler NvicMux16_IRQHandler /* CM0 + NVIC Mux input 16 */ + def_irq_handler NvicMux17_IRQHandler /* CM0 + NVIC Mux input 17 */ + def_irq_handler NvicMux18_IRQHandler /* CM0 + NVIC Mux input 18 */ + def_irq_handler NvicMux19_IRQHandler /* CM0 + NVIC Mux input 19 */ + def_irq_handler NvicMux20_IRQHandler /* CM0 + NVIC Mux input 20 */ + def_irq_handler NvicMux21_IRQHandler /* CM0 + NVIC Mux input 21 */ + def_irq_handler NvicMux22_IRQHandler /* CM0 + NVIC Mux input 22 */ + def_irq_handler NvicMux23_IRQHandler /* CM0 + NVIC Mux input 23 */ + def_irq_handler NvicMux24_IRQHandler /* CM0 + NVIC Mux input 24 */ + def_irq_handler NvicMux25_IRQHandler /* CM0 + NVIC Mux input 25 */ + def_irq_handler NvicMux26_IRQHandler /* CM0 + NVIC Mux input 26 */ + def_irq_handler NvicMux27_IRQHandler /* CM0 + NVIC Mux input 27 */ + def_irq_handler NvicMux28_IRQHandler /* CM0 + NVIC Mux input 28 */ + def_irq_handler NvicMux29_IRQHandler /* CM0 + NVIC Mux input 29 */ + def_irq_handler NvicMux30_IRQHandler /* CM0 + NVIC Mux input 30 */ + def_irq_handler NvicMux31_IRQHandler /* CM0 + NVIC Mux input 31 */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf new file mode 100644 index 0000000000..f37c1d9718 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf @@ -0,0 +1,216 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm0plus.icf +* \version 2.10 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08010000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10078000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x4000; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + + +/*-Placement-*/ + +/* Flash */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/startup_psoc63_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/startup_psoc63_cm0plus.S new file mode 100644 index 0000000000..34ad737a3a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/startup_psoc63_cm0plus.S @@ -0,0 +1,417 @@ +;/**************************************************************************//** +; * @file startup_psoc63_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Power Mode Description + DCD NvicMux0_IRQHandler ; CM0 + NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0 + NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0 + NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0 + NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0 + NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0 + NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0 + NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0 + NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0 + NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0 + NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0 + NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0 + NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0 + NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0 + NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0 + NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0 + NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0 + NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0 + NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0 + NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0 + NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0 + NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0 + NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0 + NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0 + NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0 + NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0 + NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0 + NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0 + NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0 + NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0 + NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0 + NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0 + NVIC Mux input 31 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Saves and disables the interrupts +;; + PUBLIC Cy_SaveIRQ + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_SaveIRQ + MRS r0, PRIMASK + CPSID I + BX LR + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Restores the interrupts +;; + PUBLIC Cy_RestoreIRQ + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_RestoreIRQ + MSR PRIMASK, r0 + BX LR + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK NvicMux8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux8_IRQHandler + B NvicMux8_IRQHandler + + PUBWEAK NvicMux9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux9_IRQHandler + B NvicMux9_IRQHandler + + PUBWEAK NvicMux10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux10_IRQHandler + B NvicMux10_IRQHandler + + PUBWEAK NvicMux11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux11_IRQHandler + B NvicMux11_IRQHandler + + PUBWEAK NvicMux12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux12_IRQHandler + B NvicMux12_IRQHandler + + PUBWEAK NvicMux13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux13_IRQHandler + B NvicMux13_IRQHandler + + PUBWEAK NvicMux14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux14_IRQHandler + B NvicMux14_IRQHandler + + PUBWEAK NvicMux15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux15_IRQHandler + B NvicMux15_IRQHandler + + PUBWEAK NvicMux16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux16_IRQHandler + B NvicMux16_IRQHandler + + PUBWEAK NvicMux17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux17_IRQHandler + B NvicMux17_IRQHandler + + PUBWEAK NvicMux18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux18_IRQHandler + B NvicMux18_IRQHandler + + PUBWEAK NvicMux19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux19_IRQHandler + B NvicMux19_IRQHandler + + PUBWEAK NvicMux20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux20_IRQHandler + B NvicMux20_IRQHandler + + PUBWEAK NvicMux21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux21_IRQHandler + B NvicMux21_IRQHandler + + PUBWEAK NvicMux22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux22_IRQHandler + B NvicMux22_IRQHandler + + PUBWEAK NvicMux23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux23_IRQHandler + B NvicMux23_IRQHandler + + PUBWEAK NvicMux24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux24_IRQHandler + B NvicMux24_IRQHandler + + PUBWEAK NvicMux25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux25_IRQHandler + B NvicMux25_IRQHandler + + PUBWEAK NvicMux26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux26_IRQHandler + B NvicMux26_IRQHandler + + PUBWEAK NvicMux27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux27_IRQHandler + B NvicMux27_IRQHandler + + PUBWEAK NvicMux28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux28_IRQHandler + B NvicMux28_IRQHandler + + PUBWEAK NvicMux29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux29_IRQHandler + B NvicMux29_IRQHandler + + PUBWEAK NvicMux30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux30_IRQHandler + B NvicMux30_IRQHandler + + PUBWEAK NvicMux31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux31_IRQHandler + B NvicMux31_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/ipc_rpc_m0.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/ipc_rpc_m0.c new file mode 100644 index 0000000000..5757ab5cd6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/ipc_rpc_m0.c @@ -0,0 +1,38 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "psoc6_utils.h" +#include "ipc_rpc.h" +#include "rpc_defs.h" +#include "cy_ipc_config.h" +#include "ipc/cy_ipc_pipe.h" + +#define RPC_GEN RPC_GEN_IMPLEMENTATION +#include "rpc_api.h" +#undef RPC_GEN + + +void ipcrpc_init(void) +{ + uint32_t rpc_counter = 0; + +#define RPC_GEN RPC_GEN_INITIALIZATION +#include "rpc_api.h" +#undef RPC_GEN +} + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/system_psoc63_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/system_psoc63_cm0plus.c new file mode 100644 index 0000000000..ee1d0b227f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/system_psoc63_cm0plus.c @@ -0,0 +1,636 @@ +/***************************************************************************//** +* \file system_psoc63_cm0plus.c +* \version 2.10 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2017-2018, Future Electronics +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include +#include +#include "device.h" +#include "system_psoc63.h" +#include "cy_device_headers.h" +#include "ipc_rpc.h" +#include "psoc6_utils.h" + +#if defined(CY_DEVICE_PSOC6ABLE2) + #if !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) + #include "syslib/cy_syslib.h" + #endif /* !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "ipc/cy_ipc_drv.h" + #include "flash/cy_flash.h" + #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT CY_CLK_HFCLK0_FREQ_HZ + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT CY_CLK_PERICLK_FREQ_HZ + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT CY_CLK_SLOWCLK_FREQ_HZ + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) */ + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ +/* WDT lock bits */ +#define CY_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u) +#define CY_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u) + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() +*******************************************************************************/ +#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) +#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) + + +/******************************************************************************* +* Function Name: mbed_sdk_init +****************************************************************************//** +* +* Mbed's post-memory-initialization function. +* Used here to initialize common parts of the Cypress libraries. +* +*******************************************************************************/ +void mbed_sdk_init(void) +{ + /* Initialize shared resource manager */ + cy_srm_initialize(); + /* Initialize system and clocks. */ + /* Placed here as it must be done after proper LIBC initialization. */ + SystemInit(); + /* Allocate and initialize semaphores for the system operations. */ + Cy_IPC_SystemSemaInit(); + Cy_IPC_SystemPipeInit(); + Cy_Flash_Init(); + ipcrpc_init(); +} + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system: +* - Restores FLL registers to the default state. +* - Unlocks and disables WDT. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* +*******************************************************************************/ +void SystemInit(void) +{ + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_WDT_LOCK_BIT0); + SRSS->WDT_CTL = (SRSS->WDT_CTL | CY_WDT_LOCK_BIT1); + SRSS->WDT_CTL &= (~ (uint32_t) SRSS_WDT_CTL_WDT_EN_Msk); + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if defined(CY_DEVICE_PSOC6ABLE2) + #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + /* Allocate and initialize semaphores for the system operations. */ + Cy_IPC_SystemSemaInit(); + Cy_IPC_SystemPipeInit(); + Cy_Flash_Init(); + #endif /* CY_IPC_DEFAULT_CFG_DISABLE */ + + #if !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) + if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) + { + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + IPC_STRUCT7->DATA = 0UL; + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + IPC_STRUCT7->RELEASE = 0UL; + } + #endif /* !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ +#endif /* CY_DEVICE_PSOC6ABLE2 */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t slowClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if (rootPath == 1UL) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Slow Clock Divider */ + slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + pathFreqHz = pathFreqHz / periClkDiv; + cy_PeriClkFreqHz = pathFreqHz; + pathFreqHz = pathFreqHz / slowClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_SysGetCM4Status +****************************************************************************//** +* +* Returns the Cortex-M4 core power mode. +* +* \return \ref group_system_config_cm4_status_macro +* +*******************************************************************************/ +uint32_t Cy_SysGetCM4Status(void) +{ + uint32_t regValue; + + /* Get current power mode */ + regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; + + return (regValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysEnableCM4 +****************************************************************************//** +* +* Sets vector table base address and enables the Cortex-M4 core. +* +* \note If the CPU is already enabled, it is reset and then enabled. +* +* \param vectorTableOffset The offset of the vector table base address from +* memory address 0x00000000. The offset should be multiple to 1024 bytes. +* +*******************************************************************************/ +void Cy_SysEnableCM4(uint32_t vectorTableOffset) +{ + uint32_t regValue; + uint32_t interruptState; + uint32_t cpuState; + + interruptState = Cy_SaveIRQ(); + + cpuState = Cy_SysGetCM4Status(); + if (CY_SYS_CM4_STATUS_ENABLED == cpuState) + { + Cy_SysResetCM4(); + } + + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_ENABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_RestoreIRQ(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysDisableCM4 +****************************************************************************//** +* +* Disables the Cortex-M4 core and waits for the mode to take the effect. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the +* CPU. +* +*******************************************************************************/ +void Cy_SysDisableCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SaveIRQ(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_DISABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_RestoreIRQ(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysRetainCM4 +****************************************************************************//** +* +* Retains the Cortex-M4 core and exists without waiting for the mode to take +* effect. +* +* \note The retained mode can be entered only from the enabled mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysRetainCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SaveIRQ(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RETAINED; + CPUSS->CM4_PWR_CTL = regValue; + + Cy_RestoreIRQ(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysResetCM4 +****************************************************************************//** +* +* Resets the Cortex-M4 core and waits for the mode to take the effect. +* +* \note The reset mode can not be entered from the retained mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysResetCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SaveIRQ(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RESET; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_RestoreIRQ(interruptState); +} +#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/PDL_Version.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/PDL_Version.txt new file mode 100644 index 0000000000..9cac515901 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/PDL_Version.txt @@ -0,0 +1,2 @@ +version 3.0.1 + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/README.md new file mode 100644 index 0000000000..c1a197bfb5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/README.md @@ -0,0 +1,5 @@ +README for Cypress Peripheral Driver Library +============================================ + +This folder tree contains parts (binary-only libraries and M0/M4 core specific files) of Cypress Peripheral Driver Library (PDL) necessary to support PSoC 6 MCUs. Library names have been changed (vs. standard PDL version) by prepending a "lib" prefix to fit Mbed OS build system conventions. +See [Cypress PDL page](http://www.cypress.com/documentation/software-and-drivers/peripheral-driver-library-pdl) for details. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm4_dual.sct new file mode 100644 index 0000000000..5316a1df7e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm4_dual.sct @@ -0,0 +1,212 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.scat +;* \version 2.10 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* SPDX-License-Identifier: Apache-2.0 +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +; RAM +#define RAM_START 0x08010000 +#define RAM_SIZE 0x00037800 +; Flash +; Flash +#define FLASH_START 0x10080000 +#define FLASH_SIZE 0x00078000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK appication. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm4.S new file mode 100644 index 0000000000..c31adadbef --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm4.S @@ -0,0 +1,654 @@ +;/**************************************************************************//** +; * @file startup_psoc63_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +__initial_sp EQU 0x08047800 + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Power Mode Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Saves and disables the interrupts +Cy_SaveIRQ PROC + EXPORT Cy_SaveIRQ + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + + +; Restores the interrupts +Cy_RestoreIRQ PROC + EXPORT Cy_RestoreIRQ + MSR PRIMASK, r0 + BX LR + ENDP + + +; Weak function for startup customization +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld new file mode 100644 index 0000000000..0ecc9d77ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -0,0 +1,399 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.ld +* \version 2.10 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08010000, LENGTH = 0x37800 + flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x78000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + + /* To copy multiple ROM to RAM sections, + * uncomment copy table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc63_cm4.S */ + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + + /* To clear multiple BSS sections, + * uncomment zero table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc63_cm4.S */ + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK appication. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm4.S new file mode 100644 index 0000000000..6deba77053 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/startup_psoc63_cm4.S @@ -0,0 +1,641 @@ +/**************************************************************************//** + * @file startup_psoc63_cm4.s + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Saves and disables the interrupts */ + .global Cy_SaveIRQ + .func Cy_SaveIRQ, Cy_SaveIRQ + .type Cy_SaveIRQ, %function +Cy_SaveIRQ: + mrs r0, PRIMASK + cpsid i + bx lr + .size Cy_SaveIRQ, . - Cy_SaveIRQ + .endfunc + + /* Restores the interrupts */ + .global Cy_RestoreIRQ + .func Cy_RestoreIRQ, Cy_RestoreIRQ + .type Cy_RestoreIRQ, %function +Cy_RestoreIRQ: + msr PRIMASK, r0 + bx lr + .size Cy_RestoreIRQ, . - Cy_RestoreIRQ + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + bl Cy_OnResetUser + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + + .type Fault_Handler, %function +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf new file mode 100644 index 0000000000..02c7e76ee0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -0,0 +1,217 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.icf +* \version 2.10 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08010000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x100F8000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x3800; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + + +/*-Placement-*/ + +/* Flash */ +place at start of IROM1_region { block RO }; +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/startup_psoc63_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/startup_psoc63_cm4.S new file mode 100644 index 0000000000..e6329ba27a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/startup_psoc63_cm4.S @@ -0,0 +1,1148 @@ +;/**************************************************************************//** +; * @file startup_psoc63_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN Cy_SystemInitFpuEnable + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Saves and disables the interrupts +;; + PUBLIC Cy_SaveIRQ + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_SaveIRQ + MRS r0, PRIMASK + CPSID I + BX LR + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Restores the interrupts +;; + PUBLIC Cy_RestoreIRQ + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_RestoreIRQ + MSR PRIMASK, r0 + BX LR + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #1 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK bless_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +bless_interrupt_IRQHandler + B bless_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK udb_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_0_IRQHandler + B udb_interrupts_0_IRQHandler + + PUBWEAK udb_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_1_IRQHandler + B udb_interrupts_1_IRQHandler + + PUBWEAK udb_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_2_IRQHandler + B udb_interrupts_2_IRQHandler + + PUBWEAK udb_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_3_IRQHandler + B udb_interrupts_3_IRQHandler + + PUBWEAK udb_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_4_IRQHandler + B udb_interrupts_4_IRQHandler + + PUBWEAK udb_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_5_IRQHandler + B udb_interrupts_5_IRQHandler + + PUBWEAK udb_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_6_IRQHandler + B udb_interrupts_6_IRQHandler + + PUBWEAK udb_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_7_IRQHandler + B udb_interrupts_7_IRQHandler + + PUBWEAK udb_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_8_IRQHandler + B udb_interrupts_8_IRQHandler + + PUBWEAK udb_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_9_IRQHandler + B udb_interrupts_9_IRQHandler + + PUBWEAK udb_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_10_IRQHandler + B udb_interrupts_10_IRQHandler + + PUBWEAK udb_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_11_IRQHandler + B udb_interrupts_11_IRQHandler + + PUBWEAK udb_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_12_IRQHandler + B udb_interrupts_12_IRQHandler + + PUBWEAK udb_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_13_IRQHandler + B udb_interrupts_13_IRQHandler + + PUBWEAK udb_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_14_IRQHandler + B udb_interrupts_14_IRQHandler + + PUBWEAK udb_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_15_IRQHandler + B udb_interrupts_15_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_i2s_IRQHandler + B audioss_interrupt_i2s_IRQHandler + + PUBWEAK audioss_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_pdm_IRQHandler + B audioss_interrupt_pdm_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/LICENSE.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/LICENSE.txt new file mode 100644 index 0000000000..4ac41bfc74 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/LICENSE.txt @@ -0,0 +1,52 @@ +Copyright (c) 2017-2018 Future Electronics. +Copyright (c) 2007-2018 Cypress Semiconductor. + +Permissive Binary License + +Version 1.0, September 2015 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named "DEPENDENCIES" and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/README.md new file mode 100644 index 0000000000..abd8627062 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/README.md @@ -0,0 +1,16 @@ +README for pre-compiled PSoC 6 Cortex M0+ core images +===================================================== + +This folder contains precompiled program images for the CM0+ core of the PSoC 6(63xx) MCU suitable for use with MBed OS applications running on CM4 core. Two images are available: + +* `psoc63_m0_default_1.01.hex` + + This image contains basic code, that brings up the chip, starts CM4 core and puts CM0+ core into a deep sleep. It is suitable for use with all Mbed applications except those intendif to use BLE feature. + +* `psoc63_m0_ble_controller_1.01.hex` + + This image brings up the chip, starts CM4 core and runs BLE HCI controller for the build-in BLE device. This image is suitable for use with Mbed BLE applications. + +The images are 'bare metal' code prepared with Cypress PSoC Creator IDE and are toolchain agnostic, i.e. can be used with CM4 Mbed applications build with any supported toolchain. + +**These images were prepared by Future Electronics and are made available under the conditions of Permissive Binary Licence, see file LICENSE.txt** diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_ble_controller_1.01.hex b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_ble_controller_1.01.hex new file mode 100644 index 0000000000..3942055ebc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_ble_controller_1.01.hex @@ -0,0 +1,1655 @@ +:020000041000EA +:4000000000000108310100100D00000095010010000000000000000000000000000000000000000000000000000000009101001000000000000000009101001091010010DC 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+:40230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009D +:40234000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005D +:40238000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001D +:4023C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000DD +:0200000490303A +:02000000121CD0 +:0200000490501A +:0C0000000005E20721002101E212331C80 +:00000001FF \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/ipc_rpc.cpp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/ipc_rpc.cpp new file mode 100644 index 0000000000..c331b23adc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/ipc_rpc.cpp @@ -0,0 +1,108 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ipc_rpc.h" +#include "Mutex.h" +#include "Semaphore.h" +#include "mbed_assert.h" +#include "cy_ipc_config.h" +#include "ipc/cy_ipc_pipe.h" +#include +#include "platform/SingletonPtr.h" + +using namespace rtos; + + +static SingletonPtr msg_mutex; +static SingletonPtr msg_semaphore; + + +#define RPC_GEN RPC_GEN_INTERFACE_IDS +#include "rpc_api.h" +#undef RPC_GEN + +// This function uses a "C" linkage as it is a callback called from Cypress library +// which is C-only. +extern "C" void ipcrpc_release(void); +void ipcrpc_release(void) +{ + // Just signal on semaphore that we are done with a call. + msg_semaphore->release(); +} + +// Encapsulate call arguments and send a message over IPC pipe to the +// other core for execution. +uint32_t ipcrpc_call(uint32_t call_id, uint32_t args_num, ...) +{ + va_list ap; + static IpcRpcMessage message; + cy_en_ipc_pipe_status_t status; + ScopedMutexLock lock(*msg_mutex.get()); + + // Make sure semaphore is initialized. + (void)msg_semaphore.get(); + + // Copy data to the buffer. + message.client_id = call_id; + message.args_num = args_num; + message.result = 0; // default result + + va_start(ap, args_num); + for (uint32_t i = 0; i < args_num; ++i) { + message.args[i] = va_arg (ap, uint32_t); + } + va_end (ap); + + // send message + status = Cy_IPC_Pipe_SendMessage(CY_IPC_EP_RPCPIPE_DEST, + CY_IPC_EP_RPCPIPE_ADDR, + &message, + ipcrpc_release); + // We are using dedicated IPC channel here and have locked global mutex + // so this had to succeed. + MBED_ASSERT(status == CY_IPC_PIPE_SUCCESS); + + // Now wait for the response; + msg_semaphore->wait(); + + return message.result; +} + +extern "C" { + + void ipcrpc_init(void) + { + uint32_t rpc_counter = 0; +#define RPC_GEN RPC_GEN_INTERFACE_IDS_INIT +#include "rpc_api.h" +#undef RPC_GEN + } + + +#define RPC_GEN RPC_GEN_INTERFACE +#include "rpc_api.h" +#undef RPC_GEN + + +#define RPC_GEN RPC_GEN_IMPLEMENTATION +#include "rpc_api.h" +#undef RPC_GEN + + +} /* extern "C" */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/system_psoc63_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/system_psoc63_cm4.c new file mode 100644 index 0000000000..384c287f5a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/system_psoc63_cm4.c @@ -0,0 +1,461 @@ +/***************************************************************************//** +* \file system_psoc63_cm4.c +* \version 2.10 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2017-2018, Future Electronics +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include +#include +#include "device.h" +#include "system_psoc63.h" +#include "cy_device_headers.h" +#include "ipc_rpc.h" +#include "psoc6_utils.h" + +#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "ipc/cy_ipc_drv.h" + #include "flash/cy_flash.h" +#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT CY_CLK_HFCLK0_FREQ_HZ + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT CY_CLK_PERICLK_FREQ_HZ + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT CY_CLK_HFCLK0_FREQ_HZ + + +/* +* Holds the FastClk system core clock, which is the system clock frequency +* supplied to the SysTick timer and the processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + /** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ +/* WDT lock bits */ +#define CY_WDT_LOCK_BIT0 ((uint32_t)0x01u << 30u) +#define CY_WDT_LOCK_BIT1 ((uint32_t)0x01u << 31u) + +#if (__CM0P_PRESENT == 0) + /* CLK_FLL_CONFIG default values */ + #define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) + #define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) + #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) + #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) +#endif /* (__CM0P_PRESENT == 0) */ + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ +#if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; +#endif /* (__CM0P_PRESENT == 0) */ + + /* Unlock and disable WDT */ + SRSS->WDT_CTL = ((SRSS->WDT_CTL & (uint32_t)(~SRSS_WDT_CTL_WDT_LOCK_Msk)) | CY_WDT_LOCK_BIT0); + SRSS->WDT_CTL = (SRSS->WDT_CTL | CY_WDT_LOCK_BIT1); + SRSS->WDT_CTL &= (~ (uint32_t) SRSS_WDT_CTL_WDT_EN_Msk); + + Cy_SystemInit(); + SystemCoreClockUpdate(); +} + + +/******************************************************************************* +* Function Name: mbed_sdk_init +****************************************************************************//** +* +* Mbed's post-memory-initialization function. +* Used here to initialize common parts of the Cypress libraries. +* +*******************************************************************************/ +void mbed_sdk_init(void) +{ + /* Initialize shared resource manager */ + cy_srm_initialize(); + /* Initialize system and clocks. */ + /* Placed here as it must be done after proper LIBC initialization. */ + SystemInit(); + /* Allocate and initialize semaphores for the system operations. */ + Cy_IPC_SystemSemaInit(); + Cy_IPC_SystemPipeInit(); + Cy_Flash_Init(); + ipcrpc_init(); +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if (rootPath == 1UL) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SaveIRQ(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_RestoreIRQ(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device.h new file mode 100644 index 0000000000..0ef546175a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device.h @@ -0,0 +1,81 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +/*----------------------------------------------------------------------------*/ +/** Config options. */ +/*----------------------------------------------------------------------------*/ +/** ALTHF (BLE ECO) frequency in Hz */ +#define CYDEV_CLK_ALTHF__HZ ( 8000000UL) + +/*----------------------------------------------------------------------------*/ + +#include "cmsis.h" +#include "objects.h" + +/* + * Board clocks. + */ +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ ( 8000000UL) +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ ( 32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ ( 32768UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ ( 32000UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ ( 32768UL) + +/** Default HFClk frequency in Hz */ +#ifndef CY_CLK_HFCLK0_FREQ_HZ +#define CY_CLK_HFCLK0_FREQ_HZ (100000000UL) +#endif + +/** Default PeriClk frequency in Hz */ +#ifndef CY_CLK_PERICLK_FREQ_HZ +#define CY_CLK_PERICLK_FREQ_HZ (CY_CLK_HFCLK0_FREQ_HZ / 2) +#endif + +/** Default SlowClk system core frequency in Hz */ +#ifndef CY_CLK_SYSTEM_FREQ_HZ +#define CY_CLK_SYSTEM_FREQ_HZ (CY_CLK_PERICLK_FREQ_HZ) +#endif + + +/** Interrupt assignment for CM0+ core. + * On PSoC6 CM0+ core physical interrupt are routed into NVIC through a programmable + * multiplexer. This requires that we define which of the 32 NVIC channels is used + * by which interrupt. This is done here. + */ +#define CY_M0_CORE_IRQ_CHANNEL_US_TICKER ((IRQn_Type)0) +#define CY_M0_CORE_IRQ_CHANNEL_SERIAL ((IRQn_Type)4) +#define CY_M0_CORE_IRQ_CHANNEL_BLE ((IRQn_Type)3) + +/** Identifiers used in allocation of NVIC channels. + */ +#define CY_US_TICKER_IRQN_ID (0x100) +#define CY_SERIAL_IRQN_ID (0x200) +#define CY_BLE_IRQN_ID (0x300) +#define CY_GPIO_IRQN_ID (0x400) +#define CY_LP_TICKER_IRQN_ID (0x500) +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cmsis.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cmsis.h new file mode 100644 index 0000000000..6a55fa317e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cmsis.h @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "cy_device_headers.h" +#undef BLE + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h new file mode 100644 index 0000000000..13745170e8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h @@ -0,0 +1,1280 @@ +/***************************************************************************//** +* \file cy8c6347bzi_bld53.h +* +* \brief +* CY8C6347BZI-BLD53 device header +* +* \note +* Generator version: 1.2.0.117 +* Database revision: rev#1034984 +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#ifndef _CY8C6347BZI_BLD53_H_ +#define _CY8C6347BZI_BLD53_H_ + +/** +* \addtogroup group_device CY8C6347BZI-BLD53 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* ARM Cortex-M0+ NVIC Mux inputs. Allow routing of device interrupts to the CM0+ NVIC */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */ + NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */ + NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */ + NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */ + NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */ + NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */ + NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */ + NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */ + NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */ + NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */ + NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */ + NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */ + NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */ + NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */ + NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */ + NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */ + NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */ + NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */ + NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */ + NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */ + NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */ + NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */ + NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */ + NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */ + NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6347BZI-BLD53 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + unconnected_IRQn = 240 /*!< 240 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6347BZI-BLD53 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */ + bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */ + cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */ + csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */ + udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */ + udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */ + udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */ + udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */ + udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */ + udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */ + udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */ + udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */ + udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */ + udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */ + udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */ + udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */ + udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */ + udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */ + udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */ + udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */ + pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */ + audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */ + audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */ + profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + disconnected_IRQn = 240 /*!< 240 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_psoc63.h" /*!< PSoC 63 System */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_psoc63.h" /*!< PSoC 63 System */ + +#endif + +#include "psoc63_config.h" +#include "gpio_psoc63_116_bga_ble.h" + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00020000UL +#define CY_SRAM0_BASE 0x08000000UL +#define CY_SRAM0_SIZE 0x00048000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00100000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x000000C8UL + +#define CY_DEVICE_PSOC6ABLE2 +#define CY_SILICON_ID 0xE2072100UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL +#define SCB_GET_EZ_DATA_NR(base) 256u +#define SCB_IS_I2C_SLAVE_CAPABLE(base) true +#define SCB_IS_I2C_MASTER_CAPABLE(base) ((base) != SCB8) +#define SCB_IS_I2C_DS_CAPABLE(base) ((base) == SCB8) +#define SCB_IS_SPI_SLAVE_CAPABLE(base) true +#define SCB_IS_SPI_MASTER_CAPABLE(base) ((base) != SCB8) +#define SCB_IS_SPI_DS_CAPABLE(base) ((base) == SCB8) +#define SCB_IS_UART_CAPABLE(base) ((base) != SCB8) + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 9u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 1u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 1u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 1u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 1u +#define CY_IP_MXBLESS 1u +#define CY_IP_MXBLESS_INSTANCES 1u +#define CY_IP_MXBLESS_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 1u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 16u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40PASS_CTDAC 1u +#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u +#define CY_IP_MXS40PASS_CTDAC_VERSION 1u +#define CY_IP_MXS40PASS_CTB 1u +#define CY_IP_MXS40PASS_CTB_INSTANCES 1u +#define CY_IP_MXS40PASS_CTB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXUDB 1u +#define CY_IP_MXUDB_INSTANCES 1u +#define CY_IP_MXUDB_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +/* Include IP definitions */ +#include "cyip_sflash.h" +#include "cyip_peri.h" +#include "cyip_crypto.h" +#include "cyip_cpuss.h" +#include "cyip_fault.h" +#include "cyip_ipc.h" +#include "cyip_prot.h" +#include "cyip_flashc.h" +#include "cyip_srss.h" +#include "cyip_backup.h" +#include "cyip_dw.h" +#include "cyip_efuse.h" +#include "cyip_efuse_data.h" +#include "cyip_profile.h" +#include "cyip_hsiom.h" +#include "cyip_gpio.h" +#include "cyip_smartio.h" +#include "cyip_udb.h" +#include "cyip_lpcomp.h" +#include "cyip_csd.h" +#include "cyip_tcpwm.h" +#include "cyip_lcd.h" +#include "cyip_ble.h" +#include "cyip_smif.h" +#include "cyip_scb.h" +#include "cyip_ctbm.h" +#include "cyip_ctdac.h" +#include "cyip_sar.h" +#include "cyip_pass.h" +#include "cyip_i2s.h" +#include "cyip_pdm.h" + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40010000UL +#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL +#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL +#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL +#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL +#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL +#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL +#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL +#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL +#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL +#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL +#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL +#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL +#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL +#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL +#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL +#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL +#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL +#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL +#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL +#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL +#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL +#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL +#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL +#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL +#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL +#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL +#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL +#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL +#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL +#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL +#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL +#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL +#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL +#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL +#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL +#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL +#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL +#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL +#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL +#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL +#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL +#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL +#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL +#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL +#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL +#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL +#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL +#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL +#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL +#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL +#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL +#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL +#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL +#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL +#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL +#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL +#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL +#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL +#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL +#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL +#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL +#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL +#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL +#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */ +#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */ +#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */ +#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */ +#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */ +#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */ +#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */ +#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */ +#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */ +#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */ +#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */ +#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */ +#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */ +#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */ +#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */ +#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */ +#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */ +#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */ +#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */ +#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */ +#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */ +#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */ +#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */ +#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */ +#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */ +#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */ +#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */ +#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */ +#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */ +#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */ +#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */ +#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */ +#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */ +#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */ +#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */ +#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */ +#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */ +#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */ +#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */ +#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */ +#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */ +#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */ +#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */ +#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */ +#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */ +#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */ +#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */ +#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */ +#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */ +#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */ +#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */ +#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */ +#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */ +#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */ +#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */ +#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */ +#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */ +#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */ +#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */ +#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */ +#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */ +#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */ +#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */ +#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */ +#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */ +#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */ +#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */ +#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */ +#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */ +#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */ +#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */ +#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */ +#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */ +#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */ +#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */ +#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */ +#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */ +#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */ +#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */ +#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */ +#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */ +#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */ +#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */ +#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */ +#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */ +#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */ +#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */ +#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */ +#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */ +#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */ +#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */ +#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */ +#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */ +#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */ +#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */ +#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40110000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40210000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40220000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40230000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40240000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */ +#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */ +#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */ +#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */ +#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */ +#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */ +#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */ +#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */ +#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40250000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40281000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40310000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40320000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40330000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */ + +/******************************************************************************* +* UDB +*******************************************************************************/ + +#define UDB_BASE 0x40340000UL +#define UDB ((UDB_Type*) UDB_BASE) /* 0x40340000 */ +#define UDB_WRKONE ((UDB_WRKONE_Type*) &UDB->WRKONE) /* 0x40340000 */ +#define UDB_WRKMULT ((UDB_WRKMULT_Type*) &UDB->WRKMULT) /* 0x40341000 */ +#define UDB_UDBPAIR0_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[0]) /* 0x40342000 */ +#define UDB_UDBPAIR0_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[0].UDBSNG[1]) /* 0x40342080 */ +#define UDB_UDBPAIR1_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[0]) /* 0x40342200 */ +#define UDB_UDBPAIR1_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[1].UDBSNG[1]) /* 0x40342280 */ +#define UDB_UDBPAIR2_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[0]) /* 0x40342400 */ +#define UDB_UDBPAIR2_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[2].UDBSNG[1]) /* 0x40342480 */ +#define UDB_UDBPAIR3_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[0]) /* 0x40342600 */ +#define UDB_UDBPAIR3_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[3].UDBSNG[1]) /* 0x40342680 */ +#define UDB_UDBPAIR4_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[0]) /* 0x40342800 */ +#define UDB_UDBPAIR4_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[4].UDBSNG[1]) /* 0x40342880 */ +#define UDB_UDBPAIR5_UDBSNG0 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[0]) /* 0x40342A00 */ +#define UDB_UDBPAIR5_UDBSNG1 ((UDB_UDBPAIR_UDBSNG_Type*) &UDB->UDBPAIR[5].UDBSNG[1]) /* 0x40342A80 */ +#define UDB_UDBPAIR0_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[0].ROUTE) /* 0x40342100 */ +#define UDB_UDBPAIR1_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[1].ROUTE) /* 0x40342300 */ +#define UDB_UDBPAIR2_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[2].ROUTE) /* 0x40342500 */ +#define UDB_UDBPAIR3_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[3].ROUTE) /* 0x40342700 */ +#define UDB_UDBPAIR4_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[4].ROUTE) /* 0x40342900 */ +#define UDB_UDBPAIR5_ROUTE ((UDB_UDBPAIR_ROUTE_Type*) &UDB->UDBPAIR[5].ROUTE) /* 0x40342B00 */ +#define UDB_UDBPAIR0 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[0]) /* 0x40342000 */ +#define UDB_UDBPAIR1 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[1]) /* 0x40342200 */ +#define UDB_UDBPAIR2 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[2]) /* 0x40342400 */ +#define UDB_UDBPAIR3 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[3]) /* 0x40342600 */ +#define UDB_UDBPAIR4 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[4]) /* 0x40342800 */ +#define UDB_UDBPAIR5 ((UDB_UDBPAIR_Type*) &UDB->UDBPAIR[5]) /* 0x40342A00 */ +#define UDB_DSI0 ((UDB_DSI_Type*) &UDB->DSI[0]) /* 0x40346000 */ +#define UDB_DSI1 ((UDB_DSI_Type*) &UDB->DSI[1]) /* 0x40346080 */ +#define UDB_DSI2 ((UDB_DSI_Type*) &UDB->DSI[2]) /* 0x40346100 */ +#define UDB_DSI3 ((UDB_DSI_Type*) &UDB->DSI[3]) /* 0x40346180 */ +#define UDB_DSI4 ((UDB_DSI_Type*) &UDB->DSI[4]) /* 0x40346200 */ +#define UDB_DSI5 ((UDB_DSI_Type*) &UDB->DSI[5]) /* 0x40346280 */ +#define UDB_DSI6 ((UDB_DSI_Type*) &UDB->DSI[6]) /* 0x40346300 */ +#define UDB_DSI7 ((UDB_DSI_Type*) &UDB->DSI[7]) /* 0x40346380 */ +#define UDB_DSI8 ((UDB_DSI_Type*) &UDB->DSI[8]) /* 0x40346400 */ +#define UDB_DSI9 ((UDB_DSI_Type*) &UDB->DSI[9]) /* 0x40346480 */ +#define UDB_DSI10 ((UDB_DSI_Type*) &UDB->DSI[10]) /* 0x40346500 */ +#define UDB_DSI11 ((UDB_DSI_Type*) &UDB->DSI[11]) /* 0x40346580 */ +#define UDB_PA0 ((UDB_PA_Type*) &UDB->PA[0]) /* 0x40347000 */ +#define UDB_PA1 ((UDB_PA_Type*) &UDB->PA[1]) /* 0x40347040 */ +#define UDB_PA2 ((UDB_PA_Type*) &UDB->PA[2]) /* 0x40347080 */ +#define UDB_PA3 ((UDB_PA_Type*) &UDB->PA[3]) /* 0x403470C0 */ +#define UDB_PA4 ((UDB_PA_Type*) &UDB->PA[4]) /* 0x40347100 */ +#define UDB_PA5 ((UDB_PA_Type*) &UDB->PA[5]) /* 0x40347140 */ +#define UDB_PA6 ((UDB_PA_Type*) &UDB->PA[6]) /* 0x40347180 */ +#define UDB_PA7 ((UDB_PA_Type*) &UDB->PA[7]) /* 0x403471C0 */ +#define UDB_PA8 ((UDB_PA_Type*) &UDB->PA[8]) /* 0x40347200 */ +#define UDB_PA9 ((UDB_PA_Type*) &UDB->PA[9]) /* 0x40347240 */ +#define UDB_PA10 ((UDB_PA_Type*) &UDB->PA[10]) /* 0x40347280 */ +#define UDB_PA11 ((UDB_PA_Type*) &UDB->PA[11]) /* 0x403472C0 */ +#define UDB_BCTL ((UDB_BCTL_Type*) &UDB->BCTL) /* 0x40347800 */ +#define UDB_UDBIF ((UDB_UDBIF_Type*) &UDB->UDBIF) /* 0x40347900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* BLE +*******************************************************************************/ + +#define BLE_BASE 0x403C0000UL +#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */ +#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */ +#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */ +#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */ +#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40610000UL +#define SCB1_BASE 0x40620000UL +#define SCB2_BASE 0x40630000UL +#define SCB3_BASE 0x40640000UL +#define SCB4_BASE 0x40650000UL +#define SCB5_BASE 0x40660000UL +#define SCB6_BASE 0x40670000UL +#define SCB7_BASE 0x40680000UL +#define SCB8_BASE 0x40690000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x41100000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x41100000 */ + +/******************************************************************************* +* CTDAC +*******************************************************************************/ + +#define CTDAC0_BASE 0x41140000UL +#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x411D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x411F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x42A10000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x42A20000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */ + +/* Backward compabitility definitions */ +#define I2S I2S0 +#define PDM PDM0 + +/** \} CY8C6347BZI-BLD53 */ + +#endif /* _CY8C6347BZI_BLD53_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_device_headers.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_device_headers.h new file mode 100644 index 0000000000..7225333329 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_device_headers.h @@ -0,0 +1,69 @@ +/***************************************************************************//** +* \file cy_device_headers.h +* +* \brief +* Common header file to be included by the drivers. +* +* \note +* Generator version: 1.2.0.117 +* Database revision: rev#1034984 +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#ifndef _CY_DEVICE_HEADERS_H_ +#define _CY_DEVICE_HEADERS_H_ + +#if defined (CY8C6336BZI_BLF03) + #include "cy8c6336bzi_blf03.h" +#elif defined (CY8C6316BZI_BLF03) + #include "cy8c6316bzi_blf03.h" +#elif defined (CY8C6316BZI_BLF53) + #include "cy8c6316bzi_blf53.h" +#elif defined (CY8C6336BZI_BLD13) + #include "cy8c6336bzi_bld13.h" +#elif defined (CY8C6347BZI_BLD43) + #include "cy8c6347bzi_bld43.h" +#elif defined (CY8C6347BZI_BLD33) + #include "cy8c6347bzi_bld33.h" +#elif defined (CY8C6347BZI_BLD53) + #include "cy8c6347bzi_bld53.h" +#elif defined (CY8C6347FMI_BLD13) + #include "cy8c6347fmi_bld13.h" +#elif defined (CY8C6347FMI_BLD43) + #include "cy8c6347fmi_bld43.h" +#elif defined (CY8C6347FMI_BLD33) + #include "cy8c6347fmi_bld33.h" +#elif defined (CY8C6347FMI_BLD53) + #include "cy8c6347fmi_bld53.h" +#elif defined (CY8C637BZI_MD76) + #include "cy8c637bzi_md76.h" +#elif defined (CY8C637BZI_BLD74) + #include "cy8c637bzi_bld74.h" +#elif defined (CY8C637FMI_BLD73) + #include "cy8c637fmi_bld73.h" +#elif defined (CY8C68237BZ_BLE) + #include "cy8c68237bz_ble.h" +#elif defined (CY8C68237FM_BLE) + #include "cy8c68237fm_ble.h" +#elif defined (CY8C6336BZI_BUD13) + #include "cy8c6336bzi_bud13.h" +#elif defined (CY8C6347BZI_BUD43) + #include "cy8c6347bzi_bud43.h" +#elif defined (CY8C6347BZI_BUD33) + #include "cy8c6347bzi_bud33.h" +#elif defined (CY8C6347BZI_BUD53) + #include "cy8c6347bzi_bud53.h" +#elif defined (CY8C6337BZI_BLF13) + #include "cy8c6337bzi_blf13.h" +#else + #error Undefined part number +#endif + +#endif /* _CY_DEVICE_HEADERS_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.c new file mode 100644 index 0000000000..1394c20dbe --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.c @@ -0,0 +1,190 @@ +/***************************************************************************//** +* \file cy_ipc_config.c +* \version 1.10.1 +* +* Description: +* This C file is not intended to be part of the IPC driver. It is the code +* required to configure the device specific IPC channels for semaphores +* and pipes. +* +******************************************************************************** +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "ipc/cy_ipc_drv.h" +#include "ipc/cy_ipc_pipe.h" +#include "ipc/cy_ipc_sema.h" + +#include "cy_ipc_config.h" + +/* Create an array of endpoint structures */ +static cy_stc_ipc_pipe_ep_t cy_ipc_pipe_sysEpArray[CY_IPC_MAX_ENDPOINTS]; + +#define CY_CYPIPE_DEFAULT_CONFIG \ +{\ + /* .ep0ConfigData */ {\ + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,\ + /* .ipcNotifierPriority */ CY_IPC_INTR_CYPIPE_PRIOR_EP0,\ + /* .ipcNotifierMuxNumber */ CY_IPC_INTR_CYPIPE_MUX_EP0,\ + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,\ + /* .epConfig */ CY_IPC_CYPIPE_CONFIG_EP0\ + },\ + /* .ep1ConfigData */ {\ + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,\ + /* .ipcNotifierPriority */ CY_IPC_INTR_CYPIPE_PRIOR_EP1,\ + /* .ipcNotifierMuxNumber */ 0u,\ + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,\ + /* .epConfig */ CY_IPC_CYPIPE_CONFIG_EP1\ + },\ + /* .endpointClientsCount */ CY_IPC_CYPIPE_CLIENT_CNT,\ + /* .endpointsCallbacksArray */ cy_ipc_pipe_sysCbArray,\ + /* .userPipeIsrHandler */ &Cy_IPC_SystemPipeIsr\ +} + + + +/******************************************************************************* +* Function Name: Cy_IPC_SystemSemaInit +****************************************************************************//** +* +* Initializes the system semaphores. The system semaphores are used by Flash. +* +* This function is called in the SystemInit() function. If the default startup +* file is not used, or SystemInit() is not called in your project, +* call the following three functions prior to executing any flash or EmEEPROM +* write or erase operation: +* -# Cy_IPC_SystemSemaInit() +* -# Cy_IPC_SystemPipeInit() +* -# Cy_Flash_Init() +* +*******************************************************************************/ +void Cy_IPC_SystemSemaInit(void) +{ +/* Create array used for semaphores */ +#if !(CY_CPU_CORTEX_M0P) + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#else + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); +#endif +} + + +/******************************************************************************* +* Function Name: Cy_IPC_UserPipeIsr +****************************************************************************//** +* +* This is the interrupt service routine for the user pipe. +* +*******************************************************************************/ +void Cy_IPC_UserPipeIsr(void) +{ + Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_USRPIPE_ADDR]); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_RpcPipeIsr +****************************************************************************//** +* +* This is the interrupt service routine for the RPC pipe. +* +*******************************************************************************/ +void Cy_IPC_RpcPipeIsr(void) +{ + Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_RPCPIPE_ADDR]); +} + +/******************************************************************************* +* Function Name: Cy_IPC_SystemPipeInit +****************************************************************************//** +* +* Initializes the system pipes. The system pipes are used by BLE and Flash. +* \note The function should be called on all CPUs. +* +* This function is called in the SystemInit() function. If the default startup +* file is not used, or SystemInit() is not called in your project, +* call the following three functions prior to executing any flash or EmEEPROM +* write or erase operation: +* -# Cy_IPC_SystemSemaInit() +* -# Cy_IPC_SystemPipeInit() +* -# Cy_Flash_Init() +* +* Also this function is called to support BLE host/controller communication. +* +*******************************************************************************/ +void Cy_IPC_SystemPipeInit(void) +{ + uint32_t intr; + + intr = Cy_SysLib_EnterCriticalSection(); + + static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_sysCbArray[CY_IPC_CYPIPE_CLIENT_CNT]; + static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_userCbArray[CY_IPC_USRPIPE_CLIENT_CNT]; + static cy_ipc_pipe_callback_ptr_t cy_ipc_pipe_rpcCbArray[CY_IPC_RPCPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemPipeConfig = CY_CYPIPE_DEFAULT_CONFIG; + static const cy_stc_ipc_pipe_config_t userPipeConfig = { + .ep0ConfigData = { + .ipcNotifierNumber = CY_IPC_INTR_USRPIPE_CM0, + .ipcNotifierPriority = CY_IPC_INTR_USRPIPE_PRIOR_EP0, + .ipcNotifierMuxNumber = CY_IPC_INTR_USRPIPE_MUX_EP0, + .epAddress = CY_IPC_EP_USRPIPE_CM0_ADDR, + .epConfig = CY_IPC_USRPIPE_CONFIG_EP0 + }, + .ep1ConfigData = { + .ipcNotifierNumber = CY_IPC_INTR_USRPIPE_CM4, + .ipcNotifierPriority = CY_IPC_INTR_USRPIPE_PRIOR_EP1, + .ipcNotifierMuxNumber = 0u, + .epAddress = CY_IPC_EP_USRPIPE_CM4_ADDR, + .epConfig = CY_IPC_USRPIPE_CONFIG_EP1 + }, + .endpointClientsCount = CY_IPC_USRPIPE_CLIENT_CNT, + .endpointsCallbacksArray = cy_ipc_pipe_userCbArray, + .userPipeIsrHandler = &Cy_IPC_UserPipeIsr + }; + static const cy_stc_ipc_pipe_config_t rpcPipeConfig = { + .ep0ConfigData = { + .ipcNotifierNumber = CY_IPC_INTR_RPCPIPE_CM0, + .ipcNotifierPriority = CY_IPC_INTR_RPCPIPE_PRIOR_EP0, + .ipcNotifierMuxNumber = CY_IPC_INTR_RPCPIPE_MUX_EP0, + .epAddress = CY_IPC_EP_RPCPIPE_CM0_ADDR, + .epConfig = CY_IPC_RPCPIPE_CONFIG_EP0 + }, + .ep1ConfigData = { + .ipcNotifierNumber = CY_IPC_INTR_RPCPIPE_CM4, + .ipcNotifierPriority = CY_IPC_INTR_RPCPIPE_PRIOR_EP1, + .ipcNotifierMuxNumber = 0u, + .epAddress = CY_IPC_EP_RPCPIPE_CM4_ADDR, + .epConfig = CY_IPC_RPCPIPE_CONFIG_EP1 + }, + .endpointClientsCount = CY_IPC_RPCPIPE_CLIENT_CNT, + .endpointsCallbacksArray = cy_ipc_pipe_rpcCbArray, + .userPipeIsrHandler = &Cy_IPC_RpcPipeIsr + }; + + Cy_IPC_Pipe_Config(cy_ipc_pipe_sysEpArray); + + Cy_IPC_Pipe_Init(&systemPipeConfig); + Cy_IPC_Pipe_Init(&userPipeConfig); + Cy_IPC_Pipe_Init(&rpcPipeConfig); + + Cy_SysLib_ExitCriticalSection(intr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_SystemPipeIsr +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_IPC_SystemPipeIsr(void) +{ + Cy_IPC_Pipe_ExecCallback(&cy_ipc_pipe_sysEpArray[CY_IPC_EP_CYPIPE_ADDR]); +} + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.h new file mode 100644 index 0000000000..0dc321858a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.h @@ -0,0 +1,219 @@ +/***************************************************************************//** +* \file cy_ipc_config.h +* \version 1.10.1 +* +* \brief +* This header file is not intended to be part of the IPC driver since it defines +* a device specific configuration for the IPC channels and pipes. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#ifndef CY_IPC_CONFIG_H +#define CY_IPC_CONFIG_H + +/* IPC Resources */ +#define CY_IPC_CHANNELS (uint32_t)(CPUSS_IPC_IPC_NR) +#define CY_IPC_INTERRUPTS (uint32_t)(CPUSS_IPC_IPC_IRQ_NR) + +/* IPC channel definitions */ +#define CY_IPC_CHAN_SYSCALL_CM0 (0u) /* System calls for the CM0 processor */ +#define CY_IPC_CHAN_SYSCALL_CM4 (1u) /* System calls for the 1st non-CM0 processor */ +#if (CY_CPU_CORTEX_M0P) + #define CY_IPC_CHAN_SYSCALL CY_IPC_CHAN_SYSCALL_CM0 + #define Cy_IPC_SystemPipeIsr NvicMux1_IRQHandler +#else + #define CY_IPC_CHAN_SYSCALL CY_IPC_CHAN_SYSCALL_CM4 + #define Cy_IPC_SystemPipeIsr cpuss_interrupts_ipc_4_IRQHandler +#endif /* (CY_CPU_CORTEX_M0P) */ + +#define CY_IPC_CHAN_SYSCALL_DAP (uint32_t)(2u) /**< System calls for the DAP */ +#define CY_IPC_CHAN_CRYPTO (uint32_t)(3u) /**< IPC data channel for the Crypto */ +#define CY_IPC_CHAN_SEMA (uint32_t)(4u) /**< IPC data channel for the Semaphores */ + +#define CY_IPC_CHAN_CYPIPE_EP0 (uint32_t)(5u) /**< IPC data channel for CYPIPE EP0 */ +#define CY_IPC_CHAN_CYPIPE_EP1 (uint32_t)(6u) /**< IPC data channel for CYPIPE EP1 */ + +/* IPC Notify interrupts definitions */ +#define CY_IPC_INTR_SYSCALL1 (uint32_t)(0u) + +#define CY_IPC_INTR_CRYPTO_SRV (uint32_t)(1u) /**< IPC interrupt structure for the Crypto server */ +#define CY_IPC_INTR_CRYPTO_CLI (uint32_t)(2u) /**< IPC interrupt structure for the Crypto client */ + +#define CY_IPC_INTR_SPARE (uint32_t)(7u) + +/* IPC Semaphores allocation + This will allow 128 (4*32) semaphores */ +#define CY_IPC_SEMA_COUNT (uint32_t)(128u) + +/* IPC Pipe definitions */ +#define CY_IPC_MAX_ENDPOINTS (uint32_t)(8u) + +/******************************************************************************* +** CY_PIPE default configuration +*******************************************************************************/ +#define CY_IPC_CYPIPE_CLIENT_CNT (uint32_t)(8u) +#define CY_IPC_USRPIPE_CLIENT_CNT (uint32_t)(8u) +#define CY_IPC_RPCPIPE_CLIENT_CNT (uint32_t)(16u) + +#if (CY_CPU_CORTEX_M0P) + #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM0_ADDR +#else + #define CY_IPC_EP_CYPIPE_ADDR CY_IPC_EP_CYPIPE_CM4_ADDR +#endif /* (CY_CPU_CORTEX_M0P) */ + +#define CY_IPC_INTR_CYPIPE_MUX_EP0 (uint32_t)(1u) /* IPC CYPRESS PIPE */ +#define CY_IPC_INTR_CYPIPE_EP0 (uint32_t)(3u) /* Notifier EP0 */ +#define CY_IPC_INTR_CYPIPE_PRIOR_EP0 (uint32_t)(1u) /* Notifier Priority */ + +#define CY_IPC_INTR_CYPIPE_EP1 (uint32_t)(4u) /* Notifier EP1 */ +#define CY_IPC_INTR_CYPIPE_PRIOR_EP1 (uint32_t)(1u) /* Notifier Priority */ + +#define CY_IPC_CYPIPE_CHAN_MASK_EP0 (uint32_t)(0x0001ul << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_IPC_CYPIPE_CHAN_MASK_EP1 (uint32_t)(0x0001ul << CY_IPC_CHAN_CYPIPE_EP1) + +/* Endpoint indexes in the pipe array */ +#define CY_IPC_EP_CYPIPE_CM0_ADDR (uint32_t)(0u) +#define CY_IPC_EP_CYPIPE_CM4_ADDR (uint32_t)(1u) + +/******************************************************************************/ + +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_IPC_CYPIPE_CONFIG_EP0 (uint32_t)( (CY_IPC_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_IPC_CYPIPE_CONFIG_EP1 (uint32_t)( (CY_IPC_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) +#define CY_IPC_CYPIPE_INTR_MASK (uint32_t)( CY_IPC_CYPIPE_CHAN_MASK_EP0 | CY_IPC_CYPIPE_CHAN_MASK_EP1 ) + +/******************************************************************************/ +#define CY_IPC_CHAN_USRPIPE_CM0 (uint32_t)(8u) +#define CY_IPC_CHAN_USRPIPE_CM4 (uint32_t)(9u) + +#define CY_IPC_INTR_USRPIPE_CM0 (uint32_t)(8u) +#define CY_IPC_INTR_USRPIPE_CM4 (uint32_t)(9u) + +#define CY_IPC_EP_USRPIPE_ADDR_EP0 (uint32_t)(2u) +#define CY_IPC_EP_USRPIPE_ADDR_EP1 (uint32_t)(3u) + +/* Endpoint indexes in the pipe array */ +#define CY_IPC_EP_USRPIPE_CM0_ADDR (uint32_t)(2u) +#define CY_IPC_EP_USRPIPE_CM4_ADDR (uint32_t)(3u) + + +#if (CY_CPU_CORTEX_M0P) + #define CY_IPC_EP_USRPIPE_ADDR CY_IPC_EP_USRPIPE_CM0_ADDR + #define CY_IPC_EP_USRPIPE_DEST CY_IPC_EP_USRPIPE_CM4_ADDR +#else + #define CY_IPC_EP_USRPIPE_ADDR CY_IPC_EP_USRPIPE_CM4_ADDR + #define CY_IPC_EP_USRPIPE_DEST CY_IPC_EP_USRPIPE_CM0_ADDR +#endif /* (CY_CPU_CORTEX_M0P) */ + +#define CY_IPC_INTR_USRPIPE_MUX_EP0 (uint32_t)(2u) +#define CY_IPC_INTR_USRPIPE_EP0 CY_IPC_INTR_USRPIPE_CM0 +#define CY_IPC_INTR_USRPIPE_PRIOR_EP0 (uint32_t)(1u) /* Notifier Priority */ + +#define CY_IPC_INTR_USRPIPE_EP1 CY_IPC_INTR_USRPIPE_CM4 +#define CY_IPC_INTR_USRPIPE_PRIOR_EP1 (uint32_t)(1u) /* Notifier Priority */ + +#define CY_IPC_USRPIPE_CHAN_MASK_EP0 (uint32_t)(0x0001ul << CY_IPC_CHAN_USRPIPE_CM0) +#define CY_IPC_USRPIPE_CHAN_MASK_EP1 (uint32_t)(0x0001ul << CY_IPC_CHAN_USRPIPE_CM4) + + +#define CY_IPC_USRPIPE_CONFIG_EP0 (uint32_t)( (CY_IPC_USRPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_USRPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_USRPIPE_CM0) +#define CY_IPC_USRPIPE_CONFIG_EP1 (uint32_t)( (CY_IPC_USRPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_USRPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_USRPIPE_CM4) +#define CY_IPC_USRPIPE_INTR_MASK (uint32_t)( CY_IPC_USRPIPE_CHAN_MASK_EP0 | CY_IPC_USRPIPE_CHAN_MASK_EP1 ) + + +/******************************************************************************/ +#define CY_IPC_CHAN_RPCPIPE_CM0 (uint32_t)(10u) +#define CY_IPC_CHAN_RPCPIPE_CM4 (uint32_t)(11u) + +#define CY_IPC_INTR_RPCPIPE_CM0 (uint32_t)(10u) +#define CY_IPC_INTR_RPCPIPE_CM4 (uint32_t)(11u) + +#define CY_IPC_EP_RPCPIPE_ADDR_EP0 (uint32_t)(4u) +#define CY_IPC_EP_RPCPIPE_ADDR_EP1 (uint32_t)(5u) + +/* Endpoint indexes in the pipe array */ +#define CY_IPC_EP_RPCPIPE_CM0_ADDR (uint32_t)(4u) +#define CY_IPC_EP_RPCPIPE_CM4_ADDR (uint32_t)(5u) + + +#if (CY_CPU_CORTEX_M0P) + #define CY_IPC_EP_RPCPIPE_ADDR CY_IPC_EP_RPCPIPE_CM0_ADDR + #define CY_IPC_EP_RPCPIPE_DEST CY_IPC_EP_RPCPIPE_CM4_ADDR +#else + #define CY_IPC_EP_RPCPIPE_ADDR CY_IPC_EP_RPCPIPE_CM4_ADDR + #define CY_IPC_EP_RPCPIPE_DEST CY_IPC_EP_RPCPIPE_CM0_ADDR +#endif /* (CY_CPU_CORTEX_M0P) */ + +#define CY_IPC_INTR_RPCPIPE_MUX_EP0 (uint32_t)(4u) +#define CY_IPC_INTR_RPCPIPE_EP0 CY_IPC_INTR_RPCPIPE_CM0 +#define CY_IPC_INTR_RPCPIPE_PRIOR_EP0 (uint32_t)(1u) /* Notifier Priority */ + +#define CY_IPC_INTR_RPCPIPE_EP1 CY_IPC_INTR_RPCPIPE_CM4 +#define CY_IPC_INTR_RPCPIPE_PRIOR_EP1 (uint32_t)(1u) /* Notifier Priority */ + +#define CY_IPC_RPCPIPE_CHAN_MASK_EP0 (uint32_t)(0x0001ul << CY_IPC_CHAN_RPCPIPE_CM0) +#define CY_IPC_RPCPIPE_CHAN_MASK_EP1 (uint32_t)(0x0001ul << CY_IPC_CHAN_RPCPIPE_CM4) + + +#define CY_IPC_RPCPIPE_CONFIG_EP0 (uint32_t)( (CY_IPC_RPCPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_RPCPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_RPCPIPE_CM0) +#define CY_IPC_RPCPIPE_CONFIG_EP1 (uint32_t)( (CY_IPC_RPCPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_RPCPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_RPCPIPE_CM4) +#define CY_IPC_RPCPIPE_INTR_MASK (uint32_t)( CY_IPC_RPCPIPE_CHAN_MASK_EP0 | CY_IPC_RPCPIPE_CHAN_MASK_EP1 ) + +#ifdef __cplusplus +extern "C" { +#endif + + + +/* +* \addtogroup group_ipc_configuration_sema +* \{ +*/ +void Cy_IPC_SystemSemaInit(void); +/* \} group_ipc_configuration_sema */ + +/* +* \addtogroup group_ipc_configuration_cypipe +* \{ +*/ +void Cy_IPC_SystemPipeInit(void); +/* \} group_ipc_configuration_cypipe */ + +void Cy_IPC_SystemPipeIsr(void); + +#ifdef __cplusplus +} +#endif + +#endif /* CY_IPC_CONFIG_H */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cymetadata.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cymetadata.c new file mode 100644 index 0000000000..ca605b521a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cymetadata.c @@ -0,0 +1,56 @@ +/******************************************************************************* +* File Name: cymetadata.c +* +* PSoC Creator 4.1 +* +* Description: +* This file defines all extra memory spaces that need to be included. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2007-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +********************************************************************************/ + + +#include "stdint.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_META_SECTION +#define CY_META_SECTION __attribute__ ((__section__(".cymeta"), used)) +#endif +CY_META_SECTION +#elif defined(__ICCARM__) + +#pragma location=".cymeta" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_metadata[] = { +#if defined(CY8C637BZI_BLD74) + 0x00u, 0x05u, 0xE2u, 0x01u, 0x11u, 0x00u, 0x00u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u +#elif defined(CY8C6347BZI_BLD53) + 0x00u, 0x05u, 0xE2u, 0x07u, 0x21u, 0x00u, 0x21u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u +#else +#error "Unknown target device" +#endif +}; + +#if defined(CY8C637BZI_BLD74) +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_CHIP_PROT_SECTION +#define CY_CHIP_PROT_SECTION __attribute__ ((__section__(".cychipprotect"), used)) +#endif +CY_CHIP_PROT_SECTION +#elif defined(__ICCARM__) +#pragma location=".cychipprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_chipprotect[] = { + 0x01u +}; +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h new file mode 100644 index 0000000000..296018caf2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h @@ -0,0 +1,1884 @@ +/***************************************************************************//** +* \file gpio_psoc63_116_bga_ble.h +* +* \brief +* PSoC 63 device GPIO header for 116-BGA-BLE package +* +* \note +* Generator version: 1.2.0.117 +* Database revision: rev#1034984 +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#ifndef _GPIO_PSOC63_116_BGA_BLE_H_ +#define _GPIO_PSOC63_116_BGA_BLE_H_ + +/* Package type */ +enum +{ + CY_GPIO_PACKAGE_QFN, + CY_GPIO_PACKAGE_BGA, + CY_GPIO_PACKAGE_CSP, + CY_GPIO_PACKAGE_WLCSP, + CY_GPIO_PACKAGE_LQFP, +}; + +#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA + +/* Port List */ +/* PORT 0 (GPIO) */ +#define P0_0_PORT GPIO_PRT0 +#define P0_0_PIN 0u +#define P0_0_NUM 0u +#define P0_1_PORT GPIO_PRT0 +#define P0_1_PIN 1u +#define P0_1_NUM 1u +#define P0_2_PORT GPIO_PRT0 +#define P0_2_PIN 2u +#define P0_2_NUM 2u +#define P0_3_PORT GPIO_PRT0 +#define P0_3_PIN 3u +#define P0_3_NUM 3u +#define P0_4_PORT GPIO_PRT0 +#define P0_4_PIN 4u +#define P0_4_NUM 4u +#define P0_5_PORT GPIO_PRT0 +#define P0_5_PIN 5u +#define P0_5_NUM 5u + +/* PORT 1 (GPIO_OVT) */ +#define P1_0_PORT GPIO_PRT1 +#define P1_0_PIN 0u +#define P1_0_NUM 0u +#define P1_1_PORT GPIO_PRT1 +#define P1_1_PIN 1u +#define P1_1_NUM 1u +#define P1_2_PORT GPIO_PRT1 +#define P1_2_PIN 2u +#define P1_2_NUM 2u +#define P1_3_PORT GPIO_PRT1 +#define P1_3_PIN 3u +#define P1_3_NUM 3u +#define P1_4_PORT GPIO_PRT1 +#define P1_4_PIN 4u +#define P1_4_NUM 4u +#define P1_5_PORT GPIO_PRT1 +#define P1_5_PIN 5u +#define P1_5_NUM 5u + +/* PORT 5 (GPIO) */ +#define P5_0_PORT GPIO_PRT5 +#define P5_0_PIN 0u +#define P5_0_NUM 0u +#define P5_1_PORT GPIO_PRT5 +#define P5_1_PIN 1u +#define P5_1_NUM 1u +#define P5_2_PORT GPIO_PRT5 +#define P5_2_PIN 2u +#define P5_2_NUM 2u +#define P5_3_PORT GPIO_PRT5 +#define P5_3_PIN 3u +#define P5_3_NUM 3u +#define P5_4_PORT GPIO_PRT5 +#define P5_4_PIN 4u +#define P5_4_NUM 4u +#define P5_5_PORT GPIO_PRT5 +#define P5_5_PIN 5u +#define P5_5_NUM 5u +#define P5_6_PORT GPIO_PRT5 +#define P5_6_PIN 6u +#define P5_6_NUM 6u + +/* PORT 6 (GPIO) */ +#define P6_0_PORT GPIO_PRT6 +#define P6_0_PIN 0u +#define P6_0_NUM 0u +#define P6_1_PORT GPIO_PRT6 +#define P6_1_PIN 1u +#define P6_1_NUM 1u +#define P6_2_PORT GPIO_PRT6 +#define P6_2_PIN 2u +#define P6_2_NUM 2u +#define P6_3_PORT GPIO_PRT6 +#define P6_3_PIN 3u +#define P6_3_NUM 3u +#define P6_4_PORT GPIO_PRT6 +#define P6_4_PIN 4u +#define P6_4_NUM 4u +#define P6_5_PORT GPIO_PRT6 +#define P6_5_PIN 5u +#define P6_5_NUM 5u +#define P6_6_PORT GPIO_PRT6 +#define P6_6_PIN 6u +#define P6_6_NUM 6u +#define P6_7_PORT GPIO_PRT6 +#define P6_7_PIN 7u +#define P6_7_NUM 7u + +/* PORT 7 (GPIO) */ +#define P7_0_PORT GPIO_PRT7 +#define P7_0_PIN 0u +#define P7_0_NUM 0u +#define P7_1_PORT GPIO_PRT7 +#define P7_1_PIN 1u +#define P7_1_NUM 1u +#define P7_2_PORT GPIO_PRT7 +#define P7_2_PIN 2u +#define P7_2_NUM 2u +#define P7_3_PORT GPIO_PRT7 +#define P7_3_PIN 3u +#define P7_3_NUM 3u +#define P7_4_PORT GPIO_PRT7 +#define P7_4_PIN 4u +#define P7_4_NUM 4u +#define P7_5_PORT GPIO_PRT7 +#define P7_5_PIN 5u +#define P7_5_NUM 5u +#define P7_6_PORT GPIO_PRT7 +#define P7_6_PIN 6u +#define P7_6_NUM 6u +#define P7_7_PORT GPIO_PRT7 +#define P7_7_PIN 7u +#define P7_7_NUM 7u + +/* PORT 8 (GPIO) */ +#define P8_0_PORT GPIO_PRT8 +#define P8_0_PIN 0u +#define P8_0_NUM 0u +#define P8_1_PORT GPIO_PRT8 +#define P8_1_PIN 1u +#define P8_1_NUM 1u +#define P8_2_PORT GPIO_PRT8 +#define P8_2_PIN 2u +#define P8_2_NUM 2u +#define P8_3_PORT GPIO_PRT8 +#define P8_3_PIN 3u +#define P8_3_NUM 3u +#define P8_4_PORT GPIO_PRT8 +#define P8_4_PIN 4u +#define P8_4_NUM 4u +#define P8_5_PORT GPIO_PRT8 +#define P8_5_PIN 5u +#define P8_5_NUM 5u +#define P8_6_PORT GPIO_PRT8 +#define P8_6_PIN 6u +#define P8_6_NUM 6u +#define P8_7_PORT GPIO_PRT8 +#define P8_7_PIN 7u +#define P8_7_NUM 7u + +/* PORT 9 (GPIO) */ +#define P9_0_PORT GPIO_PRT9 +#define P9_0_PIN 0u +#define P9_0_NUM 0u +#define P9_1_PORT GPIO_PRT9 +#define P9_1_PIN 1u +#define P9_1_NUM 1u +#define P9_2_PORT GPIO_PRT9 +#define P9_2_PIN 2u +#define P9_2_NUM 2u +#define P9_3_PORT GPIO_PRT9 +#define P9_3_PIN 3u +#define P9_3_NUM 3u +#define P9_4_PORT GPIO_PRT9 +#define P9_4_PIN 4u +#define P9_4_NUM 4u +#define P9_5_PORT GPIO_PRT9 +#define P9_5_PIN 5u +#define P9_5_NUM 5u +#define P9_6_PORT GPIO_PRT9 +#define P9_6_PIN 6u +#define P9_6_NUM 6u +#define P9_7_PORT GPIO_PRT9 +#define P9_7_PIN 7u +#define P9_7_NUM 7u + +/* PORT 10 (GPIO) */ +#define P10_0_PORT GPIO_PRT10 +#define P10_0_PIN 0u +#define P10_0_NUM 0u +#define P10_1_PORT GPIO_PRT10 +#define P10_1_PIN 1u +#define P10_1_NUM 1u +#define P10_2_PORT GPIO_PRT10 +#define P10_2_PIN 2u +#define P10_2_NUM 2u +#define P10_3_PORT GPIO_PRT10 +#define P10_3_PIN 3u +#define P10_3_NUM 3u +#define P10_4_PORT GPIO_PRT10 +#define P10_4_PIN 4u +#define P10_4_NUM 4u +#define P10_5_PORT GPIO_PRT10 +#define P10_5_PIN 5u +#define P10_5_NUM 5u +#define P10_6_PORT GPIO_PRT10 +#define P10_6_PIN 6u +#define P10_6_NUM 6u + +/* PORT 11 (GPIO) */ +#define P11_0_PORT GPIO_PRT11 +#define P11_0_PIN 0u +#define P11_0_NUM 0u +#define P11_1_PORT GPIO_PRT11 +#define P11_1_PIN 1u +#define P11_1_NUM 1u +#define P11_2_PORT GPIO_PRT11 +#define P11_2_PIN 2u +#define P11_2_NUM 2u +#define P11_3_PORT GPIO_PRT11 +#define P11_3_PIN 3u +#define P11_3_NUM 3u +#define P11_4_PORT GPIO_PRT11 +#define P11_4_PIN 4u +#define P11_4_NUM 4u +#define P11_5_PORT GPIO_PRT11 +#define P11_5_PIN 5u +#define P11_5_NUM 5u +#define P11_6_PORT GPIO_PRT11 +#define P11_6_PIN 6u +#define P11_6_NUM 6u +#define P11_7_PORT GPIO_PRT11 +#define P11_7_PIN 7u +#define P11_7_NUM 7u + +/* PORT 12 (GPIO) */ +#define P12_0_PORT GPIO_PRT12 +#define P12_0_PIN 0u +#define P12_0_NUM 0u +#define P12_1_PORT GPIO_PRT12 +#define P12_1_PIN 1u +#define P12_1_NUM 1u +#define P12_2_PORT GPIO_PRT12 +#define P12_2_PIN 2u +#define P12_2_NUM 2u +#define P12_3_PORT GPIO_PRT12 +#define P12_3_PIN 3u +#define P12_3_NUM 3u +#define P12_4_PORT GPIO_PRT12 +#define P12_4_PIN 4u +#define P12_4_NUM 4u +#define P12_5_PORT GPIO_PRT12 +#define P12_5_PIN 5u +#define P12_5_NUM 5u +#define P12_6_PORT GPIO_PRT12 +#define P12_6_PIN 6u +#define P12_6_NUM 6u +#define P12_7_PORT GPIO_PRT12 +#define P12_7_PIN 7u +#define P12_7_NUM 7u + +/* PORT 13 (GPIO) */ +#define P13_0_PORT GPIO_PRT13 +#define P13_0_PIN 0u +#define P13_0_NUM 0u +#define P13_1_PORT GPIO_PRT13 +#define P13_1_PIN 1u +#define P13_1_NUM 1u +#define P13_6_PORT GPIO_PRT13 +#define P13_6_PIN 6u +#define P13_6_NUM 6u +#define P13_7_PORT GPIO_PRT13 +#define P13_7_PIN 7u +#define P13_7_NUM 7u + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_CSHIELDPADS_PORT 7u +#define CSD_CSHIELDPADS_PIN 7u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define IOSS_ADFT0_NET_PORT 10u +#define IOSS_ADFT0_NET_PIN 0u +#define IOSS_ADFT1_NET_PORT 10u +#define IOSS_ADFT1_NET_PIN 1u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP0_PORT 5u +#define LPCOMP_INP_COMP0_PIN 6u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_AREF_EXT_VREF_PORT 9u +#define PASS_AREF_EXT_VREF_PIN 7u +#define PASS_CTB_OA0_OUT_10X_PORT 9u +#define PASS_CTB_OA0_OUT_10X_PIN 2u +#define PASS_CTB_OA1_OUT_10X_PORT 9u +#define PASS_CTB_OA1_OUT_10X_PIN 3u +#define PASS_CTB_PADS0_PORT 9u +#define PASS_CTB_PADS0_PIN 0u +#define PASS_CTB_PADS1_PORT 9u +#define PASS_CTB_PADS1_PIN 1u +#define PASS_CTB_PADS2_PORT 9u +#define PASS_CTB_PADS2_PIN 2u +#define PASS_CTB_PADS3_PORT 9u +#define PASS_CTB_PADS3_PIN 3u +#define PASS_CTB_PADS4_PORT 9u +#define PASS_CTB_PADS4_PIN 4u +#define PASS_CTB_PADS5_PORT 9u +#define PASS_CTB_PADS5_PIN 5u +#define PASS_CTB_PADS6_PORT 9u +#define PASS_CTB_PADS6_PIN 6u +#define PASS_CTB_PADS7_PORT 9u +#define PASS_CTB_PADS7_PIN 7u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define PASS_SARMUX_PADS2_PORT 10u +#define PASS_SARMUX_PADS2_PIN 2u +#define PASS_SARMUX_PADS3_PORT 10u +#define PASS_SARMUX_PADS3_PIN 3u +#define PASS_SARMUX_PADS4_PORT 10u +#define PASS_SARMUX_PADS4_PIN 4u +#define PASS_SARMUX_PADS5_PORT 10u +#define PASS_SARMUX_PADS5_PIN 5u +#define PASS_SARMUX_PADS6_PORT 10u +#define PASS_SARMUX_PADS6_PIN 6u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_ECO_IN_PORT 12u +#define SRSS_ECO_IN_PIN 6u +#define SRSS_ECO_OUT_PORT 12u +#define SRSS_ECO_OUT_PIN 7u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ + HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ + HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ + HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ + HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ + HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ + HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ + HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ + HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ + HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ + HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ + HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ + + /* P0.0 */ + P0_0_GPIO = 0, /* GPIO controls 'out' */ + P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_0_AMUXA = 4, /* Analog mux bus A */ + P0_0_AMUXB = 5, /* Analog mux bus B */ + P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* GPIO controls 'out' */ + P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_1_AMUXA = 4, /* Analog mux bus A */ + P0_1_AMUXB = 5, /* Analog mux bus B */ + P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P0.2 */ + P0_2_GPIO = 0, /* GPIO controls 'out' */ + P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_2_AMUXA = 4, /* Analog mux bus A */ + P0_2_AMUXB = 5, /* Analog mux bus B */ + P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ + P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ + P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ + P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ + P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ + P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ + P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ + P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ + P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ + + /* P0.3 */ + P0_3_GPIO = 0, /* GPIO controls 'out' */ + P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_3_AMUXA = 4, /* Analog mux bus A */ + P0_3_AMUXB = 5, /* Analog mux bus B */ + P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ + P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ + P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ + P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ + P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ + P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ + P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ + P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ + P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ + + /* P0.4 */ + P0_4_GPIO = 0, /* GPIO controls 'out' */ + P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_4_AMUXA = 4, /* Analog mux bus A */ + P0_4_AMUXB = 5, /* Analog mux bus B */ + P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ + P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ + P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ + P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ + P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ + P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ + P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ + P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ + P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ + + /* P0.5 */ + P0_5_GPIO = 0, /* GPIO controls 'out' */ + P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P0_5_AMUXA = 4, /* Analog mux bus A */ + P0_5_AMUXB = 5, /* Analog mux bus B */ + P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ + P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ + P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ + P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ + P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ + P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ + P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ + P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ + P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ + P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ + + /* P1.0 */ + P1_0_GPIO = 0, /* GPIO controls 'out' */ + P1_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_0_AMUXA = 4, /* Analog mux bus A */ + P1_0_AMUXB = 5, /* Analog mux bus B */ + P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ + P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ + P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ + P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ + P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ + P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ + P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */ + P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */ + P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */ + P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ + + /* P1.1 */ + P1_1_GPIO = 0, /* GPIO controls 'out' */ + P1_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_1_AMUXA = 4, /* Analog mux bus A */ + P1_1_AMUXB = 5, /* Analog mux bus B */ + P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ + P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ + P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ + P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ + P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ + P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ + P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */ + P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */ + P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */ + P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ + + /* P1.2 */ + P1_2_GPIO = 0, /* GPIO controls 'out' */ + P1_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_2_AMUXA = 4, /* Analog mux bus A */ + P1_2_AMUXB = 5, /* Analog mux bus B */ + P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_2_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:4 */ + P1_2_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:1 */ + P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ + P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ + P1_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ + P1_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ + P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */ + P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */ + + /* P1.3 */ + P1_3_GPIO = 0, /* GPIO controls 'out' */ + P1_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_3_AMUXA = 4, /* Analog mux bus A */ + P1_3_AMUXB = 5, /* Analog mux bus B */ + P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_3_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:4 */ + P1_3_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ + P1_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ + P1_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ + P1_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ + P1_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ + P1_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:0 */ + P1_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:0 */ + + /* P1.4 */ + P1_4_GPIO = 0, /* GPIO controls 'out' */ + P1_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_4_AMUXA = 4, /* Analog mux bus A */ + P1_4_AMUXB = 5, /* Analog mux bus B */ + P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */ + P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */ + P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ + P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ + P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ + P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ + P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */ + + /* P1.5 */ + P1_5_GPIO = 0, /* GPIO controls 'out' */ + P1_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P1_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P1_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P1_5_AMUXA = 4, /* Analog mux bus A */ + P1_5_AMUXB = 5, /* Analog mux bus B */ + P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */ + P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ + P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ + P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ + P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ + P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ + P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ + + /* P5.0 */ + P5_0_GPIO = 0, /* GPIO controls 'out' */ + P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_0_AMUXA = 4, /* Analog mux bus A */ + P5_0_AMUXB = 5, /* Analog mux bus B */ + P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ + P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ + P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ + P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ + P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ + P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ + P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ + P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ + P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ + P5_0_AUDIOSS_CLK_I2S_IF = 22, /* Digital Active - audioss.clk_i2s_if */ + P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ + + /* P5.1 */ + P5_1_GPIO = 0, /* GPIO controls 'out' */ + P5_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_1_AMUXA = 4, /* Analog mux bus A */ + P5_1_AMUXB = 5, /* Analog mux bus B */ + P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ + P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ + P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ + P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ + P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ + P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ + P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ + P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ + P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ + P5_1_AUDIOSS_TX_SCK = 22, /* Digital Active - audioss.tx_sck */ + P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ + + /* P5.2 */ + P5_2_GPIO = 0, /* GPIO controls 'out' */ + P5_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_2_AMUXA = 4, /* Analog mux bus A */ + P5_2_AMUXB = 5, /* Analog mux bus B */ + P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ + P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ + P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ + P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ + P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ + P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ + P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ + P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ + P5_2_AUDIOSS_TX_WS = 22, /* Digital Active - audioss.tx_ws */ + + /* P5.3 */ + P5_3_GPIO = 0, /* GPIO controls 'out' */ + P5_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_3_AMUXA = 4, /* Analog mux bus A */ + P5_3_AMUXB = 5, /* Analog mux bus B */ + P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */ + P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ + P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ + P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ + P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ + P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ + P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ + P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ + P5_3_AUDIOSS_TX_SDO = 22, /* Digital Active - audioss.tx_sdo */ + + /* P5.4 */ + P5_4_GPIO = 0, /* GPIO controls 'out' */ + P5_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_4_AMUXA = 4, /* Analog mux bus A */ + P5_4_AMUXB = 5, /* Analog mux bus B */ + P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ + P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ + P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ + P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ + P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ + P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ + P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ + P5_4_AUDIOSS_RX_SCK = 22, /* Digital Active - audioss.rx_sck */ + + /* P5.5 */ + P5_5_GPIO = 0, /* GPIO controls 'out' */ + P5_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_5_AMUXA = 4, /* Analog mux bus A */ + P5_5_AMUXB = 5, /* Analog mux bus B */ + P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */ + P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ + P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ + P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ + P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ + P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ + P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ + P5_5_AUDIOSS_RX_WS = 22, /* Digital Active - audioss.rx_ws */ + + /* P5.6 */ + P5_6_GPIO = 0, /* GPIO controls 'out' */ + P5_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P5_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P5_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P5_6_AMUXA = 4, /* Analog mux bus A */ + P5_6_AMUXB = 5, /* Analog mux bus B */ + P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ + P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ + P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ + P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ + P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ + P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ + P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ + P5_6_AUDIOSS_RX_SDI = 22, /* Digital Active - audioss.rx_sdi */ + + /* P6.0 */ + P6_0_GPIO = 0, /* GPIO controls 'out' */ + P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_0_AMUXA = 4, /* Analog mux bus A */ + P6_0_AMUXB = 5, /* Analog mux bus B */ + P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ + P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ + P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ + P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ + P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ + P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ + P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ + P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ + P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ + P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ + P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ + P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ + + /* P6.1 */ + P6_1_GPIO = 0, /* GPIO controls 'out' */ + P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_1_AMUXA = 4, /* Analog mux bus A */ + P6_1_AMUXB = 5, /* Analog mux bus B */ + P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ + P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ + P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ + P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ + P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ + P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ + P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ + P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ + P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ + P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ + P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ + P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ + + /* P6.2 */ + P6_2_GPIO = 0, /* GPIO controls 'out' */ + P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_2_AMUXA = 4, /* Analog mux bus A */ + P6_2_AMUXB = 5, /* Analog mux bus B */ + P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ + P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ + P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ + + /* P6.3 */ + P6_3_GPIO = 0, /* GPIO controls 'out' */ + P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_3_AMUXA = 4, /* Analog mux bus A */ + P6_3_AMUXB = 5, /* Analog mux bus B */ + P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ + P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ + P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ + + /* P6.4 */ + P6_4_GPIO = 0, /* GPIO controls 'out' */ + P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_4_AMUXA = 4, /* Analog mux bus A */ + P6_4_AMUXB = 5, /* Analog mux bus B */ + P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ + P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ + P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ + P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ + P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* GPIO controls 'out' */ + P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_5_AMUXA = 4, /* Analog mux bus A */ + P6_5_AMUXB = 5, /* Analog mux bus B */ + P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ + P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ + P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ + P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ + P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ + P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* GPIO controls 'out' */ + P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_6_AMUXA = 4, /* Analog mux bus A */ + P6_6_AMUXB = 5, /* Analog mux bus B */ + P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ + P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ + P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ + P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* GPIO controls 'out' */ + P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P6_7_AMUXA = 4, /* Analog mux bus A */ + P6_7_AMUXB = 5, /* Analog mux bus B */ + P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ + P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ + P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* GPIO controls 'out' */ + P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_0_AMUXA = 4, /* Analog mux bus A */ + P7_0_AMUXB = 5, /* Analog mux bus B */ + P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ + P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* GPIO controls 'out' */ + P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_1_AMUXA = 4, /* Analog mux bus A */ + P7_1_AMUXB = 5, /* Analog mux bus B */ + P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ + P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* GPIO controls 'out' */ + P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_2_AMUXA = 4, /* Analog mux bus A */ + P7_2_AMUXB = 5, /* Analog mux bus B */ + P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ + P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* GPIO controls 'out' */ + P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_3_AMUXA = 4, /* Analog mux bus A */ + P7_3_AMUXB = 5, /* Analog mux bus B */ + P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ + P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ + + /* P7.4 */ + P7_4_GPIO = 0, /* GPIO controls 'out' */ + P7_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_4_AMUXA = 4, /* Analog mux bus A */ + P7_4_AMUXB = 5, /* Analog mux bus B */ + P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ + P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */ + P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ + P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ + P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ + P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ + P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ + P7_4_BLESS_EXT_LNA_RX_CTL_OUT = 26, /* Digital Active - bless.ext_lna_rx_ctl_out */ + P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ + + /* P7.5 */ + P7_5_GPIO = 0, /* GPIO controls 'out' */ + P7_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_5_AMUXA = 4, /* Analog mux bus A */ + P7_5_AMUXB = 5, /* Analog mux bus B */ + P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */ + P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ + P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ + P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ + P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ + P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ + P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ + P7_5_BLESS_EXT_PA_TX_CTL_OUT = 26, /* Digital Active - bless.ext_pa_tx_ctl_out */ + P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ + + /* P7.6 */ + P7_6_GPIO = 0, /* GPIO controls 'out' */ + P7_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_6_AMUXA = 4, /* Analog mux bus A */ + P7_6_AMUXB = 5, /* Analog mux bus B */ + P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ + P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */ + P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ + P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ + P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ + P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ + P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ + P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT = 26, /* Digital Active - bless.ext_pa_lna_chip_en_out */ + P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ + + /* P7.7 */ + P7_7_GPIO = 0, /* GPIO controls 'out' */ + P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P7_7_AMUXA = 4, /* Analog mux bus A */ + P7_7_AMUXB = 5, /* Analog mux bus B */ + P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ + P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ + P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ + P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ + P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ + P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ + P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ + P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ + P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ + + /* P8.0 */ + P8_0_GPIO = 0, /* GPIO controls 'out' */ + P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_0_AMUXA = 4, /* Analog mux bus A */ + P8_0_AMUXB = 5, /* Analog mux bus B */ + P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ + P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ + P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ + P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ + P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ + + /* P8.1 */ + P8_1_GPIO = 0, /* GPIO controls 'out' */ + P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_1_AMUXA = 4, /* Analog mux bus A */ + P8_1_AMUXB = 5, /* Analog mux bus B */ + P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ + P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ + P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ + P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ + P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ + + /* P8.2 */ + P8_2_GPIO = 0, /* GPIO controls 'out' */ + P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_2_AMUXA = 4, /* Analog mux bus A */ + P8_2_AMUXB = 5, /* Analog mux bus B */ + P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ + P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ + P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ + P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ + P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ + P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ + P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ + P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ + P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ + + /* P8.3 */ + P8_3_GPIO = 0, /* GPIO controls 'out' */ + P8_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_3_AMUXA = 4, /* Analog mux bus A */ + P8_3_AMUXB = 5, /* Analog mux bus B */ + P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ + P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ + P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ + P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ + P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ + P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ + P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ + P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ + P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ + + /* P8.4 */ + P8_4_GPIO = 0, /* GPIO controls 'out' */ + P8_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_4_AMUXA = 4, /* Analog mux bus A */ + P8_4_AMUXB = 5, /* Analog mux bus B */ + P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ + P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */ + P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ + P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ + P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ + P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ + P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ + + /* P8.5 */ + P8_5_GPIO = 0, /* GPIO controls 'out' */ + P8_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_5_AMUXA = 4, /* Analog mux bus A */ + P8_5_AMUXB = 5, /* Analog mux bus B */ + P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ + P8_5_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ + P8_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ + P8_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ + P8_5_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ + P8_5_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ + P8_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */ + + /* P8.6 */ + P8_6_GPIO = 0, /* GPIO controls 'out' */ + P8_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_6_AMUXA = 4, /* Analog mux bus A */ + P8_6_AMUXB = 5, /* Analog mux bus B */ + P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ + P8_6_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:0 */ + P8_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ + P8_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ + P8_6_LCD_COM60 = 12, /* Digital Deep Sleep - lcd.com[60]:0 */ + P8_6_LCD_SEG60 = 13, /* Digital Deep Sleep - lcd.seg[60]:0 */ + P8_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:0 */ + + /* P8.7 */ + P8_7_GPIO = 0, /* GPIO controls 'out' */ + P8_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P8_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P8_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P8_7_AMUXA = 4, /* Analog mux bus A */ + P8_7_AMUXB = 5, /* Analog mux bus B */ + P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P8_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ + P8_7_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ + P8_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ + P8_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ + P8_7_LCD_COM61 = 12, /* Digital Deep Sleep - lcd.com[61]:0 */ + P8_7_LCD_SEG61 = 13, /* Digital Deep Sleep - lcd.seg[61]:0 */ + P8_7_SCB3_SPI_SELECT2 = 20, /* Digital Active - scb[3].spi_select2:0 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* GPIO controls 'out' */ + P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_0_AMUXA = 4, /* Analog mux bus A */ + P9_0_AMUXB = 5, /* Analog mux bus B */ + P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ + P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ + P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ + P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* GPIO controls 'out' */ + P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_1_AMUXA = 4, /* Analog mux bus A */ + P9_1_AMUXB = 5, /* Analog mux bus B */ + P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ + P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ + P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ + P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* GPIO controls 'out' */ + P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_2_AMUXA = 4, /* Analog mux bus A */ + P9_2_AMUXB = 5, /* Analog mux bus B */ + P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ + P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ + P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ + P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* GPIO controls 'out' */ + P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_3_AMUXA = 4, /* Analog mux bus A */ + P9_3_AMUXB = 5, /* Analog mux bus B */ + P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ + P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ + P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ + P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P9.4 */ + P9_4_GPIO = 0, /* GPIO controls 'out' */ + P9_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_4_AMUXA = 4, /* Analog mux bus A */ + P9_4_AMUXB = 5, /* Analog mux bus B */ + P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */ + P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ + P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */ + P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */ + P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */ + P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */ + P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ + + /* P9.5 */ + P9_5_GPIO = 0, /* GPIO controls 'out' */ + P9_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_5_AMUXA = 4, /* Analog mux bus A */ + P9_5_AMUXB = 5, /* Analog mux bus B */ + P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_5_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:5 */ + P9_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */ + P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:67 */ + P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:67 */ + P9_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:1 */ + P9_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:1 */ + P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */ + + /* P9.6 */ + P9_6_GPIO = 0, /* GPIO controls 'out' */ + P9_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_6_AMUXA = 4, /* Analog mux bus A */ + P9_6_AMUXB = 5, /* Analog mux bus B */ + P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_6_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ + P9_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */ + P9_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:68 */ + P9_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:68 */ + P9_6_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:1 */ + P9_6_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:1 */ + P9_6_SCB2_SPI_SELECT3 = 20, /* Digital Active - scb[2].spi_select3:0 */ + + /* P9.7 */ + P9_7_GPIO = 0, /* GPIO controls 'out' */ + P9_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P9_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P9_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P9_7_AMUXA = 4, /* Analog mux bus A */ + P9_7_AMUXB = 5, /* Analog mux bus B */ + P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ + P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ + P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */ + P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */ + P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */ + P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* GPIO controls 'out' */ + P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_0_AMUXA = 4, /* Analog mux bus A */ + P10_0_AMUXB = 5, /* Analog mux bus B */ + P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ + P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ + P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ + P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* GPIO controls 'out' */ + P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_1_AMUXA = 4, /* Analog mux bus A */ + P10_1_AMUXB = 5, /* Analog mux bus B */ + P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ + P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ + P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ + P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + + /* P10.2 */ + P10_2_GPIO = 0, /* GPIO controls 'out' */ + P10_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_2_AMUXA = 4, /* Analog mux bus A */ + P10_2_AMUXB = 5, /* Analog mux bus B */ + P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ + P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ + P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ + P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ + P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ + P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ + P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ + P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ + P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ + + /* P10.3 */ + P10_3_GPIO = 0, /* GPIO controls 'out' */ + P10_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_3_AMUXA = 4, /* Analog mux bus A */ + P10_3_AMUXB = 5, /* Analog mux bus B */ + P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ + P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ + P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ + P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ + P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ + P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ + P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ + P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ + P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ + + /* P10.4 */ + P10_4_GPIO = 0, /* GPIO controls 'out' */ + P10_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_4_AMUXA = 4, /* Analog mux bus A */ + P10_4_AMUXB = 5, /* Analog mux bus B */ + P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ + P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ + P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ + P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ + P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ + P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ + P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ + P10_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:0 */ + + /* P10.5 */ + P10_5_GPIO = 0, /* GPIO controls 'out' */ + P10_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_5_AMUXA = 4, /* Analog mux bus A */ + P10_5_AMUXB = 5, /* Analog mux bus B */ + P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ + P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ + P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ + P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ + P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ + P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ + P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ + P10_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:0 */ + + /* P10.6 */ + P10_6_GPIO = 0, /* GPIO controls 'out' */ + P10_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P10_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P10_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P10_6_AMUXA = 4, /* Analog mux bus A */ + P10_6_AMUXB = 5, /* Analog mux bus B */ + P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ + P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ + P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */ + P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */ + P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */ + P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */ + P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ + + /* P11.0 */ + P11_0_GPIO = 0, /* GPIO controls 'out' */ + P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_0_AMUXA = 4, /* Analog mux bus A */ + P11_0_AMUXB = 5, /* Analog mux bus B */ + P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ + P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ + P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ + P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ + P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ + P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ + P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ + P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ + P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ + P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ + + /* P11.1 */ + P11_1_GPIO = 0, /* GPIO controls 'out' */ + P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_1_AMUXA = 4, /* Analog mux bus A */ + P11_1_AMUXB = 5, /* Analog mux bus B */ + P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ + P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ + P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ + P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ + P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ + P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ + P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ + P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ + P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ + P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* GPIO controls 'out' */ + P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_2_AMUXA = 4, /* Analog mux bus A */ + P11_2_AMUXB = 5, /* Analog mux bus B */ + P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ + P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ + P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* GPIO controls 'out' */ + P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_3_AMUXA = 4, /* Analog mux bus A */ + P11_3_AMUXB = 5, /* Analog mux bus B */ + P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ + P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ + P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* GPIO controls 'out' */ + P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_4_AMUXA = 4, /* Analog mux bus A */ + P11_4_AMUXB = 5, /* Analog mux bus B */ + P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ + P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ + P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* GPIO controls 'out' */ + P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_5_AMUXA = 4, /* Analog mux bus A */ + P11_5_AMUXB = 5, /* Analog mux bus B */ + P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ + P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ + P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* GPIO controls 'out' */ + P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_6_AMUXA = 4, /* Analog mux bus A */ + P11_6_AMUXB = 5, /* Analog mux bus B */ + P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ + P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ + P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* GPIO controls 'out' */ + P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P11_7_AMUXA = 4, /* Analog mux bus A */ + P11_7_AMUXB = 5, /* Analog mux bus B */ + P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ + + /* P12.0 */ + P12_0_GPIO = 0, /* GPIO controls 'out' */ + P12_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_0_AMUXA = 4, /* Analog mux bus A */ + P12_0_AMUXB = 5, /* Analog mux bus B */ + P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */ + P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ + P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */ + P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */ + P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */ + P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */ + P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ + P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ + P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ + P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ + P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ + + /* P12.1 */ + P12_1_GPIO = 0, /* GPIO controls 'out' */ + P12_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_1_AMUXA = 4, /* Analog mux bus A */ + P12_1_AMUXB = 5, /* Analog mux bus B */ + P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */ + P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ + P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */ + P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */ + P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */ + P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */ + P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ + P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ + P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ + P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ + P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ + + /* P12.2 */ + P12_2_GPIO = 0, /* GPIO controls 'out' */ + P12_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_2_AMUXA = 4, /* Analog mux bus A */ + P12_2_AMUXB = 5, /* Analog mux bus B */ + P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */ + P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ + P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */ + P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */ + P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */ + P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */ + P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ + P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ + P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ + + /* P12.3 */ + P12_3_GPIO = 0, /* GPIO controls 'out' */ + P12_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_3_AMUXA = 4, /* Analog mux bus A */ + P12_3_AMUXB = 5, /* Analog mux bus B */ + P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */ + P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ + P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */ + P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */ + P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */ + P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */ + P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ + P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ + P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ + + /* P12.4 */ + P12_4_GPIO = 0, /* GPIO controls 'out' */ + P12_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_4_AMUXA = 4, /* Analog mux bus A */ + P12_4_AMUXB = 5, /* Analog mux bus B */ + P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */ + P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ + P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */ + P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */ + P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */ + P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */ + P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ + P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ + P12_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:1 */ + + /* P12.5 */ + P12_5_GPIO = 0, /* GPIO controls 'out' */ + P12_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_5_AMUXA = 4, /* Analog mux bus A */ + P12_5_AMUXB = 5, /* Analog mux bus B */ + P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */ + P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ + P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */ + P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */ + P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */ + P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */ + P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ + P12_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:1 */ + + /* P12.6 */ + P12_6_GPIO = 0, /* GPIO controls 'out' */ + P12_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_6_AMUXA = 4, /* Analog mux bus A */ + P12_6_AMUXB = 5, /* Analog mux bus B */ + P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ + P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ + P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ + P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ + P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ + P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ + P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ + + /* P12.7 */ + P12_7_GPIO = 0, /* GPIO controls 'out' */ + P12_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P12_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P12_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P12_7_AMUXA = 4, /* Analog mux bus A */ + P12_7_AMUXB = 5, /* Analog mux bus B */ + P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ + P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ + P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ + P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ + P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ + P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ + + /* P13.0 */ + P13_0_GPIO = 0, /* GPIO controls 'out' */ + P13_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_0_AMUXA = 4, /* Analog mux bus A */ + P13_0_AMUXB = 5, /* Analog mux bus B */ + P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ + P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */ + P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */ + P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */ + P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */ + P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */ + P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ + P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ + P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */ + P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */ + + /* P13.1 */ + P13_1_GPIO = 0, /* GPIO controls 'out' */ + P13_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_1_AMUXA = 4, /* Analog mux bus A */ + P13_1_AMUXB = 5, /* Analog mux bus B */ + P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ + P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ + P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */ + P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */ + P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */ + P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */ + P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ + P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ + P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ + P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */ + + /* P13.6 */ + P13_6_GPIO = 0, /* GPIO controls 'out' */ + P13_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_6_AMUXA = 4, /* Analog mux bus A */ + P13_6_AMUXB = 5, /* Analog mux bus B */ + P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ + P13_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:1 */ + P13_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:99 */ + P13_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:99 */ + P13_6_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:1 */ + P13_6_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:1 */ + P13_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:1 */ + + /* P13.7 */ + P13_7_GPIO = 0, /* GPIO controls 'out' */ + P13_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ + P13_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ + P13_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ + P13_7_AMUXA = 4, /* Analog mux bus A */ + P13_7_AMUXB = 5, /* Analog mux bus B */ + P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ + P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ + P13_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ + P13_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ + P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ + P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ + P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ + P13_7_LCD_SEG38 = 13 /* Digital Deep Sleep - lcd.seg[38]:1 */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC63_116_BGA_BLE_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/psoc63_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/psoc63_config.h new file mode 100644 index 0000000000..f166c7e62d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/psoc63_config.h @@ -0,0 +1,3000 @@ +/***************************************************************************//** +* \file psoc63_config.h +* +* \brief +* PSoC 63 device configuration header +* +* \note +* Generator version: 1.2.0.117 +* Database revision: rev#1034984 +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#ifndef _PSOC63_CONFIG_H_ +#define _PSOC63_CONFIG_H_ + +/* Clock Connections */ +typedef enum +{ + PCLK_SCB0_CLOCK = 0, /* scb[0].clock */ + PCLK_SCB1_CLOCK = 1, /* scb[1].clock */ + PCLK_SCB2_CLOCK = 2, /* scb[2].clock */ + PCLK_SCB3_CLOCK = 3, /* scb[3].clock */ + PCLK_SCB4_CLOCK = 4, /* scb[4].clock */ + PCLK_SCB5_CLOCK = 5, /* scb[5].clock */ + PCLK_SCB6_CLOCK = 6, /* scb[6].clock */ + PCLK_SCB7_CLOCK = 7, /* scb[7].clock */ + PCLK_SCB8_CLOCK = 8, /* scb[8].clock */ + PCLK_UDB_CLOCKS0 = 9, /* udb.clocks[0] */ + PCLK_UDB_CLOCKS1 = 10, /* udb.clocks[1] */ + PCLK_UDB_CLOCKS2 = 11, /* udb.clocks[2] */ + PCLK_UDB_CLOCKS3 = 12, /* udb.clocks[3] */ + PCLK_UDB_CLOCKS4 = 13, /* udb.clocks[4] */ + PCLK_UDB_CLOCKS5 = 14, /* udb.clocks[5] */ + PCLK_UDB_CLOCKS6 = 15, /* udb.clocks[6] */ + PCLK_UDB_CLOCKS7 = 16, /* udb.clocks[7] */ + PCLK_SMARTIO8_CLOCK = 17, /* smartio[8].clock */ + PCLK_SMARTIO9_CLOCK = 18, /* smartio[9].clock */ + PCLK_TCPWM0_CLOCKS0 = 19, /* tcpwm[0].clocks[0] */ + PCLK_TCPWM0_CLOCKS1 = 20, /* tcpwm[0].clocks[1] */ + PCLK_TCPWM0_CLOCKS2 = 21, /* tcpwm[0].clocks[2] */ + PCLK_TCPWM0_CLOCKS3 = 22, /* tcpwm[0].clocks[3] */ + PCLK_TCPWM0_CLOCKS4 = 23, /* tcpwm[0].clocks[4] */ + PCLK_TCPWM0_CLOCKS5 = 24, /* tcpwm[0].clocks[5] */ + PCLK_TCPWM0_CLOCKS6 = 25, /* tcpwm[0].clocks[6] */ + PCLK_TCPWM0_CLOCKS7 = 26, /* tcpwm[0].clocks[7] */ + PCLK_TCPWM1_CLOCKS0 = 27, /* tcpwm[1].clocks[0] */ + PCLK_TCPWM1_CLOCKS1 = 28, /* tcpwm[1].clocks[1] */ + PCLK_TCPWM1_CLOCKS2 = 29, /* tcpwm[1].clocks[2] */ + PCLK_TCPWM1_CLOCKS3 = 30, /* tcpwm[1].clocks[3] */ + PCLK_TCPWM1_CLOCKS4 = 31, /* tcpwm[1].clocks[4] */ + PCLK_TCPWM1_CLOCKS5 = 32, /* tcpwm[1].clocks[5] */ + PCLK_TCPWM1_CLOCKS6 = 33, /* tcpwm[1].clocks[6] */ + PCLK_TCPWM1_CLOCKS7 = 34, /* tcpwm[1].clocks[7] */ + PCLK_TCPWM1_CLOCKS8 = 35, /* tcpwm[1].clocks[8] */ + PCLK_TCPWM1_CLOCKS9 = 36, /* tcpwm[1].clocks[9] */ + PCLK_TCPWM1_CLOCKS10 = 37, /* tcpwm[1].clocks[10] */ + PCLK_TCPWM1_CLOCKS11 = 38, /* tcpwm[1].clocks[11] */ + PCLK_TCPWM1_CLOCKS12 = 39, /* tcpwm[1].clocks[12] */ + PCLK_TCPWM1_CLOCKS13 = 40, /* tcpwm[1].clocks[13] */ + PCLK_TCPWM1_CLOCKS14 = 41, /* tcpwm[1].clocks[14] */ + PCLK_TCPWM1_CLOCKS15 = 42, /* tcpwm[1].clocks[15] */ + PCLK_TCPWM1_CLOCKS16 = 43, /* tcpwm[1].clocks[16] */ + PCLK_TCPWM1_CLOCKS17 = 44, /* tcpwm[1].clocks[17] */ + PCLK_TCPWM1_CLOCKS18 = 45, /* tcpwm[1].clocks[18] */ + PCLK_TCPWM1_CLOCKS19 = 46, /* tcpwm[1].clocks[19] */ + PCLK_TCPWM1_CLOCKS20 = 47, /* tcpwm[1].clocks[20] */ + PCLK_TCPWM1_CLOCKS21 = 48, /* tcpwm[1].clocks[21] */ + PCLK_TCPWM1_CLOCKS22 = 49, /* tcpwm[1].clocks[22] */ + PCLK_TCPWM1_CLOCKS23 = 50, /* tcpwm[1].clocks[23] */ + PCLK_CSD_CLOCK = 51, /* csd.clock */ + PCLK_LCD_CLOCK = 52, /* lcd.clock */ + PCLK_PROFILE_CLOCK_PROFILE = 53, /* profile.clock_profile */ + PCLK_CPUSS_CLOCK_TRACE_IN = 54, /* cpuss.clock_trace_in */ + PCLK_PASS_CLOCK_CTDAC = 55, /* pass.clock_ctdac */ + PCLK_PASS_CLOCK_PUMP_PERI = 56, /* pass.clock_pump_peri */ + PCLK_PASS_CLOCK_SAR = 57, /* pass.clock_sar */ + PCLK_USB_CLOCK_DEV_BRS = 58 /* usb.clock_dev_brs */ +} en_clk_dst_t; + +/* Trigger Group */ +/* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. +* The constants are divided into four types because each signal of the TrigMux driver has a path +* through two multiplexers: the reduction multiplexer and the distribution multiplexer. This +* requires two calls for Cy_TrigMux_Connect() function. The first call - for the reduction +* multiplexer, the second call - for the distribution multiplexer. +* +* The four types of inputs/output parameters: +* 1) Parameters for reduction multiplexer's inputs (input signals of TrigMux) +* 2) Parameters for reduction multiplexer's outputs (intermediate signals); +* 3) Parameters for distribution multiplexer's inputs (intermediate signals); +* 4) Parameters for distribution multiplexer's outputs (output signals of TrigMux). +* +* The Cy_TrigMux_Connect() inTrig parameter can have 1) and 3) types parameters. The outTrig +* parameter can have 2) and 4) types parameters. +* The names of the constants for these parameters have the following format: +* +* 1) For reduction multiplexer's inputs: +* TRIG_IN_ +* the reduction multiplexer number; +* - the name of the IP block which is the source of the signal; +* - the source signal number in the IP block. +* +* Example: +* TRIG11_IN_TCPWM0_TR_OVERFLOW3 - the TCPWM0 tr_overflow[3] input of reduction multiplexer#11. +* +* 2) For reduction multiplexer's outputs: +* TRIG_OUT_TR_GROUP_INPUT +* - the reduction multiplexer number; +* - the distribution multiplexer number; +* - the input number of the distribution multiplexer. +* +* Example: +* TRIG11_OUT_TR_GROUP0_INPUT23 - Input#23 of the distribution multiplexer#0 is the destination +* of the reduction multiplexer#11. +* +* 3) For distribution multiplexer's inputs: +* TRIG_IN_TR_GROUP_OUTPUT +* - the reduction multiplexer number; +* - the distribution multiplexer number; +* - the output number of the reduction multiplexer; +* +* Example: +* TRIG0_IN_TR_GROUP11_OUTPUT15 - Output#15 of the reduction multiplexer#11 is the source of the +* distribution multiplexer#0. +* +* 4) For distribution multiplexer's outputs: +* TRIG_OUT_ +* - the distribution multiplexer number; +* - the name of the IP block which is the destination of the signal; +* - the input signal number in the IP block. +* +* Example: +* TRIG0_OUT_CPUSS_DW0_TR_IN3 - the DW0 tr_out[3] ouput of the distribution multiplexer 0.*/ +/* Trigger Group Inputs */ +/* Trigger Input Group 0 - DMA Request Assignments */ +typedef enum +{ + TRIG0_IN_CPUSS_ZERO = 0x00000000u, /* cpuss.zero */ + TRIG0_IN_TR_GROUP10_OUTPUT0 = 0x00000001u, /* tr_group[10].output[0] */ + TRIG0_IN_TR_GROUP10_OUTPUT1 = 0x00000002u, /* tr_group[10].output[1] */ + TRIG0_IN_TR_GROUP10_OUTPUT2 = 0x00000003u, /* tr_group[10].output[2] */ + TRIG0_IN_TR_GROUP10_OUTPUT3 = 0x00000004u, /* tr_group[10].output[3] */ + TRIG0_IN_TR_GROUP10_OUTPUT4 = 0x00000005u, /* tr_group[10].output[4] */ + TRIG0_IN_TR_GROUP10_OUTPUT5 = 0x00000006u, /* tr_group[10].output[5] */ + TRIG0_IN_TR_GROUP10_OUTPUT6 = 0x00000007u, /* tr_group[10].output[6] */ + TRIG0_IN_TR_GROUP10_OUTPUT7 = 0x00000008u, /* tr_group[10].output[7] */ + TRIG0_IN_TR_GROUP11_OUTPUT0 = 0x00000009u, /* tr_group[11].output[0] */ + TRIG0_IN_TR_GROUP11_OUTPUT1 = 0x0000000Au, /* tr_group[11].output[1] */ + TRIG0_IN_TR_GROUP11_OUTPUT2 = 0x0000000Bu, /* tr_group[11].output[2] */ + TRIG0_IN_TR_GROUP11_OUTPUT3 = 0x0000000Cu, /* tr_group[11].output[3] */ + TRIG0_IN_TR_GROUP11_OUTPUT4 = 0x0000000Du, /* tr_group[11].output[4] */ + TRIG0_IN_TR_GROUP11_OUTPUT5 = 0x0000000Eu, /* tr_group[11].output[5] */ + TRIG0_IN_TR_GROUP11_OUTPUT6 = 0x0000000Fu, /* tr_group[11].output[6] */ + TRIG0_IN_TR_GROUP11_OUTPUT7 = 0x00000010u, /* tr_group[11].output[7] */ + TRIG0_IN_TR_GROUP11_OUTPUT8 = 0x00000011u, /* tr_group[11].output[8] */ + TRIG0_IN_TR_GROUP11_OUTPUT9 = 0x00000012u, /* tr_group[11].output[9] */ + TRIG0_IN_TR_GROUP11_OUTPUT10 = 0x00000013u, /* tr_group[11].output[10] */ + TRIG0_IN_TR_GROUP11_OUTPUT11 = 0x00000014u, /* tr_group[11].output[11] */ + TRIG0_IN_TR_GROUP11_OUTPUT12 = 0x00000015u, /* tr_group[11].output[12] */ + TRIG0_IN_TR_GROUP11_OUTPUT13 = 0x00000016u, /* tr_group[11].output[13] */ + TRIG0_IN_TR_GROUP11_OUTPUT14 = 0x00000017u, /* tr_group[11].output[14] */ + TRIG0_IN_TR_GROUP11_OUTPUT15 = 0x00000018u, /* tr_group[11].output[15] */ + TRIG0_IN_TR_GROUP12_OUTPUT8 = 0x00000019u, /* tr_group[12].output[8] */ + TRIG0_IN_TR_GROUP12_OUTPUT9 = 0x0000001Au, /* tr_group[12].output[9] */ + TRIG0_IN_TR_GROUP13_OUTPUT0 = 0x0000001Bu, /* tr_group[13].output[0] */ + TRIG0_IN_TR_GROUP13_OUTPUT1 = 0x0000001Cu, /* tr_group[13].output[1] */ + TRIG0_IN_TR_GROUP13_OUTPUT2 = 0x0000001Du, /* tr_group[13].output[2] */ + TRIG0_IN_TR_GROUP13_OUTPUT3 = 0x0000001Eu, /* tr_group[13].output[3] */ + TRIG0_IN_TR_GROUP13_OUTPUT4 = 0x0000001Fu, /* tr_group[13].output[4] */ + TRIG0_IN_TR_GROUP13_OUTPUT5 = 0x00000020u, /* tr_group[13].output[5] */ + TRIG0_IN_TR_GROUP13_OUTPUT6 = 0x00000021u, /* tr_group[13].output[6] */ + TRIG0_IN_TR_GROUP13_OUTPUT7 = 0x00000022u, /* tr_group[13].output[7] */ + TRIG0_IN_TR_GROUP13_OUTPUT8 = 0x00000023u, /* tr_group[13].output[8] */ + TRIG0_IN_TR_GROUP13_OUTPUT9 = 0x00000024u, /* tr_group[13].output[9] */ + TRIG0_IN_TR_GROUP13_OUTPUT10 = 0x00000025u, /* tr_group[13].output[10] */ + TRIG0_IN_TR_GROUP13_OUTPUT11 = 0x00000026u, /* tr_group[13].output[11] */ + TRIG0_IN_TR_GROUP13_OUTPUT12 = 0x00000027u, /* tr_group[13].output[12] */ + TRIG0_IN_TR_GROUP13_OUTPUT13 = 0x00000028u, /* tr_group[13].output[13] */ + TRIG0_IN_TR_GROUP13_OUTPUT14 = 0x00000029u, /* tr_group[13].output[14] */ + TRIG0_IN_TR_GROUP13_OUTPUT15 = 0x0000002Au, /* tr_group[13].output[15] */ + TRIG0_IN_TR_GROUP14_OUTPUT0 = 0x0000002Bu, /* tr_group[14].output[0] */ + TRIG0_IN_TR_GROUP14_OUTPUT1 = 0x0000002Cu, /* tr_group[14].output[1] */ + TRIG0_IN_TR_GROUP14_OUTPUT2 = 0x0000002Du, /* tr_group[14].output[2] */ + TRIG0_IN_TR_GROUP14_OUTPUT3 = 0x0000002Eu, /* tr_group[14].output[3] */ + TRIG0_IN_TR_GROUP14_OUTPUT4 = 0x0000002Fu, /* tr_group[14].output[4] */ + TRIG0_IN_TR_GROUP14_OUTPUT5 = 0x00000030u, /* tr_group[14].output[5] */ + TRIG0_IN_TR_GROUP14_OUTPUT6 = 0x00000031u, /* tr_group[14].output[6] */ + TRIG0_IN_TR_GROUP14_OUTPUT7 = 0x00000032u /* tr_group[14].output[7] */ +} en_trig_input_grp0_t; + +/* Trigger Input Group 1 - DMA Request Assignments */ +typedef enum +{ + TRIG1_IN_CPUSS_ZERO = 0x00000100u, /* cpuss.zero */ + TRIG1_IN_TR_GROUP10_OUTPUT0 = 0x00000101u, /* tr_group[10].output[0] */ + TRIG1_IN_TR_GROUP10_OUTPUT1 = 0x00000102u, /* tr_group[10].output[1] */ + TRIG1_IN_TR_GROUP10_OUTPUT2 = 0x00000103u, /* tr_group[10].output[2] */ + TRIG1_IN_TR_GROUP10_OUTPUT3 = 0x00000104u, /* tr_group[10].output[3] */ + TRIG1_IN_TR_GROUP10_OUTPUT4 = 0x00000105u, /* tr_group[10].output[4] */ + TRIG1_IN_TR_GROUP10_OUTPUT5 = 0x00000106u, /* tr_group[10].output[5] */ + TRIG1_IN_TR_GROUP10_OUTPUT6 = 0x00000107u, /* tr_group[10].output[6] */ + TRIG1_IN_TR_GROUP10_OUTPUT7 = 0x00000108u, /* tr_group[10].output[7] */ + TRIG1_IN_TR_GROUP11_OUTPUT0 = 0x00000109u, /* tr_group[11].output[0] */ + TRIG1_IN_TR_GROUP11_OUTPUT1 = 0x0000010Au, /* tr_group[11].output[1] */ + TRIG1_IN_TR_GROUP11_OUTPUT2 = 0x0000010Bu, /* tr_group[11].output[2] */ + TRIG1_IN_TR_GROUP11_OUTPUT3 = 0x0000010Cu, /* tr_group[11].output[3] */ + TRIG1_IN_TR_GROUP11_OUTPUT4 = 0x0000010Du, /* tr_group[11].output[4] */ + TRIG1_IN_TR_GROUP11_OUTPUT5 = 0x0000010Eu, /* tr_group[11].output[5] */ + TRIG1_IN_TR_GROUP11_OUTPUT6 = 0x0000010Fu, /* tr_group[11].output[6] */ + TRIG1_IN_TR_GROUP11_OUTPUT7 = 0x00000110u, /* tr_group[11].output[7] */ + TRIG1_IN_TR_GROUP11_OUTPUT8 = 0x00000111u, /* tr_group[11].output[8] */ + TRIG1_IN_TR_GROUP11_OUTPUT9 = 0x00000112u, /* tr_group[11].output[9] */ + TRIG1_IN_TR_GROUP11_OUTPUT10 = 0x00000113u, /* tr_group[11].output[10] */ + TRIG1_IN_TR_GROUP11_OUTPUT11 = 0x00000114u, /* tr_group[11].output[11] */ + TRIG1_IN_TR_GROUP11_OUTPUT12 = 0x00000115u, /* tr_group[11].output[12] */ + TRIG1_IN_TR_GROUP11_OUTPUT13 = 0x00000116u, /* tr_group[11].output[13] */ + TRIG1_IN_TR_GROUP11_OUTPUT14 = 0x00000117u, /* tr_group[11].output[14] */ + TRIG1_IN_TR_GROUP11_OUTPUT15 = 0x00000118u, /* tr_group[11].output[15] */ + TRIG1_IN_TR_GROUP12_OUTPUT8 = 0x00000119u, /* tr_group[12].output[8] */ + TRIG1_IN_TR_GROUP12_OUTPUT9 = 0x0000011Au, /* tr_group[12].output[9] */ + TRIG1_IN_TR_GROUP13_OUTPUT0 = 0x0000011Bu, /* tr_group[13].output[0] */ + TRIG1_IN_TR_GROUP13_OUTPUT1 = 0x0000011Cu, /* tr_group[13].output[1] */ + TRIG1_IN_TR_GROUP13_OUTPUT2 = 0x0000011Du, /* tr_group[13].output[2] */ + TRIG1_IN_TR_GROUP13_OUTPUT3 = 0x0000011Eu, /* tr_group[13].output[3] */ + TRIG1_IN_TR_GROUP13_OUTPUT4 = 0x0000011Fu, /* tr_group[13].output[4] */ + TRIG1_IN_TR_GROUP13_OUTPUT5 = 0x00000120u, /* tr_group[13].output[5] */ + TRIG1_IN_TR_GROUP13_OUTPUT6 = 0x00000121u, /* tr_group[13].output[6] */ + TRIG1_IN_TR_GROUP13_OUTPUT7 = 0x00000122u, /* tr_group[13].output[7] */ + TRIG1_IN_TR_GROUP13_OUTPUT8 = 0x00000123u, /* tr_group[13].output[8] */ + TRIG1_IN_TR_GROUP13_OUTPUT9 = 0x00000124u, /* tr_group[13].output[9] */ + TRIG1_IN_TR_GROUP13_OUTPUT10 = 0x00000125u, /* tr_group[13].output[10] */ + TRIG1_IN_TR_GROUP13_OUTPUT11 = 0x00000126u, /* tr_group[13].output[11] */ + TRIG1_IN_TR_GROUP13_OUTPUT12 = 0x00000127u, /* tr_group[13].output[12] */ + TRIG1_IN_TR_GROUP13_OUTPUT13 = 0x00000128u, /* tr_group[13].output[13] */ + TRIG1_IN_TR_GROUP13_OUTPUT14 = 0x00000129u, /* tr_group[13].output[14] */ + TRIG1_IN_TR_GROUP13_OUTPUT15 = 0x0000012Au, /* tr_group[13].output[15] */ + TRIG1_IN_TR_GROUP14_OUTPUT0 = 0x0000012Bu, /* tr_group[14].output[0] */ + TRIG1_IN_TR_GROUP14_OUTPUT1 = 0x0000012Cu, /* tr_group[14].output[1] */ + TRIG1_IN_TR_GROUP14_OUTPUT2 = 0x0000012Du, /* tr_group[14].output[2] */ + TRIG1_IN_TR_GROUP14_OUTPUT3 = 0x0000012Eu, /* tr_group[14].output[3] */ + TRIG1_IN_TR_GROUP14_OUTPUT4 = 0x0000012Fu, /* tr_group[14].output[4] */ + TRIG1_IN_TR_GROUP14_OUTPUT5 = 0x00000130u, /* tr_group[14].output[5] */ + TRIG1_IN_TR_GROUP14_OUTPUT6 = 0x00000131u, /* tr_group[14].output[6] */ + TRIG1_IN_TR_GROUP14_OUTPUT7 = 0x00000132u /* tr_group[14].output[7] */ +} en_trig_input_grp1_t; + +/* Trigger Input Group 2 - TCPWM trigger inputs */ +typedef enum +{ + TRIG2_IN_CPUSS_ZERO = 0x00000200u, /* cpuss.zero */ + TRIG2_IN_TR_GROUP10_OUTPUT0 = 0x00000201u, /* tr_group[10].output[0] */ + TRIG2_IN_TR_GROUP10_OUTPUT1 = 0x00000202u, /* tr_group[10].output[1] */ + TRIG2_IN_TR_GROUP10_OUTPUT2 = 0x00000203u, /* tr_group[10].output[2] */ + TRIG2_IN_TR_GROUP10_OUTPUT3 = 0x00000204u, /* tr_group[10].output[3] */ + TRIG2_IN_TR_GROUP10_OUTPUT4 = 0x00000205u, /* tr_group[10].output[4] */ + TRIG2_IN_TR_GROUP10_OUTPUT5 = 0x00000206u, /* tr_group[10].output[5] */ + TRIG2_IN_TR_GROUP10_OUTPUT6 = 0x00000207u, /* tr_group[10].output[6] */ + TRIG2_IN_TR_GROUP10_OUTPUT7 = 0x00000208u, /* tr_group[10].output[7] */ + TRIG2_IN_TR_GROUP11_OUTPUT0 = 0x00000209u, /* tr_group[11].output[0] */ + TRIG2_IN_TR_GROUP11_OUTPUT1 = 0x0000020Au, /* tr_group[11].output[1] */ + TRIG2_IN_TR_GROUP11_OUTPUT2 = 0x0000020Bu, /* tr_group[11].output[2] */ + TRIG2_IN_TR_GROUP11_OUTPUT3 = 0x0000020Cu, /* tr_group[11].output[3] */ + TRIG2_IN_TR_GROUP11_OUTPUT4 = 0x0000020Du, /* tr_group[11].output[4] */ + TRIG2_IN_TR_GROUP11_OUTPUT5 = 0x0000020Eu, /* tr_group[11].output[5] */ + TRIG2_IN_TR_GROUP11_OUTPUT6 = 0x0000020Fu, /* tr_group[11].output[6] */ + TRIG2_IN_TR_GROUP11_OUTPUT7 = 0x00000210u, /* tr_group[11].output[7] */ + TRIG2_IN_TR_GROUP11_OUTPUT8 = 0x00000211u, /* tr_group[11].output[8] */ + TRIG2_IN_TR_GROUP11_OUTPUT9 = 0x00000212u, /* tr_group[11].output[9] */ + TRIG2_IN_TR_GROUP11_OUTPUT10 = 0x00000213u, /* tr_group[11].output[10] */ + TRIG2_IN_TR_GROUP11_OUTPUT11 = 0x00000214u, /* tr_group[11].output[11] */ + TRIG2_IN_TR_GROUP11_OUTPUT12 = 0x00000215u, /* tr_group[11].output[12] */ + TRIG2_IN_TR_GROUP11_OUTPUT13 = 0x00000216u, /* tr_group[11].output[13] */ + TRIG2_IN_TR_GROUP11_OUTPUT14 = 0x00000217u, /* tr_group[11].output[14] */ + TRIG2_IN_TR_GROUP11_OUTPUT15 = 0x00000218u, /* tr_group[11].output[15] */ + TRIG2_IN_TR_GROUP12_OUTPUT0 = 0x00000219u, /* tr_group[12].output[0] */ + TRIG2_IN_TR_GROUP12_OUTPUT1 = 0x0000021Au, /* tr_group[12].output[1] */ + TRIG2_IN_TR_GROUP12_OUTPUT2 = 0x0000021Bu, /* tr_group[12].output[2] */ + TRIG2_IN_TR_GROUP12_OUTPUT3 = 0x0000021Cu, /* tr_group[12].output[3] */ + TRIG2_IN_TR_GROUP12_OUTPUT4 = 0x0000021Du, /* tr_group[12].output[4] */ + TRIG2_IN_TR_GROUP12_OUTPUT5 = 0x0000021Eu, /* tr_group[12].output[5] */ + TRIG2_IN_TR_GROUP12_OUTPUT6 = 0x0000021Fu, /* tr_group[12].output[6] */ + TRIG2_IN_TR_GROUP12_OUTPUT7 = 0x00000220u, /* tr_group[12].output[7] */ + TRIG2_IN_TR_GROUP13_OUTPUT16 = 0x00000221u, /* tr_group[13].output[16] */ + TRIG2_IN_TR_GROUP13_OUTPUT17 = 0x00000222u, /* tr_group[13].output[17] */ + TRIG2_IN_TR_GROUP14_OUTPUT8 = 0x00000223u, /* tr_group[14].output[8] */ + TRIG2_IN_TR_GROUP14_OUTPUT9 = 0x00000224u, /* tr_group[14].output[9] */ + TRIG2_IN_TR_GROUP14_OUTPUT10 = 0x00000225u, /* tr_group[14].output[10] */ + TRIG2_IN_TR_GROUP14_OUTPUT11 = 0x00000226u, /* tr_group[14].output[11] */ + TRIG2_IN_TR_GROUP14_OUTPUT12 = 0x00000227u, /* tr_group[14].output[12] */ + TRIG2_IN_TR_GROUP14_OUTPUT13 = 0x00000228u, /* tr_group[14].output[13] */ + TRIG2_IN_TR_GROUP14_OUTPUT14 = 0x00000229u, /* tr_group[14].output[14] */ + TRIG2_IN_TR_GROUP14_OUTPUT15 = 0x0000022Au /* tr_group[14].output[15] */ +} en_trig_input_grp2_t; + +/* Trigger Input Group 3 - TCPWM trigger inputs */ +typedef enum +{ + TRIG3_IN_CPUSS_ZERO = 0x00000300u, /* cpuss.zero */ + TRIG3_IN_TR_GROUP10_OUTPUT0 = 0x00000301u, /* tr_group[10].output[0] */ + TRIG3_IN_TR_GROUP10_OUTPUT1 = 0x00000302u, /* tr_group[10].output[1] */ + TRIG3_IN_TR_GROUP10_OUTPUT2 = 0x00000303u, /* tr_group[10].output[2] */ + TRIG3_IN_TR_GROUP10_OUTPUT3 = 0x00000304u, /* tr_group[10].output[3] */ + TRIG3_IN_TR_GROUP10_OUTPUT4 = 0x00000305u, /* tr_group[10].output[4] */ + TRIG3_IN_TR_GROUP10_OUTPUT5 = 0x00000306u, /* tr_group[10].output[5] */ + TRIG3_IN_TR_GROUP10_OUTPUT6 = 0x00000307u, /* tr_group[10].output[6] */ + TRIG3_IN_TR_GROUP10_OUTPUT7 = 0x00000308u, /* tr_group[10].output[7] */ + TRIG3_IN_TR_GROUP11_OUTPUT0 = 0x00000309u, /* tr_group[11].output[0] */ + TRIG3_IN_TR_GROUP11_OUTPUT1 = 0x0000030Au, /* tr_group[11].output[1] */ + TRIG3_IN_TR_GROUP11_OUTPUT2 = 0x0000030Bu, /* tr_group[11].output[2] */ + TRIG3_IN_TR_GROUP11_OUTPUT3 = 0x0000030Cu, /* tr_group[11].output[3] */ + TRIG3_IN_TR_GROUP11_OUTPUT4 = 0x0000030Du, /* tr_group[11].output[4] */ + TRIG3_IN_TR_GROUP11_OUTPUT5 = 0x0000030Eu, /* tr_group[11].output[5] */ + TRIG3_IN_TR_GROUP11_OUTPUT6 = 0x0000030Fu, /* tr_group[11].output[6] */ + TRIG3_IN_TR_GROUP11_OUTPUT7 = 0x00000310u, /* tr_group[11].output[7] */ + TRIG3_IN_TR_GROUP11_OUTPUT8 = 0x00000311u, /* tr_group[11].output[8] */ + TRIG3_IN_TR_GROUP11_OUTPUT9 = 0x00000312u, /* tr_group[11].output[9] */ + TRIG3_IN_TR_GROUP11_OUTPUT10 = 0x00000313u, /* tr_group[11].output[10] */ + TRIG3_IN_TR_GROUP11_OUTPUT11 = 0x00000314u, /* tr_group[11].output[11] */ + TRIG3_IN_TR_GROUP11_OUTPUT12 = 0x00000315u, /* tr_group[11].output[12] */ + TRIG3_IN_TR_GROUP11_OUTPUT13 = 0x00000316u, /* tr_group[11].output[13] */ + TRIG3_IN_TR_GROUP11_OUTPUT14 = 0x00000317u, /* tr_group[11].output[14] */ + TRIG3_IN_TR_GROUP11_OUTPUT15 = 0x00000318u, /* tr_group[11].output[15] */ + TRIG3_IN_TR_GROUP12_OUTPUT0 = 0x00000319u, /* tr_group[12].output[0] */ + TRIG3_IN_TR_GROUP12_OUTPUT1 = 0x0000031Au, /* tr_group[12].output[1] */ + TRIG3_IN_TR_GROUP12_OUTPUT2 = 0x0000031Bu, /* tr_group[12].output[2] */ + TRIG3_IN_TR_GROUP12_OUTPUT3 = 0x0000031Cu, /* tr_group[12].output[3] */ + TRIG3_IN_TR_GROUP12_OUTPUT4 = 0x0000031Du, /* tr_group[12].output[4] */ + TRIG3_IN_TR_GROUP12_OUTPUT5 = 0x0000031Eu, /* tr_group[12].output[5] */ + TRIG3_IN_TR_GROUP12_OUTPUT6 = 0x0000031Fu, /* tr_group[12].output[6] */ + TRIG3_IN_TR_GROUP12_OUTPUT7 = 0x00000320u, /* tr_group[12].output[7] */ + TRIG3_IN_TR_GROUP13_OUTPUT16 = 0x00000321u, /* tr_group[13].output[16] */ + TRIG3_IN_TR_GROUP13_OUTPUT17 = 0x00000322u, /* tr_group[13].output[17] */ + TRIG3_IN_TR_GROUP14_OUTPUT8 = 0x00000323u, /* tr_group[14].output[8] */ + TRIG3_IN_TR_GROUP14_OUTPUT9 = 0x00000324u, /* tr_group[14].output[9] */ + TRIG3_IN_TR_GROUP14_OUTPUT10 = 0x00000325u, /* tr_group[14].output[10] */ + TRIG3_IN_TR_GROUP14_OUTPUT11 = 0x00000326u, /* tr_group[14].output[11] */ + TRIG3_IN_TR_GROUP14_OUTPUT12 = 0x00000327u, /* tr_group[14].output[12] */ + TRIG3_IN_TR_GROUP14_OUTPUT13 = 0x00000328u, /* tr_group[14].output[13] */ + TRIG3_IN_TR_GROUP14_OUTPUT14 = 0x00000329u, /* tr_group[14].output[14] */ + TRIG3_IN_TR_GROUP14_OUTPUT15 = 0x0000032Au /* tr_group[14].output[15] */ +} en_trig_input_grp3_t; + +/* Trigger Input Group 4 - PROFILE trigger multiplexer */ +typedef enum +{ + TRIG4_IN_CPUSS_ZERO = 0x00000400u, /* cpuss.zero */ + TRIG4_IN_TR_GROUP10_OUTPUT0 = 0x00000401u, /* tr_group[10].output[0] */ + TRIG4_IN_TR_GROUP10_OUTPUT1 = 0x00000402u, /* tr_group[10].output[1] */ + TRIG4_IN_TR_GROUP10_OUTPUT2 = 0x00000403u, /* tr_group[10].output[2] */ + TRIG4_IN_TR_GROUP10_OUTPUT3 = 0x00000404u, /* tr_group[10].output[3] */ + TRIG4_IN_TR_GROUP10_OUTPUT4 = 0x00000405u, /* tr_group[10].output[4] */ + TRIG4_IN_TR_GROUP10_OUTPUT5 = 0x00000406u, /* tr_group[10].output[5] */ + TRIG4_IN_TR_GROUP10_OUTPUT6 = 0x00000407u, /* tr_group[10].output[6] */ + TRIG4_IN_TR_GROUP10_OUTPUT7 = 0x00000408u, /* tr_group[10].output[7] */ + TRIG4_IN_TR_GROUP11_OUTPUT0 = 0x00000409u, /* tr_group[11].output[0] */ + TRIG4_IN_TR_GROUP11_OUTPUT1 = 0x0000040Au, /* tr_group[11].output[1] */ + TRIG4_IN_TR_GROUP11_OUTPUT2 = 0x0000040Bu, /* tr_group[11].output[2] */ + TRIG4_IN_TR_GROUP11_OUTPUT3 = 0x0000040Cu, /* tr_group[11].output[3] */ + TRIG4_IN_TR_GROUP11_OUTPUT4 = 0x0000040Du, /* tr_group[11].output[4] */ + TRIG4_IN_TR_GROUP11_OUTPUT5 = 0x0000040Eu, /* tr_group[11].output[5] */ + TRIG4_IN_TR_GROUP11_OUTPUT6 = 0x0000040Fu, /* tr_group[11].output[6] */ + TRIG4_IN_TR_GROUP11_OUTPUT7 = 0x00000410u, /* tr_group[11].output[7] */ + TRIG4_IN_TR_GROUP11_OUTPUT8 = 0x00000411u, /* tr_group[11].output[8] */ + TRIG4_IN_TR_GROUP11_OUTPUT9 = 0x00000412u, /* tr_group[11].output[9] */ + TRIG4_IN_TR_GROUP11_OUTPUT10 = 0x00000413u, /* tr_group[11].output[10] */ + TRIG4_IN_TR_GROUP11_OUTPUT11 = 0x00000414u, /* tr_group[11].output[11] */ + TRIG4_IN_TR_GROUP11_OUTPUT12 = 0x00000415u, /* tr_group[11].output[12] */ + TRIG4_IN_TR_GROUP11_OUTPUT13 = 0x00000416u, /* tr_group[11].output[13] */ + TRIG4_IN_TR_GROUP11_OUTPUT14 = 0x00000417u, /* tr_group[11].output[14] */ + TRIG4_IN_TR_GROUP11_OUTPUT15 = 0x00000418u, /* tr_group[11].output[15] */ + TRIG4_IN_TR_GROUP12_OUTPUT0 = 0x00000419u, /* tr_group[12].output[0] */ + TRIG4_IN_TR_GROUP12_OUTPUT1 = 0x0000041Au, /* tr_group[12].output[1] */ + TRIG4_IN_TR_GROUP12_OUTPUT2 = 0x0000041Bu, /* tr_group[12].output[2] */ + TRIG4_IN_TR_GROUP12_OUTPUT3 = 0x0000041Cu, /* tr_group[12].output[3] */ + TRIG4_IN_TR_GROUP12_OUTPUT4 = 0x0000041Du, /* tr_group[12].output[4] */ + TRIG4_IN_TR_GROUP12_OUTPUT5 = 0x0000041Eu, /* tr_group[12].output[5] */ + TRIG4_IN_TR_GROUP12_OUTPUT6 = 0x0000041Fu, /* tr_group[12].output[6] */ + TRIG4_IN_TR_GROUP12_OUTPUT7 = 0x00000420u, /* tr_group[12].output[7] */ + TRIG4_IN_TR_GROUP13_OUTPUT16 = 0x00000421u, /* tr_group[13].output[16] */ + TRIG4_IN_TR_GROUP13_OUTPUT17 = 0x00000422u, /* tr_group[13].output[17] */ + TRIG4_IN_TR_GROUP14_OUTPUT8 = 0x00000423u, /* tr_group[14].output[8] */ + TRIG4_IN_TR_GROUP14_OUTPUT9 = 0x00000424u, /* tr_group[14].output[9] */ + TRIG4_IN_TR_GROUP14_OUTPUT10 = 0x00000425u, /* tr_group[14].output[10] */ + TRIG4_IN_TR_GROUP14_OUTPUT11 = 0x00000426u, /* tr_group[14].output[11] */ + TRIG4_IN_TR_GROUP14_OUTPUT12 = 0x00000427u, /* tr_group[14].output[12] */ + TRIG4_IN_TR_GROUP14_OUTPUT13 = 0x00000428u, /* tr_group[14].output[13] */ + TRIG4_IN_TR_GROUP14_OUTPUT14 = 0x00000429u, /* tr_group[14].output[14] */ + TRIG4_IN_TR_GROUP14_OUTPUT15 = 0x0000042Au /* tr_group[14].output[15] */ +} en_trig_input_grp4_t; + +/* Trigger Input Group 5 - CPUSS.CTI trigger multiplexer */ +typedef enum +{ + TRIG5_IN_CPUSS_ZERO = 0x00000500u, /* cpuss.zero */ + TRIG5_IN_TR_GROUP10_OUTPUT0 = 0x00000501u, /* tr_group[10].output[0] */ + TRIG5_IN_TR_GROUP10_OUTPUT1 = 0x00000502u, /* tr_group[10].output[1] */ + TRIG5_IN_TR_GROUP10_OUTPUT2 = 0x00000503u, /* tr_group[10].output[2] */ + TRIG5_IN_TR_GROUP10_OUTPUT3 = 0x00000504u, /* tr_group[10].output[3] */ + TRIG5_IN_TR_GROUP10_OUTPUT4 = 0x00000505u, /* tr_group[10].output[4] */ + TRIG5_IN_TR_GROUP10_OUTPUT5 = 0x00000506u, /* tr_group[10].output[5] */ + TRIG5_IN_TR_GROUP10_OUTPUT6 = 0x00000507u, /* tr_group[10].output[6] */ + TRIG5_IN_TR_GROUP10_OUTPUT7 = 0x00000508u, /* tr_group[10].output[7] */ + TRIG5_IN_TR_GROUP11_OUTPUT0 = 0x00000509u, /* tr_group[11].output[0] */ + TRIG5_IN_TR_GROUP11_OUTPUT1 = 0x0000050Au, /* tr_group[11].output[1] */ + TRIG5_IN_TR_GROUP11_OUTPUT2 = 0x0000050Bu, /* tr_group[11].output[2] */ + TRIG5_IN_TR_GROUP11_OUTPUT3 = 0x0000050Cu, /* tr_group[11].output[3] */ + TRIG5_IN_TR_GROUP11_OUTPUT4 = 0x0000050Du, /* tr_group[11].output[4] */ + TRIG5_IN_TR_GROUP11_OUTPUT5 = 0x0000050Eu, /* tr_group[11].output[5] */ + TRIG5_IN_TR_GROUP11_OUTPUT6 = 0x0000050Fu, /* tr_group[11].output[6] */ + TRIG5_IN_TR_GROUP11_OUTPUT7 = 0x00000510u, /* tr_group[11].output[7] */ + TRIG5_IN_TR_GROUP11_OUTPUT8 = 0x00000511u, /* tr_group[11].output[8] */ + TRIG5_IN_TR_GROUP11_OUTPUT9 = 0x00000512u, /* tr_group[11].output[9] */ + TRIG5_IN_TR_GROUP11_OUTPUT10 = 0x00000513u, /* tr_group[11].output[10] */ + TRIG5_IN_TR_GROUP11_OUTPUT11 = 0x00000514u, /* tr_group[11].output[11] */ + TRIG5_IN_TR_GROUP11_OUTPUT12 = 0x00000515u, /* tr_group[11].output[12] */ + TRIG5_IN_TR_GROUP11_OUTPUT13 = 0x00000516u, /* tr_group[11].output[13] */ + TRIG5_IN_TR_GROUP11_OUTPUT14 = 0x00000517u, /* tr_group[11].output[14] */ + TRIG5_IN_TR_GROUP11_OUTPUT15 = 0x00000518u, /* tr_group[11].output[15] */ + TRIG5_IN_TR_GROUP12_OUTPUT0 = 0x00000519u, /* tr_group[12].output[0] */ + TRIG5_IN_TR_GROUP12_OUTPUT1 = 0x0000051Au, /* tr_group[12].output[1] */ + TRIG5_IN_TR_GROUP12_OUTPUT2 = 0x0000051Bu, /* tr_group[12].output[2] */ + TRIG5_IN_TR_GROUP12_OUTPUT3 = 0x0000051Cu, /* tr_group[12].output[3] */ + TRIG5_IN_TR_GROUP12_OUTPUT4 = 0x0000051Du, /* tr_group[12].output[4] */ + TRIG5_IN_TR_GROUP12_OUTPUT5 = 0x0000051Eu, /* tr_group[12].output[5] */ + TRIG5_IN_TR_GROUP12_OUTPUT6 = 0x0000051Fu, /* tr_group[12].output[6] */ + TRIG5_IN_TR_GROUP12_OUTPUT7 = 0x00000520u, /* tr_group[12].output[7] */ + TRIG5_IN_TR_GROUP13_OUTPUT16 = 0x00000521u, /* tr_group[13].output[16] */ + TRIG5_IN_TR_GROUP13_OUTPUT17 = 0x00000522u, /* tr_group[13].output[17] */ + TRIG5_IN_TR_GROUP14_OUTPUT8 = 0x00000523u, /* tr_group[14].output[8] */ + TRIG5_IN_TR_GROUP14_OUTPUT9 = 0x00000524u, /* tr_group[14].output[9] */ + TRIG5_IN_TR_GROUP14_OUTPUT10 = 0x00000525u, /* tr_group[14].output[10] */ + TRIG5_IN_TR_GROUP14_OUTPUT11 = 0x00000526u, /* tr_group[14].output[11] */ + TRIG5_IN_TR_GROUP14_OUTPUT12 = 0x00000527u, /* tr_group[14].output[12] */ + TRIG5_IN_TR_GROUP14_OUTPUT13 = 0x00000528u, /* tr_group[14].output[13] */ + TRIG5_IN_TR_GROUP14_OUTPUT14 = 0x00000529u, /* tr_group[14].output[14] */ + TRIG5_IN_TR_GROUP14_OUTPUT15 = 0x0000052Au /* tr_group[14].output[15] */ +} en_trig_input_grp5_t; + +/* Trigger Input Group 6 - PASS trigger multiplexer */ +typedef enum +{ + TRIG6_IN_CPUSS_ZERO = 0x00000600u, /* cpuss.zero */ + TRIG6_IN_TR_GROUP10_OUTPUT0 = 0x00000601u, /* tr_group[10].output[0] */ + TRIG6_IN_TR_GROUP10_OUTPUT1 = 0x00000602u, /* tr_group[10].output[1] */ + TRIG6_IN_TR_GROUP10_OUTPUT2 = 0x00000603u, /* tr_group[10].output[2] */ + TRIG6_IN_TR_GROUP10_OUTPUT3 = 0x00000604u, /* tr_group[10].output[3] */ + TRIG6_IN_TR_GROUP10_OUTPUT4 = 0x00000605u, /* tr_group[10].output[4] */ + TRIG6_IN_TR_GROUP10_OUTPUT5 = 0x00000606u, /* tr_group[10].output[5] */ + TRIG6_IN_TR_GROUP10_OUTPUT6 = 0x00000607u, /* tr_group[10].output[6] */ + TRIG6_IN_TR_GROUP10_OUTPUT7 = 0x00000608u, /* tr_group[10].output[7] */ + TRIG6_IN_TR_GROUP11_OUTPUT0 = 0x00000609u, /* tr_group[11].output[0] */ + TRIG6_IN_TR_GROUP11_OUTPUT1 = 0x0000060Au, /* tr_group[11].output[1] */ + TRIG6_IN_TR_GROUP11_OUTPUT2 = 0x0000060Bu, /* tr_group[11].output[2] */ + TRIG6_IN_TR_GROUP11_OUTPUT3 = 0x0000060Cu, /* tr_group[11].output[3] */ + TRIG6_IN_TR_GROUP11_OUTPUT4 = 0x0000060Du, /* tr_group[11].output[4] */ + TRIG6_IN_TR_GROUP11_OUTPUT5 = 0x0000060Eu, /* tr_group[11].output[5] */ + TRIG6_IN_TR_GROUP11_OUTPUT6 = 0x0000060Fu, /* tr_group[11].output[6] */ + TRIG6_IN_TR_GROUP11_OUTPUT7 = 0x00000610u, /* tr_group[11].output[7] */ + TRIG6_IN_TR_GROUP11_OUTPUT8 = 0x00000611u, /* tr_group[11].output[8] */ + TRIG6_IN_TR_GROUP11_OUTPUT9 = 0x00000612u, /* tr_group[11].output[9] */ + TRIG6_IN_TR_GROUP11_OUTPUT10 = 0x00000613u, /* tr_group[11].output[10] */ + TRIG6_IN_TR_GROUP11_OUTPUT11 = 0x00000614u, /* tr_group[11].output[11] */ + TRIG6_IN_TR_GROUP11_OUTPUT12 = 0x00000615u, /* tr_group[11].output[12] */ + TRIG6_IN_TR_GROUP11_OUTPUT13 = 0x00000616u, /* tr_group[11].output[13] */ + TRIG6_IN_TR_GROUP11_OUTPUT14 = 0x00000617u, /* tr_group[11].output[14] */ + TRIG6_IN_TR_GROUP11_OUTPUT15 = 0x00000618u, /* tr_group[11].output[15] */ + TRIG6_IN_TR_GROUP12_OUTPUT0 = 0x00000619u, /* tr_group[12].output[0] */ + TRIG6_IN_TR_GROUP12_OUTPUT1 = 0x0000061Au, /* tr_group[12].output[1] */ + TRIG6_IN_TR_GROUP12_OUTPUT2 = 0x0000061Bu, /* tr_group[12].output[2] */ + TRIG6_IN_TR_GROUP12_OUTPUT3 = 0x0000061Cu, /* tr_group[12].output[3] */ + TRIG6_IN_TR_GROUP12_OUTPUT4 = 0x0000061Du, /* tr_group[12].output[4] */ + TRIG6_IN_TR_GROUP12_OUTPUT5 = 0x0000061Eu, /* tr_group[12].output[5] */ + TRIG6_IN_TR_GROUP12_OUTPUT6 = 0x0000061Fu, /* tr_group[12].output[6] */ + TRIG6_IN_TR_GROUP12_OUTPUT7 = 0x00000620u, /* tr_group[12].output[7] */ + TRIG6_IN_TR_GROUP13_OUTPUT16 = 0x00000621u, /* tr_group[13].output[16] */ + TRIG6_IN_TR_GROUP13_OUTPUT17 = 0x00000622u, /* tr_group[13].output[17] */ + TRIG6_IN_TR_GROUP14_OUTPUT8 = 0x00000623u, /* tr_group[14].output[8] */ + TRIG6_IN_TR_GROUP14_OUTPUT9 = 0x00000624u, /* tr_group[14].output[9] */ + TRIG6_IN_TR_GROUP14_OUTPUT10 = 0x00000625u, /* tr_group[14].output[10] */ + TRIG6_IN_TR_GROUP14_OUTPUT11 = 0x00000626u, /* tr_group[14].output[11] */ + TRIG6_IN_TR_GROUP14_OUTPUT12 = 0x00000627u, /* tr_group[14].output[12] */ + TRIG6_IN_TR_GROUP14_OUTPUT13 = 0x00000628u, /* tr_group[14].output[13] */ + TRIG6_IN_TR_GROUP14_OUTPUT14 = 0x00000629u, /* tr_group[14].output[14] */ + TRIG6_IN_TR_GROUP14_OUTPUT15 = 0x0000062Au /* tr_group[14].output[15] */ +} en_trig_input_grp6_t; + +/* Trigger Input Group 7 - UDB general purpose trigger multiplexer */ +typedef enum +{ + TRIG7_IN_CPUSS_ZERO = 0x00000700u, /* cpuss.zero */ + TRIG7_IN_TR_GROUP10_OUTPUT0 = 0x00000701u, /* tr_group[10].output[0] */ + TRIG7_IN_TR_GROUP10_OUTPUT1 = 0x00000702u, /* tr_group[10].output[1] */ + TRIG7_IN_TR_GROUP10_OUTPUT2 = 0x00000703u, /* tr_group[10].output[2] */ + TRIG7_IN_TR_GROUP10_OUTPUT3 = 0x00000704u, /* tr_group[10].output[3] */ + TRIG7_IN_TR_GROUP10_OUTPUT4 = 0x00000705u, /* tr_group[10].output[4] */ + TRIG7_IN_TR_GROUP10_OUTPUT5 = 0x00000706u, /* tr_group[10].output[5] */ + TRIG7_IN_TR_GROUP10_OUTPUT6 = 0x00000707u, /* tr_group[10].output[6] */ + TRIG7_IN_TR_GROUP10_OUTPUT7 = 0x00000708u, /* tr_group[10].output[7] */ + TRIG7_IN_TR_GROUP11_OUTPUT0 = 0x00000709u, /* tr_group[11].output[0] */ + TRIG7_IN_TR_GROUP11_OUTPUT1 = 0x0000070Au, /* tr_group[11].output[1] */ + TRIG7_IN_TR_GROUP11_OUTPUT2 = 0x0000070Bu, /* tr_group[11].output[2] */ + TRIG7_IN_TR_GROUP11_OUTPUT3 = 0x0000070Cu, /* tr_group[11].output[3] */ + TRIG7_IN_TR_GROUP11_OUTPUT4 = 0x0000070Du, /* tr_group[11].output[4] */ + TRIG7_IN_TR_GROUP11_OUTPUT5 = 0x0000070Eu, /* tr_group[11].output[5] */ + TRIG7_IN_TR_GROUP11_OUTPUT6 = 0x0000070Fu, /* tr_group[11].output[6] */ + TRIG7_IN_TR_GROUP11_OUTPUT7 = 0x00000710u, /* tr_group[11].output[7] */ + TRIG7_IN_TR_GROUP11_OUTPUT8 = 0x00000711u, /* tr_group[11].output[8] */ + TRIG7_IN_TR_GROUP11_OUTPUT9 = 0x00000712u, /* tr_group[11].output[9] */ + TRIG7_IN_TR_GROUP11_OUTPUT10 = 0x00000713u, /* tr_group[11].output[10] */ + TRIG7_IN_TR_GROUP11_OUTPUT11 = 0x00000714u, /* tr_group[11].output[11] */ + TRIG7_IN_TR_GROUP11_OUTPUT12 = 0x00000715u, /* tr_group[11].output[12] */ + TRIG7_IN_TR_GROUP11_OUTPUT13 = 0x00000716u, /* tr_group[11].output[13] */ + TRIG7_IN_TR_GROUP11_OUTPUT14 = 0x00000717u, /* tr_group[11].output[14] */ + TRIG7_IN_TR_GROUP11_OUTPUT15 = 0x00000718u, /* tr_group[11].output[15] */ + TRIG7_IN_TR_GROUP12_OUTPUT0 = 0x00000719u, /* tr_group[12].output[0] */ + TRIG7_IN_TR_GROUP12_OUTPUT1 = 0x0000071Au, /* tr_group[12].output[1] */ + TRIG7_IN_TR_GROUP12_OUTPUT2 = 0x0000071Bu, /* tr_group[12].output[2] */ + TRIG7_IN_TR_GROUP12_OUTPUT3 = 0x0000071Cu, /* tr_group[12].output[3] */ + TRIG7_IN_TR_GROUP12_OUTPUT4 = 0x0000071Du, /* tr_group[12].output[4] */ + TRIG7_IN_TR_GROUP12_OUTPUT5 = 0x0000071Eu, /* tr_group[12].output[5] */ + TRIG7_IN_TR_GROUP12_OUTPUT6 = 0x0000071Fu, /* tr_group[12].output[6] */ + TRIG7_IN_TR_GROUP12_OUTPUT7 = 0x00000720u, /* tr_group[12].output[7] */ + TRIG7_IN_TR_GROUP13_OUTPUT16 = 0x00000721u, /* tr_group[13].output[16] */ + TRIG7_IN_TR_GROUP13_OUTPUT17 = 0x00000722u, /* tr_group[13].output[17] */ + TRIG7_IN_TR_GROUP14_OUTPUT8 = 0x00000723u, /* tr_group[14].output[8] */ + TRIG7_IN_TR_GROUP14_OUTPUT9 = 0x00000724u, /* tr_group[14].output[9] */ + TRIG7_IN_TR_GROUP14_OUTPUT10 = 0x00000725u, /* tr_group[14].output[10] */ + TRIG7_IN_TR_GROUP14_OUTPUT11 = 0x00000726u, /* tr_group[14].output[11] */ + TRIG7_IN_TR_GROUP14_OUTPUT12 = 0x00000727u, /* tr_group[14].output[12] */ + TRIG7_IN_TR_GROUP14_OUTPUT13 = 0x00000728u, /* tr_group[14].output[13] */ + TRIG7_IN_TR_GROUP14_OUTPUT14 = 0x00000729u, /* tr_group[14].output[14] */ + TRIG7_IN_TR_GROUP14_OUTPUT15 = 0x0000072Au /* tr_group[14].output[15] */ +} en_trig_input_grp7_t; + +/* Trigger Input Group 8 - Trigger multiplexer to pins */ +typedef enum +{ + TRIG8_IN_CPUSS_ZERO = 0x00000800u, /* cpuss.zero */ + TRIG8_IN_TR_GROUP10_OUTPUT0 = 0x00000801u, /* tr_group[10].output[0] */ + TRIG8_IN_TR_GROUP10_OUTPUT1 = 0x00000802u, /* tr_group[10].output[1] */ + TRIG8_IN_TR_GROUP10_OUTPUT2 = 0x00000803u, /* tr_group[10].output[2] */ + TRIG8_IN_TR_GROUP10_OUTPUT3 = 0x00000804u, /* tr_group[10].output[3] */ + TRIG8_IN_TR_GROUP10_OUTPUT4 = 0x00000805u, /* tr_group[10].output[4] */ + TRIG8_IN_TR_GROUP10_OUTPUT5 = 0x00000806u, /* tr_group[10].output[5] */ + TRIG8_IN_TR_GROUP10_OUTPUT6 = 0x00000807u, /* tr_group[10].output[6] */ + TRIG8_IN_TR_GROUP10_OUTPUT7 = 0x00000808u, /* tr_group[10].output[7] */ + TRIG8_IN_TR_GROUP11_OUTPUT0 = 0x00000809u, /* tr_group[11].output[0] */ + TRIG8_IN_TR_GROUP11_OUTPUT1 = 0x0000080Au, /* tr_group[11].output[1] */ + TRIG8_IN_TR_GROUP11_OUTPUT2 = 0x0000080Bu, /* tr_group[11].output[2] */ + TRIG8_IN_TR_GROUP11_OUTPUT3 = 0x0000080Cu, /* tr_group[11].output[3] */ + TRIG8_IN_TR_GROUP11_OUTPUT4 = 0x0000080Du, /* tr_group[11].output[4] */ + TRIG8_IN_TR_GROUP11_OUTPUT5 = 0x0000080Eu, /* tr_group[11].output[5] */ + TRIG8_IN_TR_GROUP11_OUTPUT6 = 0x0000080Fu, /* tr_group[11].output[6] */ + TRIG8_IN_TR_GROUP11_OUTPUT7 = 0x00000810u, /* tr_group[11].output[7] */ + TRIG8_IN_TR_GROUP11_OUTPUT8 = 0x00000811u, /* tr_group[11].output[8] */ + TRIG8_IN_TR_GROUP11_OUTPUT9 = 0x00000812u, /* tr_group[11].output[9] */ + TRIG8_IN_TR_GROUP11_OUTPUT10 = 0x00000813u, /* tr_group[11].output[10] */ + TRIG8_IN_TR_GROUP11_OUTPUT11 = 0x00000814u, /* tr_group[11].output[11] */ + TRIG8_IN_TR_GROUP11_OUTPUT12 = 0x00000815u, /* tr_group[11].output[12] */ + TRIG8_IN_TR_GROUP11_OUTPUT13 = 0x00000816u, /* tr_group[11].output[13] */ + TRIG8_IN_TR_GROUP11_OUTPUT14 = 0x00000817u, /* tr_group[11].output[14] */ + TRIG8_IN_TR_GROUP11_OUTPUT15 = 0x00000818u, /* tr_group[11].output[15] */ + TRIG8_IN_TR_GROUP12_OUTPUT0 = 0x00000819u, /* tr_group[12].output[0] */ + TRIG8_IN_TR_GROUP12_OUTPUT1 = 0x0000081Au, /* tr_group[12].output[1] */ + TRIG8_IN_TR_GROUP12_OUTPUT2 = 0x0000081Bu, /* tr_group[12].output[2] */ + TRIG8_IN_TR_GROUP12_OUTPUT3 = 0x0000081Cu, /* tr_group[12].output[3] */ + TRIG8_IN_TR_GROUP12_OUTPUT4 = 0x0000081Du, /* tr_group[12].output[4] */ + TRIG8_IN_TR_GROUP12_OUTPUT5 = 0x0000081Eu, /* tr_group[12].output[5] */ + TRIG8_IN_TR_GROUP12_OUTPUT6 = 0x0000081Fu, /* tr_group[12].output[6] */ + TRIG8_IN_TR_GROUP12_OUTPUT7 = 0x00000820u, /* tr_group[12].output[7] */ + TRIG8_IN_TR_GROUP13_OUTPUT16 = 0x00000821u, /* tr_group[13].output[16] */ + TRIG8_IN_TR_GROUP13_OUTPUT17 = 0x00000822u, /* tr_group[13].output[17] */ + TRIG8_IN_TR_GROUP14_OUTPUT8 = 0x00000823u, /* tr_group[14].output[8] */ + TRIG8_IN_TR_GROUP14_OUTPUT9 = 0x00000824u, /* tr_group[14].output[9] */ + TRIG8_IN_TR_GROUP14_OUTPUT10 = 0x00000825u, /* tr_group[14].output[10] */ + TRIG8_IN_TR_GROUP14_OUTPUT11 = 0x00000826u, /* tr_group[14].output[11] */ + TRIG8_IN_TR_GROUP14_OUTPUT12 = 0x00000827u, /* tr_group[14].output[12] */ + TRIG8_IN_TR_GROUP14_OUTPUT13 = 0x00000828u, /* tr_group[14].output[13] */ + TRIG8_IN_TR_GROUP14_OUTPUT14 = 0x00000829u, /* tr_group[14].output[14] */ + TRIG8_IN_TR_GROUP14_OUTPUT15 = 0x0000082Au /* tr_group[14].output[15] */ +} en_trig_input_grp8_t; + +/* Trigger Input Group 9 - Feedback mux to USB DMA interface */ +typedef enum +{ + TRIG9_IN_CPUSS_ZERO = 0x00000900u, /* cpuss.zero */ + TRIG9_IN_CPUSS_DW0_TR_OUT0 = 0x00000901u, /* cpuss.dw0_tr_out[0] */ + TRIG9_IN_CPUSS_DW0_TR_OUT1 = 0x00000902u, /* cpuss.dw0_tr_out[1] */ + TRIG9_IN_CPUSS_DW0_TR_OUT2 = 0x00000903u, /* cpuss.dw0_tr_out[2] */ + TRIG9_IN_CPUSS_DW0_TR_OUT3 = 0x00000904u, /* cpuss.dw0_tr_out[3] */ + TRIG9_IN_CPUSS_DW0_TR_OUT4 = 0x00000905u, /* cpuss.dw0_tr_out[4] */ + TRIG9_IN_CPUSS_DW0_TR_OUT5 = 0x00000906u, /* cpuss.dw0_tr_out[5] */ + TRIG9_IN_CPUSS_DW0_TR_OUT6 = 0x00000907u, /* cpuss.dw0_tr_out[6] */ + TRIG9_IN_CPUSS_DW0_TR_OUT7 = 0x00000908u, /* cpuss.dw0_tr_out[7] */ + TRIG9_IN_CPUSS_DW0_TR_OUT8 = 0x00000909u, /* cpuss.dw0_tr_out[8] */ + TRIG9_IN_CPUSS_DW0_TR_OUT9 = 0x0000090Au, /* cpuss.dw0_tr_out[9] */ + TRIG9_IN_CPUSS_DW0_TR_OUT10 = 0x0000090Bu, /* cpuss.dw0_tr_out[10] */ + TRIG9_IN_CPUSS_DW0_TR_OUT11 = 0x0000090Cu, /* cpuss.dw0_tr_out[11] */ + TRIG9_IN_CPUSS_DW0_TR_OUT12 = 0x0000090Du, /* cpuss.dw0_tr_out[12] */ + TRIG9_IN_CPUSS_DW0_TR_OUT13 = 0x0000090Eu, /* cpuss.dw0_tr_out[13] */ + TRIG9_IN_CPUSS_DW0_TR_OUT14 = 0x0000090Fu, /* cpuss.dw0_tr_out[14] */ + TRIG9_IN_CPUSS_DW0_TR_OUT15 = 0x00000910u, /* cpuss.dw0_tr_out[15] */ + TRIG9_IN_CPUSS_DW1_TR_OUT0 = 0x00000911u, /* cpuss.dw1_tr_out[0] */ + TRIG9_IN_CPUSS_DW1_TR_OUT1 = 0x00000912u, /* cpuss.dw1_tr_out[1] */ + TRIG9_IN_CPUSS_DW1_TR_OUT2 = 0x00000913u, /* cpuss.dw1_tr_out[2] */ + TRIG9_IN_CPUSS_DW1_TR_OUT3 = 0x00000914u, /* cpuss.dw1_tr_out[3] */ + TRIG9_IN_CPUSS_DW1_TR_OUT4 = 0x00000915u, /* cpuss.dw1_tr_out[4] */ + TRIG9_IN_CPUSS_DW1_TR_OUT5 = 0x00000916u, /* cpuss.dw1_tr_out[5] */ + TRIG9_IN_CPUSS_DW1_TR_OUT6 = 0x00000917u, /* cpuss.dw1_tr_out[6] */ + TRIG9_IN_CPUSS_DW1_TR_OUT7 = 0x00000918u, /* cpuss.dw1_tr_out[7] */ + TRIG9_IN_CPUSS_DW1_TR_OUT8 = 0x00000919u, /* cpuss.dw1_tr_out[8] */ + TRIG9_IN_CPUSS_DW1_TR_OUT9 = 0x0000091Au, /* cpuss.dw1_tr_out[9] */ + TRIG9_IN_CPUSS_DW1_TR_OUT10 = 0x0000091Bu, /* cpuss.dw1_tr_out[10] */ + TRIG9_IN_CPUSS_DW1_TR_OUT11 = 0x0000091Cu, /* cpuss.dw1_tr_out[11] */ + TRIG9_IN_CPUSS_DW1_TR_OUT12 = 0x0000091Du, /* cpuss.dw1_tr_out[12] */ + TRIG9_IN_CPUSS_DW1_TR_OUT13 = 0x0000091Eu, /* cpuss.dw1_tr_out[13] */ + TRIG9_IN_CPUSS_DW1_TR_OUT14 = 0x0000091Fu, /* cpuss.dw1_tr_out[14] */ + TRIG9_IN_CPUSS_DW1_TR_OUT15 = 0x00000920u /* cpuss.dw1_tr_out[15] */ +} en_trig_input_grp9_t; + +/* Trigger Input Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */ +typedef enum +{ + TRIG10_IN_CPUSS_ZERO = 0x00000A00u, /* cpuss.zero */ + TRIG10_IN_CPUSS_DW0_TR_OUT0 = 0x00000A01u, /* cpuss.dw0_tr_out[0] */ + TRIG10_IN_CPUSS_DW0_TR_OUT1 = 0x00000A02u, /* cpuss.dw0_tr_out[1] */ + TRIG10_IN_CPUSS_DW0_TR_OUT2 = 0x00000A03u, /* cpuss.dw0_tr_out[2] */ + TRIG10_IN_CPUSS_DW0_TR_OUT3 = 0x00000A04u, /* cpuss.dw0_tr_out[3] */ + TRIG10_IN_CPUSS_DW0_TR_OUT4 = 0x00000A05u, /* cpuss.dw0_tr_out[4] */ + TRIG10_IN_CPUSS_DW0_TR_OUT5 = 0x00000A06u, /* cpuss.dw0_tr_out[5] */ + TRIG10_IN_CPUSS_DW0_TR_OUT6 = 0x00000A07u, /* cpuss.dw0_tr_out[6] */ + TRIG10_IN_CPUSS_DW0_TR_OUT7 = 0x00000A08u, /* cpuss.dw0_tr_out[7] */ + TRIG10_IN_CPUSS_DW0_TR_OUT8 = 0x00000A09u, /* cpuss.dw0_tr_out[8] */ + TRIG10_IN_CPUSS_DW0_TR_OUT9 = 0x00000A0Au, /* cpuss.dw0_tr_out[9] */ + TRIG10_IN_CPUSS_DW0_TR_OUT10 = 0x00000A0Bu, /* cpuss.dw0_tr_out[10] */ + TRIG10_IN_CPUSS_DW0_TR_OUT11 = 0x00000A0Cu, /* cpuss.dw0_tr_out[11] */ + TRIG10_IN_CPUSS_DW0_TR_OUT12 = 0x00000A0Du, /* cpuss.dw0_tr_out[12] */ + TRIG10_IN_CPUSS_DW0_TR_OUT13 = 0x00000A0Eu, /* cpuss.dw0_tr_out[13] */ + TRIG10_IN_CPUSS_DW0_TR_OUT14 = 0x00000A0Fu, /* cpuss.dw0_tr_out[14] */ + TRIG10_IN_CPUSS_DW0_TR_OUT15 = 0x00000A10u, /* cpuss.dw0_tr_out[15] */ + TRIG10_IN_CPUSS_DW1_TR_OUT0 = 0x00000A11u, /* cpuss.dw1_tr_out[0] */ + TRIG10_IN_CPUSS_DW1_TR_OUT1 = 0x00000A12u, /* cpuss.dw1_tr_out[1] */ + TRIG10_IN_CPUSS_DW1_TR_OUT2 = 0x00000A13u, /* cpuss.dw1_tr_out[2] */ + TRIG10_IN_CPUSS_DW1_TR_OUT3 = 0x00000A14u, /* cpuss.dw1_tr_out[3] */ + TRIG10_IN_CPUSS_DW1_TR_OUT4 = 0x00000A15u, /* cpuss.dw1_tr_out[4] */ + TRIG10_IN_CPUSS_DW1_TR_OUT5 = 0x00000A16u, /* cpuss.dw1_tr_out[5] */ + TRIG10_IN_CPUSS_DW1_TR_OUT6 = 0x00000A17u, /* cpuss.dw1_tr_out[6] */ + TRIG10_IN_CPUSS_DW1_TR_OUT7 = 0x00000A18u, /* cpuss.dw1_tr_out[7] */ + TRIG10_IN_CPUSS_DW1_TR_OUT8 = 0x00000A19u, /* cpuss.dw1_tr_out[8] */ + TRIG10_IN_CPUSS_DW1_TR_OUT9 = 0x00000A1Au, /* cpuss.dw1_tr_out[9] */ + TRIG10_IN_CPUSS_DW1_TR_OUT10 = 0x00000A1Bu, /* cpuss.dw1_tr_out[10] */ + TRIG10_IN_CPUSS_DW1_TR_OUT11 = 0x00000A1Cu, /* cpuss.dw1_tr_out[11] */ + TRIG10_IN_CPUSS_DW1_TR_OUT12 = 0x00000A1Du, /* cpuss.dw1_tr_out[12] */ + TRIG10_IN_CPUSS_DW1_TR_OUT13 = 0x00000A1Eu, /* cpuss.dw1_tr_out[13] */ + TRIG10_IN_CPUSS_DW1_TR_OUT14 = 0x00000A1Fu, /* cpuss.dw1_tr_out[14] */ + TRIG10_IN_CPUSS_DW1_TR_OUT15 = 0x00000A20u /* cpuss.dw1_tr_out[15] */ +} en_trig_input_grp10_t; + +/* Trigger Input Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */ +typedef enum +{ + TRIG11_IN_CPUSS_ZERO = 0x00000B00u, /* cpuss.zero */ + TRIG11_IN_TCPWM0_TR_OVERFLOW0 = 0x00000B01u, /* tcpwm[0].tr_overflow[0] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW1 = 0x00000B02u, /* tcpwm[0].tr_overflow[1] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW2 = 0x00000B03u, /* tcpwm[0].tr_overflow[2] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW3 = 0x00000B04u, /* tcpwm[0].tr_overflow[3] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW4 = 0x00000B05u, /* tcpwm[0].tr_overflow[4] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW5 = 0x00000B06u, /* tcpwm[0].tr_overflow[5] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW6 = 0x00000B07u, /* tcpwm[0].tr_overflow[6] */ + TRIG11_IN_TCPWM0_TR_OVERFLOW7 = 0x00000B08u, /* tcpwm[0].tr_overflow[7] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH0 = 0x00000B09u, /* tcpwm[0].tr_compare_match[0] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH1 = 0x00000B0Au, /* tcpwm[0].tr_compare_match[1] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH2 = 0x00000B0Bu, /* tcpwm[0].tr_compare_match[2] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH3 = 0x00000B0Cu, /* tcpwm[0].tr_compare_match[3] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH4 = 0x00000B0Du, /* tcpwm[0].tr_compare_match[4] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH5 = 0x00000B0Eu, /* tcpwm[0].tr_compare_match[5] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH6 = 0x00000B0Fu, /* tcpwm[0].tr_compare_match[6] */ + TRIG11_IN_TCPWM0_TR_COMPARE_MATCH7 = 0x00000B10u, /* tcpwm[0].tr_compare_match[7] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW0 = 0x00000B11u, /* tcpwm[0].tr_underflow[0] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW1 = 0x00000B12u, /* tcpwm[0].tr_underflow[1] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW2 = 0x00000B13u, /* tcpwm[0].tr_underflow[2] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW3 = 0x00000B14u, /* tcpwm[0].tr_underflow[3] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW4 = 0x00000B15u, /* tcpwm[0].tr_underflow[4] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW5 = 0x00000B16u, /* tcpwm[0].tr_underflow[5] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW6 = 0x00000B17u, /* tcpwm[0].tr_underflow[6] */ + TRIG11_IN_TCPWM0_TR_UNDERFLOW7 = 0x00000B18u, /* tcpwm[0].tr_underflow[7] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW0 = 0x00000B19u, /* tcpwm[1].tr_overflow[0] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW1 = 0x00000B1Au, /* tcpwm[1].tr_overflow[1] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW2 = 0x00000B1Bu, /* tcpwm[1].tr_overflow[2] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW3 = 0x00000B1Cu, /* tcpwm[1].tr_overflow[3] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW4 = 0x00000B1Du, /* tcpwm[1].tr_overflow[4] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW5 = 0x00000B1Eu, /* tcpwm[1].tr_overflow[5] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW6 = 0x00000B1Fu, /* tcpwm[1].tr_overflow[6] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW7 = 0x00000B20u, /* tcpwm[1].tr_overflow[7] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW8 = 0x00000B21u, /* tcpwm[1].tr_overflow[8] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW9 = 0x00000B22u, /* tcpwm[1].tr_overflow[9] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW10 = 0x00000B23u, /* tcpwm[1].tr_overflow[10] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW11 = 0x00000B24u, /* tcpwm[1].tr_overflow[11] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW12 = 0x00000B25u, /* tcpwm[1].tr_overflow[12] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW13 = 0x00000B26u, /* tcpwm[1].tr_overflow[13] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW14 = 0x00000B27u, /* tcpwm[1].tr_overflow[14] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW15 = 0x00000B28u, /* tcpwm[1].tr_overflow[15] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW16 = 0x00000B29u, /* tcpwm[1].tr_overflow[16] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW17 = 0x00000B2Au, /* tcpwm[1].tr_overflow[17] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW18 = 0x00000B2Bu, /* tcpwm[1].tr_overflow[18] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW19 = 0x00000B2Cu, /* tcpwm[1].tr_overflow[19] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW20 = 0x00000B2Du, /* tcpwm[1].tr_overflow[20] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW21 = 0x00000B2Eu, /* tcpwm[1].tr_overflow[21] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW22 = 0x00000B2Fu, /* tcpwm[1].tr_overflow[22] */ + TRIG11_IN_TCPWM1_TR_OVERFLOW23 = 0x00000B30u, /* tcpwm[1].tr_overflow[23] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH0 = 0x00000B31u, /* tcpwm[1].tr_compare_match[0] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH1 = 0x00000B32u, /* tcpwm[1].tr_compare_match[1] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH2 = 0x00000B33u, /* tcpwm[1].tr_compare_match[2] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH3 = 0x00000B34u, /* tcpwm[1].tr_compare_match[3] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH4 = 0x00000B35u, /* tcpwm[1].tr_compare_match[4] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH5 = 0x00000B36u, /* tcpwm[1].tr_compare_match[5] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH6 = 0x00000B37u, /* tcpwm[1].tr_compare_match[6] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH7 = 0x00000B38u, /* tcpwm[1].tr_compare_match[7] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH8 = 0x00000B39u, /* tcpwm[1].tr_compare_match[8] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH9 = 0x00000B3Au, /* tcpwm[1].tr_compare_match[9] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH10 = 0x00000B3Bu, /* tcpwm[1].tr_compare_match[10] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH11 = 0x00000B3Cu, /* tcpwm[1].tr_compare_match[11] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH12 = 0x00000B3Du, /* tcpwm[1].tr_compare_match[12] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH13 = 0x00000B3Eu, /* tcpwm[1].tr_compare_match[13] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH14 = 0x00000B3Fu, /* tcpwm[1].tr_compare_match[14] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH15 = 0x00000B40u, /* tcpwm[1].tr_compare_match[15] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH16 = 0x00000B41u, /* tcpwm[1].tr_compare_match[16] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH17 = 0x00000B42u, /* tcpwm[1].tr_compare_match[17] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH18 = 0x00000B43u, /* tcpwm[1].tr_compare_match[18] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH19 = 0x00000B44u, /* tcpwm[1].tr_compare_match[19] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH20 = 0x00000B45u, /* tcpwm[1].tr_compare_match[20] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH21 = 0x00000B46u, /* tcpwm[1].tr_compare_match[21] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH22 = 0x00000B47u, /* tcpwm[1].tr_compare_match[22] */ + TRIG11_IN_TCPWM1_TR_COMPARE_MATCH23 = 0x00000B48u, /* tcpwm[1].tr_compare_match[23] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW0 = 0x00000B49u, /* tcpwm[1].tr_underflow[0] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW1 = 0x00000B4Au, /* tcpwm[1].tr_underflow[1] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW2 = 0x00000B4Bu, /* tcpwm[1].tr_underflow[2] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW3 = 0x00000B4Cu, /* tcpwm[1].tr_underflow[3] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW4 = 0x00000B4Du, /* tcpwm[1].tr_underflow[4] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW5 = 0x00000B4Eu, /* tcpwm[1].tr_underflow[5] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW6 = 0x00000B4Fu, /* tcpwm[1].tr_underflow[6] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW7 = 0x00000B50u, /* tcpwm[1].tr_underflow[7] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW8 = 0x00000B51u, /* tcpwm[1].tr_underflow[8] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW9 = 0x00000B52u, /* tcpwm[1].tr_underflow[9] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW10 = 0x00000B53u, /* tcpwm[1].tr_underflow[10] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW11 = 0x00000B54u, /* tcpwm[1].tr_underflow[11] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW12 = 0x00000B55u, /* tcpwm[1].tr_underflow[12] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW13 = 0x00000B56u, /* tcpwm[1].tr_underflow[13] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW14 = 0x00000B57u, /* tcpwm[1].tr_underflow[14] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW15 = 0x00000B58u, /* tcpwm[1].tr_underflow[15] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW16 = 0x00000B59u, /* tcpwm[1].tr_underflow[16] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW17 = 0x00000B5Au, /* tcpwm[1].tr_underflow[17] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW18 = 0x00000B5Bu, /* tcpwm[1].tr_underflow[18] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW19 = 0x00000B5Cu, /* tcpwm[1].tr_underflow[19] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW20 = 0x00000B5Du, /* tcpwm[1].tr_underflow[20] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW21 = 0x00000B5Eu, /* tcpwm[1].tr_underflow[21] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW22 = 0x00000B5Fu, /* tcpwm[1].tr_underflow[22] */ + TRIG11_IN_TCPWM1_TR_UNDERFLOW23 = 0x00000B60u /* tcpwm[1].tr_underflow[23] */ +} en_trig_input_grp11_t; + +/* Trigger Input Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */ +typedef enum +{ + TRIG12_IN_CPUSS_ZERO = 0x00000C00u, /* cpuss.zero */ + TRIG12_IN_PERI_TR_IO_INPUT0 = 0x00000C01u, /* peri.tr_io_input[0] */ + TRIG12_IN_PERI_TR_IO_INPUT1 = 0x00000C02u, /* peri.tr_io_input[1] */ + TRIG12_IN_PERI_TR_IO_INPUT2 = 0x00000C03u, /* peri.tr_io_input[2] */ + TRIG12_IN_PERI_TR_IO_INPUT3 = 0x00000C04u, /* peri.tr_io_input[3] */ + TRIG12_IN_PERI_TR_IO_INPUT4 = 0x00000C05u, /* peri.tr_io_input[4] */ + TRIG12_IN_PERI_TR_IO_INPUT5 = 0x00000C06u, /* peri.tr_io_input[5] */ + TRIG12_IN_PERI_TR_IO_INPUT6 = 0x00000C07u, /* peri.tr_io_input[6] */ + TRIG12_IN_PERI_TR_IO_INPUT7 = 0x00000C08u, /* peri.tr_io_input[7] */ + TRIG12_IN_PERI_TR_IO_INPUT8 = 0x00000C09u, /* peri.tr_io_input[8] */ + TRIG12_IN_PERI_TR_IO_INPUT9 = 0x00000C0Au, /* peri.tr_io_input[9] */ + TRIG12_IN_PERI_TR_IO_INPUT10 = 0x00000C0Bu, /* peri.tr_io_input[10] */ + TRIG12_IN_PERI_TR_IO_INPUT11 = 0x00000C0Cu, /* peri.tr_io_input[11] */ + TRIG12_IN_PERI_TR_IO_INPUT12 = 0x00000C0Du, /* peri.tr_io_input[12] */ + TRIG12_IN_PERI_TR_IO_INPUT13 = 0x00000C0Eu, /* peri.tr_io_input[13] */ + TRIG12_IN_PERI_TR_IO_INPUT14 = 0x00000C0Fu, /* peri.tr_io_input[14] */ + TRIG12_IN_PERI_TR_IO_INPUT15 = 0x00000C10u, /* peri.tr_io_input[15] */ + TRIG12_IN_PERI_TR_IO_INPUT16 = 0x00000C11u, /* peri.tr_io_input[16] */ + TRIG12_IN_PERI_TR_IO_INPUT17 = 0x00000C12u, /* peri.tr_io_input[17] */ + TRIG12_IN_PERI_TR_IO_INPUT18 = 0x00000C13u, /* peri.tr_io_input[18] */ + TRIG12_IN_PERI_TR_IO_INPUT19 = 0x00000C14u, /* peri.tr_io_input[19] */ + TRIG12_IN_PERI_TR_IO_INPUT20 = 0x00000C15u, /* peri.tr_io_input[20] */ + TRIG12_IN_PERI_TR_IO_INPUT21 = 0x00000C16u, /* peri.tr_io_input[21] */ + TRIG12_IN_PERI_TR_IO_INPUT22 = 0x00000C17u, /* peri.tr_io_input[22] */ + TRIG12_IN_PERI_TR_IO_INPUT23 = 0x00000C18u, /* peri.tr_io_input[23] */ + TRIG12_IN_PERI_TR_IO_INPUT24 = 0x00000C19u, /* peri.tr_io_input[24] */ + TRIG12_IN_PERI_TR_IO_INPUT25 = 0x00000C1Au, /* peri.tr_io_input[25] */ + TRIG12_IN_PERI_TR_IO_INPUT26 = 0x00000C1Bu, /* peri.tr_io_input[26] */ + TRIG12_IN_PERI_TR_IO_INPUT27 = 0x00000C1Cu /* peri.tr_io_input[27] */ +} en_trig_input_grp12_t; + +/* Trigger Input Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */ +typedef enum +{ + TRIG13_IN_CPUSS_ZERO = 0x00000D00u, /* cpuss.zero */ + TRIG13_IN_SCB0_TR_TX_REQ = 0x00000D01u, /* scb[0].tr_tx_req */ + TRIG13_IN_SCB0_TR_RX_REQ = 0x00000D02u, /* scb[0].tr_rx_req */ + TRIG13_IN_SCB1_TR_TX_REQ = 0x00000D03u, /* scb[1].tr_tx_req */ + TRIG13_IN_SCB1_TR_RX_REQ = 0x00000D04u, /* scb[1].tr_rx_req */ + TRIG13_IN_SCB2_TR_TX_REQ = 0x00000D05u, /* scb[2].tr_tx_req */ + TRIG13_IN_SCB2_TR_RX_REQ = 0x00000D06u, /* scb[2].tr_rx_req */ + TRIG13_IN_SCB3_TR_TX_REQ = 0x00000D07u, /* scb[3].tr_tx_req */ + TRIG13_IN_SCB3_TR_RX_REQ = 0x00000D08u, /* scb[3].tr_rx_req */ + TRIG13_IN_SCB4_TR_TX_REQ = 0x00000D09u, /* scb[4].tr_tx_req */ + TRIG13_IN_SCB4_TR_RX_REQ = 0x00000D0Au, /* scb[4].tr_rx_req */ + TRIG13_IN_SCB5_TR_TX_REQ = 0x00000D0Bu, /* scb[5].tr_tx_req */ + TRIG13_IN_SCB5_TR_RX_REQ = 0x00000D0Cu, /* scb[5].tr_rx_req */ + TRIG13_IN_SCB6_TR_TX_REQ = 0x00000D0Du, /* scb[6].tr_tx_req */ + TRIG13_IN_SCB6_TR_RX_REQ = 0x00000D0Eu, /* scb[6].tr_rx_req */ + TRIG13_IN_SCB7_TR_TX_REQ = 0x00000D0Fu, /* scb[7].tr_tx_req */ + TRIG13_IN_SCB7_TR_RX_REQ = 0x00000D10u, /* scb[7].tr_rx_req */ + TRIG13_IN_SCB8_TR_TX_REQ = 0x00000D11u, /* scb[8].tr_tx_req */ + TRIG13_IN_SCB8_TR_RX_REQ = 0x00000D12u, /* scb[8].tr_rx_req */ + TRIG13_IN_AUDIOSS_TR_PDM_RX_REQ = 0x00000D13u, /* audioss.tr_pdm_rx_req */ + TRIG13_IN_AUDIOSS_TR_I2S_TX_REQ = 0x00000D14u, /* audioss.tr_i2s_tx_req */ + TRIG13_IN_AUDIOSS_TR_I2S_RX_REQ = 0x00000D15u, /* audioss.tr_i2s_rx_req */ + TRIG13_IN_SMIF_TR_TX_REQ = 0x00000D16u, /* smif.tr_tx_req */ + TRIG13_IN_SMIF_TR_RX_REQ = 0x00000D17u, /* smif.tr_rx_req */ + TRIG13_IN_USB_DMA_REQ0 = 0x00000D18u, /* usb.dma_req[0] */ + TRIG13_IN_USB_DMA_REQ1 = 0x00000D19u, /* usb.dma_req[1] */ + TRIG13_IN_USB_DMA_REQ2 = 0x00000D1Au, /* usb.dma_req[2] */ + TRIG13_IN_USB_DMA_REQ3 = 0x00000D1Bu, /* usb.dma_req[3] */ + TRIG13_IN_USB_DMA_REQ4 = 0x00000D1Cu, /* usb.dma_req[4] */ + TRIG13_IN_USB_DMA_REQ5 = 0x00000D1Du, /* usb.dma_req[5] */ + TRIG13_IN_USB_DMA_REQ6 = 0x00000D1Eu, /* usb.dma_req[6] */ + TRIG13_IN_USB_DMA_REQ7 = 0x00000D1Fu, /* usb.dma_req[7] */ + TRIG13_IN_CSD_TR_ADC_DONE = 0x00000D20u, /* csd.tr_adc_done */ + TRIG13_IN_CSD_DSI_SENSE_OUT = 0x00000D21u /* csd.dsi_sense_out */ +} en_trig_input_grp13_t; + +/* Trigger Input Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */ +typedef enum +{ + TRIG14_IN_CPUSS_ZERO = 0x00000E00u, /* cpuss.zero */ + TRIG14_IN_UDB_TR_UDB0 = 0x00000E01u, /* udb.tr_udb[0] */ + TRIG14_IN_UDB_TR_UDB1 = 0x00000E02u, /* udb.tr_udb[1] */ + TRIG14_IN_UDB_TR_UDB2 = 0x00000E03u, /* udb.tr_udb[2] */ + TRIG14_IN_UDB_TR_UDB3 = 0x00000E04u, /* udb.tr_udb[3] */ + TRIG14_IN_UDB_TR_UDB4 = 0x00000E05u, /* udb.tr_udb[4] */ + TRIG14_IN_UDB_TR_UDB5 = 0x00000E06u, /* udb.tr_udb[5] */ + TRIG14_IN_UDB_TR_UDB6 = 0x00000E07u, /* udb.tr_udb[6] */ + TRIG14_IN_UDB_TR_UDB7 = 0x00000E08u, /* udb.tr_udb[7] */ + TRIG14_IN_UDB_TR_UDB8 = 0x00000E09u, /* udb.tr_udb[8] */ + TRIG14_IN_UDB_TR_UDB9 = 0x00000E0Au, /* udb.tr_udb[9] */ + TRIG14_IN_UDB_TR_UDB10 = 0x00000E0Bu, /* udb.tr_udb[10] */ + TRIG14_IN_UDB_TR_UDB11 = 0x00000E0Cu, /* udb.tr_udb[11] */ + TRIG14_IN_UDB_TR_UDB12 = 0x00000E0Du, /* udb.tr_udb[12] */ + TRIG14_IN_UDB_TR_UDB13 = 0x00000E0Eu, /* udb.tr_udb[13] */ + TRIG14_IN_UDB_TR_UDB14 = 0x00000E0Fu, /* udb.tr_udb[14] */ + TRIG14_IN_UDB_TR_UDB15 = 0x00000E10u, /* udb.tr_udb[15] */ + TRIG14_IN_UDB_DSI_OUT_TR0 = 0x00000E11u, /* udb.dsi_out_tr[0] */ + TRIG14_IN_UDB_DSI_OUT_TR1 = 0x00000E12u, /* udb.dsi_out_tr[1] */ + TRIG14_IN_CPUSS_CTI_TR_OUT0 = 0x00000E13u, /* cpuss.cti_tr_out[0] */ + TRIG14_IN_CPUSS_CTI_TR_OUT1 = 0x00000E14u, /* cpuss.cti_tr_out[1] */ + TRIG14_IN_PASS_TR_SAR_OUT = 0x00000E15u, /* pass.tr_sar_out */ + TRIG14_IN_PASS_TR_CTDAC_EMPTY = 0x00000E16u, /* pass.tr_ctdac_empty */ + TRIG14_IN_PASS_DSI_CTB_CMP0 = 0x00000E17u, /* pass.dsi_ctb_cmp0 */ + TRIG14_IN_PASS_DSI_CTB_CMP1 = 0x00000E18u, /* pass.dsi_ctb_cmp1 */ + TRIG14_IN_LPCOMP_DSI_COMP0 = 0x00000E19u, /* lpcomp.dsi_comp0 */ + TRIG14_IN_LPCOMP_DSI_COMP1 = 0x00000E1Au, /* lpcomp.dsi_comp1 */ + TRIG14_IN_SCB0_TR_I2C_SCL_FILTERED = 0x00000E1Bu, /* scb[0].tr_i2c_scl_filtered */ + TRIG14_IN_SCB1_TR_I2C_SCL_FILTERED = 0x00000E1Cu, /* scb[1].tr_i2c_scl_filtered */ + TRIG14_IN_SCB2_TR_I2C_SCL_FILTERED = 0x00000E1Du, /* scb[2].tr_i2c_scl_filtered */ + TRIG14_IN_SCB3_TR_I2C_SCL_FILTERED = 0x00000E1Eu, /* scb[3].tr_i2c_scl_filtered */ + TRIG14_IN_SCB4_TR_I2C_SCL_FILTERED = 0x00000E1Fu, /* scb[4].tr_i2c_scl_filtered */ + TRIG14_IN_SCB5_TR_I2C_SCL_FILTERED = 0x00000E20u, /* scb[5].tr_i2c_scl_filtered */ + TRIG14_IN_SCB6_TR_I2C_SCL_FILTERED = 0x00000E21u, /* scb[6].tr_i2c_scl_filtered */ + TRIG14_IN_SCB7_TR_I2C_SCL_FILTERED = 0x00000E22u, /* scb[7].tr_i2c_scl_filtered */ + TRIG14_IN_SCB8_TR_I2C_SCL_FILTERED = 0x00000E23u, /* scb[8].tr_i2c_scl_filtered */ + TRIG14_IN_CPUSS_TR_FAULT0 = 0x00000E24u, /* cpuss.tr_fault[0] */ + TRIG14_IN_CPUSS_TR_FAULT1 = 0x00000E25u /* cpuss.tr_fault[1] */ +} en_trig_input_grp14_t; + +/* Trigger Group Outputs */ +/* Trigger Output Group 0 - DMA Request Assignments */ +typedef enum +{ + TRIG0_OUT_CPUSS_DW0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ + TRIG0_OUT_CPUSS_DW0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ + TRIG0_OUT_CPUSS_DW0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ + TRIG0_OUT_CPUSS_DW0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ + TRIG0_OUT_CPUSS_DW0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ + TRIG0_OUT_CPUSS_DW0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ + TRIG0_OUT_CPUSS_DW0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ + TRIG0_OUT_CPUSS_DW0_TR_IN7 = 0x40000007u, /* cpuss.dw0_tr_in[7] */ + TRIG0_OUT_CPUSS_DW0_TR_IN8 = 0x40000008u, /* cpuss.dw0_tr_in[8] */ + TRIG0_OUT_CPUSS_DW0_TR_IN9 = 0x40000009u, /* cpuss.dw0_tr_in[9] */ + TRIG0_OUT_CPUSS_DW0_TR_IN10 = 0x4000000Au, /* cpuss.dw0_tr_in[10] */ + TRIG0_OUT_CPUSS_DW0_TR_IN11 = 0x4000000Bu, /* cpuss.dw0_tr_in[11] */ + TRIG0_OUT_CPUSS_DW0_TR_IN12 = 0x4000000Cu, /* cpuss.dw0_tr_in[12] */ + TRIG0_OUT_CPUSS_DW0_TR_IN13 = 0x4000000Du, /* cpuss.dw0_tr_in[13] */ + TRIG0_OUT_CPUSS_DW0_TR_IN14 = 0x4000000Eu, /* cpuss.dw0_tr_in[14] */ + TRIG0_OUT_CPUSS_DW0_TR_IN15 = 0x4000000Fu /* cpuss.dw0_tr_in[15] */ +} en_trig_output_grp0_t; + +/* Trigger Output Group 1 - DMA Request Assignments */ +typedef enum +{ + TRIG1_OUT_CPUSS_DW1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ + TRIG1_OUT_CPUSS_DW1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ + TRIG1_OUT_CPUSS_DW1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ + TRIG1_OUT_CPUSS_DW1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ + TRIG1_OUT_CPUSS_DW1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ + TRIG1_OUT_CPUSS_DW1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ + TRIG1_OUT_CPUSS_DW1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ + TRIG1_OUT_CPUSS_DW1_TR_IN7 = 0x40000107u, /* cpuss.dw1_tr_in[7] */ + TRIG1_OUT_CPUSS_DW1_TR_IN8 = 0x40000108u, /* cpuss.dw1_tr_in[8] */ + TRIG1_OUT_CPUSS_DW1_TR_IN9 = 0x40000109u, /* cpuss.dw1_tr_in[9] */ + TRIG1_OUT_CPUSS_DW1_TR_IN10 = 0x4000010Au, /* cpuss.dw1_tr_in[10] */ + TRIG1_OUT_CPUSS_DW1_TR_IN11 = 0x4000010Bu, /* cpuss.dw1_tr_in[11] */ + TRIG1_OUT_CPUSS_DW1_TR_IN12 = 0x4000010Cu, /* cpuss.dw1_tr_in[12] */ + TRIG1_OUT_CPUSS_DW1_TR_IN13 = 0x4000010Du, /* cpuss.dw1_tr_in[13] */ + TRIG1_OUT_CPUSS_DW1_TR_IN14 = 0x4000010Eu, /* cpuss.dw1_tr_in[14] */ + TRIG1_OUT_CPUSS_DW1_TR_IN15 = 0x4000010Fu /* cpuss.dw1_tr_in[15] */ +} en_trig_output_grp1_t; + +/* Trigger Output Group 2 - TCPWM trigger inputs */ +typedef enum +{ + TRIG2_OUT_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_in[0] */ + TRIG2_OUT_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_in[1] */ + TRIG2_OUT_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_in[2] */ + TRIG2_OUT_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_in[3] */ + TRIG2_OUT_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_in[4] */ + TRIG2_OUT_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_in[5] */ + TRIG2_OUT_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_in[6] */ + TRIG2_OUT_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_in[7] */ + TRIG2_OUT_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_in[8] */ + TRIG2_OUT_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_in[9] */ + TRIG2_OUT_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_in[10] */ + TRIG2_OUT_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_in[11] */ + TRIG2_OUT_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_in[12] */ + TRIG2_OUT_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_in[13] */ +} en_trig_output_grp2_t; + +/* Trigger Output Group 3 - TCPWM trigger inputs */ +typedef enum +{ + TRIG3_OUT_TCPWM1_TR_IN0 = 0x40000300u, /* tcpwm[1].tr_in[0] */ + TRIG3_OUT_TCPWM1_TR_IN1 = 0x40000301u, /* tcpwm[1].tr_in[1] */ + TRIG3_OUT_TCPWM1_TR_IN2 = 0x40000302u, /* tcpwm[1].tr_in[2] */ + TRIG3_OUT_TCPWM1_TR_IN3 = 0x40000303u, /* tcpwm[1].tr_in[3] */ + TRIG3_OUT_TCPWM1_TR_IN4 = 0x40000304u, /* tcpwm[1].tr_in[4] */ + TRIG3_OUT_TCPWM1_TR_IN5 = 0x40000305u, /* tcpwm[1].tr_in[5] */ + TRIG3_OUT_TCPWM1_TR_IN6 = 0x40000306u, /* tcpwm[1].tr_in[6] */ + TRIG3_OUT_TCPWM1_TR_IN7 = 0x40000307u, /* tcpwm[1].tr_in[7] */ + TRIG3_OUT_TCPWM1_TR_IN8 = 0x40000308u, /* tcpwm[1].tr_in[8] */ + TRIG3_OUT_TCPWM1_TR_IN9 = 0x40000309u, /* tcpwm[1].tr_in[9] */ + TRIG3_OUT_TCPWM1_TR_IN10 = 0x4000030Au, /* tcpwm[1].tr_in[10] */ + TRIG3_OUT_TCPWM1_TR_IN11 = 0x4000030Bu, /* tcpwm[1].tr_in[11] */ + TRIG3_OUT_TCPWM1_TR_IN12 = 0x4000030Cu, /* tcpwm[1].tr_in[12] */ + TRIG3_OUT_TCPWM1_TR_IN13 = 0x4000030Du /* tcpwm[1].tr_in[13] */ +} en_trig_output_grp3_t; + +/* Trigger Output Group 4 - PROFILE trigger multiplexer */ +typedef enum +{ + TRIG4_OUT_PROFILE_TR_START = 0x40000400u, /* profile.tr_start */ + TRIG4_OUT_PROFILE_TR_STOP = 0x40000401u /* profile.tr_stop */ +} en_trig_output_grp4_t; + +/* Trigger Output Group 5 - CPUSS.CTI trigger multiplexer */ +typedef enum +{ + TRIG5_OUT_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */ + TRIG5_OUT_CPUSS_CTI_TR_IN1 = 0x40000501u /* cpuss.cti_tr_in[1] */ +} en_trig_output_grp5_t; + +/* Trigger Output Group 6 - PASS trigger multiplexer */ +typedef enum +{ + TRIG6_OUT_PASS_TR_SAR_IN = 0x40000600u /* pass.tr_sar_in */ +} en_trig_output_grp6_t; + +/* Trigger Output Group 7 - UDB general purpose trigger multiplexer */ +typedef enum +{ + TRIG7_OUT_UDB_TR_IN0 = 0x40000700u, /* udb.tr_in[0] */ + TRIG7_OUT_UDB_TR_IN1 = 0x40000701u /* udb.tr_in[1] */ +} en_trig_output_grp7_t; + +/* Trigger Output Group 8 - Trigger multiplexer to pins */ +typedef enum +{ + TRIG8_OUT_PERI_TR_IO_OUTPUT0 = 0x40000800u, /* peri.tr_io_output[0] */ + TRIG8_OUT_PERI_TR_IO_OUTPUT1 = 0x40000801u /* peri.tr_io_output[1] */ +} en_trig_output_grp8_t; + +/* Trigger Output Group 9 - Feedback mux to USB DMA interface */ +typedef enum +{ + TRIG9_OUT_USB_DMA_BURSTEND0 = 0x40000900u, /* usb.dma_burstend[0] */ + TRIG9_OUT_USB_DMA_BURSTEND1 = 0x40000901u, /* usb.dma_burstend[1] */ + TRIG9_OUT_USB_DMA_BURSTEND2 = 0x40000902u, /* usb.dma_burstend[2] */ + TRIG9_OUT_USB_DMA_BURSTEND3 = 0x40000903u, /* usb.dma_burstend[3] */ + TRIG9_OUT_USB_DMA_BURSTEND4 = 0x40000904u, /* usb.dma_burstend[4] */ + TRIG9_OUT_USB_DMA_BURSTEND5 = 0x40000905u, /* usb.dma_burstend[5] */ + TRIG9_OUT_USB_DMA_BURSTEND6 = 0x40000906u, /* usb.dma_burstend[6] */ + TRIG9_OUT_USB_DMA_BURSTEND7 = 0x40000907u /* usb.dma_burstend[7] */ +} en_trig_output_grp9_t; + +/* Trigger Output Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */ +typedef enum +{ + TRIG10_OUT_UDB_TR_DW_ACK0 = 0x40000A00u, /* udb.tr_dw_ack[0] */ + TRIG10_OUT_TR_GROUP0_INPUT1 = 0x40000A00u, /* tr_group[0].input[1] */ + TRIG10_OUT_TR_GROUP1_INPUT1 = 0x40000A00u, /* tr_group[1].input[1] */ + TRIG10_OUT_TR_GROUP2_INPUT1 = 0x40000A00u, /* tr_group[2].input[1] */ + TRIG10_OUT_TR_GROUP3_INPUT1 = 0x40000A00u, /* tr_group[3].input[1] */ + TRIG10_OUT_TR_GROUP4_INPUT1 = 0x40000A00u, /* tr_group[4].input[1] */ + TRIG10_OUT_TR_GROUP5_INPUT1 = 0x40000A00u, /* tr_group[5].input[1] */ + TRIG10_OUT_TR_GROUP6_INPUT1 = 0x40000A00u, /* tr_group[6].input[1] */ + TRIG10_OUT_TR_GROUP7_INPUT1 = 0x40000A00u, /* tr_group[7].input[1] */ + TRIG10_OUT_TR_GROUP8_INPUT1 = 0x40000A00u, /* tr_group[8].input[1] */ + TRIG10_OUT_UDB_TR_DW_ACK1 = 0x40000A01u, /* udb.tr_dw_ack[1] */ + TRIG10_OUT_TR_GROUP0_INPUT2 = 0x40000A01u, /* tr_group[0].input[2] */ + TRIG10_OUT_TR_GROUP1_INPUT2 = 0x40000A01u, /* tr_group[1].input[2] */ + TRIG10_OUT_TR_GROUP2_INPUT2 = 0x40000A01u, /* tr_group[2].input[2] */ + TRIG10_OUT_TR_GROUP3_INPUT2 = 0x40000A01u, /* tr_group[3].input[2] */ + TRIG10_OUT_TR_GROUP4_INPUT2 = 0x40000A01u, /* tr_group[4].input[2] */ + TRIG10_OUT_TR_GROUP5_INPUT2 = 0x40000A01u, /* tr_group[5].input[2] */ + TRIG10_OUT_TR_GROUP6_INPUT2 = 0x40000A01u, /* tr_group[6].input[2] */ + TRIG10_OUT_TR_GROUP7_INPUT2 = 0x40000A01u, /* tr_group[7].input[2] */ + TRIG10_OUT_TR_GROUP8_INPUT2 = 0x40000A01u, /* tr_group[8].input[2] */ + TRIG10_OUT_UDB_TR_DW_ACK2 = 0x40000A02u, /* udb.tr_dw_ack[2] */ + TRIG10_OUT_TR_GROUP0_INPUT3 = 0x40000A02u, /* tr_group[0].input[3] */ + TRIG10_OUT_TR_GROUP1_INPUT3 = 0x40000A02u, /* tr_group[1].input[3] */ + TRIG10_OUT_TR_GROUP2_INPUT3 = 0x40000A02u, /* tr_group[2].input[3] */ + TRIG10_OUT_TR_GROUP3_INPUT3 = 0x40000A02u, /* tr_group[3].input[3] */ + TRIG10_OUT_TR_GROUP4_INPUT3 = 0x40000A02u, /* tr_group[4].input[3] */ + TRIG10_OUT_TR_GROUP5_INPUT3 = 0x40000A02u, /* tr_group[5].input[3] */ + TRIG10_OUT_TR_GROUP6_INPUT3 = 0x40000A02u, /* tr_group[6].input[3] */ + TRIG10_OUT_TR_GROUP7_INPUT3 = 0x40000A02u, /* tr_group[7].input[3] */ + TRIG10_OUT_TR_GROUP8_INPUT3 = 0x40000A02u, /* tr_group[8].input[3] */ + TRIG10_OUT_UDB_TR_DW_ACK3 = 0x40000A03u, /* udb.tr_dw_ack[3] */ + TRIG10_OUT_TR_GROUP0_INPUT4 = 0x40000A03u, /* tr_group[0].input[4] */ + TRIG10_OUT_TR_GROUP1_INPUT4 = 0x40000A03u, /* tr_group[1].input[4] */ + TRIG10_OUT_TR_GROUP2_INPUT4 = 0x40000A03u, /* tr_group[2].input[4] */ + TRIG10_OUT_TR_GROUP3_INPUT4 = 0x40000A03u, /* tr_group[3].input[4] */ + TRIG10_OUT_TR_GROUP4_INPUT4 = 0x40000A03u, /* tr_group[4].input[4] */ + TRIG10_OUT_TR_GROUP5_INPUT4 = 0x40000A03u, /* tr_group[5].input[4] */ + TRIG10_OUT_TR_GROUP6_INPUT4 = 0x40000A03u, /* tr_group[6].input[4] */ + TRIG10_OUT_TR_GROUP7_INPUT4 = 0x40000A03u, /* tr_group[7].input[4] */ + TRIG10_OUT_TR_GROUP8_INPUT4 = 0x40000A03u, /* tr_group[8].input[4] */ + TRIG10_OUT_UDB_TR_DW_ACK4 = 0x40000A04u, /* udb.tr_dw_ack[4] */ + TRIG10_OUT_TR_GROUP0_INPUT5 = 0x40000A04u, /* tr_group[0].input[5] */ + TRIG10_OUT_TR_GROUP1_INPUT5 = 0x40000A04u, /* tr_group[1].input[5] */ + TRIG10_OUT_TR_GROUP2_INPUT5 = 0x40000A04u, /* tr_group[2].input[5] */ + TRIG10_OUT_TR_GROUP3_INPUT5 = 0x40000A04u, /* tr_group[3].input[5] */ + TRIG10_OUT_TR_GROUP4_INPUT5 = 0x40000A04u, /* tr_group[4].input[5] */ + TRIG10_OUT_TR_GROUP5_INPUT5 = 0x40000A04u, /* tr_group[5].input[5] */ + TRIG10_OUT_TR_GROUP6_INPUT5 = 0x40000A04u, /* tr_group[6].input[5] */ + TRIG10_OUT_TR_GROUP7_INPUT5 = 0x40000A04u, /* tr_group[7].input[5] */ + TRIG10_OUT_TR_GROUP8_INPUT5 = 0x40000A04u, /* tr_group[8].input[5] */ + TRIG10_OUT_UDB_TR_DW_ACK5 = 0x40000A05u, /* udb.tr_dw_ack[5] */ + TRIG10_OUT_TR_GROUP0_INPUT6 = 0x40000A05u, /* tr_group[0].input[6] */ + TRIG10_OUT_TR_GROUP1_INPUT6 = 0x40000A05u, /* tr_group[1].input[6] */ + TRIG10_OUT_TR_GROUP2_INPUT6 = 0x40000A05u, /* tr_group[2].input[6] */ + TRIG10_OUT_TR_GROUP3_INPUT6 = 0x40000A05u, /* tr_group[3].input[6] */ + TRIG10_OUT_TR_GROUP4_INPUT6 = 0x40000A05u, /* tr_group[4].input[6] */ + TRIG10_OUT_TR_GROUP5_INPUT6 = 0x40000A05u, /* tr_group[5].input[6] */ + TRIG10_OUT_TR_GROUP6_INPUT6 = 0x40000A05u, /* tr_group[6].input[6] */ + TRIG10_OUT_TR_GROUP7_INPUT6 = 0x40000A05u, /* tr_group[7].input[6] */ + TRIG10_OUT_TR_GROUP8_INPUT6 = 0x40000A05u, /* tr_group[8].input[6] */ + TRIG10_OUT_UDB_TR_DW_ACK6 = 0x40000A06u, /* udb.tr_dw_ack[6] */ + TRIG10_OUT_TR_GROUP0_INPUT7 = 0x40000A06u, /* tr_group[0].input[7] */ + TRIG10_OUT_TR_GROUP1_INPUT7 = 0x40000A06u, /* tr_group[1].input[7] */ + TRIG10_OUT_TR_GROUP2_INPUT7 = 0x40000A06u, /* tr_group[2].input[7] */ + TRIG10_OUT_TR_GROUP3_INPUT7 = 0x40000A06u, /* tr_group[3].input[7] */ + TRIG10_OUT_TR_GROUP4_INPUT7 = 0x40000A06u, /* tr_group[4].input[7] */ + TRIG10_OUT_TR_GROUP5_INPUT7 = 0x40000A06u, /* tr_group[5].input[7] */ + TRIG10_OUT_TR_GROUP6_INPUT7 = 0x40000A06u, /* tr_group[6].input[7] */ + TRIG10_OUT_TR_GROUP7_INPUT7 = 0x40000A06u, /* tr_group[7].input[7] */ + TRIG10_OUT_TR_GROUP8_INPUT7 = 0x40000A06u, /* tr_group[8].input[7] */ + TRIG10_OUT_UDB_TR_DW_ACK7 = 0x40000A07u, /* udb.tr_dw_ack[7] */ + TRIG10_OUT_TR_GROUP0_INPUT8 = 0x40000A07u, /* tr_group[0].input[8] */ + TRIG10_OUT_TR_GROUP1_INPUT8 = 0x40000A07u, /* tr_group[1].input[8] */ + TRIG10_OUT_TR_GROUP2_INPUT8 = 0x40000A07u, /* tr_group[2].input[8] */ + TRIG10_OUT_TR_GROUP3_INPUT8 = 0x40000A07u, /* tr_group[3].input[8] */ + TRIG10_OUT_TR_GROUP4_INPUT8 = 0x40000A07u, /* tr_group[4].input[8] */ + TRIG10_OUT_TR_GROUP5_INPUT8 = 0x40000A07u, /* tr_group[5].input[8] */ + TRIG10_OUT_TR_GROUP6_INPUT8 = 0x40000A07u, /* tr_group[6].input[8] */ + TRIG10_OUT_TR_GROUP7_INPUT8 = 0x40000A07u, /* tr_group[7].input[8] */ + TRIG10_OUT_TR_GROUP8_INPUT8 = 0x40000A07u /* tr_group[8].input[8] */ +} en_trig_output_grp10_t; + +/* Trigger Output Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */ +typedef enum +{ + TRIG11_OUT_TR_GROUP0_INPUT9 = 0x40000B00u, /* tr_group[0].input[9] */ + TRIG11_OUT_TR_GROUP1_INPUT9 = 0x40000B00u, /* tr_group[1].input[9] */ + TRIG11_OUT_TR_GROUP2_INPUT9 = 0x40000B00u, /* tr_group[2].input[9] */ + TRIG11_OUT_TR_GROUP3_INPUT9 = 0x40000B00u, /* tr_group[3].input[9] */ + TRIG11_OUT_TR_GROUP4_INPUT9 = 0x40000B00u, /* tr_group[4].input[9] */ + TRIG11_OUT_TR_GROUP5_INPUT9 = 0x40000B00u, /* tr_group[5].input[9] */ + TRIG11_OUT_TR_GROUP6_INPUT9 = 0x40000B00u, /* tr_group[6].input[9] */ + TRIG11_OUT_TR_GROUP7_INPUT9 = 0x40000B00u, /* tr_group[7].input[9] */ + TRIG11_OUT_TR_GROUP8_INPUT9 = 0x40000B00u, /* tr_group[8].input[9] */ + TRIG11_OUT_TR_GROUP0_INPUT10 = 0x40000B01u, /* tr_group[0].input[10] */ + TRIG11_OUT_TR_GROUP1_INPUT10 = 0x40000B01u, /* tr_group[1].input[10] */ + TRIG11_OUT_TR_GROUP2_INPUT10 = 0x40000B01u, /* tr_group[2].input[10] */ + TRIG11_OUT_TR_GROUP3_INPUT10 = 0x40000B01u, /* tr_group[3].input[10] */ + TRIG11_OUT_TR_GROUP4_INPUT10 = 0x40000B01u, /* tr_group[4].input[10] */ + TRIG11_OUT_TR_GROUP5_INPUT10 = 0x40000B01u, /* tr_group[5].input[10] */ + TRIG11_OUT_TR_GROUP6_INPUT10 = 0x40000B01u, /* tr_group[6].input[10] */ + TRIG11_OUT_TR_GROUP7_INPUT10 = 0x40000B01u, /* tr_group[7].input[10] */ + TRIG11_OUT_TR_GROUP8_INPUT10 = 0x40000B01u, /* tr_group[8].input[10] */ + TRIG11_OUT_TR_GROUP0_INPUT11 = 0x40000B02u, /* tr_group[0].input[11] */ + TRIG11_OUT_TR_GROUP1_INPUT11 = 0x40000B02u, /* tr_group[1].input[11] */ + TRIG11_OUT_TR_GROUP2_INPUT11 = 0x40000B02u, /* tr_group[2].input[11] */ + TRIG11_OUT_TR_GROUP3_INPUT11 = 0x40000B02u, /* tr_group[3].input[11] */ + TRIG11_OUT_TR_GROUP4_INPUT11 = 0x40000B02u, /* tr_group[4].input[11] */ + TRIG11_OUT_TR_GROUP5_INPUT11 = 0x40000B02u, /* tr_group[5].input[11] */ + TRIG11_OUT_TR_GROUP6_INPUT11 = 0x40000B02u, /* tr_group[6].input[11] */ + TRIG11_OUT_TR_GROUP7_INPUT11 = 0x40000B02u, /* tr_group[7].input[11] */ + TRIG11_OUT_TR_GROUP8_INPUT11 = 0x40000B02u, /* tr_group[8].input[11] */ + TRIG11_OUT_TR_GROUP0_INPUT12 = 0x40000B03u, /* tr_group[0].input[12] */ + TRIG11_OUT_TR_GROUP1_INPUT12 = 0x40000B03u, /* tr_group[1].input[12] */ + TRIG11_OUT_TR_GROUP2_INPUT12 = 0x40000B03u, /* tr_group[2].input[12] */ + TRIG11_OUT_TR_GROUP3_INPUT12 = 0x40000B03u, /* tr_group[3].input[12] */ + TRIG11_OUT_TR_GROUP4_INPUT12 = 0x40000B03u, /* tr_group[4].input[12] */ + TRIG11_OUT_TR_GROUP5_INPUT12 = 0x40000B03u, /* tr_group[5].input[12] */ + TRIG11_OUT_TR_GROUP6_INPUT12 = 0x40000B03u, /* tr_group[6].input[12] */ + TRIG11_OUT_TR_GROUP7_INPUT12 = 0x40000B03u, /* tr_group[7].input[12] */ + TRIG11_OUT_TR_GROUP8_INPUT12 = 0x40000B03u, /* tr_group[8].input[12] */ + TRIG11_OUT_TR_GROUP0_INPUT13 = 0x40000B04u, /* tr_group[0].input[13] */ + TRIG11_OUT_TR_GROUP1_INPUT13 = 0x40000B04u, /* tr_group[1].input[13] */ + TRIG11_OUT_TR_GROUP2_INPUT13 = 0x40000B04u, /* tr_group[2].input[13] */ + TRIG11_OUT_TR_GROUP3_INPUT13 = 0x40000B04u, /* tr_group[3].input[13] */ + TRIG11_OUT_TR_GROUP4_INPUT13 = 0x40000B04u, /* tr_group[4].input[13] */ + TRIG11_OUT_TR_GROUP5_INPUT13 = 0x40000B04u, /* tr_group[5].input[13] */ + TRIG11_OUT_TR_GROUP6_INPUT13 = 0x40000B04u, /* tr_group[6].input[13] */ + TRIG11_OUT_TR_GROUP7_INPUT13 = 0x40000B04u, /* tr_group[7].input[13] */ + TRIG11_OUT_TR_GROUP8_INPUT13 = 0x40000B04u, /* tr_group[8].input[13] */ + TRIG11_OUT_TR_GROUP0_INPUT14 = 0x40000B05u, /* tr_group[0].input[14] */ + TRIG11_OUT_TR_GROUP1_INPUT14 = 0x40000B05u, /* tr_group[1].input[14] */ + TRIG11_OUT_TR_GROUP2_INPUT14 = 0x40000B05u, /* tr_group[2].input[14] */ + TRIG11_OUT_TR_GROUP3_INPUT14 = 0x40000B05u, /* tr_group[3].input[14] */ + TRIG11_OUT_TR_GROUP4_INPUT14 = 0x40000B05u, /* tr_group[4].input[14] */ + TRIG11_OUT_TR_GROUP5_INPUT14 = 0x40000B05u, /* tr_group[5].input[14] */ + TRIG11_OUT_TR_GROUP6_INPUT14 = 0x40000B05u, /* tr_group[6].input[14] */ + TRIG11_OUT_TR_GROUP7_INPUT14 = 0x40000B05u, /* tr_group[7].input[14] */ + TRIG11_OUT_TR_GROUP8_INPUT14 = 0x40000B05u, /* tr_group[8].input[14] */ + TRIG11_OUT_TR_GROUP0_INPUT15 = 0x40000B06u, /* tr_group[0].input[15] */ + TRIG11_OUT_TR_GROUP1_INPUT15 = 0x40000B06u, /* tr_group[1].input[15] */ + TRIG11_OUT_TR_GROUP2_INPUT15 = 0x40000B06u, /* tr_group[2].input[15] */ + TRIG11_OUT_TR_GROUP3_INPUT15 = 0x40000B06u, /* tr_group[3].input[15] */ + TRIG11_OUT_TR_GROUP4_INPUT15 = 0x40000B06u, /* tr_group[4].input[15] */ + TRIG11_OUT_TR_GROUP5_INPUT15 = 0x40000B06u, /* tr_group[5].input[15] */ + TRIG11_OUT_TR_GROUP6_INPUT15 = 0x40000B06u, /* tr_group[6].input[15] */ + TRIG11_OUT_TR_GROUP7_INPUT15 = 0x40000B06u, /* tr_group[7].input[15] */ + TRIG11_OUT_TR_GROUP8_INPUT15 = 0x40000B06u, /* tr_group[8].input[15] */ + TRIG11_OUT_TR_GROUP0_INPUT16 = 0x40000B07u, /* tr_group[0].input[16] */ + TRIG11_OUT_TR_GROUP1_INPUT16 = 0x40000B07u, /* tr_group[1].input[16] */ + TRIG11_OUT_TR_GROUP2_INPUT16 = 0x40000B07u, /* tr_group[2].input[16] */ + TRIG11_OUT_TR_GROUP3_INPUT16 = 0x40000B07u, /* tr_group[3].input[16] */ + TRIG11_OUT_TR_GROUP4_INPUT16 = 0x40000B07u, /* tr_group[4].input[16] */ + TRIG11_OUT_TR_GROUP5_INPUT16 = 0x40000B07u, /* tr_group[5].input[16] */ + TRIG11_OUT_TR_GROUP6_INPUT16 = 0x40000B07u, /* tr_group[6].input[16] */ + TRIG11_OUT_TR_GROUP7_INPUT16 = 0x40000B07u, /* tr_group[7].input[16] */ + TRIG11_OUT_TR_GROUP8_INPUT16 = 0x40000B07u, /* tr_group[8].input[16] */ + TRIG11_OUT_TR_GROUP0_INPUT17 = 0x40000B08u, /* tr_group[0].input[17] */ + TRIG11_OUT_TR_GROUP1_INPUT17 = 0x40000B08u, /* tr_group[1].input[17] */ + TRIG11_OUT_TR_GROUP2_INPUT17 = 0x40000B08u, /* tr_group[2].input[17] */ + TRIG11_OUT_TR_GROUP3_INPUT17 = 0x40000B08u, /* tr_group[3].input[17] */ + TRIG11_OUT_TR_GROUP4_INPUT17 = 0x40000B08u, /* tr_group[4].input[17] */ + TRIG11_OUT_TR_GROUP5_INPUT17 = 0x40000B08u, /* tr_group[5].input[17] */ + TRIG11_OUT_TR_GROUP6_INPUT17 = 0x40000B08u, /* tr_group[6].input[17] */ + TRIG11_OUT_TR_GROUP7_INPUT17 = 0x40000B08u, /* tr_group[7].input[17] */ + TRIG11_OUT_TR_GROUP8_INPUT17 = 0x40000B08u, /* tr_group[8].input[17] */ + TRIG11_OUT_TR_GROUP0_INPUT18 = 0x40000B09u, /* tr_group[0].input[18] */ + TRIG11_OUT_TR_GROUP1_INPUT18 = 0x40000B09u, /* tr_group[1].input[18] */ + TRIG11_OUT_TR_GROUP2_INPUT18 = 0x40000B09u, /* tr_group[2].input[18] */ + TRIG11_OUT_TR_GROUP3_INPUT18 = 0x40000B09u, /* tr_group[3].input[18] */ + TRIG11_OUT_TR_GROUP4_INPUT18 = 0x40000B09u, /* tr_group[4].input[18] */ + TRIG11_OUT_TR_GROUP5_INPUT18 = 0x40000B09u, /* tr_group[5].input[18] */ + TRIG11_OUT_TR_GROUP6_INPUT18 = 0x40000B09u, /* tr_group[6].input[18] */ + TRIG11_OUT_TR_GROUP7_INPUT18 = 0x40000B09u, /* tr_group[7].input[18] */ + TRIG11_OUT_TR_GROUP8_INPUT18 = 0x40000B09u, /* tr_group[8].input[18] */ + TRIG11_OUT_TR_GROUP0_INPUT19 = 0x40000B0Au, /* tr_group[0].input[19] */ + TRIG11_OUT_TR_GROUP1_INPUT19 = 0x40000B0Au, /* tr_group[1].input[19] */ + TRIG11_OUT_TR_GROUP2_INPUT19 = 0x40000B0Au, /* tr_group[2].input[19] */ + TRIG11_OUT_TR_GROUP3_INPUT19 = 0x40000B0Au, /* tr_group[3].input[19] */ + TRIG11_OUT_TR_GROUP4_INPUT19 = 0x40000B0Au, /* tr_group[4].input[19] */ + TRIG11_OUT_TR_GROUP5_INPUT19 = 0x40000B0Au, /* tr_group[5].input[19] */ + TRIG11_OUT_TR_GROUP6_INPUT19 = 0x40000B0Au, /* tr_group[6].input[19] */ + TRIG11_OUT_TR_GROUP7_INPUT19 = 0x40000B0Au, /* tr_group[7].input[19] */ + TRIG11_OUT_TR_GROUP8_INPUT19 = 0x40000B0Au, /* tr_group[8].input[19] */ + TRIG11_OUT_TR_GROUP0_INPUT20 = 0x40000B0Bu, /* tr_group[0].input[20] */ + TRIG11_OUT_TR_GROUP1_INPUT20 = 0x40000B0Bu, /* tr_group[1].input[20] */ + TRIG11_OUT_TR_GROUP2_INPUT20 = 0x40000B0Bu, /* tr_group[2].input[20] */ + TRIG11_OUT_TR_GROUP3_INPUT20 = 0x40000B0Bu, /* tr_group[3].input[20] */ + TRIG11_OUT_TR_GROUP4_INPUT20 = 0x40000B0Bu, /* tr_group[4].input[20] */ + TRIG11_OUT_TR_GROUP5_INPUT20 = 0x40000B0Bu, /* tr_group[5].input[20] */ + TRIG11_OUT_TR_GROUP6_INPUT20 = 0x40000B0Bu, /* tr_group[6].input[20] */ + TRIG11_OUT_TR_GROUP7_INPUT20 = 0x40000B0Bu, /* tr_group[7].input[20] */ + TRIG11_OUT_TR_GROUP8_INPUT20 = 0x40000B0Bu, /* tr_group[8].input[20] */ + TRIG11_OUT_TR_GROUP0_INPUT21 = 0x40000B0Cu, /* tr_group[0].input[21] */ + TRIG11_OUT_TR_GROUP1_INPUT21 = 0x40000B0Cu, /* tr_group[1].input[21] */ + TRIG11_OUT_TR_GROUP2_INPUT21 = 0x40000B0Cu, /* tr_group[2].input[21] */ + TRIG11_OUT_TR_GROUP3_INPUT21 = 0x40000B0Cu, /* tr_group[3].input[21] */ + TRIG11_OUT_TR_GROUP4_INPUT21 = 0x40000B0Cu, /* tr_group[4].input[21] */ + TRIG11_OUT_TR_GROUP5_INPUT21 = 0x40000B0Cu, /* tr_group[5].input[21] */ + TRIG11_OUT_TR_GROUP6_INPUT21 = 0x40000B0Cu, /* tr_group[6].input[21] */ + TRIG11_OUT_TR_GROUP7_INPUT21 = 0x40000B0Cu, /* tr_group[7].input[21] */ + TRIG11_OUT_TR_GROUP8_INPUT21 = 0x40000B0Cu, /* tr_group[8].input[21] */ + TRIG11_OUT_TR_GROUP0_INPUT22 = 0x40000B0Du, /* tr_group[0].input[22] */ + TRIG11_OUT_TR_GROUP1_INPUT22 = 0x40000B0Du, /* tr_group[1].input[22] */ + TRIG11_OUT_TR_GROUP2_INPUT22 = 0x40000B0Du, /* tr_group[2].input[22] */ + TRIG11_OUT_TR_GROUP3_INPUT22 = 0x40000B0Du, /* tr_group[3].input[22] */ + TRIG11_OUT_TR_GROUP4_INPUT22 = 0x40000B0Du, /* tr_group[4].input[22] */ + TRIG11_OUT_TR_GROUP5_INPUT22 = 0x40000B0Du, /* tr_group[5].input[22] */ + TRIG11_OUT_TR_GROUP6_INPUT22 = 0x40000B0Du, /* tr_group[6].input[22] */ + TRIG11_OUT_TR_GROUP7_INPUT22 = 0x40000B0Du, /* tr_group[7].input[22] */ + TRIG11_OUT_TR_GROUP8_INPUT22 = 0x40000B0Du, /* tr_group[8].input[22] */ + TRIG11_OUT_TR_GROUP0_INPUT23 = 0x40000B0Eu, /* tr_group[0].input[23] */ + TRIG11_OUT_TR_GROUP1_INPUT23 = 0x40000B0Eu, /* tr_group[1].input[23] */ + TRIG11_OUT_TR_GROUP2_INPUT23 = 0x40000B0Eu, /* tr_group[2].input[23] */ + TRIG11_OUT_TR_GROUP3_INPUT23 = 0x40000B0Eu, /* tr_group[3].input[23] */ + TRIG11_OUT_TR_GROUP4_INPUT23 = 0x40000B0Eu, /* tr_group[4].input[23] */ + TRIG11_OUT_TR_GROUP5_INPUT23 = 0x40000B0Eu, /* tr_group[5].input[23] */ + TRIG11_OUT_TR_GROUP6_INPUT23 = 0x40000B0Eu, /* tr_group[6].input[23] */ + TRIG11_OUT_TR_GROUP7_INPUT23 = 0x40000B0Eu, /* tr_group[7].input[23] */ + TRIG11_OUT_TR_GROUP8_INPUT23 = 0x40000B0Eu, /* tr_group[8].input[23] */ + TRIG11_OUT_TR_GROUP0_INPUT24 = 0x40000B0Fu, /* tr_group[0].input[24] */ + TRIG11_OUT_TR_GROUP1_INPUT24 = 0x40000B0Fu, /* tr_group[1].input[24] */ + TRIG11_OUT_TR_GROUP2_INPUT24 = 0x40000B0Fu, /* tr_group[2].input[24] */ + TRIG11_OUT_TR_GROUP3_INPUT24 = 0x40000B0Fu, /* tr_group[3].input[24] */ + TRIG11_OUT_TR_GROUP4_INPUT24 = 0x40000B0Fu, /* tr_group[4].input[24] */ + TRIG11_OUT_TR_GROUP5_INPUT24 = 0x40000B0Fu, /* tr_group[5].input[24] */ + TRIG11_OUT_TR_GROUP6_INPUT24 = 0x40000B0Fu, /* tr_group[6].input[24] */ + TRIG11_OUT_TR_GROUP7_INPUT24 = 0x40000B0Fu, /* tr_group[7].input[24] */ + TRIG11_OUT_TR_GROUP8_INPUT24 = 0x40000B0Fu /* tr_group[8].input[24] */ +} en_trig_output_grp11_t; + +/* Trigger Output Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */ +typedef enum +{ + TRIG12_OUT_TR_GROUP2_INPUT25 = 0x40000C00u, /* tr_group[2].input[25] */ + TRIG12_OUT_TR_GROUP3_INPUT25 = 0x40000C00u, /* tr_group[3].input[25] */ + TRIG12_OUT_TR_GROUP4_INPUT25 = 0x40000C00u, /* tr_group[4].input[25] */ + TRIG12_OUT_TR_GROUP5_INPUT25 = 0x40000C00u, /* tr_group[5].input[25] */ + TRIG12_OUT_TR_GROUP6_INPUT25 = 0x40000C00u, /* tr_group[6].input[25] */ + TRIG12_OUT_TR_GROUP7_INPUT25 = 0x40000C00u, /* tr_group[7].input[25] */ + TRIG12_OUT_TR_GROUP8_INPUT25 = 0x40000C00u, /* tr_group[8].input[25] */ + TRIG12_OUT_TR_GROUP2_INPUT26 = 0x40000C01u, /* tr_group[2].input[26] */ + TRIG12_OUT_TR_GROUP3_INPUT26 = 0x40000C01u, /* tr_group[3].input[26] */ + TRIG12_OUT_TR_GROUP4_INPUT26 = 0x40000C01u, /* tr_group[4].input[26] */ + TRIG12_OUT_TR_GROUP5_INPUT26 = 0x40000C01u, /* tr_group[5].input[26] */ + TRIG12_OUT_TR_GROUP6_INPUT26 = 0x40000C01u, /* tr_group[6].input[26] */ + TRIG12_OUT_TR_GROUP7_INPUT26 = 0x40000C01u, /* tr_group[7].input[26] */ + TRIG12_OUT_TR_GROUP8_INPUT26 = 0x40000C01u, /* tr_group[8].input[26] */ + TRIG12_OUT_TR_GROUP2_INPUT27 = 0x40000C02u, /* tr_group[2].input[27] */ + TRIG12_OUT_TR_GROUP3_INPUT27 = 0x40000C02u, /* tr_group[3].input[27] */ + TRIG12_OUT_TR_GROUP4_INPUT27 = 0x40000C02u, /* tr_group[4].input[27] */ + TRIG12_OUT_TR_GROUP5_INPUT27 = 0x40000C02u, /* tr_group[5].input[27] */ + TRIG12_OUT_TR_GROUP6_INPUT27 = 0x40000C02u, /* tr_group[6].input[27] */ + TRIG12_OUT_TR_GROUP7_INPUT27 = 0x40000C02u, /* tr_group[7].input[27] */ + TRIG12_OUT_TR_GROUP8_INPUT27 = 0x40000C02u, /* tr_group[8].input[27] */ + TRIG12_OUT_TR_GROUP2_INPUT28 = 0x40000C03u, /* tr_group[2].input[28] */ + TRIG12_OUT_TR_GROUP3_INPUT28 = 0x40000C03u, /* tr_group[3].input[28] */ + TRIG12_OUT_TR_GROUP4_INPUT28 = 0x40000C03u, /* tr_group[4].input[28] */ + TRIG12_OUT_TR_GROUP5_INPUT28 = 0x40000C03u, /* tr_group[5].input[28] */ + TRIG12_OUT_TR_GROUP6_INPUT28 = 0x40000C03u, /* tr_group[6].input[28] */ + TRIG12_OUT_TR_GROUP7_INPUT28 = 0x40000C03u, /* tr_group[7].input[28] */ + TRIG12_OUT_TR_GROUP8_INPUT28 = 0x40000C03u, /* tr_group[8].input[28] */ + TRIG12_OUT_TR_GROUP2_INPUT29 = 0x40000C04u, /* tr_group[2].input[29] */ + TRIG12_OUT_TR_GROUP3_INPUT29 = 0x40000C04u, /* tr_group[3].input[29] */ + TRIG12_OUT_TR_GROUP4_INPUT29 = 0x40000C04u, /* tr_group[4].input[29] */ + TRIG12_OUT_TR_GROUP5_INPUT29 = 0x40000C04u, /* tr_group[5].input[29] */ + TRIG12_OUT_TR_GROUP6_INPUT29 = 0x40000C04u, /* tr_group[6].input[29] */ + TRIG12_OUT_TR_GROUP7_INPUT29 = 0x40000C04u, /* tr_group[7].input[29] */ + TRIG12_OUT_TR_GROUP8_INPUT29 = 0x40000C04u, /* tr_group[8].input[29] */ + TRIG12_OUT_TR_GROUP2_INPUT30 = 0x40000C05u, /* tr_group[2].input[30] */ + TRIG12_OUT_TR_GROUP3_INPUT30 = 0x40000C05u, /* tr_group[3].input[30] */ + TRIG12_OUT_TR_GROUP4_INPUT30 = 0x40000C05u, /* tr_group[4].input[30] */ + TRIG12_OUT_TR_GROUP5_INPUT30 = 0x40000C05u, /* tr_group[5].input[30] */ + TRIG12_OUT_TR_GROUP6_INPUT30 = 0x40000C05u, /* tr_group[6].input[30] */ + TRIG12_OUT_TR_GROUP7_INPUT30 = 0x40000C05u, /* tr_group[7].input[30] */ + TRIG12_OUT_TR_GROUP8_INPUT30 = 0x40000C05u, /* tr_group[8].input[30] */ + TRIG12_OUT_TR_GROUP2_INPUT31 = 0x40000C06u, /* tr_group[2].input[31] */ + TRIG12_OUT_TR_GROUP3_INPUT31 = 0x40000C06u, /* tr_group[3].input[31] */ + TRIG12_OUT_TR_GROUP4_INPUT31 = 0x40000C06u, /* tr_group[4].input[31] */ + TRIG12_OUT_TR_GROUP5_INPUT31 = 0x40000C06u, /* tr_group[5].input[31] */ + TRIG12_OUT_TR_GROUP6_INPUT31 = 0x40000C06u, /* tr_group[6].input[31] */ + TRIG12_OUT_TR_GROUP7_INPUT31 = 0x40000C06u, /* tr_group[7].input[31] */ + TRIG12_OUT_TR_GROUP8_INPUT31 = 0x40000C06u, /* tr_group[8].input[31] */ + TRIG12_OUT_TR_GROUP2_INPUT32 = 0x40000C07u, /* tr_group[2].input[32] */ + TRIG12_OUT_TR_GROUP3_INPUT32 = 0x40000C07u, /* tr_group[3].input[32] */ + TRIG12_OUT_TR_GROUP4_INPUT32 = 0x40000C07u, /* tr_group[4].input[32] */ + TRIG12_OUT_TR_GROUP5_INPUT32 = 0x40000C07u, /* tr_group[5].input[32] */ + TRIG12_OUT_TR_GROUP6_INPUT32 = 0x40000C07u, /* tr_group[6].input[32] */ + TRIG12_OUT_TR_GROUP7_INPUT32 = 0x40000C07u, /* tr_group[7].input[32] */ + TRIG12_OUT_TR_GROUP8_INPUT32 = 0x40000C07u, /* tr_group[8].input[32] */ + TRIG12_OUT_TR_GROUP0_INPUT25 = 0x40000C08u, /* tr_group[0].input[25] */ + TRIG12_OUT_TR_GROUP1_INPUT25 = 0x40000C08u, /* tr_group[1].input[25] */ + TRIG12_OUT_TR_GROUP0_INPUT26 = 0x40000C09u, /* tr_group[0].input[26] */ + TRIG12_OUT_TR_GROUP1_INPUT26 = 0x40000C09u /* tr_group[1].input[26] */ +} en_trig_output_grp12_t; + +/* Trigger Output Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */ +typedef enum +{ + TRIG13_OUT_TR_GROUP0_INPUT27 = 0x40000D00u, /* tr_group[0].input[27] */ + TRIG13_OUT_TR_GROUP1_INPUT27 = 0x40000D00u, /* tr_group[1].input[27] */ + TRIG13_OUT_TR_GROUP0_INPUT28 = 0x40000D01u, /* tr_group[0].input[28] */ + TRIG13_OUT_TR_GROUP1_INPUT28 = 0x40000D01u, /* tr_group[1].input[28] */ + TRIG13_OUT_TR_GROUP0_INPUT29 = 0x40000D02u, /* tr_group[0].input[29] */ + TRIG13_OUT_TR_GROUP1_INPUT29 = 0x40000D02u, /* tr_group[1].input[29] */ + TRIG13_OUT_TR_GROUP0_INPUT30 = 0x40000D03u, /* tr_group[0].input[30] */ + TRIG13_OUT_TR_GROUP1_INPUT30 = 0x40000D03u, /* tr_group[1].input[30] */ + TRIG13_OUT_TR_GROUP0_INPUT31 = 0x40000D04u, /* tr_group[0].input[31] */ + TRIG13_OUT_TR_GROUP1_INPUT31 = 0x40000D04u, /* tr_group[1].input[31] */ + TRIG13_OUT_TR_GROUP0_INPUT32 = 0x40000D05u, /* tr_group[0].input[32] */ + TRIG13_OUT_TR_GROUP1_INPUT32 = 0x40000D05u, /* tr_group[1].input[32] */ + TRIG13_OUT_TR_GROUP0_INPUT33 = 0x40000D06u, /* tr_group[0].input[33] */ + TRIG13_OUT_TR_GROUP1_INPUT33 = 0x40000D06u, /* tr_group[1].input[33] */ + TRIG13_OUT_TR_GROUP0_INPUT34 = 0x40000D07u, /* tr_group[0].input[34] */ + TRIG13_OUT_TR_GROUP1_INPUT34 = 0x40000D07u, /* tr_group[1].input[34] */ + TRIG13_OUT_TR_GROUP0_INPUT35 = 0x40000D08u, /* tr_group[0].input[35] */ + TRIG13_OUT_TR_GROUP1_INPUT35 = 0x40000D08u, /* tr_group[1].input[35] */ + TRIG13_OUT_TR_GROUP0_INPUT36 = 0x40000D09u, /* tr_group[0].input[36] */ + TRIG13_OUT_TR_GROUP1_INPUT36 = 0x40000D09u, /* tr_group[1].input[36] */ + TRIG13_OUT_TR_GROUP0_INPUT37 = 0x40000D0Au, /* tr_group[0].input[37] */ + TRIG13_OUT_TR_GROUP1_INPUT37 = 0x40000D0Au, /* tr_group[1].input[37] */ + TRIG13_OUT_TR_GROUP0_INPUT38 = 0x40000D0Bu, /* tr_group[0].input[38] */ + TRIG13_OUT_TR_GROUP1_INPUT38 = 0x40000D0Bu, /* tr_group[1].input[38] */ + TRIG13_OUT_TR_GROUP0_INPUT39 = 0x40000D0Cu, /* tr_group[0].input[39] */ + TRIG13_OUT_TR_GROUP1_INPUT39 = 0x40000D0Cu, /* tr_group[1].input[39] */ + TRIG13_OUT_TR_GROUP0_INPUT40 = 0x40000D0Du, /* tr_group[0].input[40] */ + TRIG13_OUT_TR_GROUP1_INPUT40 = 0x40000D0Du, /* tr_group[1].input[40] */ + TRIG13_OUT_TR_GROUP0_INPUT41 = 0x40000D0Eu, /* tr_group[0].input[41] */ + TRIG13_OUT_TR_GROUP1_INPUT41 = 0x40000D0Eu, /* tr_group[1].input[41] */ + TRIG13_OUT_TR_GROUP0_INPUT42 = 0x40000D0Fu, /* tr_group[0].input[42] */ + TRIG13_OUT_TR_GROUP1_INPUT42 = 0x40000D0Fu, /* tr_group[1].input[42] */ + TRIG13_OUT_TR_GROUP2_INPUT33 = 0x40000D10u, /* tr_group[2].input[33] */ + TRIG13_OUT_TR_GROUP3_INPUT33 = 0x40000D10u, /* tr_group[3].input[33] */ + TRIG13_OUT_TR_GROUP4_INPUT33 = 0x40000D10u, /* tr_group[4].input[33] */ + TRIG13_OUT_TR_GROUP5_INPUT33 = 0x40000D10u, /* tr_group[5].input[33] */ + TRIG13_OUT_TR_GROUP6_INPUT33 = 0x40000D10u, /* tr_group[6].input[33] */ + TRIG13_OUT_TR_GROUP7_INPUT33 = 0x40000D10u, /* tr_group[7].input[33] */ + TRIG13_OUT_TR_GROUP8_INPUT33 = 0x40000D10u, /* tr_group[8].input[33] */ + TRIG13_OUT_TR_GROUP2_INPUT34 = 0x40000D11u, /* tr_group[2].input[34] */ + TRIG13_OUT_TR_GROUP3_INPUT34 = 0x40000D11u, /* tr_group[3].input[34] */ + TRIG13_OUT_TR_GROUP4_INPUT34 = 0x40000D11u, /* tr_group[4].input[34] */ + TRIG13_OUT_TR_GROUP5_INPUT34 = 0x40000D11u, /* tr_group[5].input[34] */ + TRIG13_OUT_TR_GROUP6_INPUT34 = 0x40000D11u, /* tr_group[6].input[34] */ + TRIG13_OUT_TR_GROUP7_INPUT34 = 0x40000D11u, /* tr_group[7].input[34] */ + TRIG13_OUT_TR_GROUP8_INPUT34 = 0x40000D11u /* tr_group[8].input[34] */ +} en_trig_output_grp13_t; + +/* Trigger Output Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */ +typedef enum +{ + TRIG14_OUT_TR_GROUP0_INPUT43 = 0x40000E00u, /* tr_group[0].input[43] */ + TRIG14_OUT_TR_GROUP1_INPUT43 = 0x40000E00u, /* tr_group[1].input[43] */ + TRIG14_OUT_TR_GROUP0_INPUT44 = 0x40000E01u, /* tr_group[0].input[44] */ + TRIG14_OUT_TR_GROUP1_INPUT44 = 0x40000E01u, /* tr_group[1].input[44] */ + TRIG14_OUT_TR_GROUP0_INPUT45 = 0x40000E02u, /* tr_group[0].input[45] */ + TRIG14_OUT_TR_GROUP1_INPUT45 = 0x40000E02u, /* tr_group[1].input[45] */ + TRIG14_OUT_TR_GROUP0_INPUT46 = 0x40000E03u, /* tr_group[0].input[46] */ + TRIG14_OUT_TR_GROUP1_INPUT46 = 0x40000E03u, /* tr_group[1].input[46] */ + TRIG14_OUT_TR_GROUP0_INPUT47 = 0x40000E04u, /* tr_group[0].input[47] */ + TRIG14_OUT_TR_GROUP1_INPUT47 = 0x40000E04u, /* tr_group[1].input[47] */ + TRIG14_OUT_TR_GROUP0_INPUT48 = 0x40000E05u, /* tr_group[0].input[48] */ + TRIG14_OUT_TR_GROUP1_INPUT48 = 0x40000E05u, /* tr_group[1].input[48] */ + TRIG14_OUT_TR_GROUP0_INPUT49 = 0x40000E06u, /* tr_group[0].input[49] */ + TRIG14_OUT_TR_GROUP1_INPUT49 = 0x40000E06u, /* tr_group[1].input[49] */ + TRIG14_OUT_TR_GROUP0_INPUT50 = 0x40000E07u, /* tr_group[0].input[50] */ + TRIG14_OUT_TR_GROUP1_INPUT50 = 0x40000E07u, /* tr_group[1].input[50] */ + TRIG14_OUT_TR_GROUP2_INPUT35 = 0x40000E08u, /* tr_group[2].input[35] */ + TRIG14_OUT_TR_GROUP3_INPUT35 = 0x40000E08u, /* tr_group[3].input[35] */ + TRIG14_OUT_TR_GROUP4_INPUT35 = 0x40000E08u, /* tr_group[4].input[35] */ + TRIG14_OUT_TR_GROUP5_INPUT35 = 0x40000E08u, /* tr_group[5].input[35] */ + TRIG14_OUT_TR_GROUP6_INPUT35 = 0x40000E08u, /* tr_group[6].input[35] */ + TRIG14_OUT_TR_GROUP7_INPUT35 = 0x40000E08u, /* tr_group[7].input[35] */ + TRIG14_OUT_TR_GROUP8_INPUT35 = 0x40000E08u, /* tr_group[8].input[35] */ + TRIG14_OUT_TR_GROUP2_INPUT36 = 0x40000E09u, /* tr_group[2].input[36] */ + TRIG14_OUT_TR_GROUP3_INPUT36 = 0x40000E09u, /* tr_group[3].input[36] */ + TRIG14_OUT_TR_GROUP4_INPUT36 = 0x40000E09u, /* tr_group[4].input[36] */ + TRIG14_OUT_TR_GROUP5_INPUT36 = 0x40000E09u, /* tr_group[5].input[36] */ + TRIG14_OUT_TR_GROUP6_INPUT36 = 0x40000E09u, /* tr_group[6].input[36] */ + TRIG14_OUT_TR_GROUP7_INPUT36 = 0x40000E09u, /* tr_group[7].input[36] */ + TRIG14_OUT_TR_GROUP8_INPUT36 = 0x40000E09u, /* tr_group[8].input[36] */ + TRIG14_OUT_TR_GROUP2_INPUT37 = 0x40000E0Au, /* tr_group[2].input[37] */ + TRIG14_OUT_TR_GROUP3_INPUT37 = 0x40000E0Au, /* tr_group[3].input[37] */ + TRIG14_OUT_TR_GROUP4_INPUT37 = 0x40000E0Au, /* tr_group[4].input[37] */ + TRIG14_OUT_TR_GROUP5_INPUT37 = 0x40000E0Au, /* tr_group[5].input[37] */ + TRIG14_OUT_TR_GROUP6_INPUT37 = 0x40000E0Au, /* tr_group[6].input[37] */ + TRIG14_OUT_TR_GROUP7_INPUT37 = 0x40000E0Au, /* tr_group[7].input[37] */ + TRIG14_OUT_TR_GROUP8_INPUT37 = 0x40000E0Au, /* tr_group[8].input[37] */ + TRIG14_OUT_TR_GROUP2_INPUT38 = 0x40000E0Bu, /* tr_group[2].input[38] */ + TRIG14_OUT_TR_GROUP3_INPUT38 = 0x40000E0Bu, /* tr_group[3].input[38] */ + TRIG14_OUT_TR_GROUP4_INPUT38 = 0x40000E0Bu, /* tr_group[4].input[38] */ + TRIG14_OUT_TR_GROUP5_INPUT38 = 0x40000E0Bu, /* tr_group[5].input[38] */ + TRIG14_OUT_TR_GROUP6_INPUT38 = 0x40000E0Bu, /* tr_group[6].input[38] */ + TRIG14_OUT_TR_GROUP7_INPUT38 = 0x40000E0Bu, /* tr_group[7].input[38] */ + TRIG14_OUT_TR_GROUP8_INPUT38 = 0x40000E0Bu, /* tr_group[8].input[38] */ + TRIG14_OUT_TR_GROUP2_INPUT39 = 0x40000E0Cu, /* tr_group[2].input[39] */ + TRIG14_OUT_TR_GROUP3_INPUT39 = 0x40000E0Cu, /* tr_group[3].input[39] */ + TRIG14_OUT_TR_GROUP4_INPUT39 = 0x40000E0Cu, /* tr_group[4].input[39] */ + TRIG14_OUT_TR_GROUP5_INPUT39 = 0x40000E0Cu, /* tr_group[5].input[39] */ + TRIG14_OUT_TR_GROUP6_INPUT39 = 0x40000E0Cu, /* tr_group[6].input[39] */ + TRIG14_OUT_TR_GROUP7_INPUT39 = 0x40000E0Cu, /* tr_group[7].input[39] */ + TRIG14_OUT_TR_GROUP8_INPUT39 = 0x40000E0Cu, /* tr_group[8].input[39] */ + TRIG14_OUT_TR_GROUP2_INPUT40 = 0x40000E0Du, /* tr_group[2].input[40] */ + TRIG14_OUT_TR_GROUP3_INPUT40 = 0x40000E0Du, /* tr_group[3].input[40] */ + TRIG14_OUT_TR_GROUP4_INPUT40 = 0x40000E0Du, /* tr_group[4].input[40] */ + TRIG14_OUT_TR_GROUP5_INPUT40 = 0x40000E0Du, /* tr_group[5].input[40] */ + TRIG14_OUT_TR_GROUP6_INPUT40 = 0x40000E0Du, /* tr_group[6].input[40] */ + TRIG14_OUT_TR_GROUP7_INPUT40 = 0x40000E0Du, /* tr_group[7].input[40] */ + TRIG14_OUT_TR_GROUP8_INPUT40 = 0x40000E0Du, /* tr_group[8].input[40] */ + TRIG14_OUT_TR_GROUP2_INPUT41 = 0x40000E0Eu, /* tr_group[2].input[41] */ + TRIG14_OUT_TR_GROUP3_INPUT41 = 0x40000E0Eu, /* tr_group[3].input[41] */ + TRIG14_OUT_TR_GROUP4_INPUT41 = 0x40000E0Eu, /* tr_group[4].input[41] */ + TRIG14_OUT_TR_GROUP5_INPUT41 = 0x40000E0Eu, /* tr_group[5].input[41] */ + TRIG14_OUT_TR_GROUP6_INPUT41 = 0x40000E0Eu, /* tr_group[6].input[41] */ + TRIG14_OUT_TR_GROUP7_INPUT41 = 0x40000E0Eu, /* tr_group[7].input[41] */ + TRIG14_OUT_TR_GROUP8_INPUT41 = 0x40000E0Eu, /* tr_group[8].input[41] */ + TRIG14_OUT_TR_GROUP2_INPUT42 = 0x40000E0Fu, /* tr_group[2].input[42] */ + TRIG14_OUT_TR_GROUP3_INPUT42 = 0x40000E0Fu, /* tr_group[3].input[42] */ + TRIG14_OUT_TR_GROUP4_INPUT42 = 0x40000E0Fu, /* tr_group[4].input[42] */ + TRIG14_OUT_TR_GROUP5_INPUT42 = 0x40000E0Fu, /* tr_group[5].input[42] */ + TRIG14_OUT_TR_GROUP6_INPUT42 = 0x40000E0Fu, /* tr_group[6].input[42] */ + TRIG14_OUT_TR_GROUP7_INPUT42 = 0x40000E0Fu, /* tr_group[7].input[42] */ + TRIG14_OUT_TR_GROUP8_INPUT42 = 0x40000E0Fu /* tr_group[8].input[42] */ +} en_trig_output_grp14_t; + +/* Level or edge detection setting for a trigger mux */ +typedef enum +{ + /* The trigger is a simple level output */ + TRIGGER_TYPE_LEVEL = 0u, + /* The trigger is synchronized to the consumer blocks clock + and a two cycle pulse is generated on this clock */ + TRIGGER_TYPE_EDGE = 1u +} en_trig_type_t; + +/* Trigger Type Defines */ +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE +/* CSD Trigger Types */ +#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +/* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE +/* AUDIOSS Trigger Types */ +#define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE +/* UDB Trigger Types */ +#define TRIGGER_TYPE_UDB_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_DW_ACK__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_DW_ACK__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_TR_UDB__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_TR_UDB__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_UDB_DSI_OUT_TR__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_UDB_DSI_OUT_TR__EDGE TRIGGER_TYPE_EDGE +/* PROFILE Trigger Types */ +#define TRIGGER_TYPE_PROFILE_TR_START TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PROFILE_TR_STOP TRIGGER_TYPE_EDGE +/* TR_GROUP Trigger Types */ +#define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE TRIGGER_TYPE_EDGE + +/* Monitor Signal Defines */ +typedef enum +{ + PROFILE_ONE = 0, /* profile.one */ + CPUSS_MONITOR_CM0 = 1, /* cpuss.monitor_cm0 */ + CPUSS_MONITOR_CM4 = 2, /* cpuss.monitor_cm4 */ + CPUSS_MONITOR_FLASH = 3, /* cpuss.monitor_flash */ + CPUSS_MONITOR_DW0_AHB = 4, /* cpuss.monitor_dw0_ahb */ + CPUSS_MONITOR_DW1_AHB = 5, /* cpuss.monitor_dw1_ahb */ + CPUSS_MONITOR_CRYPTO = 6, /* cpuss.monitor_crypto */ + USB_MONITOR_AHB = 7, /* usb.monitor_ahb */ + SCB0_MONITOR_AHB = 8, /* scb[0].monitor_ahb */ + SCB1_MONITOR_AHB = 9, /* scb[1].monitor_ahb */ + SCB2_MONITOR_AHB = 10, /* scb[2].monitor_ahb */ + SCB3_MONITOR_AHB = 11, /* scb[3].monitor_ahb */ + SCB4_MONITOR_AHB = 12, /* scb[4].monitor_ahb */ + SCB5_MONITOR_AHB = 13, /* scb[5].monitor_ahb */ + SCB6_MONITOR_AHB = 14, /* scb[6].monitor_ahb */ + SCB7_MONITOR_AHB = 15, /* scb[7].monitor_ahb */ + SCB8_MONITOR_AHB = 16, /* scb[8].monitor_ahb */ + UDB_MONITOR_UDB0 = 17, /* udb.monitor_udb[0] */ + UDB_MONITOR_UDB1 = 18, /* udb.monitor_udb[1] */ + UDB_MONITOR_UDB2 = 19, /* udb.monitor_udb[2] */ + UDB_MONITOR_UDB3 = 20, /* udb.monitor_udb[3] */ + SMIF_MONITOR_SMIF_SPI_SELECT0 = 21, /* smif.monitor_smif_spi_select[0] */ + SMIF_MONITOR_SMIF_SPI_SELECT1 = 22, /* smif.monitor_smif_spi_select[1] */ + SMIF_MONITOR_SMIF_SPI_SELECT2 = 23, /* smif.monitor_smif_spi_select[2] */ + SMIF_MONITOR_SMIF_SPI_SELECT3 = 24, /* smif.monitor_smif_spi_select[3] */ + SMIF_MONITOR_SMIF_SPI_SELECT_ANY = 25, /* smif.monitor_smif_spi_select_any */ + BLESS_EXT_LNA_RX_CTL_OUT = 26, /* bless.ext_lna_rx_ctl_out */ + BLESS_EXT_PA_TX_CTL_OUT = 27 /* bless.ext_pa_tx_ctl_out */ +} en_ep_mon_sel_t; + +/* Total count of Energy Profiler monitor signal connections */ +#define EP_MONITOR_COUNT 28u + +/* Bus masters */ +typedef enum +{ + CPUSS_MS_ID_CM0 = 0, + CPUSS_MS_ID_CRYPTO = 1, + CPUSS_MS_ID_DW0 = 2, + CPUSS_MS_ID_DW1 = 3, + CPUSS_MS_ID_CM4 = 14, + CPUSS_MS_ID_TC = 15 +} en_prot_master_t; + +/* Parameter Defines */ +/* Number of regulator modules instantiated within SRSS */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 1u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 1u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 5u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 5u +/* Number of PWR_HIB_DATA registers */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 2u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 1u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 0u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 9u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of GPIO ports in range 0..31 */ +#define IOSS_GPIO_GPIO_PORT_NR_0_31 15u +/* Number of GPIO ports in range 32..63 */ +#define IOSS_GPIO_GPIO_PORT_NR_32_63 0u +/* Number of GPIO ports in range 64..95 */ +#define IOSS_GPIO_GPIO_PORT_NR_64_95 0u +/* Number of GPIO ports in range 96..127 */ +#define IOSS_GPIO_GPIO_PORT_NR_96_127 0u +/* Number of ports in device */ +#define IOSS_GPIO_GPIO_PORT_NR 15u +/* Mask of SMARTIO instances presence */ +#define IOSS_SMARTIO_SMARTIO_MASK 768u +/* The number of protection contexts ([2, 16]). */ +#define PERI_PC_NR 8u +/* Master interface presence mask (4 bits) */ +#define PERI_MS_PRESENT 15u +/* Master interface PPU combinatorial (1) or registerd (0) */ +#define PERI_MS_PPU_COMBINATORIAL 1u +/* The number of programmable PPU structures for PERI (all peripherals) */ +#define PERI_MS_PPU_PROG_STRUCT_NR 16u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Presence of a timeout functionality (1: Yes, 0:No) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Number of programmable clocks (outputs) */ +#define PERI_CLOCK_NR 59u +/* Number of 8.0 dividers */ +#define PERI_DIV_8_NR 8u +/* Number of 16.0 dividers */ +#define PERI_DIV_16_NR 16u +/* Number of 16.5 (fractional) dividers */ +#define PERI_DIV_16_5_NR 4u +/* Number of 24.5 (fractional) dividers */ +#define PERI_DIV_24_5_NR 1u +/* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ +#define PERI_DIV_ADDR_WIDTH 4u +/* Trigger module present (0=No, 1=Yes) */ +#define PERI_TR 1u +/* Number of trigger groups */ +#define PERI_TR_GROUP_NR 15u +/* The number of protection contexts minus 1 ([1, 15]). */ +#define PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1 7u +/* The number of protection contexts minus 1 ([1, 15]). */ +#define PERI_PPU_PROG_STRUCT_PC_NR_MINUS1 7u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 288u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 9u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 32u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 256u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 16u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 128u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 1024u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 32u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output size (in Bytes) */ +#define CPUSS_FLASHC_WORD_SIZE 16u +/* Flash row address width */ +#define CPUSS_FLASHC_ROW_ADDR_WIDTH 12u +/* Flash column address width */ +#define CPUSS_FLASHC_COL_ADDR_WIDTH 5u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_IRQ_NR 147u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_DPSLP_IRQ_NR 41u +/* Number of DeepSleep wakeup interrupt inputs to CM0+ (product configuration) */ +#define CPUSS_CM0_DPSLP_IRQ_NR 8u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3 + for trace level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 16u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 1u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 8u +/* Width of the TPIU interface in bits ([1,32]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 256u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 16u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 16u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* AES cipher support (0 = no support, 1 = support */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support (0 = no support, 1 = support */ +#define CPUSS_CRYPTO_DES 1u +/* Pseudo random number generation support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA support included */ +#define CPUSS_CRYPTO_SHA 1u +/* SHA1 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA256 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA256 1u +/* SHA512 hash support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_SHA512 1u +/* Cyclic Redundancy Check support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_CRC 1u +/* Vector unit support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_VU 1u +/* True random number generation support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_TR 1u +/* String support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_STR 1u +/* AHB-Lite master interface support (0 = no support, 1 = support) */ +#define CPUSS_CRYPTO_MASTER_IF 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 7u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* Number of channels in each DataWire controller (must be the same for now) */ +#define CPUSS_DW_CH_NR 16u +/* Number of profiling counters. Legal range [1, 32] */ +#define PROFILE_PRFL_CNT_NR 8u +/* Number of monitor event signals. Legal range [1, 128] */ +#define PROFILE_PRFL_MONITOR_NR 128u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* Number of UDB Interrupts */ +#define UDB_NUMINT 16u +/* Number of triggers */ +#define UDB_NUMTR 16u +/* Number of UDB array rows (must be multiple of 2) */ +#define UDB_NUMROW 2u +/* Number of UDB array columns */ +#define UDB_NUMCOL 6u +/* DSI on bottom (1) or on bottom and top (2) of UDB array */ +#define UDB_DSISIDES 2u +/* Number of UDBs = NUMROW * NUMCOL */ +#define UDB_NUMUDB 12u +/* Number of UDB pairs = NUMUDB / 2 */ +#define UDB_NUMUDBPAIR 6u +/* Number of DSIs = NUMCOL * DSISIDES */ +#define UDB_NUMDSI 12u +/* Number of quad clocks */ +#define UDB_NUMQCLK 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB0_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB0_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB0_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB0_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB0_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB0_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB0_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB0_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB0_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB0_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB0_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB0_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB0_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB0_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB0_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB0_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB0_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB0_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB0_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB0_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB0_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB0_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB0_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB1_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB1_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB1_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB1_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB1_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB1_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB1_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB1_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB1_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB1_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB1_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB1_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB1_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB1_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB1_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB1_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB1_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB1_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB1_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB1_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB1_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB1_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB1_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB2_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB2_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB2_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB2_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB2_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB2_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB2_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB2_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB2_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB2_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB2_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB2_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB2_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB2_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB2_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB2_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB2_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB2_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB2_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB2_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB2_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB2_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB2_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB3_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB3_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB3_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB3_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB3_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB3_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB3_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB3_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB3_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB3_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB3_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB3_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB3_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB3_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB3_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB3_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB3_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB3_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB3_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB3_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB3_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB3_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB3_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB4_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB4_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB4_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB4_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB4_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB4_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB4_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB4_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB4_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB4_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB4_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB4_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB4_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB4_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB4_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB4_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB4_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB4_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB4_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB4_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB4_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB4_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB4_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB5_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB5_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB5_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB5_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB5_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB5_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB5_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB5_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB5_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB5_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB5_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB5_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB5_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB5_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB5_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB5_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB5_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB5_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB5_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB5_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB5_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB5_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB5_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB6_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB6_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB6_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB6_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB6_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB6_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB6_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB6_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB6_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB6_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB6_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB6_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB6_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB6_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB6_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB6_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB6_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB6_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB6_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB6_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB6_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB6_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB6_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB7_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB7_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB7_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB7_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB7_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB7_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB7_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB7_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB7_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB7_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB7_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB7_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB7_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB7_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB7_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB7_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB7_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB7_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB7_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB7_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB7_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB7_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB7_I2C_FAST_PLUS 1u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB8_DEEPSLEEP 1u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB8_EC 1u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB8_I2C_M 0u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB8_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB8_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB8_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB8_I2C_EC 1u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB8_I2C_M_S 0u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB8_I2C_S_EC 1u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB8_SPI_M 0u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB8_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB8_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB8_SPI_EC 1u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB8_SPI_S_EC 1u +/* UART support? ('0': no, '1': yes) */ +#define SCB8_UART 0u +/* SPI or UART (SPI | UART) */ +#define SCB8_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB8_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB8_CMD_RESP 1u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB8_EZ 1u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB8_EZ_CMD_RESP 1u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB8_I2C_S_EZ 1u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB8_SPI_S_EZ 1u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB8_I2C_FAST_PLUS 1u +/* Number of counters per IP (1..8) */ +#define TCPWM0_CNT_NR 8u +/* Counter width (in number of bits) */ +#define TCPWM0_CNT_CNT_WIDTH 32u +/* Number of counters per IP (1..8) */ +#define TCPWM1_CNT_NR 24u +/* Counter width (in number of bits) */ +#define TCPWM1_CNT_CNT_WIDTH 16u +/* Max number of LCD commons supported */ +#define LCD_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_PIN_NR 62u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 1u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 1u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 1u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 1u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u +#define PASS_CTBM_CTDAC_PRESENT 1u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]) */ +#define SMIF_MASTER_WIDTH 8u +/* Base address of the SMIF XIP memory region. This address must be a multiple of + the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This + address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP + memory region should NOT overlap with other memory regions. */ +#define SMIF_SMIF_XIP_ADDR 402653184u +/* Capacity of the SMIF XIP memory region. The more significant bits of this + parameter must be '1' and the lesser significant bits of this paramter must + be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are + {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, + 0xffe0:0000, ..., 0xe000:0000}. */ +#define SMIF_SMIF_XIP_MASK 4160749568u +/* Cryptography (AES) support ('0' = no support, '1' = support) */ +#define SMIF_CRYPTO 1u +/* Number of external devices supported ([1,4]) */ +#define SMIF_DEVICE_NR 4u +/* External device write support. This is a 4-bit field. Each external device has + a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */ +#define SMIF_DEVICE_WR_EN 15u +/* Set to 1 if IP will instantiate spares (0=None, 1=Max, 2=Min) */ +#define SMIF_SPARE_EN 1u +/* I2S capable? (0=No,1=Yes) */ +#define AUDIOSS_I2S 1u +/* PDM capable? (0=No,1=Yes) */ +#define AUDIOSS_PDM 1u + +/* MMIO Targets Defines */ +#define CY_MMIO_CRYPTO_GROUP_NR 1u +#define CY_MMIO_CRYPTO_SLAVE_NR 1u +#define CY_MMIO_CPUSS_GROUP_NR 2u +#define CY_MMIO_CPUSS_SLAVE_NR 1u +#define CY_MMIO_FAULT_GROUP_NR 2u +#define CY_MMIO_FAULT_SLAVE_NR 2u +#define CY_MMIO_IPC_GROUP_NR 2u +#define CY_MMIO_IPC_SLAVE_NR 3u +#define CY_MMIO_PROT_GROUP_NR 2u +#define CY_MMIO_PROT_SLAVE_NR 4u +#define CY_MMIO_FLASHC_GROUP_NR 2u +#define CY_MMIO_FLASHC_SLAVE_NR 5u +#define CY_MMIO_SRSS_GROUP_NR 2u +#define CY_MMIO_SRSS_SLAVE_NR 6u +#define CY_MMIO_BACKUP_GROUP_NR 2u +#define CY_MMIO_BACKUP_SLAVE_NR 7u +#define CY_MMIO_DW_GROUP_NR 2u +#define CY_MMIO_DW_SLAVE_NR 8u +#define CY_MMIO_EFUSE_GROUP_NR 2u +#define CY_MMIO_EFUSE_SLAVE_NR 12u +#define CY_MMIO_PROFILE_GROUP_NR 2u +#define CY_MMIO_PROFILE_SLAVE_NR 13u +#define CY_MMIO_HSIOM_GROUP_NR 3u +#define CY_MMIO_HSIOM_SLAVE_NR 1u +#define CY_MMIO_GPIO_GROUP_NR 3u +#define CY_MMIO_GPIO_SLAVE_NR 2u +#define CY_MMIO_SMARTIO_GROUP_NR 3u +#define CY_MMIO_SMARTIO_SLAVE_NR 3u +#define CY_MMIO_UDB_GROUP_NR 3u +#define CY_MMIO_UDB_SLAVE_NR 4u +#define CY_MMIO_LPCOMP_GROUP_NR 3u +#define CY_MMIO_LPCOMP_SLAVE_NR 5u +#define CY_MMIO_CSD0_GROUP_NR 3u +#define CY_MMIO_CSD0_SLAVE_NR 6u +#define CY_MMIO_TCPWM0_GROUP_NR 3u +#define CY_MMIO_TCPWM0_SLAVE_NR 8u +#define CY_MMIO_TCPWM1_GROUP_NR 3u +#define CY_MMIO_TCPWM1_SLAVE_NR 9u +#define CY_MMIO_LCD0_GROUP_NR 3u +#define CY_MMIO_LCD0_SLAVE_NR 10u +#define CY_MMIO_BLE_GROUP_NR 3u +#define CY_MMIO_BLE_SLAVE_NR 11u +#define CY_MMIO_USBFS0_GROUP_NR 3u +#define CY_MMIO_USBFS0_SLAVE_NR 12u +#define CY_MMIO_SMIF0_GROUP_NR 4u +#define CY_MMIO_SMIF0_SLAVE_NR 2u +#define CY_MMIO_SCB0_GROUP_NR 6u +#define CY_MMIO_SCB0_SLAVE_NR 1u +#define CY_MMIO_SCB1_GROUP_NR 6u +#define CY_MMIO_SCB1_SLAVE_NR 2u +#define CY_MMIO_SCB2_GROUP_NR 6u +#define CY_MMIO_SCB2_SLAVE_NR 3u +#define CY_MMIO_SCB3_GROUP_NR 6u +#define CY_MMIO_SCB3_SLAVE_NR 4u +#define CY_MMIO_SCB4_GROUP_NR 6u +#define CY_MMIO_SCB4_SLAVE_NR 5u +#define CY_MMIO_SCB5_GROUP_NR 6u +#define CY_MMIO_SCB5_SLAVE_NR 6u +#define CY_MMIO_SCB6_GROUP_NR 6u +#define CY_MMIO_SCB6_SLAVE_NR 7u +#define CY_MMIO_SCB7_GROUP_NR 6u +#define CY_MMIO_SCB7_SLAVE_NR 8u +#define CY_MMIO_SCB8_GROUP_NR 6u +#define CY_MMIO_SCB8_SLAVE_NR 9u +#define CY_MMIO_PASS_GROUP_NR 9u +#define CY_MMIO_PASS_SLAVE_NR 1u +#define CY_MMIO_I2S0_GROUP_NR 10u +#define CY_MMIO_I2S0_SLAVE_NR 1u +#define CY_MMIO_PDM0_GROUP_NR 10u +#define CY_MMIO_PDM0_SLAVE_NR 2u + +#endif /* _PSOC63_CONFIG_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/system_psoc63.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/system_psoc63.h new file mode 100644 index 0000000000..98b31f45ba --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/system_psoc63.h @@ -0,0 +1,556 @@ +/***************************************************************************//** +* \file system_psoc63.h +* \version 2.10 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC63_H_ +#define _SYSTEM_PSOC63_H_ + +/** +* \defgroup group_system_config System Configuration Files (Startup) +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - Default interrupt handlers definition +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files: +* 'startup_xx_yy.S', where 'xx' is the device family, and 'yy' is the target CPU; +* for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s. +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files: +* 'startup_xx_yy.s', where 'xx' is the device family, and 'yy' is the target +* CPU; for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files: 'startup_xx_yy.S', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, startup_psoc63_cm0plus.S and +* startup_psoc63_cm4.S. The code in these files copies the vector table from +* Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files: 'startup_xx_yy.s', where 'xx' is the device family, and 'yy' is the +* target CPU; for example, startup_psoc63_cm0plus.s and startup_psoc63_cm4.s. +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files: 'startup_xx_yy.s', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, startup_psoc63_cm0plus.s and +* startup_psoc63_cm4.s. The code in these files copies the vector table +* from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#define CY_CORTEX_M4_APPL_ADDR (0x10080000UL) /* <<< 512 KB reserved for the Cortex-M0+ application */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0Eu) & 0x3FFFu) << 18u)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0Fu) & 0x3FFFu) << 18u)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); +extern uint32_t Cy_SaveIRQ(void); +extern void Cy_RestoreIRQ(uint32_t saved); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3u) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0u) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2u) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1u) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC63_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/ipc_rpc.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/ipc_rpc.h new file mode 100644 index 0000000000..581aca85ce --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/ipc_rpc.h @@ -0,0 +1,77 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef IPC_RPC_H +#define IPC_RPC_H + +#include + +#if defined(__MBED__) +#define IPCPIPE_ASSERT MBED_ASSERT +#include "mbed_assert.h" +#else +#include "project.h" +#define IPCPIPE_ASSERT CY_ASSERT +#endif + +#define IPCRPC_MAX_ARGUMENTS 8 + +/** IPC RPC message data structure + * Used to pass RPC call arguments to M0 core for execution + */ +typedef struct { + uint32_t client_id; ///< Client ID of the RPC client + uint32_t result; ///< Function execution result returned from callee to caller + uint32_t args_num; ///< Number of arguments to RPC function call + uint32_t args[IPCRPC_MAX_ARGUMENTS]; ///< Arguments of RPC function call +} IpcRpcMessage; + + +/** IPC RPC message buffer + * Used to hold and transfer RPC message + */ +typedef struct { + volatile uint8_t busy_flag; ///< Indicates whether the RPC call using this buffer is in progress + IpcRpcMessage message; ///< RPC message associated with a call +} IpcRpcBuffer; + + +/** Function handling the RPC call + * It packs its arguments into the RPC message buffer, initializes transfer + * and waits for completion. + * + * @param call_id unique identifier of the RPC API function to be executed + * @param args_num number of call arguments + * @param ... call arguments + * + * @return call result (as returned by executed function) + */ +uint32_t ipcrpc_call(uint32_t call_id, uint32_t args_num, ...); + +#if defined(__cplusplus) +extern "C" { +#endif +/** Initialization function for RPC mechanism. + * Generated automatically during wrapper generation; needs to be called from startup code. + */ +void ipcrpc_init(void); +#if defined(__cplusplus) +} +#endif + +#endif /* IPC_RPC_H */ +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/psoc6_static_srm.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/psoc6_static_srm.h new file mode 100644 index 0000000000..9a1f9870c0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/psoc6_static_srm.h @@ -0,0 +1,74 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + + */ + +/* + * This file defines hardware resources statically allocated to M0 core + * when static resource managemnt is used. + * + * There are 4 classes of resources that must be declared here: + * - M0_ASSIGNED_PORTS macro defines which ports and pins are reserved + * for M0 core use. + * You define these as a colon separated list of ports and pins reserved + * using macro SRM_PORT(port_num, pins), one time for each reserved port. + * SRM_PORT macro arguments are port number, in the range 0 .. 14 and + * pins is a hex value with a bit set for each reserved pin on a port. + * + * - M0_ASSIGNED_DIVIDERS macro defines which clock dividers are reserved + * for M0 core use. + * You define these as a colon separated list of dividers reserved + * using macro SRM_DIVIDER(type, reservations), one time for each required + * devider type. + * SRM_DIVIDER arguments are divider type, one of cy_en_divider_types_t + * values and reservations is a hex mask value with a bit set for each + * reserved divider of a given type. + * + * - M0_ASSIGNED_SCBS macro defines which SCB blocks are reserved + * for M0 core use. + * You define these as a colon separated list of SCBs reserved using + * macro SRM_SCB(n), which argument is SCB number in a range 0 .. 7. + * + * - M0_ASSIGNED_TCPWM macro defines which TCPWM blocks are reserved + * for M0 core use. + * You define these as a colon separated list of TCPWMs reserved using + * macro SRM_TCPWM(n), which argument is TCPWM number in a range 0 .. 31. + * + * If a particular resource class is not used at all by M0 core you can + * skip defining relevant M0_ASSIGNED_* macro or define it as an empty one. + * + * Examples: + * #define M0_ASSIGNED_PORTS SRM_PORT(0, 0x30), SRM_PORT(5, 0x03) + * + * #define M0_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01) + * + * #define M0_ASSIGNED_SCBS SRM_SCB(2) + * + * #define M0_ASSIGNED_TCPWMS + * + */ + +// Reservations below apply to default M0 hex image. + +// P0_0 and p0_1 reserved for WCO, P6-6 and P6_7 reserved for SWD +#define M0_ASSIGNED_PORTS SRM_PORT(0, 0x03), SRM_PORT(6, 0xc0), SRM_PORT(11, 0x02) +// 8-bit divider 0 reserved for us ticker. +#define M0_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01), \ + SRM_DIVIDER(CY_SYSCLK_DIV_16_BIT, 0x01) +#define M0_ASSIGNED_SCBS +#define M0_ASSIGNED_TCPWMS + +/* End of File */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/PinNames.h new file mode 100644 index 0000000000..10a8f6dd41 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/PinNames.h @@ -0,0 +1,253 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" +#include "PortNames.h" + +#if PSOC6_ENABLE_M0_M4_DEBUG + +#define CY_STDIO_UART_RX P9_0 +#define CY_STDIO_UART_TX P9_1 +#define CY_STDIO_UART_CTS P9_2 +#define CY_STDIO_UART_RTS P9_3 +#else + +#define CY_STDIO_UART_RX P5_0 +#define CY_STDIO_UART_TX P5_1 +#define CY_STDIO_UART_CTS P5_2 +#define CY_STDIO_UART_RTS P5_3 + +#endif // PSOC6_ENABLE_M0_M4_DEBUG + +// PinName[15-0] = Port[15-8] + Pin[7-0] +typedef enum { + P0_0 = (Port0 << 8) + 0x00, + P0_1 = (Port0 << 8) + 0x01, + P0_2 = (Port0 << 8) + 0x02, + P0_3 = (Port0 << 8) + 0x03, + P0_4 = (Port0 << 8) + 0x04, + P0_5 = (Port0 << 8) + 0x05, + P0_6 = (Port0 << 8) + 0x06, + P0_7 = (Port0 << 8) + 0x07, + + P1_0 = (Port1 << 8) + 0x00, + P1_1 = (Port1 << 8) + 0x01, + P1_2 = (Port1 << 8) + 0x02, + P1_3 = (Port1 << 8) + 0x03, + P1_4 = (Port1 << 8) + 0x04, + P1_5 = (Port1 << 8) + 0x05, + P1_6 = (Port1 << 8) + 0x06, + P1_7 = (Port1 << 8) + 0x07, + + P2_0 = (Port2 << 8) + 0x00, + P2_1 = (Port2 << 8) + 0x01, + P2_2 = (Port2 << 8) + 0x02, + P2_3 = (Port2 << 8) + 0x03, + P2_4 = (Port2 << 8) + 0x04, + P2_5 = (Port2 << 8) + 0x05, + P2_6 = (Port2 << 8) + 0x06, + P2_7 = (Port2 << 8) + 0x07, + + P3_0 = (Port3 << 8) + 0x00, + P3_1 = (Port3 << 8) + 0x01, + P3_2 = (Port3 << 8) + 0x02, + P3_3 = (Port3 << 8) + 0x03, + P3_4 = (Port3 << 8) + 0x04, + P3_5 = (Port3 << 8) + 0x05, + P3_6 = (Port3 << 8) + 0x06, + P3_7 = (Port3 << 8) + 0x07, + + P4_0 = (Port4 << 8) + 0x00, + P4_1 = (Port4 << 8) + 0x01, + P4_2 = (Port4 << 8) + 0x02, + P4_3 = (Port4 << 8) + 0x03, + P4_4 = (Port4 << 8) + 0x04, + P4_5 = (Port4 << 8) + 0x05, + P4_6 = (Port4 << 8) + 0x06, + P4_7 = (Port4 << 8) + 0x07, + + P5_0 = (Port5 << 8) + 0x00, + P5_1 = (Port5 << 8) + 0x01, + P5_2 = (Port5 << 8) + 0x02, + P5_3 = (Port5 << 8) + 0x03, + P5_4 = (Port5 << 8) + 0x04, + P5_5 = (Port5 << 8) + 0x05, + P5_6 = (Port5 << 8) + 0x06, + P5_7 = (Port5 << 8) + 0x07, + + P6_0 = (Port6 << 8) + 0x00, + P6_1 = (Port6 << 8) + 0x01, + P6_2 = (Port6 << 8) + 0x02, + P6_3 = (Port6 << 8) + 0x03, + P6_4 = (Port6 << 8) + 0x04, + P6_5 = (Port6 << 8) + 0x05, + P6_6 = (Port6 << 8) + 0x06, + P6_7 = (Port6 << 8) + 0x07, + + P7_0 = (Port7 << 8) + 0x00, + P7_1 = (Port7 << 8) + 0x01, + P7_2 = (Port7 << 8) + 0x02, + P7_3 = (Port7 << 8) + 0x03, + P7_4 = (Port7 << 8) + 0x04, + P7_5 = (Port7 << 8) + 0x05, + P7_6 = (Port7 << 8) + 0x06, + P7_7 = (Port7 << 8) + 0x07, + + P8_0 = (Port8 << 8) + 0x00, + P8_1 = (Port8 << 8) + 0x01, + P8_2 = (Port8 << 8) + 0x02, + P8_3 = (Port8 << 8) + 0x03, + P8_4 = (Port8 << 8) + 0x04, + P8_5 = (Port8 << 8) + 0x05, + P8_6 = (Port8 << 8) + 0x06, + P8_7 = (Port8 << 8) + 0x07, + + P9_0 = (Port9 << 8) + 0x00, + P9_1 = (Port9 << 8) + 0x01, + P9_2 = (Port9 << 8) + 0x02, + P9_3 = (Port9 << 8) + 0x03, + P9_4 = (Port9 << 8) + 0x04, + P9_5 = (Port9 << 8) + 0x05, + P9_6 = (Port9 << 8) + 0x06, + P9_7 = (Port9 << 8) + 0x07, + + P10_0 = (Port10 << 8) + 0x00, + P10_1 = (Port10 << 8) + 0x01, + P10_2 = (Port10 << 8) + 0x02, + P10_3 = (Port10 << 8) + 0x03, + P10_4 = (Port10 << 8) + 0x04, + P10_5 = (Port10 << 8) + 0x05, + P10_6 = (Port10 << 8) + 0x06, + P10_7 = (Port10 << 8) + 0x07, + + P11_0 = (Port11 << 8) + 0x00, + P11_1 = (Port11 << 8) + 0x01, + P11_2 = (Port11 << 8) + 0x02, + P11_3 = (Port11 << 8) + 0x03, + P11_4 = (Port11 << 8) + 0x04, + P11_5 = (Port11 << 8) + 0x05, + P11_6 = (Port11 << 8) + 0x06, + P11_7 = (Port11 << 8) + 0x07, + + P12_0 = (Port12 << 8) + 0x00, + P12_1 = (Port12 << 8) + 0x01, + P12_2 = (Port12 << 8) + 0x02, + P12_3 = (Port12 << 8) + 0x03, + P12_4 = (Port12 << 8) + 0x04, + P12_5 = (Port12 << 8) + 0x05, + P12_6 = (Port12 << 8) + 0x06, + P12_7 = (Port12 << 8) + 0x07, + + P13_0 = (Port13 << 8) + 0x00, + P13_1 = (Port13 << 8) + 0x01, + P13_2 = (Port13 << 8) + 0x02, + P13_3 = (Port13 << 8) + 0x03, + P13_4 = (Port13 << 8) + 0x04, + P13_5 = (Port13 << 8) + 0x05, + P13_6 = (Port13 << 8) + 0x06, + P13_7 = (Port13 << 8) + 0x07, + + P14_0 = (Port14 << 8) + 0x00, + P14_1 = (Port14 << 8) + 0x01, + P14_2 = (Port14 << 8) + 0x02, + P14_3 = (Port14 << 8) + 0x03, + P14_4 = (Port14 << 8) + 0x04, + P14_5 = (Port14 << 8) + 0x05, + P14_6 = (Port14 << 8) + 0x06, + P14_7 = (Port14 << 8) + 0x07, + + // Arduino connector namings + A0 = P10_4, + A1 = P10_5, + A2 = P10_2, + A3 = P10_3, + A4 = P10_1, + A5 = P10_0, + + D0 = P6_4, + D1 = P6_5, + D2 = P10_6, + D3 = P12_6, + D4 = P12_7, + D5 = P6_2, + D6 = P6_3, + D7 = P7_2, + D8 = P7_1, + D9 = P7_7, + D10 = P9_4, + D11 = P9_0, + D12 = P9_1, + D13 = P9_2, + D14 = P10_1, + D15 = P10_0, + + // Generic signal names + + I2C_SCL = P10_0, + I2C_SDA = P10_1, + SPI_MOSI = P9_0, + SPI_MISO = P9_1, + SPI_CLK = P9_2, + SPI_CS = P9_3, + UART_RX = P6_4, + UART_TX = P6_5, + + SWITCH2 = P0_4, + LED1 = P6_2, + LED2 = P6_3, + LED3 = P7_2, + LED4 = P6_2, + LED_RED = LED1, + + USER_BUTTON = SWITCH2, + BUTTON1 = USER_BUTTON, + + // Standardized interfaces names + STDIO_UART_TX = CY_STDIO_UART_TX, + STDIO_UART_RX = CY_STDIO_UART_RX, + STDIO_UART_CTS = CY_STDIO_UART_CTS, + STDIO_UART_RTS = CY_STDIO_UART_RTS, + USBTX = CY_STDIO_UART_TX, + USBRX = CY_STDIO_UART_RX, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// PinName[15-0] = Port[15-8] + Pin[4-0] +static inline unsigned CY_PIN(PinName pin) +{ + return pin & 0x07; +} + +static inline unsigned CY_PORT(PinName pin) +{ + return (pin >> 8) & 0xFF; +} + +// Because MBED pin mapping API does not allow to map multiple instances of the PWM +// to be mapped to the same pin, we create special pin names to force 32-bit PWM unit +// usage instead of standard 16-bit PWM. + +#define PWM32(pin) CY_PIN_FORCE_PWM_32(pin) + + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/TARGET_FUTURE_SEQUANA_M0/board_config.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/TARGET_FUTURE_SEQUANA_M0/board_config.c new file mode 100644 index 0000000000..6570356cfb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/TARGET_FUTURE_SEQUANA_M0/board_config.c @@ -0,0 +1,330 @@ + +/******************************************************************************* +* File Name: board_config.c (formerly cyfitter_cfg.c) +* +* PSoC Creator 4.2 +* +* Description: +* This file contains device initialization code. +* Except for the user defined sections in CyClockStartupError(), this file should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright 2007-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2017-2018, Future Electronics +* SPDX-License-Identifier: Apache-2.0 +********************************************************************************/ + +#include +#include "device.h" +#include "gpio/cy_gpio.h" +#include "syslib/cy_syslib.h" +#include "sysclk/cy_sysclk.h" +#include "systick/cy_systick.h" +#include "sysanalog/cy_sysanalog.h" + +#if FEATURE_BLE +#include "ble/cy_ble_clk.h" +#endif // FEATURE_BLE + +#define CY_NEED_CYCLOCKSTARTUPERROR 1 +#include "syspm/cy_syspm.h" + +#include "psoc6_utils.h" + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#define CYPACKED +#define CYPACKED_ATTR __attribute__ ((packed)) +#define CYALIGNED __attribute__ ((aligned)) +#define CY_CFG_UNUSED __attribute__ ((unused)) +#ifndef CY_CFG_SECTION +#define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) +#endif + +#if defined(__ARMCC_VERSION) +#define CY_CFG_MEMORY_BARRIER() __memory_changed() +#else +#define CY_CFG_MEMORY_BARRIER() __sync_synchronize() +#endif + +#elif defined(__ICCARM__) +#include + +#define CYPACKED __packed +#define CYPACKED_ATTR +#define CYALIGNED _Pragma("data_alignment=4") +#define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") +#define CY_CFG_SECTION _Pragma("location=\".psocinit\"") + +#define CY_CFG_MEMORY_BARRIER() __DMB() + +#else +#error Unsupported toolchain +#endif + +#ifndef CYCODE +#define CYCODE +#endif +#ifndef CYDATA +#define CYDATA +#endif +#ifndef CYFAR +#define CYFAR +#endif +#ifndef CYXDATA +#define CYXDATA +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + + + + +/* Clock startup error codes */ +#define CYCLOCKSTART_NO_ERROR 0u +#define CYCLOCKSTART_XTAL_ERROR 1u +#define CYCLOCKSTART_32KHZ_ERROR 2u +#define CYCLOCKSTART_PLL_ERROR 3u +#define CYCLOCKSTART_FLL_ERROR 4u +#define CYCLOCKSTART_WCO_ERROR 5u + +#ifdef CY_NEED_CYCLOCKSTARTUPERROR +/******************************************************************************* +* Function Name: CyClockStartupError +******************************************************************************** +* Summary: +* If an error is encountered during clock configuration (crystal startup error, +* PLL lock error, etc.), the system will end up here. Unless reimplemented by +* the customer, this function will stop in an infinite loop. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode); +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode) +{ + /* To remove the compiler warning if errorCode not used. */ + errorCode = errorCode; + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + +#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK + CY_CFG_Clock_Startup_ErrorCallback(); +#else + while(1) {} +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ +} +#endif + +static void ClockInit(void) +{ + uint32_t status; + + /* Enable all source clocks */ + status = Cy_SysClk_WcoEnable(500000u); + if (CY_RET_SUCCESS != status) { + CyClockStartupError(CYCLOCKSTART_WCO_ERROR); + } + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); + +#if FEATURE_BLE + { + cy_stc_ble_bless_eco_cfg_params_t bleCfg = { + .ecoXtalStartUpTime = (785 / 31.25), + .loadCap = ((9.9 - 7.5) / 0.075), + .ecoFreq = CY_BLE_BLESS_ECO_FREQ_32MHZ, + .ecoSysDiv = CY_BLE_SYS_ECO_CLK_DIV_4 + }; + Cy_BLE_EcoStart(&bleCfg); + } +#endif // FEATURE_BLE + + /* Configure CPU clock dividers */ + Cy_SysClk_ClkFastSetDivider(0u); + Cy_SysClk_ClkPeriSetDivider((CY_CLK_HFCLK0_FREQ_HZ / CY_CLK_PERICLK_FREQ_HZ) - 1); + Cy_SysClk_ClkSlowSetDivider((CY_CLK_PERICLK_FREQ_HZ / CY_CLK_SYSTEM_FREQ_HZ) - 1); + + /* Configure LF & HF clocks */ + Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH1); + Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(0u); + + /* Configure Path Clocks */ + /* PLL path is used to clock HF domain from BLE ECO */ + Cy_SysClk_ClkPathSetSource(2, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkPathSetSource(3, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkPathSetSource(4, CY_SYSCLK_CLKPATH_IN_IMO); +#if FEATURE_BLE + Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_ALTHF); + Cy_SysClk_ClkPathSetSource(1, CY_SYSCLK_CLKPATH_IN_ALTHF); + { + const cy_stc_pll_config_t pllConfig = { + .inputFreq = CY_CLK_ALTHF_FREQ_HZ, + .outputFreq = CY_CLK_HFCLK0_FREQ_HZ, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO + }; +#else + Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkPathSetSource(1, CY_SYSCLK_CLKPATH_IN_IMO); + { + const cy_stc_pll_config_t pllConfig = { + .inputFreq = CY_CLK_IMO_FREQ_HZ, + .outputFreq = CY_CLK_HFCLK0_FREQ_HZ, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO + }; +#endif // FEATURE_BLE + status = Cy_SysClk_PllConfigure(1u, &pllConfig); + if (CY_SYSCLK_SUCCESS != status) { + CyClockStartupError(CYCLOCKSTART_PLL_ERROR); + } + } + status = Cy_SysClk_PllEnable(1u, 10000u); + if (CY_SYSCLK_SUCCESS != status) { + CyClockStartupError(CYCLOCKSTART_PLL_ERROR); + } + + /* Configure miscellaneous clocks */ + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV); + Cy_SysClk_ClkTimerSetDivider(0); + Cy_SysClk_ClkTimerEnable(); + Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH0); + Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_DIV_4); + Cy_SysClk_ClkPumpEnable(); + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); + + /* Disable unused clocks started by default */ + Cy_SysClk_IloDisable(); + + /* Set memory wait states based on HFClk[0] */ + Cy_SysLib_SetWaitStates(false, (CY_CLK_HFCLK0_FREQ_HZ + 990000) / 1000000UL); +} + + +/* Analog API Functions */ + + +/******************************************************************************* +* Function Name: AnalogSetDefault +******************************************************************************** +* +* Summary: +* Sets up the analog portions of the chip to default values based on chip +* configuration options from the project. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void AnalogSetDefault(void) +{ + const cy_stc_sysanalog_config_t config = { + .startup = CY_SYSANALOG_STARTUP_NORMAL, + .iztat = CY_SYSANALOG_IZTAT_SOURCE_LOCAL, + .vref = CY_SYSANALOG_VREF_SOURCE_LOCAL_1_2V, + .deepSleep = CY_SYSANALOG_DEEPSLEEP_IPTAT_1 + }; + Cy_SysAnalog_Init(&config); + Cy_SysAnalog_Enable(); +} + + + + +/******************************************************************************* +* Function Name: Cy_SystemInit +******************************************************************************** +* Summary: +* This function is called by the start-up code for the selected device. It +* performs all of the necessary device configuration based on the design +* settings. This includes settings from the Design Wide Resources (DWR) such +* as Clocks and Pins as well as any component configuration that is necessary. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +void Cy_SystemInit(void) +{ + /* Set worst case memory wait states (150 MHz), ClockInit() will update */ + Cy_SysLib_SetWaitStates(false, 150); + + if(0u == Cy_SysLib_GetResetReason()) { /* POR, XRES, or BOD */ + Cy_SysLib_ResetBackupDomain(); + } + + /* Power Mode */ + Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_1_1V); + + /* PMIC Control */ + Cy_SysPm_UnlockPmic(); + Cy_SysPm_DisablePmicOutput(); + + /* Pin0_0 and Pin0_1 drive WCO, configure as analog before configuring clock */ + cy_reserve_io_pin(P0_0); + cy_reserve_io_pin(P0_1); + Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0, CY_GPIO_DM_ANALOG, 0, P0_0_GPIO); + Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1, CY_GPIO_DM_ANALOG, 0, P0_1_GPIO); + + /* Clock */ + ClockInit(); + + /******* Pre-defined port configuration section ********/ + { + /* RGB LED is P_0_3 (R), P_1_1 (G) and P_11_1 (B) */ + const uint32_t led_off = 1; + Cy_GPIO_Pin_FastInit(GPIO_PRT0, 3, CY_GPIO_DM_STRONG_IN_OFF, led_off, P0_3_GPIO); + Cy_GPIO_Pin_FastInit(GPIO_PRT1, 1, CY_GPIO_DM_STRONG_IN_OFF, led_off, P1_1_GPIO); + Cy_GPIO_Pin_FastInit(GPIO_PRT11, 1, CY_GPIO_DM_STRONG_IN_OFF, led_off, P11_1_GPIO); + + /* USER BUTTON is P_0_4 */ + Cy_GPIO_Pin_FastInit(GPIO_PRT0, 4, CY_GPIO_DM_PULLUP, 1, P0_4_GPIO); + + /* Configure hw debug interface on port 6 */ + cy_reserve_io_pin(P6_6); + cy_reserve_io_pin(P6_7); + Cy_GPIO_Pin_FastInit(GPIO_PRT6, 6, CY_GPIO_DM_PULLUP, 0, P6_6_CPUSS_SWJ_SWDIO_TMS); + Cy_GPIO_Pin_FastInit(GPIO_PRT6, 7, CY_GPIO_DM_PULLDOWN, 0, P6_7_CPUSS_SWJ_SWCLK_TCLK); + } + + /* Perform basic analog initialization to defaults */ + AnalogSetDefault(); + +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/stdio_init.cpp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/stdio_init.cpp new file mode 100644 index 0000000000..5aabfe4b3b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/stdio_init.cpp @@ -0,0 +1,30 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" + +/* + * This makes sure, stdio serial is initialized on M4 core at the very beginning + * and outside of any critical context, so printf is usable anywhere, including + * interrupt and fault handlers. + * Hardware devices cannot be initialized in the interrupt or critical section context + * on PSoC 6 M4 core. + */ + +#if DEVICE_STDIO_MESSAGES && !defined(TARGET_MCU_PSOC6_M0) +Serial _stdio_uart_object(STDIO_UART_TX, STDIO_UART_RX); +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/analogin_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/analogin_api.c new file mode 100644 index 0000000000..9e57aa551b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/analogin_api.c @@ -0,0 +1,171 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "device.h" +#include "analogin_api.h" +#include "cy_sar.h" +#include "psoc6_utils.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "platform/mbed_error.h" + +#if DEVICE_ANALOGIN + +const uint16_t ADC_MAX_VALUE = 0x0fff; + +const uint32_t SAR_BASE_CLOCK_HZ = 18000000; // 18 MHz or less + +/** Default SAR channel configuration. + * Notice, that because dynamic SAR MUX switching is disabled, + * per-channel MUX configuration is ignored, thus not configured here. + */ +#define DEFAULT_CHANNEL_CONFIG ( \ + CY_SAR_CHAN_SINGLE_ENDED | \ + CY_SAR_CHAN_AVG_ENABLE | \ + CY_SAR_CHAN_SAMPLE_TIME_0 \ +) + + +/** Global SAR configuration data, modified as channels are configured. + */ +static cy_stc_sar_config_t sar_config = { + .ctrl = CY_SAR_VREF_SEL_VDDA_DIV_2 | + CY_SAR_NEG_SEL_VREF | + CY_SAR_CTRL_COMP_DLY_12 | + CY_SAR_COMP_PWR_50 | + CY_SAR_SARSEQ_SWITCH_DISABLE, /**< Control register */ + .sampleCtrl = CY_SAR_RIGHT_ALIGN | + CY_SAR_SINGLE_ENDED_UNSIGNED | + CY_SAR_AVG_CNT_16 | + CY_SAR_AVG_MODE_SEQUENTIAL_FIXED | + CY_SAR_TRIGGER_MODE_FW_ONLY, /**< Sample control register */ + .sampleTime01 = (4uL << CY_SAR_SAMPLE_TIME0_SHIFT) | + (4uL << CY_SAR_SAMPLE_TIME1_SHIFT), /**< Sample time in ADC clocks for ST0 and ST1 */ + .sampleTime23 = (4uL << CY_SAR_SAMPLE_TIME2_SHIFT) | + (4uL << CY_SAR_SAMPLE_TIME3_SHIFT), /**< Sample time in ADC clocks for ST2 and ST3 */ + .rangeThres = 0, /**< Range detect threshold register for all channels (unused)*/ + .rangeCond = 0, /**< Range detect mode for all channels (unused)*/ + .chanEn = 0, /**< Enable bits for the channels */ + .chanConfig = { /**< Channel configuration registers */ + DEFAULT_CHANNEL_CONFIG, // chn 0 + DEFAULT_CHANNEL_CONFIG, // chn 1 + DEFAULT_CHANNEL_CONFIG, // chn 2 + DEFAULT_CHANNEL_CONFIG, // chn 3 + DEFAULT_CHANNEL_CONFIG, // chn 4 + DEFAULT_CHANNEL_CONFIG, // chn 5 + DEFAULT_CHANNEL_CONFIG, // chn 6 + DEFAULT_CHANNEL_CONFIG, // chn 7 + DEFAULT_CHANNEL_CONFIG, // chn 8 + DEFAULT_CHANNEL_CONFIG, // chn 9 + DEFAULT_CHANNEL_CONFIG, // chn 10 + DEFAULT_CHANNEL_CONFIG, // chn 11 + DEFAULT_CHANNEL_CONFIG, // chn 12 + DEFAULT_CHANNEL_CONFIG, // chn 13 + DEFAULT_CHANNEL_CONFIG, // chn 14 + DEFAULT_CHANNEL_CONFIG, // chn 15 + }, + .intrMask = 0, /**< Interrupt enable mask */ + .satIntrMask = 0, /**< Saturate interrupt mask register */ + .rangeIntrMask = 0, /**< Range interrupt mask register */ + .muxSwitch = 0, /**< SARMUX firmware switches to connect analog signals to SAR */ + .muxSwitchSqCtrl = 0, /**< SARMUX Switch SAR sequencer control */ + .configRouting = false, /**< Configure or ignore routing related registers (muxSwitch, muxSwitchSqCtrl) */ + .vrefMvValue = 0, /**< Reference voltage in millivolts used in counts to volts conversion */ +}; + +static bool sar_initialized = false; + + +static void sar_init(analogin_t *obj) +{ + if (!sar_initialized) { + uint32_t sar_clock_divider = CY_INVALID_DIVIDER; + + sar_initialized = true; + // Allocate and setup clock. + sar_clock_divider = cy_clk_allocate_divider(CY_SYSCLK_DIV_8_BIT); + if (sar_clock_divider == CY_INVALID_DIVIDER) { + error("SAR clock divider allocation failed."); + return; + } + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, + sar_clock_divider, + ((CY_CLK_PERICLK_FREQ_HZ + SAR_BASE_CLOCK_HZ / 2) / SAR_BASE_CLOCK_HZ) - 1); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, sar_clock_divider); + Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_8_BIT, sar_clock_divider); + + Cy_SAR_Init(obj->base, &sar_config); + Cy_SAR_Enable(obj->base); + } +} + +void analogin_init(analogin_t *obj, PinName pin) +{ + uint32_t sar = 0; + uint32_t sar_function = 0; + + MBED_ASSERT(obj); + MBED_ASSERT(pin != (PinName)NC); + + + sar = pinmap_peripheral(pin, PinMap_ADC); + if (sar != (uint32_t)NC) { + if (cy_reserve_io_pin(pin)) { + error("ANALOG IN pin reservation conflict."); + } + obj->base = (SAR_Type*)CY_PERIPHERAL_BASE(sar); + obj->pin = pin; + obj->channel_mask = 1 << CY_PIN(pin); + + // Configure clock. + sar_function = pinmap_function(pin, PinMap_ADC); + obj->clock = CY_PIN_CLOCK(sar_function); + sar_init(obj); + pin_function(pin, sar_function); + } else { + error("ANALOG IN pinout mismatch."); + } +} + +float analogin_read(analogin_t *obj) +{ + uint16_t result = analogin_read_u16(obj); + + return (float)result * (1.0 / ADC_MAX_VALUE); +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint32_t result = 0; + + Cy_SAR_SetChanMask(obj->base, obj->channel_mask); + Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_CLOSE); + Cy_SAR_StartConvert(obj->base, CY_SAR_START_CONVERT_SINGLE_SHOT); + if (Cy_SAR_IsEndConversion(obj->base, CY_SAR_WAIT_FOR_RESULT) == CY_SAR_SUCCESS) { + result = Cy_SAR_GetResult32(obj->base, CY_PIN(obj->pin)); + } else { + error("ANALOG IN: measurement failed!"); + } + Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_OPEN); + // We are running 16x oversampling extending results to 16 bits. + return (uint16_t)(result); +} + +#endif // DEVICE_ANALOGIN + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/analogout_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/analogout_api.c new file mode 100644 index 0000000000..98be654530 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/analogout_api.c @@ -0,0 +1,150 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "device.h" +#include "analogout_api.h" +#include "cy_ctdac.h" +#include "psoc6_utils.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "platform/mbed_error.h" + +#if DEVICE_ANALOGOUT + +#define CTDAC_NUM_BITS 12 +const uint16_t CTDAC_MAX_VALUE = (uint16_t)((1UL << CTDAC_NUM_BITS) - 1); + +const uint32_t CTDAC_BASE_CLOCK_HZ = 500000; // 500 kHz or less + +#define CTDAC_DEGLITCH_CYCLES 35 + + + +/** Global CTDAC configuration data. + */ +static cy_stc_ctdac_config_t ctdac_config = { + .refSource = CY_CTDAC_REFSOURCE_VDDA, /**< Reference source: Vdda or externally through Opamp1 of CTB */ + .formatMode = CY_CTDAC_FORMAT_UNSIGNED, /**< Format of DAC value: signed or unsigned */ + .updateMode = CY_CTDAC_UPDATE_BUFFERED_WRITE, /**< Update mode: direct or buffered writes or hardware, edge or level */ + .deglitchMode = CY_CTDAC_DEGLITCHMODE_UNBUFFERED, /**< Deglitch mode: disabled, buffered, unbuffered, or both */ + .outputMode = CY_CTDAC_OUTPUT_VALUE, /**< Output mode: enabled (value or value + 1), high-z, Vssa, or Vdda */ + .outputBuffer = CY_CTDAC_OUTPUT_UNBUFFERED, /**< Output path: Buffered through Opamp0 of CTB or connected directly to Pin 6 */ + .deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE, /**< Enable or disable the CTDAC during Deep Sleep */ + .deglitchCycles = CTDAC_DEGLITCH_CYCLES, /**< Number of deglitch cycles from 0 to 63 */ + .value = 0, /**< Current DAC value */ + .nextValue = 0, /**< Next DAC value for double buffering */ + .enableInterrupt = false, /**< If true, enable interrupt when next value register is transferred to value register */ + .configClock = false, /**< Configure or ignore clock information */ +}; + + +static bool ctdac_initialized = 0; + +static void ctdac_init(dac_t *obj) +{ + if (!ctdac_initialized) { + uint32_t dac_clock_divider = CY_INVALID_DIVIDER; + + ctdac_initialized = true; + // Allocate and setup clock. + dac_clock_divider = cy_clk_allocate_divider(CY_SYSCLK_DIV_8_BIT); + if (dac_clock_divider == CY_INVALID_DIVIDER) { + error("CTDAC clock divider allocation failed."); + return; + } + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, + dac_clock_divider, + ((CY_CLK_PERICLK_FREQ_HZ + CTDAC_BASE_CLOCK_HZ / 2) / CTDAC_BASE_CLOCK_HZ) - 1); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, dac_clock_divider); + Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_8_BIT, dac_clock_divider); + + Cy_CTDAC_Init(obj->base, &ctdac_config); + Cy_CTDAC_Enable(obj->base); + } +} + + +void analogout_init(dac_t *obj, PinName pin) +{ + uint32_t dac = 0; + uint32_t dac_function = 0; + + MBED_ASSERT(obj); + MBED_ASSERT(pin != (PinName)NC); + + dac = pinmap_peripheral(pin, PinMap_DAC); + if (dac != (uint32_t)NC) { + if (cy_reserve_io_pin(pin)) { + error("ANALOG OUT pin reservation conflict."); + } + obj->base = (CTDAC_Type*)CY_PERIPHERAL_BASE(dac); + obj->pin = pin; + + // Configure clock. + dac_function = pinmap_function(pin, PinMap_DAC); + obj->clock = CY_PIN_CLOCK(dac_function); + pin_function(pin, dac_function); + ctdac_init(obj); + } else { + error("ANALOG OUT pinout mismatch."); + } +} + +void analogout_free(dac_t *obj) +{ + // Not supported yet. +} + +void analogout_write(dac_t *obj, float value) +{ + uint32_t val = 0; + + if (value > 1.0) { + val = CTDAC_MAX_VALUE; + } else if (value > 0.0) { + val = value * CTDAC_MAX_VALUE; + } + Cy_CTDAC_SetValueBuffered(obj->base, val); +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + uint32_t val = 0; + + val = (value >> (16 - CTDAC_NUM_BITS)); // Convert from 16-bit range. + + Cy_CTDAC_SetValueBuffered(obj->base, val); +} + +float analogout_read(dac_t *obj) +{ + return (float)analogout_read_u16(obj) / 0xffff; +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + uint16_t value = (obj->base->CTDAC_VAL_NXT >> CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk; + + value <<= (16 - CTDAC_NUM_BITS); // Convert to 16-bit range. + + return value; +} + +#endif // DEVICE_ANALOGIN + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/PDL_Version.txt b/targets/TARGET_Cypress/TARGET_PSOC6/device/PDL_Version.txt new file mode 100644 index 0000000000..9cac515901 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/PDL_Version.txt @@ -0,0 +1,2 @@ +version 3.0.1 + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/device/README.md new file mode 100644 index 0000000000..9d2b3a0bdc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/README.md @@ -0,0 +1,4 @@ +README for Cypress Peripheral Driver Library +============================================ + +This folder tree contains parts of Cypress Peripheral Driver Library (PDL) necessary to support PSoC 6 MCUs. See [Cypress PDL page](http://www.cypress.com/documentation/software-and-drivers/peripheral-driver-library-pdl) for details. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.c new file mode 100644 index 0000000000..ba0d725b21 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.c @@ -0,0 +1,1355 @@ +/***************************************************************************//** +* \file cy_ctb.c +* \version 1.0 +* +* \brief +* Provides the public functions for the CTB driver. +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "ctb/cy_ctb.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Fast Config Selections +***************************************/ +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Unused = +{ + /*.oa0Power */ CY_CTB_POWER_OFF, + /*.oa0Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa0SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_COMP, + /*.oa0SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa0SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp10x = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa0SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Diffamp = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_POS_PIN0_MASK | (uint32_t) CY_CTB_SW_OA0_NEG_PIN1_MASK, + /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK, + /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK, +}; + +const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out_SH = +{ + /*.oa0Power */ CY_CTB_POWER_MEDIUM, + /*.oa0Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa0SwitchCtrl */ (uint32_t) CY_CTB_SW_OA0_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK, + /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK | (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Unused = +{ + /*.oa1Power */ CY_CTB_POWER_OFF, + /*.oa1Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa1SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Comp = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_COMP, + /*.oa1SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp1x = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa1SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp10x = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa1SwitchCtrl */ CY_CTB_DEINIT, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Diffamp = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_OPAMP10X, + /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_POS_PIN7_MASK | (uint32_t) CY_CTB_SW_OA1_NEG_PIN4_MASK, + /*.ctdSwitchCtrl */ CY_CTB_DEINIT, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA1_POS_AREF_MASK, + /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_REF_OA1_OUT_MASK, +}; + +const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 = +{ + /*.oa1Power */ CY_CTB_POWER_MEDIUM, + /*.oa1Mode */ CY_CTB_MODE_OPAMP1X, + /*.oa1SwitchCtrl */ (uint32_t) CY_CTB_SW_OA1_NEG_OUT_MASK | (uint32_t) CY_CTB_SW_OA1_POS_PIN5_MASK, + /*.ctdSwitchCtrl */ (uint32_t) CY_CTB_SW_CTD_REF_OA1_OUT_MASK, +}; + +/******************************************************************************* +* Function Name: Cy_CTB_Init +****************************************************************************//** +* +* Initialize or restore the CTB and both opamps according to the +* provided settings. Parameters are usually set only once, at initialization. +* +* \param base +* Pointer to structure describing registers +* +* \param config +* Pointer to structure containing configuration data for entire CTB +* +* \return +* Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM +* +* \funcusage +* +* The following code snippet configures Opamp0 as a comparator +* and Opamp1 as an opamp follower with 10x drive. The terminals +* are routed to external pins by closing the switches shown. +* +* \image html ctb_init_funcusage.png +* \image latex ctb_init_funcusage.png +* +* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_CTBINIT +* +*******************************************************************************/ +cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config) +{ + CY_ASSERT_L1(NULL != base); + CY_ASSERT_L1(NULL != config); + + cy_en_ctb_status_t result; + + if ((NULL == base) || (NULL == config)) + { + result = CY_CTB_BAD_PARAM; + } + else + { + CY_ASSERT_L3(CY_CTB_DEEPSLEEP(config->deepSleep)); + + /* Enum checks for Opamp0 config */ + CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa0Power)); + CY_ASSERT_L3(CY_CTB_OAMODE(config->oa0Mode)); + CY_ASSERT_L3(CY_CTB_OAPUMP(config->oa0Pump)); + CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oa0CompEdge)); + CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oa0CompLevel)); + CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oa0CompBypass)); + CY_ASSERT_L3(CY_CTB_COMPHYST(config->oa0CompHyst)); + + /* Enum checks for Opamp0 config */ + CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa1Power)); + CY_ASSERT_L3(CY_CTB_OAMODE(config->oa1Mode)); + CY_ASSERT_L3(CY_CTB_OAPUMP(config->oa1Pump)); + CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oa1CompEdge)); + CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oa1CompLevel)); + CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oa1CompBypass)); + CY_ASSERT_L3(CY_CTB_COMPHYST(config->oa1CompHyst)); + + /* Boundary checks for analog routing switch masks */ + CY_ASSERT_L2(CY_CTB_OA0SWITCH(config->oa0SwitchCtrl)); + CY_ASSERT_L2(CY_CTB_OA1SWITCH(config->oa1SwitchCtrl)); + CY_ASSERT_L2(CY_CTB_CTDSWITCH(config->ctdSwitchCtrl)); + + base->CTB_CTRL = (uint32_t) config->deepSleep; + base->OA_RES0_CTRL = (uint32_t) config->oa0Power \ + | (uint32_t) config->oa0Mode \ + | (uint32_t) config->oa0Pump \ + | (uint32_t) config->oa0CompEdge \ + | (uint32_t) config->oa0CompLevel \ + | (uint32_t) config->oa0CompBypass \ + | (uint32_t) config->oa0CompHyst \ + | ((CY_CTB_MODE_OPAMP1X == config->oa0Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); + + base->OA_RES1_CTRL = (uint32_t) config->oa1Power \ + | (uint32_t) config->oa1Mode \ + | (uint32_t) config->oa1Pump \ + | (uint32_t) config->oa1CompEdge \ + | (uint32_t) config->oa1CompLevel \ + | (uint32_t) config->oa1CompBypass \ + | (uint32_t) config->oa1CompHyst \ + | ((CY_CTB_MODE_OPAMP1X == config->oa1Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); + + base->INTR_MASK = (config->oa0CompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT) \ + | (config->oa1CompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT); + + base->OA0_COMP_TRIM = (uint32_t) ((config->oa0Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + base->OA1_COMP_TRIM = (uint32_t) ((config->oa1Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + + if (config->configRouting) + { + base->OA0_SW = config->oa0SwitchCtrl; + base->OA1_SW = config->oa1SwitchCtrl; + base->CTD_SW = config->ctdSwitchCtrl; + } + + result = CY_CTB_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpampInit +****************************************************************************//** +* +* Initialize each opamp separately without impacting analog routing. +* Intended for use by automatic analog routing and configuration tools +* to configure each opamp without having to integrate the settings with +* those of the other opamp first. +* +* Can also be used to configure both opamps to have the same settings. +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \param config +* Pointer to structure containing configuration data +* +* \return +* Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_OPAMPINIT +* +*******************************************************************************/ +cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, const cy_stc_ctb_opamp_config_t *config) +{ + CY_ASSERT_L1(NULL != base); + CY_ASSERT_L1(NULL != config); + + cy_en_ctb_status_t result; + uint32_t oaResCtrl; + + if ((NULL == base) || (NULL == config)) + { + result = CY_CTB_BAD_PARAM; + } + else + { + CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum)); + CY_ASSERT_L3(CY_CTB_DEEPSLEEP(config->deepSleep)); + CY_ASSERT_L3(CY_CTB_OAPOWER(config->oaPower)); + CY_ASSERT_L3(CY_CTB_OAMODE(config->oaMode)); + CY_ASSERT_L3(CY_CTB_OAPUMP(config->oaPump)); + CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oaCompEdge)); + CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oaCompLevel)); + CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oaCompBypass)); + CY_ASSERT_L3(CY_CTB_COMPHYST(config->oaCompHyst)); + + base->CTB_CTRL = (uint32_t) config->deepSleep; + + /* The two opamp control registers are symmetrical */ + oaResCtrl = (uint32_t) config->oaPower \ + | (uint32_t) config->oaMode \ + | (uint32_t) config->oaPump \ + | (uint32_t) config->oaCompEdge \ + | (uint32_t) config->oaCompLevel \ + | (uint32_t) config->oaCompBypass \ + | (uint32_t) config->oaCompHyst \ + | ((CY_CTB_MODE_OPAMP1X == config->oaMode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); + + if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA_RES0_CTRL = oaResCtrl; + base->OA0_COMP_TRIM = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + + /* The INTR_MASK register is shared between the two opamps */ + base->INTR_MASK |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP0_MASK_Msk : CY_CTB_DEINIT); + } + + if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA_RES1_CTRL = oaResCtrl; + base->OA1_COMP_TRIM = (uint32_t) ((config->oaMode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + + /* The INTR_MASK register is shared between the two opamps */ + base->INTR_MASK |= (config->oaCompIntrEn ? CTBM_INTR_MASK_COMP1_MASK_Msk : CY_CTB_DEINIT); + } + + result = CY_CTB_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTB_DeInit +****************************************************************************//** +* +* Reset CTB registers back to power on reset defaults. +* +* \param base +* Pointer to structure describing registers +* +* \param deInitRouting +* If true, all analog routing switches are reset to their default state. +* If false, analog switch registers are untouched. +* +* \return +* Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM +* +*******************************************************************************/ +cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting) +{ + CY_ASSERT_L1(NULL != base); + + cy_en_ctb_status_t result; + + if (NULL == base) + { + result = CY_CTB_BAD_PARAM; + } + else + { + base->CTB_CTRL = CY_CTB_DEINIT; + base->OA_RES0_CTRL = CY_CTB_DEINIT; + base->OA_RES1_CTRL = CY_CTB_DEINIT; + base->INTR_MASK = CY_CTB_DEINIT; + + if (deInitRouting) + { + base->OA0_SW_CLEAR = CY_CTB_DEINIT_OA0_SW; + base->OA1_SW_CLEAR = CY_CTB_DEINIT_OA1_SW; + base->CTD_SW_CLEAR = CY_CTB_DEINIT_CTD_SW; + } + + result = CY_CTB_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTB_FastInit +****************************************************************************//** +* +* Initialize each opamp of the CTB to one of the common use modes. +* +* This function provides a quick and easy method of configuring the CTB +* using pre-defined configurations. +* Only routing switches required for the selected mode are configured, leaving final input and output connections +* to the user. +* Additional use modes that relate to the \ref group_ctdac "CTDAC" +* are provided to support easy configuration of the CTDAC output buffer and input +* reference buffer. +* +* The fast configuration structures define the opamp power, mode, and routing. +* This function sets the other configuration options of the CTB to: +* - .deepSleep = CY_CTB_DEEPSLEEP_DISABLE +* - .oaPump = \ref CY_CTB_PUMP_ENABLE +* - .oaCompEdge = \ref CY_CTB_COMP_EDGE_BOTH +* - .oaCompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL +* - .oaCompBypass = \ref CY_CTB_COMP_BYPASS_SYNC +* - .oaCompHyst = \ref CY_CTB_COMP_HYST_10MV +* - .oaCompIntrEn = true + +* \param base +* Pointer to structure describing registers +* +* \param config0 +* Pointer to structure containing configuration data for quick initialization +* of Opamp0. Defined your own or use one of the provided structures: +* - \ref Cy_CTB_Fast_Opamp0_Unused +* - \ref Cy_CTB_Fast_Opamp0_Comp +* - \ref Cy_CTB_Fast_Opamp0_Opamp1x +* - \ref Cy_CTB_Fast_Opamp0_Opamp10x +* - \ref Cy_CTB_Fast_Opamp0_Diffamp +* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out +* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH +* +* \param config1 +* Pointer to structure containing configuration data for quick initialization +* of Opamp1. Defined your own or use one of the provided structures: +* - \ref Cy_CTB_Fast_Opamp1_Unused +* - \ref Cy_CTB_Fast_Opamp1_Comp +* - \ref Cy_CTB_Fast_Opamp1_Opamp1x +* - \ref Cy_CTB_Fast_Opamp1_Opamp10x +* - \ref Cy_CTB_Fast_Opamp1_Diffamp +* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref +* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 +* +* \return +* Status of initialization, \ref CY_CTB_SUCCESS or \ref CY_CTB_BAD_PARAM +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_FASTINIT +* +*******************************************************************************/ +cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config_oa0_t *config0, const cy_stc_ctb_fast_config_oa1_t *config1) +{ + CY_ASSERT_L1(NULL != base); + CY_ASSERT_L1(NULL != config0); + CY_ASSERT_L1(NULL != config1); + + cy_en_ctb_status_t result; + + if ((NULL == base) || (NULL == config0) || (NULL == config1)) + { + result = CY_CTB_BAD_PARAM; + } + else + { + /* Enum and boundary checks for config0 */ + CY_ASSERT_L3(CY_CTB_OAPOWER(config0->oa0Power)); + CY_ASSERT_L3(CY_CTB_OAMODE(config0->oa0Mode)); + CY_ASSERT_L2(CY_CTB_OA0SWITCH(config0->oa0SwitchCtrl)); + CY_ASSERT_L2(CY_CTB_CTDSWITCH(config0->ctdSwitchCtrl)); + + /* Enum and boundary checks for config1 */ + CY_ASSERT_L3(CY_CTB_OAPOWER(config1->oa1Power)); + CY_ASSERT_L3(CY_CTB_OAMODE(config1->oa1Mode)); + CY_ASSERT_L2(CY_CTB_OA1SWITCH(config1->oa1SwitchCtrl)); + CY_ASSERT_L2(CY_CTB_CTDSWITCH(config1->ctdSwitchCtrl)); + + base->CTB_CTRL = (uint32_t) CY_CTB_DEEPSLEEP_DISABLE; + + base->OA_RES0_CTRL = (uint32_t) config0->oa0Power \ + | (uint32_t) config0->oa0Mode \ + | (uint32_t) CY_CTB_PUMP_ENABLE \ + | (uint32_t) CY_CTB_COMP_EDGE_BOTH \ + | (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL \ + | (uint32_t) CY_CTB_COMP_BYPASS_SYNC \ + | (uint32_t) CY_CTB_COMP_HYST_10MV \ + | ((CY_CTB_MODE_OPAMP1X == config0->oa0Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); + + base->OA_RES1_CTRL = (uint32_t) config1->oa1Power \ + | (uint32_t) config1->oa1Mode \ + | (uint32_t) CY_CTB_PUMP_ENABLE \ + | (uint32_t) CY_CTB_COMP_EDGE_BOTH \ + | (uint32_t) CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL \ + | (uint32_t) CY_CTB_COMP_BYPASS_SYNC \ + | (uint32_t) CY_CTB_COMP_HYST_10MV \ + | ((CY_CTB_MODE_OPAMP1X == config1->oa1Mode) ? CY_CTB_OPAMP_BOOST_ENABLE : CY_CTB_OPAMP_BOOST_DISABLE); + + base->INTR_MASK = CTBM_INTR_MASK_COMP0_MASK_Msk | CTBM_INTR_MASK_COMP1_MASK_Msk; + + base->OA0_COMP_TRIM = (uint32_t) ((config0->oa0Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + base->OA1_COMP_TRIM = (uint32_t) ((config1->oa1Mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + + base->OA0_SW = config0->oa0SwitchCtrl; + base->OA1_SW = config1->oa1SwitchCtrl; + base->CTD_SW = config0->ctdSwitchCtrl | config1->ctdSwitchCtrl; + + result = CY_CTB_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetCurrentMode +****************************************************************************//** +* +* High level function to configure the current modes of the opamps. +* This function configures all opamps of the CTB to the same current mode. +* These modes are differentiated by the reference current level, the opamp +* input range, and the Deep Sleep mode operation. +* +* - The reference current level is set using \ref Cy_CTB_SetIptatLevel +* - When 1 uA current level is used in Deep Sleep, +* - All generators in the AREF must be enabled in Deep Sleep. That is, +* \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF. +* - When 100 nA current level is used, +* - \ref Cy_CTB_EnableRedirect is called to route the AREF IPTAT reference +* to the opamp IZTAT and disable the opamps IPTAT. +* - The IPTAT generator is enabled in Deep Sleep. That is, +* \ref Cy_SysAnalog_SetDeepSleepMode is called with CY_SYSANALOG_DEEPSLEEP_IPTAT_2 +* unless it is already configured for CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF. +* +* \note +* The IPTAT level is a chip wide configuration so multiple +* opamps cannot operate at different IPTAT levels. +* When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device, +* it should be called for all other CTB instances as well. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Current ModeIPTAT LevelInput RangeDeep Sleep Operation
\ref CY_CTB_CURRENT_HIGH_ACTIVE1 uARail-to-Rail (charge pump enabled)Disabled in Deep Sleep
\ref CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP1 uA0 - VDDA-1.5 V (charge pump disabled)Enabled in Deep Sleep
\ref CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP100 nA0 - VDDA-1.5 V (charge pump disabled)Enabled in Deep Sleep
+* +* \note +* The output range of the opamp is 0.2 V to VDDA - 0.2 V (depending on output load). +* +* \param base +* Pointer to structure describing registers +* +* \param currentMode +* Current mode selection +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CURRENT_MODE +* +*******************************************************************************/ +void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode) +{ + CY_ASSERT_L3(CY_CTB_CURRENTMODE(currentMode)); + + cy_en_sysanalog_deep_sleep_t arefDeepSleep; + + switch(currentMode) + { + case CY_CTB_CURRENT_HIGH_ACTIVE: + + /* Does not disable AREF for Deep Sleep in case the AREF is used by other blocks */ + + /* Use a 1 uA IPTAT level and disable redirection */ + Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL); + Cy_CTB_DisableRedirect(); + + /* Disable Deep Sleep mode for the CTB - not opamp specific */ + Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_DISABLE); + + /* Enable Opamp0 pump */ + base->OA_RES0_CTRL |= CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk; + + /* Enable Opamp1 pump */ + base->OA_RES1_CTRL |= CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk; + + break; + case CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP: + + /* All generators (IPTAT, IZTAT, and VREF) of the AREF block must be enabled for Deep Sleep */ + Cy_SysAnalog_SetDeepSleepMode(CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF); + + /* Use a 1 uA IPTAT level and disable redirection */ + Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_NORMAL); + Cy_CTB_DisableRedirect(); + + /* Enable Deep Sleep mode for the CTB - not opamp specific */ + Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE); + + /* Disable Opamp0 pump */ + base->OA_RES0_CTRL &= ~CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk; + + /* Disable Opamp1 pump */ + base->OA_RES1_CTRL &= ~CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk; + + break; + case CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP: + default: + + /* The AREF IPTAT output for the opamps must be enabled in Deep Sleep. + * This means a minimum Deep Sleep mode setting of CY_SYSANALOG_DEEPSLEEP_IPTAT_2. */ + arefDeepSleep = Cy_SysAnalog_GetDeepSleepMode(); + if ((arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_DISABLE) || (arefDeepSleep == CY_SYSANALOG_DEEPSLEEP_IPTAT_1)) + { + Cy_SysAnalog_SetDeepSleepMode(CY_SYSANALOG_DEEPSLEEP_IPTAT_2); + } + + /* Use a 100 nA IPTAT level and enable redirection */ + Cy_CTB_SetIptatLevel(CY_CTB_IPTAT_LOW); + Cy_CTB_EnableRedirect(); + + /* Enable Deep Sleep mode for the CTB - not opamp specific */ + Cy_CTB_SetDeepSleepMode(base, CY_CTB_DEEPSLEEP_ENABLE); + + /* Disable Opamp0 pump */ + base->OA_RES0_CTRL &= ~CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk; + + /* Disable Opamp1 pump */ + base->OA_RES1_CTRL &= ~CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk; + break; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetDeepSleepMode +****************************************************************************//** +* +* Enable or disable the entire CTB (not per opamp) in Deep Sleep mode. +* +* If enabled, the AREF block must also be enabled for Deep Sleep to provide +* the needed reference currents to the opamps (see \ref Cy_SysAnalog_SetDeepSleepMode). +* Additionally, ensure that only internal CTB switches are used for routing. +* Switches on AMUXBUSA and AMUXBUSB are not enabled in Deep Sleep. +* See the \ref group_ctb_dependencies section for more information. +* +* \note +* In Deep Sleep mode, the charge pumps are disabled so the input +* range of the opamps is reduced to 0 V to VDDA - 1.5 V. +* +* \param base +* Pointer to structure describing registers +* +* \param deepSleep +* \ref CY_CTB_DEEPSLEEP_DISABLE or \ref CY_CTB_DEEPSLEEP_ENABLE from +* \ref cy_en_ctb_deep_sleep_t. +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_DEEPSLEEP_MODE +* +*******************************************************************************/ +void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep) +{ + CY_ASSERT_L3(CY_CTB_DEEPSLEEP(deepSleep)); + + uint32_t ctbCtrl; + + ctbCtrl = base->CTB_CTRL & ~CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk; + + base->CTB_CTRL = ctbCtrl | (uint32_t)deepSleep; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetOutputMode +****************************************************************************//** +* +* Set the opamp output mode to 1x drive, 10x drive, or comparator mode. +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \param mode +* Opamp mode selection. Select a value from \ref cy_en_ctb_mode_t. +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_OUTPUT_MODE +* +*******************************************************************************/ +void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_mode_t mode) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum)); + CY_ASSERT_L3(CY_CTB_OAMODE(mode)); + + uint32_t oaCtrlReg; + + if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + + /* Clear the three affected bits before setting them */ + oaCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk | CTBM_OA_RES0_CTRL_OA0_COMP_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk); + base->OA_RES0_CTRL = oaCtrlReg | (uint32_t) mode | ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_BOOST_DISABLE : CY_CTB_OPAMP_BOOST_ENABLE); + base->OA0_COMP_TRIM = (uint32_t) ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + } + + if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + oaCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk | CTBM_OA_RES1_CTRL_OA1_COMP_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Msk); + base->OA_RES1_CTRL = oaCtrlReg | (uint32_t) mode | ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_BOOST_DISABLE : CY_CTB_OPAMP_BOOST_ENABLE); + base->OA1_COMP_TRIM = (uint32_t) ((mode == CY_CTB_MODE_OPAMP10X) ? CY_CTB_OPAMP_COMPENSATION_CAP_MAX: CY_CTB_OPAMP_COMPENSATION_CAP_MIN); + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetPower +****************************************************************************//** +* +* Configure the power level and charge pump for a specific opamp. +* +* At higher power levels, the opamp consumes more current but provides more +* gain bandwidth. +* Enabling the charge pump increases current but provides +* rail-to-rail input range. Disabling the charge pump limits the input range to +* VDDA - 1.5 V. +* See the device datasheet for performance specifications. +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \param power +* Power mode selection. Select a value from \ref cy_en_ctb_power_t. +* +* \param pump +* Enable or disable the charge pump. Select a value from \ref cy_en_ctb_pump_t. +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_POWER +* +*******************************************************************************/ +void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_power_t power, cy_en_ctb_pump_t pump) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum)); + CY_ASSERT_L3(CY_CTB_OAPOWER(power)); + CY_ASSERT_L3(CY_CTB_OAPUMP(pump)); + + uint32_t oaCtrlReg; + + if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + + /* Clear the two affected bits before setting them */ + oaCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Msk | CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk); + base->OA_RES0_CTRL = oaCtrlReg | (uint32_t) power | (uint32_t) pump; + } + + if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + oaCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Msk | CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk); + base->OA_RES1_CTRL = oaCtrlReg | (uint32_t) power | (uint32_t) pump; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_DACSampleAndHold +****************************************************************************//** +* +* Perform sampling and holding of the CTDAC output. +* To perform a sample or a hold, a preparation step must first be executed to +* open the required switches. Because of this, each sample or hold +* requires three function calls: +* +* -# Call this function to prepare for a sample or hold +* -# Enable or disable the CTDAC output +* -# Call this function again to perform a sample or hold +* +* It takes 10 us to perform a sample of the CTDAC output to provide +* time for the capacitor to settle to the new value. +* +* \param base +* Pointer to structure describing registers +* +* \param mode +* Mode to prepare or perform a sample or hold, or disable the ability +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SAMPLE_CODE_SNIPPET +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_HOLD_CODE_SNIPPET +* +*******************************************************************************/ +void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode) +{ + CY_ASSERT_L3(CY_CTB_SAMPLEHOLD(mode)); + + switch(mode) + { + case CY_CTB_SH_DISABLE: + base->CTD_SW_CLEAR = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Open COB switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK /* Open CIS switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK /* Open ILR switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK; /* Open CHD switch */ + base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK; /* Close COS switch */ + break; + case CY_CTB_SH_PREPARE_SAMPLE: + base->CTD_SW_CLEAR = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Open COB switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK /* Open CIS switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK; /* Open ILR switch */ + base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_CHOLD_CONNECT_MASK; /* Close CHD switch */ + break; + case CY_CTB_SH_SAMPLE: + base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK; /* Close COS switch */ + break; + case CY_CTB_SH_PREPARE_HOLD: + base->CTD_SW_CLEAR = (uint32_t) CY_CTB_SW_CTD_OUT_CHOLD_MASK /* Open COS switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK; /* Open CIS switch */ + break; + case CY_CTB_SH_HOLD: + default: + base->CTD_SW = (uint32_t) CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK /* Close COB switch to reduce leakage through COS switch */ + | (uint32_t) CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK; /* Close ILR switch to reduce leakage through CIS switch */ + break; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpampSetOffset +****************************************************************************//** +* +* Override the CTB opamp offset factory trim. +* The trim is a six bit value and the MSB is a direction bit. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Bit 5Bits 4:0Note
000000Negative trim direction - minimum setting
011111Negative trim direction - maximum setting
100000Positive trim direction - minimum setting
111111Positive trim direction - maximum setting
+* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \param trim +* Trim value from 0 to 63 +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_OFFSET_TRIM +* +*******************************************************************************/ +void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum)); + CY_ASSERT_L2(CY_CTB_TRIM(trim)); + + if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA0_OFFSET_TRIM = (trim << CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos) & CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk; + } + + if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA1_OFFSET_TRIM = (trim << CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos) & CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpampGetOffset +****************************************************************************//** +* +* Return the current CTB opamp offset trim value. +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1 +* +* \return Offset trim value +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_OFFSET_TRIM +* +*******************************************************************************/ +uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(opampNum)); + + uint32_t trimReg; + + if (opampNum == CY_CTB_OPAMP_0) + { + trimReg = base->OA0_OFFSET_TRIM; + } + else + { + trimReg = base->OA1_OFFSET_TRIM; + } + + return trimReg; +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpampSetSlope +****************************************************************************//** +* +* Override the CTB opamp slope factory trim. +* The offset of the opamp will vary across temperature. +* This trim compensates for the slope of the offset across temperature. +* This compensation uses a bias current from the Analaog Reference block. +* To disable it, set the trim to 0. +* +* The trim is a six bit value and the MSB is a direction bit. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Bit 5Bits 4:0Note
000000Negative trim direction - minimum setting
011111Negative trim direction - maximum setting
100000Positive trim direction - minimum setting
111111Positive trim direction - maximum setting
+* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \param trim +* Trim value from 0 to 63 +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_SLOPE_TRIM +* +*******************************************************************************/ +void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(opampNum)); + CY_ASSERT_L2(CY_CTB_TRIM(trim)); + + if ((opampNum == CY_CTB_OPAMP_0) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA0_SLOPE_OFFSET_TRIM = (trim << CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos) & CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk; + } + + if ((opampNum == CY_CTB_OPAMP_1) || (opampNum == CY_CTB_OPAMP_BOTH)) + { + base->OA1_SLOPE_OFFSET_TRIM = (trim << CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos) & CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_OpampGetSlope +****************************************************************************//** +* +* Return the CTB opamp slope trim value. +* +* \param base +* Pointer to structure describing registers +* +* \param opampNum +* \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1 +* +* \return Slope trim value +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_SLOPE_TRIM +* +*******************************************************************************/ +uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(opampNum)); + + uint32_t trimReg; + + if (opampNum == CY_CTB_OPAMP_0) + { + trimReg = base->OA0_SLOPE_OFFSET_TRIM; + } + else + { + trimReg = base->OA1_SLOPE_OFFSET_TRIM; + } + + return trimReg; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetAnalogSwitch +****************************************************************************//** +* +* Provide firmware control of the CTB switches. Each call to this function +* can open a set of switches or close a set of switches in one register. +* +* \param base +* Pointer to structure describing registers +* +* \param switchSelect +* A value of the enum \ref cy_en_ctb_switch_register_sel_t to select the switch +* register +* +* \param switchMask +* The mask of the switches to either open or close. +* The switch masks can be found in the following enums: \ref cy_en_ctb_oa0_switches_t, +* \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t. +* Use the enum that is consistent with the provided register. +* +* \param state +* \ref CY_CTB_SWITCH_OPEN or \ref CY_CTB_SWITCH_CLOSE +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_ANALOG_SWITCH +* +*******************************************************************************/ +void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state) +{ + CY_ASSERT_L3(CY_CTB_SWITCHSELECT(switchSelect)); + CY_ASSERT_L2(CY_CTB_SWITCHMASK(switchSelect, switchMask)); + CY_ASSERT_L3(CY_CTB_SWITCHSTATE(state)); + + __IOM uint32_t *switchReg; + __IOM uint32_t *switchClearReg; + + switch(switchSelect) + { + case CY_CTB_SWITCH_OA0_SW: + switchReg = &base->OA0_SW; + switchClearReg = &base->OA0_SW_CLEAR; + break; + case CY_CTB_SWITCH_OA1_SW: + switchReg = &base->OA1_SW; + switchClearReg = &base->OA1_SW_CLEAR; + break; + case CY_CTB_SWITCH_CTD_SW: + default: + switchReg = &base->CTD_SW; + switchClearReg = &base->CTD_SW_CLEAR; + break; + } + + switch(state) + { + case CY_CTB_SWITCH_CLOSE: + *switchReg = switchMask; + break; + case CY_CTB_SWITCH_OPEN: + default: + *switchClearReg = switchMask; + break; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_GetAnalogSwitch +****************************************************************************//** +* +* Return the open or closed state of the specified analog switch. +* +* \param base +* Pointer to structure describing registers +* +* \param switchSelect +* A value of the enum \ref cy_en_ctb_switch_register_sel_t to select the switch +* register +* +* \return +* The state of the switches in the provided register. +* Compare this value to the switch masks in the following enums: +* \ref cy_en_ctb_oa0_switches_t, \ref cy_en_ctb_oa1_switches_t, and \ref cy_en_ctb_ctd_switches_t. +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_ANALOG_SWITCH +* +*******************************************************************************/ +uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect) +{ + CY_ASSERT_L3(CY_CTB_SWITCHSELECT(switchSelect)); + + uint32_t switchRegValue; + + switch(switchSelect) + { + case CY_CTB_SWITCH_OA0_SW: + switchRegValue = base->OA0_SW; + break; + case CY_CTB_SWITCH_OA1_SW: + switchRegValue = base->OA1_SW; + break; + case CY_CTB_SWITCH_CTD_SW: + default: + switchRegValue = base->CTD_SW; + break; + } + + return switchRegValue; +} + +/******************************************************************************* +* Function Name: Cy_CTB_CompSetConfig +****************************************************************************//** +* +* Configure the CTB comparator for pulse or level output, to bypass clock +* synchronization, and to enable hysteresis. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \param level +* Configure output to produce a pulse or level output signal + +* \param bypass +* Configure output to be clock synchronized or unsynchronized + +* \param hyst +* Enable or disable input hysteresis + +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_SET_CONFIG +* +*******************************************************************************/ +void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_bypass_t bypass, cy_en_ctb_comp_hyst_t hyst) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + CY_ASSERT_L3(CY_CTB_COMPLEVEL(level)); + CY_ASSERT_L3(CY_CTB_COMPBYPASS(bypass)); + CY_ASSERT_L3(CY_CTB_COMPHYST(hyst)); + + uint32_t opampCtrlReg; + + if ((compNum == CY_CTB_OPAMP_0) || (compNum == CY_CTB_OPAMP_BOTH)) + { + opampCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk); + base->OA_RES0_CTRL = opampCtrlReg | (uint32_t) level |(uint32_t) bypass | (uint32_t) hyst; + } + + if ((compNum == CY_CTB_OPAMP_1) || (compNum == CY_CTB_OPAMP_BOTH)) + { + opampCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk); + base->OA_RES1_CTRL = opampCtrlReg | (uint32_t) level |(uint32_t) bypass | (uint32_t) hyst; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_CompGetConfig +****************************************************************************//** +* +* Return the CTB comparator operating configuration as set by \ref Cy_CTB_CompSetConfig. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1 +* +* \return +* The comparator configuration. +* Compare the register value with the masks in \ref cy_en_ctb_comp_level_t, +* \ref cy_en_ctb_comp_bypass_t, and \ref cy_en_ctb_comp_hyst_t. +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_GET_CONFIG +* +*******************************************************************************/ +uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(compNum)); + + uint32_t config; + + if (compNum == CY_CTB_OPAMP_0) + { + config = base->OA_RES0_CTRL & (CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk | CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk); + } + else + { + config = base->OA_RES1_CTRL & (CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk | CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk | CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk); + } + + return config; +} + +/******************************************************************************* +* Function Name: Cy_CTB_CompSetInterruptEdgeType +****************************************************************************//** +* +* Configure the type of edge that will trigger a comparator interrupt. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \param edge +* Edge type that will trigger an interrupt. Select a value from \ref cy_en_ctb_comp_edge_t. +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_SET_INTERRUPT_EDGE_TYPE +* +*******************************************************************************/ +void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + CY_ASSERT_L3(CY_CTB_COMPEDGE(edge)); + + uint32_t opampCtrlReg; + + if ((compNum == CY_CTB_OPAMP_0) || (compNum == CY_CTB_OPAMP_BOTH)) + { + opampCtrlReg = base->OA_RES0_CTRL & ~(CTBM_OA_RES0_CTRL_OA0_COMPINT_Msk); + base->OA_RES0_CTRL = opampCtrlReg | (uint32_t) edge; + } + + if ((compNum == CY_CTB_OPAMP_1) || (compNum == CY_CTB_OPAMP_BOTH)) + { + opampCtrlReg = base->OA_RES1_CTRL & ~(CTBM_OA_RES1_CTRL_OA1_COMPINT_Msk); + base->OA_RES1_CTRL = opampCtrlReg | (uint32_t) edge; + } +} + +/******************************************************************************* +* Function Name: Cy_CTB_CompGetStatus +****************************************************************************//** +* +* Return the comparator output status. +* When the positive input voltage is greater than the negative input voltage, +* the comparator status is high. Otherwise, the status is low. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* \ref CY_CTB_OPAMP_0 or \ref CY_CTB_OPAMP_1. +* \ref CY_CTB_OPAMP_NONE and \ref CY_CTB_OPAMP_BOTH are invalid options. +* +* \return +* The comparator status. +* A value of 0 is returned if compNum is invalid. +* - 0: Status is low +* - 1: Status is high +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_COMP_GET_STATUS +* +*******************************************************************************/ +uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM_0_1(compNum)); + + uint32_t compStatusResult; + + if (CY_CTB_OPAMP_0 == compNum) + { + compStatusResult = (base->COMP_STAT & CTBM_COMP_STAT_OA0_COMP_Msk) >> CTBM_COMP_STAT_OA0_COMP_Pos; + } + else if (CY_CTB_OPAMP_1 == compNum) + { + compStatusResult = (base->COMP_STAT & CTBM_COMP_STAT_OA1_COMP_Msk) >> CTBM_COMP_STAT_OA1_COMP_Pos; + } + else + { + compStatusResult = 0uL; + } + + return compStatusResult; +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.h new file mode 100644 index 0000000000..cceedf093b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.h @@ -0,0 +1,1508 @@ +/***************************************************************************//** +* \file cy_ctb.h +* \version 1.0 +* +* Header file for the CTB driver +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +/** +* \defgroup group_ctb Continuous Time Block (CTB) +* \{ +* This driver provides API functions to configure and use the analog CTB. +* The CTB comprises two identical opamps, a switch routing matrix, +* and a sample and hold (SH) circuit. The high level features are: +* +* - Two highly configurable opamps +* - Each opamp has programmable power and output drive strength +* - Each opamp can be configured as a voltage follower using internal routing +* - Each opamp can be configured as a comparator with optional 10 mV hysteresis +* - Flexible input and output routing +* - Works as a buffer or amplifier for SAR ADC inputs +* - Works as a buffer, amplifier, or sample and hold (SH) for the CTDAC output +* - Can operate in Deep Sleep power mode +* +* Each opamp, marked OA0 and OA1, has one input and three output stages, +* all of which share the common input stage. +* Note that only one output stage can be selected at a time. +* The output stage can operate as a low-drive strength opamp for internal connections (1X), a high-drive strength +* opamp for driving a device pin (10X), or a comparator. +* +* Using the switching matrix, the opamp inputs and outputs +* can be connected to dedicated general-purpose I/Os or other internal analog +* blocks. See the device datasheet for the dedicated CTB port. +* +* \image html ctb_block_diagram.png "CTB Switch Diagram" width=1000px +* \image latex ctb_block_diagram.png +* +* \section group_ctb_init Initialization and Enable +* +* Before enabling the CTB, set up any external components (such as resistors) +* that are needed for the design. To configure the entire hardware block, call \ref Cy_CTB_Init. +* The base address of the CTB hardware can be found in the device specific header file. +* Alternatively, to configure only one opamp without any routing, call \ref Cy_CTB_OpampInit. +* The driver also provides a \ref Cy_CTB_FastInit function for fast and easy initialization of the CTB +* based on commonly used configurations. They are pre-defined in the driver as: +* +* Opamp0 +* - \ref Cy_CTB_Fast_Opamp0_Unused +* - \ref Cy_CTB_Fast_Opamp0_Comp +* - \ref Cy_CTB_Fast_Opamp0_Opamp1x +* - \ref Cy_CTB_Fast_Opamp0_Opamp10x +* - \ref Cy_CTB_Fast_Opamp0_Diffamp +* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out +* - \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH +* +* Opamp1 +* - \ref Cy_CTB_Fast_Opamp1_Unused +* - \ref Cy_CTB_Fast_Opamp1_Comp +* - \ref Cy_CTB_Fast_Opamp1_Opamp1x +* - \ref Cy_CTB_Fast_Opamp1_Opamp10x +* - \ref Cy_CTB_Fast_Opamp1_Diffamp +* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref +* - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 +* +* After initialization, call \ref Cy_CTB_Enable to enable the hardware. +* +* \section group_ctb_io_connections Input/Output Connections +* +* The CTB has internal switches to support flexible input and output routing. If these switches +* have not been configured during initialization, call \ref Cy_CTB_SetAnalogSwitch to +* make the input and output connections. +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_ANALOG_SWITCH +* +* As shown in the CTB switch diagram, the 10x output of OA0 and OA1 have dedicated +* connections to Pin 2 and Pin 3, respectively, of the CTB port. If different output +* connections are required, the other CTB switches and/or AMUXBUX A/B switches can be used. +* +* \section group_ctb_comparator Comparator Mode +* +* Each opamp can be configured as a comparator. Note that when used as a +* comparator, the hardware shuts down the 1X and 10X output drivers. +* Specific to the comparator mode, there is an optional 10 mV input hysteresis +* and configurable edge detection interrupt handling. +* +* - Negative input terminal: This input is usually connected to the reference voltage. +* - Positive input terminal: This input is usually connected to the voltage that is being compared. +* - Comparator digital output: This output goes high when the positive input voltage +* is greater than the negative input voltage. +* +* The comparator output can be routed to a pin or other components using HSIOM or trigger muxes. +* +* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_OUT_ROUTING +* +* \subsection group_ctb_comparator_handling_interrupts Handling interrupts +* +* The comparator output is connected to an edge detector +* block, which is used to detect the edge (rising, falling, both, or disabled) +* for interrupt generation. +* +* The following code snippet demonstrates how to implement a routine to handle the interrupt. +* The routine gets called when any comparator on the device generates an interrupt. +* +* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_ISR +* +* The following code snippet demonstrates how to configure and enable the interrupt. +* +* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_INTR_SETUP +* +* \section group_ctb_opamp_range Opamp Input and Output Range +* +* The input range of the opamp can be rail-to-rail if the charge pump is enabled. +* Without the charge pump, the input range is 0 V to VDDA - 1.5 V. The output range +* of the opamp is typically 0.2 V to VDDA - 0.2 V and will depend on the load. See the +* device datasheet for more detail. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Charge PumpInput Range
Output Range
Enabled0 V to VDDA0.2 V to VDDA - 0.2 V
Disabled0 V to VDDA - 1.5 V0.2 V to VDDA - 0.2 V
+* +* \section group_ctb_sample_hold Sample and Hold Mode +* +* The CTB has a sample and hold (SH) circuit at the non-inverting input of Opamp0. +* The circuit includes a hold capacitor, Chold, with a firmware controlled switch, CHD. +* Sampling and holding the source voltage is performed +* by closing and opening appropriate switches in the CTB using firmware. +* If the SH circuit is used for the CTDAC, the \ref Cy_CTB_DACSampleAndHold function +* should be called. +* +* \image html ctb_fast_config_vdac_sh.png +* \image latex ctb_fast_config_vdac_sh.png +* +* \section group_ctb_dependencies Configuration Dependencies +* +* The CTB relies on other blocks to function properly. The dependencies +* are documented here. +* +* \subsection group_ctb_dependencies_charge_pump Charge Pump Configuration +* +* Each opamp of the CTB has a charge pump that when enabled increases the +* input range to the supply rails. When disabled, the opamp input range is 0 - VDDA - 1.5 V. +* When enabled, the pump requires a clock. +* Call the \ref Cy_CTB_SetClkPumpSource function in the \ref group_sysanalog driver to +* set the clock source for all CTBs. This clock can come from one of two sources: +* +* -# A dedicated clock divider from one of the CLK_PATH in the SRSS +* +* Call the following functions to configure the pump clock from the SRSS: +* - \ref Cy_SysClk_ClkPumpSetSource +* - \ref Cy_SysClk_ClkPumpSetDivider +* - \ref Cy_SysClk_ClkPumpEnable +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_SRSS +* +* -# One of the Peri Clock dividers +* +* Call the following functions to configure a Peri Clock divider as the +* pump clock: +* - \ref Cy_SysClk_PeriphAssignDivider with the IP block set to PCLK_PASS_CLOCK_PUMP_PERI +* - \ref Cy_SysClk_PeriphSetDivider +* - \ref Cy_SysClk_PeriphEnableDivider +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_PERI +* +* When the charge pump is enabled, the clock frequency should be set as follows: +* +* +* +* +* +* +* +* +* +* +* +*
Opamp Power LevelPump Clock Freq
Low or Medium8 - 24 MHz
High24 MHz
+* +* The High power level of the opamp requires a 24 MHz pump clock. +* In Deep Sleep mode, all high frequency clocks are +* disabled and the charge pump will be disabled. +* +* \note +* The same pump clock is used by all opamps on the device. Be aware of this +* when configuring different opamps to different power levels. +* +* \subsection group_ctb_dependencies_reference_current Reference Current Configurations +* +* The CTB uses two reference current generators, IPTAT and IZTAT, from +* the AREF block (see \ref group_sysanalog driver). The IPTAT current is +* used to trim the slope of the opamp offset across temperature. +* The AREF must be initialized and enabled for the CTB to function properly. +* +* If the CTB is configured to operate in Deep Sleep mode, +* the appropriate reference current generators from the AREF block must be enabled in Deep Sleep. +* When waking up from Deep Sleep, +* the AREF block has a wakeup time that must be +* considered. Note that configurations in the AREF block +* are chip wide and affect all CTBs on the device. +* +* The following reference current configurations are supported: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Reference Current LevelSupported ModeInput Range
1 uAActive/Low PowerRail-to-Rail (charge pump enabled)
1 uAActive/Low Power/Deep Sleep0 - VDDA-1.5 V (charge pump disabled)
100 nAActive/Low Power/Deep Sleep0 - VDDA-1.5 V (charge pump disabled)
+* +* The first configuration provides low offset and drift with maximum input range +* while consuming the most current. +* For Deep Sleep operation, use the other two configurations with the charge pump disabled. +* For ultra low power, use the 100 nA current level. +* To configure the opamps to operate in one of these options, call \ref Cy_CTB_SetCurrentMode. +* +* \subsection group_ctb_dependencies_sample_hold Sample and Hold Switch Control +* +* If you are using rev-08 of the CY8CKIT-062, the following eight switches +* in the CTB are enabled by the CTDAC IP block: +* +* - COS, CA0, CHD, CH6, COB, COR, CRS, and CRD +* +* On the rev-08 board, if any of the above switches are used, you must call \ref Cy_CTDAC_Enable +* to enable these switches. +* +* Additionally, on the rev-08 board, if any of the switches are used in Deep Sleep mode, +* the CTDAC must also be configured to operate in Deep Sleep (see \ref Cy_CTDAC_SetDeepSleepMode). +* +* In later revisions of the board, the switches are enabled by the CTB block so +* calls to the CTDAC IP block are not necessary. +* +* \section group_ctb_more_information More Information +* +* Refer to technical reference manual (TRM) and the device datasheet. +* +* \section group_ctb_MISRA MISRA-C Compliance] +* +* This driver does not have any specific deviations. +* +* \section group_ctb_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_ctb_macros Macros +* \defgroup group_ctb_functions Functions +* \{ +* \defgroup group_ctb_functions_init Initialization Functions +* \defgroup group_ctb_functions_basic Basic Configuration Functions +* \defgroup group_ctb_functions_comparator Comparator Functions +* \defgroup group_ctb_functions_sample_hold Sample and Hold Functions +* \defgroup group_ctb_functions_interrupts Interrupt Functions +* \defgroup group_ctb_functions_switches Switch Control Functions +* \defgroup group_ctb_functions_trim Offset and Slope Trim Functions +* \defgroup group_ctb_functions_aref Reference Current Mode Functions +* \} +* \defgroup group_ctb_globals Global Variables +* \defgroup group_ctb_data_structures Data Structures +* \defgroup group_ctb_enums Enumerated Types +*/ + +#if !defined(CY_CTB_H) +#define CY_CTB_H + +#include +#include +#include +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" +#include "sysanalog/cy_sysanalog.h" + +#ifndef CY_IP_MXS40PASS_CTB + #error "The CTB driver is not supported on this device" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_ctb_macros +* \{ +*/ + +/** Driver major version */ +#define CY_CTB_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_CTB_DRV_VERSION_MINOR 0 + +/** CTB driver identifier*/ +#define CY_CTB_ID CY_PDL_DRV_ID(0x0Bu) + +/** \cond INTERNAL */ + +/**< De-init value for most CTB registers */ +#define CY_CTB_DEINIT (0uL) + +/**< De-init value for the opamp0 switch control register */ +#define CY_CTB_DEINIT_OA0_SW (CTBM_OA0_SW_CLEAR_OA0P_A00_Msk \ + | CTBM_OA0_SW_CLEAR_OA0P_A20_Msk \ + | CTBM_OA0_SW_CLEAR_OA0P_A30_Msk \ + | CTBM_OA0_SW_CLEAR_OA0M_A11_Msk \ + | CTBM_OA0_SW_CLEAR_OA0M_A81_Msk \ + | CTBM_OA0_SW_CLEAR_OA0O_D51_Msk \ + | CTBM_OA0_SW_CLEAR_OA0O_D81_Msk) + +/**< De-init value for the opamp1 switch control register */ +#define CY_CTB_DEINIT_OA1_SW (CTBM_OA1_SW_CLEAR_OA1P_A03_Msk \ + | CTBM_OA1_SW_CLEAR_OA1P_A13_Msk \ + | CTBM_OA1_SW_CLEAR_OA1P_A43_Msk \ + | CTBM_OA1_SW_CLEAR_OA1P_A73_Msk \ + | CTBM_OA1_SW_CLEAR_OA1M_A22_Msk \ + | CTBM_OA1_SW_CLEAR_OA1M_A82_Msk \ + | CTBM_OA1_SW_CLEAR_OA1O_D52_Msk \ + | CTBM_OA1_SW_CLEAR_OA1O_D62_Msk \ + | CTBM_OA1_SW_CLEAR_OA1O_D82_Msk) + +/**< De-init value for the CTDAC switch control register */ +#define CY_CTB_DEINIT_CTD_SW (CTBM_CTD_SW_CLEAR_CTDD_CRD_Msk \ + | CTBM_CTD_SW_CLEAR_CTDS_CRS_Msk \ + | CTBM_CTD_SW_CLEAR_CTDS_COR_Msk \ + | CTBM_CTD_SW_CLEAR_CTDO_C6H_Msk \ + | CTBM_CTD_SW_CLEAR_CTDO_COS_Msk \ + | CTBM_CTD_SW_CLEAR_CTDH_COB_Msk \ + | CTBM_CTD_SW_CLEAR_CTDH_CHD_Msk \ + | CTBM_CTD_SW_CLEAR_CTDH_CA0_Msk \ + | CTBM_CTD_SW_CLEAR_CTDH_CIS_Msk \ + | CTBM_CTD_SW_CLEAR_CTDH_ILR_Msk) + +#define CY_CTB_TRIM_VALUE_MAX (63uL) + +/**< Macros for conditions used by CY_ASSERT calls */ + +#define CY_CTB_OPAMPNUM(num) (((num) == CY_CTB_OPAMP_0) || ((num) == CY_CTB_OPAMP_1) || ((num) == CY_CTB_OPAMP_BOTH)) +#define CY_CTB_OPAMPNUM_0_1(num) (((num) == CY_CTB_OPAMP_0) || ((num) == CY_CTB_OPAMP_1)) +#define CY_CTB_OPAMPNUM_ALL(num) (((num) == CY_CTB_OPAMP_NONE) \ + || ((num) == CY_CTB_OPAMP_0) \ + || ((num) == CY_CTB_OPAMP_1) \ + || ((num) == CY_CTB_OPAMP_BOTH)) +#define CY_CTB_IPTAT(iptat) (((iptat) == CY_CTB_IPTAT_NORMAL) || ((iptat) == CY_CTB_IPTAT_LOW)) +#define CY_CTB_CLKPUMP(clkPump) (((clkPump) == CY_CTB_CLK_PUMP_SRSS) || ((clkPump) == CY_CTB_CLK_PUMP_PERI)) +#define CY_CTB_DEEPSLEEP(deepSleep) (((deepSleep) == CY_CTB_DEEPSLEEP_DISABLE) || ((deepSleep) == CY_CTB_DEEPSLEEP_ENABLE)) +#define CY_CTB_OAPOWER(power) ((power) <= CY_CTB_POWER_HIGH) +#define CY_CTB_OAMODE(mode) (((mode) == CY_CTB_MODE_OPAMP1X) \ + || ((mode) == CY_CTB_MODE_OPAMP10X) \ + || ((mode) == CY_CTB_MODE_COMP)) +#define CY_CTB_OAPUMP(pump) (((pump) == CY_CTB_PUMP_DISABLE) || ((pump) == CY_CTB_PUMP_ENABLE)) +#define CY_CTB_COMPEDGE(edge) (((edge) == CY_CTB_COMP_EDGE_DISABLE) \ + || ((edge) == CY_CTB_COMP_EDGE_RISING) \ + || ((edge) == CY_CTB_COMP_EDGE_FALLING) \ + || ((edge) == CY_CTB_COMP_EDGE_BOTH)) +#define CY_CTB_COMPLEVEL(level) (((level) == CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE) || ((level) == CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL)) +#define CY_CTB_COMPBYPASS(bypass) (((bypass) == CY_CTB_COMP_BYPASS_SYNC) || ((bypass) == CY_CTB_COMP_BYPASS_NO_SYNC)) +#define CY_CTB_COMPHYST(hyst) (((hyst) == CY_CTB_COMP_HYST_DISABLE) || ((hyst) == CY_CTB_COMP_HYST_10MV)) +#define CY_CTB_CURRENTMODE(mode) (((mode) == CY_CTB_CURRENT_HIGH_ACTIVE) \ + || ((mode) == CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP) \ + || ((mode) == CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP)) +#define CY_CTB_SAMPLEHOLD(mode) ((mode) <= CY_CTB_SH_HOLD) +#define CY_CTB_TRIM(trim) ((trim) <= CY_CTB_TRIM_VALUE_MAX) +#define CY_CTB_SWITCHSELECT(select) (((select) == CY_CTB_SWITCH_OA0_SW) \ + || ((select) == CY_CTB_SWITCH_OA1_SW) \ + || ((select) == CY_CTB_SWITCH_CTD_SW)) +#define CY_CTB_SWITCHSTATE(state) (((state) == CY_CTB_SWITCH_OPEN) || ((state) == CY_CTB_SWITCH_CLOSE)) +#define CY_CTB_OA0SWITCH(mask) (((mask) & (~CY_CTB_DEINIT_OA0_SW)) == 0uL) +#define CY_CTB_OA1SWITCH(mask) (((mask) & (~CY_CTB_DEINIT_OA1_SW)) == 0uL) +#define CY_CTB_CTDSWITCH(mask) (((mask) & (~CY_CTB_DEINIT_CTD_SW)) == 0uL) +#define CY_CTB_SWITCHMASK(select,mask) (((select) == CY_CTB_SWITCH_OA0_SW) ? (((mask) & (~CY_CTB_DEINIT_OA0_SW)) == 0uL) : \ + (((select) == CY_CTB_SWITCH_OA1_SW) ? (((mask) & (~CY_CTB_DEINIT_OA1_SW)) == 0uL) : \ + (((mask) & (~CY_CTB_DEINIT_CTD_SW)) == 0uL))) +#define CY_CTB_SARSEQCTRL(mask) (((mask) == CY_CTB_SW_SEQ_CTRL_D51_MASK) \ + || ((mask) == CY_CTB_SW_SEQ_CTRL_D52_D62_MASK) \ + || ((mask) == CY_CTB_SW_SEQ_CTRL_D51_D52_D62_MASK)) + +/** \endcond */ + +/** \} group_ctb_macros */ + +/*************************************** +* Enumerated Types +***************************************/ + +/** +* \addtogroup group_ctb_enums +* \{ +*/ + +/** +* Most functions allow you to configure a single opamp or both opamps at once. +* The \ref Cy_CTB_SetInterruptMask function can be called with \ref CY_CTB_OPAMP_NONE +* and interrupts will be disabled. +*/ +typedef enum{ + CY_CTB_OPAMP_NONE = 0, /**< For disabling interrupts for both opamps. Used with \ref Cy_CTB_SetInterruptMask */ + CY_CTB_OPAMP_0 = CTBM_INTR_COMP0_Msk, /**< For configuring Opamp0 */ + CY_CTB_OPAMP_1 = CTBM_INTR_COMP1_Msk, /**< For configuring Opamp1 */ + CY_CTB_OPAMP_BOTH = CTBM_INTR_COMP0_Msk | CTBM_INTR_COMP1_Msk, /**< For configuring both Opamp0 and Opamp1 */ +}cy_en_ctb_opamp_sel_t; + +/** Enable or disable CTB while in Deep Sleep mode. +*/ +typedef enum { + CY_CTB_DEEPSLEEP_DISABLE = 0u, /**< CTB is disabled during Deep Sleep power mode */ + CY_CTB_DEEPSLEEP_ENABLE = CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk, /**< CTB remains enabled during Deep Sleep power mode */ +}cy_en_ctb_deep_sleep_t; + +/** +* Configure the power mode of each opamp. Each power setting +* consumes different levels of current and supports a different +* input range and gain bandwidth. +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Opamp PowerIDDGain bandwidth
OFF0NA
LOW350 uA1 MHz
MEDIUM600 uA3 MHz for 1X, 2.5 MHz for 10x
HIGH1.5 mA8 MHz for 1X, 6 MHz for 10x
+* +*/ +typedef enum { + CY_CTB_POWER_OFF = 0u, /**< Opamp is off */ + CY_CTB_POWER_LOW = 1u, /**< Low power: IDD = 350 uA, GBW = 1 MHz for both 1x and 10x */ + CY_CTB_POWER_MEDIUM = 2u, /**< Medium power: IDD = 600 uA, GBW = 3 MHz for 1x and 2.5 MHz for 10x */ + CY_CTB_POWER_HIGH = 3u, /**< High power: IDD = 1500 uA, GBW = 8 MHz for 1x and 6 MHz for 10x */ +}cy_en_ctb_power_t; + +/** +* The output stage of each opamp can be configured for low-drive strength (1X) to drive internal circuits, +* for high-drive strength (10X) to drive external circuits, or as a comparator. +*/ +typedef enum { + CY_CTB_MODE_OPAMP1X = 0u, /**< Configure opamp for low drive strength for internal connections (1x) */ + CY_CTB_MODE_OPAMP10X = 1u << CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos, /**< Configure opamp high drive strength for driving a device pin (10x) */ + CY_CTB_MODE_COMP = 1u << CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos, /**< Configure opamp as a comparator */ +}cy_en_ctb_mode_t; + +/** +* Each opamp has a charge pump to increase the input range to the rails. +* When the charge pump is enabled, the input range is 0 to VDDA. +* When disabled, the input range is 0 to VDDA - 1.5 V. +* +** +* +* +* +* +* +* +* +* +* +*
Charge PumpInput Range (V)
OFF0 to VDDA-1.5
ON0 to VDDA
+* +* Note that in Deep Sleep mode, the charge pump is disabled so the input +* range is reduced. +*/ +typedef enum{ + CY_CTB_PUMP_DISABLE = 0u, /**< Charge pump is disabled for an input range of 0 to VDDA - 1.5 V */ + CY_CTB_PUMP_ENABLE = CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk, /**< Charge pump is enabled for an input range of 0 to VDDA */ +}cy_en_ctb_pump_t; + +/** +* Configure the type of edge that will trigger a comparator interrupt or +* disable the interrupt entirely. +*/ +typedef enum +{ + CY_CTB_COMP_EDGE_DISABLE = 0u, /**< Disabled, no interrupts generated */ + CY_CTB_COMP_EDGE_RISING = 1u << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Rising edge generates an interrupt */ + CY_CTB_COMP_EDGE_FALLING = 2u << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Falling edge generates an interrupt */ + CY_CTB_COMP_EDGE_BOTH = 3u << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Both edges generate an interrupt */ +}cy_en_ctb_comp_edge_t; + +/** Configure the comparator DSI trigger output level when output is synchronized. */ +typedef enum +{ + CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE = 0u, /**< Send pulse on DSI for each edge of comparator output */ + CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL = CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk, /**< DSI output is synchronized version of comparator output */ +}cy_en_ctb_comp_level_t; + +/** Bypass the comparator output synchronization for DSI trigger. */ +typedef enum +{ + CY_CTB_COMP_BYPASS_SYNC = 0u, /**< Comparator output is synchronized for DSI trigger */ + CY_CTB_COMP_BYPASS_NO_SYNC = CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk, /**< Comparator output is not synchronized for DSI trigger */ +}cy_en_ctb_comp_bypass_t; + +/** Disable or enable the 10 mV hysteresis for the comparator. */ +typedef enum +{ + CY_CTB_COMP_HYST_DISABLE = 0u, /**< Disable hysteresis */ + CY_CTB_COMP_HYST_10MV = CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk, /**< Enable the 10 mV hysteresis */ +}cy_en_ctb_comp_hyst_t; + +/** Switch state, either open or closed, to be used in \ref Cy_CTB_SetAnalogSwitch. */ +typedef enum +{ + CY_CTB_SWITCH_OPEN = 0uL, /**< Open the switch */ + CY_CTB_SWITCH_CLOSE = 1uL /**< Close the switch */ +}cy_en_ctb_switch_state_t; + +/** +* The switch register to be used in \ref Cy_CTB_SetAnalogSwitch. +* The CTB has three registers for configuring the switch routing matrix. +* */ +typedef enum +{ + CY_CTB_SWITCH_OA0_SW = 0u, /**< Switch register for Opamp0 */ + CY_CTB_SWITCH_OA1_SW = 1u, /**< Switch register for Opamp1 */ + CY_CTB_SWITCH_CTD_SW = 2u, /**< Switch register for CTDAC routing */ +}cy_en_ctb_switch_register_sel_t; + +/** +* Switch masks for Opamp0 to be used in \ref Cy_CTB_SetAnalogSwitch. +*/ +typedef enum +{ + CY_CTB_SW_OA0_POS_AMUXBUSA_MASK = CTBM_OA0_SW_OA0P_A00_Msk, /**< Switch A00: Opamp0 non-inverting input to AMUXBUS A */ + CY_CTB_SW_OA0_POS_PIN0_MASK = CTBM_OA0_SW_OA0P_A20_Msk, /**< Switch A20: Opamp0 non-inverting input to Pin 0 of CTB device port */ + CY_CTB_SW_OA0_POS_PIN6_MASK = CTBM_OA0_SW_OA0P_A30_Msk, /**< Switch A30: Opamp0 non-inverting input to Pin 6 of CTB device port */ + CY_CTB_SW_OA0_NEG_PIN1_MASK = CTBM_OA0_SW_OA0M_A11_Msk, /**< Switch A11: Opamp0 inverting input to Pin 1 of CTB device port */ + CY_CTB_SW_OA0_NEG_OUT_MASK = CTBM_OA0_SW_OA0M_A81_Msk, /**< Switch A81: Opamp0 inverting input to Opamp0 output */ + CY_CTB_SW_OA0_OUT_SARBUS0_MASK = CTBM_OA0_SW_OA0O_D51_Msk, /**< Switch D51: Opamp0 output to sarbus0 */ + CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK = CTBM_OA0_SW_OA0O_D81_Msk, /**< Switch D81: Short Opamp0 1x with 10x outputs */ +}cy_en_ctb_oa0_switches_t; + +/** +* Switch masks for Opamp1 to be used in \ref Cy_CTB_SetAnalogSwitch. +*/ +typedef enum +{ + CY_CTB_SW_OA1_POS_AMUXBUSB_MASK = CTBM_OA1_SW_OA1P_A03_Msk, /**< Switch A03: Opamp1 non-inverting input to AMUXBUS B */ + CY_CTB_SW_OA1_POS_PIN5_MASK = CTBM_OA1_SW_OA1P_A13_Msk, /**< Switch A13: Opamp1 non-inverting input to Pin 5 of CTB device port */ + CY_CTB_SW_OA1_POS_PIN7_MASK = CTBM_OA1_SW_OA1P_A43_Msk, /**< Switch A43: Opamp1 non-inverting input to Pin 7 of CTB device port */ + CY_CTB_SW_OA1_POS_AREF_MASK = CTBM_OA1_SW_OA1P_A73_Msk, /**< Switch A73: Opamp1 non-inverting input to device Analog Reference (AREF) */ + CY_CTB_SW_OA1_NEG_PIN4_MASK = CTBM_OA1_SW_OA1M_A22_Msk, /**< Switch A22: Opamp1 inverting input to Pin 4 of CTB device port */ + CY_CTB_SW_OA1_NEG_OUT_MASK = CTBM_OA1_SW_OA1M_A82_Msk, /**< switch A82: Opamp1 inverting input to Opamp1 output */ + CY_CTB_SW_OA1_OUT_SARBUS0_MASK = CTBM_OA1_SW_OA1O_D52_Msk, /**< Switch D52: Opamp1 output to sarbus0 */ + CY_CTB_SW_OA1_OUT_SARBUS1_MASK = CTBM_OA1_SW_OA1O_D62_Msk, /**< Switch D62: Opamp1 output to sarbus1 */ + CY_CTB_SW_OA1_OUT_SHORT_1X_10X_MASK = CTBM_OA1_SW_OA1O_D82_Msk, /**< Switch D82: Short Opamp1 1x with 10x outputs */ +}cy_en_ctb_oa1_switches_t; + +/** +* Switch masks for CTDAC to CTB routing to be used in \ref Cy_CTB_SetAnalogSwitch. +*/ +typedef enum +{ + CY_CTB_SW_CTD_REF_OA1_OUT_MASK = CTBM_CTD_SW_CTDD_CRD_Msk, /**< Switch CRD: Opamp1 output to CTDAC reference. */ + CY_CTB_SW_CTD_REFSENSE_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_CRS_Msk, /**< Switch CRS: CTDAC reference sense to Opamp1 inverting input. */ + CY_CTB_SW_CTD_OUT_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_COR_Msk, /**< Switch COR: CTDAC output to Opamp1 inverting input. */ + CY_CTB_SW_CTD_OUT_PIN6_MASK = CTBM_CTD_SW_CTDO_C6H_Msk, /**< Switch C6H: CTDAC output to P6 of CTB device port. */ + CY_CTB_SW_CTD_OUT_CHOLD_MASK = CTBM_CTD_SW_CTDO_COS_Msk, /**< Switch COS: CTDAC output to hold cap (deglitch capable). */ + CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK = CTBM_CTD_SW_CTDH_COB_Msk, /**< Switch COB: Drive CTDAC output with opamp0 1x output during hold mode. */ + CY_CTB_SW_CTD_CHOLD_CONNECT_MASK = CTBM_CTD_SW_CTDH_CHD_Msk, /**< Switch CHD: Hold cap connection. */ + CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK = CTBM_CTD_SW_CTDH_CA0_Msk, /**< Switch CA0: Hold cap to Opamp0 non-inverting input. */ + CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK = CTBM_CTD_SW_CTDH_CIS_Msk, /**< Switch CIS: Opamp0 non-inverting input isolation (for hold cap) */ + CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK = CTBM_CTD_SW_CTDH_ILR_Msk, /**< Switch ILR: Hold cap leakage reduction (drives far side of isolation switch CIS) */ +}cy_en_ctb_ctd_switches_t; + + +/** +* Masks for CTB switches that can be controlled by the SAR sequencer. +* These masks are used in \ref Cy_CTB_EnableSarSeqCtrl and \ref Cy_CTB_DisableSarSeqCtrl. +* +* The SAR ADC subsystem supports analog routes through three CTB switches on SARBUS0 and SARBUS1. +* This control allows for pins on the CTB dedicated port to route to the SAR ADC input channels: +* +* - D51: Connects the inverting terminal of OA0 to SARBUS0 +* - D52: Connects the inverting terminal of OA1 to SARBUS0 +* - D62: Connects the inverting terminal of OA1 to SARBUS1 +*/ +typedef enum +{ + CY_CTB_SW_SEQ_CTRL_D51_MASK = CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk, /**< Enable SAR sequencer control of the D51 switch */ + CY_CTB_SW_SEQ_CTRL_D52_D62_MASK = CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk, /**< Enable SAR sequencer control of the D52 and D62 switches */ + CY_CTB_SW_SEQ_CTRL_D51_D52_D62_MASK = CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk | CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk, /**< Enable SAR sequency control of all three switches */ +}cy_en_ctb_switch_sar_seq_t; + +/** +* Each opamp also has a programmable compensation capacitor block, +* that optimizes the stability of the opamp performance based on output load. +* The compensation cap will be set by the driver based on the opamp drive strength (1x or 10x) selection. +*/ +typedef enum +{ + CY_CTB_OPAMP_COMPENSATION_CAP_OFF = 0u, /**< No compensation */ + CY_CTB_OPAMP_COMPENSATION_CAP_MIN = 1u, /**< Minimum compensation - for 1x drive*/ + CY_CTB_OPAMP_COMPENSATION_CAP_MED = 2u, /**< Medium compensation */ + CY_CTB_OPAMP_COMPENSATION_CAP_MAX = 3u, /**< Maximum compensation - for 10x drive */ +}cy_en_ctb_compensation_cap_t; + +/** Enable or disable the gain booster. +* The gain booster will be set by the driver based on the opamp drive strength (1x or 10x) selection. +*/ +typedef enum +{ + CY_CTB_OPAMP_BOOST_DISABLE = 0u, /**< Disable gain booster - for 10x drive */ + CY_CTB_OPAMP_BOOST_ENABLE = CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk, /**< Enable gain booster - for 1x drive */ +}cy_en_ctb_boost_en_t; + +/** Sample and hold modes for firmware sampling of the CTDAC output. +* +* To perform a sample or a hold, a preparation step must first be executed to +* open the required switches. +* +* -# Call \ref Cy_CTB_DACSampleAndHold with \ref CY_CTB_SH_PREPARE_SAMPLE or \ref CY_CTB_SH_PREPARE_HOLD +* -# Enable or disable CTDAC output +* -# Call \ref Cy_CTB_DACSampleAndHold with \ref CY_CTB_SH_SAMPLE or \ref CY_CTB_SH_HOLD +*/ +typedef enum +{ + CY_CTB_SH_DISABLE = 0u, /**< The hold capacitor is not connected - this disables sample and hold */ + CY_CTB_SH_PREPARE_SAMPLE = 1u, /**< Prepares the required switches for a following sample */ + CY_CTB_SH_SAMPLE = 2u, /**< Performs a sample of the voltage */ + CY_CTB_SH_PREPARE_HOLD = 3u, /**< Prepares the required switches for a following hold */ + CY_CTB_SH_HOLD = 4u, /**< Performs a hold of the previously sampled voltage */ +}cy_en_ctb_sample_hold_mode_t; + +/** AREF IPTAT bias current output for the CTB +* +* The CTB bias current can be 1 uA (normal) or 100 nA (low current). +*/ +typedef enum +{ + CY_CTB_IPTAT_NORMAL = 0u, /**< 1 uA bias current to the CTB */ + CY_CTB_IPTAT_LOW = 1u << PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Pos, /**< 100 nA bias current to the CTB */ +}cy_en_ctb_iptat_t; + +/** CTB charge pump clock sources +* +* The CTB pump clock can come from: +* - a dedicated divider clock in the SRSS +* - one of the CLK_PERI dividers +*/ +typedef enum +{ + CY_CTB_CLK_PUMP_SRSS = 0u, /**< Use the dedicated pump clock from SRSSp */ + CY_CTB_CLK_PUMP_PERI = 1u << PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos, /**< Use one of the CLK_PERI dividers */ +}cy_en_ctb_clk_pump_source_t; + +/** High level opamp current modes */ +typedef enum +{ + CY_CTB_CURRENT_HIGH_ACTIVE = 0u, /**< Uses 1 uA reference current with charge pump enabled. Available in Active and Low Power */ + CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP = 1u, /**< Uses 1 uA reference current with charge pump disabled. Available in all power modes */ + CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP = 2u, /**< Uses 100 nA reference current with charge pump disabled. Available in all power modes */ +}cy_en_ctb_current_mode_t; + +/** Return states for \ref Cy_CTB_Init, \ref Cy_CTB_OpampInit, \ref Cy_CTB_DeInit, and \ref Cy_CTB_FastInit */ +typedef enum { + CY_CTB_SUCCESS = 0x00uL, /**< Initialization completed successfully */ + CY_CTB_BAD_PARAM = CY_CTB_ID | CY_PDL_STATUS_ERROR | 0x01uL, /**< Input pointers were NULL and initialization could not be completed */ +}cy_en_ctb_status_t; + +/** \} group_ctb_enums */ + +/*************************************** +* Configuration Structures +***************************************/ + +/** +* \addtogroup group_ctb_data_structures +* \{ +*/ + +/** +* Configuration structure to set up the entire CTB to be used with \ref Cy_CTB_Init. +*/ +typedef struct { + cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTB during Deep Sleep */ + + /* Opamp0 configuration */ + cy_en_ctb_power_t oa0Power; /**< Opamp0 power mode: off, low, medium, or high */ + cy_en_ctb_mode_t oa0Mode; /**< Opamp0 usage mode: 1x drive, 10x drive, or as a comparator */ + cy_en_ctb_pump_t oa0Pump; /**< Opamp0 charge pump: enable to increase input range for rail-to-rail operation */ + cy_en_ctb_comp_edge_t oa0CompEdge; /**< Opamp0 comparator edge detection: disable, rising, falling, or both */ + cy_en_ctb_comp_level_t oa0CompLevel; /**< Opamp0 comparator DSI (trigger) output: pulse or level */ + cy_en_ctb_comp_bypass_t oa0CompBypass; /**< Opamp0 comparator DSI (trigger) output synchronization */ + cy_en_ctb_comp_hyst_t oa0CompHyst; /**< Opamp0 comparator hysteresis: enable for 10 mV hysteresis */ + bool oa0CompIntrEn; /**< Opamp0 comparator interrupt enable */ + + /* Opamp1 configuration */ + cy_en_ctb_power_t oa1Power; /**< Opamp1 power mode: off, low, medium, or high */ + cy_en_ctb_mode_t oa1Mode; /**< Opamp1 usage mode: 1x drive, 10x drive, or as a comparator */ + cy_en_ctb_pump_t oa1Pump; /**< Opamp1 charge pump: enable to increase input range for rail-to-rail operation */ + cy_en_ctb_comp_edge_t oa1CompEdge; /**< Opamp1 comparator edge detection: disable, rising, falling, or both */ + cy_en_ctb_comp_level_t oa1CompLevel; /**< Opamp1 comparator DSI (trigger) output: pulse or level */ + cy_en_ctb_comp_bypass_t oa1CompBypass; /**< Opamp1 comparator DSI (trigger) output synchronization */ + cy_en_ctb_comp_hyst_t oa1CompHyst; /**< Opamp1 comparator hysteresis: enable for 10 mV hysteresis */ + bool oa1CompIntrEn; /**< Opamp1 comparator interrupt enable */ + + /* Switch analog routing configuration */ + bool configRouting; /**< Configure or ignore routing related registers */ + uint32_t oa0SwitchCtrl; /**< Opamp0 routing control */ + uint32_t oa1SwitchCtrl; /**< Opamp1 routing control */ + uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */ +}cy_stc_ctb_config_t; + +/** +* This configuration structure is used to initialize only one opamp of the CTB +* without impacting analog routing. This structure is used with \ref Cy_CTB_OpampInit. +*/ +typedef struct { + cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTB during Deep Sleep */ + + /* Opamp configuration */ + cy_en_ctb_power_t oaPower; /**< Opamp power mode: off, low, medium, or high */ + cy_en_ctb_mode_t oaMode; /**< Opamp usage mode: 1x drive, 10x drive, or as a comparator */ + cy_en_ctb_pump_t oaPump; /**< Opamp charge pump: enable to increase input range for rail-to-rail operation */ + cy_en_ctb_comp_edge_t oaCompEdge; /**< Opamp comparator edge detection: disable, rising, falling, or both */ + cy_en_ctb_comp_level_t oaCompLevel; /**< Opamp comparator DSI (trigger) output: pulse or level */ + cy_en_ctb_comp_bypass_t oaCompBypass; /**< Opamp comparator DSI (trigger) output synchronization */ + cy_en_ctb_comp_hyst_t oaCompHyst; /**< Opamp comparator hysteresis: enable for 10 mV hysteresis */ + bool oaCompIntrEn; /**< Opamp comparator interrupt enable */ +}cy_stc_ctb_opamp_config_t; + +/** This configuration structure is used to quickly initialize Opamp0 for the most commonly used configurations. +* +* Other configuration options are set to: +* - .oa0Pump = \ref CY_CTB_PUMP_ENABLE +* - .oa0CompEdge = \ref CY_CTB_COMP_EDGE_BOTH +* - .oa0CompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL +* - .oa0CompBypass = \ref CY_CTB_COMP_BYPASS_SYNC +* - .oa0CompHyst = \ref CY_CTB_COMP_HYST_10MV +* - .oa0CompIntrEn = true +*/ +typedef struct +{ + cy_en_ctb_power_t oa0Power; /**< Opamp0 power mode: off, low, medium, or high */ + cy_en_ctb_mode_t oa0Mode; /**< Opamp0 usage mode: 1x drive, 10x drive, or as a comparator */ + uint32_t oa0SwitchCtrl; /**< Opamp0 routing control */ + uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */ +}cy_stc_ctb_fast_config_oa0_t; + +/** This configuration structure is used to quickly initialize Opamp1 for the most commonly used configurations. +* +* Other configuration options are set to: +* - .oa1Pump = \ref CY_CTB_PUMP_ENABLE +* - .oa1CompEdge = \ref CY_CTB_COMP_EDGE_BOTH +* - .oa1CompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL +* - .oa1CompBypass = \ref CY_CTB_COMP_BYPASS_SYNC +* - .oa1CompHyst = \ref CY_CTB_COMP_HYST_10MV +* - .oa1CompIntrEn = true +*/ +typedef struct +{ + cy_en_ctb_power_t oa1Power; /**< Opamp1 power mode: off, low, medium, or high */ + cy_en_ctb_mode_t oa1Mode; /**< Opamp1 usage mode: 1x drive, 10x drive, or as a comparator */ + uint32_t oa1SwitchCtrl; /**< Opamp1 routing control */ + uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */ +}cy_stc_ctb_fast_config_oa1_t; + +/** \} group_ctb_data_structures */ + + +/** \addtogroup group_ctb_globals +* \{ +*/ +/*************************************** +* Global Variables +***************************************/ + +/** Configure Opamp0 as unused - powered down. See \ref Cy_CTB_FastInit. */ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Unused; + +/** Configure Opamp0 as a comparator. No routing is configured. +* +* \image html ctb_fast_config_comp.png +* \image latex ctb_fast_config_comp.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp; + +/** Configure Opamp0 as an opamp with 1x drive. No routing is configured. +* +* \image html ctb_fast_config_opamp1x.png +* \image latex ctb_fast_config_opamp1x.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x; + +/** Configure Opamp0 as an opamp with 10x drive. No routing is configured. +* +* \image html ctb_fast_config_opamp10x.png +* \image latex ctb_fast_config_opamp10x.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp10x; + +/** Configure Opamp0 as one stage of a differential amplifier. +* The opamp is in 10x drive and the switches shown are closed. +* +* \image html ctb_fast_config_oa0_diffamp.png +* \image latex ctb_fast_config_oa0_diffamp.png width=100px +* +* See the device datasheet for the dedicated CTB port. +* +* To be used with \ref Cy_CTB_FastInit and \ref Cy_CTB_Fast_Opamp1_Diffamp. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Diffamp; + +/** Configure Opamp0 as a buffer for the CTDAC output. +* The buffer is in 10x drive and the switches shown are closed. +* Configure the CTDAC for output buffer mode by calling \ref Cy_CTDAC_FastInit +* with \ref Cy_CTDAC_Fast_VddaRef_BufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut. +* +* \image html ctb_fast_config_vdac_output.png +* \image latex ctb_fast_config_vdac_output.png +* +* See the device datasheet for the dedicated CTB port. +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out; + +/** Configure Opamp0 as a buffer for the CTDAC output with the sample and hold capacitor connected. +* The buffer is in 10x drive and the switches shown are closed. +* Configure the CTDAC for output buffer mode by calling \ref Cy_CTDAC_FastInit +* with \ref Cy_CTDAC_Fast_VddaRef_BufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut. + +* \image html ctb_fast_config_vdac_sh.png +* \image latex ctb_fast_config_vdac_sh.png +* +* See the device datasheet for the dedicated CTB port. +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out_SH; + +/** Configure Opamp1 as unused - powered down. See \ref Cy_CTB_FastInit.*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Unused; + +/** Configure Opamp1 as a comparator. No routing is configured. +* +* \image html ctb_fast_config_comp.png +* \image latex ctb_fast_config_comp.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Comp; + +/** Configure Opamp1 as an opamp with 1x drive. No routing is configured. +* +* \image html ctb_fast_config_opamp1x.png +* \image latex ctb_fast_config_opamp1x.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp1x; + +/** Configure Opamp1 as an opamp with 10x drive. No routing is configured. +* +* \image html ctb_fast_config_opamp10x.png +* \image latex ctb_fast_config_opamp10x.png width=100px +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp10x; + +/** Configure Opamp1 as one stage of a differential amplifier. +* The opamp is in 10x drive and the switches shown are closed. +* +* \image html ctb_fast_config_oa1_diffamp.png +* \image latex ctb_fast_config_oa1_diffamp.png width=100px +* +* See the device datasheet for the dedicated CTB port. +* +* To be used with \ref Cy_CTB_FastInit and \ref Cy_CTB_Fast_Opamp0_Diffamp. +* +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Diffamp; + +/** Configure Opamp1 as a buffer for the CTDAC reference. The reference comes from the +* internal analog reference block (AREF). +* The buffer is in 1x drive and the switches shown are closed. +* Configure the CTDAC to use the buffered reference by calling \ref Cy_CTDAC_FastInit +* with \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut. +* +* \image html ctb_fast_config_vdac_aref.png +* \image latex ctb_fast_config_vdac_aref.png +* +* See \ref Cy_CTB_FastInit. +* +* Note the AREF block needs to be configured using a separate driver. +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref; + +/** Configure Opamp1 as a buffer for the CTDAC reference. The reference comes from Pin 5. +* The buffer is in 1x drive and the switches shown are closed. +* Configure the CTDAC to use the buffered reference by calling \ref Cy_CTDAC_FastInit +* with \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut. +* +* \image html ctb_fast_config_vdac_pin5.png +* \image latex ctb_fast_config_vdac_pin5.png +* +* See the device datasheet for the dedicated CTB port. +* +* See \ref Cy_CTB_FastInit. +*/ +extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5; + +/** \} group_ctb_globals */ + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_ctb_functions +* \{ +*/ + +/** +* \addtogroup group_ctb_functions_init +* This set of functions are for initializing, enabling, and disabling the CTB. +* \{ +*/ +cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config); +cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, const cy_stc_ctb_opamp_config_t *config); +cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting); +cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config_oa0_t *config0, const cy_stc_ctb_fast_config_oa1_t *config1); +__STATIC_INLINE void Cy_CTB_Enable(CTBM_Type *base); +__STATIC_INLINE void Cy_CTB_Disable(CTBM_Type *base); +/** \} */ + +/** +* \addtogroup group_ctb_functions_basic +* This set of functions are for configuring basic usage of the CTB. +* \{ +*/ +void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep); +void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_mode_t mode); +void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_power_t power, cy_en_ctb_pump_t pump); +/** \} */ + +/** +* \addtogroup group_ctb_functions_sample_hold +* This function enables sample and hold of the CTDAC output. +* \{ +*/ +void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode); +/** \} */ + +/** +* \addtogroup group_ctb_functions_comparator +* This set of functions are specific to the comparator mode +* \{ +*/ +void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_bypass_t bypass, cy_en_ctb_comp_hyst_t hyst); +uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge); +uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +/** \} */ + +/** +* \addtogroup group_ctb_functions_trim +* These are advanced functions for trimming the offset and slope of the opamps. +* Most users do not need to call these functions and can use the factory trimmed values. +* \{ +*/ +void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim); +uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum); +void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim); +uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum); +/** \} */ + +/** +* \addtogroup group_ctb_functions_switches +* This set of functions is for controlling routing switches. +* \{ +*/ +void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state); +uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect); +__STATIC_INLINE void Cy_CTB_OpenAllSwitches(CTBM_Type *base); +__STATIC_INLINE void Cy_CTB_EnableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask); +__STATIC_INLINE void Cy_CTB_DisableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask); +/** \} */ + +/** +* \addtogroup group_ctb_functions_interrupts +* This set of functions is related to the comparator interrupts. +* \{ +*/ +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +__STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +__STATIC_INLINE void Cy_CTB_SetInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +__STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum); +/** \} */ + +/** +* \addtogroup group_ctb_functions_aref +* This set of functions impacts all opamps on the chip. +* Notice how some of these functions do not take a base address input. +* When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device, +* it should be called for all other CTB instances as well. This is because +* there is only one IPTAT level (1 uA or 100 nA) chip wide. +* \{ +*/ +void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode); +__STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat); +__STATIC_INLINE void Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump); +__STATIC_INLINE void Cy_CTB_EnableRedirect(void); +__STATIC_INLINE void Cy_CTB_DisableRedirect(void); +/** \} */ + +/** +* \addtogroup group_ctb_functions_init +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_CTB_Enable +****************************************************************************//** +* +* Power up the CTB hardware block. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_Enable(CTBM_Type *base) +{ + base->CTB_CTRL |= CTBM_CTB_CTRL_ENABLED_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTB_Disable +****************************************************************************//** +* +* Power down the CTB hardware block. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_Disable(CTBM_Type *base) +{ + base->CTB_CTRL &= (~CTBM_CTB_CTRL_ENABLED_Msk); +} + +/** \} */ + +/** +* \addtogroup group_ctb_functions_switches +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_CTB_OpenAllSwitches +****************************************************************************//** +* +* Open all the switches and disable all hardware (SAR Sequencer and DSI) control of the switches. +* Primarily used as a quick method of re-configuring all analog connections +* that are sparsely closed. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_OPEN_ALL_SWITCHES +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_OpenAllSwitches(CTBM_Type *base) +{ + base->OA0_SW_CLEAR = CY_CTB_DEINIT_OA0_SW; + base->OA1_SW_CLEAR = CY_CTB_DEINIT_OA1_SW; + base->CTD_SW_CLEAR = CY_CTB_DEINIT_CTD_SW; + base->CTB_SW_DS_CTRL = CY_CTB_DEINIT; + base->CTB_SW_SQ_CTRL = CY_CTB_DEINIT; +} + +/******************************************************************************* +* Function Name: Cy_CTB_EnableSarSeqCtrl +****************************************************************************//** +* +* Enable SAR sequencer control of specified switch(es). +* +* This allows the SAR ADC to use routes through the CTB when configuring its channels. +* +* There are three switches in the CTB that can be enabled by the SAR sequencer. +* - D51: This switch connects the negative input of Opamp0 to the SARBUS0 +* - D52: This switch connects the positive input of Opamp1 to the SARBUS0 +* - D62: This switch connects the positive input of Opamp1 to the SARBUS1 +* +* \param base +* Pointer to structure describing registers +* +* \param switchMask +* The switch or switches in which to enable SAR sequencer control. +* Use an enumerated value from \ref cy_en_ctb_switch_sar_seq_t. +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_ENABLE_SAR_SEQ_CTRL +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_EnableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask) +{ + CY_ASSERT_L3(CY_CTB_SARSEQCTRL(switchMask)); + + base->CTB_SW_SQ_CTRL |= (uint32_t) switchMask; +} + +/******************************************************************************* +* Function Name: Cy_CTB_DisableSarSeqCtrl +****************************************************************************//** +* +* Disable SAR sequencer control of specified switch(es). +* +* \param base +* Pointer to structure describing registers +* +* \param switchMask +* The switch or switches in which to disable SAR sequencer control. +* Use an enumerated value from \ref cy_en_ctb_switch_sar_seq_t. +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_DISABLE_SAR_SEQ_CTRL +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_DisableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask) +{ + CY_ASSERT_L3(CY_CTB_SARSEQCTRL(switchMask)); + + base->CTB_SW_SQ_CTRL &= ~((uint32_t) switchMask); +} +/** \} */ + +/** +* \addtogroup group_ctb_functions_interrupts +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_CTB_GetInterruptStatus +****************************************************************************//** +* +* Return the status of the interrupt when the configured comparator +* edge is detected. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \return +* The interrupt status. +* If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned status +* to \ref cy_en_ctb_opamp_sel_t to determine which comparator edge (or both) +* was detected. +* - 0: Edge was not detected +* - Non-zero: Configured edge type was detected +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm0p.c SNIPPET_COMP_GETINTERRUPTSTATUS +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + + return base->INTR & (uint32_t) compNum; +} + +/******************************************************************************* +* Function Name: Cy_CTB_ClearInterrupt +****************************************************************************//** +* +* Clear the CTB comparator triggered interrupt. +* The interrupt must be cleared with this function so that the hardware +* can set subsequent interrupts and those interrupts can be forwarded +* to the interrupt controller, if enabled. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + + base->INTR = (uint32_t) compNum; + + /* Dummy read for buffered writes. */ + (void) base->INTR; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetInterrupt +****************************************************************************//** +* +* Force the CTB interrupt to trigger using software. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_SetInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + + base->INTR_SET = (uint32_t) compNum; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetInterruptMask +****************************************************************************//** +* +* Configure the CTB comparator edge interrupt to be forwarded to the +* CPU interrupt controller. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* \ref CY_CTB_OPAMP_NONE, \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH. +* Calling this function with CY_CTB_OPAMP_NONE will disable all interrupt requests. +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_INTERRUPT_MASK +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM_ALL(compNum)); + + base->INTR_MASK = (uint32_t) compNum; +} + +/******************************************************************************* +* Function Name: Cy_CTB_GetInterruptMask +****************************************************************************//** +* +* Return whether the CTB comparator edge interrupt output is +* forwarded to the CPU interrupt controller as configured by +* \ref Cy_CTB_SetInterruptMask. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \return +* The interrupt mask. +* If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned mask +* to \ref cy_en_ctb_opamp_sel_t to determine which comparator interrupt +* output (or both) is forwarded. +* - 0: Interrupt output not forwarded to interrupt controller +* - Non-zero: Interrupt output forwarded to interrupt controller +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_GET_INTERRUPT_MASK +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + + return base->INTR_MASK & (uint32_t) compNum; +} + +/******************************************************************************* +* Function Name: Cy_CTB_GetInterruptStatusMasked +****************************************************************************//** +* +* Return the CTB comparator edge output interrupt state after being masked. +* This is the bitwise AND of \ref Cy_CTB_GetInterruptStatus and \ref Cy_CTB_GetInterruptMask. +* +* \param base +* Pointer to structure describing registers +* +* \param compNum +* \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH +* +* \return +* If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned value +* to \ref cy_en_ctb_opamp_sel_t to determine which comparator interrupt +* output (or both) is detected and masked. +* - 0: Configured edge not detected or not masked +* - Non-zero: Configured edge type detected and masked +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum) +{ + CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); + + return base->INTR_MASKED & (uint32_t) compNum; +} +/** \} */ + +/** +* \addtogroup group_ctb_functions_aref +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_CTB_SetIptatLevel +****************************************************************************//** +* +* Set the IPTAT reference level to 1 uA or 100 nA. The IPTAT generator is used by the CTB +* for slope offset drift. +* +* \param iptat +* Value from enum \ref cy_en_ctb_iptat_t +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_IPTAT_LEVEL +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat) +{ + CY_ASSERT_L3(CY_CTB_IPTAT(iptat)); + + PASS_AREF->AREF_CTRL = (PASS_AREF->AREF_CTRL & ~PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Msk) | (uint32_t) iptat; +} + +/******************************************************************************* +* Function Name: Cy_CTB_SetClkPumpSource +****************************************************************************//** +* +* Set the clock source for both charge pumps in the CTB. Recall that each opamp +* has its own charge pump. The clock can come from: +* +* - A dedicated divider off of one of the CLK_PATH in the SRSS. +* Call the following functions to configure the pump clock from the SRSS: +* - \ref Cy_SysClk_ClkPumpSetSource +* - \ref Cy_SysClk_ClkPumpSetDivider +* - \ref Cy_SysClk_ClkPumpEnable +* - One of the Peri Clock dividers. +* Call the following functions to configure a Peri Clock divider as the +* pump clock: +* - \ref Cy_SysClk_PeriphAssignDivider with the IP block set to PCLK_PASS_CLOCK_PUMP_PERI +* - \ref Cy_SysClk_PeriphSetDivider +* - \ref Cy_SysClk_PeriphEnableDivider +* +* \param clkPump +* Clock source selection (SRSS or PeriClk) for the pump. Select a value from +* \ref cy_en_ctb_clk_pump_source_t +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_SRSS +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_PERI +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump) +{ + CY_ASSERT_L3(CY_CTB_CLKPUMP(clkPump)); + + PASS_AREF->AREF_CTRL = (PASS_AREF->AREF_CTRL & ~PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk) | (uint32_t) clkPump; +} + +/******************************************************************************* +* Function Name: Cy_CTB_EnableRedirect +****************************************************************************//** +* +* Normally, the AREF IZTAT is routed to the CTB IZTAT and the AREF IPTAT +* is routed to the CTB IPTAT: +* +* - CTB.IZTAT = AREF.IZTAT +* - CTB.IPTAT = AREF.IPTAT +* +* However, the AREF IPTAT can be redirected to the CTB IZTAT and the CTB IPTAT +* is off. +* +* - CTB.IZTAT = AREF.IPTAT +* - CTB.IPTAT = HiZ +* +* The redirection applies to all opamps on the device and +* should be used when the IPTAT bias level is set to 100 nA +* (see \ref Cy_CTB_SetIptatLevel). +* +* When the CTB.IPTAT is HiZ, the CTB cannot compensate for the slope of +* the offset across temperature. +* +* \return None +* +* \funcusage +* +* \snippet ctb_sut_01.cydsn/main_cm4.c CTB_SNIPPET_ENABLE_REDIRECT +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_EnableRedirect(void) +{ + PASS_AREF->AREF_CTRL |= PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTB_DisableRedirect +****************************************************************************//** +* +* Disable the redirection of the AREF IPTAT to the CTB IZTAT for all opamps +* on the device as enabled by \ref Cy_CTB_EnableRedirect. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTB_DisableRedirect(void) +{ + PASS_AREF->AREF_CTRL &= ~(PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk); +} + +/** \} */ + +/** \} group_ctb_functions */ + +#if defined(__cplusplus) +} +#endif + +#endif /** !defined(CY_CTB_H) */ + +/** \} group_ctb */ + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.c new file mode 100644 index 0000000000..7ec4d5838d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.c @@ -0,0 +1,721 @@ +/***************************************************************************//** +* \file cy_ctdac.c +* \version 1.0.1 +* +* Provides the public functions for the API for the CTDAC driver. +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "ctdac/cy_ctdac.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** Static function to configure the clock */ +static void Cy_CTDAC_ConfigureClock(cy_en_ctdac_update_t updateMode, cy_en_divider_types_t dividerType, + uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue); + +const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_UnbufferedOut = +{ + /*.refSource */ CY_CTDAC_REFSOURCE_VDDA, + /*.outputBuffer */ CY_CTDAC_OUTPUT_UNBUFFERED, +}; + +const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_BufferedOut = +{ + /*.refSource */ CY_CTDAC_REFSOURCE_VDDA, + /*.outputBuffer */ CY_CTDAC_OUTPUT_BUFFERED, +}; + +const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_UnbufferedOut = +{ + /*.refSource */ CY_CTDAC_REFSOURCE_EXTERNAL, + /*.outputBuffer */ CY_CTDAC_OUTPUT_UNBUFFERED, +}; + +const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_BufferedOut = +{ + /*.refSource */ CY_CTDAC_REFSOURCE_EXTERNAL, + /*.outputBuffer */ CY_CTDAC_OUTPUT_BUFFERED, +}; + +/******************************************************************************* +* Function Name: Cy_CTDAC_Init +****************************************************************************//** +* +* Initialize all CTDAC configuration registers +* +* \param base +* Pointer to structure describing registers +* +* \param config +* Pointer to structure containing configuration data +* +* \return +* Status of initialization, \ref CY_CTDAC_SUCCESS or \ref CY_CTDAC_BAD_PARAM +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_INIT_CUSTOM +* +*******************************************************************************/ +cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config) +{ + CY_ASSERT_L1(NULL != base); + CY_ASSERT_L1(NULL != config); + + cy_en_ctdac_status_t result; + uint32_t ctdacCtrl = CY_CTDAC_DEINIT; + uint32_t setSwitch = CY_CTDAC_DEINIT; + uint32_t clearSwitch = CY_CTDAC_DEINIT; + + if ((NULL == base) || (NULL == config)) + { + result = CY_CTDAC_BAD_PARAM; + } + else + { + + CY_ASSERT_L3(CY_CTDAC_REFSOURCE(config->refSource)); + CY_ASSERT_L3(CY_CTDAC_FORMAT(config->formatMode)); + CY_ASSERT_L3(CY_CTDAC_UPDATE(config->updateMode)); + CY_ASSERT_L3(CY_CTDAC_DEGLITCH(config->deglitchMode)); + CY_ASSERT_L3(CY_CTDAC_OUTPUTMODE(config->outputMode)); + CY_ASSERT_L3(CY_CTDAC_OUTPUTBUFFER(config->outputBuffer)); + CY_ASSERT_L3(CY_CTDAC_DEEPSLEEP(config->deepSleep)); + CY_ASSERT_L2(CY_CTDAC_DEGLITCHCYCLES(config->deglitchCycles)); + + /* Handle the deglitch counts */ + ctdacCtrl |= (config->deglitchCycles << CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos) & CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk; + + /* Handle the deglitch mode */ + ctdacCtrl |= (uint32_t)config->deglitchMode; + + /* Handle the update mode */ + if ((config->updateMode == CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE) \ + || (config->updateMode == CY_CTDAC_UPDATE_STROBE_EDGE_SYNC) \ + || (config->updateMode == CY_CTDAC_UPDATE_STROBE_LEVEL)) + { + ctdacCtrl |= CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Msk; + } + + if (config->updateMode == CY_CTDAC_UPDATE_STROBE_LEVEL) + { + ctdacCtrl |= CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Msk; + } + + /* Handle the sign format */ + ctdacCtrl |= (uint32_t)config->formatMode; + + /* Handle the Deep Sleep mode */ + ctdacCtrl |= (uint32_t)config->deepSleep; + + /* Handle the output mode */ + ctdacCtrl |= (uint32_t)config->outputMode; + + /* Handle the reference source */ + switch(config->refSource) + { + case CY_CTDAC_REFSOURCE_VDDA: + + /* Close the CVD switch to use Vdda as the reference source */ + setSwitch |= CTDAC_CTDAC_SW_CTDD_CVD_Msk; + break; + case CY_CTDAC_REFSOURCE_EXTERNAL: + default: + clearSwitch |= CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk; + break; + } + + /* Handle the output buffer switch CO6 */ + switch(config->outputBuffer) + { + case CY_CTDAC_OUTPUT_UNBUFFERED: + + /* Close the CO6 switch to send output to a direct pin unbuffered */ + setSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk; + break; + case CY_CTDAC_OUTPUT_BUFFERED: + default: + clearSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk; + break; + } + + base->INTR_MASK = (uint32_t)config->enableInterrupt << CTDAC_INTR_VDAC_EMPTY_Pos; + base->CTDAC_SW = setSwitch; + base->CTDAC_SW_CLEAR = clearSwitch; + base->CTDAC_VAL = (((uint32_t)config->value) << CTDAC_CTDAC_VAL_VALUE_Pos) & CTDAC_CTDAC_VAL_VALUE_Msk; + base->CTDAC_VAL_NXT = (((uint32_t)config->nextValue) << CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk; + + if (config->configClock) + { + Cy_CTDAC_ConfigureClock(config->updateMode, config->dividerType, config->dividerNum, config->dividerIntValue, config->dividerFracValue); + } + + base->CTDAC_CTRL = ctdacCtrl; + result = CY_CTDAC_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_DeInit +****************************************************************************//** +* +* Reset CTDAC registers back to power on reset defaults. +* +* \note +* Does not disable the clock. +* +* \param base +* Pointer to structure describing registers +* +* \param deInitRouting +* If true, all switches are reset to their default state. +* If false, switch registers are untouched. +* +* \return +* Status of initialization, \ref CY_CTDAC_SUCCESS, or \ref CY_CTDAC_BAD_PARAM +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_DEINIT +* +*******************************************************************************/ +cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting) +{ + CY_ASSERT_L1(NULL != base); + + cy_en_ctdac_status_t result; + + if (NULL == base) + { + result = CY_CTDAC_BAD_PARAM; + } + else + { + base->CTDAC_CTRL = CY_CTDAC_DEINIT; + base->INTR_MASK = CY_CTDAC_DEINIT; + base->CTDAC_VAL = CY_CTDAC_DEINIT; + base->CTDAC_VAL_NXT = CY_CTDAC_DEINIT; + + if (deInitRouting) + { + base->CTDAC_SW_CLEAR = CY_CTDAC_DEINIT; + } + + result = CY_CTDAC_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_FastInit +****************************************************************************//** +* +* Initialize the CTDAC to one of the common use modes. +* This function provides a quick and easy method of configuring the CTDAC when using +* the PDL driver for device configuration. +* +* The other configuration options are set to: +* - .formatMode = \ref CY_CTDAC_FORMAT_UNSIGNED +* - .updateMode = \ref CY_CTDAC_UPDATE_BUFFERED_WRITE +* - .deglitchMode = \ref CY_CTDAC_DEGLITCHMODE_NONE +* - .outputMode = \ref CY_CTDAC_OUTPUT_VALUE +* - .deepSleep = \ref CY_CTDAC_DEEPSLEEP_DISABLE +* - .deglitchCycles = \ref CY_CTDAC_DEINIT +* - .value = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE +* - .nextValue = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE +* - .enableInterrupt = true +* - .configClock = true +* - .dividerType = \ref CY_CTDAC_FAST_CLKCFG_TYPE +* - .dividerNum = \ref CY_CTDAC_FAST_CLKCFG_NUM +* - .dividerInitValue = \ref CY_CTDAC_FAST_CLKCFG_DIV +* - .dividerFracValue = \ref CY_CTDAC_DEINIT +* +* A separate call to \ref Cy_CTDAC_Enable is needed to turn on the hardware. +* +* \param base +* Pointer to structure describing registers +* +* \param config +* Pointer to structure containing configuration data for quick initialization. +* Define your own or use one of the provided structures: +* - \ref Cy_CTDAC_Fast_VddaRef_UnbufferedOut +* - \ref Cy_CTDAC_Fast_VddaRef_BufferedOut +* - \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut +* - \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut +* +* \return +* Status of initialization, \ref CY_CTDAC_SUCCESS or \ref CY_CTDAC_BAD_PARAM +* +* \funcusage +* +* The following code snippets configures VDDA as the reference source and +* routes the output directly to Pin 6 (unbuffered). +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_FAST_INIT +* +* \funcusage +* +* The following code snippet shows how the CTDAC and CTB blocks can +* quickly be configured to work together. The code +* configures the CTDAC to use a buffered output, +* a buffered reference source from the internal bandgap voltage, and closes +* all required analog routing switches. +* +* \image html ctdac_fast_init_funcusage.png +* \image latex ctdac_fast_init_funcusage.png +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_FAST_INIT_CTB +* +*******************************************************************************/ +cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast_config_t *config) +{ + CY_ASSERT_L1(NULL != base); + CY_ASSERT_L1(NULL != config); + + cy_en_ctdac_status_t result; + uint32_t ctdacCtrl; + uint32_t setSwitch = CY_CTDAC_DEINIT; + uint32_t clearSwitch = CY_CTDAC_DEINIT; + + if ((NULL == base) || (NULL == config)) + { + result = CY_CTDAC_BAD_PARAM; + } + else + { + CY_ASSERT_L3(CY_CTDAC_REFSOURCE(config->refSource)); + CY_ASSERT_L3(CY_CTDAC_OUTPUTBUFFER(config->outputBuffer)); + + ctdacCtrl = (uint32_t) CY_CTDAC_DEGLITCHMODE_NONE \ + | (uint32_t) CY_CTDAC_UPDATE_BUFFERED_WRITE \ + | (uint32_t) CY_CTDAC_FORMAT_UNSIGNED \ + | (uint32_t) CY_CTDAC_DEEPSLEEP_DISABLE \ + | (uint32_t) CY_CTDAC_OUTPUT_VALUE; + + /* Handle the reference source */ + switch(config->refSource) + { + case CY_CTDAC_REFSOURCE_VDDA: + + /* Close the CVD switch to use Vdda as the reference source */ + setSwitch |= CTDAC_CTDAC_SW_CTDD_CVD_Msk; + break; + case CY_CTDAC_REFSOURCE_EXTERNAL: + default: + clearSwitch |= CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk; + break; + } + + /* Handle the output buffer switch CO6 */ + switch(config->outputBuffer) + { + case CY_CTDAC_OUTPUT_UNBUFFERED: + + /* Close the CO6 switch to send output to a direct pin unbuffered */ + setSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk; + break; + case CY_CTDAC_OUTPUT_BUFFERED: + default: + clearSwitch |= CTDAC_CTDAC_SW_CTDO_CO6_Msk; + break; + } + + base->INTR_MASK = CTDAC_INTR_VDAC_EMPTY_Msk; + base->CTDAC_SW = setSwitch; + base->CTDAC_SW_CLEAR = clearSwitch; + base->CTDAC_VAL = CY_CTDAC_UNSIGNED_MID_CODE_VALUE; + base->CTDAC_VAL_NXT = CY_CTDAC_UNSIGNED_MID_CODE_VALUE; + + /* For fast configuration, the DAC clock is the Peri clock divided by 100. */ + Cy_CTDAC_ConfigureClock(CY_CTDAC_UPDATE_BUFFERED_WRITE, CY_CTDAC_FAST_CLKCFG_TYPE, CY_CTDAC_FAST_CLKCFG_NUM, CY_CTDAC_FAST_CLKCFG_DIV, CY_CTDAC_DEINIT); + + base->CTDAC_CTRL = ctdacCtrl; + result = CY_CTDAC_SUCCESS; + } + + return result; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_ConfigureClock +****************************************************************************//** +* +* Private function for configuring the CTDAC clock based on the desired +* update mode. This function is called by \ref Cy_CTDAC_Init. +* +* \param updateMode +* Update mode value. See \ref cy_en_ctdac_update_t for values. +* +* \return None +* +*******************************************************************************/ +static void Cy_CTDAC_ConfigureClock(cy_en_ctdac_update_t updateMode, cy_en_divider_types_t dividerType, + uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue) +{ + if (updateMode == CY_CTDAC_UPDATE_DIRECT_WRITE) + { /* In direct mode, there is not a clock */ + } + else if(updateMode == CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE) + { + + /* In this mode, the Peri Clock is divided by 1 to give a constant logic high on the CTDAC clock. */ + (void)Cy_SysClk_PeriphDisableDivider(dividerType, dividerNum); + + (void)Cy_SysClk_PeriphAssignDivider(PCLK_PASS_CLOCK_CTDAC, dividerType, dividerNum); + + if ((dividerType == CY_SYSCLK_DIV_8_BIT) || (dividerType == CY_SYSCLK_DIV_16_BIT)) + { + (void)Cy_SysClk_PeriphSetDivider(dividerType, dividerNum, CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV); + } + else + { + (void)Cy_SysClk_PeriphSetFracDivider(dividerType, dividerNum, CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV, CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV_FRAC); + } + + (void)Cy_SysClk_PeriphEnableDivider(dividerType, dividerNum); + } + else + { + + /* All other modes, require a CTDAC clock configured to the desired user frequency */ + (void)Cy_SysClk_PeriphDisableDivider(dividerType, dividerNum); + + (void)Cy_SysClk_PeriphAssignDivider(PCLK_PASS_CLOCK_CTDAC, dividerType, dividerNum); + + if ((dividerType == CY_SYSCLK_DIV_8_BIT) || (dividerType == CY_SYSCLK_DIV_16_BIT)) + { + (void)Cy_SysClk_PeriphSetDivider(dividerType, dividerNum, dividerIntValue); + } + else + { + (void)Cy_SysClk_PeriphSetFracDivider(dividerType, dividerNum, dividerIntValue, dividerFracValue); + } + (void)Cy_SysClk_PeriphEnableDivider(dividerType, dividerNum); + } + +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetSignMode +****************************************************************************//** +* +* Set whether to interpret the DAC value as signed or unsigned. +* In unsigned mode, the DAC value register is used without any decoding. +* In signed mode, the MSB is inverted by adding 0x800 to the DAC value. +* This converts the lowest signed number, 0x800, to the lowest unsigned +* number, 0x000. +* +* \param base +* Pointer to structure describing registers +* +* \param formatMode +* Mode can be signed or unsigned. See \ref cy_en_ctdac_format_t for values. +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_SIGN_MODE +* +*******************************************************************************/ +void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode) +{ + CY_ASSERT_L3(CY_CTDAC_FORMAT(formatMode)); + + uint32_t ctdacCtrl; + + /* Clear the CTDAC_MODE bits */ + ctdacCtrl = base->CTDAC_CTRL & ~CTDAC_CTDAC_CTRL_CTDAC_MODE_Msk; + + base->CTDAC_CTRL = ctdacCtrl | (uint32_t)formatMode; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetDeepSleepMode +****************************************************************************//** +* +* Enable or disable the DAC hardware operation in Deep Sleep mode. +* +* \param base +* Pointer to structure describing registers +* +* \param deepSleep +* Enable or disable Deep Sleep operation. Select value from \ref cy_en_ctdac_deep_sleep_t. +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_DEEPSLEEP_MODE +* +*******************************************************************************/ +void Cy_CTDAC_SetDeepSleepMode(CTDAC_Type *base, cy_en_ctdac_deep_sleep_t deepSleep) +{ + CY_ASSERT_L3(CY_CTDAC_DEEPSLEEP(deepSleep)); + + uint32_t ctdacCtrl; + + ctdacCtrl = base->CTDAC_CTRL & ~CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk; + + base->CTDAC_CTRL = ctdacCtrl | (uint32_t)deepSleep; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetOutputMode +****************************************************************************//** +* +* Set the output mode of the CTDAC: +* - \ref CY_CTDAC_OUTPUT_HIGHZ : Disable the output +* - \ref CY_CTDAC_OUTPUT_VALUE : Enable the output and drive the value +* stored in the CTDAC_VAL register. +* - \ref CY_CTDAC_OUTPUT_VALUE_PLUS1 : Enable the output and drive the +* value stored in the CTDAC_VAL register plus 1. +* - \ref CY_CTDAC_OUTPUT_VSSA : Output pulled to VSSA through 1.1 MOhm (typ) resistor. +* - \ref CY_CTDAC_OUTPUT_VREF : Output pulled to VREF through 1.1 MOhm (typ) resistor. +* +* \param base +* Pointer to structure describing registers +* +* \param outputMode +* Select a value from \ref cy_en_ctdac_output_mode_t. +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_OUTPUT_MODE +* +*******************************************************************************/ +void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMode) +{ + CY_ASSERT_L3(CY_CTDAC_OUTPUTMODE(outputMode)); + + uint32_t ctdacCtrl; + + /* Clear out the three affected bits */ + ctdacCtrl = base->CTDAC_CTRL & ~(CTDAC_CTDAC_CTRL_OUT_EN_Msk | CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk | CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk); + + base->CTDAC_CTRL = ctdacCtrl | (uint32_t)outputMode; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetDeglitchMode +****************************************************************************//** +* +* Enable deglitching on the unbuffered path, buffered path, both, or +* disable deglitching. The deglitch mode should match the configured output path. +* +* \param base +* Pointer to structure describing registers +* +* \param deglitchMode +* Deglitching mode selection. See \ref cy_en_ctdac_deglitch_t for values. +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_DEGLITCH_MODE +* +*******************************************************************************/ +void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchMode) +{ + CY_ASSERT_L3(CY_CTDAC_DEGLITCH(deglitchMode)); + + uint32_t ctdacCtrl; + + /* Clear out DEGLITCH_CO6 and DEGLITCH_C0S bits */ + ctdacCtrl = base->CTDAC_CTRL & ~(CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk | CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk); + + base->CTDAC_CTRL = ctdacCtrl | (uint32_t)deglitchMode; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetDeglitchCycles +****************************************************************************//** +* +* Set the number of deglitch cycles (0 to 63) that will be used. +* To calculate the deglitch time: +* +* (DEGLITCH_CNT + 1) / PERI_CLOCK_FREQ +* +* The optimal deglitch time is 700 ns. +* +* \param base +* Pointer to structure describing registers +* +* \param deglitchCycles +* Number of cycles to deglitch +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_DEGLITCH_CYCLES +* +*******************************************************************************/ +void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles) +{ + CY_ASSERT_L2(CY_CTDAC_DEGLITCHCYCLES(deglitchCycles)); + + uint32_t ctdacCtrl; + + ctdacCtrl = (base->CTDAC_CTRL) & ~CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk; + + base->CTDAC_CTRL = ctdacCtrl | ((deglitchCycles << CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos) & CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk); +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetRef +****************************************************************************//** +* +* Set the CTDAC reference source to Vdda or an external reference. +* The external reference must come from Opamp1 of the CTB. +* +* \param base +* Pointer to structure describing registers +* +* \param refSource +* The reference source. Select a value from \ref cy_en_ctdac_ref_source_t. +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_REF +* +*******************************************************************************/ +void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource) +{ + CY_ASSERT_L3(CY_CTDAC_REFSOURCE(refSource)); + + switch(refSource) + { + case CY_CTDAC_REFSOURCE_VDDA: + + /* Close the CVD switch to use Vdda as the reference source */ + base->CTDAC_SW |= CTDAC_CTDAC_SW_CTDD_CVD_Msk; + break; + case CY_CTDAC_REFSOURCE_EXTERNAL: + default: + base->CTDAC_SW_CLEAR = CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk; + break; + } +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetAnalogSwitch +****************************************************************************//** +* +* Provide firmware control of the CTDAC switches. Each call to this function +* can open a set of switches or close a set of switches. +* +* \note +* The switches are configured by the reference +* source and output mode selections during initialization. +* +* \param base +* Pointer to structure describing registers +* +* \param switchMask +* The mask of the switches to either open or close. +* Select one or more values from \ref cy_en_ctdac_switches_t and "OR" them together. +* +* \param state +* Open or close the switche(s). Select a value from \ref cy_en_ctdac_switch_state_t. +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_ANALOG_SWITCH +* +*******************************************************************************/ +void Cy_CTDAC_SetAnalogSwitch(CTDAC_Type *base, uint32_t switchMask, cy_en_ctdac_switch_state_t state) +{ + CY_ASSERT_L2(CY_CTDAC_SWITCHMASK(switchMask)); + CY_ASSERT_L3(CY_CTDAC_SWITCHSTATE(state)); + + switch(state) + { + case CY_CTDAC_SWITCH_CLOSE: + base->CTDAC_SW |= switchMask; + break; + case CY_CTDAC_SWITCH_OPEN: + default: + + /* Unlike the close case, do not OR the register. Set 1 to clear.*/ + base->CTDAC_SW_CLEAR = switchMask; + break; + } +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_DeepSleepCallback +****************************************************************************//** +* +* Callback to prepare the CTDAC before entering and after exiting Deep Sleep +* mode. If deglitching is used, it is disabled before entering Deep Sleep +* to ensure the deglitch switches are closed. This is needed only +* if the CTDAC will be enabled in DeepSleep. Upon wakeup, deglitching will +* be re-enabled if it was previously used. +* +* \param callbackParams +* Pointer to structure of type \ref cy_stc_syspm_callback_params_t +* +* \return +* See \ref cy_en_syspm_status_t +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_DEEP_SLEEP_CALLBACK +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams) +{ + /* Static variable preserved between function calls. + * Tracks the state of the deglitch mode before sleep so that it can be re-enabled after wakeup */ + static uint32_t deglitchModeBeforeSleep; + + cy_en_syspm_status_t returnValue = CY_SYSPM_SUCCESS; + + CTDAC_Type *ctdacBase = (CTDAC_Type *)callbackParams->base; + + if (CY_SYSPM_BEFORE_TRANSITION == callbackParams->mode) + { /* Actions that should be done before entering the Deep Sleep mode */ + + /* Store the state of the deglitch switches before turning deglitch off */ + deglitchModeBeforeSleep = ctdacBase->CTDAC_CTRL & (CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk | CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk); + + /* Turn deglitch off before entering Deep Sleep */ + ctdacBase->CTDAC_CTRL &= ~(CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk | CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk); + } + else if (CY_SYSPM_AFTER_TRANSITION == callbackParams->mode) + { /* Actions that should be done after exiting the Deep Sleep mode */ + + /* Re-enable the deglitch mode that was configured before Deep Sleep entry */ + ctdacBase->CTDAC_CTRL |= deglitchModeBeforeSleep; + } + else + { /* Does nothing in other modes */ + } + + return returnValue; +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.h new file mode 100644 index 0000000000..ddfb6b9922 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.h @@ -0,0 +1,1045 @@ +/***************************************************************************//** +* \file cy_ctdac.h +* \version 1.0.1 +* +* Header file for the CTDAC driver +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +/** +* \defgroup group_ctdac Continuous Time Digital to Analog Converter (CTDAC) +* \{ +* The CTDAC driver provides APIs to configure the 12-bit Continuous-Time DAC. +* +* - 12-bit continuous time output +* - 2 us settling time for a 25 pF load when output buffered through Opamp0 of \ref group_ctb "CTB" +* - Can be enabled in Deep Sleep power mode +* - Selectable voltage reference: +* - VDDA +* - Internal analog reference buffered through Opamp1 of \ref group_ctb "CTB" +* - External reference buffered through Opamp1 of \ref group_ctb "CTB" +* - Selectable output paths: +* - Direct DAC output to a pin +* - Buffered DAC output through Opamp0 of \ref group_ctb "CTB" +* - Sample and hold output path through Opamp0 of \ref group_ctb "CTB" +* - Selectable input modes: +* - Unsigned 12-bit mode +* - Virtual signed 12-bit mode +* - Configurable update rate using clock or strobe signal +* - Double buffered DAC voltage control register +* - Interrupt and DMA trigger on DAC buffer empty +* - Configurable as PGA along with Opamp1 of the \ref group_ctb "CTB" +* +* The CTDAC generates a 12-bit DAC output voltage from the reference. +* The DAC reference can come from VDDA or from any signal buffered through Opamp0 +* of the CTB. This can be an external signal through a GPIO or from the internal +* AREF. The CTDAC is closely integrated with the CTB block, +* which provides easy buffering of the DAC output voltage, +* buffered input reference voltage, and sample and hold for the DAC output. +* The CTDAC control interface provides control of the DAC output through CPU or DMA. +* This includes a double-buffered DAC voltage control register, clock input for programmable +* update rate, interrupt on DAC buffer empty, and trigger to DMA. +* +* \image html ctdac_block_diagram.png +* \image latex ctdac_block_diagram.png +* +* The CTDAC has two switches, CO6 for configuring the output path and +* CVD for the reference source. +* +* \image html ctdac_switches.png +* \image latex ctdac_switches.png +* +* \section group_ctdac_init Initialization +* +* Configure the CTDAC hardware block by calling \ref Cy_CTDAC_Init. +* The base address of the CTDAC hardware can be found in the device-specific header file. +* If the buffers in the CTB are used for the reference source or the output, +* initialize the CTB hardware block. After both blocks are initialized, +* enable the CTB block before enabling the CTDAC block. +* +* The driver also provides a \ref Cy_CTDAC_FastInit function for fast and easy initialization of the CTDAC. +* The driver has pre-defined configuration structures for the four combinations of the reference and output buffers. +* +* - \ref Cy_CTDAC_Fast_VddaRef_UnbufferedOut +* - \ref Cy_CTDAC_Fast_VddaRef_BufferedOut +* - \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut +* - \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut +* +* After initialization, call \ref Cy_CTDAC_Enable to enable the hardware. +* +* \section group_ctdac_updatemode Update Modes +* The CTDAC contains two registers: +* -# CTDAC_VAL +* +* For direct firmware writes to update the current DAC value immediately. +* This register is written with \ref Cy_CTDAC_SetValue. +* -# CTDAC_VAL_NXT +* +* For buffered writes to update the DAC value at a +* periodic rate or with a strobe trigger input. +* This register is written with \ref Cy_CTDAC_SetValueBuffered. +* +* The update mode is +* selected during initialization with the \ref cy_stc_ctdac_config_t.updateMode. +* Four of these modes require a dedicated clock resource and the driver +* can configure the clock during initialization (see \ref cy_stc_ctdac_config_t). +* +* Three of these modes use a strobe signal through the digital signal interface (DSI). +* This allows control of the buffered update timing from an external source, for example, by another +* chip peripheral or from an off-chip source. +* +* \subsection group_ctdac_updatemode_direct_write Direct write +* +* In this mode, the user writes directly into the CTDAC_VAL register +* using \ref Cy_CTDAC_SetValue. The action of writing to this register +* will update the DAC output. This mode does not generate an interrupt +* or trigger signal. +* In this mode, a clock must not be configured. Additionally, calling \ref +* Cy_CTDAC_SetValueBuffered does not update the DAC output. +* +* \image html ctdac_update_mode_direct_write.png +* \image latex ctdac_update_mode_direct_write.png +* +* \subsection group_ctdac_updatemode_buffered_write Buffered write +* +* In this mode, the user writes to the CTDAC_VAL_NXT register using +* \ref Cy_CTDAC_SetValueBuffered. The rising edge of the clock +* will update the DAC output and generate the interrupt and trigger signals. +* +* Whenever data is transferred from the CTDAC_VAL_NXT register, +* an interrupt is asserted the same time as the trigger. But while +* the trigger is automatically cleared after two PeriClk cycles, the +* user must clear the interrupt with \ref Cy_CTDAC_ClearInterrupt. +* +* \image html ctdac_update_mode_buffered_write.png +* \image latex ctdac_update_mode_buffered_write.png +* +* \subsection group_ctdac_updatemode_strobe_edge_sync Strobe edge sync +* +* In this mode, the user writes to the CTDAC_VAL_NXT register using +* \ref Cy_CTDAC_SetValueBuffered. +* Each rising edge of the DSI strobe input enables +* one subsequent update from the next rising edge of the clock. The DSI +* input must remain high for two PeriClk cycles and go low for +* another two PeriClk cycles to allow for the next update. +* This restricts the DSI strobe input frequency to the PeriClk frequency divided by four. +* +* \image html ctdac_update_mode_strobe_edge_sync.png +* \image latex ctdac_update_mode_strobe_edge_sync.png +* +* \subsection group_ctdac_updatemode_strobe_edge_immediate Strobe edge immediate +* +* In this mode, the user writes to the CTDAC_VAL_NXT register using +* \ref Cy_CTDAC_SetValueBuffered. +* The clock resource is used but set to a logic high. +* Therefore, each rising edge of the DSI strobe input immediately +* updates the DAC output. +* +* \image html ctdac_update_mode_strobe_edge_immediate.png +* \image latex ctdac_update_mode_strobe_edge_immediate.png +* +* \subsection group_ctdac_updatemode_strobe_level Strobe level +* +* In this mode, the user writes to the CTDAC_VAL_NXT register using +* \ref Cy_CTDAC_SetValueBuffered. +* The DSI strobe input acts as a hardware enable signal. +* While the DSI strobe input is high, the mode behaves +* like the Buffered write mode. When the DSI strobe input is low, +* updates are disabled. +* +* \image html ctdac_update_mode_strobe_level.png +* \image latex ctdac_update_mode_strobe_level.png +* +* \section group_ctdac_dacmode DAC Modes +* +* The format of code stored in the CTDAC_VAL register can either be unsigned +* or signed two's complemented. +* Only the first 12 bits of the register are used by the DAC so there is +* no need for sign extension. With the signed format, the DAC decodes +* the code in the register by adding 0x800. +* The DAC can output the register value or the register value plus 1 (see \ref Cy_CTDAC_SetOutputMode). +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
12-bit unsigned code12-bit two's complement signed codeVout (for \ref CY_CTDAC_OUTPUT_VALUE )Vout (for \ref CY_CTDAC_OUTPUT_VALUE_PLUS1 )
0x0000x8000Vref/4096
0x8000x0000.5 * VrefVref * 2049 / 4096
0xFFF0x7FFVref * 4095 / 4096Vref
+* +* The expressions in the above table are based on an unbuffered DAC output. +* When the output is buffered, the input and output range of the buffer will affect the +* output voltage. See \ref group_ctb_opamp_range in the CTB driver for more information. +* +* \section group_ctdac_trigger Interrupts and Trigger +* +* When data from the CTDAC_VAL_NXT is transferred to the CTDAC_VAL register, +* an interrupt and trigger output are generated. The trigger output can be +* used with a DMA block to update the CTDAC value register at high speeds without any CPU intervention. +* Alternatively, the interrupt output can be used when DMA is not available +* to update the CTDAC value register, but at a slower speed. +* +* Recall with the \ref group_ctdac_updatemode, the interrupt and trigger output are available in all modes except +* \ref group_ctdac_updatemode_direct_write. +* +* \subsection group_ctdac_dma_trigger DMA Trigger +* +* The CTDAC trigger output signal can be routed to a DMA block using the \ref group_trigmux +* to trigger an update to the CTDAC_VAL_NXT register. +* When making the required \ref Cy_TrigMux_Connect calls, use the pre-defined enums, TRIG14_IN_PASS_TR_CTDAC_EMPTY +* and TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY. +* +* \subsection group_ctdac_handling_interrupts Handling Interrupts +* +* The following code snippet demonstrates how to implement a routine to handle the interrupt. +* The routine gets called when any CTDAC on the device generates an interrupt. +* +* \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_ISR +* +* The following code snippet demonstrates how to configure and enable the interrupt. +* +* \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_INTR_SETUP +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_DMA_TRIGGER +* +* \section group_ctdac_deglitch Deglitch +* +* The hardware has the ability to deglitch the output value every time it is updated. +* This prevents small glitches in the DAC output during an update to propagate to +* the pin or opamp input. When deglitch is enabled, a switch on the output path +* is forced open for a configurable number of PeriClk cycles. This deglitch time +* is calculated as: +* +* (DEGLITCH_CNT + 1) / PERI_CLOCK_FREQ +* +* The optimal and recommended deglitch time is 700 ns. Call \ref Cy_CTDAC_SetDeglitchCycles to set DEGLITCH_CNT. +* +* There are two switches used for deglitching. +* - Switch COS in the CTB between the DAC output and the Opamp0 input +* - Switch CO6 in the CTDAC between the DAC output and external pin +* +* Call \ref Cy_CTDAC_SetDeglitchMode to set the deglitch path. Match this with the output buffer selection. +* If the output is buffered through the CTB, select \ref CY_CTDAC_DEGLITCHMODE_BUFFERED. +* If the output is unbuffered to a direct pin, select \ref CY_CTDAC_DEGLITCHMODE_UNBUFFERED. +* +* \note +* If deglitching is enabled, the hardware does not force the deglitch switches into a closed +* state during Deep Sleep mode. Therefore, there is a chance that the device enters +* Deep Sleep mode while the hardware is deglitching and the switches on the output path remain open. +* To ensure the DAC will operate properly in Deep Sleep when enabled, make sure to +* register the \ref Cy_CTDAC_DeepSleepCallback before entering Deep Sleep mode. +* +* \section group_ctdac_sample_hold Sample and Hold +* +* When buffering the DAC output, the CTB has a Sample and Hold (SH) feature that can be used for saving power. +* The DAC output voltage is retained on an internal capacitor for a duration of time while the +* DAC output can be turned off. The DAC hardware needs to be turned on in a periodic fashion +* to recharge the hold capacitor. This feature is firmware controlled using a sequence of function calls. +* See \ref Cy_CTB_DACSampleAndHold in the \ref group_ctb_sample_hold "CTB" driver. +* +* The hold time depends on the supply and reference voltages. The following hold times are based on the +* time it takes for the buffered output to change by 1 LSB. +* +* - Hold time = 750 us @ Vref = VDDA , VDDA = 1.7 V +* - Hold time = 525 us @ Vref = VDDA , VDDA = 3.6 V +* - Hold time = 200 us @ Vref = 1.2 V, VDDA = 3.6 V +* +* \section group_ctdac_low_power Low Power Support +* +* The CTDAC driver provides a callback function to handle power mode transitions. +* If the CTDAC is configured for Deep Sleep operation and \ref group_ctdac_deglitch "deglitching" is enabled, +* the callback \ref Cy_CTDAC_DeepSleepCallback must be registered before calling +* \ref Cy_SysPm_DeepSleep. +* Refer to \ref group_syspm driver for more information about power mode transitions and +* callback registration. +* +* \section group_ctdac_more_information More Information +* +* Refer to the technical reference manual (TRM) and the device datasheet. +* +* \section group_ctdac_MISRA MISRA-C Compliance] +* +* This driver has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AdvisoryA cast should not be performed between a pointer to object type and a different pointer to object type.The cy_syspm driver defines the pointer to void in the \ref cy_stc_syspm_callback_params_t.base field. +* This CTDAC driver implements a Deep Sleep callback conforming to the cy_syspm driver requirements. +* When the callback is called, the base is cast to a pointer to CTDAC_Type. +*
+* +* \section group_ctdac_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0.1Added low power support section. Minor documentation edits.Documentation update and clarification
1.0Initial version
+* +* \defgroup group_ctdac_macros Macros +* \defgroup group_ctdac_functions Functions +* \{ +* \defgroup group_ctdac_functions_init Initialization Functions +* \defgroup group_ctdac_functions_basic Basic Configuration Functions +* \defgroup group_ctdac_functions_switches Switch Control Functions +* \defgroup group_ctdac_functions_interrupts Interrupt Functions +* \defgroup group_ctdac_functions_syspm_callback Low Power Callback +* \} +* \defgroup group_ctdac_globals Global Variables +* \defgroup group_ctdac_data_structures Data Structures +* \defgroup group_ctdac_enums Enumerated Types +*/ + +#if !defined(CY_CTDAC_H) +#define CY_CTDAC_H + +#include +#include +#include +#include "cy_device_headers.h" +#include "syspm/cy_syspm.h" +#include "syslib/cy_syslib.h" +#include "sysclk/cy_sysclk.h" + +#ifndef CY_IP_MXS40PASS_CTDAC + #error "The CTDAC driver is not supported on this device" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_ctdac_macros +* \{ +*/ + +/** Driver major version */ +#define CY_CTDAC_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_CTDAC_DRV_VERSION_MINOR 0 + +/** CTDAC driver identifier */ +#define CY_CTDAC_ID CY_PDL_DRV_ID(0x19u) + +#define CY_CTDAC_DEINIT (0uL) /**< De-init value for CTDAC registers */ +#define CY_CTDAC_UNSIGNED_MID_CODE_VALUE (0x800uL) /**< Middle code value for unsigned values */ +#define CY_CTDAC_UNSIGNED_MAX_CODE_VALUE (0xFFFuL) /**< Maximum code value for unsigned values */ +#define CY_CTDAC_FAST_CLKCFG_TYPE CY_SYSCLK_DIV_8_BIT /**< Clock divider type for quick clock setup */ +#define CY_CTDAC_FAST_CLKCFG_NUM (0uL) /**< Clock divider number for quick clock setup */ +#define CY_CTDAC_FAST_CLKCFG_DIV (99uL) /**< Clock divider integer value for quick clock setup. Divides PERI clock by 100. */ + +/** \cond INTERNAL */ +#define CY_CTDAC_DEINT_CTDAC_SW (CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk | CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Msk) /**< Mask for de-initializing the CTDAC switch control register */ +#define CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV (0uL) /**< Clock divider value for the Strobe Edge Immediate update mode */ +#define CY_CTDAC_STROBE_EDGE_IMMEDIATE_DIV_FRAC (0uL) /**< Clock fractional divider value for the Strobe Edge Immediate update mode */ +#define CY_CTDAC_DEGLITCH_CYCLES_MAX (63uL) + +/**< Macros for conditions used by CY_ASSERT calls */ +#define CY_CTDAC_REFSOURCE(source) (((source) == CY_CTDAC_REFSOURCE_EXTERNAL) || ((source) == CY_CTDAC_REFSOURCE_VDDA)) +#define CY_CTDAC_FORMAT(mode) (((mode) == CY_CTDAC_FORMAT_UNSIGNED) || ((mode) == CY_CTDAC_FORMAT_SIGNED)) +#define CY_CTDAC_UPDATE(mode) ((mode) <= CY_CTDAC_UPDATE_STROBE_LEVEL) +#define CY_CTDAC_DEGLITCH(mode) (((mode) == CY_CTDAC_DEGLITCHMODE_NONE) \ + || ((mode) == CY_CTDAC_DEGLITCHMODE_UNBUFFERED) \ + || ((mode) == CY_CTDAC_DEGLITCHMODE_BUFFERED) \ + || ((mode) == CY_CTDAC_DEGLITCHMODE_BOTH)) +#define CY_CTDAC_OUTPUTMODE(mode) (((mode) == CY_CTDAC_OUTPUT_HIGHZ) \ + || ((mode) == CY_CTDAC_OUTPUT_VALUE) \ + || ((mode) == CY_CTDAC_OUTPUT_VALUE_PLUS1) \ + || ((mode) == CY_CTDAC_OUTPUT_VSSA) \ + || ((mode) == CY_CTDAC_OUTPUT_VREF)) +#define CY_CTDAC_OUTPUTBUFFER(buffer) (((buffer) == CY_CTDAC_OUTPUT_UNBUFFERED) || ((buffer) == CY_CTDAC_OUTPUT_BUFFERED)) +#define CY_CTDAC_DEEPSLEEP(deepSleep) (((deepSleep) == CY_CTDAC_DEEPSLEEP_DISABLE) || ((deepSleep) == CY_CTDAC_DEEPSLEEP_ENABLE)) +#define CY_CTDAC_DEGLITCHCYCLES(cycles) ((cycles) <= CY_CTDAC_DEGLITCH_CYCLES_MAX) +#define CY_CTDAC_SWITCHMASK(mask) ((mask) <= (uint32_t) (CY_CTDAC_SWITCH_CVD_MASK | CY_CTDAC_SWITCH_CO6_MASK)) +#define CY_CTDAC_SWITCHSTATE(state) (((state) == CY_CTDAC_SWITCH_OPEN) || ((state) == CY_CTDAC_SWITCH_CLOSE)) +#define CY_CTDAC_INTRMASK(mask) (((mask) == 0uL) || ((mask) == 1uL)) +/** \endcond */ + +/** \} group_ctdac_macros */ + +/*************************************** +* Enumerated Types +***************************************/ + +/** +* \addtogroup group_ctdac_enums +* \{ +*/ + +/** +* Configure the mode for how the DAC value is updated. +* All the modes require a CTDAC clock except for \ref group_ctdac_updatemode_direct_write. +*/ +typedef enum { + CY_CTDAC_UPDATE_DIRECT_WRITE = 0uL, /**< DAC value is updated with a direct write by calling to \ref Cy_CTDAC_SetValue */ + CY_CTDAC_UPDATE_BUFFERED_WRITE = 1uL, /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on the next CTDAC clock edge */ + CY_CTDAC_UPDATE_STROBE_EDGE_SYNC = 2uL, /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on the next CTDAC clock edge after a rising edge of the strobe */ + CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE = 3uL, /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on the rising edge of the strobe input */ + CY_CTDAC_UPDATE_STROBE_LEVEL = 4uL /**< DAC value stored with \ref Cy_CTDAC_SetValueBuffered is updated on every CTDAC clock edge while the strobe line is high */ +}cy_en_ctdac_update_t; + +/** +* Configure the format in which the DAC value register is decoded. +*/ +typedef enum { + CY_CTDAC_FORMAT_UNSIGNED = 0uL, /**< Unsigned 12-bit DAC. No value decoding */ + CY_CTDAC_FORMAT_SIGNED = 1uL << CTDAC_CTDAC_CTRL_CTDAC_MODE_Pos /**< Virtual signed. Add 0x800 to the 12-bit DAC value */ +}cy_en_ctdac_format_t; + +/** +* Enable or disable the CTDAC hardware during Deep Sleep. +*/ +typedef enum { + CY_CTDAC_DEEPSLEEP_DISABLE = 0uL, /**< DAC is disabled during Deep Sleep power mode */ + CY_CTDAC_DEEPSLEEP_ENABLE = CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk /**< DAC remains enabled during Deep Sleep power mode */ +}cy_en_ctdac_deep_sleep_t; + +/** +* Configure the output state of the CTDAC. +*/ +typedef enum { + CY_CTDAC_OUTPUT_HIGHZ = 0uL, /**< DAC output is tri-state */ + CY_CTDAC_OUTPUT_VALUE = CTDAC_CTDAC_CTRL_OUT_EN_Msk, /**< DAC Output is enabled and drives the programmed value */ + CY_CTDAC_OUTPUT_VALUE_PLUS1 = CTDAC_CTDAC_CTRL_OUT_EN_Msk \ + | CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk, /**< DAC Output enabled and drives the programmed value plus 1 */ + CY_CTDAC_OUTPUT_VSSA = CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk, /**< Output is pulled to Vssa through a 1.1 MOhm (typ) resistor */ + CY_CTDAC_OUTPUT_VREF = CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk \ + | CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk /**< Output is pulled to Vref through a 1.1 MOhm (typ) resistor */ +}cy_en_ctdac_output_mode_t; + +/** +* Configure the deglitch mode. See the \ref group_ctdac_deglitch section for +* more information on how deglitching works. +*/ +typedef enum { + CY_CTDAC_DEGLITCHMODE_NONE = 0uL, /**< Disable deglitch */ + CY_CTDAC_DEGLITCHMODE_UNBUFFERED = CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk, /**< Deglitch through the CO6 switch */ + CY_CTDAC_DEGLITCHMODE_BUFFERED = CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk, /**< Deglitch through the CTB COS switch */ + CY_CTDAC_DEGLITCHMODE_BOTH = CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk \ + | CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk /**< Deglitch through both CO6 and CTB COS switches */ +}cy_en_ctdac_deglitch_t; + +/** +* Configure the reference source for the CTDAC +* +* The CVD switch is closed when Vdda is the reference source. +*/ +typedef enum { + CY_CTDAC_REFSOURCE_EXTERNAL = 0uL, /**< Use an external source from Opamp1 of the CTB as the reference. CVD switch is open. */ + CY_CTDAC_REFSOURCE_VDDA = 1uL /**< Use Vdda as the reference. CVD switch is closed. */ +}cy_en_ctdac_ref_source_t; + +/** Configure the output to be buffered or unbuffered +* +* The CO6 switch is closed when the output is unbuffered to Pin 6 of the CTDAC port. +* See the device datasheet for the CTDAC port. +*/ +typedef enum { + CY_CTDAC_OUTPUT_BUFFERED = 0uL, /**< Buffer the output through the CTB OA0 */ + CY_CTDAC_OUTPUT_UNBUFFERED = 1uL /**< Send output to a direct pin */ +}cy_en_ctdac_output_buffer_t; + +/** Switch state, either open or closed, to be used in \ref Cy_CTDAC_SetAnalogSwitch. */ +typedef enum +{ + CY_CTDAC_SWITCH_OPEN = 0uL, /**< Open the switch */ + CY_CTDAC_SWITCH_CLOSE = 1uL /**< Close the switch */ +}cy_en_ctdac_switch_state_t; + +/** Switch mask to be used in \ref Cy_CTDAC_SetAnalogSwitch */ +typedef enum +{ + CY_CTDAC_SWITCH_CVD_MASK = CTDAC_CTDAC_SW_CTDD_CVD_Msk, /**< Switch for the reference source, Vdda or external */ + CY_CTDAC_SWITCH_CO6_MASK = CTDAC_CTDAC_SW_CTDO_CO6_Msk /**< Switch for the output, buffered or direct */ +}cy_en_ctdac_switches_t; + +/** Return states for \ref Cy_CTDAC_Init, \ref Cy_CTDAC_DeInit, and \ref Cy_CTDAC_FastInit */ +typedef enum { + CY_CTDAC_SUCCESS = 0x00uL, /**< Initialization completed successfully */ + CY_CTDAC_BAD_PARAM = CY_CTDAC_ID | CY_PDL_STATUS_ERROR | 0x01uL /**< Input pointers were NULL and Initialization could not be completed */ +}cy_en_ctdac_status_t; + +/** \} group_ctdac_enums */ + +/*************************************** +* Configuration Structures +***************************************/ + +/** +* \addtogroup group_ctdac_data_structures +* \{ +*/ + +/** Configuration structure to set up the entire CTDAC block to be used with \ref Cy_CTDAC_Init +*/ +typedef struct +{ + cy_en_ctdac_ref_source_t refSource; /**< Reference source: Vdda or externally through Opamp1 of CTB */ + cy_en_ctdac_format_t formatMode; /**< Format of DAC value: signed or unsigned */ + cy_en_ctdac_update_t updateMode; /**< Update mode: direct or buffered writes or hardware, edge or level */ + cy_en_ctdac_deglitch_t deglitchMode; /**< Deglitch mode: disabled, buffered, unbuffered, or both */ + cy_en_ctdac_output_mode_t outputMode; /**< Output mode: enabled (value or value + 1), high-z, Vssa, or Vdda */ + cy_en_ctdac_output_buffer_t outputBuffer; /**< Output path: Buffered through Opamp0 of CTB or connected directly to Pin 6 */ + cy_en_ctdac_deep_sleep_t deepSleep; /**< Enable or disable the CTDAC during Deep Sleep */ + uint32_t deglitchCycles; /**< Number of deglitch cycles from 0 to 63 */ + int32_t value; /**< Current DAC value */ + int32_t nextValue; /**< Next DAC value for double buffering */ + bool enableInterrupt; /**< If true, enable interrupt when next value register is transferred to value register */ + + /* Configuring the clock */ + bool configClock; /**< Configure or ignore clock information */ + cy_en_divider_types_t dividerType; /**< Specifies which type of divider to use. Can be integer or fractional divider. Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE */ + uint32_t dividerNum; /**< Specifies which divider of the selected type to configure. Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE */ + uint32_t dividerIntValue; /**< The integer divider value. The divider value causes integer division of (divider value + 1). Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE or \ref CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE */ + uint32_t dividerFracValue; /**< The fractional divider value if using a fractional clock. Not used if updateMode is \ref CY_CTDAC_UPDATE_DIRECT_WRITE or \ref CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE */ +}cy_stc_ctdac_config_t; + +/** Configuration structure to quickly set up the CTDAC to be used with \ref Cy_CTDAC_FastInit +* This structure provides a selection for the CTDAC reference source and output path. +* +* The other configuration options are set to: +* - .formatMode = \ref CY_CTDAC_FORMAT_UNSIGNED +* - .updateMode = \ref CY_CTDAC_UPDATE_BUFFERED_WRITE +* - .deglitchMode = \ref CY_CTDAC_DEGLITCHMODE_NONE +* - .outputMode = \ref CY_CTDAC_OUTPUT_VALUE +* - .deepSleep = \ref CY_CTDAC_DEEPSLEEP_DISABLE +* - .deglitchCycles = \ref CY_CTDAC_DEINIT +* - .value = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE +* - .nextValue = \ref CY_CTDAC_UNSIGNED_MID_CODE_VALUE +* - .enableInterrupt = true +* - .configClock = true +* - .dividerType = \ref CY_CTDAC_FAST_CLKCFG_TYPE +* - .dividerNum = \ref CY_CTDAC_FAST_CLKCFG_NUM +* - .dividerInitValue = \ref CY_CTDAC_FAST_CLKCFG_DIV +* - .dividerFracValue = \ref CY_CTDAC_DEINIT +*/ +typedef struct +{ + cy_en_ctdac_ref_source_t refSource; /**< Reference source: Vdda or externally through Opamp1 of CTB */ + cy_en_ctdac_output_buffer_t outputBuffer; /**< Output path: Buffered through Opamp0 of CTB or connected directly to Pin 6 */ +}cy_stc_ctdac_fast_config_t; + +/** \} group_ctdac_data_structures */ + +/** \addtogroup group_ctdac_globals +* \{ +*/ +/*************************************** +* Global Variables +***************************************/ + +/** Configure CTDAC to use Vdda reference and output unbuffered. See \ref Cy_CTDAC_FastInit. */ +extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_UnbufferedOut; + +/** Configure CTDAC to use Vdda reference and output buffered through Opamp0 of CTB. See \ref Cy_CTDAC_FastInit. +* +* To quickly configure Opamp0, call with \ref Cy_CTB_FastInit +* with \ref Cy_CTB_Fast_Opamp0_Vdac_Out or \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH. +*/ +extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_VddaRef_BufferedOut; + +/** Configure CTDAC to use a buffered reference from Opamp1 of CTB +* and output unbuffered. See \ref Cy_CTDAC_FastInit. +* +* To use the reference from the Analog Reference (AREF), +* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref. +* +* To use an external reference from a GPIO, +* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 +* for Pin 5 on the CTB port. +*/ +extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_UnbufferedOut; + +/** Configure CTDAC to use a buffered reference from Opamp1 of CTB +* and output buffered through Opamp0 of CTB. See \ref Cy_CTDAC_FastInit. +* +* To quickly configure Opamp0, call with \ref Cy_CTB_FastInit +* with \ref Cy_CTB_Fast_Opamp0_Vdac_Out or \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH. +* +* To use the reference from the Analog Reference (AREF), +* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref. +* +* To use an external reference from a GPIO, +* call \ref Cy_CTB_FastInit with \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5 +* for Pins 5 on the CTB port. +*/ +extern const cy_stc_ctdac_fast_config_t Cy_CTDAC_Fast_OA1Ref_BufferedOut; + +/** \} group_ctdac_globals */ + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_ctdac_functions +* \{ +*/ + +/** +* \addtogroup group_ctdac_functions_init +* This set of functions are for initializing, enabling, and disabling the CTDAC. +* \{ +*/ +cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config); +cy_en_ctdac_status_t Cy_CTDAC_DeInit(CTDAC_Type *base, bool deInitRouting); +cy_en_ctdac_status_t Cy_CTDAC_FastInit(CTDAC_Type *base, const cy_stc_ctdac_fast_config_t *config); +__STATIC_INLINE void Cy_CTDAC_Enable(CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_Disable(CTDAC_Type *base); +/** \} */ + +/** +* \addtogroup group_ctdac_functions_basic +* This set of functions are for configuring basic usage of the CTDAC. +* \{ +*/ +__STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value); +__STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value); +void Cy_CTDAC_SetSignMode(CTDAC_Type *base, cy_en_ctdac_format_t formatMode); +void Cy_CTDAC_SetDeepSleepMode(CTDAC_Type *base, cy_en_ctdac_deep_sleep_t deepSleep); +void Cy_CTDAC_SetOutputMode(CTDAC_Type *base, cy_en_ctdac_output_mode_t outputMode); +void Cy_CTDAC_SetDeglitchMode(CTDAC_Type *base, cy_en_ctdac_deglitch_t deglitchMode); +void Cy_CTDAC_SetDeglitchCycles(CTDAC_Type *base, uint32_t deglitchCycles); +void Cy_CTDAC_SetRef(CTDAC_Type *base, cy_en_ctdac_ref_source_t refSource); +/** \} */ + +/** \addtogroup group_ctdac_functions_switches +* +* This set of functions is for controlling the two CTDAC analog switches, CVD, and CO6. +* These are advanced functions. The switches will be managed by the reference +* source and output mode selections when initializing the hardware. +* \{ +*/ +void Cy_CTDAC_SetAnalogSwitch(CTDAC_Type *base, uint32_t switchMask, cy_en_ctdac_switch_state_t state); +__STATIC_INLINE uint32_t Cy_CTDAC_GetAnalogSwitch(const CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_SetSwitchCO6(CTDAC_Type *base, cy_en_ctdac_switch_state_t state); +__STATIC_INLINE void Cy_CTDAC_OpenAllSwitches(CTDAC_Type *base); +/** \} */ + +/** \addtogroup group_ctdac_functions_interrupts +* This set of functions is related to the CTDAC interrupt +* \{ +*/ +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_SetInterrupt(CTDAC_Type *base); +__STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask); +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base); +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *base); +/** \} */ + +/** \addtogroup group_ctdac_functions_syspm_callback +* This driver supports one SysPm callback for Deep Sleep transition. +* \{ +*/ +cy_en_syspm_status_t Cy_CTDAC_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams); +/** \} */ + +/** +* \addtogroup group_ctdac_functions_init +* \{ +*/ +/******************************************************************************* +* Function Name: Cy_CTDAC_Enable +****************************************************************************//** +* +* Power up the CTDAC hardware block. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_Enable(CTDAC_Type *base) +{ + base->CTDAC_CTRL |= CTDAC_CTDAC_CTRL_ENABLED_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_Disable +****************************************************************************//** +* +* Turn off the hardware block. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_Disable(CTDAC_Type *base) +{ + base->CTDAC_CTRL &= ~CTDAC_CTDAC_CTRL_ENABLED_Msk; +} +/** \} */ + +/** +* \addtogroup group_ctdac_functions_basic +* \{ +*/ +/******************************************************************************* +* Function Name: Cy_CTDAC_SetValue +****************************************************************************//** +* +* Set the CTDAC_VAL register (DAC hardware is +* updated on the next PeriClk cycle). Only the least significant 12 bits +* have an effect. Sign extension of negative values is unnecessary and is +* ignored by the hardware. The way in which the CTDAC interprets the 12-bit +* data is controlled by \ref Cy_CTDAC_SetSignMode. +* +* \note +* Call this function only when the update mode is set to \ref group_ctdac_updatemode_direct_write. +* Calling this function for any other update mode will not have the intended effect. +* +* \param base +* Pointer to structure describing registers +* +* \param value +* Value to write into the CTDAC_VAL register +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_VALUE +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_SetValue(CTDAC_Type *base, int32_t value) +{ + base->CTDAC_VAL = (((uint32_t)value) << CTDAC_CTDAC_VAL_VALUE_Pos) & CTDAC_CTDAC_VAL_VALUE_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetValueBuffered +****************************************************************************//** +* +* Set the CTDAC_VAL_NEXT register. The value is transferred +* to the CTDAC_VAL register on the next edge of the CTDAC clock. +* Only the least significant 12 bits +* have an effect. Sign extension of negative values is unnecessary and is +* ignored by the hardware. The way in which the CTDAC interprets the 12-bit +* data is controlled by \ref Cy_CTDAC_SetSignMode. +* +* \note +* Calling this function in \ref group_ctdac_updatemode_direct_write mode will not update the DAC output. +* Call this function for all modes that use buffered values (i.e. uses a clock). +* +* \param base +* Pointer to structure describing registers +* +* \param value +* Value to write into the CTDAC_VAL_NEXT register +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_VALUE_BUFFERED +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_SetValueBuffered(CTDAC_Type *base, int32_t value) +{ + base->CTDAC_VAL_NXT = (((uint32_t)value) << CTDAC_CTDAC_VAL_NXT_VALUE_Pos) & CTDAC_CTDAC_VAL_NXT_VALUE_Msk; +} +/** \} */ + +/** +* \addtogroup group_ctdac_functions_switches +* \{ +*/ +/******************************************************************************* +* Function Name: Cy_CTDAC_GetAnalogSwitch +****************************************************************************//** +* +* Return the state (open or close) of the CTDAC switches. +* +* \note +* The switches will be managed by the reference +* source and output mode selections when initializing the hardware. +* +* \param base +* Pointer to structure describing registers +* +* \return +* Switch state. Compare this value to the masks found in \ref cy_en_ctdac_switches_t. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTDAC_GetAnalogSwitch(const CTDAC_Type *base) +{ + return base->CTDAC_SW; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetSwitchCO6 +****************************************************************************//** +* +* Open or close switch CO6 that controls whether the output gets routed +* directly to a pin or through Opamp0 of the CTB. This function calls +* \ref Cy_CTDAC_SetAnalogSwitch with the switchMask set to \ref CY_CTDAC_SWITCH_CO6_MASK. +* +* \note +* The switches is configured by the output mode selections during initialization. +* +* \note +* This switch will temporarily +* be opened for deglitching if the degitch mode is \ref CY_CTDAC_DEGLITCHMODE_UNBUFFERED or +* \ref CY_CTDAC_DEGLITCHMODE_BOTH. +* +* \param base +* Pointer to structure describing registers +* +* \param state +* State of the switch, open or close. +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_SET_SWITCH_CO6 +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_SetSwitchCO6(CTDAC_Type *base, cy_en_ctdac_switch_state_t state) +{ + Cy_CTDAC_SetAnalogSwitch(base, (uint32_t) CY_CTDAC_SWITCH_CO6_MASK, state); +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_OpenAllSwitches +****************************************************************************//** +* +* Open all switches in the CTDAC (CO6 and CVD). +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm4.c CTDAC_SNIPPET_OPEN_ALL_SWITCHES +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_OpenAllSwitches(CTDAC_Type *base) +{ + base->CTDAC_SW_CLEAR = CY_CTDAC_DEINT_CTDAC_SW; +} + +/** \} */ + +/** +* \addtogroup group_ctdac_functions_interrupts +* \{ +*/ +/******************************************************************************* +* Function Name: Cy_CTDAC_GetInterruptStatus +****************************************************************************//** +* +* Return the interrupt status which gets set by the hardware +* when the CTDAC_VAL_NXT register value is transferred to the CTDAC_VAL register. +* Once set, the CTDAC_VAL_NXT register is ready to accept a new value. +* +* \note +* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write. +* +* \param base +* Pointer to structure describing registers +* +* \return +* - 0: Value not moved from CTDAC_VAL_NXT to CTDAC_VAL +* - 1: Value moved from CTDAC_VAL_NXT to CTDAC_VAL +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_GET_INTERRUPT_STATUS +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatus(const CTDAC_Type *base) +{ + return (base->INTR & CTDAC_INTR_VDAC_EMPTY_Msk) >> CTDAC_INTR_VDAC_EMPTY_Pos; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_ClearInterrupt +****************************************************************************//** +* +* Clear the interrupt that was set by the hardware when the +* CTDAC_VAL_NXT register value is transferred to the CTDAC_VAL register. +* The interrupt must be cleared with this function so that +* the hardware can set subsequent interrupts and those interrupts +* can be forwarded to the interrupt controller, if enabled. +* +* \note +* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_ClearInterrupt(CTDAC_Type *base) +{ + base->INTR = CTDAC_INTR_VDAC_EMPTY_Msk; + + /* Dummy read for buffered writes. */ + (void) base->INTR; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetInterrupt +****************************************************************************//** +* +* Force the CTDAC interrupt to trigger using software. +* +* \note +* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write. +* +* \param base +* Pointer to structure describing registers +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_SetInterrupt(CTDAC_Type *base) +{ + base->INTR_SET = CTDAC_INTR_SET_VDAC_EMPTY_SET_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_SetInterruptMask +****************************************************************************//** +* +* Configure the CTDAC interrupt to be forwarded to the CPU interrupt +* controller. +* +* \note +* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write. +* +* \param base +* Pointer to structure describing registers +* +* \param mask +* The CTDAC only has one interrupt so the mask is one bit. +* - 0: Disable CTDAC interrupt request (will not be forwarded to CPU interrupt controller) +* - 1: Enable CTDAC interrupt request (will be forwarded to CPU interrupt controller) +* +* \return None +* +* \funcusage +* +* \snippet ctdac_sut_01.cydsn/main_cm0p.c SNIPPET_CTDAC_SET_INTERRUPT_MASK +* +*******************************************************************************/ +__STATIC_INLINE void Cy_CTDAC_SetInterruptMask(CTDAC_Type *base, uint32_t mask) +{ + CY_ASSERT_L2(CY_CTDAC_INTRMASK(mask)); + + base->INTR_MASK = mask & CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_GetInterruptMask +****************************************************************************//** +* +* Return whether the CTDAC interrupt is +* forwarded to the CPU interrupt controller +* as configured by \ref Cy_CTDAC_SetInterruptMask. +* +* \note +* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write. +* +* \param base +* Pointer to structure describing registers +* +* \return +* The CTDAC only has one interrupt so the return value is either 0 or 1. +* - 0: Interrupt output not forwarded to CPU interrupt controller +* - 1: Interrupt output forwarded to CPU interrupt controller +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptMask(const CTDAC_Type *base) +{ + return (base->INTR_MASK & CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk) >> CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Pos; +} + +/******************************************************************************* +* Function Name: Cy_CTDAC_GetInterruptStatusMasked +****************************************************************************//** +* +* Return the bitwise AND of \ref Cy_CTDAC_GetInterruptStatus and +* \ref Cy_CTDAC_SetInterruptMask. When high, the DAC interrupt is +* asserted and the interrupt is forwarded to the CPU interrupt +* controller. +* +* \note +* Interrupts are available in all update modes except \ref group_ctdac_updatemode_direct_write. +* +* \param base +* Pointer to structure describing registers +* +* \return +* - 0: Value not moved from CTDAC_VAL_NXT to CTDAC_VAL or not masked +* - 1: Value moved from CTDAC_VAL_NXT to CTDAC_VAL and masked +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_CTDAC_GetInterruptStatusMasked(const CTDAC_Type *base){ + return (base->INTR_MASKED & CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Msk) >> CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Pos; +} + +/** \} */ + +/** \} group_ctdac_functions */ + +#if defined(__cplusplus) +} +#endif + +#endif /** !defined(CY_CTDAC_H) */ + +/** \} group_ctdac */ + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.c new file mode 100644 index 0000000000..5f9bd8164b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.c @@ -0,0 +1,353 @@ +/***************************************************************************//** +* \file cy_dma.c +* \version 2.0.1 +* +* \brief +* The source code file for the DMA driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "cy_dma.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_Init +****************************************************************************//** +* +* Initializes the descriptor structure in SRAM from a pre-initialized +* configuration structure. +* This function initializes only the descriptor and not the channel. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param config +* This is a configuration structure that has all initialization information for +* the descriptor. +* +* \return +* The status /ref cy_en_dma_status_t. +* +*******************************************************************************/ +cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor, const cy_stc_dma_descriptor_config_t * config) +{ + cy_en_dma_status_t retVal = CY_DMA_BAD_PARAM; + + if ((NULL != descriptor) && (NULL != config)) + { + CY_ASSERT_L3(CY_DMA_IS_RETRIGGER_VALID(config->retrigger)); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->interruptType)); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->triggerOutType)); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->triggerInType)); + CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(config->srcTransferSize)); + CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(config->dstTransferSize)); + CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(config->channelState)); + CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(config->dataSize)); + CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(config->descriptorType)); + + descriptor->ctl = + _VAL2FLD(CY_DMA_CTL_RETRIG, config->retrigger) | + _VAL2FLD(CY_DMA_CTL_INTR_TYPE, config->interruptType) | + _VAL2FLD(CY_DMA_CTL_TR_OUT_TYPE, config->triggerOutType) | + _VAL2FLD(CY_DMA_CTL_TR_IN_TYPE, config->triggerInType) | + _VAL2FLD(CY_DMA_CTL_SRC_SIZE, config->srcTransferSize) | + _VAL2FLD(CY_DMA_CTL_DST_SIZE, config->dstTransferSize) | + _VAL2FLD(CY_DMA_CTL_CH_DISABLE, config->channelState) | + _VAL2FLD(CY_DMA_CTL_DATA_SIZE, config->dataSize) | + _VAL2FLD(CY_DMA_CTL_TYPE, config->descriptorType); + + descriptor->src = (uint32_t)config->srcAddress; + + descriptor->dst = (uint32_t)config->dstAddress; + + switch(config->descriptorType) + { + case CY_DMA_SINGLE_TRANSFER: + { + descriptor->xCtl = (uint32_t)config->nextDescriptor; + break; + } + case CY_DMA_1D_TRANSFER: + { + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcXincrement)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstXincrement)); + CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->xCount)); + + descriptor->xCtl = + _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) | + /* Convert the data count from the user's range (1-256) into the machine range (0-255). */ + _VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL); + + descriptor->yCtl = (uint32_t)config->nextDescriptor; + break; + } + case CY_DMA_2D_TRANSFER: + { + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcXincrement)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstXincrement)); + CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->xCount)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcYincrement)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstYincrement)); + CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->yCount)); + + descriptor->xCtl = + _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) | + /* Convert the data count from the user's range (1-256) into the machine range (0-255). */ + _VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL); + + descriptor->yCtl = + _VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcYincrement) | + _VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstYincrement) | + /* Convert the data count from the user's range (1-256) into the machine range (0-255). */ + _VAL2FLD(CY_DMA_CTL_COUNT, config->yCount - 1UL); + + descriptor->nextPtr = (uint32_t)config->nextDescriptor; + break; + } + default: + { + /* An unsupported type of a descriptor */ + break; + } + } + + retVal = CY_DMA_SUCCESS; + } + + return retVal; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_DeInit +****************************************************************************//** +* +* Clears the content of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +*******************************************************************************/ +void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor) +{ + descriptor->ctl = 0UL; + descriptor->src = 0UL; + descriptor->dst = 0UL; + descriptor->xCtl = 0UL; + descriptor->yCtl = 0UL; + descriptor->nextPtr = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_Init +****************************************************************************//** +* +* Initializes the DMA channel with a descriptor and other parameters. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +* \param channelConfig +* The structure that has the initialization information for the +* channel. +* +* \return +* The status /ref cy_en_dma_status_t. +* +*******************************************************************************/ +cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_dma_channel_config_t const * channelConfig) +{ + cy_en_dma_status_t retVal = CY_DMA_BAD_PARAM; + + if (((CY_DMA_IS_DW_CH_NR_VALID(base, channel)) && (NULL != channelConfig) && (NULL != channelConfig->descriptor))) + { + CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(channelConfig->priority)); + + /* Set the current descriptor */ + base->CH_STRUCT[channel].CH_CURR_PTR = (uint32_t)channelConfig->descriptor; + + /* Set the channel configuration */ + base->CH_STRUCT[channel].CH_CTL = _BOOL2FLD(DW_CH_STRUCT_CH_CTL_PREEMPTABLE, channelConfig->preemptable) | + _VAL2FLD(DW_CH_STRUCT_CH_CTL_PRIO, channelConfig->priority) | + _BOOL2FLD(DW_CH_STRUCT_CH_CTL_ENABLED, channelConfig->enable) | + _BOOL2FLD(DW_CH_STRUCT_CH_CTL_B, channelConfig->bufferable); + retVal = CY_DMA_SUCCESS; + } + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_DeInit +****************************************************************************//** +* +* Clears the content of registers corresponding to the channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* A channel number. +* +*******************************************************************************/ +void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + base->CH_STRUCT[channel].CH_CTL = 0UL; + base->CH_STRUCT[channel].CH_IDX = 0UL; + base->CH_STRUCT[channel].CH_CURR_PTR = 0UL; + base->CH_STRUCT[channel].INTR_MASK = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetNextDescriptor +****************************************************************************//** +* +* Sets a Next Descriptor parameter for the specified descriptor. +* +* Based on the descriptor type, the offset of the address for the next descriptor may +* vary. For the single-transfer descriptor type, this register is at offset 0x0c. +* For the 1D-transfer descriptor type, this register is at offset 0x10. +* For the 2D-transfer descriptor type, this register is at offset 0x14. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param nextDescriptor +* The pointer to the next descriptor. +* +*******************************************************************************/ +void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + switch((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl)) + { + case CY_DMA_SINGLE_TRANSFER: + descriptor->xCtl = (uint32_t)nextDescriptor; + break; + + case CY_DMA_1D_TRANSFER: + descriptor->yCtl = (uint32_t)nextDescriptor; + break; + + case CY_DMA_2D_TRANSFER: + descriptor->nextPtr = (uint32_t)nextDescriptor; + break; + + default: + /* Unsupported type of descriptor */ + break; + } +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetNextDescriptor +****************************************************************************//** +* +* Returns a next descriptor address of the specified descriptor. +* +* Based on the descriptor type, the offset of the address for the next descriptor may +* vary. For a single-transfer descriptor type, this register is at offset 0x0c. +* For the 1D-transfer descriptor type, this register is at offset 0x10. +* For the 2D-transfer descriptor type, this register is at offset 0x14. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The pointer to the next descriptor. +* +*******************************************************************************/ +cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descriptor_t const * descriptor) +{ + cy_stc_dma_descriptor_t * retVal = NULL; + + CY_ASSERT_L1(NULL != descriptor); + + switch((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl)) + { + case CY_DMA_SINGLE_TRANSFER: + retVal = (cy_stc_dma_descriptor_t*) descriptor->xCtl; + break; + + case CY_DMA_1D_TRANSFER: + retVal = (cy_stc_dma_descriptor_t*) descriptor->yCtl; + break; + + case CY_DMA_2D_TRANSFER: + retVal = (cy_stc_dma_descriptor_t*) descriptor->nextPtr; + break; + + default: + /* An unsupported type of the descriptor */ + break; + } + + return (retVal); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetDescriptorType +****************************************************************************//** +* +* Sets the descriptor's type for the specified descriptor. +* Moves the next descriptor register value into the proper place in accordance +* to the actual descriptor type. +* During the descriptor's type changing, the Xloop and Yloop settings, such as +* data count and source/destination increment (i.e. the content of the +* xCtl and yCtl descriptor registers) might be lost (overriden by the +* next descriptor value) because of the different descriptor registers structures +* for different descriptor types. Set up carefully the Xloop +* (and Yloop, if used) data count and source/destination increment if the +* descriptor type is changed from a simpler to a more complicated type +* ("single transfer" -> "1D", "1D" -> "2D", etc.). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param descriptorType +* The descriptor type \ref cy_en_dma_descriptor_type_t. +* +*******************************************************************************/ +void Cy_DMA_Descriptor_SetDescriptorType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(descriptorType)); + + if (descriptorType != Cy_DMA_Descriptor_GetDescriptorType(descriptor)) /* Don't perform if the type is not changed */ + { + /* Store the current nextDescriptor pointer. */ + cy_stc_dma_descriptor_t * locNextDescriptor = Cy_DMA_Descriptor_GetNextDescriptor(descriptor); + /* Change the descriptor type. */ + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TYPE, descriptorType); + /* Restore the nextDescriptor pointer into the proper place. */ + Cy_DMA_Descriptor_SetNextDescriptor(descriptor, locNextDescriptor); + } +} + + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.h new file mode 100644 index 0000000000..85b1857aaa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.h @@ -0,0 +1,1810 @@ +/***************************************************************************//** +* \file cy_dma.h +* \version 2.0.1 +* +* \brief +* The header file of the DMA driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +/** +* \defgroup group_dma Direct Memory Access (DMA) +* \{ +* Configures a DMA channel and its descriptor(s). +* +* The DMA channel can be used in any project to transfer data +* without CPU intervention basing on a hardware trigger signal from another component. +* +* A device may support more than one DMA hardware block. Each block has a set of +* registers, a base hardware address, and supports multiple channels. +* Many API functions for the DMA driver require a base hardware address and +* channel number. Ensure that you use the correct hardware address for the DMA block in use. +* +* Features: +* * Devices support up to two DMA hardware blocks +* * Each DMA block supports up to 16 DMA channels +* * Supports channel descriptors in SRAM +* * Four priority levels for each channel +* * Byte, half-word (2-byte), and word (4-byte) transfers +* * Configurable source and destination addresses +* +* \section group_dma_configuration Configuration Considerations +* +* To set up a DMA driver, initialize a descriptor, +* intialize and enable a channel, and enable the DMA block. +* +* To set up a descriptor, provide the configuration parameters for the +* descriptor in the \ref cy_stc_dma_descriptor_config_t structure. Then call the +* \ref Cy_DMA_Descriptor_Init function to initialize the descriptor in SRAM. You can +* modify the source and destination addresses dynamically by calling +* \ref Cy_DMA_Descriptor_SetSrcAddress and \ref Cy_DMA_Descriptor_SetDstAddress. +* +* To set up a DMA channel, provide a filled \ref cy_stc_dma_channel_config_t +* structure. Call the \ref Cy_DMA_Channel_Init function, specifying the channel +* number. Use \ref Cy_DMA_Channel_Enable to enable the configured DMA channel. +* +* Call \ref Cy_DMA_Channel_Enable for each DMA channel in use. +* +* When configured, another peripheral typically triggers the DMA. The trigger is +* connected to the DMA using the trigger multiplexer. The trigger multiplexer +* driver has a software trigger you can use in firmware to trigger the DMA. See the +* Trigger Multiplexer documentation. +* +* The following is a simplified structure of the DMA driver API interdependencies +* in a typical user application: +* \image html dma.png +* +* NOTE: Even if a DMA channel is enabled, it is not operational until +* the DMA block is enabled using function \ref Cy_DMA_Enable.\n +* NOTE: if the DMA descriptor is configured to generate an interrupt, +* the interrupt must be enabled using the \ref Cy_DMA_Channel_SetInterruptMask +* function for each DMA channel. +* +* For example: +* \snippet dma/dma_v2_0_sut_00.cydsn/main_cm4.c Cy_DMA_Snippet +* +* \section group_dma_more_information More Information. +* See: the DMA chapter of the device technical reference manual (TRM); +* the DMA Component datasheet; +* CE219940 - PSoC 6 MCU Multiple DMA Concatenation. +* +* \section group_dma_MISRA MISRA-C Compliance +* The DMA driver has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
10.3RA composite expression of the "essentially unsigned" type is being +* cast to a different type category.The value got from the bitfield physically cannot exceed the enumeration +* that describes this bitfield. So, the code is safe by design.
14.2RAll non-null statements will either: +* a) have at least one-side effect however executed; +* b) cause the control flow to changeA Read operation result is ignored when this read is just intended +* to ensure the previous Write operation is flushed out to the hardware.
+* +* \section group_dma_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.0.1Changed \ref CY_DMA_BWC macro values from Boolean to numericImprovements made based on usability feedback
2.0* All the API is refactored to be consistent within itself and with the +* rest of the PDL content. +* * The descriptor API is updated as follows: +* The \ref Cy_DMA_Descriptor_Init function sets a full bunch of descriptor +* settings, and the rest of the descriptor API is a get/set interface +* to each of the descriptor settings. +* * There is a group of macros to support the backward compatibility with most +* of the driver version 1.0 API. But, it is strongly recommended to use +* the new v2.0 interface in new designs (do not just copy-paste from old +* projects). To enable the backward compatibility support, the CY_DMA_BWC +* definition should be changed to "1".
1.0Initial version
+* + +* \defgroup group_dma_macros Macros +* \defgroup group_dma_functions Functions +* \{ +* \defgroup group_dma_block_functions Block Functions +* \defgroup group_dma_descriptor_functions Descriptor Functions +* \defgroup group_dma_channel_functions Channel Functions +* \} +* \defgroup group_dma_data_structures Data Structures +* \defgroup group_dma_enums Enumerated Types +*/ + +#if !defined(CY_DMA_H) +#define CY_DMA_H + +#include +#include +#include +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" + +#ifndef CY_IP_M4CPUSS_DMA + #error "The DMA driver is not supported on this device" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** + * Macro definitions * + ******************************************************************************/ + +/** +* \addtogroup group_dma_macros +* \{ +*/ + +/** The driver major version */ +#define CY_DMA_DRV_VERSION_MAJOR 2 + +/** The driver minor version */ +#define CY_DMA_DRV_VERSION_MINOR 0 + +/** The DMA driver identifier */ +#define CY_DMA_ID (CY_PDL_DRV_ID(0x13U)) + +/** The DMA channel interrupt mask */ +#define CY_DMA_INTR_MASK (0x01UL) + +/** The backward compatibility flag. Enables a group of macros which provide +* the backward compatibility with most of the DMA driver version 1.0 interface. */ +#ifndef CY_DMA_BWC + #define CY_DMA_BWC (0U) +#endif + +/** \} group_dma_macros */ + + +/** +* \addtogroup group_dma_enums +* \{ +*/ + +/** Contains the possible interrupt cause values */ +typedef enum +{ + CY_DMA_INTR_CAUSE_NO_INTR = 0U, /**< No interrupt */ + CY_DMA_INTR_CAUSE_COMPLETION = 1U, /**< Completion */ + CY_DMA_INTR_CAUSE_SRC_BUS_ERROR = 2U, /**< Source bus error */ + CY_DMA_INTR_CAUSE_DST_BUS_ERROR = 3U, /**< Destination bus error */ + CY_DMA_INTR_CAUSE_SRC_MISAL = 4U, /**< Source address is not aligned */ + CY_DMA_INTR_CAUSE_DST_MISAL = 5U, /**< Destination address is not aligned */ + CY_DMA_INTR_CAUSE_CURR_PTR_NULL = 6U, /**< Current descripror pointer is NULL */ + CY_DMA_INTR_CAUSE_ACTIVE_CH_DISABLED = 7U, /**< Active channel is disabled */ + CY_DMA_INTR_CAUSE_DESCR_BUS_ERROR = 8U /**< Descriptor bus error */ +} cy_en_dma_intr_cause_t; + +/** Contains the options for the descriptor type */ +typedef enum +{ + CY_DMA_SINGLE_TRANSFER = 0UL, /**< Single transfer. */ + CY_DMA_1D_TRANSFER = 1UL, /**< 1D transfer. */ + CY_DMA_2D_TRANSFER = 2UL /**< 2D transfer. */ +} cy_en_dma_descriptor_type_t; + +/** Contains the options for the interrupt, trig-in and trig-out type parameters of the descriptor */ +typedef enum +{ + CY_DMA_1ELEMENT = 0UL, /**< One element transfer. */ + CY_DMA_X_LOOP = 1UL, /**< One X loop transfer. */ + CY_DMA_DESCR = 2UL, /**< One descriptor transfer. */ + CY_DMA_DESCR_CHAIN = 3UL /**< Entire descriptor chain transfer. */ +} cy_en_dma_trigger_type_t; + +/** This enum has the options for the data size */ +typedef enum +{ + CY_DMA_BYTE = 0UL, /**< One byte */ + CY_DMA_HALFWORD = 1UL, /**< Half word (two bytes) */ + CY_DMA_WORD = 2UL /**< Full word (four bytes) */ +} cy_en_dma_data_size_t; + +/** This enum has the options for descriptor retriggering */ +typedef enum +{ + CY_DMA_RETRIG_IM = 0UL, /**< Retrigger immediatelly */ + CY_DMA_RETRIG_4CYC = 1UL, /**< Retrigger after 4 Clk_Slow cycles */ + CY_DMA_RETRIG_16CYC = 2UL, /**< Retrigger after 16 Clk_Slow cycles */ + CY_DMA_WAIT_FOR_REACT = 3UL /**< Wait for trigger reactivation */ +} cy_en_dma_retrigger_t; + +/** This enum has the options for the transfer size */ +typedef enum +{ + CY_DMA_TRANSFER_SIZE_DATA = 0UL, /**< As specified by dataSize. */ + CY_DMA_TRANSFER_SIZE_WORD = 1UL, /**< A full word (four bytes). */ +} cy_en_dma_transfer_size_t; + +/** This enum has the options for the state of the channel when the descriptor is completed */ +typedef enum +{ + CY_DMA_CHANNEL_ENABLED = 0UL, /**< Channel stays enabled */ + CY_DMA_CHANNEL_DISABLED = 1UL /**< Channel is disabled */ +} cy_en_dma_channel_state_t; + +/** This enum has the return values of the DMA driver */ +typedef enum +{ + CY_DMA_SUCCESS = 0x00UL, /**< Success. */ + CY_DMA_BAD_PARAM = CY_DMA_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< The input parameters passed to the DMA API are not valid. */ +} cy_en_dma_status_t; + +/** \} group_dma_enums */ + + +/** \cond Macros for the conditions used by CY_ASSERT calls */ + +#define CY_DMA_IS_COUNT_VALID(count) (((count) >= 1UL) && ((count) <= 256UL)) +#define CY_DMA_IS_INCR_VALID(incr) (((incr) >= -2048L) && ((incr) <= 2047L)) +#define CY_DMA_IS_PRIORITY_VALID(prio) ((prio) <= 3UL) +#define CY_DMA_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_DMA_INTR_MASK))) + +#define CY_DMA_IS_RETRIGGER_VALID(retrigger) ((CY_DMA_RETRIG_IM == (retrigger)) || \ + (CY_DMA_RETRIG_4CYC == (retrigger)) || \ + (CY_DMA_RETRIG_16CYC == (retrigger)) || \ + (CY_DMA_WAIT_FOR_REACT == (retrigger))) + +#define CY_DMA_IS_TRIG_TYPE_VALID(trigType) ((CY_DMA_1ELEMENT == (trigType)) || \ + (CY_DMA_X_LOOP == (trigType)) || \ + (CY_DMA_DESCR == (trigType)) || \ + (CY_DMA_DESCR_CHAIN == (trigType))) + +#define CY_DMA_IS_XFER_SIZE_VALID(xferSize) ((CY_DMA_TRANSFER_SIZE_DATA == (xferSize)) || \ + (CY_DMA_TRANSFER_SIZE_WORD == (xferSize))) + +#define CY_DMA_IS_CHANNEL_STATE_VALID(state) ((CY_DMA_CHANNEL_ENABLED == (state)) || \ + (CY_DMA_CHANNEL_DISABLED == (state))) + +#define CY_DMA_IS_DATA_SIZE_VALID(dataSize) ((CY_DMA_BYTE == (dataSize)) || \ + (CY_DMA_HALFWORD == (dataSize)) || \ + (CY_DMA_WORD == (dataSize))) + +#define CY_DMA_IS_TYPE_VALID(descrType) ((CY_DMA_SINGLE_TRANSFER == (descrType)) || \ + (CY_DMA_1D_TRANSFER == (descrType)) || \ + (CY_DMA_2D_TRANSFER == (descrType))) + +#define CY_DMA_IS_DW_CH_NR_VALID(dwNr, chNr) (((0U != CPUSS_DW0_PRESENT) && (DW0 == (dwNr)) && ((chNr) < CPUSS_DW0_CH_NR)) || \ + ((0U != CPUSS_DW1_PRESENT) && (DW1 == (dwNr)) && ((chNr) < CPUSS_DW1_CH_NR))) + +/* The descriptor structure bit-filed definitions */ +#define CY_DMA_CTL_RETRIG_Pos 0UL +#define CY_DMA_CTL_RETRIG_Msk 0x3UL +#define CY_DMA_CTL_INTR_TYPE_Pos 2UL +#define CY_DMA_CTL_INTR_TYPE_Msk 0xCUL +#define CY_DMA_CTL_TR_OUT_TYPE_Pos 4UL +#define CY_DMA_CTL_TR_OUT_TYPE_Msk 0x30UL +#define CY_DMA_CTL_TR_IN_TYPE_Pos 6UL +#define CY_DMA_CTL_TR_IN_TYPE_Msk 0xC0UL +#define CY_DMA_CTL_CH_DISABLE_Pos 24UL +#define CY_DMA_CTL_CH_DISABLE_Msk 0x1000000UL +#define CY_DMA_CTL_SRC_SIZE_Pos 26UL +#define CY_DMA_CTL_SRC_SIZE_Msk 0x4000000UL +#define CY_DMA_CTL_DST_SIZE_Pos 27UL +#define CY_DMA_CTL_DST_SIZE_Msk 0x8000000UL +#define CY_DMA_CTL_DATA_SIZE_Pos 28UL +#define CY_DMA_CTL_DATA_SIZE_Msk 0x30000000UL +#define CY_DMA_CTL_TYPE_Pos 30UL +#define CY_DMA_CTL_TYPE_Msk 0xC0000000UL + +#define CY_DMA_CTL_SRC_INCR_Pos 0UL +#define CY_DMA_CTL_SRC_INCR_Msk 0xFFFUL +#define CY_DMA_CTL_DST_INCR_Pos 12UL +#define CY_DMA_CTL_DST_INCR_Msk 0xFFF000UL +#define CY_DMA_CTL_COUNT_Pos 24UL +#define CY_DMA_CTL_COUNT_Msk 0xFF000000UL + +/** \endcond */ + + +/** +* \addtogroup group_dma_data_structures +* \{ +*/ + +/** +* DMA descriptor structure type. It is a user/component-declared structure +* allocated in RAM. The DMA HW requires a pointer to this structure to work with it. +* +* For advanced users: the descriptor can be allocated even in Flash, then the user +* manually predefines all the structure items with constants, +* bacause most of the driver's API (especially functions modifying +* descriptors, including \ref Cy_DMA_Descriptor_Init()) can't work with +* read-only descriptors. +*/ +typedef struct +{ + uint32_t ctl; /*!< 0x00000000 Descriptor control */ + uint32_t src; /*!< 0x00000004 Descriptor source */ + uint32_t dst; /*!< 0x00000008 Descriptor destination */ + uint32_t xCtl; /*!< 0x0000000C Descriptor X loop control */ + uint32_t yCtl; /*!< 0x00000010 Descriptor Y loop control */ + uint32_t nextPtr; /*!< 0x00000014 Descriptor next pointer */ +} cy_stc_dma_descriptor_t; + +/** +* This structure is a configuration structure pre-initialized by the user and +* passed as a parameter to the \ref Cy_DMA_Descriptor_Init(). +* It can be allocated in RAM/Flash (on user's choice). +* In case of Flash allocation there is a possibility to reinitialize the descriptor in runtime. +* This structure has all the parameters of the descriptor as separate parameters. +* Most of these parameters are represented in the \ref cy_stc_dma_descriptor_t structure as bit fields. +*/ +typedef struct +{ + cy_en_dma_retrigger_t retrigger; /**< Specifies whether the DW controller should wait for the input trigger to be deactivated. */ + cy_en_dma_trigger_type_t interruptType; /**< Sets the event that triggers an interrupt, see \ref cy_en_dma_trigger_type_t. */ + cy_en_dma_trigger_type_t triggerOutType; /**< Sets the event that triggers an output, see \ref cy_en_dma_trigger_type_t. */ + cy_en_dma_channel_state_t channelState; /**< Specifies if the channel is enabled or disabled on completion of descriptor see \ref cy_en_dma_channel_state_t. */ + cy_en_dma_trigger_type_t triggerInType; /**< Sets what type of transfer is triggered, see \ref cy_en_dma_trigger_type_t. */ + cy_en_dma_data_size_t dataSize; /**< The size of the data bus for transfer, see \ref cy_en_dma_data_size_t. */ + cy_en_dma_transfer_size_t srcTransferSize; /**< The source transfer size. */ + cy_en_dma_transfer_size_t dstTransferSize; /**< The destination transfer size. */ + cy_en_dma_descriptor_type_t descriptorType; /**< The type of the descriptor see \ref cy_en_dma_descriptor_type_t. */ + void * srcAddress; /**< The source address of the transfer. */ + void * dstAddress; /**< The destination address of the transfer. */ + int32_t srcXincrement; /**< The address increment of the source after each X-loop transfer. Valid range is -2048...2047. */ + int32_t dstXincrement; /**< The address increment of the destination after each X-loop transfer. Valid range is -2048...2047. */ + uint32_t xCount; /**< The number of transfers in an X-loop. Valid range is 1...256. */ + int32_t srcYincrement; /**< The address increment of the source after each Y-loop transfer. Valid range is -2048...2047. */ + int32_t dstYincrement; /**< The address increment of the destination after each Y-loop transfer. Valid range is -2048...2047. */ + uint32_t yCount; /**< The number of X-loops in the Y-loop. Valid range is 1...256. */ + cy_stc_dma_descriptor_t * nextDescriptor; /**< The next descriptor to chain after completion, a NULL value will signify no chaining. */ +} cy_stc_dma_descriptor_config_t; + +/** This structure holds the initialization values for the DMA channel */ +typedef struct +{ + cy_stc_dma_descriptor_t * descriptor; /**< The DMA descriptor associated with the channel being initialized */ + bool preemptable; /**< Specifies if the channel is preemptable by another higher-priority channel */ + uint32_t priority; /**< This parameter specifies the channel's priority */ + bool enable; /**< This parameter specifies if the channel is enabled after initializing */ + bool bufferable; /**< This parameter specifies whether a write transaction can complete + without waiting for the destination to accept the write transaction data. */ +} cy_stc_dma_channel_config_t; + +/** \} group_dma_data_structures */ + + +/** +* \addtogroup group_dma_functions +* \{ +*/ + +__STATIC_INLINE void Cy_DMA_Enable (DW_Type * base); +__STATIC_INLINE void Cy_DMA_Disable (DW_Type * base); +__STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel (DW_Type const * base); +__STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type const * base); +__STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base); + + +/** +* \addtogroup group_dma_descriptor_functions +* \{ +*/ + + cy_en_dma_status_t Cy_DMA_Descriptor_Init (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_config_t const * config); + void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor); + + void Cy_DMA_Descriptor_SetNextDescriptor (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor); + void Cy_DMA_Descriptor_SetDescriptorType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType); +__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress (cy_stc_dma_descriptor_t * descriptor, void const * srcAddress); +__STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress (cy_stc_dma_descriptor_t * descriptor, void const * dstAddress); +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t xCount); +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount (cy_stc_dma_descriptor_t * descriptor, uint32_t yCount); +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement); +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement); +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement); +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement); +__STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType); +__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType); +__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType); +__STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize); +__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize); +__STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize); +__STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger); +__STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState); + + cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger (cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState (cy_stc_dma_descriptor_t const * descriptor); + +/** \} group_dma_descriptor_functions */ + + +/** +* \addtogroup group_dma_channel_functions +* \{ +*/ + + cy_en_dma_status_t Cy_DMA_Channel_Init (DW_Type * base, uint32_t channel, cy_stc_dma_channel_config_t const * channelConfig); + void Cy_DMA_Channel_DeInit (DW_Type * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor); +__STATIC_INLINE void Cy_DMA_Channel_Enable (DW_Type * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_Disable (DW_Type * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_SetPriority (DW_Type * base, uint32_t channel, uint32_t priority); +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority (DW_Type const * base, uint32_t channel); +__STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel); +__STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel); + +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus (DW_Type const * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt (DW_Type * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_SetInterrupt (DW_Type * base, uint32_t channel); +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask (DW_Type const * base, uint32_t channel); +__STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask (DW_Type * base, uint32_t channel, uint32_t interrupt); +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel); + +/** \} group_dma_channel_functions */ + + +/*************************************** +* In-line Function Implementation +***************************************/ + + +/** +* \addtogroup group_dma_block_functions +* \{ +*/ + + +/******************************************************************************* +* Function Name: Cy_DMA_Enable +****************************************************************************//** +* +* Enables the DMA block. +* +* \param base +* The pointer to the hardware DMA block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Enable(DW_Type * base) +{ + base->CTL |= DW_CTL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Disable +****************************************************************************//** +* +* Disables the DMA block. +* +* \param base +* The pointer to the hardware DMA block. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Disable(DW_Type * base) +{ + base->CTL &= (uint32_t) ~DW_CTL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_GetActiveChannel +****************************************************************************//** +* +* Returns the status of the active/pending channels. +* the DMA block. +* +* \param base +* The pointer to the hardware DMA block. +* +* \return +* Returns a bit-field with all of the currently active/pending channels in the +* DMA block. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_GetActiveChannel(DW_Type const * base) +{ + return(_FLD2VAL(DW_STATUS_CH_IDX, base->STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_GetActiveSrcAddress +****************************************************************************//** +* +* Returns the source address being used for the current transfer. +* +* \param base +* The pointer to the hardware DMA block. +* +* \return +* Returns the pointer to the source of transfer. +* +*******************************************************************************/ +__STATIC_INLINE void * Cy_DMA_GetActiveSrcAddress(DW_Type const * base) +{ + return ((void *)base->ACT_DESCR_SRC); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_GetActiveDstAddress +****************************************************************************//** +* +* Returns the destination address being used for the current transfer. +* +* \param base +* The pointer to the hardware DMA block. +* +* \return +* Returns the pointer to the destination of transfer. +* +*******************************************************************************/ +__STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base) +{ + return ((void *) base->ACT_DESCR_DST); +} + +/** \} group_dma_block_functions */ + + +/** +* \addtogroup group_dma_descriptor_functions +* \{ +*/ + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetSrcAddress +****************************************************************************//** +* +* Sets the source address parameter for the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param srcAddress +* The source address value for the descriptor. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * descriptor, void const * srcAddress) +{ + descriptor->src = (uint32_t) srcAddress; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetSrcAddress +****************************************************************************//** +* +* Returns the source address parameter of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The source address value of the descriptor. +* +*******************************************************************************/ +__STATIC_INLINE void * Cy_DMA_Descriptor_GetSrcAddress(cy_stc_dma_descriptor_t const * descriptor) +{ + return ((void *) descriptor->src); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetDstAddress +****************************************************************************//** +* +* Sets the destination address parameter for the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param dstAddress +* The destination address value for the descriptor. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * descriptor, void const * dstAddress) +{ + descriptor->dst = (uint32_t) dstAddress; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetDstAddress +****************************************************************************//** +* +* Returns the destination address parameter of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The destination address value of the descriptor. +* +*******************************************************************************/ +__STATIC_INLINE void * Cy_DMA_Descriptor_GetDstAddress(cy_stc_dma_descriptor_t const * descriptor) +{ + return ((void *) descriptor->dst); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetInterruptType +****************************************************************************//** +* +* Sets the interrupt type parameter for the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param interruptType +* The interrupt type set for the descriptor. \ref cy_en_dma_trigger_type_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t interruptType) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(interruptType)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_INTR_TYPE, interruptType); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetInterruptType +****************************************************************************//** +* +* Returns the Interrupt-Type of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The Interrupt-Type \ref cy_en_dma_trigger_type_t. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_INTR_TYPE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetTriggerInType +****************************************************************************//** +* +* Sets the Trigger-In-Type parameter for the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param triggerInType +* The Trigger In Type parameter \ref cy_en_dma_trigger_type_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerInType) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerInType)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TR_IN_TYPE, triggerInType); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetTriggerInType +****************************************************************************//** +* +* Returns the Trigger-In-Type parameter of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The Trigger-In-Type \ref cy_en_dma_trigger_type_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_IN_TYPE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetTriggerOutType +****************************************************************************//** +* +* Sets the Trigger-Out-Type parameter for the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param triggerOutType +* The Trigger-Out-Type set for the descriptor. \ref cy_en_dma_trigger_type_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_trigger_type_t triggerOutType) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerOutType)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TR_OUT_TYPE, triggerOutType); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetTriggerOutType +****************************************************************************//** +* +* Returns the Trigger-Out-Type parameter of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The Trigger-Out-Type parameter \ref cy_en_dma_trigger_type_t. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_OUT_TYPE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetDataSize +****************************************************************************//** +* +* Sets the Data Element Size parameter for the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param dataSize +* The Data Element Size \ref cy_en_dma_data_size_t +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(dataSize)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_DATA_SIZE, dataSize); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetDataSize +****************************************************************************//** +* +* Returns the Data Element Size parameter of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The Data Element Size \ref cy_en_dma_data_size_t. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_data_size_t) _FLD2VAL(CY_DMA_CTL_DATA_SIZE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetSrcTransferSize +****************************************************************************//** +* +* Sets the Source Transfer Size parameter for the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param srcTransferSize +* The Source Transfer Size \ref cy_en_dma_transfer_size_t. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t srcTransferSize) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(srcTransferSize)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_SRC_SIZE, srcTransferSize); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetSrcTransferSize +****************************************************************************//** +* +* Returns the Source Transfer Size parameter of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The Source Transfer Size \ref cy_en_dma_transfer_size_t. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_SRC_SIZE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetDstTransferSize +****************************************************************************//** +* +* Sets the Destination Transfer Size parameter for the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param dstTransferSize +* The Destination Transfer Size \ref cy_en_dma_transfer_size_t. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_transfer_size_t dstTransferSize) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(dstTransferSize)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_DST_SIZE, dstTransferSize); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetDstTransferSize +****************************************************************************//** +* +* Returns the Destination Transfer Size parameter of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The Destination Transfer Size \ref cy_en_dma_transfer_size_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_DST_SIZE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetRetrigger +****************************************************************************//** +* +* Sets the retrigger value which specifies whether the controller should +* wait for the input trigger to be deactivated. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param retrigger +* The \ref cy_en_dma_retrigger_t parameter specifies whether the controller +* should wait for the input trigger to be deactivated. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_retrigger_t retrigger) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_RETRIGGER_VALID(retrigger)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_RETRIG, retrigger); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetRetrigger +****************************************************************************//** +* +* Returns a value which specifies whether the controller should +* wait for the input trigger to be deactivated. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The Retrigger setting \ref cy_en_dma_retrigger_t. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_retrigger_t) _FLD2VAL(CY_DMA_CTL_RETRIG, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetDescriptorType +****************************************************************************//** +* +* Returns the descriptor's type of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The descriptor type \ref cy_en_dma_descriptor_type_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetChannelState +****************************************************************************//** +* +* Sets the channel state on completion of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param channelState +* The channel state \ref cy_en_dma_channel_state_t. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_channel_state_t channelState) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(channelState)); + + descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_CH_DISABLE, channelState); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetChannelState +****************************************************************************//** +* +* Returns the channel state on completion of the specified descriptor. +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The Channel State setting \ref cy_en_dma_channel_state_t +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + + return((cy_en_dma_channel_state_t) _FLD2VAL(CY_DMA_CTL_CH_DISABLE, descriptor->ctl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetXloopDataCount +****************************************************************************//** +* +* Sets the number of data elements to transfer in the X loop +* for the specified descriptor (for 1D or 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param xCount +* The number of data elements to transfer in the X loop. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t xCount) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(xCount)); + /* Convert the data count from the user's range (1-256) into the machine range (0-255). */ + descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_COUNT, xCount - 1UL); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetXloopDataCount +****************************************************************************//** +* +* Returns the number of data elements for the X loop of the specified +* descriptor (for 1D or 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The number of data elements to transfer in the X loop. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + /* Convert the data count from the machine range (0-255) into the user's range (1-256). */ + return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->xCtl) + 1UL); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetXloopSrcIncrement +****************************************************************************//** +* +* Sets the source increment parameter for the X loop of the specified +* descriptor (for 1D or 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param srcXincrement +* The value of the source increment. The valid range is -2048 ... 2047. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcXincrement) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(srcXincrement)); + + descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_SRC_INCR, srcXincrement); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetXloopSrcIncrement +****************************************************************************//** +* +* Returns the source increment parameter for the X loop of the specified +* descriptor (for 1D or 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The value of the source increment. +* +*******************************************************************************/ +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + + return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->xCtl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetXloopDstIncrement +****************************************************************************//** +* +* Sets the destination increment parameter for the X loop for the specified +* descriptor (for 1D or 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param dstXincrement +* The value of the destination increment. The valid range is -2048 ... 2047. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(dstXincrement)); + + descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_DST_INCR, dstXincrement); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetXloopDstIncrement +****************************************************************************//** +* +* Returns the destination increment parameter for the X loop of the specified +* descriptor (for 1D or 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The value of the destination increment. +* +*******************************************************************************/ +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + + return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->xCtl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetYloopDataCount +****************************************************************************//** +* +* Sets the number of data elements for the Y loop of the specified descriptor +* (for 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param yCount +* The number of X loops to execute in the Y loop. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t yCount) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(yCount)); + /* Convert the data count from the user's range (1-256) into the machine range (0-255). */ + descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_COUNT, yCount - 1UL); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetYloopDataCount +****************************************************************************//** +* +* Returns the number of X loops to execute in the Y loop of the specified +* descriptor (for 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The number of X loops to execute in the Y loop. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + /* Convert the data count from the machine range (0-255) into the user's range (1-256). */ + return (_FLD2VAL(CY_DMA_CTL_COUNT, descriptor->yCtl) + 1UL); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetYloopSrcIncrement +****************************************************************************//** +* +* Sets the source increment parameter for the Y loop for the specified +* descriptor (for 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param srcYincrement +* The value of the source increment. The valid range is -2048 ... 2047. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(srcYincrement)); + + descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_SRC_INCR, srcYincrement); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetYloopSrcIncrement +****************************************************************************//** +* +* Returns the source increment parameter for the outer Y of the specified +* descriptor (for 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The value of source increment. +* +*******************************************************************************/ +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + + return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->yCtl)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_SetYloopDstIncrement +****************************************************************************//** +* +* Sets the destination increment parameter for the Y loop of the specified +* descriptor (for 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \param dstYincrement +* The value of the destination increment. Valid range is -2048 ... 2047. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstYincrement) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(dstYincrement)); + + descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_DST_INCR, dstYincrement); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Descriptor_GetYloopDstIncrement +****************************************************************************//** +* +* Returns the destination increment parameter for the Y loop of the specified +* descriptor (for 2D descriptors only). +* +* \param descriptor +* The descriptor structure instance declared by the user/component. +* +* \return +* The value of the destination increment. +* +*******************************************************************************/ +__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(NULL != descriptor); + CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor)); + + return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->yCtl)); +} + + +/** \} group_dma_descriptor_functions */ + + +/** +* \addtogroup group_dma_channel_functions +* \{ +*/ + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_SetDescriptor +****************************************************************************//** +* +* Sets a descriptor as current for the specified DMA channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +* \param descriptor +* This is the descriptor to be associated with the channel. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t channel, cy_stc_dma_descriptor_t const * descriptor) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + CY_ASSERT_L1(NULL != descriptor); + + base->CH_STRUCT[channel].CH_CURR_PTR = (uint32_t)descriptor; + base->CH_STRUCT[channel].CH_IDX &= (uint32_t) ~(DW_CH_STRUCT_CH_IDX_X_IDX_Msk | DW_CH_STRUCT_CH_IDX_Y_IDX_Msk); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_Enable +****************************************************************************//** +* +* The function is used to enable a DMA channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + base->CH_STRUCT[channel].CH_CTL |= DW_CH_STRUCT_CH_CTL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_Disable +****************************************************************************//** +* +* The function is used to disable a DMA channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + base->CH_STRUCT[channel].CH_CTL &= (uint32_t) ~DW_CH_STRUCT_CH_CTL_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_SetPriority +****************************************************************************//** +* +* The function is used to set a priority for the DMA channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +* \param priority +* The priority to be set for the DMA channel. The allowed values are 0,1,2,3. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel, uint32_t priority) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(priority)); + + base->CH_STRUCT[channel].CH_CTL = _CLR_SET_FLD32U(base->CH_STRUCT[channel].CH_CTL, DW_CH_STRUCT_CH_CTL_PRIO, priority); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetPriority +****************************************************************************//** +* +* Returns the priority of the DMA channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +* \return +* The priority of the channel. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return ((uint32_t) _FLD2VAL(DW_CH_STRUCT_CH_CTL_PRIO, base->CH_STRUCT[channel].CH_CTL)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetCurrentDescriptor +****************************************************************************//** +* +* Returns the descriptor that is active in the channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +* \return +* The pointer to the descriptor assocaited with the channel. +* +*******************************************************************************/ +__STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return ((cy_stc_dma_descriptor_t*)(base->CH_STRUCT[channel].CH_CURR_PTR)); +} + + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetInterruptStatus +****************************************************************************//** +* +* Returns the interrupt status of the specified channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +* \return +* The status of an interrupt for the specified channel. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return (base->CH_STRUCT[channel].INTR); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetStatus +****************************************************************************//** +* +* Returns the interrupt reason of the specified channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +* \return +* The cause \ref cy_en_dma_intr_cause_t of the interrupt. +* +*******************************************************************************/ +__STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return ((cy_en_dma_intr_cause_t) _FLD2VAL(DW_CH_STRUCT_CH_STATUS_INTR_CAUSE, base->CH_STRUCT[channel].CH_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_ClearInterrupt +****************************************************************************//** +* +* Clears the interrupt status of the specified channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + base->CH_STRUCT[channel].INTR = CY_DMA_INTR_MASK; + (void) base->CH_STRUCT[channel].INTR; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_SetInterrupt +****************************************************************************//** +* +* Sets the interrupt for the specified channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + base->CH_STRUCT[channel].INTR_SET = CY_DMA_INTR_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetInterruptMask +****************************************************************************//** +* +* Returns the interrupt mask value of the specified channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +* \return +* The interrupt mask value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return (base->CH_STRUCT[channel].INTR_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_SetInterruptMask +****************************************************************************//** +* +* Sets an interrupt mask value for the specified channel. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +* \param interrupt +* The interrupt mask: +* CY_DMA_INTR_MASK to enable the interrupt or 0UL to disable the interrupt. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t channel, uint32_t interrupt) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + CY_ASSERT_L2(CY_DMA_IS_INTR_MASK_VALID(interrupt)); + base->CH_STRUCT[channel].INTR_MASK = interrupt; +} + + +/******************************************************************************* +* Function Name: Cy_DMA_Channel_GetInterruptStatusMasked +****************************************************************************//** +* +* Returns the logical AND of the corresponding INTR and INTR_MASK fields +* in a single-load operation. +* +* \param base +* The pointer to the hardware DMA block. +* +* \param channel +* The channel number. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel) +{ + CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel)); + + return (base->CH_STRUCT[channel].INTR_MASKED); +} + +/** \} group_dma_channel_functions */ + +/** \} group_dma_functions */ + + +/** \cond The definitions to support the backward compatibility, do not use them in new designs */ + +#if(CY_DMA_BWC) + + /* Type definitions */ + #define cy_stc_dma_chnl_config_t cy_stc_dma_channel_config_t + #define cy_stc_dma_descr_t cy_stc_dma_descriptor_t + #define cy_stc_dma_descr_config_t cy_stc_dma_descriptor_config_t + #define cy_en_dma_trig_type_t cy_en_dma_trigger_type_t + + /* Structure items */ + #define DMA_Descriptor descriptor + #define deact retrigger + #define intrType interruptType + #define chStateAtCmplt channelState + #define srcTxfrSize srcTransferSize + #define destTxfrSize dstTransferSize + #define trigoutType triggerOutType + #define triginType triggerInType + #define descrType descriptorType + #define srcAddr srcAddress + #define destAddr dstAddress + #define srcXincr srcXincrement + #define srcYincr srcYincrement + #define destXincr dstXincrement + #define destYincr dstYincrement + #define descrNext nextDescriptor + + /* Constants */ + #define CY_DMA_CH_DISABLED (CY_DMA_CHANNEL_DISABLED) + #define CY_DMA_CH_ENABLED (CY_DMA_CHANNEL_ENABLED) + + #define CY_DMA_TXFR_SIZE_DATA_SIZE (CY_DMA_TRANSFER_SIZE_DATA) + #define CY_DMA_TXFR_SIZE_WORD (CY_DMA_TRANSFER_SIZE_WORD) + + #define CY_DMA_INTR_1ELEMENT_CMPLT (CY_DMA_1ELEMENT) + #define CY_DMA_INTR_X_LOOP_CMPLT (CY_DMA_X_LOOP) + #define CY_DMA_INTR_DESCR_CMPLT (CY_DMA_DESCR) + #define CY_DMA_INTR_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN) + + #define CY_DMA_TRIGOUT_1ELEMENT_CMPLT (CY_DMA_1ELEMENT) + #define CY_DMA_TRIGOUT_X_LOOP_CMPLT (CY_DMA_X_LOOP) + #define CY_DMA_TRIGOUT_DESCR_CMPLT (CY_DMA_DESCR) + #define CY_DMA_TRIGOUT_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN) + + #define CY_DMA_TRIGIN_1ELEMENT (CY_DMA_1ELEMENT) + #define CY_DMA_TRIGIN_XLOOP (CY_DMA_X_LOOP) + #define CY_DMA_TRIGIN_DESCR (CY_DMA_DESCR) + #define CY_DMA_TRIGIN_DESCRCHAIN (CY_DMA_DESCR_CHAIN) + + #define CY_DMA_INVALID_INPUT_PARAMETERS (CY_DMA_BAD_PARAM) + + #define CY_DMA_RETDIG_IM (CY_DMA_RETRIG_IM) + #define CY_DMA_RETDIG_4CYC (CY_DMA_RETRIG_4CYC) + #define CY_DMA_RETDIG_16CYC (CY_DMA_RETRIG_16CYC) + + /* Descriptor structure items */ + #define DESCR_CTL ctl + #define DESCR_SRC src + #define DESCR_DST dst + #define DESCR_X_CTL xCtl + #define DESCR_Y_CTL yCtl + #define DESCR_NEXT_PTR nextPtr + + /* Descriptor structure bit-fields */ + #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL + #define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL + #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Pos 2UL + #define DW_DESCR_STRUCT_DESCR_CTL_INTR_TYPE_Msk 0xCUL + #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Pos 4UL + #define DW_DESCR_STRUCT_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL + #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Pos 6UL + #define DW_DESCR_STRUCT_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL + #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Pos 24UL + #define DW_DESCR_STRUCT_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL + #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL + #define DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL + #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL + #define DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL + #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Pos 28UL + #define DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk 0x30000000UL + #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Pos 30UL + #define DW_DESCR_STRUCT_DESCR_CTL_DESCR_TYPE_Msk 0xC0000000UL + #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Pos 0UL + #define DW_DESCR_STRUCT_DESCR_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL + #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Pos 0UL + #define DW_DESCR_STRUCT_DESCR_DST_DST_ADDR_Msk 0xFFFFFFFFUL + #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Pos 0UL + #define DW_DESCR_STRUCT_DESCR_X_CTL_SRC_X_INCR_Msk 0xFFFUL + #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Pos 12UL + #define DW_DESCR_STRUCT_DESCR_X_CTL_DST_X_INCR_Msk 0xFFF000UL + #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Pos 24UL + #define DW_DESCR_STRUCT_DESCR_X_CTL_X_COUNT_Msk 0xFF000000UL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Pos 0UL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_SRC_Y_INCR_Msk 0xFFFUL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Pos 12UL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_DST_Y_INCR_Msk 0xFFF000UL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Pos 24UL + #define DW_DESCR_STRUCT_DESCR_Y_CTL_Y_COUNT_Msk 0xFF000000UL + #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Pos 2UL + #define DW_DESCR_STRUCT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL + + /* Functions */ + #define Cy_DMA_GetActiveChnl Cy_DMA_GetActiveChannel + #define Cy_DMA_GetActiveSrcAddr Cy_DMA_GetActiveSrcAddress + #define Cy_DMA_GetActiveDstAddr Cy_DMA_GetActiveDstAddress + #define Cy_DMA_Descr_Init Cy_DMA_Descriptor_Init + #define Cy_DMA_Descr_DeInit Cy_DMA_Descriptor_DeInit + #define Cy_DMA_Descr_SetSrcAddr Cy_DMA_Descriptor_SetSrcAddress + #define Cy_DMA_Descr_SetDestAddr Cy_DMA_Descriptor_SetDstAddress + #define Cy_DMA_Descr_SetNxtDescr Cy_DMA_Descriptor_SetNextDescriptor + #define Cy_DMA_Descr_SetIntrType Cy_DMA_Descriptor_SetInterruptType + #define Cy_DMA_Descr_SetTrigInType Cy_DMA_Descriptor_SetTriggerInType + #define Cy_DMA_Descr_SetTrigOutType Cy_DMA_Descriptor_SetTriggerOutType + #define Cy_DMA_Chnl_Init Cy_DMA_Channel_Init + #define Cy_DMA_Chnl_DeInit Cy_DMA_Channel_DeInit + #define Cy_DMA_Chnl_SetDescr Cy_DMA_Channel_SetDescriptor + #define Cy_DMA_Chnl_Enable Cy_DMA_Channel_Enable + #define Cy_DMA_Chnl_Disable Cy_DMA_Channel_Disable + #define Cy_DMA_Chnl_GetCurrentDescr Cy_DMA_Channel_GetCurrentDescriptor + #define Cy_DMA_Chnl_SetPriority Cy_DMA_Channel_SetPriority + #define Cy_DMA_Chnl_GetPriority Cy_DMA_Channel_GetPriority + #define Cy_DMA_Chnl_GetInterruptStatus Cy_DMA_Channel_GetInterruptStatus + #define Cy_DMA_Chnl_GetInterruptCause Cy_DMA_Channel_GetStatus + #define Cy_DMA_Chnl_ClearInterrupt Cy_DMA_Channel_ClearInterrupt + #define Cy_DMA_Chnl_SetInterrupt Cy_DMA_Channel_SetInterrupt + #define Cy_DMA_Chnl_GetInterruptMask Cy_DMA_Channel_GetInterruptMask + #define Cy_DMA_Chnl_GetInterruptStatusMasked Cy_DMA_Channel_GetInterruptStatusMasked + #define Cy_DMA_Chnl_SetInterruptMask(base, channel) (Cy_DMA_Channel_SetInterruptMask(base, channel, CY_DMA_INTR_MASK)) + + +/******************************************************************************* +* Function Name: Cy_DMA_Descr_SetTxfrWidth +****************************************************************************//** +* This is a legacy API function, it is left here just for the backward compatibility +* Do not use it in new designs. +*******************************************************************************/ + __STATIC_INLINE void Cy_DMA_Descr_SetTxfrWidth(cy_stc_dma_descr_t * descriptor, + uint32_t dataElementSize, + uint32_t srcTxfrWidth, + uint32_t dstTxfrWidth) + { + uint32_t regValue; + regValue = descriptor->ctl & ((uint32_t)(~(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk | + DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE_Msk | + DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE_Msk))); + + descriptor->ctl = regValue | + _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE, dataElementSize) | + _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_SRC_TRANSFER_SIZE, srcTxfrWidth) | + _VAL2FLD(DW_DESCR_STRUCT_DESCR_CTL_DST_TRANSFER_SIZE, dstTxfrWidth); + } + +#endif /* CY_DMA_BWC */ + +/** \endcond */ + + +#if defined(__cplusplus) +} +#endif + +#endif /* (CY_DMA_H) */ + +/** \} group_dma */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.c new file mode 100644 index 0000000000..0892255e78 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.c @@ -0,0 +1,225 @@ +/***************************************************************************//** +* \file cy_efuse.c +* \version 1.0 +* +* \brief +* Provides API implementation of the eFuse driver. +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "cy_efuse.h" +#include "ipc/cy_ipc_drv.h" + +/** \cond INTERNAL */ +#define CY_EFUSE_OPCODE_SUCCESS (0xA0000000UL) /**< The command completed with no errors */ +#define CY_EFUSE_OPCODE_STS_Msk (0xF0000000UL) /**< The status mask of the SROM API return value */ +#define CY_EFUSE_OPCODE_INV_PROT (0xF0000001UL) /**< The API is not available in the current protection state */ +#define CY_EFUSE_OPCODE_INV_ADDR (0xF0000002UL) /**< An attempt to read byte from the out-of-bond or protected eFuse region */ +#define CY_EFUSE_OPCODE_READ_FUSE_BYTE (0x03000000UL) /**< The SROM API opcode for Read fuse byte operation */ +#define CY_EFUSE_OPCODE_OFFSET_Pos (8UL) /**< A fuse byte offset position in an opcode */ +#define CY_EFUSE_OPCODE_DATA_Msk (0xFFUL) /**< The mask for extracting data from the SROM API return value */ +#define CY_EFUSE_IPC_STRUCT (Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) /**< IPC structure to be used */ +#define CY_EFUSE_IPC_NOTIFY_STRUCT0 (0x1UL << CY_IPC_INTR_SYSCALL1) /**< IPC notify bit for IPC_STRUCT0 (dedicated to System Call) */ +/** \endcond */ + +static volatile uint32_t opcode; + +static cy_en_efuse_status_t ProcessOpcode(void); + +/******************************************************************************* +* Function Name: Cy_EFUSE_GetEfuseBit +****************************************************************************//** +* +* Reports the current state of a given eFuse bit-number. Consult the device TRM +* to determine the target fuse bit number. +* +* \note An attempt to read an eFuse data from a protected memory region +* will generate a HardFault. +* +* \param bitNum +* The number of the bit to read. The valid range of the bit number is +* from 0 to EFUSE_EFUSE_NR * 32 * 8 - 1 where: +* - EFUSE_EFUSE_NR is number of efuse macros in the selected device series, +* - 32 is a number of fuse bytes in one efuse macro, +* - 8 is a number of fuse bits in the byte. +* +* The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g +* \e \/devices/psoc6/psoc63/include/psoc63_config.\e h +* +* \param bitVal +* The pointer to the location to store the bit value. +* +* \return +* \ref cy_en_efuse_status_t +* +* \funcusage +* The example below shows how to read device life-cycle register bits in +* PSoC 6: +* \snippet eFuse_v1_0_sut_00.cydsn/main_cm0p.c SNIPPET_EFUSE_READ_BIT +* +*******************************************************************************/ +cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal) +{ + cy_en_efuse_status_t result = CY_EFUSE_BAD_PARAM; + + if (bitVal != NULL) + { + uint32_t offset = bitNum / CY_EFUSE_BITS_PER_BYTE; + uint8_t byteVal; + *bitVal = false; + + /* Read the eFuse byte */ + result = Cy_EFUSE_GetEfuseByte(offset, &byteVal); + + if (result == CY_EFUSE_SUCCESS) + { + uint32_t bitPos = bitNum % CY_EFUSE_BITS_PER_BYTE; + /* Extract the bit from the byte */ + *bitVal = (((byteVal >> bitPos) & 0x01U) != 0U); + } + } + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_EFUSE_GetEfuseByte +****************************************************************************//** +* +* Reports the current state of the eFuse byte. +* If the offset parameter is beyond the available quantities, +* zeroes will be stored to the byteVal parameter. Consult the device TRM +* to determine the target fuse byte offset. +* +* \note An attempt to read an eFuse data from a protected memory region +* will generate a HardFault. +* +* \param offset +* The offset of the byte to read. The valid range of the byte offset is +* from 0 to EFUSE_EFUSE_NR * 32 - 1 where: +* - EFUSE_EFUSE_NR is a number of efuse macros in the selected device series, +* - 32 is a number of fuse bytes in one efuse macro. +* +* The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g +* \e \/devices/psoc6/psoc63/include/psoc63_config.\e h +* +* \param byteVal +* The pointer to the location to store eFuse data. +* +* \return +* \ref cy_en_efuse_status_t +* +* \funcusage +* The example below shows how to read a device life-cycle stage register in +* PSoC 6: +* \snippet eFuse_v1_0_sut_00.cydsn/main_cm0p.c SNIPPET_EFUSE_READ_LIFECYCLE +* +*******************************************************************************/ +cy_en_efuse_status_t Cy_EFUSE_GetEfuseByte(uint32_t offset, uint8_t *byteVal) +{ + cy_en_efuse_status_t result = CY_EFUSE_BAD_PARAM; + + if (byteVal != NULL) + { + /* Prepare opcode before calling the SROM API */ + opcode = CY_EFUSE_OPCODE_READ_FUSE_BYTE | (offset << CY_EFUSE_OPCODE_OFFSET_Pos); + + /* Send the IPC message */ + if (Cy_IPC_Drv_SendMsgPtr(CY_EFUSE_IPC_STRUCT, CY_EFUSE_IPC_NOTIFY_STRUCT0, (void*)&opcode) == CY_IPC_DRV_SUCCESS) + { + /* Wait until the IPC structure is locked */ + while(Cy_IPC_Drv_IsLockAcquired(CY_EFUSE_IPC_STRUCT) != false) + { + } + + /* The result of the SROM API call is returned to the opcode variable */ + if ((opcode & CY_EFUSE_OPCODE_STS_Msk) == CY_EFUSE_OPCODE_SUCCESS) + { + *byteVal = (uint8_t)(opcode & CY_EFUSE_OPCODE_DATA_Msk); + result = CY_EFUSE_SUCCESS; + } + else + { + result = ProcessOpcode(); + *byteVal = 0U; + } + } + else + { + result = CY_EFUSE_IPC_BUSY; + } + } + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_EFUSE_GetExternalStatus +****************************************************************************//** +* +* This function handles the case where a module such as a security image captures +* a system call from this driver and reports its own status or error code, +* for example, protection violation. In that case, a function from this +* driver returns an unknown error (see \ref cy_en_efuse_status_t). After receipt +* of an unknown error, the user may call this function to get the status +* of the capturing module. +* +* The user is responsible for parsing the content of the returned value +* and casting it to the appropriate enumeration. +* +* \return +* The error code of the previous efuse operation. +* +*******************************************************************************/ +uint32_t Cy_EFUSE_GetExternalStatus(void) +{ + return (opcode); +} + + +/******************************************************************************* +* Function Name: ProcessOpcode +****************************************************************************//** +* +* Converts System Call returns to the eFuse driver return defines. If +* an unknown error was returned, the error code can be accessed via the +* Cy_EFUSE_GetExternalStatus() function. +* +* \param opcode The value returned by a System Call. +* +* \return +* \ref cy_en_efuse_status_t +* +*******************************************************************************/ +static cy_en_efuse_status_t ProcessOpcode(void) +{ + cy_en_efuse_status_t result; + + switch(opcode) + { + case CY_EFUSE_OPCODE_INV_PROT : + { + result = CY_EFUSE_INVALID_PROTECTION; + break; + } + case CY_EFUSE_OPCODE_INV_ADDR : + { + result = CY_EFUSE_INVALID_FUSE_ADDR; + break; + } + default : + { + result = CY_EFUSE_ERR_UNC; + break; + } + } + + return (result); +} + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.h new file mode 100644 index 0000000000..4c8a12763a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.h @@ -0,0 +1,178 @@ +/***************************************************************************//** +* \file cy_efuse.h +* \version 1.0 +* +* Provides the API declarations of the eFuse driver. +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#if !defined(CY_EFUSE_H) +#define CY_EFUSE_H + +/** +* \defgroup group_efuse Electronic Fuses (eFuse) +* \{ +* +* Electronic Fuses (eFuses) - non-volatile memory whose +* each bit is one-time programmable (OTP). One eFuse macro consists of +* 256 bits (32 * 8). The PSoC devices have up to 16 eFuse macros; consult the +* device-specific datasheet to determine how many macros for a particular device. +* These are implemented as a regular Advanced High-performance Bus (AHB) +* peripheral with the following characteristics: +* - eFuses are used to control the device life-cycle stage (NORMAL, SECURE, +* and SECURE_WITH_DEBUG) and the protection settings; +* - eFuse memory can be programmed (eFuse bit value changed from '0' to '1') +* only once; if an eFuse bit is blown, it cannot be cleared again; +* - programming fuses requires the associated I/O supply to be at a specific +* level: the VDDIO0 (or VDDIO if only one VDDIO is present in the package) +* supply of the device should be set to 2.5 V (±5%); +* - fuses are programmed via the PSoC Programmer tool that parses the hex file +* and extracts the necessary information; the fuse data must be located at the +* dedicated section in the hex file. For more details see +* [PSoC 6 Programming Specifications](http://www.cypress.com/documentation/programming-specifications/psoc-6-programming-specifications) +* +* \section group_efuse_configuration Configuration Considerations +* +* Efuse memory can have different organization depending on the selected device. +* Consult the device TRM to determine the efuse memory organization and +* registers bitmap on the selected device. +* +* To read fuse data use the driver [functions] (\ref group_efuse_functions). +* +* To blow fuses, define a data structure of \ref cy_stc_efuse_data_t type in the +* firmware. The structure must be placed in the special memory section, for +* this use a compiler attribute. +* Each byte in the structure corresponds to the one fuse bit in the +* device. It allows the PSoC Programmer tool to distinguish bytes that are +* being set from bytes we don't care about or with unknown values. Fill the +* structure with the following values: +* - 0x00 - Not blown; +* - 0x01 - Blown; +* - 0xFF - Ignore. +* +* After the structure is defined and the values are set, build the project and +* download the firmware. To blow fuses, the firmware must be downloaded by the +* PSoC Programmer tool. Before you download firmware, ensure that the +* conditions from the PSoC 6 Programming Specification are met. +* +* The code below shows an example of the efuse data structure +* definition to blow SECURE bit of the life-cycle stage register. +* The bits to blow are set to the EFUSE_STATE_SET value. +* \snippet eFuse_v1_0_sut_00.cydsn/main_cm0p.c SNIPPET_EFUSE_DATA_STC +* +* \section group_efuse_more_information More Information +* +* Refer to the technical reference manual (TRM) and the device datasheet. +* +* \section group_efuse_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
11.5RDangerous pointer cast results in loss of volatile qualification.The removal of the volatile qualification inside the function has no +* side effects.
+* +* \section group_efuse_changelog Changelog +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.0Initial version
+* +* \defgroup group_efuse_macros Macros +* \defgroup group_efuse_functions Functions +* \defgroup group_efuse_data_structures Data Structures +* \defgroup group_efuse_enumerated_types Enumerated Types +*/ + +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" + +/*************************************** +* Macro Definitions +***************************************/ +/** +* \addtogroup group_efuse_macros +* \{ +*/ + +/** The driver major version */ +#define CY_EFUSE_DRV_VERSION_MAJOR 1 +/** The driver minor version */ +#define CY_EFUSE_DRV_VERSION_MINOR 0 +/** The eFuse driver identifier */ +#define CY_EFUSE_ID (CY_PDL_DRV_ID(0x1AUL)) +/** The number of bits in the byte */ +#define CY_EFUSE_BITS_PER_BYTE (8UL) +/** \} group_efuse_macros */ + +/*************************************** +* Enumerated Types +***************************************/ +/** +* \addtogroup group_efuse_enumerated_types +* \{ +*/ +/** This enum has the return values of the eFuse driver */ +typedef enum +{ + CY_EFUSE_SUCCESS = 0x00UL, /**< Success */ + CY_EFUSE_INVALID_PROTECTION = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< Invalid access in the current protection state */ + CY_EFUSE_INVALID_FUSE_ADDR = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< Invalid eFuse address */ + CY_EFUSE_BAD_PARAM = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x03UL, /**< One or more invalid parameters */ + CY_EFUSE_IPC_BUSY = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x04UL, /**< The IPC structure is already locked by another process */ + CY_EFUSE_ERR_UNC = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0xFFUL /**< Unknown error code. See Cy_EFUSE_GetExternalStatus() */ +} cy_en_efuse_status_t; + +/** \} group_efuse_data_structure */ + +#if defined(__cplusplus) +extern "C" { +#endif +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_efuse_functions +* \{ +*/ +cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal); +cy_en_efuse_status_t Cy_EFUSE_GetEfuseByte(uint32_t offset, uint8_t *byteVal); +uint32_t Cy_EFUSE_GetExternalStatus(void); +/** \} group_efuse_functions */ + +#if defined(__cplusplus) +} +#endif + + +#endif /* #if !defined(CY_EFUSE_H) */ + +/** \} group_efuse */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/flash/cy_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/flash/cy_flash.c new file mode 100644 index 0000000000..84434d6ded --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/flash/cy_flash.c @@ -0,0 +1,1271 @@ +/***************************************************************************//** +* \file cy_flash.c +* \version 3.0 +* +* \brief +* Provides the public functions for the API for the PSoC 6 Flash Driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "flash/cy_flash.h" +#include "sysclk/cy_sysclk.h" +#include "sysint/cy_sysint.h" +#include "ipc/cy_ipc_drv.h" +#include "ipc/cy_ipc_sema.h" +#include "ipc/cy_ipc_pipe.h" + +/*************************************** +* Data Structure definitions +***************************************/ + +/* Flash driver context */ +typedef struct +{ + uint32_t opcode; /**< Specifies the code of flash operation */ + uint32_t arg1; /**< Specifies the configuration of flash operation */ + uint32_t arg2; /**< Specifies the configuration of flash operation */ + uint32_t arg3; /**< Specifies the configuration of flash operation */ +} cy_stc_flash_context_t; + + +/*************************************** +* Macro definitions +***************************************/ + +/** \cond INTERNAL */ +/** Set SROM API in blocking mode */ +#define CY_FLASH_BLOCKING_MODE ((0x01UL) << 8UL) +/** Set SROM API in non blocking mode */ +#define CY_FLASH_NON_BLOCKING_MODE (0UL) + +/** SROM API flash region ID shift for flash row information */ +#define CY_FLASH_REGION_ID_SHIFT (16U) +#define CY_FLASH_REGION_ID_MASK (3U) +#define CY_FLASH_ROW_ID_MASK (0xFFFFU) +/** SROM API flash region IDs */ +#define CY_FLASH_REGION_ID_MAIN (0UL) +#define CY_FLASH_REGION_ID_EM_EEPROM (1UL) +#define CY_FLASH_REGION_ID_SFLASH (2UL) + +/** SROM API opcode mask */ +#define CY_FLASH_OPCODE_Msk ((0xFFUL) << 24UL) +/** SROM API opcode for flash write operation */ +#define CY_FLASH_OPCODE_WRITE_ROW ((0x05UL) << 24UL) +/** SROM API opcode for flash program operation */ +#define CY_FLASH_OPCODE_PROGRAM_ROW ((0x06UL) << 24UL) +/** SROM API opcode for row erase operation */ +#define CY_FLASH_OPCODE_ERASE_ROW ((0x1CUL) << 24UL) +/** SROM API opcode for flash checksum operation */ +#define CY_FLASH_OPCODE_CHECKSUM ((0x0BUL) << 24UL) +/** SROM API opcode for flash hash operation */ +#define CY_FLASH_OPCODE_HASH ((0x0DUL) << 24UL) +/** SROM API flash row shift for flash checksum operation */ +#define CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT (8UL) +/** SROM API flash row shift for flash checksum operation */ +#define CY_FLASH_OPCODE_CHECKSUM_REGION_SHIFT (22UL) +/** SROM API flash data size parameter for flash write operation */ +#define CY_FLASH_CONFIG_DATASIZE (CPUSS_FLASHC_PA_SIZE_LOG2 - 1UL) +/** Data to be programmed to flash is located in SRAM memory region */ +#define CY_FLASH_DATA_LOC_SRAM (0x100UL) +/** SROM API flash verification option for flash write operation */ +#define CY_FLASH_CONFIG_VERIFICATION_EN ((0x01UL) << 16u) + +/** Command completed with no errors */ +#define CY_FLASH_ROMCODE_SUCCESS (0xA0000000UL) +/** Invalid device protection state */ +#define CY_FLASH_ROMCODE_INVALID_PROTECTION (0xF0000001UL) +/** Invalid flash page latch address */ +#define CY_FLASH_ROMCODE_INVALID_FM_PL (0xF0000003UL) +/** Invalid flash address */ +#define CY_FLASH_ROMCODE_INVALID_FLASH_ADDR (0xF0000004UL) +/** Row is write protected */ +#define CY_FLASH_ROMCODE_ROW_PROTECTED (0xF0000005UL) +/** Comparison between Page Latches and FM row failed */ +#define CY_FLASH_ROMCODE_PL_ROW_COMP_FA (0xF0000022UL) +/** Command in progress; no error */ +#define CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR (0xA0000009UL) +/** Flash operation is successfully initiated */ +#define CY_FLASH_IS_OPERATION_STARTED (0x00000010UL) +/** Flash is under operation */ +#define CY_FLASH_IS_BUSY (0x00000040UL) +/** IPC structure is already locked by another process */ +#define CY_FLASH_IS_IPC_BUSY (0x00000080UL) +/** Input parameters passed to Flash API are not valid */ +#define CY_FLASH_IS_INVALID_INPUT_PARAMETERS (0x00000100UL) + +/** Result mask */ +#define CY_FLASH_RESULT_MASK (0x0FFFFFFFUL) +/** Error shift */ +#define CY_FLASH_ERROR_SHIFT (28UL) +/** No error */ +#define CY_FLASH_ERROR_NO_ERROR (0xAUL) + +/** CM4 Flash Proxy address */ +#define CY_FLASH_CM4_FLASH_PROXY_ADDR (*(Cy_Flash_Proxy *)(0x00000D1CUL)) +typedef cy_en_flashdrv_status_t (*Cy_Flash_Proxy)(cy_stc_flash_context_t *context); + +/** IPC notify bit for IPC_STRUCT0 (dedicated to flash operation) */ +#define CY_FLASH_IPC_NOTIFY_STRUCT0 (0x1UL << CY_IPC_INTR_SYSCALL1) + +/** Disable delay */ +#define CY_FLASH_NO_DELAY (0U) + +#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) + /** Number of ticks to wait 1 uS */ + #define CY_FLASH_TICKS_FOR_1US (8U) + /** Slow control register */ + #define CY_FLASH_TST_DDFT_SLOW_CTL_REG (*(reg32 *) 0x40260108U) + /** Slow control register */ + #define CY_FLASH_TST_DDFT_FAST_CTL_REG (*(reg32 *) 0x40260104U) + /** Define to set the IMO to perform a delay after the flash operation started */ + #define CY_FLASH_TST_DDFT_SLOW_CTL_MASK (0x00001F1EUL) + /** Fast control register */ + #define CY_FLASH_TST_DDFT_FAST_CTL_MASK (62U) + /** Slow output register - output disabled */ + #define CY_FLASH_CLK_OUTPUT_DISABLED (0U) + + /* The default delay time value */ + #define CY_FLASH_DEFAULT_DELAY (150UL) + /* Calculates the time in microseconds to wait for the number of the CM0P ticks */ + #define CY_FLASH_DELAY_CORRECTIVE(ticks) ((((uint32)Cy_SysClk_ClkPeriGetDivider() + 1UL) * \ + (Cy_SysClk_ClkSlowGetDivider() + 1UL) * (ticks) * 1000UL)\ + / ((uint32_t)cy_Hfclk0FreqHz / 1000UL)) + + /* Number of the CM0P ticks for StartProgram function delay corrective time */ + #define CY_FLASH_START_PROGRAM_DELAY_TICKS (6000UL) + /* Delay time for StartProgram function in us */ + #define CY_FLASH_START_PROGRAM_DELAY_TIME (900UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_DELAY_TICKS)) + /* Number of the CM0P ticks for StartErase function delay corrective time */ + #define CY_FLASH_START_ERASE_DELAY_TICKS (9500UL) + /* Delay time for StartErase function in us */ + #define CY_FLASH_START_ERASE_DELAY_TIME (2200UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_ERASE_DELAY_TICKS)) + /* Number of the CM0P ticks for StartWrite function delay corrective time */ + #define CY_FLASH_START_WRITE_DELAY_TICKS (19000UL) + /* Delay time for StartWrite function in us */ + #define CY_FLASH_START_WRITE_DELAY_TIME (9800UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_WRITE_DELAY_TICKS)) + + /** Delay time for Start Write function in us with corrective time */ + #define CY_FLASH_START_WRITE_DELAY (CY_FLASH_START_WRITE_DELAY_TIME) + /** Delay time for Start Program function in us with corrective time */ + #define CY_FLASH_START_PROGRAM_DELAY (CY_FLASH_START_PROGRAM_DELAY_TIME) + /** Delay time for Start Erase function in uS with corrective time */ + #define CY_FLASH_START_ERASE_DELAY (CY_FLASH_START_ERASE_DELAY_TIME) + + #define CY_FLASH_ENTER_WAIT_LOOP (0xFFU) + #define CY_FLASH_IPC_CLIENT_ID (2U) + + /** Semaphore number reserved for flash driver */ + #define CY_FLASH_WAIT_SEMA (0UL) + /* Semaphore check timeout (in tries) */ + #define CY_FLASH_SEMA_WAIT_MAX_TRIES (150000UL) + + typedef struct + { + uint8_t clientID; + uint8_t pktType; + uint16_t intrRelMask; + } cy_flash_notify_t; + + static void Cy_Flash_NotifyHandler(uint32_t * msgPtr); + static void Cy_Flash_RAMDelay(uint32_t microseconds); + + #if (CY_CPU_CORTEX_M0P) + #define IS_CY_PIPE_FREE(...) (!Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP1))) + #define NOTIFY_PEER_CORE(a) Cy_IPC_Pipe_SendMessage(CY_IPC_EP_CYPIPE_CM4_ADDR, CY_IPC_EP_CYPIPE_CM0_ADDR, (a), NULL) + #else + #define IS_CY_PIPE_FREE(...) (!Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP0))) + #define NOTIFY_PEER_CORE(a) Cy_IPC_Pipe_SendMessage(CY_IPC_EP_CYPIPE_CM0_ADDR, CY_IPC_EP_CYPIPE_CM4_ADDR, (a), NULL) + #endif + + #if (CY_CPU_CORTEX_M4) + static void Cy_Flash_ResumeIrqHandler(void); + #endif +#else /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ + /** Delay time for Start Write function in us with corrective time */ + #define CY_FLASH_START_WRITE_DELAY (CY_FLASH_NO_DELAY) + /** Delay time for Start Program function in us with corrective time */ + #define CY_FLASH_START_PROGRAM_DELAY (CY_FLASH_NO_DELAY) + /** Delay time fot Start Erase function in uS with corrective time */ + #define CY_FLASH_START_ERASE_DELAY (CY_FLASH_NO_DELAY) +#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ +/** \endcond */ + + +/* Static functions */ +static bool Cy_Flash_BoundsCheck(uint32_t flashAddr); +static uint32_t Cy_Flash_GetRowNum(uint32_t flashAddr); +static cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode); +static cy_en_flashdrv_status_t Cy_Flash_OperationStatus(void); +static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microseconds); + +static volatile cy_stc_flash_context_t flashContext; + +#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) + /******************************************************************************* + * Function Name: Cy_Flash_NotifyHandler + ****************************************************************************//** + * + * This is the interrupt service routine for the pipe notifications. + * + *******************************************************************************/ + typedef struct + { + uint32_t maxSema; /* Maximum semaphores in system */ + uint32_t *arrayPtr; /* Pointer to semaphores array */ + } cy_stc_ipc_sema_t; + + #if defined (__ICCARM__) + #pragma diag_suppress=Ta023 + __ramfunc + #else + CY_SECTION(".cy_ramfunc") + #endif + static void Cy_Flash_NotifyHandler(uint32_t * msgPtr) + { + uint32_t intr; + static uint32_t semaIndex; + static uint32_t semaMask; + static volatile uint32_t *semaPtr; + static cy_stc_ipc_sema_t *semaStruct; + + cy_flash_notify_t *ipcMsgPtr = (cy_flash_notify_t *)msgPtr; + + if (CY_FLASH_ENTER_WAIT_LOOP == ipcMsgPtr->pktType) + { + intr = Cy_SysLib_EnterCriticalSection(); + + /* Get pointer to structure */ + semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(Cy_IPC_Drv_GetIpcBaseAddress( CY_IPC_CHAN_SEMA)); + + /* Get the index into the semaphore array and calculate the mask */ + semaIndex = CY_FLASH_WAIT_SEMA / CY_IPC_SEMA_PER_WORD; + semaMask = (uint32_t)(1ul << (CY_FLASH_WAIT_SEMA - (semaIndex * CY_IPC_SEMA_PER_WORD) )); + semaPtr = &semaStruct->arrayPtr[semaIndex]; + + /* Notification to the Flash driver to start the current operation */ + *semaPtr |= semaMask; + + /* Check a notification from other core to end of waiting */ + while (((*semaPtr) & semaMask) != 0ul) + { + } + + Cy_SysLib_ExitCriticalSection(intr); + } + } + #if defined (__ICCARM__) + #pragma diag_default=Ta023 + #endif +#endif + +/******************************************************************************* +* Function Name: Cy_Flash_Init +****************************************************************************//** +* +* Initiates all needed prerequisites to support flash erase/write. +* Should be called from each core. +* +* Requires a call to Cy_IPC_SystemSemaInit() and Cy_IPC_SystemPipeInit() functions +* before use. +* +* This function is called in the SystemInit() function, for proper flash write +* and erase operations. If the default startup file is not used, or the function +* SystemInit() is not called in your project, call the following three functions +* prior to executing any flash or EmEEPROM write or erase operations: +* -# Cy_IPC_SystemSemaInit() +* -# Cy_IPC_SystemPipeInit() +* -# Cy_Flash_Init() +* +*******************************************************************************/ +void Cy_Flash_Init(void) +{ + #if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) + #if (CY_CPU_CORTEX_M4) + cy_stc_sysint_t flashIntConfig = + { + cpuss_interrupt_fm_IRQn, /* .intrSrc */ + 0 /* .intrPriority */ + }; + + (void)Cy_SysInt_Init(&flashIntConfig, &Cy_Flash_ResumeIrqHandler); + NVIC_EnableIRQ(flashIntConfig.intrSrc); + #endif + + (void)Cy_IPC_Pipe_RegisterCallback(CY_IPC_EP_CYPIPE_ADDR, &Cy_Flash_NotifyHandler, + (uint32_t)CY_FLASH_IPC_CLIENT_ID); + #endif +} + +/******************************************************************************* +* Function Name: Cy_Flash_SendCmd +****************************************************************************//** +* +* Sends a command to the SROM via the IPC channel. The function is placed to the +* SRAM memory to guarantee successful operation. After an IPC message is sent, +* the function waits for a defined time before exiting the function. +* +* \param mode +* Sets the blocking or non-blocking Flash operation. +* +* \param microseconds +* The number of microseconds to wait before exiting the functions +* in range 0-65535 us. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +#if defined(CY_DEVICE_PSOC6ABLE2) \ + && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) \ + && !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) + #if defined (__ICCARM__) + #pragma diag_suppress=Ta023 + __ramfunc + #else + CY_SECTION(".cy_ramfunc") + #endif +#endif +static cy_en_flashdrv_status_t Cy_Flash_SendCmd(uint32_t mode, uint32_t microseconds) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_IPC_BUSY; + IPC_STRUCT_Type *ipcBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL); + +#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) + + uint32_t semaTryCount = 0uL; + uint32_t intr; + + CY_ALIGN(4) static cy_flash_notify_t ipcWaitMessage = + { + /* .clientID */ CY_FLASH_IPC_CLIENT_ID, + /* .pktType */ CY_FLASH_ENTER_WAIT_LOOP, + /* .intrRelMask */ 0 + }; + + #if (CY_CPU_CORTEX_M0P) + bool isCM4Powered = (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status()); + + if (!isCM4Powered) + { + result = CY_FLASH_DRV_SUCCESS; + } + else + { + #endif + if (IS_CY_PIPE_FREE()) + { + if (CY_IPC_SEMA_STATUS_LOCKED != Cy_IPC_Sema_Status(CY_FLASH_WAIT_SEMA)) + { + if (CY_IPC_PIPE_SUCCESS == NOTIFY_PEER_CORE(&ipcWaitMessage)) + { + /* Wait for SEMA lock by peer core */ + while ((CY_IPC_SEMA_STATUS_LOCKED != Cy_IPC_Sema_Status(CY_FLASH_WAIT_SEMA)) && ((semaTryCount < CY_FLASH_SEMA_WAIT_MAX_TRIES))) + { + /* check for timeout (as maximum tries count) */ + ++semaTryCount; + } + + if (semaTryCount < CY_FLASH_SEMA_WAIT_MAX_TRIES) + { + result = CY_FLASH_DRV_SUCCESS; + } + } + } + } + #if (CY_CPU_CORTEX_M0P) + } + #endif + + if (CY_FLASH_DRV_SUCCESS == result) + { + /* Notifier is ready, start of the operation */ + intr = Cy_SysLib_EnterCriticalSection(); + +#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ + + /* Tries to acquire the IPC structure and pass the arguments to SROM API */ + if (Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL), CY_FLASH_IPC_NOTIFY_STRUCT0, + (void*)&flashContext) == CY_IPC_DRV_SUCCESS) + { + if (mode == CY_FLASH_NON_BLOCKING_MODE) + { + #if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) + Cy_Flash_RAMDelay(microseconds); + #endif + + /* The Flash operation is successfully initiated */ + result = CY_FLASH_DRV_OPERATION_STARTED; + } + else + { + while (0u != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, ipcBase->LOCK_STATUS)) + { + /* Polls whether the IPC is released and the Flash operation is performed */ + } + + result = Cy_Flash_OperationStatus(); + } + } + else + { + /* The IPC structure is already locked by another process */ + result = CY_FLASH_DRV_IPC_BUSY; + } + +#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) + #if (CY_CPU_CORTEX_M0P) + if (isCM4Powered) + { + #endif + while (CY_IPC_SEMA_SUCCESS != Cy_IPC_Sema_Clear(CY_FLASH_WAIT_SEMA, true)) + { + /* Clear SEMA lock */ + } + #if (CY_CPU_CORTEX_M0P) + } + #endif + + Cy_SysLib_ExitCriticalSection(intr); + /* End of the flash operation */ + } +#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ + + return (result); +} +#if defined (__ICCARM__) + #pragma diag_default=Ta023 +#endif + + +#if !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) + /******************************************************************************* + * Function Name: Cy_Flash_RAMDelay + ****************************************************************************//** + * + * Wait for a defined time in the SRAM memory region. + * + * \param microseconds + * Delay time in microseconds in range 0-65535 us. + * + *******************************************************************************/ + #if defined (__ICCARM__) + #pragma diag_suppress=Ta023 + __ramfunc + #else + CY_SECTION(".cy_ramfunc") + #endif + static void Cy_Flash_RAMDelay(uint32_t microseconds) + { + uint32_t ticks = (microseconds & 0xFFFFUL) * CY_FLASH_TICKS_FOR_1US; + if (ticks != CY_FLASH_NO_DELAY) + { + CY_FLASH_TST_DDFT_FAST_CTL_REG = CY_FLASH_TST_DDFT_FAST_CTL_MASK; + CY_FLASH_TST_DDFT_SLOW_CTL_REG = CY_FLASH_TST_DDFT_SLOW_CTL_MASK; + + SRSS->CLK_OUTPUT_SLOW = _VAL2FLD(SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0, CY_SYSCLK_MEAS_CLK_IMO) | + _VAL2FLD(SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1, CY_FLASH_CLK_OUTPUT_DISABLED); + + /* Load the down-counter without status bit value */ + SRSS->CLK_CAL_CNT1 = _VAL2FLD(SRSS_CLK_CAL_CNT1_CAL_COUNTER1, ticks); + + /* Make sure that the counter is started */ + ticks = _FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS->CLK_CAL_CNT1); + + while (0UL == _FLD2VAL(SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE, SRSS->CLK_CAL_CNT1)) + { + /* Wait until the counter stops counting */ + } + } + } + #if defined (__ICCARM__) + #pragma diag_default=Ta023 + #endif + + #if (CY_CPU_CORTEX_M4) + + /* Based on bookmark codes of mxs40srompsoc BROS,002-03298 */ + #define CY_FLASH_PROGRAM_ROW_BOOKMARK (0x00000001UL) + #define CY_FLASH_ERASE_ROW_BOOKMARK (0x00000002UL) + #define CY_FLASH_WRITE_ROW_ERASE_BOOKMARK (0x00000003UL) + #define CY_FLASH_WRITE_ROW_PROGRAM_BOOKMARK (0x00000004UL) + + /* Number of the CM0P ticks for function delay corrective time at final stage */ + #define CY_FLASH_START_PROGRAM_FINAL_DELAY_TICKS (1000UL) + #define CY_FLASH_PROGRAM_ROW_DELAY (130UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_FINAL_DELAY_TICKS)) + #define CY_FLASH_ERASE_ROW_DELAY (130UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_FINAL_DELAY_TICKS)) + #define CY_FLASH_WRITE_ROW_ERASE_DELAY (130UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_FINAL_DELAY_TICKS)) + #define CY_FLASH_WRITE_ROW_PROGRAM_DELAY (130UL + CY_FLASH_DELAY_CORRECTIVE(CY_FLASH_START_PROGRAM_FINAL_DELAY_TICKS)) + + + /******************************************************************************* + * Function Name: Cy_Flash_ResumeIrqHandler + ****************************************************************************//** + * + * This is the interrupt service routine to make additional processing of the + * flash operations resume phase. + * + *******************************************************************************/ + #if defined (__ICCARM__) + #pragma diag_suppress=Ta023 + __ramfunc + #else + CY_SECTION(".cy_ramfunc") + #endif + static void Cy_Flash_ResumeIrqHandler(void) + { + IPC_STRUCT_Type *ipcBase = Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_CYPIPE_EP0); + + uint32_t bookmark; + bookmark = FLASHC->FM_CTL.BOOKMARK & 0xffffUL; + + uint32_t cm0s = CPUSS->CM0_STATUS; + + switch (bookmark) + { + case CY_FLASH_PROGRAM_ROW_BOOKMARK: + if (cm0s == (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk)) + { + ipcBase->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, (1UL << CY_IPC_INTR_CYPIPE_EP0)); + } + Cy_Flash_RAMDelay(CY_FLASH_PROGRAM_ROW_DELAY); + break; + case CY_FLASH_ERASE_ROW_BOOKMARK: + if (cm0s == (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk)) + { + ipcBase->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, (1UL << CY_IPC_INTR_CYPIPE_EP0)); + } + Cy_Flash_RAMDelay(CY_FLASH_ERASE_ROW_DELAY); /* Delay when erase row is finished */ + break; + case CY_FLASH_WRITE_ROW_ERASE_BOOKMARK: + if (cm0s == (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk)) + { + ipcBase->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, (1UL << CY_IPC_INTR_CYPIPE_EP0)); + } + Cy_Flash_RAMDelay(CY_FLASH_WRITE_ROW_ERASE_DELAY); /* Delay when erase phase for row is finished */ + break; + case CY_FLASH_WRITE_ROW_PROGRAM_BOOKMARK: + if (cm0s == (CPUSS_CM0_STATUS_SLEEPING_Msk | CPUSS_CM0_STATUS_SLEEPDEEP_Msk)) + { + ipcBase->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, (1UL << CY_IPC_INTR_CYPIPE_EP0)); + } + Cy_Flash_RAMDelay(CY_FLASH_WRITE_ROW_PROGRAM_DELAY); + break; + default: + break; + } + } + #if defined (__ICCARM__) + #pragma diag_default=Ta023 + #endif + #endif /* (CY_CPU_CORTEX_M4) */ +#endif /* !defined(CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ + + +/******************************************************************************* +* Function Name: Cy_Flash_EraseRow +****************************************************************************//** +* +* This function erases a single row of flash. Reports success or +* a reason for failure. Does not return until the Write operation is +* complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in +* the case when another process is writing to flash or erasing the row. +* +* User firmware should not enter the Hibernate or Deep-Sleep mode until flash +* Erase is complete. +* For all safe execution conditions see \ref group_flash_configuration +* documentation section. +* +* \param rowAddr Address of the flash row. +* Address must match row start address otherwise API returns \ref +* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + + /* Prepares arguments to be passed to SROM API */ + if (Cy_Flash_BoundsCheck(rowAddr) != false) + { + SystemCoreClockUpdate(); + + flashContext.opcode = CY_FLASH_OPCODE_ERASE_ROW | CY_FLASH_BLOCKING_MODE; + flashContext.arg1 = rowAddr; + flashContext.arg2 = 0UL; + flashContext.arg3 = 0UL; + + result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY); + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_ProgramRow +****************************************************************************//** +* +* This function writes an array of data to a single row of flash. Before calling +* this function, the target flash region must be erased by the +* Cy_Flash_StartErase() or Cy_Flash_EraseRow() function. +* +* Reports success or a reason for failure. Does not return until the Program +* operation is complete. Returns immediately and reports a +* \ref CY_FLASH_DRV_IPC_BUSY error in the case when another process is writing +* to flash. +* +* User firmware should not enter the Hibernate or Deep-sleep mode until flash +* Program is complete. +* For all safe execution conditions see \ref group_flash_configuration +* documentation section. +* +* Data to be programmed must be located in the SRAM memory region. +* \note Before reading data from previously programmed/erased flash rows, the +* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* function. +* +* \param rowAddr Address of the flash row. +* Address must match row start address otherwise API returns \ref +* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* +* \param data The pointer to the data which has to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_ProgramRow(uint32_t rowAddr, const uint32_t* data) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + + /* Checks whether the input parameters are valid */ + if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data)) + { + SystemCoreClockUpdate(); + + /* Prepares arguments to be passed to SROM API */ + flashContext.opcode = CY_FLASH_OPCODE_PROGRAM_ROW | CY_FLASH_BLOCKING_MODE; + flashContext.arg1 = CY_FLASH_CONFIG_DATASIZE | CY_FLASH_DATA_LOC_SRAM; + flashContext.arg2 = rowAddr; + flashContext.arg3 = (uint32_t)data; + + result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_PROGRAM_DELAY); + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_WriteRow +****************************************************************************//** +* +* This function writes an array of data to a single row of flash. This is done +* in two steps - erase and then program flash row with the input data. +* Reports success or a reason for failure. Does not return until the Write +* operation is complete. +* Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case +* when another process is writing to flash. +* +* User firmware should not enter the Hibernate or Deep-sleep mode until flash +* Write is complete. +* For all safe execution conditions see \ref group_flash_configuration +* documentation section. +* +* Data to be programmed must be located in the SRAM memory region. +* \note Before reading data from previously programmed/erased flash rows, the +* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* function. +* +* \param rowAddr Address of the flash row. +* Address must match row start address otherwise API returns \ref +* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* +* \param data The pointer to the data which has to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + + /* Checks whether the input parameters are valid */ + if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data)) + { + SystemCoreClockUpdate(); + + /* Prepares arguments to be passed to SROM API */ + flashContext.opcode = CY_FLASH_OPCODE_WRITE_ROW | CY_FLASH_BLOCKING_MODE; + flashContext.arg1 = 0UL; + flashContext.arg2 = rowAddr; + flashContext.arg3 = (uint32_t)data; + + result = Cy_Flash_SendCmd(CY_FLASH_BLOCKING_MODE, CY_FLASH_START_WRITE_DELAY); + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_StartWrite +****************************************************************************//** +* +* Erase flash row and performs programming of the row with the input data. +* Returns immediately and reports a successful start or reason for failure. +* Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when another process is +* writing to flash. +* +* User firmware should not enter the Hibernate or Deep-Sleep mode until flash +* Write is complete. +* For all safe execution conditions see \ref group_flash_configuration +* documentation section. +* +* Data to be programmed must be located in the SRAM memory region. +* \note Before reading data from previously programmed/erased flash rows, the +* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* function. +* +* \param rowAddr Address of the flash row. +* Address must match row start address otherwise API returns \ref +* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash write operation is +* performing. Refer to the device datasheet for the details. +* +* \param data The pointer to the data to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + + /* Checks whether the input parameters are valid */ + if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data)) + { + result = Cy_Flash_StartErase(rowAddr); + + if (CY_FLASH_DRV_OPERATION_STARTED == result) + { + /* Polls whether the IPC is released and the Flash operation is performed */ + do + { + result = Cy_Flash_OperationStatus(); + } + while (result == CY_FLASH_DRV_OPCODE_BUSY); + + if (CY_FLASH_DRV_SUCCESS == result) + { + result = Cy_Flash_StartProgram(rowAddr, data); + } + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_IsOperationComplete +****************************************************************************//** +* +* Reports a successful operation result, reason of failure or busy status +* ( \ref CY_FLASH_DRV_OPCODE_BUSY ). +* +* \return Returns the status of the Flash operation (see \ref cy_en_flashdrv_status_t). +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_IsOperationComplete(void) +{ + return (Cy_Flash_OperationStatus()); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_StartErase +****************************************************************************//** +* +* Starts erasing a single row of flash. Returns immediately and reports a +* successful start or reason for failure. Reports a \ref CY_FLASH_DRV_IPC_BUSY +* error in the case when IPC structure is locked by another process. +* +* User firmware should not enter the Hibernate or Deep-Sleep mode until +* flash Erase is complete. +* For all safe execution conditions see \ref group_flash_configuration +* documentation section. +* +* \note Before reading data from previously programmed/erased flash rows, the +* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* function. +* +* \param rowAddr Address of the flash row. +* Address must match row start address otherwise API returns \ref +* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the flash read operation is +* initiated in the same flash sector where the flash erase operation is +* performing. Refer to the device datasheet for the details. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_StartErase(uint32_t rowAddr) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + + if (Cy_Flash_BoundsCheck(rowAddr) != false) + { + SystemCoreClockUpdate(); + + /* Prepares arguments to be passed to SROM API */ + flashContext.opcode = CY_FLASH_OPCODE_ERASE_ROW; + flashContext.arg1 = rowAddr; + flashContext.arg2 = 0UL; + flashContext.arg3 = 0UL; + result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_ERASE_DELAY); + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_StartProgram +****************************************************************************//** +* +* Starts writing an array of data to a single row of flash. Before calling this +* function, the target flash region must be erased by the Cy_Flash_StartErase() +* or Cy_Flash_EraseRow() function. +* +* Returns immediately and reports a successful start or reason for failure. +* Reports a \ref CY_FLASH_DRV_IPC_BUSY error if another process is writing +* to flash. +* +* The user firmware should not enter Hibernate or Deep-Sleep mode until flash +* Program is complete. +* For all safe execution conditions see \ref group_flash_configuration +* documentation section. +* +* Data to be programmed must be located in the SRAM memory region. +* \note Before reading data from previously programmed/erased flash rows, the +* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* function. +* +* \param rowAddr Address of the flash row. +* Address must match row start address otherwise API returns \ref +* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* The Read-while-Write violation occurs when the Flash Write operation is +* performing. Refer to the device datasheet for the details. +* +* \param data The pointer to the data to be written to flash. The size +* of the data array must be equal to the flash row size. The flash row size for +* the selected device is defined by the \ref CY_FLASH_SIZEOF_ROW macro. Refer to +* the device datasheet for the details. +* +* \return Returns the status of the Flash operation, +* see \ref cy_en_flashdrv_status_t. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + + if ((Cy_Flash_BoundsCheck(rowAddr) != false) && (NULL != data)) + { + SystemCoreClockUpdate(); + + /* Prepares arguments to be passed to SROM API */ + flashContext.opcode = CY_FLASH_OPCODE_PROGRAM_ROW | CY_FLASH_NON_BLOCKING_MODE; + flashContext.arg1 = CY_FLASH_CONFIG_DATASIZE | CY_FLASH_DATA_LOC_SRAM; + flashContext.arg2 = rowAddr; + flashContext.arg3 = (uint32_t)data; + + result = Cy_Flash_SendCmd(CY_FLASH_NON_BLOCKING_MODE, CY_FLASH_START_PROGRAM_DELAY); + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_RowChecksum +****************************************************************************//** +* +* Returns a checksum value of the specified flash row. +* +* \note Now Cy_Flash_RowChecksum() requires the row address (rowAddr) +* as a parameter. In previous versions of the driver, this function used +* the row number (rowNum) for this parameter. +* +* \param rowAddr Address of the flash row. +* Address must match row start address otherwise API returns \ref +* CY_FLASH_DRV_INVALID_INPUT_PARAMETERS status. The number of the flash rows +* is defined by the \ref CY_FLASH_NUMBER_ROWS macro for the selected device. +* +* \param checksumPtr The pointer to the address where checksum is to be stored +* +* \return Returns the status of the Flash operation. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_RowChecksum (uint32_t rowAddr, uint32_t* checksumPtr) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + uint32_t resTmp; + uint32_t rowID; + + /* Checks whether the input parameters are valid */ + if ((Cy_Flash_BoundsCheck(rowAddr)) && (NULL != checksumPtr)) + { + rowID = Cy_Flash_GetRowNum(rowAddr); + + /* Prepares arguments to be passed to SROM API */ + flashContext.opcode = CY_FLASH_OPCODE_CHECKSUM | + (((rowID >> CY_FLASH_REGION_ID_SHIFT) & CY_FLASH_REGION_ID_MASK) << CY_FLASH_OPCODE_CHECKSUM_REGION_SHIFT) | + ((rowID & CY_FLASH_ROW_ID_MASK) << CY_FLASH_OPCODE_CHECKSUM_ROW_SHIFT); + + /* Tries to acquire the IPC structure and pass the arguments to SROM API */ + if (Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL), CY_FLASH_IPC_NOTIFY_STRUCT0, + (void*)&flashContext) == CY_IPC_DRV_SUCCESS) + { + /* Polls whether IPC is released and the Flash operation is performed */ + while (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) != false) + { + /* Wait till IPC is released */ + } + + resTmp = flashContext.opcode; + + if ((resTmp >> CY_FLASH_ERROR_SHIFT) == CY_FLASH_ERROR_NO_ERROR) + { + result = CY_FLASH_DRV_SUCCESS; + *checksumPtr = flashContext.opcode & CY_FLASH_RESULT_MASK; + } + else + { + result = Cy_Flash_ProcessOpcode(flashContext.opcode); + } + } + else + { + /* The IPC structure is already locked by another process */ + result = CY_FLASH_DRV_IPC_BUSY; + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_CalculateHash +****************************************************************************//** +* +* Returns a hash value of the specified region of flash. Hash calculation +* algorithm provided by SROM code. +* +* \param data Start the data address. API returns invalid address status if +* called on out of bound FLASH region. +* +* \param numberOfBytes The hash value is calculated for the number of bytes +* after the start data address (0 - 1 byte, 1- 2 bytes etc). +* +* \param hashPtr The pointer to the address where hash is to be stored +* +* \return Returns the status of the Flash operation. +* +*******************************************************************************/ +cy_en_flashdrv_status_t Cy_Flash_CalculateHash (const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + volatile uint32_t resTmp; + + /* Checks whether the input parameters are valid */ + if ((data != NULL) && (0ul != numberOfBytes)) + { + /* Prepares arguments to be passed to SROM API */ + flashContext.opcode = CY_FLASH_OPCODE_HASH; + flashContext.arg1 = (uint32_t)data; + flashContext.arg2 = numberOfBytes; + + /* Tries to acquire the IPC structure and pass the arguments to SROM API */ + if (Cy_IPC_Drv_SendMsgPtr(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL), CY_FLASH_IPC_NOTIFY_STRUCT0, + (void*)&flashContext) == CY_IPC_DRV_SUCCESS) + { + /* Polls whether IPC is released and the Flash operation is performed */ + while (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) != false) + { + /* Wait till IPC is released */ + } + + resTmp = flashContext.opcode; + + if ((resTmp >> CY_FLASH_ERROR_SHIFT) == CY_FLASH_ERROR_NO_ERROR) + { + result = CY_FLASH_DRV_SUCCESS; + *hashPtr = flashContext.opcode & CY_FLASH_RESULT_MASK; + } + else + { + result = Cy_Flash_ProcessOpcode(flashContext.opcode); + } + } + else + { + /* The IPC structure is already locked by another process */ + result = CY_FLASH_DRV_IPC_BUSY; + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_GetRowNum +****************************************************************************//** +* +* Returns flash region ID and row number of the Flash address. +* +* \param flashAddr Address to be checked +* +* \return +* The valid return value is encoded as follows (or 0xFFFFFFFFUL for invalid +* address) +* +*
Field Value +*
Flash row number [15:0] bits +*
Flash region ID [31:16] bits +*
+* +*******************************************************************************/ +static uint32_t Cy_Flash_GetRowNum(uint32_t flashAddr) +{ + uint32_t result; + + if ((flashAddr >= CY_FLASH_BASE) && (flashAddr < (CY_FLASH_BASE + CY_FLASH_SIZE))) + { + result = (CY_FLASH_REGION_ID_MAIN << CY_FLASH_REGION_ID_SHIFT) | + ((flashAddr - CY_FLASH_BASE) / CY_FLASH_SIZEOF_ROW); + } + else + if ((flashAddr >= CY_EM_EEPROM_BASE) && (flashAddr < (CY_EM_EEPROM_BASE + CY_EM_EEPROM_SIZE))) + { + result = (CY_FLASH_REGION_ID_EM_EEPROM << CY_FLASH_REGION_ID_SHIFT) | + ((flashAddr - CY_EM_EEPROM_BASE) / CY_FLASH_SIZEOF_ROW); + } + else + if ((flashAddr >= SFLASH_BASE) && (flashAddr < (SFLASH_BASE + SFLASH_SECTION_SIZE))) + { + result = (CY_FLASH_REGION_ID_SFLASH << CY_FLASH_REGION_ID_SHIFT) | + ((flashAddr - SFLASH_BASE) / CY_FLASH_SIZEOF_ROW); + } + else + { + result = 0xFFFFFFFFUL; + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_BoundsCheck +****************************************************************************//** +* +* Returns false if Flash address is out of boundary, otherwise returns true. +* +* \param flashAddr Address to be checked +* +* \return false - out of bound, true - in flash bounds +* +*******************************************************************************/ +static bool Cy_Flash_BoundsCheck(uint32_t flashAddr) +{ + return ((Cy_Flash_GetRowNum(flashAddr) != 0xFFFFFFFFUL) && ((flashAddr % CY_FLASH_SIZEOF_ROW) == 0UL)); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_ProcessOpcode +****************************************************************************//** +* +* Converts System Call returns to the Flash driver return defines. +* +* \param opcode The value returned by the System Call. +* +* \return Flash driver return. +* +*******************************************************************************/ +static cy_en_flashdrv_status_t Cy_Flash_ProcessOpcode(uint32_t opcode) +{ + cy_en_flashdrv_status_t result; + + switch (opcode) + { + case 0UL: + { + result = CY_FLASH_DRV_SUCCESS; + break; + } + case CY_FLASH_ROMCODE_SUCCESS: + { + result = CY_FLASH_DRV_SUCCESS; + break; + } + case CY_FLASH_ROMCODE_INVALID_PROTECTION: + { + result = CY_FLASH_DRV_INV_PROT; + break; + } + case CY_FLASH_ROMCODE_INVALID_FM_PL: + { + result = CY_FLASH_DRV_INVALID_FM_PL; + break; + } + case CY_FLASH_ROMCODE_INVALID_FLASH_ADDR: + { + result = CY_FLASH_DRV_INVALID_FLASH_ADDR; + break; + } + case CY_FLASH_ROMCODE_ROW_PROTECTED: + { + result = CY_FLASH_DRV_ROW_PROTECTED; + break; + } + case CY_FLASH_ROMCODE_IN_PROGRESS_NO_ERROR: + { + result = CY_FLASH_DRV_PROGRESS_NO_ERROR; + break; + } + case (uint32_t)CY_FLASH_DRV_INVALID_INPUT_PARAMETERS: + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + break; + } + case CY_FLASH_IS_OPERATION_STARTED : + { + result = CY_FLASH_DRV_OPERATION_STARTED; + break; + } + case CY_FLASH_IS_BUSY : + { + result = CY_FLASH_DRV_OPCODE_BUSY; + break; + } + case CY_FLASH_IS_IPC_BUSY : + { + result = CY_FLASH_DRV_IPC_BUSY; + break; + } + case CY_FLASH_IS_INVALID_INPUT_PARAMETERS : + { + result = CY_FLASH_DRV_INVALID_INPUT_PARAMETERS; + break; + } + default: + { + result = CY_FLASH_DRV_ERR_UNC; + break; + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_OperationStatus +****************************************************************************//** +* +* Checks the status of the Flash Operation, and returns it. +* +* \return Returns the status of the Flash operation +* (see \ref cy_en_flashdrv_status_t). +* +*******************************************************************************/ +static cy_en_flashdrv_status_t Cy_Flash_OperationStatus(void) +{ + cy_en_flashdrv_status_t result = CY_FLASH_DRV_OPCODE_BUSY; + + /* Checks if the IPC structure is not locked */ + if (Cy_IPC_Drv_IsLockAcquired(Cy_IPC_Drv_GetIpcBaseAddress(CY_IPC_CHAN_SYSCALL)) == false) + { + /* The result of SROM API calling is returned to the driver context */ + result = Cy_Flash_ProcessOpcode(flashContext.opcode); + + /* Clear pre-fetch cache after flash operation */ +#if (CY_CPU_CORTEX_M0P) + FLASHC->CM0_CA_CMD = FLASHC_CM0_CA_CMD_INV_Msk; +#else + FLASHC->CM4_CA_CMD = FLASHC_CM4_CA_CMD_INV_Msk; +#endif /* (CY_CPU_CORTEX_M0P) */ + + while ((FLASHC->CM0_CA_CMD != 0U) || (FLASHC->CM4_CA_CMD != 0U)) + { + } + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_Flash_GetExternalStatus +****************************************************************************//** +* +* This function handles the case where a module such as security image captures +* a system call from this driver and reports its own status or error code, +* for example protection violation. In that case, a function from this +* driver returns an unknown error (see \ref cy_en_flashdrv_status_t). After receipt +* of an unknown error, the user may call this function to get the status +* of the capturing module. +* +* The user is responsible for parsing the content of the returned value +* and casting it to the appropriate enumeration. +* +* \return +* The error code that was stored in the opcode variable. +* +*******************************************************************************/ +uint32_t Cy_Flash_GetExternalStatus(void) +{ + return (flashContext.opcode); +} + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/flash/cy_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/flash/cy_flash.h new file mode 100644 index 0000000000..cd4255a6c1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/flash/cy_flash.h @@ -0,0 +1,405 @@ +/***************************************************************************//** +* \file cy_flash.h +* \version 3.0 +* +* Provides the API declarations of the Flash driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#if !defined(CY_FLASH_H) +#define CY_FLASH_H + +/** +* \defgroup group_flash Flash System Routine (Flash) +* \{ +* Internal flash memory programming +* +* Flash memory in PSoC devices provides non-volatile storage for user firmware, +* user configuration data, and bulk data storage. +* +* Flash operations are implemented as system calls. System calls are executed +* out of SROM in the privileged mode of operation. Users have no access to read +* or modify the SROM code. The driver API requests the system call by acquiring +* the Inter-processor communication (IPC) and writing the SROM function opcode +* and parameters to its input registers. As a result, an NMI interrupt is invoked +* and the requested SROM API is executed. The operation status is returned to the +* driver context and a release interrupt is triggered. +* +* Writing to flash can take up to 20 milliseconds. During this time, +* the device should not be reset (including XRES pin, software reset, and +* watchdog) or unexpected changes may be made to portions of the flash. +* Also, the low-voltage detect circuits should be configured to generate an +* interrupt instead of a reset. +* +* A Read while Write violation occurs when a flash Read operation is initiated +* in the same or neighboring flash sector where the flash Write, Erase, or +* Program operation is working. This violation may cause a HardFault exception. +* To avoid the Read while Write violation, the user must carefully split the +* Read and Write operation on flash sectors which are not neighboring, +* considering both cores in the multi-processor device. The flash is divided +* into four equal sectors. You may edit the linker script to place the code +* into neighboring sectors. For example, use sectors number 0 and 1 for code +* and sectors 2 and 3 for data storage. +* +* \section group_flash_configuration Configuration Considerations +* +* \subsection group_flash_config_intro Introduction: +* The PSoC 6 MCU user-programmable Flash consists of: +* - Up to four User Flash sectors (0 through 3) - 256KB each. +* - EEPROM emulation sector - 32KB. +* +* Write operations are performed on a per-sector basis and may be done as +* Blocking or Partially Blocking, defined as follows: +* +* \subsection group_flash_config_blocking Blocking: +* In this case, the entire Flash block is not available for the duration of the +* Write (up to 20 milliseconds). Therefore, no Flash accesses +* (from any Bus Master) can occur during that time. CPU execution can be +* performed from SRAM. All pre-fetching must be disabled. Application code +* execution from Flash is blocked for the Flash Write duration for both cores. +* +* \subsection group_flash_config_block_const Constraints for Blocking Flash operations: +* -# During write to flash, the device should not be reset (including XRES pin, +* software reset, and watchdog), or unexpected changes may be made to portions +* of the flash. +* -# The low-voltage detect circuits should be configured to generate an +* interrupt instead of a reset. +* -# Flash write operation is allowed only in one of the following CM4 states: +* -# CM4 is Active and initialized:
+* call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". +* Note: If desired user may put CM4 core in Deep Sleep any time +* after calling Cy_SysEnableCM4(). +* -# CM4 is Off:
+* call Cy_SysDisableCM4(). Note: In this state Debug mode is not +* supported. +* . +* -# Flash write cannot be performed in ULP (core voltage 0.9V) mode. +* -# Interrupts must be enabled on both active cores. Do not enter a critical +* section during flash operation. +* -# User must guarantee that system pipe interrupts (IPC interrupts 3 and 4) +* have the highest priority, or at least that pipe interrupts are not +* interrupted or in a pending state for more than 700 µs. +* -# User must guarantee that during flash write operation no flash read +* operations are performed by bus masters other than CM0+ and CM4 (DMA and +* Crypto). +* -# If you do not use the default startup, ensure that firmware calls the +* following functions before any flash write/erase operations: +* \snippet Flash_sut_01.cydsn/main_cm0p.c Flash Initialization +* +* \subsection group_flash_config_rww Partially Blocking: +* This method has a much shorter time window during which Flash accesses are not +* allowed. Application code execution from Flash is blocked for only a part of +* Flash Write duration, for both cores. Blocking duration depends upon the API +* sequence used. +* +* For API sequence Cy_Flash_StartErase() + Cy_Flash_StartProgram() there are +* four block-out regions during which the read is blocked using the software +* driver (PDL). See Figure 1. +* +*
+* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
Table 1 - Block-out periods
Block-outPhaseDuration
AThe beginning of the Erase operation2ms + 9500 SlowClk cycles
BThe end of the Erase operation0.13ms + 1000 SlowClk cycles
CThe beginning of the Program operation0.8ms + 6000 SlowClk cycles
DThe end of the Program operation0.13ms + 1000 SlowClk cycles
+*
+* +* This allows both cores to execute an application for about 80% of Flash Write +* operation - see Figure 1. +* This capability is important for communication protocols that rely on fast +* response. +* +* \image html flash-rww-diagram.png "Figure 1 - Blocking Intervals in Flash Write operation" width=70% +* +* For the Cy_Flash_StartWrite() function, the block-out period is different for +* the two cores. The core that initiates Cy_Flash_StartWrite() is blocked for +* two periods: +* - From start of Erase operation (start of A on Figure 1) till the start of +* Program operation (end of C on Figure 1). +* - During D period on Figure 1. +* +* The core that performs read/execute is blocked identically to the +* Cy_Flash_StartErase() + Cy_Flash_StartProgram() sequence - see Figure 1. +* +* This allows the core that initiates Cy_Flash_StartWrite() to execute an +* application for about 20% of the Flash Write operation. The other core executes +* the application for about 80% of the Flash Write operation. +* +* Some constraints must be planned for in the Partially Blocking mode which are +* described in detail below. +* +* \subsection group_flash_config_rww_const Constraints for Partially Blocking Flash operations: +* -# During write to flash, the device should not be reset (including XRES pin, +* software reset, and watchdog) or unexpected changes may be made to portions +* of the flash. +* -# The low-voltage detect circuits should be configured to generate an +* interrupt instead of a reset. +* -# During write to flash, application code should not change the clock +* settings. Use Cy_Flash_IsOperationComplete() to ensure flash write +* operation is finished. +* -# Flash write operation is allowed only in one of the following CM4 states: +* -# CM4 is Active and initialized:
+* call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". +* Note: If desired user may put CM4 core in Deep Sleep any time +* after calling Cy_SysEnableCM4(). +* -# CM4 is Off:
+* call Cy_SysDisableCM4(). Note: In this state Debug mode is not +* supported. +* . +* -# Use the following rules for split by sectors. (In this context, read means +* read of any bus master: CM0+, CM4, DMA, Crypto, etc.) +* -# Do not write to and read/execute from the same flash sector at the same +* time. This is true for all sectors. +* -# Writing rules in User Flash: +* -# Any bus master can read/execute from UFLASH S0 and/or S1, during +* flash write to UFLASH S2 or S3. +* -# Any bus master can read/execute from UFLASH S2 and/or S3, during +* flash write to UFLASH S0 or S1. +* +* Suggestion: in case of bootloading, it is recommended to place +* code for CM4 in either S0 or S1. CM0+ code resides in S0. Write data +* to S2 and S3 sections. +* . +* -# Flash write cannot be performed in ULP mode (core voltage 0.9V). +* -# Interrupts must be enabled on both active cores. Do not enter a critical +* section during flash operation. +* -# User must guarantee that system pipe interrupts (IPC interrupts 3 and 4) +* have the highest priority, or at least that pipe interrupts are not +* interrupted or in a pending state for more than 700 µs. +* -# User must guarantee that during flash write operation no flash read +* operations are performed by bus masters other than CM0+ and CM4 +* (DMA and Crypto). +* -# If you do not use the default startup, ensure that firmware calls the +* following functions before any flash write/erase operations: +* \snippet Flash_sut_01.cydsn/main_cm0p.c Flash Initialization +* +* \subsection group_flash_config_emeeprom EEPROM section use: +* If you plan to use "cy_em_eeprom" section for different purposes for both of +* device cores or use Em_EEPROM Middleware together with flash driver +* write operations you must modify the linker scripts.
+* For more information, refer to the Middleware/Cypress Em_EEPROM Middleware +* Library section of the PDL documentation. +* +* \section group_flash_more_information More Information +* +* See the technical reference manual (TRM) for more information about the Flash +* architecture. +* +* \section group_flash_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4ACasting to different object pointer type.The cast of the uint32_t pointer to pipe message structure pointer +* is used to get transmitted data via the \ref group_ipc channel. +* We cast only one pointer, so there is no way to avoid this cast.
11.5RNot performed, the cast that removes any const or volatile qualification from the type addressed by a pointer.The removal of the volatile qualification inside the function has no side effects.
+* +* \section group_flash_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
3.0New function - Cy_Flash_ProgramRow();
+* Updated Cy_Flash_RowChecksum(): changed input parameter to take the +* row address (rowAddr) instead of the row number +* (rowNum);
+* Renamed macro for disabling RWW support in driver to +* CY_FLASH_RWW_DRV_SUPPORT_DISABLED.
+* Updated \ref group_flash_configuration documentation section with +* flash usage constraints.		Improvements made based on usability feedback to use a common +* interface
2.0Added non-blocking erase function - Cy_Flash_StartErase(). +* Removed the clear cache function call.The clear cache operation is removed from the blocking Write/Erase +* function because in this case it is performed by the hardware. +* Otherwise it is documented that it is the user's responsibility to +* clear the cache after executing the non-blocking Write/Erase flash +* operation.
Added new Cy_Flash_IsOperationComplete() function to check completeness. +* Obsoleted Cy_Flash_IsWriteComplete(), Cy_Flash_IsProgramComplete(), +* and Cy_Flash_IsEraseComplete() functions.
+* Added Cy_Flash_GetExternalStatus() function to get unparsed status where +* flash driver will be used in security applications with other modules +* as SecureImage.
+* Added Cy_Flash_Init() function to initialize all needed prerequisites +* for Erase/Write operations.		Updated driver design to improve user experience.
Updated driver implementation to remove MISRA rules deviations.Driver implementation quality improvement.
1.0Initial version
+* +* \defgroup group_flash_macros Macros +* \{ +* \defgroup group_flash_general_macros Flash general parameters +* Provides general information about flash +* \} +* \defgroup group_flash_functions Functions +* \defgroup group_flash_enumerated_types Enumerated Types +*/ + +#include +#include "syslib/cy_syslib.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Macro definitions +***************************************/ +/** +* \addtogroup group_flash_macros +* \{ +*/ + +/** Driver major version */ +#define CY_FLASH_DRV_VERSION_MAJOR 3 + +/** Driver minor version */ +#define CY_FLASH_DRV_VERSION_MINOR 0 + +#define CY_FLASH_ID (CY_PDL_DRV_ID(0x14UL)) /**< FLASH PDL ID */ + +#define CY_FLASH_ID_INFO (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_INFO ) /**< Return prefix for FLASH driver function status codes */ +#define CY_FLASH_ID_WARNING (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_WARNING) /**< Return prefix for FLASH driver function warning return values */ +#define CY_FLASH_ID_ERROR (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_ERROR) /**< Return prefix for FLASH driver function error return values */ + +/** \} group_flash_macros */ + + +/** +* \addtogroup group_flash_general_macros +* \{ +*/ + +/** Flash row size */ +#define CY_FLASH_SIZEOF_ROW (CPUSS_FLASHC_PA_SIZE * 4u) +/** Number of flash rows */ +#define CY_FLASH_NUMBER_ROWS (CY_FLASH_SIZE / CY_FLASH_SIZEOF_ROW) +/** Long words flash row size */ +#define CY_FLASH_SIZEOF_ROW_LONG_UNITS (CY_FLASH_SIZEOF_ROW / sizeof(uint32_t)) + +/** \} group_flash_general_macros */ + + +/** +* \addtogroup group_flash_enumerated_types +* \{ +*/ + +/** This enum has the return values of the Flash driver */ +typedef enum cy_en_flashdrv_status +{ + CY_FLASH_DRV_SUCCESS = 0x00UL, /**< Success */ + CY_FLASH_DRV_INV_PROT = ( CY_FLASH_ID_ERROR + 0x0UL), /**< Invalid device protection state */ + CY_FLASH_DRV_INVALID_FM_PL = ( CY_FLASH_ID_ERROR + 0x1UL), /**< Invalid flash page latch address */ + CY_FLASH_DRV_INVALID_FLASH_ADDR = ( CY_FLASH_ID_ERROR + 0x2UL), /**< Invalid flash address */ + CY_FLASH_DRV_ROW_PROTECTED = ( CY_FLASH_ID_ERROR + 0x3UL), /**< Row is write protected */ + CY_FLASH_DRV_IPC_BUSY = ( CY_FLASH_ID_ERROR + 0x5UL), /**< IPC structure is already locked by another process */ + CY_FLASH_DRV_INVALID_INPUT_PARAMETERS = ( CY_FLASH_ID_ERROR + 0x6UL), /**< Input parameters passed to Flash API are not valid */ + CY_FLASH_DRV_PL_ROW_COMP_FA = ( CY_FLASH_ID_ERROR + 0x22UL), /**< Comparison between Page Latches and FM row failed */ + CY_FLASH_DRV_ERR_UNC = ( CY_FLASH_ID_ERROR + 0xFFUL), /**< Unknown error code. See \ref Cy_Flash_GetExternalStatus() */ + CY_FLASH_DRV_PROGRESS_NO_ERROR = ( CY_FLASH_ID_INFO + 0x0UL), /**< Command in progress; no error */ + CY_FLASH_DRV_OPERATION_STARTED = ( CY_FLASH_ID_INFO + 0x1UL), /**< Flash operation is successfully initiated */ + CY_FLASH_DRV_OPCODE_BUSY = ( CY_FLASH_ID_INFO + 0x2UL) /**< Flash is under operation */ +} cy_en_flashdrv_status_t; + +/** \} group_flash_enumerated_types */ + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_flash_functions +* \{ +*/ +void Cy_Flash_Init(void); +cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr); +cy_en_flashdrv_status_t Cy_Flash_ProgramRow(uint32_t rowAddr, const uint32_t* data); +cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data); +cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data); +cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data); +cy_en_flashdrv_status_t Cy_Flash_StartErase(uint32_t rowAddr); +cy_en_flashdrv_status_t Cy_Flash_IsOperationComplete(void); +cy_en_flashdrv_status_t Cy_Flash_RowChecksum(uint32_t rowAddr, uint32_t* checksumPtr); +cy_en_flashdrv_status_t Cy_Flash_CalculateHash(const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr); +uint32_t Cy_Flash_GetExternalStatus(void); +/** \} group_flash_functions */ + +/** \cond INTERNAL */ +/* Macros to backward compatibility */ +#define Cy_Flash_IsWriteComplete(...) Cy_Flash_IsOperationComplete() +#define Cy_Flash_IsProgramComplete(...) Cy_Flash_IsOperationComplete() +#define Cy_Flash_IsEraseComplete(...) Cy_Flash_IsOperationComplete() +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + + +#endif /* #if !defined(CY_FLASH_H) */ + +/** \} group_flash */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.c new file mode 100644 index 0000000000..dc394efd93 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.c @@ -0,0 +1,262 @@ +/***************************************************************************//** +* \file cy_gpio.c +* \version 1.10.1 +* +* \brief +* Provides an API implementation of the GPIO driver +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "cy_gpio.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_GPIO_Pin_Init +****************************************************************************//** +* +* \brief Initializes all pin configuration settings for the specified pin. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param config +* Pointer to the pin config structure base address +* +* \return +* Initialization status +* +* \note +* This function modifies port registers in read-modify-write operations. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Pin_Init +* +*******************************************************************************/ +cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config) +{ + cy_en_gpio_status_t status = CY_GPIO_SUCCESS; + uint32_t maskCfgOut; + uint32_t tempReg; + + if((NULL != base) && (NULL != config)) + { + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->outVal)); + CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(config->driveMode)); + CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom)); + CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->intMask)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtrip)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->slewRate)); + CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(config->driveSel)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vregEn)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->ibufMode)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtripSel)); + CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(config->vrefSel)); + CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(config->vohSel)); + + Cy_GPIO_Write(base, pinNum, config->outVal); + Cy_GPIO_SetDrivemode(base, pinNum, config->driveMode); + Cy_GPIO_SetHSIOM(base, pinNum, config->hsiom); + + Cy_GPIO_SetInterruptEdge(base, pinNum, config->intEdge); + Cy_GPIO_SetInterruptMask(base, pinNum, config->intMask); + Cy_GPIO_SetVtrip(base, pinNum, config->vtrip); + + /* Slew rate and Driver strength */ + maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum) + | (CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET)); + tempReg = base->CFG_OUT & ~(maskCfgOut); + base->CFG_OUT = tempReg | ((config->slewRate & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum) + | ((config->driveSel & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET)); + + /* SIO specific configuration */ + tempReg = base->CFG_SIO & ~(CY_GPIO_SIO_PIN_MASK); + base->CFG_SIO = tempReg | (((config->vregEn & CY_GPIO_VREG_EN_MASK) + | ((config->ibufMode & CY_GPIO_IBUF_MASK) << CY_GPIO_IBUF_SHIFT) + | ((config->vtripSel & CY_GPIO_VTRIP_SEL_MASK) << CY_GPIO_VTRIP_SEL_SHIFT) + | ((config->vrefSel & CY_GPIO_VREF_SEL_MASK) << CY_GPIO_VREF_SEL_SHIFT) + | ((config->vohSel & CY_GPIO_VOH_SEL_MASK) << CY_GPIO_VOH_SEL_SHIFT)) + << ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET)); + } + else + { + status = CY_GPIO_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Port_Init +****************************************************************************//** +* +* \brief Initialize a complete port of pins from a single init structure. +* +* The configuration structure used in this function has a 1:1 mapping to the +* GPIO and HSIOM registers. Refer to the device Technical Reference Manual (TRM) +* for the register details on how to populate them. +* +* \param base +* Pointer to the pin's port register base address +* +* \param config +* Pointer to the pin config structure base address +* +* \return +* Initialization status +* +* \note +* If using the PSoC Creator IDE, there is no need to initialize the pins when +* using the GPIO component on the schematic. Ports are configured in +* Cy_SystemInit() before main() entry. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Port_Init +* +*******************************************************************************/ +cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config) +{ + cy_en_gpio_status_t status = CY_GPIO_SUCCESS; + uint32_t portNum; + HSIOM_PRT_Type* baseHSIOM; + + if((NULL != base) && (NULL != config)) + { + CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->out)); + CY_ASSERT_L2(CY_GPIO_IS_PIN_BIT_VALID(config->cfgIn)); + CY_ASSERT_L2(CY_GPIO_IS_INTR_CFG_VALID(config->intrCfg)); + CY_ASSERT_L2(CY_GPIO_IS_INTR_MASK_VALID(config->intrMask)); + CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel0Active)); + CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel1Active)); + + portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE; + baseHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); + + base->OUT = config->out; + base->CFG = config->cfg; + base->CFG_IN = config->cfgIn; + base->CFG_OUT = config->cfgOut; + base->INTR_CFG = config->intrCfg; + base->INTR_MASK = config->intrMask; + base->CFG_SIO = config->cfgSIO; + baseHSIOM->PORT_SEL0 = config->sel0Active; + baseHSIOM->PORT_SEL1 = config->sel1Active; + } + else + { + status = CY_GPIO_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Pin_FastInit +****************************************************************************//** +* +* \brief Initialize the most common configuration settings for all pin types. +* +* These include, drive mode, initial output value, and HSIOM connection. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param driveMode +* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros +* +* \param outVal +* Logic state of the output buffer driven to the pin (1 or 0) +* +* \param hsiom +* HSIOM input selection +* +* \return +* void +* +* \note +* This function modifies port registers in read-modify-write operations. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Pin_FastInit +* +*******************************************************************************/ +void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, + uint32_t outVal, en_hsiom_sel_t hsiom) +{ + uint32_t tempReg; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(driveMode)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(outVal)); + CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(hsiom)); + + tempReg = (base->OUT & ~(CY_GPIO_OUT_MASK << pinNum)); + base->OUT = tempReg | ((outVal & CY_GPIO_OUT_MASK) << pinNum); + + tempReg = (base->CFG & ~(CY_GPIO_CFG_DM_MASK << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET))); + base->CFG = tempReg | ((driveMode & CY_GPIO_CFG_DM_MASK) << (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)); + + Cy_GPIO_SetHSIOM(base, pinNum, hsiom); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Port_Deinit +****************************************************************************//** +* +* \brief Reset a complete port of pins back to power on reset defaults. +* +* \param base +* Pointer to the pin's port register base address +* +* \return +* void +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Port_Deinit +* +*******************************************************************************/ +void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base) +{ + uint32_t portNum; + HSIOM_PRT_Type* portAddrHSIOM; + + portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE; + portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); + + base->OUT = CY_GPIO_PRT_DEINIT; + base->CFG = CY_GPIO_PRT_DEINIT; + base->CFG_IN = CY_GPIO_PRT_DEINIT; + base->CFG_OUT = CY_GPIO_PRT_DEINIT; + base->INTR_CFG = CY_GPIO_PRT_DEINIT; + base->INTR_MASK = CY_GPIO_PRT_DEINIT; + base->CFG_SIO = CY_GPIO_PRT_DEINIT; + portAddrHSIOM->PORT_SEL0 = CY_GPIO_PRT_DEINIT; + portAddrHSIOM->PORT_SEL1 = CY_GPIO_PRT_DEINIT; +} + +#if defined(__cplusplus) +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.h new file mode 100644 index 0000000000..6b5d97f7e4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.h @@ -0,0 +1,1958 @@ +/***************************************************************************//** +* \file cy_gpio.h +* \version 1.10.1 +* +* \brief +* Provides an API declaration of the GPIO driver +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +/** +* \defgroup group_gpio General Purpose Input Output (GPIO) +* \{ +* The GPIO driver provides an API to configure and access device Input/Output pins. +* IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and +* their variants. +* +* Initialization can be performed either at the port level or by configuring the +* individual pins. For efficient use of code space, port +* configuration should be used in the field. Refer to the product device header files +* for the list of supported ports and pins. +* +* - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit +* (provide specific values) or \ref Cy_GPIO_Pin_Init (provide a filled +* cy_stc_gpio_pin_config_t structure). +* - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled +* cy_stc_gpio_prt_config_t structure. The values in the structure are +* bitfields representing the desired value for each pin in the port. +* - Pin configuration and management is based on the port address and pin number. +* \ref Cy_GPIO_PortToAddr function can optionally be used to calculate the port +* address from the port number at run-time. +* +* Once the pin/port initialization is complete, each pin can be accessed by +* specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API +* functions. +* +* \section group_gpio_configuration Configuration Considerations +* +* 1. Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection. +* This allows the pin to connect to signal sources/sinks throughout the device, +* as defined by the pin HSIOM selection options (en_hsiom_sel_t). +* 2. All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW +* control digital pin only) at Power-On-Reset(POR). +* 3. Some API functions perform read-modify-write operations on shared port +* registers. These functions are not thread safe and care must be taken when +* called by the application. +* +* Multiple pins on a port can be updated using direct port register writes with an +* appropriate port mask. An example is shown below, highlighting the different ways of +* configuring Port 1 pins using, +* +* - Port output data register +* - Port output data set register +* - Port output data clear register +* +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c Cy_GPIO_Snippet +* +* \section group_gpio_more_information More Information +* +* Refer to the technical reference manual (TRM) and the device datasheet. +* +* \section group_gpio_MISRA MISRA-C Compliance] +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
16.7AA pointer parameter in a function prototype should be declared as pointer +* to const if the pointer is not used to modify the addressed object.The objects pointed to by the base addresses of the GPIO port are not always modified. +* While a const qualifier can be used in select scenarios, it brings little benefit +* in adding this to the affected functions.
+* +* \section group_gpio_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.10.1Updated description for the functions: \ref Cy_GPIO_GetInterruptStatus, +* \ref Cy_GPIO_GetInterruptMask, \ref Cy_GPIO_GetInterruptStatusMasked. +* Minor documentation edits. +* Documentation update and clarification
1.10Added input parameter validation to the API functions
1.0Initial version
+* +* \defgroup group_gpio_macros Macros +* \defgroup group_gpio_functions Functions +* \{ +* \defgroup group_gpio_functions_init Initialization Functions +* \defgroup group_gpio_functions_gpio GPIO Functions +* \defgroup group_gpio_functions_sio SIO Functions +* \defgroup group_gpio_functions_interrupt Port Interrupt Functions +* \} +* \defgroup group_gpio_data_structures Data Structures +* \defgroup group_gpio_enums Enumerated Types +*/ + +#if !defined(CY_GPIO_H) +#define CY_GPIO_H + +#include +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_gpio_macros +* \{ +*/ + +/** Driver major version */ +#define CY_GPIO_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_GPIO_DRV_VERSION_MINOR 10 + +/** GPIO driver ID */ +#define CY_GPIO_ID CY_PDL_DRV_ID(0x16u) + +/** \} group_gpio_macros */ + + +/*************************************** +* Enumerations +***************************************/ +/** +* \addtogroup group_gpio_enums +* \{ +*/ + +/** +* GPIO Driver error codes +*/ +typedef enum +{ + CY_GPIO_SUCCESS = 0x00u, /**< Returned successful */ + CY_GPIO_BAD_PARAM = CY_GPIO_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */ +} cy_en_gpio_status_t; + +/** \} group_gpio_enums */ + + +/*************************************** +* Configuration Structures +***************************************/ + +/** +* \addtogroup group_gpio_data_structures +* \{ +*/ + +/** This structure is used to initialize a port of GPIO pins */ +typedef struct { + uint32_t out; /**< Initial output data for the IO pins in the port */ + uint32_t intrMask; /**< Interrupt enable mask for the port interrupt */ + uint32_t intrCfg; /**< Port pin interrupt edge detection configuration */ + uint32_t cfg; /**< Port pin drive modes and input buffer enable configuration */ + uint32_t cfgIn; /**< Port pin input buffer configuration */ + uint32_t cfgOut; /**< Port pin output buffer configuration */ + uint32_t cfgSIO; /**< Port SIO pins configuration */ + uint32_t sel0Active; /**< HSIOM selection for port pins 0,1,2,3 */ + uint32_t sel1Active; /**< HSIOM selection for port pins 4,5,6,7 */ +} cy_stc_gpio_prt_config_t; + +/** This structure is used to initialize a single GPIO pin */ +typedef struct { + uint32_t outVal; /**< Pin output state */ + uint32_t driveMode; /**< Drive mode */ + en_hsiom_sel_t hsiom; /**< HSIOM selection */ + uint32_t intEdge; /**< Interrupt Edge type */ + uint32_t intMask; /**< Interrupt enable mask */ + uint32_t vtrip; /**< Input buffer voltage trip type */ + uint32_t slewRate; /**< Output buffer slew rate */ + uint32_t driveSel; /**< Drive strength */ + uint32_t vregEn; /**< SIO pair output buffer mode */ + uint32_t ibufMode; /**< SIO pair input buffer mode */ + uint32_t vtripSel; /**< SIO pair input buffer trip point */ + uint32_t vrefSel; /**< SIO pair reference voltage for input buffer trip point */ + uint32_t vohSel; /**< SIO pair regulated voltage output level */ +} cy_stc_gpio_pin_config_t; + +/** \} group_gpio_data_structures */ + +/*************************************** +* Constants +***************************************/ + +/** \cond INTERNAL */ + +/* General Constants */ +#define CY_GPIO_PRT_HALF (4UL) /**< Half-way point of a GPIO port */ +#define CY_GPIO_PRT_DEINIT (0UL) /**< De-init value for port registers */ + +/* GPIO Masks */ +#define CY_GPIO_HSIOM_MASK (0x1FUL) /**< HSIOM selection mask */ +#define CY_GPIO_OUT_MASK (0x01UL) /**< Single pin mask for OUT register */ +#define CY_GPIO_IN_MASK (0x01UL) /**< Single pin mask for IN register */ +#define CY_GPIO_CFG_DM_MASK (0x0FUL) /**< Single pin mask for drive mode in CFG register */ +#define CY_GPIO_CFG_IN_VTRIP_SEL_MASK (0x01UL) /**< Single pin mask for VTRIP selection in CFG IN register */ +#define CY_GPIO_CFG_OUT_SLOW_MASK (0x01UL) /**< Single pin mask for slew rate in CFG OUT register */ +#define CY_GPIO_CFG_OUT_DRIVE_SEL_MASK (0x03UL) /**< Single pin mask for drive strength in CFG OUT register */ +#define CY_GPIO_INTR_STATUS_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */ +#define CY_GPIO_INTR_EN_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */ +#define CY_GPIO_INTR_MASKED_MASK (0x01UL) /**< Single pin mask for masked interrupt status in INTR_MASKED register */ +#define CY_GPIO_INTR_SET_MASK (0x01UL) /**< Single pin mask for setting the interrupt in INTR_MASK register */ +#define CY_GPIO_INTR_EDGE_MASK (0x03UL) /**< Single pin mask for interrupt edge type in INTR_EDGE register */ +#define CY_GPIO_INTR_FLT_EDGE_MASK (0x07UL) /**< Single pin mask for setting filtered interrupt */ + +/* SIO Masks */ +#define CY_GPIO_VREG_EN_MASK (0x01UL) /**< Single SIO pin mask for voltage regulation enable */ +#define CY_GPIO_IBUF_MASK (0x01UL) /**< Single SIO pin mask for input buffer */ +#define CY_GPIO_IBUF_SHIFT (0x01UL) /**< Single SIO pin shift for input buffer */ +#define CY_GPIO_VTRIP_SEL_MASK (0x01UL) /**< Single SIO pin mask for the input buffer trip point */ +#define CY_GPIO_VTRIP_SEL_SHIFT (0x02UL) /**< Single SIO pin shift for the input buffer trip point */ +#define CY_GPIO_VREF_SEL_MASK (0x03UL) /**< Single SIO pin mask for voltage reference */ +#define CY_GPIO_VREF_SEL_SHIFT (0x03UL) /**< Single SIO pin shift for voltage reference */ +#define CY_GPIO_VOH_SEL_MASK (0x07UL) /**< Single SIO pin mask for VOH */ +#define CY_GPIO_VOH_SEL_SHIFT (0x05UL) /**< Single SIO pin shift for VOH */ + +/* Special mask for SIO pin pair setting */ +#define CY_GPIO_SIO_ODD_PIN_MASK (0x00FEUL) /**< SIO pin pair selection mask */ +#define CY_GPIO_SIO_PIN_MASK (0x00FFUL) /**< SIO pin pair mask */ + +/* Offsets */ +#define CY_GPIO_HSIOM_OFFSET (3UL) /**< Offset for HSIOM */ +#define CY_GPIO_DRIVE_MODE_OFFSET (2UL) /**< Offset for Drive mode */ +#define CY_GPIO_INBUF_OFFSET (3UL) /**< Offset for input buffer */ +#define CY_GPIO_CFG_OUT_DRIVE_OFFSET (16UL) /**< Offset for drive strength */ +#define CY_GPIO_INTR_CFG_OFFSET (1UL) /**< Offset for interrupt config */ +#define CY_GPIO_INTR_FILT_OFFSET (18UL) /**< Offset for filtered interrupt config */ +#define CY_GPIO_CFG_SIO_OFFSET (2UL) /**< Offset for SIO config */ + +/* Parameter validation constants */ +#define CY_GPIO_PINS_MAX (8UL) /**< Number of pins in the port */ +#define CY_GPIO_PRT_PINS_MASK (0x0000000FFUL) +#define CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK (GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk | \ + GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk | \ + GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk | \ + GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk | \ + GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk | \ + GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk | \ + GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk | \ + GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk) +#define CY_GPIO_PRT_INTR_CFG_RANGE_MASK (CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK | \ + GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk | \ + GPIO_PRT_INTR_CFG_FLT_SEL_Msk) +#define CY_GPIO_PRT_INT_MASK_MASK (0x0000001FFUL) +#define CY_GPIO_PRT_SEL_ACTIVE_MASK (0x1FFFFFFFUL) + +/* Parameter validation macros */ +#define CY_GPIO_IS_PIN_VALID(pinNum) (CY_GPIO_PINS_MAX > (pinNum)) +#define CY_GPIO_IS_FILTER_PIN_VALID(pinNum) (CY_GPIO_PINS_MAX >= (pinNum)) +#define CY_GPIO_IS_VALUE_VALID(outVal) (1UL >= (outVal)) +#define CY_GPIO_IS_DM_VALID(driveMode) (0U == ((driveMode) & (uint32_t)~CY_GPIO_CFG_DM_MASK)) + +#define CY_GPIO_IS_HSIOM_VALID(hsiom) (0U == ((hsiom) & (uint32_t)~CY_GPIO_HSIOM_MASK)) + +#define CY_GPIO_IS_INT_EDGE_VALID(intEdge) ((CY_GPIO_INTR_DISABLE == (intEdge)) || \ + (CY_GPIO_INTR_RISING == (intEdge)) || \ + (CY_GPIO_INTR_FALLING == (intEdge)) || \ + (CY_GPIO_INTR_BOTH == (intEdge))) + +#define CY_GPIO_IS_DRIVE_SEL_VALID(driveSel) ((CY_GPIO_DRIVE_FULL == (driveSel)) || \ + (CY_GPIO_DRIVE_1_2 == (driveSel)) || \ + (CY_GPIO_DRIVE_1_4 == (driveSel)) || \ + (CY_GPIO_DRIVE_1_8 == (driveSel))) + +#define CY_GPIO_IS_VREF_SEL_VALID(vrefSel) ((CY_SIO_VREF_PINREF == (vrefSel)) || \ + (CY_SIO_VREF_1_2V == (vrefSel)) || \ + (CY_SIO_VREF_AMUX_A == (vrefSel)) || \ + (CY_SIO_VREF_AMUX_B == (vrefSel))) + +#define CY_GPIO_IS_VOH_SEL_VALID(vrefSel) ((CY_SIO_VOH_1_00 == (vrefSel)) || \ + (CY_SIO_VOH_1_25 == (vrefSel)) || \ + (CY_SIO_VOH_1_49 == (vrefSel)) || \ + (CY_SIO_VOH_1_67 == (vrefSel)) || \ + (CY_SIO_VOH_2_08 == (vrefSel)) || \ + (CY_SIO_VOH_2_50 == (vrefSel)) || \ + (CY_SIO_VOH_2_78 == (vrefSel)) || \ + (CY_SIO_VOH_4_16 == (vrefSel))) + +#define CY_GPIO_IS_PIN_BIT_VALID(pinBit) (0U == ((pinBit) & (uint32_t)~CY_GPIO_PRT_PINS_MASK)) +#define CY_GPIO_IS_INTR_CFG_VALID(intrCfg) (0U == ((intrCfg) & (uint32_t)~CY_GPIO_PRT_INTR_CFG_RANGE_MASK)) +#define CY_GPIO_IS_INTR_MASK_VALID(intrMask) (0U == ((intrMask) & (uint32_t)~CY_GPIO_PRT_INT_MASK_MASK)) +#define CY_GPIO_IS_SEL_ACT_VALID(selActive) (0U == ((selActive) & (uint32_t)~CY_GPIO_PRT_SEL_ACTIVE_MASK)) + +/** \endcond */ + + +/*************************************** +* Function Constants +***************************************/ + +/** +* \addtogroup group_gpio_macros +* \{ +*/ + +/** +* \defgroup group_gpio_driveModes Pin drive mode +* \{ +* Constants to be used for setting the drive mode of the pin. +*/ +#define CY_GPIO_DM_ANALOG (0x00UL) /**< \brief Analog High-Z. Input buffer off */ +#define CY_GPIO_DM_PULLUP_IN_OFF (0x02UL) /**< \brief Resistive Pull-Up. Input buffer off */ +#define CY_GPIO_DM_PULLDOWN_IN_OFF (0x03UL) /**< \brief Resistive Pull-Down. Input buffer off */ +#define CY_GPIO_DM_OD_DRIVESLOW_IN_OFF (0x04UL) /**< \brief Open Drain, Drives Low. Input buffer off */ +#define CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF (0x05UL) /**< \brief Open Drain, Drives High. Input buffer off */ +#define CY_GPIO_DM_STRONG_IN_OFF (0x06UL) /**< \brief Strong Drive. Input buffer off */ +#define CY_GPIO_DM_PULLUP_DOWN_IN_OFF (0x07UL) /**< \brief Resistive Pull-Up/Down. Input buffer off */ +#define CY_GPIO_DM_HIGHZ (0x08UL) /**< \brief Digital High-Z. Input buffer on */ +#define CY_GPIO_DM_PULLUP (0x0AUL) /**< \brief Resistive Pull-Up. Input buffer on */ +#define CY_GPIO_DM_PULLDOWN (0x0BUL) /**< \brief Resistive Pull-Down. Input buffer on */ +#define CY_GPIO_DM_OD_DRIVESLOW (0x0CUL) /**< \brief Open Drain, Drives Low. Input buffer on */ +#define CY_GPIO_DM_OD_DRIVESHIGH (0x0DUL) /**< \brief Open Drain, Drives High. Input buffer on */ +#define CY_GPIO_DM_STRONG (0x0EUL) /**< \brief Strong Drive. Input buffer on */ +#define CY_GPIO_DM_PULLUP_DOWN (0x0FUL) /**< \brief Resistive Pull-Up/Down. Input buffer on */ +/** \} */ + +/** +* \defgroup group_gpio_vtrip Voltage trip mode +* \{ +* Constants to be used for setting the voltage trip type on the pin. +*/ +#define CY_GPIO_VTRIP_CMOS (0x00UL) /**< \brief Input buffer compatible with CMOS and I2C interfaces */ +#define CY_GPIO_VTRIP_TTL (0x01UL) /**< \brief Input buffer compatible with TTL and MediaLB interfaces */ +/** \} */ + +/** +* \defgroup group_gpio_slewRate Slew Rate Mode +* \{ +* Constants to be used for setting the slew rate of the pin. +*/ +#define CY_GPIO_SLEW_FAST (0x00UL) /**< \brief Fast slew rate */ +#define CY_GPIO_SLEW_SLOW (0x01UL) /**< \brief Slow slew rate */ +/** \} */ + +/** +* \defgroup group_gpio_driveStrength Pin drive strength +* \{ +* Constants to be used for setting the drive strength of the pin. +*/ +#define CY_GPIO_DRIVE_FULL (0x00UL) /**< \brief Full drive strength: Max drive current */ +#define CY_GPIO_DRIVE_1_2 (0x01UL) /**< \brief 1/2 drive strength: 1/2 drive current */ +#define CY_GPIO_DRIVE_1_4 (0x02UL) /**< \brief 1/4 drive strength: 1/4 drive current */ +#define CY_GPIO_DRIVE_1_8 (0x03UL) /**< \brief 1/8 drive strength: 1/8 drive current */ +/** \} */ + +/** +* \defgroup group_gpio_interruptTrigger Interrupt trigger type +* \{ +* Constants to be used for setting the interrupt trigger type on the pin. +*/ +#define CY_GPIO_INTR_DISABLE (0x00UL) /**< \brief Disable the pin interrupt generation */ +#define CY_GPIO_INTR_RISING (0x01UL) /**< \brief Rising-Edge interrupt */ +#define CY_GPIO_INTR_FALLING (0x02UL) /**< \brief Falling-Edge interrupt */ +#define CY_GPIO_INTR_BOTH (0x03UL) /**< \brief Both-Edge interrupt */ +/** \} */ + +/** +* \defgroup group_gpio_sioVreg SIO output buffer mode +* \{ +* Constants to be used for setting the SIO output buffer mode on the pin. +*/ +#define CY_SIO_VREG_UNREGULATED (0x00UL) /**< \brief Unregulated output buffer */ +#define CY_SIO_VREG_REGULATED (0x01UL) /**< \brief Regulated output buffer */ +/** \} */ + +/** +* \defgroup group_gpio_sioIbuf SIO input buffer mode +* \{ +* Constants to be used for setting the SIO input buffer mode on the pin. +*/ +#define CY_SIO_IBUF_SINGLEENDED (0x00UL) /**< \brief Single ended input buffer */ +#define CY_SIO_IBUF_DIFFERENTIAL (0x01UL) /**< \brief Differential input buffer */ +/** \} */ + +/** +* \defgroup group_gpio_sioVtrip SIO input buffer trip-point +* \{ +* Constants to be used for setting the SIO input buffer trip-point of the pin. +*/ +#define CY_SIO_VTRIP_CMOS (0x00UL) /**< \brief CMOS input buffer (single-ended) */ +#define CY_SIO_VTRIP_TTL (0x01UL) /**< \brief TTL input buffer (single-ended) */ +#define CY_SIO_VTRIP_0_5VDDIO_0_5VOH (0x00UL) /**< \brief 0.5xVddio or 0.5xVoh (differential) */ +#define CY_SIO_VTRIP_0_4VDDIO_1_0VREF (0x01UL) /**< \brief 0.4xVddio or 0.4xVoh (differential) */ +/** \} */ + +/** +* \defgroup group_gpio_sioVref SIO reference voltage for input buffer trip-point +* \{ +* Constants to be used for setting the reference voltage of SIO input buffer trip-point. +*/ +#define CY_SIO_VREF_PINREF (0x00UL) /**< \brief Vref from analog pin */ +#define CY_SIO_VREF_1_2V (0x01UL) /**< \brief Vref from internal 1.2V reference */ +#define CY_SIO_VREF_AMUX_A (0x02UL) /**< \brief Vref from AMUXBUS_A */ +#define CY_SIO_VREF_AMUX_B (0x03UL) /**< \brief Vref from AMUXBUS_B */ +/** \} */ + +/** +* \defgroup group_gpio_sioVoh Regulated output voltage level (Voh) and input buffer trip-point of an SIO pair +* \{ +* Constants to be used for setting the Voh and input buffer trip-point of an SIO pair +*/ +#define CY_SIO_VOH_1_00 (0x00UL) /**< \brief Voh = 1 x Reference */ +#define CY_SIO_VOH_1_25 (0x01UL) /**< \brief Voh = 1.25 x Reference */ +#define CY_SIO_VOH_1_49 (0x02UL) /**< \brief Voh = 1.49 x Reference */ +#define CY_SIO_VOH_1_67 (0x03UL) /**< \brief Voh = 1.67 x Reference */ +#define CY_SIO_VOH_2_08 (0x04UL) /**< \brief Voh = 2.08 x Reference */ +#define CY_SIO_VOH_2_50 (0x05UL) /**< \brief Voh = 2.50 x Reference */ +#define CY_SIO_VOH_2_78 (0x06UL) /**< \brief Voh = 2.78 x Reference */ +#define CY_SIO_VOH_4_16 (0x07UL) /**< \brief Voh = 4.16 x Reference */ +/** \} */ + +/** \} group_gpio_macros */ + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_gpio_functions +* \{ +*/ + +/** +* \addtogroup group_gpio_functions_init +* \{ +*/ + +cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type* base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config); +cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config); +void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, uint32_t outVal, en_hsiom_sel_t hsiom); +void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base); +__STATIC_INLINE void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value); +__STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum); + +/** \} group_gpio_functions_init */ + +/** +* \addtogroup group_gpio_functions_gpio +* \{ +*/ + +__STATIC_INLINE uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum); + +/** \} group_gpio_functions_gpio */ + +/** +* \addtogroup group_gpio_functions_sio +* \{ +*/ + +__STATIC_INLINE void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum); + +/** \} group_gpio_functions_sio */ + +/** +* \addtogroup group_gpio_functions_interrupt +* \{ +*/ + +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum); +__STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value); +__STATIC_INLINE uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base); + +#if (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) || defined (CY_DOXYGEN) +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void); +#endif /* (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) */ + +#if (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) || defined (CY_DOXYGEN) +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void); +#endif /* (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) */ + +#if (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) || defined (CY_DOXYGEN) +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void); +#endif /* (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) */ + +#if (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) || defined (CY_DOXYGEN) +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void); +#endif /* (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) */ + +/** \} group_gpio_functions_interrupt */ + + +/** +* \addtogroup group_gpio_functions_init +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_GPIO_SetHSIOM +****************************************************************************//** +* +* \brief Configures the HSIOM connection to the pin. +* +* Connects the specified High-Speed Input Output Multiplexer (HSIOM) selection +* to the pin. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* HSIOM input selection +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetHSIOM +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value) +{ + uint32_t portNum; + uint32_t tempReg; + HSIOM_PRT_Type* portAddrHSIOM; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(value)); + + portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE; + portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); + + if(pinNum < CY_GPIO_PRT_HALF) + { + tempReg = portAddrHSIOM->PORT_SEL0 & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); + portAddrHSIOM->PORT_SEL0 = tempReg | ((value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); + } + else + { + pinNum -= CY_GPIO_PRT_HALF; + tempReg = portAddrHSIOM->PORT_SEL1 & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); + portAddrHSIOM->PORT_SEL1 = tempReg | ((value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); + } +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetHSIOM +****************************************************************************//** +* +* \brief Returns the current HSIOM multiplexer connection to the pin. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* HSIOM input selection +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetHSIOM +* +*******************************************************************************/ +__STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum) +{ + uint32_t returnValue; + uint32_t portNum; + HSIOM_PRT_Type* portAddrHSIOM; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE; + portAddrHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); + + if(pinNum < CY_GPIO_PRT_HALF) + { + returnValue = (portAddrHSIOM->PORT_SEL0 >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK; + } + else + { + pinNum -= CY_GPIO_PRT_HALF; + returnValue = (portAddrHSIOM->PORT_SEL1 >> (pinNum << CY_GPIO_HSIOM_OFFSET)) & CY_GPIO_HSIOM_MASK; + } + + return (en_hsiom_sel_t)returnValue; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_PortToAddr +****************************************************************************//** +* +* \brief Retrieves the port address based on the given port number. +* +* This is a helper function to calculate the port base address when given a port +* number. It is to be used when pin access needs to be calculated at runtime. +* +* \param portNum +* Port number +* +* \return +* Base address of the port register structure +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_PortToAddr +* +*******************************************************************************/ +__STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum) +{ + GPIO_PRT_Type* base; + + if(portNum < (uint32_t)IOSS_GPIO_GPIO_PORT_NR) + { + base = (GPIO_PRT_Type *)(GPIO_BASE + (GPIO_PRT_SECTION_SIZE * portNum)); + } + else + { + /* Error: Return default base address */ + base = (GPIO_PRT_Type *)(GPIO_BASE); + } + + return (base); +} + +/** \} group_gpio_functions_init */ + +/** +* \addtogroup group_gpio_functions_gpio +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_GPIO_Read +****************************************************************************//** +* +* \brief Reads the current logic level on the input buffer of the pin. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register. +* Bit position 8 is the routed pin through the port glitch filter. +* +* \return +* Logic level present on the pin +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Read +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); + + return (base->IN >> (pinNum)) & CY_GPIO_IN_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Write +****************************************************************************//** +* +* \brief Write a logic 0 or logic 1 state to the output driver. +* +* This function should be used only for software driven pins. It does not have +* any effect on peripheral driven pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Logic level to drive out on the pin +* +* \return +* void +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Write +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value)); + + /* Thread-safe: Directly access the pin registers instead of base->OUT */ + if(0UL == value) + { + base->OUT_CLR = CY_GPIO_OUT_MASK << pinNum; + } + else + { + base->OUT_SET = CY_GPIO_OUT_MASK << pinNum; + } +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_ReadOut +****************************************************************************//** +* +* \brief Reads the current logic level on the pin output driver. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Logic level on the pin output driver +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_ReadOut +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + return (base->OUT >> pinNum) & CY_GPIO_OUT_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Set +****************************************************************************//** +* +* \brief Set a pin output to logic state high. +* +* This function should be used only for software driven pins. It does not have +* any effect on peripheral driven pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* void +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Set +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + base->OUT_SET = CY_GPIO_OUT_MASK << pinNum; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Clr +****************************************************************************//** +* +* \brief Set a pin output to logic state Low. +* +* This function should be used only for software driven pins. It does not have +* any effect on peripheral driven pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* void +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Clr +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + base->OUT_CLR = CY_GPIO_OUT_MASK << pinNum; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_Inv +****************************************************************************//** +* +* \brief Set a pin output logic state to the inverse of the current output +* logic state. +* +* This function should be used only for software driven pins. It does not have +* any effect on peripheral driven pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* void +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_Inv +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + base->OUT_INV = CY_GPIO_OUT_MASK << pinNum; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetDrivemode +****************************************************************************//** +* +* \brief Configures the pin output buffer drive mode and input buffer enable. +* +* The output buffer drive mode and input buffer enable are combined into a single +* parameter. The drive mode controls the behavior of the pin in general. +* Enabling the input buffer allows the digital pin state to be read but also +* contributes to extra current consumption. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetDrivemode +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(value)); + + pinLoc = pinNum << CY_GPIO_DRIVE_MODE_OFFSET; + tempReg = (base->CFG & ~(CY_GPIO_CFG_DM_MASK << pinLoc)); + base->CFG = tempReg | ((value & CY_GPIO_CFG_DM_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetDrivemode +****************************************************************************//** +* +* \brief Returns the pin output buffer drive mode and input buffer enable state. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Pin drive mode. Options are detailed in \ref group_gpio_driveModes macros +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetDrivemode +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + return (base->CFG >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetVtrip +****************************************************************************//** +* +* \brief Configures the GPIO pin input buffer voltage threshold mode. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVtrip +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value)); + + tempReg = base->CFG_IN & ~(CY_GPIO_CFG_IN_VTRIP_SEL_MASK << pinNum); + base->CFG_IN = tempReg | ((value & CY_GPIO_CFG_IN_VTRIP_SEL_MASK) << pinNum); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetVtrip +****************************************************************************//** +* +* \brief Returns the pin input buffer voltage threshold mode. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Pin voltage threshold mode. Options are detailed in \ref group_gpio_vtrip macros +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVtrip +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + return (base->CFG_IN >> pinNum) & CY_GPIO_CFG_IN_VTRIP_SEL_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetSlewRate +****************************************************************************//** +* +* \brief Configures the pin output buffer slew rate. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetSlewRate +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value)); + + tempReg = base->CFG_OUT & ~(CY_GPIO_CFG_OUT_SLOW_MASK << pinNum); + base->CFG_OUT = tempReg | ((value & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetSlewRate +****************************************************************************//** +* +* \brief Returns the pin output buffer slew rate. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Pin slew rate. Options are detailed in \ref group_gpio_slewRate macros +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetSlewRate +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + return (base->CFG_OUT >> pinNum) & CY_GPIO_CFG_OUT_SLOW_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetDriveSel +****************************************************************************//** +* +* \brief Configures the pin output buffer drive strength. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetDriveSel +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(value)); + + pinLoc = (uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET; + tempReg = base->CFG_OUT & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc); + base->CFG_OUT = tempReg | ((value & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetDriveSel +****************************************************************************//** +* +* \brief Returns the pin output buffer drive strength. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* Pin drive strength. Options are detailed in \ref group_gpio_driveStrength macros +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetDriveSel +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + return ((base->CFG_OUT >> ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET)) + & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK); +} + +/** \} group_gpio_functions_gpio */ + +/** +* \addtogroup group_gpio_functions_sio +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_GPIO_SetVregEn +****************************************************************************//** +* +* \brief Configures the SIO pin pair output buffer regulation mode. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVregEn +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value)); + + pinLoc = (pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET; + tempReg = base->CFG_SIO & ~(CY_GPIO_VREG_EN_MASK << pinLoc); + base->CFG_SIO = tempReg | ((value & CY_GPIO_VREG_EN_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetVregEn +****************************************************************************//** +* +* \brief Returns the SIO pin pair output buffer regulation mode. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* SIO pair output buffer regulator mode. Options are detailed in \ref group_gpio_sioVreg macros +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVregEn +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + return (base->CFG_SIO >> ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET)) & CY_GPIO_VREG_EN_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetIbufMode +****************************************************************************//** +* +* \brief Configures the SIO pin pair input buffer mode. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetIbufMode +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value)); + + pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT; + tempReg = (base->CFG_SIO & ~(CY_GPIO_IBUF_MASK << pinLoc)); + base->CFG_SIO = tempReg | ((value & CY_GPIO_IBUF_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetIbufMode +****************************************************************************//** +* +* \brief Returns the SIO pin pair input buffer mode. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* SIO pair input buffer mode. Options are detailed in \ref group_gpio_sioIbuf macros +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetIbufMode +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT)) & CY_GPIO_IBUF_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetVtripSel +****************************************************************************//** +* +* \brief Configures the SIO pin pair input buffer trip point. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVtripSel +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value)); + + pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT; + tempReg = (base->CFG_SIO & ~(CY_GPIO_VTRIP_SEL_MASK << pinLoc)); + base->CFG_SIO = tempReg | ((value & CY_GPIO_VTRIP_SEL_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetVtripSel +****************************************************************************//** +* +* \brief Returns the SIO pin pair input buffer trip point. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* SIO pair input buffer trip point. Options are detailed in \ref group_gpio_sioVtrip macros +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVtripSel +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VTRIP_SEL_SHIFT)) & CY_GPIO_VTRIP_SEL_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetVrefSel +****************************************************************************//** +* +* \brief Configures the SIO reference voltage for the input buffer trip point. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVrefSel +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(value)); + + pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT; + tempReg = (base->CFG_SIO & ~(CY_GPIO_VREF_SEL_MASK << pinLoc)); + base->CFG_SIO = tempReg | ((value & CY_GPIO_VREF_SEL_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetVrefSel +****************************************************************************//** +* +* \brief Returns the SIO reference voltage for the input buffer trip point. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVref macros +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVrefSel +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT)) & CY_GPIO_VREF_SEL_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetVohSel +****************************************************************************//** +* +* \brief Configures the regulated output reference multiplier for the SIO pin pair. +* +* The regulated output reference controls both the output level of digital output +* pin and the input trip point of digital input pin in the SIO pair. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \param value +* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVohSel +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(value)); + + pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT; + tempReg = (base->CFG_SIO & ~(CY_GPIO_VOH_SEL_MASK << pinLoc)); + base->CFG_SIO = tempReg | ((value & CY_GPIO_VOH_SEL_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetVohSel +****************************************************************************//** +* +* \brief Returns the regulated output reference multiplier for the SIO pin pair. +* +* Note that this function has no effect on non-SIO pins. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* +* \return +* SIO pair reference voltage. Options are detailed in \ref group_gpio_sioVoh macros +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetVohSel +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); + + return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT)) & CY_GPIO_VOH_SEL_MASK; +} + +/** \} group_gpio_functions_sio */ + +/** +* \addtogroup group_gpio_functions_interrupt +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptStatus +****************************************************************************//** +* +* \brief Returns the current unmasked interrupt state of the pin. +* +* The core processor's NVIC is triggered by the masked interrupt bits. This +* function allows reading the unmasked interrupt state. Whether the bit +* positions actually trigger the interrupt are defined by the interrupt mask bits. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* Bit position 8 is the routed pin through the port glitch filter. +* +* \return +* 0 = Pin interrupt condition not detected +* 1 = Pin interrupt condition detected +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_GetInterruptStatus +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); + + return (base->INTR >> pinNum) & CY_GPIO_INTR_STATUS_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_ClearInterrupt +****************************************************************************//** +* +* \brief Clears the triggered pin interrupt. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register +* Bit position 8 is the routed pin through the port glitch filter. +* +* \return +* void +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_ClearInterrupt +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); + + /* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */ + (void)base->INTR; + + base->INTR = CY_GPIO_INTR_STATUS_MASK << pinNum; + + /* This read ensures that the initial write has been flushed out to the hardware */ + (void)base->INTR; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetInterruptMask +****************************************************************************//** +* +* \brief Configures the pin interrupt to be forwarded to the CPU NVIC. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register. +* Bit position 8 is the routed pin through the port glitch filter. +* +* \param value +* 0 = Pin interrupt not forwarded to CPU interrupt controller +* 1 = Pin interrupt masked and forwarded to CPU interrupt controller +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetInterruptMask +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + + CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(value)); + + tempReg= base->INTR_MASK & ~(CY_GPIO_INTR_EN_MASK << pinNum); + base->INTR_MASK = tempReg | ((value & CY_GPIO_INTR_EN_MASK) << pinNum); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptMask +****************************************************************************//** +* +* \brief Returns the state of the pin interrupt mask. +* +* This mask is used to determine whether the pin is configured to be forwarded +* to the CPU NVIC. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register. +* Bit position 8 is the routed pin through the port glitch filter. +* +* \return +* 0 = Pin interrupt not forwarded to CPU interrupt controller +* 1 = Pin interrupt masked and forwarded to CPU interrupt controller +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetInterruptMask +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); + + return (base->INTR_MASK >> pinNum) & CY_GPIO_INTR_EN_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptStatusMasked +****************************************************************************//** +* +* \brief Return the pin's current interrupt state after being masked. +* +* The core processor's NVIC is triggered by the masked interrupt bits. This +* function allows reading this masked interrupt state. Note that the bits that +* are not masked will not be forwarded to the NVIC. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register. +* Bit position 8 is the routed pin through the port glitch filter. +* +* \return +* 0 = Pin interrupt not detected or not forwarded to CPU interrupt controller +* 1 = Pin interrupt detected and forwarded to CPU interrupt controller +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_GetInterruptStatusMasked +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); + + return (base->INTR_MASKED >> pinNum) & CY_GPIO_INTR_MASKED_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetSwInterrupt +****************************************************************************//** +* +* \brief Force a pin interrupt to trigger. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register. +* Bit position 8 is the routed pin through the port glitch filter. +* +* \return +* void +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetSwInterrupt +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); + + base->INTR_SET = CY_GPIO_INTR_SET_MASK << pinNum; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetInterruptEdge +****************************************************************************//** +* +* \brief Configures the type of edge that will trigger a pin interrupt. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register. +* Bit position 8 is the routed pin through the port glitch filter. +* +* \param value +* Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetInterruptEdge +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value) +{ + uint32_t tempReg; + uint32_t pinLoc; + + CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); + CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(value)); + + pinLoc = pinNum << CY_GPIO_INTR_CFG_OFFSET; + tempReg = base->INTR_CFG & ~(CY_GPIO_INTR_EDGE_MASK << pinLoc); + base->INTR_CFG = tempReg | ((value & CY_GPIO_INTR_EDGE_MASK) << pinLoc); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptEdge +****************************************************************************//** +* +* \brief Returns the current pin interrupt edge type. +* +* \param base +* Pointer to the pin's port register base address +* +* \param pinNum +* Position of the pin bit-field within the port register. +* Bit position 8 is the routed pin through the port glitch filter. +* +* \return +* Pin interrupt mode. Options are detailed in \ref group_gpio_interruptTrigger macros +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetInterruptEdge +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum) +{ + CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum)); + + return (base->INTR_CFG >> (pinNum << CY_GPIO_INTR_CFG_OFFSET)) & CY_GPIO_INTR_EDGE_MASK; +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_SetFilter +****************************************************************************//** +* +* \brief Configures which pin on the port connects to the port-specific glitch filter. +* +* Each port contains a single 50ns glitch filter. Any of the pins on the port +* can be routed to this filter such that the input signal is filtered before +* reaching the edge-detect interrupt circuitry. The state of the filterred pin +* can also be read by calling the Cy_GPIO_Read() function. +* +* \param base +* Pointer to the pin's port register base address +* +* \param value +* The number of the port pin to route to the port filter (0...7) +* +* \return +* void +* +* \note +* This function modifies a port register in a read-modify-write operation. It is +* not thread safe as the resource is shared among multiple pins on a port. +* +* \note +* The filtered pin does not have an associated HSIOM connection. Therefore +* it cannot be routed directly to other peripherals in hardware. +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetFilter +* +*******************************************************************************/ +__STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value) +{ + uint32_t tempReg; + + CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(value)); + + tempReg = base->INTR_CFG & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET); + base->INTR_CFG = tempReg | ((value & CY_GPIO_INTR_FLT_EDGE_MASK) << CY_GPIO_INTR_FILT_OFFSET); +} + + +/******************************************************************************* +* Function Name: Cy_GPIO_GetFilter +****************************************************************************//** +* +* \brief Returns which pin is currently configured to connect to the port-specific +* glitch filter. +* +* Each port contains a single 50ns glitch filter. Any of the pins on the port +* can be routed to this filter such that the input signal is filtered before +* reaching the edge-detect interrupt circuitry. The state of the filterred pin +* can also be read by calling the Cy_GPIO_Read() function. +* +* \param base +* Pointer to the pin's port register base address +* +* \return +* The number of the port pin routed to the port filter (0...7) +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_SetFilter +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base) +{ + return (base->INTR_CFG >> CY_GPIO_INTR_FILT_OFFSET) & CY_GPIO_INTR_FLT_EDGE_MASK; +} + + +#if (IOSS_GPIO_GPIO_PORT_NR_0_31 != 0) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptCause0 +****************************************************************************//** +* +* \brief Returns the interrupt status for ports 0 to 31. +* +* \return +* 0 = Interrupt not detected on port +* 1 = Interrupt detected and sent to CPU interrupt controller on port +* +* \funcusage +* \snippet gpio/gpio_v1_10_sut_01.cydsn/main_cm4.c snippet_Cy_GPIO_GetInterruptCause0 +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void) +{ + return GPIO->INTR_CAUSE0; +} + +#endif + +#if (IOSS_GPIO_GPIO_PORT_NR_32_63 != 0) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptCause1 +****************************************************************************//** +* +* \brief Returns the interrupt status for ports 32 to 63. +* +* \return +* 0 = Interrupt not detected on port +* 1 = Interrupt detected and sent to CPU interrupt controller on port +* +* \funcusage +* Refer to the Cy_GPIO_GetInterruptCause0() example. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void) +{ + return GPIO->INTR_CAUSE1; +} + +#endif + +#if (IOSS_GPIO_GPIO_PORT_NR_64_95 != 0) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptCause2 +****************************************************************************//** +* +* \brief Returns the interrupt status for ports 64 to 95. +* +* \return +* 0 = Interrupt not detected on port +* 1 = Interrupt detected and sent to CPU interrupt controller on port +* +* \funcusage +* Refer to the Cy_GPIO_GetInterruptCause0() example. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void) +{ + return GPIO->INTR_CAUSE2; +} + +#endif + +#if (IOSS_GPIO_GPIO_PORT_NR_96_127 != 0) || defined (CY_DOXYGEN) + +/******************************************************************************* +* Function Name: Cy_GPIO_GetInterruptCause3 +****************************************************************************//** +* +* \brief Returns the interrupt status for ports 96 to 127. +* +* \return +* 0 = Interrupt not detected on port +* 1 = Interrupt detected and sent to CPU interrupt controller on port +* +* \funcusage +* Refer to the Cy_GPIO_GetInterruptCause0() example. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void) +{ + return GPIO->INTR_CAUSE3; +} + +#endif + +/** \} group_gpio_functions_interrupt */ + +/** \} group_gpio_functions */ + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_GPIO_H */ + +/** \} group_gpio */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.c new file mode 100644 index 0000000000..38d316dc09 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.c @@ -0,0 +1,287 @@ +/***************************************************************************//** +* \file cy_i2s.c +* \version 2.0.1 +* +* The source code file for the I2S driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "cy_i2s.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_I2S_Init +****************************************************************************//** +* +* Initializes the I2S module in accordance with a configuration structure. +* +* \pre If the I2S module is initialized previously, the \ref Cy_I2S_DeInit() +* must be called before calling this function. +* +* \param base The pointer to the I2S instance address. +* +* \param config The pointer to a configuration structure. +* +* \return error / status code. See \ref cy_en_i2s_status_t. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_Init +* +*******************************************************************************/ +cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config) +{ + cy_en_i2s_status_t ret = CY_I2S_BAD_PARAM; + + if((NULL != base) && (NULL != config)) + { + cy_en_i2s_ws_pw_t wsPulseWidth; + cy_en_i2s_len_t channelLength; + uint32_t channels; + uint32_t clockDiv = (uint32_t)config->clkDiv - 1U; + + CY_ASSERT_L2(CY_I2S_IS_CLK_DIV_VALID(clockDiv)); + + /* The clock setting */ + base->CLOCK_CTL = _VAL2FLD(I2S_CLOCK_CTL_CLOCK_DIV, clockDiv) | + _BOOL2FLD(I2S_CLOCK_CTL_CLOCK_SEL, config->extClk); + + /* The Tx setting */ + if (config->txEnabled) + { + CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->txAlignment)); + CY_ASSERT_L3(CY_I2S_IS_OVHDATA_VALID(config->txOverheadValue)); + + if ((CY_I2S_TDM_MODE_A == config->txAlignment) || (CY_I2S_TDM_MODE_B == config->txAlignment)) + { + channels = (uint32_t)config->txChannels - 1UL; + wsPulseWidth = config->txWsPulseWidth; + channelLength = CY_I2S_LEN32; + + CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels)); + CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth)); + CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->txWordLength)); + } + else + { + channels = 1UL; + wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH; + channelLength = config->txChannelLength; + + CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->txWordLength)); + } + + CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->txFifoTriggerLevel, channels)); + + base->TX_WATCHDOG = config->txWatchdogValue; + + base->TX_CTL = _VAL2FLD(I2S_TX_CTL_I2S_MODE, config->txAlignment) | + _BOOL2FLD(I2S_TX_CTL_B_CLOCK_INV, config->txSdoLatchingTime) | + _VAL2FLD(I2S_TX_CTL_CH_NR, channels) | + _BOOL2FLD(I2S_TX_CTL_MS, config->txMasterMode) | + _VAL2FLD(I2S_TX_CTL_WS_PULSE, wsPulseWidth) | + _BOOL2FLD(I2S_TX_CTL_WD_EN, config->txWatchdogEnable) | + _BOOL2FLD(I2S_TX_CTL_SCKO_POL, config->txSckoInversion) | + _BOOL2FLD(I2S_TX_CTL_SCKI_POL, config->txSckiInversion) | + _VAL2FLD(I2S_TX_CTL_CH_LEN, channelLength) | + _VAL2FLD(I2S_TX_CTL_WORD_LEN, config->txWordLength) | + _VAL2FLD(I2S_TX_CTL_OVHDATA, config->txOverheadValue); + } + + /* The Rx setting */ + if (config->rxEnabled) + { + CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->rxAlignment)); + + if ((CY_I2S_TDM_MODE_A == config->rxAlignment) || (CY_I2S_TDM_MODE_B == config->rxAlignment)) + { + channels = (uint32_t)config->rxChannels - 1UL; + wsPulseWidth = config->rxWsPulseWidth; + channelLength = CY_I2S_LEN32; + + CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels)); + CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth)); + CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->rxWordLength)); + } + else + { + channels = 1UL; + wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH; + channelLength = config->rxChannelLength; + + CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->rxWordLength)); + } + + CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->rxFifoTriggerLevel, channels)); + + base->RX_WATCHDOG = config->rxWatchdogValue; + + base->RX_CTL = _VAL2FLD(I2S_RX_CTL_I2S_MODE, config->rxAlignment) | + _BOOL2FLD(I2S_RX_CTL_B_CLOCK_INV, config->rxSdiLatchingTime) | + _VAL2FLD(I2S_RX_CTL_CH_NR, channels) | + _BOOL2FLD(I2S_RX_CTL_MS, config->rxMasterMode) | + _VAL2FLD(I2S_RX_CTL_WS_PULSE, wsPulseWidth) | + _BOOL2FLD(I2S_RX_CTL_WD_EN, config->rxWatchdogEnable) | + _BOOL2FLD(I2S_RX_CTL_SCKO_POL, config->rxSckoInversion) | + _BOOL2FLD(I2S_RX_CTL_SCKI_POL, config->rxSckiInversion) | + _VAL2FLD(I2S_RX_CTL_CH_LEN, channelLength) | + _VAL2FLD(I2S_RX_CTL_WORD_LEN, config->rxWordLength) | + _BOOL2FLD(I2S_RX_CTL_BIT_EXTENSION, config->rxSignExtension); + } + + /* The I2S enable setting */ + if (config->txEnabled) + { + base->CTL |= I2S_CTL_TX_ENABLED_Msk; + } + + if (config->rxEnabled) + { + base->CTL |= I2S_CTL_RX_ENABLED_Msk; + } + + /* The FIFO setting */ + if (config->txEnabled) + { + base->TX_FIFO_CTL = _VAL2FLD(I2S_TX_FIFO_CTL_TRIGGER_LEVEL, config->txFifoTriggerLevel); + + base->TR_CTL |= _BOOL2FLD(I2S_TR_CTL_TX_REQ_EN, config->txDmaTrigger); + } + + if (config->rxEnabled) + { + base->RX_FIFO_CTL = _VAL2FLD(I2S_RX_FIFO_CTL_TRIGGER_LEVEL, config->rxFifoTriggerLevel); + + base->TR_CTL |= _BOOL2FLD(I2S_TR_CTL_RX_REQ_EN, config->rxDmaTrigger); + } + + ret = CY_I2S_SUCCESS; + } + + return (ret); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_DeInit +****************************************************************************//** +* +* Uninitializes the I2S module (reverts default register values). +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DeInit +* +*******************************************************************************/ +void Cy_I2S_DeInit(I2S_Type * base) +{ + base->INTR_MASK = 0UL; /* Disable interrupts prior to stopping the operation */ + base->CMD = 0UL; + base->TR_CTL = 0UL; + base->TX_FIFO_CTL = 0UL; + base->RX_FIFO_CTL = 0UL; + base->CTL = 0UL; + base->TX_CTL = CY_I2S_TX_CTL_DEFAULT; + base->RX_CTL = CY_I2S_RX_CTL_DEFAULT; + base->TX_WATCHDOG = 0UL; + base->RX_WATCHDOG = 0UL; + base->CLOCK_CTL = 0UL; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_DeepSleepCallback +****************************************************************************//** +* +* This is a callback function to be used at the application layer to +* manage an I2S operation during the Deep-Sleep cycle. It stores the I2S state +* (Tx/Rx enabled/disabled/paused) into the context structure and stops the +* communication before entering into Deep-Sleep power mode and restores the I2S +* state after waking up. +* +* \param +* callbackParams - The pointer to the callback parameters structure, +* see \ref cy_stc_syspm_callback_params_t. +* +* \return the SysPm callback status \ref cy_en_syspm_status_t. +* +* \note Use the \ref cy_stc_i2s_context_t data type for definition of the +* *context element of the \ref cy_stc_syspm_callback_params_t strusture. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DeepSleepCallback +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams) +{ + cy_en_syspm_status_t ret = CY_SYSPM_SUCCESS; + CY_ASSERT_L1(NULL != callbackParams->context); + I2S_Type * locBase = (I2S_Type*) callbackParams->base; + uint32_t * locInterruptMask = (uint32_t*) &(((cy_stc_i2s_context_t*)(callbackParams->context))->interruptMask); + uint32_t * locState = (uint32_t*) &(((cy_stc_i2s_context_t*)(callbackParams->context))->enableState); + + switch(callbackParams->mode) + { + case CY_SYSPM_CHECK_READY: + case CY_SYSPM_CHECK_FAIL: + break; + + case CY_SYSPM_BEFORE_TRANSITION: + *locInterruptMask = Cy_I2S_GetInterruptMask(locBase); /* Store I2S interrupts */ + *locState = Cy_I2S_GetCurrentState(locBase); /* Store I2S state */ + if (0UL != (*locState & I2S_CMD_TX_START_Msk)) + { + Cy_I2S_DisableTx(locBase); /* Stop TX operation */ + } + if (0UL != (*locState & I2S_CMD_RX_START_Msk)) + { + Cy_I2S_DisableRx(locBase); /* Stop RX operation */ + } + Cy_I2S_SetInterruptMask(locBase, 0UL); /* Disable I2S interrupts */ + /* Unload FIFOs in order not to lose data (if needed) */ + break; + + case CY_SYSPM_AFTER_TRANSITION: + if (0UL != (*locState & I2S_CMD_RX_START_Msk)) + { + Cy_I2S_ClearRxFifo(locBase); /* Clear the RX FIFO */ + Cy_I2S_EnableRx(locBase); /* Start RX operation */ + } + if (0UL != (*locState & I2S_CMD_TX_START_Msk)) + { + Cy_I2S_ClearTxFifo(locBase); /* Clear the TX FIFO */ + Cy_I2S_WriteTxData(locBase, 0UL); /* Fill at least one TX frame */ + Cy_I2S_WriteTxData(locBase, 0UL); + if (0UL != (*locState & I2S_CMD_TX_PAUSE_Msk)) + { + Cy_I2S_PauseTx(locBase); /* Restore the TX paused state */ + } + Cy_I2S_EnableTx(locBase); /* Start TX operation */ + } + Cy_I2S_ClearInterrupt(locBase, *locInterruptMask); /* Clear possible pending I2S interrupts */ + Cy_I2S_SetInterruptMask(locBase, *locInterruptMask); /* Restore I2S interrupts */ + break; + + default: + ret = CY_SYSPM_FAIL; + break; + } + + return(ret); +} + + +#ifdef __cplusplus +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.h new file mode 100644 index 0000000000..0e89d1a5c4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.h @@ -0,0 +1,1087 @@ +/***************************************************************************//** +* \file cy_i2s.h +* \version 2.0.1 +* +* The header file of the I2S driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +/** +* \defgroup group_i2s Inter-IC Sound (I2S) +* \{ +* The I2S driver provides a function API to manage Inter-IC Sound. I2S is used +* to send digital audio streaming data to external I2S devices, such as audio +* codecs or simple DACs. It can also receive digital audio streaming data. +* +* Features: +* * An industry standard NXP I2S interface. +* * Supports master/slave TX/RX operation. +* * Programmable Channel/Word Lengths. +* * Supports External Clock operation. +* +* The I2S bus is an industry standard. The hardware interface was +* developed by Philips Semiconductors (now NXP Semiconductors). +* +* \section group_i2s_configuration_considerations Configuration Considerations +* +* To set up an I2S, provide the configuration parameters in the +* \ref cy_stc_i2s_config_t structure. +* +* For example, for Tx configuration, set txEnabled to true, configure +* txDmaTrigger (depending on whether DMA is going to be used or not), set +* extClk (if an external clock is used), provide clkDiv, txMasterMode, +* txAlignment, txChannels (only 2 is supported in I2S and Left Justified modes) +* txSdoLatchingTime (for slave mode only), txChannelLength, txWordLength, +* txWsPulseWidth (for TMD modes only), txWatchdogEnable and txWatchdogValue +* (both for Slave mode only, and when the watchdog interrupt will be used), +* either txSckoInversion or txSckiInversion (based on txMasterMode setting), +* txFifoTriggerLevel (when the Trig interrupt will be used) and txOverheadValue +* (only when the word length is less than channel length). +* A similar setup is for the Rx configuration. +* +* To initialize the I2S block, call the \ref Cy_I2S_Init function, providing the +* filled \ref cy_stc_i2s_config_t structure. +* Before starting the transmission, clear the FIFO \ref Cy_I2S_ClearTxFifo, then +* fill the first Tx data frame by calling \ref Cy_I2S_WriteTxData once for each +* channel (e.g. twice for I2S mode with only two channels) with zero data. Then +* call the \ref Cy_I2S_EnableTx itself. +* For the reception the sequence is the same except for filling the first data +* frame, just RX FIFO clearing is enough. +* +* For example: +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_Init +* +* If you use a DMA, the DMA channel should be previously configured. The I2S interrupts +* (if applicable) can be enabled by calling \ref Cy_I2S_SetInterruptMask. +* +* For example, if the trigger interrupt is used, during operation the ISR +* should call the \ref Cy_I2S_WriteTxData as many times as required for your +* FIFO payload, but not more than the FIFO size. Then call \ref Cy_I2S_ClearInterrupt +* with appropriate parameters. +* +* The I2S/Left Justified data formats always contains two data channels. +* They are ordered one-by-one in the FIFOs, left always goes first. +* So in case of mono audio stream transmission, each sample can be put twice +* into the TX FIFO (in this case both channels will sound the same), +* or combined with zeroes: sample1-zero-sample2-zero (in this case only the +* left channel will finally sound, for right-only case zero should go first). +* The TDM frame word order in FIFOs is similar, one-by-one. +* +* If a DMA is used and the DMA channel is properly configured - no CPU activity +* (or any application code) is needed for I2S operation. +* +* The I2S frame appears as: +* \image html i2s_frame.png +* This is an example for the channel length = 32. A similar is for all the rest +* channel lengths, with one limitation: the word length could be less or equal +* to the channel length. See the device Technical Reference Manual (TRM) +* for more details. +* +* \section group_i2s_more_information More Information +* See: the the I2S chapter of the device technical reference manual (TRM); +* I2S_PDL Component datasheet; +* CE218636 - PSOC 6 MCU INTER-IC SOUND (I2S) EXAMPLE. +* +* \section group_i2s_MISRA MISRA-C Compliance +* The I2S driver has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to the object type and +* a different pointer to the object type.The function \ref Cy_I2S_DeepSleepCallback is a callback of +* \ref cy_en_syspm_status_t type. The cast operation safety in this +* function becomes the user responsibility because the pointer is +* initialized when a callback is registered in the SysPm driver.
+* +* \section group_i2s_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.0.1Added Low Power Callback sectionDocumentation update and clarification
2.0The slave operation is added, Left Justified and TDM modes are added
1.0Initial version
+* +* \defgroup group_i2s_macros Macros +* \defgroup group_i2s_functions Functions +* \{ +* \defgroup group_i2s_functions_syspm_callback Low Power Callback +* \} +* \defgroup group_i2s_data_structures Data Structures +* \defgroup group_i2s_enums Enumerated Types +*/ + + +#if !defined CY_I2S_H +#define CY_I2S_H + +#include +#include +#include "syslib/cy_syslib.h" +#include "syspm/cy_syspm.h" + +#ifndef CY_IP_MXAUDIOSS + #error "The I2S driver is not supported on this device" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** \addtogroup group_i2s_macros +* \{ +*/ + +/** The driver major version */ +#define CY_I2S_DRV_VERSION_MAJOR 2 + +/** The driver minor version */ +#define CY_I2S_DRV_VERSION_MINOR 0 + +/** The I2S driver identifier */ +#define CY_I2S_ID (CY_PDL_DRV_ID(0x20U)) + +/** +* \defgroup group_i2s_macros_intrerrupt_masks Interrupt Masks +* \{ +*/ + +/** Bit 0: Less entries in the TX FIFO than specified by Trigger Level. */ +#define CY_I2S_INTR_TX_TRIGGER (I2S_INTR_TX_TRIGGER_Msk) +/** Bit 1: TX FIFO is not full. */ +#define CY_I2S_INTR_TX_NOT_FULL (I2S_INTR_TX_NOT_FULL_Msk) +/** Bit 4: TX FIFO is empty, i.e. it has 0 entries. */ +#define CY_I2S_INTR_TX_EMPTY (I2S_INTR_TX_EMPTY_Msk) +/** Bit 5: Attempt to write to a full TX FIFO. */ +#define CY_I2S_INTR_TX_OVERFLOW (I2S_INTR_TX_OVERFLOW_Msk) +/** Bit 6: Attempt to read from an empty TX FIFO. +* This happens when the IP is ready to transfer data and TX_EMPTY is '1'. */ +#define CY_I2S_INTR_TX_UNDERFLOW (I2S_INTR_TX_UNDERFLOW_Msk) +/** Bit 8: Tx watchdog event occurs. */ +#define CY_I2S_INTR_TX_WD (I2S_INTR_TX_WD_Msk) +/** Bit 16: More entries in the RX FIFO than specified by Trigger Level. */ +#define CY_I2S_INTR_RX_TRIGGER (I2S_INTR_RX_TRIGGER_Msk) +/** Bit 18: RX FIFO is not empty. */ +#define CY_I2S_INTR_RX_NOT_EMPTY (I2S_INTR_RX_NOT_EMPTY_Msk) +/** Bit 19: RX FIFO is full. */ +#define CY_I2S_INTR_RX_FULL (I2S_INTR_RX_FULL_Msk) +/** Bit 21: Attempt to write to a full RX FIFO. */ +#define CY_I2S_INTR_RX_OVERFLOW (I2S_INTR_RX_OVERFLOW_Msk) +/** Bit 22: Attempt to read from an empty RX FIFO. */ +#define CY_I2S_INTR_RX_UNDERFLOW (I2S_INTR_RX_UNDERFLOW_Msk) +/** Bit 24: Rx watchdog event occurs. */ +#define CY_I2S_INTR_RX_WD (I2S_INTR_RX_WD_Msk) + +/** \} group_i2s_macros_intrerrupt_masks */ + + +/** +* \defgroup group_i2s_macros_current_state Current State +* \{ +*/ + +/** Transmission is active */ +#define CY_I2S_TX_START (I2S_CMD_TX_START_Msk) +/** Transmission is paused */ +#define CY_I2S_TX_PAUSE (I2S_CMD_TX_PAUSE_Msk) +/** Reception is active */ +#define CY_I2S_RX_START (I2S_CMD_RX_START_Msk) + +/** \} group_i2s_macros_current_state */ + +/** \} group_i2s_macros */ + +/** +* \addtogroup group_i2s_enums +* \{ +*/ + +/** +* I2S status definitions. +*/ + +typedef enum +{ + CY_I2S_SUCCESS = 0x00UL, /**< Successful. */ + CY_I2S_BAD_PARAM = CY_I2S_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< One or more invalid parameters. */ +} cy_en_i2s_status_t; + + +/** +* I2S data alignment. +*/ +typedef enum +{ + CY_I2S_LEFT_JUSTIFIED = 0U, /**< Left justified. */ + CY_I2S_I2S_MODE = 1U, /**< I2S mode. */ + CY_I2S_TDM_MODE_A = 2U, /**< TDM mode A. */ + CY_I2S_TDM_MODE_B = 3U /**< TDM mode B. */ +} cy_en_i2s_alignment_t; + +/** +* I2S channel/word length. +*/ +typedef enum +{ + CY_I2S_LEN8 = 0U, /**< Channel/word length: 8 bit. */ + CY_I2S_LEN16 = 1U, /**< Channel/Word length: 16 bit. */ + CY_I2S_LEN18 = 2U, /**< Channel/Word length: 18 bit. */ + CY_I2S_LEN20 = 3U, /**< Channel/Word length: 20 bit. */ + CY_I2S_LEN24 = 4U, /**< Channel/Word length: 24 bit. */ + CY_I2S_LEN32 = 5U /**< Channel/Word length: 32 bit. */ +} cy_en_i2s_len_t; + +/** +* I2S TX overhead value. +*/ +typedef enum +{ + CY_I2S_OVHDATA_ZERO = 0U, /**< Fill overhead bits by zeroes. */ + CY_I2S_OVHDATA_ONE = 1U, /**< Fill overhead bits by ones. */ +} cy_en_i2s_overhead_t; + +/** +* I2S WS pulse width. +*/ +typedef enum +{ + CY_I2S_WS_ONE_SCK_CYCLE = 0U, /**< WS pulse width is one SCK cycle. */ + CY_I2S_WS_ONE_CHANNEL_LENGTH = 1U, /**< WS pulse width is one channel length. */ +} cy_en_i2s_ws_pw_t; + +/** \} group_i2s_enums */ + +/** +* \addtogroup group_i2s_data_structures +* \{ +*/ + +/** +* I2S initialization configuration. +*/ +typedef struct +{ + bool txEnabled; /**< Enables the I2S TX component: 'false': disabled. 'true': enabled. */ + bool rxEnabled; /**< Enables the I2S RX component: 'false': disabled. 'true': enabled. */ + bool txDmaTrigger; /**< 'false': TX DMA trigger disable, 'true': TX DMA trigger enable. */ + bool rxDmaTrigger; /**< 'false': RX DMA trigger disable, 'true': RX DMA trigger enable. */ + uint8_t clkDiv; /**< CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, ..., 64: 1/64. */ + bool extClk; /**< 'false': internal clock, 'true': external clock. */ + bool txMasterMode; /**< 'false': TX in slave mode, 'true': TX in master mode. */ + cy_en_i2s_alignment_t txAlignment; /**< TX data alignment, see: #cy_en_i2s_alignment_t. */ + cy_en_i2s_ws_pw_t txWsPulseWidth; /**< TX Word Select pulse width. + The value of this parameter is ignored in I2S and Left Justified modes + the WS pulse width is always "one channel length" in these modes. */ + bool txWatchdogEnable; /**< 'false': TX watchdog disabled, 'true': TX watchdog enabled. */ + uint32_t txWatchdogValue; /**< TX watchdog counter value (32 bit). */ + bool txSdoLatchingTime; /**< 'false': SDO bit starts at falling edge (accordingly to the I2S + Standard, if txSckoInversion is false), + 'true': SDO bit starts at rising edge which goes before the above + mentioned falling edge, i.e. the SDO signal is advanced by 0.5 SCK + period (if txSckoInversion is false). + If txSckoInversion is true - the rising/falling edges just swaps + in above explanations. + Effective only in slave mode, must be false in master mode.*/ + bool txSckoInversion; /**< TX SCKO polarity: + 'false': When transmitter is in master mode, serial data is + transmitted off the falling bit clock edge (accordingly to + the I2S Standard); + 'true': When transmitter is in master mode, serial data is + transmitted off the rising bit clock edge. + Effective only in master mode. */ + bool txSckiInversion; /**< TX SCKI polarity: + 'false': When transmitter is in slave mode, serial data is + transmitted off the falling bit clock edge (accordingly to + the I2S Standard); + 'true': When transmitter is in slave mode, serial data is + transmitted off the rising bit clock edge. + Effective only in slave mode. */ + uint8_t txChannels; /**< Number of TX channels, valid range is 1...8 for TDM modes. + In the I2S and Left Justified modes the value of this parameter is + ignored - the real number of channels is always 2 in these modes. */ + cy_en_i2s_len_t txChannelLength; /**< TX channel length, see #cy_en_i2s_len_t, + the value of this parameter is ignored in TDM modes, the real + channel length is 32 bit in these modes. */ + cy_en_i2s_len_t txWordLength; /**< TX word length, see #cy_en_i2s_len_t, + must be less or equal to txChannelLength. */ + cy_en_i2s_overhead_t txOverheadValue; /**< TX overhead bits value + when the word length is less than the channel length. */ + uint8_t txFifoTriggerLevel; /**< TX FIFO interrupt trigger level (0, 1, ..., 255). */ + bool rxMasterMode; /**< 'false': RX in slave mode, 'true': RX in master mode. */ + cy_en_i2s_alignment_t rxAlignment; /**< RX data alignment, see: #cy_en_i2s_alignment_t. */ + cy_en_i2s_ws_pw_t rxWsPulseWidth; /**< RX Word Select pulse width. + The value of this parameter is ignored in I2S and Left Justified modes + the WS pulse width is always "one channel length" in these modes. */ + bool rxWatchdogEnable; /**< 'false': RX watchdog disabled, 'true': RX watchdog enabled. */ + uint32_t rxWatchdogValue; /**< RX watchdog counter value (32 bit). */ + bool rxSdiLatchingTime; /**< 'false': SDI bit starts at falling edge (accordingly to the I2S + Standard if rxSckoInversion is false), + 'true': SDI bit starts at rising edge which goes after the above + mentioned falling edge, i.e. the SDI signal is delayed by 0.5 SCK + period (if rxSckoInversion is false). + If rxSckoInversion is true - the rising/falling edges just swaps + in above explanations. + Effective only in master mode, must be false in slave mode. */ + bool rxSckoInversion; /**< RX SCKO polarity: + 'false': When receiver is in master mode, serial data is + captured by the rising bit clock edge (accordingly to the + I2S Standard); + 'true': When receiver is in master mode, serial data is + captured by the falling bit clock edge. + Effective only in master mode. */ + bool rxSckiInversion; /**< RX SCKI polarity: + 'false': When receiver is in slave mode, serial data is + captured by the rising bit clock edge (accordingly to the + I2S Standard); + 'true': When receiver is in slave mode, serial data is + captured by the falling bit clock edge. + Effective only in slave mode. */ + uint8_t rxChannels; /**< Number of RX channels, valid range is 1...8 for TDM modes. + In the I2S and Left Justified modes the value of this parameter is + ignored - the real number of channels is always 2 in these modes. */ + cy_en_i2s_len_t rxChannelLength; /**< RX channel length, see #cy_en_i2s_len_t, + the value of this parameter is ignored in TDM modes, the real + channel length is 32 bit in these modes. */ + cy_en_i2s_len_t rxWordLength; /**< RX word length, see #cy_en_i2s_len_t, + must be less or equal to rxChannelLength. */ + bool rxSignExtension; /**< RX value sign extension (when the word length is less than 32 bits), + 'false': all MSB are filled by zeroes, + 'true': all MSB are filled by the original sign bit value. */ + uint8_t rxFifoTriggerLevel; /**< RX FIFO interrupt trigger level + (0, 1, ..., (255 - (number of channels))). */ +} cy_stc_i2s_config_t; + + +/** + * The I2S backup structure type to be used for the SysPm callback. + * \ref Cy_I2S_DeepSleepCallback context definition. + * + * \cond Also can be used for other purposes to store the current Tx/Rx + * operation state and interrupt settings - the factors that are usually + * changed on the fly. \endcond + */ +typedef struct +{ + uint32_t enableState; /**< Stores the I2S state */ + uint32_t interruptMask; /**< Stores the I2S interrupt mask */ +} cy_stc_i2s_context_t; + +/** \} group_i2s_data_structures */ + +/** \cond INTERNAL */ +/****************************************************************************** + * Local definitions +*******************************************************************************/ + +#define CY_I2S_INTR_MASK (CY_I2S_INTR_TX_TRIGGER | \ + CY_I2S_INTR_TX_NOT_FULL | \ + CY_I2S_INTR_TX_EMPTY | \ + CY_I2S_INTR_TX_OVERFLOW | \ + CY_I2S_INTR_TX_UNDERFLOW | \ + CY_I2S_INTR_TX_WD | \ + CY_I2S_INTR_RX_TRIGGER | \ + CY_I2S_INTR_RX_NOT_EMPTY | \ + CY_I2S_INTR_RX_FULL | \ + CY_I2S_INTR_RX_OVERFLOW | \ + CY_I2S_INTR_RX_UNDERFLOW | \ + CY_I2S_INTR_RX_WD) + +/* Non-zero default values */ +#define CY_I2S_TX_CTL_CH_NR_DEFAULT (0x1U) +#define CY_I2S_TX_CTL_I2S_MODE_DEFAULT (0x2U) +#define CY_I2S_TX_CTL_WS_PULSE_DEFAULT (0x1U) +#define CY_I2S_TX_CTL_CH_LEN_DEFAULT (0x4U) +#define CY_I2S_TX_CTL_WORD_LEN_DEFAULT (0x4U) + +#define CY_I2S_TX_CTL_DEFAULT (_VAL2FLD(I2S_TX_CTL_CH_NR, CY_I2S_TX_CTL_CH_NR_DEFAULT) | \ + _VAL2FLD(I2S_TX_CTL_I2S_MODE, CY_I2S_TX_CTL_I2S_MODE_DEFAULT) | \ + _VAL2FLD(I2S_TX_CTL_WS_PULSE, CY_I2S_TX_CTL_WS_PULSE_DEFAULT) | \ + _VAL2FLD(I2S_TX_CTL_CH_LEN, CY_I2S_TX_CTL_CH_LEN_DEFAULT) | \ + _VAL2FLD(I2S_TX_CTL_WORD_LEN, CY_I2S_TX_CTL_WORD_LEN_DEFAULT)) + +#define CY_I2S_RX_CTL_CH_NR_DEFAULT (0x1U) +#define CY_I2S_RX_CTL_I2S_MODE_DEFAULT (0x2U) +#define CY_I2S_RX_CTL_WS_PULSE_DEFAULT (0x1U) +#define CY_I2S_RX_CTL_CH_LEN_DEFAULT (0x4U) +#define CY_I2S_RX_CTL_WORD_LEN_DEFAULT (0x4U) + +#define CY_I2S_RX_CTL_DEFAULT (_VAL2FLD(I2S_RX_CTL_CH_NR, CY_I2S_RX_CTL_CH_NR_DEFAULT) | \ + _VAL2FLD(I2S_RX_CTL_I2S_MODE, CY_I2S_RX_CTL_I2S_MODE_DEFAULT) | \ + _VAL2FLD(I2S_RX_CTL_WS_PULSE, CY_I2S_RX_CTL_WS_PULSE_DEFAULT) | \ + _VAL2FLD(I2S_RX_CTL_CH_LEN, CY_I2S_RX_CTL_CH_LEN_DEFAULT) | \ + _VAL2FLD(I2S_RX_CTL_WORD_LEN, CY_I2S_RX_CTL_WORD_LEN_DEFAULT)) + +/* Macros for conditions used by CY_ASSERT calls */ +#define CY_I2S_IS_ALIGNMENT_VALID(alignment) ((CY_I2S_LEFT_JUSTIFIED == (alignment)) || \ + (CY_I2S_I2S_MODE == (alignment)) || \ + (CY_I2S_TDM_MODE_A == (alignment)) || \ + (CY_I2S_TDM_MODE_B == (alignment))) + +#define CY_I2S_IS_LEN_VALID(length) ((CY_I2S_LEN8 == (length)) || \ + (CY_I2S_LEN16 == (length)) || \ + (CY_I2S_LEN18 == (length)) || \ + (CY_I2S_LEN20 == (length)) || \ + (CY_I2S_LEN24 == (length)) || \ + (CY_I2S_LEN32 == (length))) + +#define CY_I2S_IS_OVHDATA_VALID(overhead) ((CY_I2S_OVHDATA_ZERO == (overhead)) || \ + (CY_I2S_OVHDATA_ONE == (overhead))) + +#define CY_I2S_IS_WSPULSE_VALID(wsPulse) ((CY_I2S_WS_ONE_SCK_CYCLE == (wsPulse)) || \ + (CY_I2S_WS_ONE_CHANNEL_LENGTH == (wsPulse))) + +#define CY_I2S_IS_CLK_DIV_VALID(clkDiv) ((clkDiv) <= 63U) +#define CY_I2S_IS_CHANNELS_VALID(channels) ((channels) <= 7UL) +#define CY_I2S_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_I2S_INTR_MASK))) + +#define CY_I2S_IS_CHAN_WORD_VALID(channel, word) ((CY_I2S_IS_LEN_VALID(channel)) && \ + (CY_I2S_IS_LEN_VALID(word)) && \ + ((channel) >= (word))) +#define CY_I2S_IS_TRIG_LEVEL_VALID(trigLevel, channels) ((trigLevel) <= (255U - (channels))) + +/** \endcond */ + + +/** +* \addtogroup group_i2s_functions +* \{ +*/ + + cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config); + void Cy_I2S_DeInit(I2S_Type * base); + +/** \addtogroup group_i2s_functions_syspm_callback +* The driver supports SysPm callback for Deep Sleep transition. +* \{ +*/ +cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams); +/** \} */ + +__STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base); +__STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base); + +__STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base); +__STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base); +__STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data); +__STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base); +__STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base); +__STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base); + +__STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base); +__STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base); +__STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base); +__STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base); +__STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base); +__STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base); +__STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base); +__STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base); + +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base); +__STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt); +__STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt); +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base); +__STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt); +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base); + +/******************************************************************************* +* Function Name: Cy_I2S_EnableTx +****************************************************************************//** +* +* Starts an I2S transmission. Interrupts enabling (by the +* \ref Cy_I2S_SetInterruptMask) is required after this function call, in case +* if any I2S interrupts are used in the application. +* +* \pre Cy_I2S_Init() must be called before. +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_EnableTx +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base) +{ + base->CMD |= I2S_CMD_TX_START_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_PauseTx +****************************************************************************//** +* +* Pauses an I2S transmission. +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_PauseTx +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base) +{ + base->CMD |= I2S_CMD_TX_PAUSE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ResumeTx +****************************************************************************//** +* +* Resumes an I2S transmission. +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ResumeTx +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base) +{ + base->CMD &= (uint32_t) ~I2S_CMD_TX_PAUSE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_DisableTx +****************************************************************************//** +* +* Stops an I2S transmission. +* +* \pre TX interrupts disabling (by the \ref Cy_I2S_SetInterruptMask) is required +* prior to this function call, in case if any TX I2S interrupts are used. +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DisableTx +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base) +{ + base->CMD &= (uint32_t) ~I2S_CMD_TX_START_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_EnableRx +****************************************************************************//** +* +* Starts an I2S reception. Interrupts enabling (by the +* \ref Cy_I2S_SetInterruptMask) is required after this function call, in case +* if any I2S interrupts are used in the application. +* +* \pre \ref Cy_I2S_Init() must be called before. +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_EnableRx +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base) +{ + base->CMD |= I2S_CMD_RX_START_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_DisableRx +****************************************************************************//** +* +* Stops an I2S reception. +* +* \pre RX interrupts disabling (by the \ref Cy_I2S_SetInterruptMask) is required +* prior to this function call, in case if any RX I2S interrupts are used. +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_DisableRx +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base) +{ + base->CMD &= (uint32_t) ~I2S_CMD_RX_START_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetCurrentState +****************************************************************************//** +* +* Returns the current I2S state (TX/RX running/paused/stopped). +* +* \param base The pointer to the I2S instance address. +* +* \return The current state \ref group_i2s_macros_current_state. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetCurrentState +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base) +{ + return (base->CMD & (I2S_CMD_TX_START_Msk | I2S_CMD_TX_PAUSE_Msk | I2S_CMD_RX_START_Msk)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ClearTxFifo +****************************************************************************//** +* +* Clears the TX FIFO (resets the Read/Write FIFO pointers). +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearTxFifo +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base) +{ + base->TX_FIFO_CTL |= I2S_TX_FIFO_CTL_CLEAR_Msk; + base->TX_FIFO_CTL &= (uint32_t) ~I2S_TX_FIFO_CTL_CLEAR_Msk; + (void) base->TX_FIFO_CTL; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetNumInTxFifo +****************************************************************************//** +* +* Gets the number of used words in the TX FIFO. +* +* \param base The pointer to the I2S instance address. +* +* \return The current number of used words in the TX FIFO. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetNumInTxFifo +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base) +{ + return (_FLD2VAL(I2S_TX_FIFO_STATUS_USED, base->TX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_WriteTxData +****************************************************************************//** +* +* Writes data to the TX FIFO. Increases the TX FIFO level. +* +* \param base The pointer to the I2S instance address. +* +* \param data Data to be written to the TX FIFO. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_WriteTxData +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_WriteTxData(I2S_Type * base, uint32_t data) +{ + base->TX_FIFO_WR = data; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetTxReadPointer +****************************************************************************//** +* +* Gets the TX FIFO Read pointer. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +* \return The current TX Read pointer value. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetTxReadPointer +* +*******************************************************************************/ +__STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer(I2S_Type const * base) +{ + return ((uint8_t) _FLD2VAL(I2S_TX_FIFO_STATUS_RD_PTR, base->TX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetTxWritePointer +****************************************************************************//** +* +* Gets the TX FIFO Write pointer. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +* \return The current TX Write pointer value. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetTxWritePointer +* +*******************************************************************************/ +__STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer(I2S_Type const * base) +{ + return ((uint8_t) _FLD2VAL(I2S_TX_FIFO_STATUS_WR_PTR, base->TX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_FreezeTxFifo +****************************************************************************//** +* +* Freezes the TX FIFO. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_FreezeTxFifo +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_FreezeTxFifo(I2S_Type * base) +{ + base->TX_FIFO_CTL |= I2S_TX_FIFO_CTL_FREEZE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_UnfreezeTxFifo +****************************************************************************//** +* +* Unfreezes the TX FIFO. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_UnfreezeTxFifo +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_UnfreezeTxFifo(I2S_Type * base) +{ + base->TX_FIFO_CTL &= (uint32_t) ~I2S_TX_FIFO_CTL_FREEZE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ClearRxFifo +****************************************************************************//** +* +* Clears the RX FIFO (resets the Read/Write FIFO pointers). +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearRxFifo +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_ClearRxFifo(I2S_Type * base) +{ + base->RX_FIFO_CTL |= I2S_RX_FIFO_CTL_CLEAR_Msk; + base->RX_FIFO_CTL &= (uint32_t) ~I2S_RX_FIFO_CTL_CLEAR_Msk; + (void) base->RX_FIFO_CTL; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetNumInRxFifo +****************************************************************************//** +* +* Gets the number of used words in the RX FIFO. +* +* \param base The pointer to the I2S instance address. +* +* \return The current number of used words in rge RX FIFO. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetNumInRxFifo +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo(I2S_Type const * base) +{ + return (_FLD2VAL(I2S_RX_FIFO_STATUS_USED, base->RX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ReadRxData +****************************************************************************//** +* +* Reads data from the RX FIFO. Decreases the RX FIFO level. +* +* \param base The pointer to the I2S instance address. +* +* \return The read data. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ReadRxData +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_ReadRxData(I2S_Type const * base) +{ + return (base->RX_FIFO_RD); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ReadRxDataSilent +****************************************************************************//** +* +* Reads data from the RX FIFO without updating the RX FIFO read pointer. +* This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +* \return The read data. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ReadRxDataSilent +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent(I2S_Type const * base) +{ + return (base->RX_FIFO_RD_SILENT); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetRxReadPointer +****************************************************************************//** +* +* Gets the RX FIFO Read pointer. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +* \return The current RX Read pointer value. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetRxReadPointer +* +*******************************************************************************/ +__STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer(I2S_Type const * base) +{ + return ((uint8_t) _FLD2VAL(I2S_RX_FIFO_STATUS_RD_PTR, base->RX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetRxWritePointer +****************************************************************************//** +* +* Gets the RX FIFO Write pointer. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +* \return The current RX Write pointer value. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetRxWritePointer +* +*******************************************************************************/ +__STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer(I2S_Type const * base) +{ + return ((uint8_t) _FLD2VAL(I2S_RX_FIFO_STATUS_WR_PTR, base->RX_FIFO_STATUS)); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_FreezeRxFifo +****************************************************************************//** +* +* Freezes the RX FIFO. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_FreezeRxFifo +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_FreezeRxFifo(I2S_Type * base) +{ + base->RX_FIFO_CTL |= I2S_RX_FIFO_CTL_FREEZE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_UnfreezeRxFifo +****************************************************************************//** +* +* Unfreezes the RX FIFO. This function is rather for debug purposes. +* +* \param base The pointer to the I2S instance address. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_UnfreezeRxFifo +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_UnfreezeRxFifo(I2S_Type * base) +{ + base->RX_FIFO_CTL &= (uint32_t) ~I2S_RX_FIFO_CTL_FREEZE_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetInterruptStatus +****************************************************************************//** +* +* Gets an interrupt status (returns a content of the INTR register). +* +* \param base The pointer to the I2S instance address. +* +* \return The interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetInterruptStatus +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus(I2S_Type const * base) +{ + return (base->INTR); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_ClearInterrupt +****************************************************************************//** +* +* Clears one or more interrupt factors (sets the INTR register). +* +* \param base The pointer to the I2S instance address. +* +* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearInterrupt +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_ClearInterrupt(I2S_Type * base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt)); + base->INTR = interrupt; + (void) base->INTR; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_SetInterrupt +****************************************************************************//** +* +* Sets one or more interrupt factors (sets the INTR_SET register). +* +* \param base The pointer to the I2S instance address. +* +* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_SetInterrupt +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_SetInterrupt(I2S_Type * base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt)); + base->INTR_SET = interrupt; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetInterruptMask +****************************************************************************//** +* +* Returns the interrupt mask (a content of the INTR_MASK register). +* +* \param base The pointer to the I2S instance address. +* +* \return The interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_GetInterruptMask +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask(I2S_Type const * base) +{ + return (base->INTR_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_I2S_SetInterruptMask +****************************************************************************//** +* +* Sets one or more interrupt factor masks (the INTR_MASK register). +* +* \param base The pointer to the I2S instance address. +* +* \param interrupt Interrupt bit mask \ref group_i2s_macros_intrerrupt_masks. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_SetInterruptMask +* +*******************************************************************************/ +__STATIC_INLINE void Cy_I2S_SetInterruptMask(I2S_Type * base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_I2S_IS_INTR_MASK_VALID(interrupt)); + base->INTR_MASK = interrupt; +} + + +/******************************************************************************* +* Function Name: Cy_I2S_GetInterruptStatusMasked +****************************************************************************//** +* +* Returns the interrupt status masked (a content of the INTR_MASKED register). +* +* \param base The pointer to the I2S instance address. +* +* \return The interrupt bit mask(s) \ref group_i2s_macros_intrerrupt_masks. +* +* \funcusage +* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_ClearInterrupt +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base) +{ + return (base->INTR_MASKED); +} + +/** \} group_i2s_functions */ + +#ifdef __cplusplus +} +#endif + +#endif /* CY_I2S_H */ + + +/** \} group_i2s */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.c new file mode 100644 index 0000000000..c6732f2dc6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.c @@ -0,0 +1,170 @@ +/***************************************************************************//** +* \file cy_ipc_drv.c +* \version 1.10.1 +* +* \breif +* IPC Driver - This source file contains the low-level driver code for +* the IPC hardware. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "cy_ipc_drv.h" + + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_LockRelease +****************************************************************************//** +* +* The function is used to release an IPC channel from the locked state. +* The function also has a way to specify through a parameter which IPC +* interrupts must be notified during the release event. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param releaseEventIntr +* Bit encoded list of IPC interrupt lines that are triggered by a release event. +* +* \return Status of the operation +* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC channel +* was released. +* \retval CY_IPC_DRV_ERROR: The IPC channel was not acquired before the +* function call. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgPtr +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type* base, uint32_t releaseEventIntr) +{ + cy_en_ipcdrv_status_t retStatus; + + /* Check to make sure the IPC is Acquired */ + if( Cy_IPC_Drv_IsLockAcquired(base) ) + { + /* The IPC was acquired, release the IPC channel */ + Cy_IPC_Drv_ReleaseNotify(base, releaseEventIntr); + + retStatus = CY_IPC_DRV_SUCCESS; + } + else /* The IPC channel was already released (not acquired) */ + { + retStatus = CY_IPC_DRV_ERROR; + } + + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_SendMsgWord +****************************************************************************//** +* +* This function is used to send a 32-bit word message through an IPC channel. +* The function also has an associated notification field that will let the +* message notify one or multiple IPC interrupts. The IPC channel is locked and +* remains locked after the function returns. The receiver of the message should +* release the channel. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt lines that are triggered by a notification. +* +* \param message +* The message word that is the data placed in the IPC data register. +* +* \return Status of the operation: +* \retval CY_IPC_DRV_SUCCESS: The send operation was successful. +* \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because it is already locked. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgWord +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, uint32_t message) +{ + cy_en_ipcdrv_status_t retStatus; + + if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire(base) ) + { + /* If the channel was acquired, send the message. */ + Cy_IPC_Drv_WriteDataValue(base, message); + + Cy_IPC_Drv_AcquireNotify(base, notifyEventIntr); + + retStatus = CY_IPC_DRV_SUCCESS; + } + else + { + /* Channel was already acquired, return Error */ + retStatus = CY_IPC_DRV_ERROR; + } + return (retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ReadMsgWord +****************************************************************************//** +* +* This function is used to read a 32-bit word message through an IPC channel. +* This function assumes that the channel is locked (for a valid message). +* If the channel is not locked, the message is invalid. The user must call +* Cy_IPC_Drv_Release() function after reading the message to release the +* IPC channel. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param message +* A variable where the read data is copied. +* +* \return Status of the operation +* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC +* was acquired. +* \retval CY_IPC_DRV_ERROR: The function encountered an error because the IPC +* channel was already in a released state, meaning the data +* may be invalid. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgWord +* +*******************************************************************************/ +cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message) +{ + cy_en_ipcdrv_status_t retStatus; + + CY_ASSERT_L1(NULL != message); + + if ( Cy_IPC_Drv_IsLockAcquired(base) ) + { + /* The channel is locked; message is valid. */ + *message = Cy_IPC_Drv_ReadDataValue(base); + + retStatus = CY_IPC_DRV_SUCCESS; + } + else + { + /* The channel is not locked so channel is invalid. */ + retStatus = CY_IPC_DRV_ERROR; + } + return(retStatus); +} + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.h new file mode 100644 index 0000000000..bf8005a7af --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.h @@ -0,0 +1,930 @@ +/***************************************************************************//** +* \file cy_ipc_drv.h +* \version 1.10.1 +* +* Provides an API declaration of the IPC driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#ifndef CY_IPC_DRV_H +#define CY_IPC_DRV_H + + +/** +* \defgroup group_ipc Inter Process Communication (IPC) +* \{ +* The inter-processor communication (IPC) driver provides a safe and reliable +* method to transfer data between CPUs. Hardware locking ensures that only one +* device can acquire and transfer data at a time so no data is lost or +* overwritten by asynchronous processes or CPUs. +* +* There are three parts to the API: +* - Driver-level (DRV) API - used internally by Semaphore and Pipe levels +* - Pipe-level (PIPE) API - establishes a communication channel between +* processors +* - Semaphore-level (SEMA) API - enables users to set and clear flags to +* synchronize operations. +* +* Firmware does not need to use the DRV API. It can implement IPC functionality +* entirely with the PIPE and SEMA APIs. +* +* \section group_ipc_background Background +* +* IPC is implemented in hardware as a collection of individual communication +* channels, each with a set of 32-bit registers. The IPC design implements a set +* of interrupts that enable each processor to notify the other that data is +* available, or has been processed. There is also a locking mechanism that +* allows only one CPU to gain access at a time. +* +* The Driver-level API manages each channel's registers to implement IPC +* functionality. For information on the IPC registers, see the IPC chapter of +* the Technical Reference Manual (TRM). +* +* At the hardware level, communication is a five-step process. +* -# The sending processor acquires a channel +* -# It puts data into the channel +* -# The sender generates a notify event (interrupt) +* -# The receiving processor identifies the sender and retrieves the data +* -# The receiving processor generates a release event (interrupt) +* +* \image html ipc_driver.png +* +* These transactions are handled transparently by the DRV-level API. Use the +* PIPE and SEMA layers of the API to implement communication in your application. +* The data transferred is limited to a single 32-bit value. As implemented by +* the PIPE API, that value is a pointer to a data structure of arbitrary size +* and complexity. +* +* \section group_ipc_overview Overview +* +* The Pipe is the key element in the PDL design. A pipe is typically a +* full-duplex communication channel between CPU cores. A pipe allows a single +* conduit to transfer messages or data to and from multiple processes or CPUs. +* +* A pipe has two endpoints, one on each core. Each endpoint contains a dedicated +* IPC channel and an interrupt. IPC channels 0-7 and IPC interrupts 0-7 are +* reserved for system use. +* +* The pipe also contains the number of clients it supports, and for each client +* a callback function. So the pipe can service a number of clients, each with a +* separate callback function, on either endpoint. The number of clients a pipe +* supports is the sum of each endpoint's clients. +* +* This design enables any number of processes on the sending core to put +* arbitrary data into a single pipe. The first element of that data is the +* client ID of the client that should handle the data. +* +* An interrupt notifies the receiving core that data is available. The receiving +* core parses the data to identify the client, and then dispatches the event to +* the appropriate client via the client callback function. An interrupt notifies +* the sending core that the receiver is finished. In this way a single pipe can +* manage arbitrary data transfers between cores with data flowing in either +* direction. +* +* \image html ipc_ints.png +* +* The application can use semaphores to control access to shared resources, as +* required by the application's logic. +* +* The PDL provides two specific files that set up default IPC functionality. +* They are cy_ipc_config.h and cy_ipc_config.c. You can modify these files based +* on the requirements of your design. If you use PSoC Creator as a development +* environment, it will not overwrite your changes when you generate the +* application or build your code. +* +* \section group_ipc_pipe_layer PIPE layer +* +* A pipe is a communication channel between two endpoints. PSoC 6 devices support +* 16 IPC channels, and 16 IPC interrupts, each numbered 0-15. IPC Channels 0-7 +* and IPC interrupts 0-7 are reserved for system use. Channels 8-15 and +* interrupts 8-15 are available for application use. +* +* A full duplex pipe uses two IPC channels, one per endpoint. Each endpoint +* specifies all the information required to process a message (either sent or +* received). Each endpoint is configured to use an IPC channel, and an IPC +* interrupt. Common practice is to use the interrupt with the same number as +* the IPC channel. However, IPC Interrupts are not directly associated with the +* IPC channels, so any channel can use any interrupt. Any IPC channel can +* trigger 0, 1 or all the IPC interrupts at once, depending on the Notify or +* Release masks used. +* +* It is also possible to set up a one-directional pipe, using a single IPC +* channel. In this design one processor is always the sender, and the other is +* always the receiver. However, there are still two endpoints. +* +* A pipe supports an arbitrary number of clients with an array of callback +* functions, one per client. The client ID is the index number into the array +* for the client. After a pipe is configured and initialized, the application +* calls Cy_IPC_Pipe_RegisterCallback() once per client to register each client's +* callback function. Multiple clients can use the same callback function. The +* endpoints in a pipe share the callback array. +* +* Use Cy_IPC_Pipe_SendMessage() to send data. You specify both the "to" and +* "from" endpoints, and a callback function to be used when the data transfer is +* complete. The data is a 32-bit void pointer. The data pointed to is arbitrary, +* and can be an array, a structure, or a location in memory. The only limitation +* is that the first element of the data must be a 32-bit unsigned word containing +* a client ID number. The ID number is the index into the callback array. +* +* When a message is sent, the receiving endpoint's interrupt handler is called. +* The ISR can perform any task required by the design. However, as part of its +* function it calls \ref Cy_IPC_Pipe_ExecCallback. This function retrieves the +* client ID from the data and calls the associated callback function. +* The user-supplied callback function handles the data in whatever way is +* appropriate based on the application logic. +* +* After the callback function is returned by the receiver, it invokes the release +* callback function defined by the sender of the message. +* +* \section group_ipc_sema_layer SEMA Layer +* +* A semaphore is a flag the application uses to control access to a shared +* resource. The SEMA-level API uses an IPC channel to implement +* semaphores. Startup code sets up a default semaphore system. The +* default system creates an array of 128 semaphores (four 32-bit values). +* Semaphores 0-15 are reserved for system use. See +* Configuration Considerations - SEMA. +* +* Functions are available to initialize the semaphore system, to set or +* clear a semaphore, or to get the semaphore's current status. Application +* logic uses SEMA functions to relate a particular semaphore to a particular +* shared resource, and set, clear, or check the flag when accessing the +* shared resource. +* +* \section group_ipc_configuration_cypipe Configuration Considerations - CYPIPE +* +* There are none. The cy_ipc_config files set up the required CYPIPE for system +* use. Do not modify the CYPIPE. It uses IPC channels 5 and 6 to implement full +* duplex communication between cores. On the CM0+ the notify interrupt is +* assigned to NVIC IRQn 27. See System Interrupt (SysInt) for background. +* +* To create your own pipe you should make 3 steps: +* -# Define pipe callbacks processing interrupt handler +* -# Define your pipe configuration by cy_stc_ipc_pipe_config_t type structure +* -# Call Cy_IPC_Pipe_Init() to initialize your pipe on both cores +* +* \section group_ipc_configuration_sema Configuration Considerations - SEMA +* +* Startup code calls Cy_IPC_SystemSemaInit() (in cy_ipc_config.c) to set up +* semaphore functionality. This function calls the PDL init function +* Cy_IPC_Sema_Init() with default values. By default the semaphore system +* uses IPC channel 4, and creates 128 semaphores. Do not change the IPC +* channel. You can change the number of semaphores. +* +* To change the number of semaphores, modify this line of code in cy_ipc_config.h. +* +* \code +* #define CY_IPC_SEMA_COUNT (uint32_t)(128u) +* \endcode +* +* The file cy_ipc_config.c declares array ipcSemaArray to hold the semaphore +* flags based on the size defined for this symbol. Use increments of 32. You +* must have at least 32 semaphores. Semaphores 0-15 are reserved for +* system use. Your application can use semaphores greater than 15. +* +* \section group_ipc_more_information More Information +* +* Cy_IPC_SystemSemaInit() and Cy_IPC_SystemPipeInit() functions are called in the +* SystemInit function. If the default startup file is not used, or SystemInit is +* not called in your project, call the following three functions prior to +* executing any flash or EmEEPROM write or erase operation. For example: +* -# Cy_IPC_SystemSemaInit() +* -# Cy_IPC_SystemPipeInit() +* -# Cy_Flash_Init() +* +* Also Cy_IPC_SystemPipeInit function is called to support BLE host/controller +* communication. +* +* See the technical reference manual(TRM) for more information on the IPC. +* +* \section group_ipc_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
10.3RThe value of a complex expression of integer type shall be cast +* only to a type of the same signedness that is no wider than the underlying +* type of the expression.The cast from integer to enumeration value is used to calculate +* the interrupt vector source from the integer number of the IPC interrupt +* structure, so there is no way to avoid this cast.
11.4AA cast should not be performed between a pointer to the void to a +* pointer to the object type.The cast from the void to pointer and vice versa is used to transmit +* data via the \ref group_ipc channel by exchanging the pointer. We +* exchange only one pointer, so there is no way to avoid this cast.
+* +* \section group_ipc_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.10.1Updated description of the \ref Cy_IPC_Pipe_Init, +* \ref Cy_IPC_Pipe_EndpointInit, \ref Cy_IPC_Sema_Set functions. +* Added / updated code snippets. +* Documentation update and clarification
1.10Added support for more IPC structuresNew device support
1.0Initial version
+* +* \defgroup group_ipc_drv IPC driver layer (IPC_DRV) +* \{ +* The functions of this layer are used in the higher IPC levels +* (Semaphores and Pipes). +* Users should not call any of these IPC functions directly. +* +* \defgroup group_ipc_macros Macros +* Macro definitions are used in the driver +* +* \defgroup group_ipc_functions Functions +* Functions are used in the driver +* +* \defgroup group_ipc_data_structures Data Structures +* Data structures are used in the driver +* +* \defgroup group_ipc_enums Enumerated Types +* Enumerations are used in the driver +* \} +* +* \defgroup group_ipc_sema IPC semaphores layer (IPC_SEMA) +* \defgroup group_ipc_pipe IPC pipes layer (IPC_PIPE) +* +*/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "syslib/cy_syslib.h" +#include "cy_device_headers.h" +#include "cy_ipc_config.h" +#include + +/** +* \addtogroup group_ipc_macros +* \{ +*/ + +/** Driver major version */ +#define CY_IPC_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_IPC_DRV_VERSION_MINOR 10 + +/** Defines a value to indicate that no notification events are needed */ +#define CY_IPC_NO_NOTIFICATION (uint32_t)(0x00000000ul) + +/* Error Code constants */ +#define CY_IPC_ID CY_PDL_DRV_ID(0x22u) /**< Software PDL driver ID for IPC */ + +/** Return prefix for IPC driver function status codes */ +#define CY_IPC_ID_INFO (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_INFO ) +/** Return prefix for IPC driver function warning return values */ +#define CY_IPC_ID_WARNING (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_WARNING) +/** Return prefix for IPC driver function error return values */ +#define CY_IPC_ID_ERROR (uint32_t)( CY_IPC_ID | CY_PDL_STATUS_ERROR) + +/** Converts the IPC interrupt channel number to interrupt vector */ +#define CY_IPC_INTR_NUM_TO_VECT(x) ((int32_t)cpuss_interrupts_ipc_0_IRQn + (x)) + +/** \} group_ipc_macros */ + +/* end of definition in device.h */ + + +/** +* \addtogroup group_ipc_enums +* \{ +*/ + +/** +* This is a list of ENUMs used for function return status. +*/ +typedef enum +{ + /** Function was successfully executed */ + CY_IPC_DRV_SUCCESS = (0x00u), + /** Function was not executed due to an error. + Typical conditions for the error explained + in the function description */ + CY_IPC_DRV_ERROR = ( CY_IPC_ID_ERROR + 1ul), +} cy_en_ipcdrv_status_t; + +/** \} group_ipc_enums */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** \cond INTERNAL */ + +__STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint32_t dataValue); +__STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base); + +__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractAcquireMask (uint32_t intMask); +__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask); + +/** \endcond */ + +/** +* \addtogroup group_ipc_functions +* \{ +*/ + +__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex); +__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex); + +__STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type * base, uint32_t notifyEventIntr); +__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type * base, uint32_t notifyEventIntr); + +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base); +cy_en_ipcdrv_status_t Cy_IPC_Drv_LockRelease (IPC_STRUCT_Type * base, uint32_t releaseEventIntr); +__STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base); +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base); + +cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgWord (IPC_STRUCT_Type * base, uint32_t notifyEventIntr, uint32_t message); +cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgWord (IPC_STRUCT_Type const * base, uint32_t * message); +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr (IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr); +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr); + +__STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type * base, + uint32_t ipcReleaseMask, uint32_t ipcNotifyMask); +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask (IPC_INTR_STRUCT_Type const * base); +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base); +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus (IPC_INTR_STRUCT_Type const * base); +__STATIC_INLINE void Cy_IPC_Drv_SetInterrupt (IPC_INTR_STRUCT_Type * base, + uint32_t ipcReleaseMask, uint32_t ipcNotifyMask); +__STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt (IPC_INTR_STRUCT_Type * base, + uint32_t ipcReleaseMask, uint32_t ipcNotifyMask); + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetIpcBaseAddress +****************************************************************************//** +* +* This function takes an IPC channel index as a parameter and returns the base +* address the IPC registers corresponding to the IPC channel. +* +* \note The user is responsible for ensuring that ipcIndex does not exceed the +* limits. +* +* \param ipcIndex +* Represents the number of IPC structure. This is converted to the base address of +* the IPC channel registers. +* +* \return +* Returns a pointer to the base of the IPC registers. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgWord +* +*******************************************************************************/ +__STATIC_INLINE IPC_STRUCT_Type* Cy_IPC_Drv_GetIpcBaseAddress (uint32_t ipcIndex) +{ + CY_ASSERT_L1((uint32_t)CY_IPC_CHANNELS > ipcIndex); + return ( (IPC_STRUCT_Type*) ( &IPC->STRUCT[ipcIndex] ) ); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetIntrBaseAddr +****************************************************************************//** +* +* This function takes an IPC interrupt structure index and returns the base +* address of the IPC interrupt registers corresponding to the IPC Interrupt. +* +* \note The user is responsible for ensuring that ipcIntrIndex does not exceed the +* limits. +* +* \param ipcIntrIndex +* Represents the number of IPC interrupt structure. This is converted to the +* base address of the IPC interrupt registers. +* +* \return +* Returns a pointer to the base of the IPC interrupt registers. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatus +* +*******************************************************************************/ +__STATIC_INLINE IPC_INTR_STRUCT_Type* Cy_IPC_Drv_GetIntrBaseAddr (uint32_t ipcIntrIndex) +{ + CY_ASSERT_L1((uint32_t)CY_IPC_INTERRUPTS > ipcIntrIndex); + return ( (IPC_INTR_STRUCT_Type*) ( &IPC->INTR_STRUCT[ipcIntrIndex] ) ); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_SetInterruptMask +****************************************************************************//** +* +* This function is used to set the interrupt mask for an IPC Interrupt. +* The mask sets release or acquire notification events for all IPC channels. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from the +* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \param ipcReleaseMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* release event. +* +* \param ipcNotifyMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* notify event. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_SetInterruptMask (IPC_INTR_STRUCT_Type* base, + uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) +{ + CY_ASSERT_L1(0ul == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); + CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk))); + base->INTR_MASK = _VAL2FLD( IPC_INTR_STRUCT_INTR_MASK_NOTIFY, ipcNotifyMask) | + _VAL2FLD( IPC_INTR_STRUCT_INTR_MASK_RELEASE, ipcReleaseMask); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetInterruptMask +****************************************************************************//** +* +* This function is used to read the interrupt mask. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from +* the IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \return +* The return value is encoded as follows +* +*
Interrupt sources Value +*
Ipc_PORTX_RELEASE Xth bit set +*
Ipc_PORTX_NOTIFY X+16th bit set +*
+* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptMask(IPC_INTR_STRUCT_Type const * base) +{ + return (base->INTR_MASK); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetInterruptStatusMasked +****************************************************************************//** +* +* This function is used to read the active unmasked interrupt. This function +* can be used in the interrupt service routine to find which source triggered +* the interrupt. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from the +* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \return +* The return value is encoded as follows +* +*
Interrupt sources Value +*
Ipc_PORTX_RELEASE Xth bit set +*
Ipc_PORTX_NOTIFY X+16th bit set +*
+* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatusMasked (IPC_INTR_STRUCT_Type const * base) +{ + return (base->INTR_MASKED); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetInterruptStatus +****************************************************************************//** +* +* This function is used to read the pending interrupts. Note that this read is +* an unmasked read of the interrupt status. Interrupt sources read as active by +* this function would generate interrupts only if they were not masked. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from the +* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \return +* The return value is encoded as follows +* +*
Interrupt sources Value +*
Ipc_PORTX_RELEASE Xth bit set +*
Ipc_PORTX_NOTIFY X+16th bit set +*
+* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatus +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetInterruptStatus(IPC_INTR_STRUCT_Type const * base) +{ + return (base->INTR); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_SetInterrupt +****************************************************************************//** +* +* This function is used to set the interrupt source. This function can be used +* to activate interrupts through software. +* \note That interrupt sources set using this interrupt would generate interrupts +* only if they are not masked. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from the +* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \param ipcReleaseMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* release event. +* +* \param ipcNotifyMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* notify event. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SetInterrupt +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_SetInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) +{ + CY_ASSERT_L1(0ul == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); + CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk))); + base->INTR_SET = _VAL2FLD( IPC_INTR_STRUCT_INTR_NOTIFY, ipcNotifyMask ) | + _VAL2FLD( IPC_INTR_STRUCT_INTR_RELEASE, ipcReleaseMask ); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ClearInterrupt +****************************************************************************//** +* +* This function is used to clear the interrupt source. Use this function to clear +* a pending interrupt source in the interrupt status. +* +* \param base +* This is a handle to the IPC interrupt. This handle can be calculated from the +* IPC interrupt number using \ref Cy_IPC_Drv_GetIntrBaseAddr. +* +* \param ipcReleaseMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* release event. +* +* \param ipcNotifyMask +* An encoded list of all IPC channels that can trigger the interrupt on a +* notify event. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetInterruptStatusMasked +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_ClearInterrupt(IPC_INTR_STRUCT_Type* base, uint32_t ipcReleaseMask, uint32_t ipcNotifyMask) +{ + CY_ASSERT_L1(0ul == (ipcNotifyMask & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); + CY_ASSERT_L1(0ul == (ipcReleaseMask & ~(uint32_t)(IPC_STRUCT_RELEASE_INTR_RELEASE_Msk))); + base->INTR = _VAL2FLD(IPC_INTR_STRUCT_INTR_NOTIFY, ipcNotifyMask) | + _VAL2FLD(IPC_INTR_STRUCT_INTR_RELEASE, ipcReleaseMask); + (void)base->INTR; /* Read the register to flush the cache */ +} + +/** \} group_ipc_functions */ + +/** \} group_ipc */ + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_AcquireNotify +****************************************************************************//** +* +* The function generates a notify event by IPC interrupt structures. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt structures that are triggered +* by a notification. Bit number correspond to number of the IPC interrupt +* structure. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_AcquireNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr) +{ + CY_ASSERT_L1(0ul == (notifyEventIntr & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); + base->NOTIFY = _VAL2FLD(IPC_STRUCT_NOTIFY_INTR_NOTIFY, notifyEventIntr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ReleaseNotify +****************************************************************************//** +* +* The function generates a notify event to an IPC interrupt structure. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt lines that are triggered by a notification. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgWord +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_ReleaseNotify (IPC_STRUCT_Type* base, uint32_t notifyEventIntr) +{ + CY_ASSERT_L1(0ul == (notifyEventIntr & ~(uint32_t)(IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk))); + base->RELEASE = _VAL2FLD(IPC_INTR_STRUCT_INTR_RELEASE, notifyEventIntr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_WriteDataValue +****************************************************************************//** +* +* The function writes a value to the DATA register of the IPC channel. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param dataValue +* Value to be written. +* +*******************************************************************************/ +__STATIC_INLINE void Cy_IPC_Drv_WriteDataValue (IPC_STRUCT_Type* base, uint32_t dataValue) +{ + base->DATA = dataValue; +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ReadDataValue +****************************************************************************//** +* +* The function reads a value from the DATA register of the IPC channel. +* +* This function is internal and should not be called directly by user +* software. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \return +* Value from DATA register. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_ReadDataValue (IPC_STRUCT_Type const * base) +{ + return (base->DATA); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_IsLockAcquired +****************************************************************************//** +* +* The function is used to test the status of an IPC channel. The function +* tells the reader if the IPC channel was in the locked or released state. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \return +* Status for the function: +* true: The IPC channel is in the Locked state. +* false: The IPC channel is in the Released state. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_IPC_Drv_IsLockAcquired (IPC_STRUCT_Type const * base) +{ + return ( 0u != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, base->LOCK_STATUS) ); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_GetLockStatus +****************************************************************************//** +* +* The function is used to get the status of an IPC channel. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \return +* Value from LOCK_STATUS register. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_GetLockStatus +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_GetLockStatus (IPC_STRUCT_Type const * base) +{ + return (base->LOCK_STATUS); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ExtractAcquireMask +****************************************************************************//** +* +* The function extracts an Acquire mask part from full interrupt mask value. +* +* This function is internal and should not be called directly by user +* software. +* +* \param intMask +* Interrupt mask value to be processed. +* +* \return +* Acquire mask value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractAcquireMask (uint32_t intMask) +{ + return _FLD2VAL(IPC_INTR_STRUCT_INTR_MASK_NOTIFY, intMask); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ExtractReleaseMask +****************************************************************************//** +* +* The function extracts a Release mask part from full interrupt mask value. +* +* This function is internal and should not be called directly by user +* software. +* +* \param intMask +* Interrupt mask value to be processed. +* +* \return +* Release mask value. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_IPC_Drv_ExtractReleaseMask (uint32_t intMask) +{ + return _FLD2VAL(IPC_INTR_STRUCT_INTR_MASK_RELEASE, intMask); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_SendMsgPtr +****************************************************************************//** +* +* This function is used to send a message pointer through an IPC channel. +* The message structure may hold a generic pointer that may contain the address +* of any user data type or structure. This parameter could be a pointer to a 32-bit +* integer, an array, or even a data structure defined in the user code. This +* function acts as a transfer engine for sending the pointer. Any memory +* management of the pointer allocation and deallocation is up to the application +* code. +* The function also has an associated notification field that will let the +* message notify one or multiple interrupts. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param notifyEventIntr +* Bit encoded list of IPC interrupt lines that are triggered during the release +* action. +* +* \param msgPtr +* The message pointer that is being sent over the IPC channel. +* +* \return Status of the operation: +* \retval CY_IPC_DRV_SUCCESS: The send operation was successful. +* \retval CY_IPC_DRV_ERROR: The IPC channel is unavailable because +* it is already locked. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_SendMsgPtr +* +*******************************************************************************/ +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_SendMsgPtr(IPC_STRUCT_Type* base, uint32_t notifyEventIntr, void const * msgPtr) +{ + CY_ASSERT_L1(NULL != msgPtr); + return Cy_IPC_Drv_SendMsgWord(base, notifyEventIntr, (uint32_t)msgPtr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_ReadMsgPtr +****************************************************************************//** +* +* This function is used to read a 32-bit pointer message through an IPC channel. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress. +* +* \param msgPtr +* Pointer variable to hold the data pointer that is being read from the IPC +* channel. +* +* +* \return Status of the operation +* \retval CY_IPC_DRV_SUCCESS: The function executed successfully and the IPC +* was acquired. +* \retval CY_IPC_DRV_ERROR: The function encountered an error because the IPC +* channel was already in a released state meaning the data +* in it is invalid. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_ReadMsgPtr +* +*******************************************************************************/ +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_ReadMsgPtr (IPC_STRUCT_Type const * base, void ** msgPtr) +{ + CY_ASSERT_L1(NULL != msgPtr); + return Cy_IPC_Drv_ReadMsgWord(base, (uint32_t *)msgPtr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Drv_LockAcquire +****************************************************************************//** +* +* This function is used to acquire the IPC channel. +* +* \param base +* This parameter is a handle that represents the base address of the registers +* of the IPC channel. +* The parameter is generally returned from a call to the \ref +* Cy_IPC_Drv_GetIpcBaseAddress +* +* \return Status of the operation +* \retval CY_IPC_DRV_SUCCESS: The IPC was successfully acquired +* \retval CY_IPC_DRV_ERROR: The IPC was not acquired because it was already acquired +* by another master +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Drv_LockAcquire +* +*******************************************************************************/ +__STATIC_INLINE cy_en_ipcdrv_status_t Cy_IPC_Drv_LockAcquire (IPC_STRUCT_Type const * base) +{ + return ( 0ul != _FLD2VAL(IPC_STRUCT_ACQUIRE_SUCCESS, base->ACQUIRE)) ? CY_IPC_DRV_SUCCESS : CY_IPC_DRV_ERROR; +} + +#ifdef __cplusplus +} +#endif + +#endif /* !defined(CY_IPC_DRV_H) */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c new file mode 100644 index 0000000000..7c8b830edc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c @@ -0,0 +1,565 @@ +/***************************************************************************//** +* \file cy_ipc_pipe.c +* \version 1.10.1 +* +* Description: +* IPC Pipe Driver - This source file includes code for the Pipe layer on top +* of the IPC driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "cy_ipc_pipe.h" + +/* Define a pointer to array of endPoints. */ +static cy_stc_ipc_pipe_ep_t * cy_ipc_pipe_epArray = NULL; + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_Config +****************************************************************************//** +* +* This function stores a copy of a pointer to the array of endpoints. All +* access to endpoints will be via the index of the endpoint in this array. +* +* \note In general case, this function is called in the default startup code, +* so user doesn't need to call it anywhere. +* However, it may be useful in case of some pipe customizations. +* +* \param theEpArray +* This is the pointer to an array of endpoint structures that the designer +* created and will be used to reference all endpoints. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpArray +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_Config +* +*******************************************************************************/ +void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray) +{ + /* Keep copy of this endpoint */ + if (cy_ipc_pipe_epArray == NULL) + { + cy_ipc_pipe_epArray = theEpArray; + } +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_Init +****************************************************************************//** +* +* Initializes the system pipes. The system pipes are used by BLE. +* \note The function should be called on all CPUs. +* +* \note In general case, this function is called in the default startup code, +* so user doesn't need to call it anywhere. +* However, it may be useful in case of some pipe customizations. +* +* \param config +* This is the pointer to the pipe configuration structure +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeCbArray +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpConfig +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_Init +* +*******************************************************************************/ +void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config) +{ + /* Create the interrupt structures and arrays needed */ + + cy_stc_sysint_t ipc_intr_cypipeConfig; + + cy_stc_ipc_pipe_ep_config_t epConfigDataA; + cy_stc_ipc_pipe_ep_config_t epConfigDataB; + + /* Parameters checking begin */ + CY_ASSERT_L1(NULL != config); + #if (CY_CPU_CORTEX_M0P) + CY_ASSERT_L2((uint32_t)(1UL << __NVIC_PRIO_BITS) > config->ep0ConfigData.ipcNotifierPriority); + #else + CY_ASSERT_L2((uint32_t)(1UL << __NVIC_PRIO_BITS) > config->ep1ConfigData.ipcNotifierPriority); + #endif + CY_ASSERT_L1(NULL != config->endpointsCallbacksArray); + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > config->ep0ConfigData.epAddress); + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > config->ep1ConfigData.epAddress); + CY_ASSERT_L1(NULL != config->userPipeIsrHandler); + /* Parameters checking end */ + +#if (CY_CPU_CORTEX_M0P) + + /* Receiver endpoint = EP0, Sender endpoint = EP1 */ + epConfigDataA = config->ep0ConfigData; + epConfigDataB = config->ep1ConfigData; + + /* Configure CM0 interrupts */ + ipc_intr_cypipeConfig.intrSrc = (IRQn_Type)epConfigDataA.ipcNotifierMuxNumber; + ipc_intr_cypipeConfig.cm0pSrc = (cy_en_intr_t)((int32_t)cpuss_interrupts_ipc_0_IRQn + (int32_t)epConfigDataA.ipcNotifierNumber); + ipc_intr_cypipeConfig.intrPriority = epConfigDataA.ipcNotifierPriority; + +#else + + /* Receiver endpoint = EP1, Sender endpoint = EP0 */ + epConfigDataA = config->ep1ConfigData; + epConfigDataB = config->ep0ConfigData; + + /* Configure interrupts */ + ipc_intr_cypipeConfig.intrSrc = (IRQn_Type)(cpuss_interrupts_ipc_0_IRQn + epConfigDataA.ipcNotifierNumber); + ipc_intr_cypipeConfig.intrPriority = epConfigDataA.ipcNotifierPriority; + +#endif + + /* Initialize the pipe endpoints */ + Cy_IPC_Pipe_EndpointInit(epConfigDataA.epAddress, + config->endpointsCallbacksArray, + config->endpointClientsCount, + epConfigDataA.epConfig, + &ipc_intr_cypipeConfig); + + /* Create the endpoints for the CM4 just for reference */ + Cy_IPC_Pipe_EndpointInit(epConfigDataB.epAddress, NULL, 0ul, epConfigDataB.epConfig, NULL); + + (void)Cy_SysInt_Init(&ipc_intr_cypipeConfig, config->userPipeIsrHandler); + + /* Enable the interrupts */ + NVIC_EnableIRQ(ipc_intr_cypipeConfig.intrSrc); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_EndpointInit +****************************************************************************//** +* +* This function initializes the endpoint of a pipe for the current CPU. The +* current CPU is the CPU that is executing the code. An endpoint of a pipe +* is for the IPC channel that receives a message for the current CPU. +* +* After this function is called, the callbackArray needs to be populated +* with the callback functions for that endpoint using the +* Cy_IPC_Pipe_RegisterCallback() function. +* +* \note In general case, this function is called within \ref Cy_IPC_Pipe_Init, +* so user doesn't need to call it anywhere. +* However, it may be useful in case of some pipe/endpoint customizations. +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint you want to initialize. +* +* \param cbArray +* This is a pointer to the callback function array. Based on the client ID, one +* of the functions in this array is called to process the message. +* +* \param cbCnt +* This is the size of the callback array, or the number of defined clients. +* +* \param epConfig +* This value defines the IPC channel, IPC interrupt number, and the interrupt +* mask for the entire pipe. +* The format of the endpoint configuration +* Bits[31:16] Interrupt Mask +* Bits[15:8 ] IPC interrupt +* Bits[ 7:0 ] IPC channel +* +* \param epInterrupt +* This is a pointer to the endpoint interrupt description structure. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeCbArray +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpConfig +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointInit +* +*******************************************************************************/ +void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray, + uint32_t cbCnt, uint32_t epConfig, cy_stc_sysint_t const *epInterrupt) +{ + cy_stc_ipc_pipe_ep_t * endpoint; + + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); + + endpoint = &cy_ipc_pipe_epArray[epAddr]; + + /* Extract the channel, interrupt and interrupt mask */ + endpoint->ipcChan = _FLD2VAL(CY_IPC_PIPE_CFG_CHAN, epConfig); + endpoint->intrChan = _FLD2VAL(CY_IPC_PIPE_CFG_INTR, epConfig); + endpoint->pipeIntMask = _FLD2VAL(CY_IPC_PIPE_CFG_IMASK, epConfig); + + /* Assign IPC channel to this endpoint */ + endpoint->ipcPtr = Cy_IPC_Drv_GetIpcBaseAddress (endpoint->ipcChan); + + /* Assign interrupt structure to endpoint and Initialize the interrupt mask for this endpoint */ + endpoint->ipcIntrPtr = Cy_IPC_Drv_GetIntrBaseAddr(endpoint->intrChan); + + /* Only allow notify and release interrupts from endpoints in this pipe. */ + Cy_IPC_Drv_SetInterruptMask(endpoint->ipcIntrPtr, endpoint->pipeIntMask, endpoint->pipeIntMask); + + /* Save the Client count and the callback array pointer */ + endpoint->clientCount = cbCnt; + endpoint->callbackArray = cbArray; + endpoint->busy = CY_IPC_PIPE_ENDPOINT_NOTBUSY; + + if (NULL != epInterrupt) + { + endpoint->pipeIntrSrc = epInterrupt->intrSrc; + } +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_SendMessage +****************************************************************************//** +* +* This function is used to send a message from one endpoint to another. It +* generates an interrupt on the endpoint that receives the message and a +* release interrupt to the sender to acknowledge the message has been processed. +* +* \param toAddr +* This parameter is the address (or index in the array of endpoint structures) +* of the endpoint to which you are sending the message. +* +* \param fromAddr +* This parameter is the address (or index in the array of endpoint structures) +* of the endpoint from which the message is being sent. +* +* \param msgPtr +* Pointer to the message structure to be sent. +* +* \param callBackPtr +* Pointer to the Release callback function. +* +* \return +* CY_IPC_PIPE_SUCCESS: Message was sent to the other end of the pipe +* CY_IPC_PIPE_ERROR_BAD_HANDLE: The handle provided for the pipe was not valid +* CY_IPC_PIPE_ERROR_SEND_BUSY: The pipe is already busy sending a message +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myReleaseCallback +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_SendMessage +* +*******************************************************************************/ +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr, + void * msgPtr, cy_ipc_pipe_relcallback_ptr_t callBackPtr) +{ + cy_en_ipc_pipe_status_t returnStatus; + uint32_t releaseMask; + uint32_t notifyMask; + + cy_stc_ipc_pipe_ep_t * fromEp; + cy_stc_ipc_pipe_ep_t * toEp; + + CY_ASSERT_L1(NULL != msgPtr); + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > toAddr); + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > fromAddr); + + toEp = &(cy_ipc_pipe_epArray[toAddr]); + fromEp = &cy_ipc_pipe_epArray[fromAddr]; + + /* Create the release mask for the "fromAddr" channel's interrupt channel */ + releaseMask = (uint32_t)(1ul << (fromEp->intrChan)); + + /* Shift into position */ + releaseMask = _VAL2FLD(CY_IPC_PIPE_MSG_RELEASE, releaseMask); + + /* Create the notify mask for the "toAddr" channel's interrupt channel */ + notifyMask = (uint32_t)(1ul << (toEp->intrChan)); + + /* Check if IPC channel valid */ + if( toEp->ipcPtr != NULL) + { + if(fromEp->busy == CY_IPC_PIPE_ENDPOINT_NOTBUSY) + { + /* Attempt to acquire the channel */ + if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire(toEp->ipcPtr) ) + { + /* Mask out the release mask area */ + * (uint32_t *) msgPtr &= ~(CY_IPC_PIPE_MSG_RELEASE_Msk); + + * (uint32_t *) msgPtr |= releaseMask; + + /* If the channel was acquired, write the message. */ + Cy_IPC_Drv_WriteDataValue(toEp->ipcPtr, (uint32_t) msgPtr); + + /* Set the busy flag. The ISR clears this after the release */ + fromEp->busy = CY_IPC_PIPE_ENDPOINT_BUSY; + + /* Setup release callback function */ + fromEp->releaseCallbackPtr = callBackPtr; + + /* Cause notify event/interrupt */ + Cy_IPC_Drv_AcquireNotify(toEp->ipcPtr, notifyMask); + + returnStatus = CY_IPC_PIPE_SUCCESS; + } + else + { + /* Channel was already acquired, return Error */ + returnStatus = CY_IPC_PIPE_ERROR_SEND_BUSY; + } + } + else + { + /* Channel may not be acquired, but the release interrupt has not executed yet */ + returnStatus = CY_IPC_PIPE_ERROR_SEND_BUSY; + } + } + else + { + /* Null pipe handle. */ + returnStatus = CY_IPC_PIPE_ERROR_BAD_HANDLE; + } + return (returnStatus); +} + + + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_RegisterCallback +****************************************************************************//** +* +* This function registers a callback that is called when a message is received +* on a pipe. +* The client_ID is the same as the index of the callback function array. +* The callback may be a real function pointer or NULL if no callback is required. +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint to which you want to add callback functions. +* +* \param callBackPtr +* Pointer to the callback function called when the endpoint has received a message. +* If this parameters is NULL current callback will be unregistered. +* +* \param clientId +* The index in the callback array (Client ID) where the function pointer is saved. +* +* \return +* CY_IPC_PIPE_SUCCESS: Callback registered successfully +* CY_IPC_PIPE_ERROR_BAD_CLIENT: Client ID out of range, callback not registered. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myAcquireCallback +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_RegisterCallback +* +*******************************************************************************/ +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId) +{ + cy_en_ipc_pipe_status_t returnStatus; + cy_stc_ipc_pipe_ep_t * thisEp; + + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); + + thisEp = &cy_ipc_pipe_epArray[epAddr]; + + /* Check if clientId is between 0 and less than client count */ + if (clientId < thisEp->clientCount) + { + /* Copy callback function into callback function pointer array */ + thisEp->callbackArray[clientId] = callBackPtr; + + returnStatus = CY_IPC_PIPE_SUCCESS; + } + else + { + returnStatus = CY_IPC_PIPE_ERROR_BAD_CLIENT; + } + return (returnStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_RegisterCallbackRel +****************************************************************************//** +* +* This function registers a default callback if a release interrupt +* is generated but the current release callback function is null. +* +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint to which you want to add a release callback function. +* +* \param callBackPtr +* Pointer to the callback executed when the endpoint has received a message. +* If this parameters is NULL current callback will be unregistered. +* +* \return +* None +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myDefaultReleaseCallback +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_RegisterCallbackRel +* +*******************************************************************************/ +void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr) +{ + cy_stc_ipc_pipe_ep_t * endpoint; + + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); + + endpoint = &cy_ipc_pipe_epArray[epAddr]; + + /* Copy callback function into callback function pointer array */ + endpoint->defaultReleaseCallbackPtr = callBackPtr; +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_ExecCallback +****************************************************************************//** +* +* This function is called by the ISR for a given pipe endpoint to dispatch +* the appropriate callback function based on the client ID for that endpoint. +* +* \param endpoint +* Pointer to endpoint structure. +* +* \return +* None +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_myIpcPipeEpArray +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_ExecCallback +* +*******************************************************************************/ +void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint) +{ + uint32_t *msgPtr = NULL; + uint32_t clientID; + uint32_t shadowIntr; + uint32_t releaseMask = (uint32_t)0; + + cy_ipc_pipe_callback_ptr_t callbackPtr; + + /* Parameters checking begin */ + CY_ASSERT_L1(NULL != endpoint); + CY_ASSERT_L1(NULL != endpoint->ipcPtr); + CY_ASSERT_L1(NULL != endpoint->ipcIntrPtr); + CY_ASSERT_L1(NULL != endpoint->callbackArray); + /* Parameters checking end */ + + shadowIntr = Cy_IPC_Drv_GetInterruptStatusMasked(endpoint->ipcIntrPtr); + + /* Check to make sure the interrupt was a notify interrupt */ + if (0ul != Cy_IPC_Drv_ExtractAcquireMask(shadowIntr)) + { + /* Clear the notify interrupt. */ + Cy_IPC_Drv_ClearInterrupt(endpoint->ipcIntrPtr, CY_IPC_NO_NOTIFICATION, Cy_IPC_Drv_ExtractAcquireMask(shadowIntr)); + + if ( Cy_IPC_Drv_IsLockAcquired (endpoint->ipcPtr) ) + { + /* Extract Client ID */ + if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_ReadMsgPtr (endpoint->ipcPtr, (void **)&msgPtr)) + { + /* Get release mask */ + releaseMask = _FLD2VAL(CY_IPC_PIPE_MSG_RELEASE, *msgPtr); + clientID = _FLD2VAL(CY_IPC_PIPE_MSG_CLIENT, *msgPtr); + + /* Make sure client ID is within valid range */ + if (endpoint->clientCount > clientID) + { + callbackPtr = endpoint->callbackArray[clientID]; /* Get the callback function */ + + if (callbackPtr != NULL) + { + callbackPtr(msgPtr); /* Call the function pointer for "clientID" */ + } + } + } + + /* Must always release the IPC channel */ + (void)Cy_IPC_Drv_LockRelease (endpoint->ipcPtr, releaseMask); + } + } + + /* Check to make sure the interrupt was a release interrupt */ + if (0ul != Cy_IPC_Drv_ExtractReleaseMask(shadowIntr)) /* Check for a Release interrupt */ + { + /* Clear the release interrupt */ + Cy_IPC_Drv_ClearInterrupt(endpoint->ipcIntrPtr, Cy_IPC_Drv_ExtractReleaseMask(shadowIntr), CY_IPC_NO_NOTIFICATION); + + if (endpoint->releaseCallbackPtr != NULL) + { + endpoint->releaseCallbackPtr(); + + /* Clear the pointer after it was called */ + endpoint->releaseCallbackPtr = NULL; + } + else + { + if (endpoint->defaultReleaseCallbackPtr != NULL) + { + endpoint->defaultReleaseCallbackPtr(); + } + } + + /* Clear the busy flag when release is detected */ + endpoint->busy = CY_IPC_PIPE_ENDPOINT_NOTBUSY; + } + + (void)Cy_IPC_Drv_GetInterruptStatus(endpoint->ipcIntrPtr); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_EndpointPause +****************************************************************************//** +* +* This function sets the receiver endpoint to paused state. +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint to pause. +* +* \return +* CY_IPC_PIPE_SUCCESS: Callback registered successfully +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointPauseResume +* +*******************************************************************************/ +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr) +{ + cy_stc_ipc_pipe_ep_t * endpoint; + + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); + + endpoint = &cy_ipc_pipe_epArray[epAddr]; + + /* Disable the interrupts */ + NVIC_DisableIRQ(endpoint->pipeIntrSrc); + + return (CY_IPC_PIPE_SUCCESS); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Pipe_EndpointResume +****************************************************************************//** +* +* This function sets the receiver endpoint to active state. +* +* \param epAddr +* This parameter is the address (or index in the array of endpoint structures) +* that designates the endpoint to resume. +* +* \return +* CY_IPC_PIPE_SUCCESS: Callback registered successfully +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Pipe_EndpointPauseResume +* +*******************************************************************************/ +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr) +{ + cy_stc_ipc_pipe_ep_t * endpoint; + + CY_ASSERT_L2(CY_IPC_MAX_ENDPOINTS > epAddr); + + endpoint = &cy_ipc_pipe_epArray[epAddr]; + + /* Enable the interrupts */ + NVIC_EnableIRQ(endpoint->pipeIntrSrc); + + return (CY_IPC_PIPE_SUCCESS); +} + + +/* [] END OF FILE */ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h new file mode 100644 index 0000000000..0bac9a0e16 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h @@ -0,0 +1,265 @@ +/***************************************************************************//** +* \file cy_ipc_pipe.h +* \version 1.10.1 +* +* Description: +* IPC Pipe Driver - This header file contains all the function prototypes, +* structure definitions, pipe constants, and pipe endpoint address definitions. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef CY_IPC_PIPE_H +#define CY_IPC_PIPE_H + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ipc/cy_ipc_drv.h" +#include "syslib/cy_syslib.h" +#include "sysint/cy_sysint.h" + +/** +* \addtogroup group_ipc_pipe IPC pipes layer (IPC_PIPE) +* \{ +* The Pipe functions provide a method to transfer one or more words of data +* between CPUs or tasks. The data can be defined as a single 32-bit unsigned +* word, an array of data, or a user-defined structure. The only limitation is +* that the first word in the array or structure must be a 32-bit unsigned word +* in which a client ID number is passed. The client ID dictates the callback +* function that will be called by the receiver of the message. After the +* callback function returns by the receiver, it will invoke a release callback +* function defined by the sender of the message. +* +* A User Pipe is provided for the user to transfer data between CPUs and +* tasks. +* +* \defgroup group_ipc_pipe_macros Macros +* Macro definitions are used in the driver +* +* \defgroup group_ipc_pipe_functions Functions +* Functions are used in the driver +* +* \defgroup group_ipc_pipe_data_structures Data Structures +* Data structures are used in the driver +* +* \defgroup group_ipc_pipe_enums Enumerated Types +* Enumerations are used in the driver +* \} +* +*/ + +/* + * This section defines the system level constants required to define + * callback arrays for the Cypress pipe and the user pipe. These defines + * are used for both the max callback count and maximum clients. +*/ + +/** Typedef for pipe callback function pointer */ +typedef void (* cy_ipc_pipe_callback_ptr_t)(uint32_t * msgPtr); + +/** Typedef for a pipe release callback function pointer */ +typedef void (* cy_ipc_pipe_relcallback_ptr_t)(void); + +/** Typedef for array of callback function pointers */ +typedef cy_ipc_pipe_callback_ptr_t *cy_ipc_pipe_callback_array_ptr_t; + + +/** +* \addtogroup group_ipc_pipe_macros +* \{ +*/ + +/* + * The System pipe address is what is used to send a message to one of the + * endpoints of a pipe. Currently the Cypress pipe and the User pipe + * are supported. For parts with extra IPC channels users may create + * their own custom pipes and create their own pipe addresses. + * + * The format of the endpoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ +#define CY_IPC_PIPE_CFG_IMASK_Pos (16UL) /**< Interrupts shift value for endpoint address */ +#define CY_IPC_PIPE_CFG_IMASK_Msk (0xFFFF0000UL) /**< Interrupts mask for endpoint address */ +#define CY_IPC_PIPE_CFG_INTR_Pos (8UL) /**< IPC Interrupt shift value for endpoint address */ +#define CY_IPC_PIPE_CFG_INTR_Msk (0x0000FF00UL) /**< IPC Interrupt mask for endpoint address */ +#define CY_IPC_PIPE_CFG_CHAN_Pos (0UL) /**< IPC Channel shift value for endpoint address */ +#define CY_IPC_PIPE_CFG_CHAN_Msk (0x000000FFUL) /**< IPC Channel mask for endpoint address */ + + + +#define CY_IPC_PIPE_MSG_CLIENT_Msk (0x000000FFul) /**< Client mask for first word of Pipe message */ +#define CY_IPC_PIPE_MSG_CLIENT_Pos (0ul) /**< Client shift for first word of Pipe message */ +#define CY_IPC_PIPE_MSG_USR_Msk (0x0000FF00ul) /**< User data mask for first word of Pipe message */ +#define CY_IPC_PIPE_MSG_USR_Pos (8ul) /**< User data shift for first word of Pipe message */ +#define CY_IPC_PIPE_MSG_RELEASE_Msk (0xFFFF0000ul) /**< Mask for message release mask */ +#define CY_IPC_PIPE_MSG_RELEASE_Pos (16UL) /**< Shift require to line up mask to LSb */ + +/** Use to set the busy flag when waiting for a release interrupt */ +#define CY_IPC_PIPE_ENDPOINT_BUSY (1UL) +/** Denotes that a release interrupt is not pending */ +#define CY_IPC_PIPE_ENDPOINT_NOTBUSY (0UL) + +/** \} group_ipc_pipe_macros */ + +/** +* \addtogroup group_ipc_pipe_data_structures +* \{ +*/ + +/** +* This is the definition of a pipe endpoint. There is one endpoint structure +* for each CPU in a pipe. It contains all the information to process a message +* send to other CPUs in the pipe. +*/ +typedef struct +{ + uint32_t ipcChan; /**< IPC channel number used for this endpoint to receive messages */ + uint32_t intrChan; /**< IPC interrupt channel number used for this endpoint to receive interrupts */ + uint32_t pipeIntMask; /**< Release/Notify interrupt mask that includes all endpoints on pipe */ + IRQn_Type pipeIntrSrc; /**< Interrupt vector number that includes all endpoints on pipe */ + + IPC_STRUCT_Type *ipcPtr; /**< Pointer to receive IPC channel ( If ipcPtr == NULL, cannot receive ) */ + IPC_INTR_STRUCT_Type *ipcIntrPtr; /**< Pointer to IPC interrupt, needed to clear the interrupt */ + uint32_t busy; /**< Endpoint busy flag. If sent no messages can be sent from this endpoint */ + uint32_t clientCount; /**< Client count and size of MsgCallback array */ + + cy_ipc_pipe_callback_array_ptr_t callbackArray; /**< Pointer to array of callback functions, one for each Client */ + cy_ipc_pipe_relcallback_ptr_t releaseCallbackPtr; /**< Pointer to release callback function */ + cy_ipc_pipe_relcallback_ptr_t defaultReleaseCallbackPtr; /**< Pointer to default release callback function */ +} cy_stc_ipc_pipe_ep_t; + +/** The Pipe endpoint configuration structure. */ +typedef struct +{ + uint32_t ipcNotifierNumber; /**< Notifier */ + uint32_t ipcNotifierPriority; /**< Notifier Priority */ + uint32_t ipcNotifierMuxNumber; /**< CM0+ interrupt multiplexer number */ + + uint32_t epAddress; /**< Index in the array of endpoint structure */ + uint32_t epConfig; /**< Configuration mask, contains IPC channel, IPC interrupt number, + and the interrupt mask */ +} cy_stc_ipc_pipe_ep_config_t; + +/** The Pipe channel configuration structure. */ +typedef struct +{ + /** Specifies the notify interrupt number for the first endpoint */ + cy_stc_ipc_pipe_ep_config_t ep0ConfigData; + + /** Specifies the notify interrupt number for the second endpoint */ + cy_stc_ipc_pipe_ep_config_t ep1ConfigData; + + /** Client count and size of MsgCallback array */ + uint32_t endpointClientsCount; + + /** Pipes callback function array. */ + cy_ipc_pipe_callback_array_ptr_t endpointsCallbacksArray; + + /** User IRQ handler function that is called when IPC receive data to process (interrupt was raised). */ + cy_israddress userPipeIsrHandler; +} cy_stc_ipc_pipe_config_t; + +/** \} goup_ipc_pipe_data_structures */ + +/** +* \addtogroup group_ipc_pipe_macros +* \{ +*/ +/* Status and error types */ +#define CY_IPC_PIPE_RTN (0x0200ul) /**< Software PDL driver ID for IPC pipe functions */ +#define CY_IPC_PIPE_ID_INFO (uint32_t)( CY_IPC_ID_INFO | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function status codes */ +#define CY_IPC_PIPE_ID_WARNING (uint32_t)( CY_IPC_ID_WARNING | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function warning return values */ +#define CY_IPC_PIPE_ID_ERROR (uint32_t)( CY_IPC_ID_ERROR | CY_IPC_PIPE_RTN) /**< Return prefix for IPC pipe function error return values */ + +/** \} group_ipc_pipe_macros */ + +/** +* \addtogroup group_ipc_pipe_enums +* \{ +*/ + +/** Return constants for IPC pipe functions. */ +typedef enum +{ + CY_IPC_PIPE_SUCCESS =(uint32_t)(0x00u), /**< Pipe API return for no error */ + CY_IPC_PIPE_ERROR_NO_IPC =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 1ul), /**< Pipe API return for no valid IPC channel */ + CY_IPC_PIPE_ERROR_NO_INTR =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 2ul), /**< Pipe API return for no valid interrupt */ + CY_IPC_PIPE_ERROR_BAD_PRIORITY =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 3ul), /**< Pipe API return for bad priority parameter */ + CY_IPC_PIPE_ERROR_BAD_HANDLE =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 4ul), /**< Pipe API return for bad pipe handle */ + CY_IPC_PIPE_ERROR_BAD_ID =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 5ul), /**< Pipe API return for bad pipe ID */ + CY_IPC_PIPE_ERROR_DIR_ERROR =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 6ul), /**< Pipe API return for invalid direction (Not used at this time) */ + CY_IPC_PIPE_ERROR_SEND_BUSY =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 7ul), /**< Pipe API return for pipe is currently busy */ + CY_IPC_PIPE_ERROR_NO_MESSAGE =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 8ul), /**< Pipe API return for no message indicated */ + CY_IPC_PIPE_ERROR_BAD_CPU =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 9ul), /**< Pipe API return for invalid CPU value */ + CY_IPC_PIPE_ERROR_BAD_CLIENT =(uint32_t)(CY_IPC_PIPE_ID_ERROR | 10ul) /**< Pipe API return for client out of range */ +} cy_en_ipc_pipe_status_t; + +/** \} group_ipc_pipe_enums */ + +/** +* \addtogroup group_ipc_pipe_data_structures +* \{ +*/ + +/** \cond +* NOTE: This doxygen comment must be placed before some code entity, or else +* it will belong to a random entity that follows it, e.g. group_ipc_functions +* +* Client identifier for a message. +* For a given pipe, traffic across the pipe can be multiplexed with multiple +* senders on one end and multiple receivers on the other end. +* +* The first 32-bit word of the message is used to identify the client that owns +* the message. +* +* The upper 16 bits are the client ID. +* +* The lower 16 bits are for use by the client in any way desired. +* +* The lower 16 bits are preserved (not modified) and not interpreted in any way. +* \endcond +*/ + +/** \} group_ipc_pipe_data_structures */ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +/** +* \addtogroup group_ipc_pipe_functions +* \{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +void Cy_IPC_Pipe_EndpointInit(uint32_t epAddr, cy_ipc_pipe_callback_array_ptr_t cbArray, + uint32_t cbCnt, uint32_t epConfig, cy_stc_sysint_t const *epInterrupt); +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_SendMessage(uint32_t toAddr, uint32_t fromAddr, void *msgPtr, + cy_ipc_pipe_relcallback_ptr_t callBackPtr); +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_RegisterCallback(uint32_t epAddr, + cy_ipc_pipe_callback_ptr_t callBackPtr, uint32_t clientId); +void Cy_IPC_Pipe_ExecCallback(cy_stc_ipc_pipe_ep_t * endpoint); +void Cy_IPC_Pipe_RegisterCallbackRel(uint32_t epAddr, cy_ipc_pipe_relcallback_ptr_t callBackPtr); +void Cy_IPC_Pipe_Config(cy_stc_ipc_pipe_ep_t * theEpArray); +void Cy_IPC_Pipe_Init(cy_stc_ipc_pipe_config_t const *config); + +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointPause(uint32_t epAddr); +cy_en_ipc_pipe_status_t Cy_IPC_Pipe_EndpointResume(uint32_t epAddr); + +#ifdef __cplusplus +} +#endif + +/** \} group_ipc_pipe_functions */ + +#endif /* CY_IPC_PIPE_H */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.c new file mode 100644 index 0000000000..1154997e23 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.c @@ -0,0 +1,392 @@ +/***************************************************************************//** +* \file cy_ipc_sema.c +* \version 1.10.1 +* +* Description: +* IPC Semaphore Driver - This source file contains the source code for the +* semaphore level APIs for the IPC interface. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "ipc/cy_ipc_drv.h" +#include "ipc/cy_ipc_sema.h" +#include "syslib/cy_syslib.h" +#include /* The memset() definition */ + +/* Defines a mask to Check if semaphore count is a multiple of 32 */ +#define CY_IPC_SEMA_PER_WORD_MASK (CY_IPC_SEMA_PER_WORD - 1ul) + +/* Pointer to IPC structure used for semaphores */ +static IPC_STRUCT_Type* cy_semaIpcStruct; + +/* +* Internal IPC semaphore control data structure. +*/ +typedef struct +{ + uint32_t maxSema; /* Maximum semaphores in system */ + uint32_t *arrayPtr; /* Pointer to semaphores array */ +} cy_stc_ipc_sema_t; + +/******************************************************************************* +* Function Name: Cy_IPC_Sema_Init +****************************************************************************//** +* +* This function initializes the semaphores subsystem. The user must create an +* array of unsigned 32-bit words to hold the semaphore bits. The number +* of semaphores will be the size of the array * 32. The total semaphores count +* will always be a multiple of 32. +* +* \note In a multi-CPU system this init function should be called with all +* initialized parameters on one CPU only to provide a pointer to SRAM that can +* be shared between all the CPUs in the system that will use semaphores. +* On other CPUs user must specify the IPC semaphores channel and pass 0 / NULL +* to count and memPtr parameters correspondingly. +* +* \param ipcChannel +* The IPC channel number used for semaphores +* +* \param count +* The maximum number of semaphores to be supported (multiple of 32). +* +* \param memPtr +* This points to the array of (count/32) words that contain the semaphore data. +* +* \return Status of the operation +* \retval CY_IPC_SEMA_SUCCESS: Successfully initialized +* \retval CY_IPC_SEMA_BAD_PARAM: Memory pointer is NULL and count is not zero, +* or count not multiple of 32 +* \retval CY_IPC_SEMA_ERROR_LOCKED: Could not acquire semaphores IPC channel +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Init +* +*******************************************************************************/ +cy_en_ipcsema_status_t Cy_IPC_Sema_Init(uint32_t ipcChannel, + uint32_t count, uint32_t memPtr[]) +{ + /* Structure containing semaphores control data */ + static cy_stc_ipc_sema_t cy_semaData; + + cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_BAD_PARAM; + + if (ipcChannel >= CY_IPC_CHANNELS) + { + retStatus = CY_IPC_SEMA_BAD_PARAM; + } + else + { + if( (NULL == memPtr) && (0u == count)) + { + cy_semaIpcStruct = Cy_IPC_Drv_GetIpcBaseAddress(ipcChannel); + + retStatus = CY_IPC_SEMA_SUCCESS; + } + + /* Check for non Null pointers and count value */ + else if ((NULL != memPtr) && (0u != count)) + { + /* Check if semaphore count is a multiple of 32 */ + if( 0ul == (count & CY_IPC_SEMA_PER_WORD_MASK)) + { + cy_semaIpcStruct = Cy_IPC_Drv_GetIpcBaseAddress(ipcChannel); + + cy_semaData.maxSema = count; + cy_semaData.arrayPtr = memPtr; + + /* Initialize all semaphores to released */ + (void)memset(cy_semaData.arrayPtr, 0, (count /8u)); + + /* Make sure semaphores start out released. */ + /* Ignore the return value since it is OK if it was already released. */ + (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION); + + /* Set the IPC Data with the pointer to the array. */ + if( CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_SendMsgPtr (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION, &cy_semaData)) + { + if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION)) + { + retStatus = CY_IPC_SEMA_SUCCESS; + } + else + { + /* IPC channel not released, still semaphored */ + retStatus = CY_IPC_SEMA_ERROR_LOCKED; + } + } + else + { + /* Could not acquire semaphore channel */ + retStatus = CY_IPC_SEMA_ERROR_LOCKED; + } + } + else + { + retStatus = CY_IPC_SEMA_BAD_PARAM; + } + } + else + { + retStatus = CY_IPC_SEMA_BAD_PARAM; + } + } + + return(retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Sema_Set +****************************************************************************//** +* +* This function tries to acquire a semaphore. If the +* semaphore is not available, this function returns immediately with +* CY_IPC_SEMA_LOCKED. +* +* It first acquires the IPC channel that is used for all the semaphores, sets +* the semaphore if it is cleared, then releases the IPC channel used for the +* semaphore. +* +* \param semaNumber +* The semaphore number to acquire. +* +* \param preemptable +* When this parameter is enabled the function can be preempted by another +* task or other forms of context switching in an RTOS environment. +* +* \note +* If preemptable is enabled (true), the user must ensure that there are +* no deadlocks in the system, which can be caused by an interrupt that occurs +* after the IPC channel is locked. Unless the user is ready to handle IPC +* channel locks correctly at the application level, set premptable to +* false. +* +* \return Status of the operation +* \retval CY_IPC_SEMA_SUCCESS: The semaphore was set successfully +* \retval CY_IPC_SEMA_LOCKED: The semaphore channel is busy or locked +* by another process +* \retval CY_IPC_SEMA_NOT_ACQUIRED: Semaphore was already set +* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Set +* +*******************************************************************************/ +cy_en_ipcsema_status_t Cy_IPC_Sema_Set(uint32_t semaNumber, bool preemptable) +{ + uint32_t semaIndex; + uint32_t semaMask; + uint32_t interruptState = 0ul; + + cy_stc_ipc_sema_t *semaStruct; + cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_LOCKED; + + /* Get pointer to structure */ + semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct); + + if (semaNumber < semaStruct->maxSema) + { + semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD; + semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) )); + + if (!preemptable) + { + interruptState = Cy_SysLib_EnterCriticalSection(); + } + + /* Check to make sure the IPC channel is released + If so, check if specific channel can be locked. */ + if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire (cy_semaIpcStruct)) + { + if((semaStruct->arrayPtr[semaIndex] & semaMask) == 0ul) + { + semaStruct->arrayPtr[semaIndex] |= semaMask; + retStatus = CY_IPC_SEMA_SUCCESS; + } + else + { + retStatus = CY_IPC_SEMA_NOT_ACQUIRED; + } + + /* Release, but do not trigger a release event */ + (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION); + } + + if (!preemptable) + { + Cy_SysLib_ExitCriticalSection(interruptState); + } + } + else + { + retStatus = CY_IPC_SEMA_OUT_OF_RANGE; + } + + return(retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Sema_Clear +****************************************************************************//** +* +* This functions tries to releases a semaphore. +* +* It first acquires the IPC channel that is used for all the semaphores, clears +* the semaphore if it is set, then releases the IPC channel used for the +* semaphores. +* +* \param semaNumber +* The index of the semaphore to release. +* +* \param preemptable +* When this parameter is enabled the function can be preempted by another +* task or other forms of context switching in an RTOS environment. +* +* \note +* If preemptable is enabled (true), the user must ensure that there are +* no deadlocks in the system, which can be caused by an interrupt that occurs +* after the IPC channel is locked. Unless the user is ready to handle IPC +* channel locks correctly at the application level, set premptable to +* false. +* +* \return Status of the operation +* \retval CY_IPC_SEMA_SUCCESS: The semaphore was cleared successfully +* \retval CY_IPC_SEMA_NOT_ACQUIRED: The semaphore was already cleared +* \retval CY_IPC_SEMA_LOCKED: The semaphore channel was semaphored or busy +* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Clear +* +*******************************************************************************/ +cy_en_ipcsema_status_t Cy_IPC_Sema_Clear(uint32_t semaNumber, bool preemptable) +{ + uint32_t semaIndex; + uint32_t semaMask; + uint32_t interruptState = 0ul; + + cy_stc_ipc_sema_t *semaStruct; + cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_LOCKED; + + /* Get pointer to structure */ + semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct); + + if (semaNumber < semaStruct->maxSema) + { + semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD; + semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) )); + + if (!preemptable) + { + interruptState = Cy_SysLib_EnterCriticalSection(); + } + + /* Check to make sure the IPC channel is released + If so, check if specific channel can be locked. */ + if(CY_IPC_DRV_SUCCESS == Cy_IPC_Drv_LockAcquire (cy_semaIpcStruct)) + { + if((semaStruct->arrayPtr[semaIndex] & semaMask) != 0ul) + { + semaStruct->arrayPtr[semaIndex] &= ~semaMask; + retStatus = CY_IPC_SEMA_SUCCESS; + } + else + { + retStatus = CY_IPC_SEMA_NOT_ACQUIRED; + } + + /* Release, but do not trigger a release event */ + (void) Cy_IPC_Drv_LockRelease (cy_semaIpcStruct, CY_IPC_NO_NOTIFICATION); + } + + if (!preemptable) + { + Cy_SysLib_ExitCriticalSection(interruptState); + } + } + else + { + retStatus = CY_IPC_SEMA_OUT_OF_RANGE; + } + return(retStatus); +} + +/******************************************************************************* +* Function Name: Cy_IPC_Sema_Status +****************************************************************************//** +* +* This function returns the status of the semaphore. +* +* \param semaNumber +* The index of the semaphore to return status. +* +* \return Status of the operation +* \retval CY_IPC_SEMA_STATUS_LOCKED: The semaphore is in the set state. +* \retval CY_IPC_SEMA_STATUS_UNLOCKED: The semaphore is in the cleared state. +* \retval CY_IPC_SEMA_OUT_OF_RANGE: The semaphore number is not valid +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_Status +* +*******************************************************************************/ +cy_en_ipcsema_status_t Cy_IPC_Sema_Status(uint32_t semaNumber) +{ + cy_en_ipcsema_status_t retStatus; + uint32_t semaIndex; + uint32_t semaMask; + cy_stc_ipc_sema_t *semaStruct; + + /* Get pointer to structure */ + semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct); + + if (semaNumber < semaStruct->maxSema) + { + /* Get the index into the semaphore array and calculate the mask */ + semaIndex = semaNumber / CY_IPC_SEMA_PER_WORD; + semaMask = (uint32_t)(1ul << (semaNumber - (semaIndex * CY_IPC_SEMA_PER_WORD) )); + + if((semaStruct->arrayPtr[semaIndex] & semaMask) != 0ul) + { + retStatus = CY_IPC_SEMA_STATUS_LOCKED; + } + else + { + retStatus = CY_IPC_SEMA_STATUS_UNLOCKED; + } + } + else + { + retStatus = CY_IPC_SEMA_OUT_OF_RANGE; + } + return(retStatus); +} + + +/******************************************************************************* +* Function Name: Cy_IPC_Sema_GetMaxSems +****************************************************************************//** +* +* This function returns the number of semaphores in the semaphores subsystem. +* +* \return +* Returns the semaphores quantity. +* +* \funcusage +* \snippet IPC_sut_01.cydsn/main_cm4.c snippet_Cy_IPC_Sema_GetMaxSems +* +*******************************************************************************/ +uint32_t Cy_IPC_Sema_GetMaxSems(void) +{ + cy_stc_ipc_sema_t *semaStruct; + + /* Get pointer to structure */ + semaStruct = (cy_stc_ipc_sema_t *)Cy_IPC_Drv_ReadDataValue(cy_semaIpcStruct); + + return (semaStruct->maxSema); +} + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.h new file mode 100644 index 0000000000..fb0179c7b4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.h @@ -0,0 +1,114 @@ +/***************************************************************************//** +* \file cy_ipc_sema.h +* \version 1.10.1 +* +* \brief +* Header file for IPC SEM functions +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#ifndef CY_IPC_SEMA_H +#define CY_IPC_SEMA_H + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "cy_ipc_drv.h" +#include + +/** +* \addtogroup group_ipc_sema IPC semaphores layer (IPC_SEMA) +* \{ +* The semaphores layer functions made use of a single IPC channel to allow +* multiple semaphores that can be used by system or user function calls. +* By default there are 128 semaphores provided, although the user may modify +* the default value to any number, limited only by SRAM. +* +* \defgroup group_ipc_sema_macros Macros +* Macro definitions are used in the driver +* +* \defgroup group_ipc_sema_functions Functions +* Functions are used in the driver +* +* \defgroup group_ipc_sema_enums Enumerated Types +* Enumerations are used in the driver +* \} +* +* \addtogroup group_ipc_sema_macros +* \{ +*/ + +/** Software PDL driver ID for IPC semaphore functions */ +#define CY_IPC_SEMA_RTN (0x0100ul) +/** Return prefix for IPC semaphore function status codes */ +#define CY_IPC_SEMA_ID_INFO (uint32_t)( CY_IPC_ID_INFO | CY_IPC_SEMA_RTN) +/** Return prefix for IPC semaphore function warning return values */ +#define CY_IPC_SEMA_ID_WARNING (uint32_t)( CY_IPC_ID_WARNING | CY_IPC_SEMA_RTN) +/** Return prefix for IPC semaphore function error return values */ +#define CY_IPC_SEMA_ID_ERROR (uint32_t)( CY_IPC_ID_ERROR | CY_IPC_SEMA_RTN) + +#define CY_IPC_SEMA_PER_WORD (uint32_t)32u /**< 32 semaphores per word */ + +/** \} group_ipc_sema_macros */ + +/** +* \addtogroup group_ipc_sema_enums +* \{ +*/ + +/** Return constants for IPC semaphores functions. */ +typedef enum +{ + /** No error has occurred */ + CY_IPC_SEMA_SUCCESS = (uint32_t)(0ul), + /** Semaphores IPC channel has already been locked */ + CY_IPC_SEMA_ERROR_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 1ul), + /** Semaphores IPC channel is unlocked */ + CY_IPC_SEMA_ERROR_UNLOCKED = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 2ul), + /** Semaphore API bad parameter */ + CY_IPC_SEMA_BAD_PARAM = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 3ul), + /** Semaphore API return when semaphore number is out of the range */ + CY_IPC_SEMA_OUT_OF_RANGE = (uint32_t)(CY_IPC_SEMA_ID_ERROR | 4ul), + + /** Semaphore API return when IPC channel was not acquired */ + CY_IPC_SEMA_NOT_ACQUIRED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 2ul), + /** Semaphore API return status when semaphore channel is busy or locked +* by another process */ + CY_IPC_SEMA_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 3ul), + /** Semaphore status return that the semaphore is set */ + CY_IPC_SEMA_STATUS_LOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 1ul), + /** Semaphore status return that the semaphore is cleared */ + CY_IPC_SEMA_STATUS_UNLOCKED = (uint32_t)(CY_IPC_SEMA_ID_INFO | 0ul) +} cy_en_ipcsema_status_t; + +/** \} group_ipc_sema_enums */ + +/** +* \addtogroup group_ipc_sema_functions +* \{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +cy_en_ipcsema_status_t Cy_IPC_Sema_Init (uint32_t ipcChannel, uint32_t count, uint32_t memPtr[]); +cy_en_ipcsema_status_t Cy_IPC_Sema_Set (uint32_t semaNumber, bool preemptable); +cy_en_ipcsema_status_t Cy_IPC_Sema_Clear (uint32_t semaNumber, bool preemptable); +cy_en_ipcsema_status_t Cy_IPC_Sema_Status (uint32_t semaNumber); +uint32_t Cy_IPC_Sema_GetMaxSems(void); + +#ifdef __cplusplus +} +#endif + +/** \} group_ipc_sema_functions */ + +#endif /* CY_IPC_SEMA_H */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c new file mode 100644 index 0000000000..c0d13a8365 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c @@ -0,0 +1,627 @@ +/******************************************************************************* +* \file cy_lpcomp.c +* \version 1.10.1 +* +* \brief +* This file provides the driver code to the API for the Low Power Comparator +* component. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "cy_lpcomp.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +static cy_stc_lpcomp_context_t cy_lpcomp_context; + +/******************************************************************************* +* Function Name: Cy_LPComp_Init +****************************************************************************//** +* +* Initializes LPCOMP and returns the LPCOMP register address. +* +* \param *base +* LPCOMP registers structure pointer. +* +* \param *config +* The pointer to the configuration structure for PDL. +* +* \param channel +* The LPCOMP channel index. +* +* \return cy_en_lpcomp_status_t +* *base checking result. If the pointer is NULL, returns error. +* +*******************************************************************************/ +cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, const cy_stc_lpcomp_config_t* config) +{ + cy_en_lpcomp_status_t ret = CY_LPCOMP_BAD_PARAM; + + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(config->outputMode)); + CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(config->hysteresis)); + CY_ASSERT_L3(CY_LPCOMP_IS_POWER_VALID(config->power)); + CY_ASSERT_L3(CY_LPCOMP_IS_INTR_MODE_VALID(config->intType)); + + if ((base != NULL) && (config != NULL)) + { + Cy_LPComp_GlobalEnable(base); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_CTRL = _VAL2FLD(LPCOMP_CMP0_CTRL_HYST0, (uint32_t)config->hysteresis) | + _VAL2FLD(LPCOMP_CMP0_CTRL_DSI_BYPASS0, (uint32_t)config->outputMode) | + _VAL2FLD(LPCOMP_CMP0_CTRL_DSI_LEVEL0, (uint32_t)config->outputMode >> 1u); + } + else + { + base->CMP1_CTRL = _VAL2FLD(LPCOMP_CMP1_CTRL_HYST1, (uint32_t)config->hysteresis) | + _VAL2FLD(LPCOMP_CMP1_CTRL_DSI_BYPASS1, (uint32_t)config->outputMode) | + _VAL2FLD(LPCOMP_CMP1_CTRL_DSI_LEVEL1, (uint32_t)config->outputMode >> 1u); + } + + /* Save intType to use it in the Cy_LPComp_Enable() function */ + cy_lpcomp_context.intType[(uint8_t)channel - 1u] = config->intType; + + /* Save power to use it in the Cy_LPComp_Enable() function */ + cy_lpcomp_context.power[(uint8_t)channel - 1u] = config->power; + + ret = CY_LPCOMP_SUCCESS; + } + + return (ret); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_Enable +****************************************************************************//** +* +* Enables the LPCOMP and sets the LPCOMP interrupt mode. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel) +{ + cy_en_lpcomp_pwr_t powerSpeed; + + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + + powerSpeed = cy_lpcomp_context.power[(uint8_t)channel - 1u]; + + /* Set power */ + Cy_LPComp_SetPower(base, channel, powerSpeed); + + /* Make delay before enabling the comparator interrupt to prevent false triggering */ + if (CY_LPCOMP_MODE_ULP == powerSpeed) + { + Cy_SysLib_DelayUs(CY_LPCOMP_ULP_POWER_DELAY); + } + else if (CY_LPCOMP_MODE_LP == powerSpeed) + { + Cy_SysLib_DelayUs(CY_LPCOMP_LP_POWER_DELAY); + } + else + { + Cy_SysLib_DelayUs(CY_LPCOMP_NORMAL_POWER_DELAY); + } + + /* Enable the comparator interrupt */ + Cy_LPComp_SetInterruptTriggerMode(base, channel, cy_lpcomp_context.intType[(uint8_t)channel - 1u]); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_Disable +****************************************************************************//** +* +* Disables the LPCOMP power and sets the interrupt mode to disabled. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + + /* Disable the comparator interrupt */ + Cy_LPComp_SetInterruptTriggerMode(base, channel, CY_LPCOMP_INTR_DISABLE); + + /* Set power off */ + Cy_LPComp_SetPower(base, channel, CY_LPCOMP_MODE_OFF); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetInterruptTriggerMode +****************************************************************************//** +* +* Sets the interrupt edge-detect mode. +* This also controls the value provided on the output. +* \note Interrupts can be enabled after the block is enabled and the appropriate +* start-up time has elapsed: +* 3 us for the normal power mode; +* 6 us for the LP mode; +* 50 us for the ULP mode. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \param intType +* Interrupt edge trigger selection +* CY_LPCOMP_INTR_DISABLE (=0) - Disabled, no interrupt will be detected +* CY_LPCOMP_INTR_RISING (=1) - Rising edge +* CY_LPCOMP_INTR_FALLING (=2) - Falling edge +* CY_LPCOMP_INTR_BOTH (=3) - Both rising and falling edges. +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_int_t intType) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_INTR_MODE_VALID(intType)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, LPCOMP_CMP0_CTRL_INTTYPE0, (uint32_t)intType); + } + else + { + base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, LPCOMP_CMP1_CTRL_INTTYPE1, (uint32_t)intType); + } + + /* Save interrupt type to use it in the Cy_LPComp_Enable() function */ + cy_lpcomp_context.intType[(uint8_t)channel - 1u] = intType; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetPower +****************************************************************************//** +* +* Sets the drive power and speeds to one of the four settings. +* \note Interrupts can be enabled after the block is enabled and the appropriate +* start-up time has elapsed: +* 3 us for the normal power mode; +* 6 us for the LP mode; +* 50 us for the ULP mode. +* Otherwise, unexpected interrupts events can occur. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \param power +* The power setting sets an operation mode of the component: +* CY_LPCOMP_OFF_POWER (=0) - Off power +* CY_LPCOMP_MODE_ULP (=1) - Slow/ultra low power +* CY_LPCOMP_MODE_LP (=2) - Medium/low power +* CY_LPCOMP_MODE_NORMAL(=3) - Fast/normal power +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_SetPower(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_pwr_t power) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_POWER_VALID(power)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, LPCOMP_CMP0_CTRL_MODE0, (uint32_t)power); + } + else + { + base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, LPCOMP_CMP1_CTRL_MODE1, (uint32_t)power); + } +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetHysteresis +****************************************************************************//** +* +* Adds the 30mV hysteresis to the comparator. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \param hysteresis +* Sets an operation mode of the component +* CY_LPCOMP_HYST_ENABLE (=1) - Enables HYST +* CY_LPCOMP_HYST_DISABLE(=0) - Disable HYST. +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_hyst_t hysteresis) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(hysteresis)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, LPCOMP_CMP0_CTRL_HYST0, (uint32_t)hysteresis); + } + else + { + base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL , LPCOMP_CMP1_CTRL_HYST1, (uint32_t)hysteresis); + } +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetInputs +****************************************************************************//** +* +* Sets the comparator input sources. The comparator inputs can be connected +* to the dedicated GPIO pins or AMUXBUSA/AMUXBUSB. Additionally, the negative +* comparator input can be connected to the local VREF. +* At least one unconnected input causes a comparator undefined output. +* +* \note Connection to AMUXBUSA/AMUXBUSB requires closing the additional +* switches which are a part of the IO system. These switches can be configured +* using the HSIOM->AMUX_SPLIT_CTL[3] register. +* Refer to the appropriate Technical Reference Manual (TRM) of a device +* for a detailed description. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \param inputP +* Positive input selection +* CY_LPCOMP_SW_GPIO (0x01u) +* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode +* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in the hibernate mode. +* +* \param inputN +* Negative input selection +* CY_LPCOMP_SW_GPIO (0x01u) +* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode +* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in hibernate mode +* CY_LPCOMP_SW_LOCAL_VREF (0x08u) - the negative input only for a crude REF. +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_SetInputs(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_inputs_t inputP, cy_en_lpcomp_inputs_t inputN) +{ + uint32_t input; + + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_INPUT_P_VALID(inputP)); + CY_ASSERT_L3(CY_LPCOMP_IS_INPUT_N_VALID(inputN)); + + switch(inputP) + { + case CY_LPCOMP_SW_AMUXBUSA: + { + input = (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_AP0_Msk : LPCOMP_CMP1_SW_CMP1_AP1_Msk; + HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR, 3u); + break; + } + case CY_LPCOMP_SW_AMUXBUSB: + { + input = (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_BP0_Msk : LPCOMP_CMP1_SW_CMP1_BP1_Msk; + HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR, 3u); + break; + } + default: + { + input = (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_IP0_Msk : LPCOMP_CMP1_SW_CMP1_IP1_Msk; + break; + } + } + + switch(inputN) + { + case CY_LPCOMP_SW_AMUXBUSA: + { + input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_AN0_Msk : LPCOMP_CMP1_SW_CMP1_AN1_Msk; + HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR, 3u); + break; + } + case CY_LPCOMP_SW_AMUXBUSB: + { + input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_BN0_Msk : LPCOMP_CMP1_SW_CMP1_BN1_Msk; + HSIOM->AMUX_SPLIT_CTL[3] = _CLR_SET_FLD32U(HSIOM->AMUX_SPLIT_CTL[3], CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR, 3u); + break; + } + case CY_LPCOMP_SW_LOCAL_VREF: + { + input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_VN0_Msk : LPCOMP_CMP1_SW_CMP1_VN1_Msk; + break; + } + default: + { + input |= (channel == CY_LPCOMP_CHANNEL_0) ? LPCOMP_CMP0_SW_CMP0_IN0_Msk : LPCOMP_CMP1_SW_CMP1_IN1_Msk; + break; + } + } + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_SW_CLEAR = CY_LPCOMP_CMP0_SW_POS_Msk | CY_LPCOMP_CMP0_SW_NEG_Msk; + base->CMP0_SW = input; + } + else + { + base->CMP1_SW_CLEAR = CY_LPCOMP_CMP1_SW_POS_Msk | CY_LPCOMP_CMP1_SW_NEG_Msk; + base->CMP1_SW = input; + } +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetOutputMode +****************************************************************************//** +* +* Sets the type of the comparator DSI output. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \param outType +* Interrupt edge trigger selection +* CY_LPCOMP_OUT_PULSE (=0) - the DSI output with the pulse option, no bypass +* CY_LPCOMP_OUT_DIRECT (=1) - the bypass mode, the direct output of the comparator +* CY_LPCOMP_OUT_SYNC (=2) - DSI output with the level option, it is similar to the +* bypass mode but it is 1 cycle slow than the bypass. +* [DSI_LEVELx : DSI_BYPASSx] = [Bit11 : Bit10] +* 0 : 0 = 0x00 -> Pulse (PULSE) +* 1 : 0 = 0x02 -> Level (SYNC) +* x : 1 = 0x01 -> Bypass (Direct). +* +* \return None +* +*******************************************************************************/ +void Cy_LPComp_SetOutputMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_out_t outType) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(outType)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_CTRL = _CLR_SET_FLD32U(base->CMP0_CTRL, CY_LPCOMP_CMP0_OUTPUT_CONFIG, (uint32_t)outType); + } + else + { + base->CMP1_CTRL = _CLR_SET_FLD32U(base->CMP1_CTRL, CY_LPCOMP_CMP1_OUTPUT_CONFIG, (uint32_t)outType); + } +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_DeepSleepCallback +****************************************************************************//** +* +* This function checks the current power mode of LPComp and then disables the +* LPComp block if there is no wake-up source from LPComp in the deep-sleep mode. +* It stores the state of the LPComp enable and then disables the LPComp block +* before going to the low power modes, and recovers the LPComp power state after +* wake-up using the stored value. +* +* \param *callbackParams +* The \ref cy_stc_syspm_callback_params_t structure with the callback +* parameters which consists of mode, base and context fields: +* *base - LPComp register structure pointer; +* *context - Context for the call-back function; +* mode +* CY_SYSPM_CHECK_READY - No action for this state. +* CY_SYSPM_CHECK_FAIL - No action for this state. +* CY_SYSPM_BEFORE_TRANSITION - Checks the LPComp interrupt mask and the power +* mode, and then disables or enables the LPComp block +* according to the condition. +* Stores the LPComp state to recover the state after +* wake up. +* CY_SYSPM_AFTER_TRANSITION - Enables the LPComp block, if it was disabled +* before the sleep mode. +* +* \return +* \ref cy_en_syspm_status_t +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams) +{ + cy_en_syspm_status_t ret = CY_SYSPM_FAIL; + LPCOMP_Type *locBase = (LPCOMP_Type *) (callbackParams->base); + static uint32_t enabled_status; + + switch(callbackParams->mode) + { + case CY_SYSPM_CHECK_READY: + { + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_CHECK_FAIL: + { + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_BEFORE_TRANSITION: + { + /* Save the LPComp the enabled/disabled status. */ + enabled_status = _FLD2VAL(LPCOMP_CONFIG_ENABLED, locBase->CONFIG); + + if (0u != enabled_status) + { + /* Disable the LPComp block when there is no wake-up source from any channel. */ + if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, locBase->CMP0_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) && + _FLD2BOOL(LPCOMP_INTR_MASK_COMP0_MASK, locBase->INTR_MASK)) || + ((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, locBase->CMP1_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) && + _FLD2BOOL(LPCOMP_INTR_MASK_COMP1_MASK, locBase->INTR_MASK))) ) + + { + /* Disable the LPComp block to avoid leakage. */ + Cy_LPComp_GlobalDisable(locBase); + } + else + { + /* Set LPComp the status to the not changed state. */ + enabled_status = 0u; + } + } + else + { + /* The LPComp block was already disabled and + * the system is allowed to go to the low power mode. + */ + } + + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_AFTER_TRANSITION: + { + /* Enable LPComp to operate if it was enabled + * before entering to the low power mode. + */ + if (0u != enabled_status) + { + Cy_LPComp_GlobalEnable(locBase); + } + else + { + /* The LPComp block was disabled before calling this API + * with mode = CY_SYSPM_CHECK_READY. + */ + } + + ret = CY_SYSPM_SUCCESS; + } + break; + + default: + break; + } + + return (ret); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_HibernateCallback +****************************************************************************//** +* +* This function checks the current power mode of LPComp and then disable the +* LPComp block, if there is no wake-up source from LPComp in the hibernate mode. +* +* \param *callbackParams +* The \ref cy_stc_syspm_callback_params_t structure with the callback +* parameters which consists of mode, base and context fields: +* *base - LPComp register structure pointer; +* *context - Context for the call-back function; +* mode +* CY_SYSPM_CHECK_READY - No action for this state. +* CY_SYSPM_CHECK_FAIL - No action for this state. +* CY_SYSPM_BEFORE_TRANSITION - Checks the wake-up source from the hibernate mode +* of the LPComp block, and then disables or enables +* the LPComp block according to the condition. +* +* \return +* \ref cy_en_syspm_status_t +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams) +{ + cy_en_syspm_status_t ret = CY_SYSPM_FAIL; + LPCOMP_Type *locBase = (LPCOMP_Type *) (callbackParams->base); + static uint32_t enabled_status; + + switch(callbackParams->mode) + { + case CY_SYSPM_CHECK_READY: + { + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_CHECK_FAIL: + { + ret = CY_SYSPM_SUCCESS; + } + break; + + case CY_SYSPM_BEFORE_TRANSITION: + { + /* Save the LPComp the enabled/disabled status. */ + enabled_status = _FLD2VAL(LPCOMP_CONFIG_ENABLED, locBase->CONFIG); + + if (0u != enabled_status) + { + /* Disable the LPComp block when there is no wake-up source from any channel. */ + if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, locBase->CMP0_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) && + _FLD2BOOL(CY_LPCOMP_WAKEUP_PIN0, SRSS->PWR_HIBERNATE)) || + ((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, locBase->CMP1_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) && + _FLD2BOOL(CY_LPCOMP_WAKEUP_PIN1, SRSS->PWR_HIBERNATE))) ) + + { + /* Disable the LPComp block to avoid leakage. */ + Cy_LPComp_GlobalDisable(locBase); + } + else + { + /* Set LPComp the status to the not changed state. */ + enabled_status = 0u; + } + } + else + { + /* The LPComp block was already disabled and + * the system is allowed to go to the low power mode. + */ + } + + ret = CY_SYSPM_SUCCESS; + } + break; + + default: + break; + } + + return (ret); +} + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h new file mode 100644 index 0000000000..1e57e7da0e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h @@ -0,0 +1,717 @@ +/***************************************************************************//** +* \file cy_lpcomp.h +* \version 1.10.1 +* +* This file provides constants and parameter values for the Low Power Comparator driver. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +/** +* \defgroup group_lpcomp Low Power Comparator (LPComp) +* \{ +* Provides access to the low-power comparators implemented using the fixed-function +* LP comparator block that is present in PSoC 6. +* +* These comparators can perform fast analog signal comparison of internal +* and external analog signals in all system power modes. Low-power comparator +* output can be inspected by the CPU, used as an interrupt/wakeup source to the +* CPU when in low-power mode (Sleep, Low-Power Sleep, or Deep-Sleep), used as +* a wakeup source to system resources when in Hibernate mode, or fed to DSI as +* an asynchronous or synchronous signal (level or pulse). +* +* \section group_lpcomp_section_Configuration_Considerations Configuration Considerations +* To set up an LPComp, the inputs, the output, the mode, the interrupts and +* other configuration parameters should be configured. Power the LPComp to operate. +* +* The sequence recommended for the LPComp operation: +* +* 1) To initialize the driver, call the Cy_LPComp_Init() function providing +* the filled cy_stc_lpcomp_config_t structure, the LPComp channel number, +* and the LPCOMP registers structure pointer. +* +* 2) Optionally, configure the interrupt requests if the interrupt event +* triggering is needed. Use the Cy_LPComp_SetInterruptMask() function with +* the parameter for the mask available in the configuration file. +* Additionally, enable the Global interrupts and initialize the referenced +* interrupt by setting the priority and the interrupt vector using +* the \ref Cy_SysInt_Init() function of the sysint driver. +* +* 3) Configure the inputs and the output using the \ref Cy_GPIO_Pin_Init() +* functions of the GPIO driver. +* The High Impedance Analog drive mode is for the inputs and +* the Strong drive mode is for the output. +* Use the Cy_LPComp_SetInputs() function to connect the comparator inputs +* to the dedicated IO pins, AMUXBUSA/AMUXBUSB or Vref: +* \image html lpcomp_inputs.png +* +* 4) Power on the comparator using the Cy_LPComp_Enable() function. +* +* 5) The comparator output can be monitored using +* the Cy_LPComp_GetCompare() function or using the LPComp interrupt +* (if the interrupt is enabled). +* +* \note The interrupt is not cleared automatically. +* It is the user's responsibility to do that. +* The interrupt is cleared by writing a 1 in the corresponding interrupt +* register bit position. The preferred way to clear interrupt sources +* is using the Cy_LPComp_ClearInterrupt() function. +* +* \note Individual comparator interrupt outputs are ORed together +* as a single asynchronous interrupt source before it is sent out and +* used to wake up the system in the low-power mode. +* For PSoC 6 devices, the individual comparator interrupt is masked +* by the INTR_MASK register. The masked result is captured in +* the INTR_MASKED register. +* Writing a 1 to the INTR register bit will clear the interrupt. +* +* \section group_lpcomp_lp Low Power Support +* The LPComp provides the callback functions to facilitate +* the low-power mode transition. The callback +* \ref Cy_LPComp_DeepSleepCallback must be called during execution +* of \ref Cy_SysPm_DeepSleep; \ref Cy_LPComp_HibernateCallback must be +* called during execution of \ref Cy_SysPm_Hibernate. +* To trigger the callback execution, the callback must be registered +* before calling the mode transition function. +* Refer to \ref group_syspm driver for more +* information about low-power mode transitions. +* +* \section group_lpcomp_more_information More Information +* +* Refer to the appropriate device technical reference manual (TRM) for +* a detailed description of the registers. +* +* \section group_lpcomp_MISRA MISRA-C Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AA cast should not be performed between a pointer to object type and +* a different pointer to object type. +* The pointer to the buffer memory is void to allow handling different +* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits). +* The cast operation is safe because the configuration is verified +* before operation is performed. +* The function \ref Cy_LPComp_DeepSleepCallback is a callback of +* the \ref cy_en_syspm_status_t type. The cast operation safety in this +* function becomes the user's responsibility because the pointers are +* initialized when a callback is registered in the SysPm driver.
+* +* \section group_lpcomp_Changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.10.1Added Low Power Callback sectionDocumentation update and clarification
1.10The CY_WEAK keyword is removed from Cy_LPComp_DeepSleepCallback() +* and Cy_LPComp_HibernateCallback() functions
+* Added input parameter validation to the API functions.
1.0Initial version
+* +* \defgroup group_lpcomp_macros Macros +* \defgroup group_lpcomp_functions Functions +* \{ +* \defgroup group_lpcomp_functions_syspm_callback Low Power Callback +* \} +* \defgroup group_lpcomp_data_structures Data Structures +* \defgroup group_lpcomp_enums Enumerated Types +*/ + +#ifndef CY_LPCOMP_PDL_H +#define CY_LPCOMP_PDL_H + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include +#include +#include "cy_device_headers.h" +#include "syslib/cy_syslib.h" +#include "syspm/cy_syspm.h" + +#ifndef CY_IP_MXLPCOMP + #error "The LPCOMP driver is not supported on this device" +#endif + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \addtogroup group_lpcomp_macros +* \{ +*/ + +/** Driver major version */ +#define CY_LPCOMP_DRV_VERSION_MAJOR 1 + +/** Driver minor version */ +#define CY_LPCOMP_DRV_VERSION_MINOR 10 + +/****************************************************************************** +* API Constants +******************************************************************************/ + +/**< LPCOMP PDL ID */ +#define CY_LPCOMP_ID CY_PDL_DRV_ID(0x23u) + +/** The LPCOMP's number of channels. */ +#define CY_LPCOMP_MAX_CHANNEL_NUM (2u) + +/** LPCOMP's comparator 1 interrupt mask. */ +#define CY_LPCOMP_COMP0 (0x01u) +/** LPCOMP's comparator 2 interrupt mask. */ +#define CY_LPCOMP_COMP1 (0x02u) + +/** \cond INTERNAL_MACROS */ + + +/****************************************************************************** +* Registers Constants +******************************************************************************/ + +#define CY_LPCOMP_MODE_ULP_Pos (0x0uL) +#define CY_LPCOMP_MODE_ULP_Msk (0x1uL) + +#define CY_LPCOMP_INTR_Pos (LPCOMP_INTR_COMP0_Pos) +#define CY_LPCOMP_INTR_Msk (LPCOMP_INTR_COMP0_Msk | LPCOMP_INTR_COMP1_Msk) + +#define CY_LPCOMP_CMP0_SW_POS_Msk (LPCOMP_CMP0_SW_CMP0_IP0_Msk | \ + LPCOMP_CMP0_SW_CMP0_AP0_Msk | \ + LPCOMP_CMP0_SW_CMP0_BP0_Msk) +#define CY_LPCOMP_CMP0_SW_NEG_Msk (LPCOMP_CMP0_SW_CMP0_IN0_Msk | \ + LPCOMP_CMP0_SW_CMP0_AN0_Msk | \ + LPCOMP_CMP0_SW_CMP0_BN0_Msk | \ + LPCOMP_CMP0_SW_CMP0_VN0_Msk) +#define CY_LPCOMP_CMP1_SW_POS_Msk (LPCOMP_CMP1_SW_CMP1_IP1_Msk | \ + LPCOMP_CMP1_SW_CMP1_AP1_Msk | \ + LPCOMP_CMP1_SW_CMP1_BP1_Msk) +#define CY_LPCOMP_CMP1_SW_NEG_Msk (LPCOMP_CMP1_SW_CMP1_IN1_Msk | \ + LPCOMP_CMP1_SW_CMP1_AN1_Msk | \ + LPCOMP_CMP1_SW_CMP1_BN1_Msk | \ + LPCOMP_CMP1_SW_CMP1_VN1_Msk) + +#define CY_LPCOMP_CMP0_OUTPUT_CONFIG_Pos LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos +#define CY_LPCOMP_CMP1_OUTPUT_CONFIG_Pos LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos + +#define CY_LPCOMP_CMP0_OUTPUT_CONFIG_Msk (LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk | \ + LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk) + +#define CY_LPCOMP_CMP1_OUTPUT_CONFIG_Msk (LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk | \ + LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk) + +#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR_Pos HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos + +#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR_Msk (HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | \ + HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk) + +#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR_Pos HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos + +#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR_Msk (HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | \ + HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk) + +#define CY_LPCOMP_REF_CONNECTED (1u) + +#define CY_LPCOMP_WAKEUP_PIN0_Msk CY_SYSPM_WAKEUP_LPCOMP0 +#define CY_LPCOMP_WAKEUP_PIN1_Msk CY_SYSPM_WAKEUP_LPCOMP1 + +/* Internal constants for Cy_LPComp_Enable() */ +#define CY_LPCOMP_NORMAL_POWER_DELAY (3u) +#define CY_LPCOMP_LP_POWER_DELAY (6u) +#define CY_LPCOMP_ULP_POWER_DELAY (50u) + +/** \endcond */ +/** \} group_lpcomp_macros */ + +/** +* \addtogroup group_lpcomp_enums +* \{ +*/ + +/****************************************************************************** + * Enumerations + *****************************************************************************/ +/** The LPCOMP output modes. */ +typedef enum +{ + CY_LPCOMP_OUT_PULSE = 0u, /**< The LPCOMP DSI output with the pulse option, no bypass. */ + CY_LPCOMP_OUT_DIRECT = 1u, /**< The LPCOMP bypass mode, the direct output of a comparator. */ + CY_LPCOMP_OUT_SYNC = 2u /**< The LPCOMP DSI output with the level option, it is similar + to the bypass mode but it is 1 cycle slow than the bypass. */ +} cy_en_lpcomp_out_t; + +/** The LPCOMP hysteresis modes. */ +typedef enum +{ + CY_LPCOMP_HYST_ENABLE = 1u, /**< The LPCOMP enable hysteresis. */ + CY_LPCOMP_HYST_DISABLE = 0u /**< The LPCOMP disable hysteresis. */ +} cy_en_lpcomp_hyst_t; + +/** The LPCOMP's channel number. */ +typedef enum +{ + CY_LPCOMP_CHANNEL_0 = 0x1u, /**< The LPCOMP Comparator 0. */ + CY_LPCOMP_CHANNEL_1 = 0x2u /**< The LPCOMP Comparator 1. */ +} cy_en_lpcomp_channel_t; + +/** The LPCOMP interrupt modes. */ +typedef enum +{ + CY_LPCOMP_INTR_DISABLE = 0u, /**< The LPCOMP interrupt disabled, no interrupt will be detected. */ + CY_LPCOMP_INTR_RISING = 1u, /**< The LPCOMP interrupt on the rising edge. */ + CY_LPCOMP_INTR_FALLING = 2u, /**< The LPCOMP interrupt on the falling edge. */ + CY_LPCOMP_INTR_BOTH = 3u /**< The LPCOMP interrupt on both rising and falling edges. */ +} cy_en_lpcomp_int_t; + +/** The LPCOMP power-mode selection. */ +typedef enum +{ + CY_LPCOMP_MODE_OFF = 0u, /**< The LPCOMP's channel power-off. */ + CY_LPCOMP_MODE_ULP = 1u, /**< The LPCOMP's channel ULP mode. */ + CY_LPCOMP_MODE_LP = 2u, /**< The LPCOMP's channel LP mode. */ + CY_LPCOMP_MODE_NORMAL = 3u /**< The LPCOMP's channel normal mode. */ +} cy_en_lpcomp_pwr_t; + +/** The LPCOMP inputs. */ +typedef enum +{ + CY_LPCOMP_SW_GPIO = 0x01u, /**< The LPCOMP input connects to GPIO pin. */ + CY_LPCOMP_SW_AMUXBUSA = 0x02u, /**< The LPCOMP input connects to AMUXBUSA. */ + CY_LPCOMP_SW_AMUXBUSB = 0x04u, /**< The LPCOMP input connects to AMUXBUSB. */ + CY_LPCOMP_SW_LOCAL_VREF = 0x08u /**< The LPCOMP input connects to local VREF. */ +} cy_en_lpcomp_inputs_t; + +/** The LPCOMP error codes. */ +typedef enum +{ + CY_LPCOMP_SUCCESS = 0x00u, /**< Successful */ + CY_LPCOMP_BAD_PARAM = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */ + CY_LPCOMP_TIMEOUT = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x02u, /**< Operation timed out */ + CY_LPCOMP_INVALID_STATE = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x03u, /**< Operation not setup or is in an improper state */ + CY_LPCOMP_UNKNOWN = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0xFFu, /**< Unknown failure */ +} cy_en_lpcomp_status_t; + +/** \} group_lpcomp_enums */ + +/** +* \addtogroup group_lpcomp_data_structures +* \{ +*/ + +/****************************************************************************** + * Structures + *****************************************************************************/ + +/** The LPCOMP configuration structure. */ +typedef struct { + cy_en_lpcomp_out_t outputMode; /**< The LPCOMP's outputMode: Direct output, + Synchronized output or Pulse output */ + cy_en_lpcomp_hyst_t hysteresis; /**< Enables or disables the LPCOMP's hysteresis */ + cy_en_lpcomp_pwr_t power; /**< Sets the LPCOMP power mode */ + cy_en_lpcomp_int_t intType; /**< Sets the LPCOMP interrupt mode */ +} cy_stc_lpcomp_config_t; + +/** \cond CONTEXT_STRUCTURE */ + +typedef struct { + cy_en_lpcomp_int_t intType[CY_LPCOMP_MAX_CHANNEL_NUM]; + cy_en_lpcomp_pwr_t power[CY_LPCOMP_MAX_CHANNEL_NUM]; +} cy_stc_lpcomp_context_t; + +/** \endcond */ + +/** \} group_lpcomp_data_structures */ + +/** \cond INTERNAL_MACROS */ + +/****************************************************************************** + * Macros + *****************************************************************************/ +#define CY_LPCOMP_IS_CHANNEL_VALID(channel) (((channel) == CY_LPCOMP_CHANNEL_0) || \ + ((channel) == CY_LPCOMP_CHANNEL_1)) +#define CY_LPCOMP_IS_OUT_MODE_VALID(mode) (((mode) == CY_LPCOMP_OUT_PULSE) || \ + ((mode) == CY_LPCOMP_OUT_DIRECT) || \ + ((mode) == CY_LPCOMP_OUT_SYNC)) +#define CY_LPCOMP_IS_HYSTERESIS_VALID(hyst) (((hyst) == CY_LPCOMP_HYST_ENABLE) || \ + ((hyst) == CY_LPCOMP_HYST_DISABLE)) +#define CY_LPCOMP_IS_INTR_MODE_VALID(intr) (((intr) == CY_LPCOMP_INTR_DISABLE) || \ + ((intr) == CY_LPCOMP_INTR_RISING) || \ + ((intr) == CY_LPCOMP_INTR_FALLING) || \ + ((intr) == CY_LPCOMP_INTR_BOTH)) +#define CY_LPCOMP_IS_POWER_VALID(power) (((power) == CY_LPCOMP_MODE_OFF) || \ + ((power) == CY_LPCOMP_MODE_ULP) || \ + ((power) == CY_LPCOMP_MODE_LP) || \ + ((power) == CY_LPCOMP_MODE_NORMAL)) +#define CY_LPCOMP_IS_INTR_VALID(intr) (((intr) == CY_LPCOMP_COMP0) || \ + ((intr) == CY_LPCOMP_COMP1) || \ + ((intr) == (CY_LPCOMP_COMP0 | CY_LPCOMP_COMP1))) +#define CY_LPCOMP_IS_INPUT_P_VALID(input) (((input) == CY_LPCOMP_SW_GPIO) || \ + ((input) == CY_LPCOMP_SW_AMUXBUSA) || \ + ((input) == CY_LPCOMP_SW_AMUXBUSB)) +#define CY_LPCOMP_IS_INPUT_N_VALID(input) (((input) == CY_LPCOMP_SW_GPIO) || \ + ((input) == CY_LPCOMP_SW_AMUXBUSA) || \ + ((input) == CY_LPCOMP_SW_AMUXBUSB) || \ + ((input) == CY_LPCOMP_SW_LOCAL_VREF)) + +/** \endcond */ + +/** +* \addtogroup group_lpcomp_functions +* \{ +*/ + +/****************************************************************************** +* Functions +*******************************************************************************/ + +cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel, const cy_stc_lpcomp_config_t *config); +void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel); +void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel); +__STATIC_INLINE void Cy_LPComp_GlobalEnable(LPCOMP_Type *base); +__STATIC_INLINE void Cy_LPComp_GlobalDisable(LPCOMP_Type *base); +__STATIC_INLINE void Cy_LPComp_UlpReferenceEnable(LPCOMP_Type *base); +__STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base); +__STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lpcomp_channel_t channel); +void Cy_LPComp_SetPower(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_pwr_t power); +void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_hyst_t hysteresis); +void Cy_LPComp_SetInputs(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_inputs_t inputP, cy_en_lpcomp_inputs_t inputN); +void Cy_LPComp_SetOutputMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_out_t outType); +void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_int_t intType); +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatus(LPCOMP_Type const * base); +__STATIC_INLINE void Cy_LPComp_ClearInterrupt(LPCOMP_Type* base, uint32_t interrupt); +__STATIC_INLINE void Cy_LPComp_SetInterrupt(LPCOMP_Type* base, uint32_t interrupt); +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base); +__STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t interrupt); +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const * base); +__STATIC_INLINE void Cy_LPComp_ConnectULPReference(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel); +/** \addtogroup group_lpcomp_functions_syspm_callback +* The driver supports SysPm callback for Deep Sleep and Hibernate transition. +* \{ +*/ +cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams); +cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams); +/** \} */ + + +/******************************************************************************* +* Function Name: Cy_LPComp_GlobalEnable +****************************************************************************//** +* +* Activates the IP of the LPCOMP hardware block. This API should be enabled +* before operating any channel of comparators. +* Note: Interrupts can be enabled after the block is enabled and the appropriate +* start-up time has elapsed: +* 3 us for the normal power mode; +* 6 us for the LP mode; +* 50 us for the ULP mode. +* +* \param *base +* The structure of the channel pointer. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_GlobalEnable(LPCOMP_Type* base) +{ + base->CONFIG |= LPCOMP_CONFIG_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_GlobalDisable +****************************************************************************//** +* +* Deactivates the IP of the LPCOMP hardware block. +* (Analog in power down, open all switches, all clocks off). +* +* \param *base +* The structure of the channel pointer. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_GlobalDisable(LPCOMP_Type *base) +{ + base->CONFIG &= (uint32_t) ~LPCOMP_CONFIG_ENABLED_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_UlpReferenceEnable +****************************************************************************//** +* +* Enables the local reference-generator circuit. +* +* \param *base +* The structure of the channel pointer. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_UlpReferenceEnable(LPCOMP_Type *base) +{ + base->CONFIG |= LPCOMP_CONFIG_LPREF_EN_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_UlpReferenceDisable +****************************************************************************//** +* +* Disables the local reference-generator circuit. +* +* \param *base +* The structure of the channel pointer. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base) +{ + base->CONFIG &= (uint32_t) ~LPCOMP_CONFIG_LPREF_EN_Msk; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_GetCompare +****************************************************************************//** +* +* This function returns a nonzero value when the voltage connected to the +* positive input is greater than the negative input voltage. +* +* \param *base +* The LPComp register structure pointer. +* +* \param channel +* The LPComp channel index. +* +* \return LPComp compare result. +* The value is a nonzero value when the voltage connected to the positive +* input is greater than the negative input voltage. +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lpcomp_channel_t channel) +{ + uint32_t result; + + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + result = _FLD2VAL(LPCOMP_STATUS_OUT0, base->STATUS); + } + else + { + result = _FLD2VAL(LPCOMP_STATUS_OUT1, base->STATUS); + } + + return (result); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetInterruptMask +****************************************************************************//** +* +* Configures which bits of the interrupt request register will trigger an +* interrupt event. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param interrupt +* uint32_t interruptMask: Bit Mask of interrupts to set. +* Bit 0: COMP0 Interrupt Mask +* Bit 1: COMP1 Interrupt Mask +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt)); + + base->INTR_MASK |= interrupt; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_GetInterruptMask +****************************************************************************//** +* +* Returns an interrupt mask. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \return bit mapping information +* Bit 0: COMP0 Interrupt Mask +* Bit 1: COMP1 Interrupt Mask +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base) +{ + return (base->INTR_MASK); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_GetInterruptStatusMasked +****************************************************************************//** +* +* Returns an interrupt request register masked by an interrupt mask. +* Returns the result of the bitwise AND operation between the corresponding +* interrupt request and mask bits. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \return bit mapping information +* Bit 0: COMP0 Interrupt Masked +* Bit 1: COMP1 Interrupt Masked +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const * base) +{ + return (base->INTR_MASKED); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_GetInterruptStatus +****************************************************************************//** +* +* Returns the status of 2 different LPCOMP interrupt requests. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \return bit mapping information +* Bit 0: COMP0 Interrupt status +* Bit 1: COMP1 Interrupt status +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatus(LPCOMP_Type const * base) +{ + return (_FLD2VAL(CY_LPCOMP_INTR, base->INTR)); +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_ClearInterrupt +****************************************************************************//** +* +* Clears LPCOMP interrupts by setting each bit. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param interrupt +* Bit 0: COMP0 Interrupt status +* Bit 1: COMP1 Interrupt status +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_ClearInterrupt(LPCOMP_Type* base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt)); + base->INTR |= interrupt; + (void) LPCOMP->INTR; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_SetInterrupt +****************************************************************************//** +* +* Sets a software interrupt request. +* This function is used in the case of combined interrupt signal from the global +* signal reference. This function from either component instance can be used +* to trigger either or both software interrupts. It sets the INTR_SET interrupt mask. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param interrupt +* Bit 0: COMP0 Interrupt status +* Bit 1: COMP1 Interrupt status +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_SetInterrupt(LPCOMP_Type* base, uint32_t interrupt) +{ + CY_ASSERT_L2(CY_LPCOMP_IS_INTR_VALID(interrupt)); + base->INTR_SET = interrupt; +} + + +/******************************************************************************* +* Function Name: Cy_LPComp_ConnectULPReference +****************************************************************************//** +* +* Connects the local reference generator output to the comparator negative input. +* +* \param *base +* The LPCOMP register structure pointer. +* +* \param channel +* The LPCOMP channel index. +* +* \return None +* +*******************************************************************************/ +__STATIC_INLINE void Cy_LPComp_ConnectULPReference(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel) +{ + CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); + + if (CY_LPCOMP_CHANNEL_0 == channel) + { + base->CMP0_SW_CLEAR = CY_LPCOMP_CMP0_SW_NEG_Msk; + base->CMP0_SW = _CLR_SET_FLD32U(base->CMP0_SW, LPCOMP_CMP0_SW_CMP0_VN0, CY_LPCOMP_REF_CONNECTED); + } + else + { + base->CMP1_SW_CLEAR = CY_LPCOMP_CMP1_SW_NEG_Msk; + base->CMP1_SW = _CLR_SET_FLD32U(base->CMP1_SW, LPCOMP_CMP1_SW_CMP1_VN1, CY_LPCOMP_REF_CONNECTED); + } +} + +/** \} group_lpcomp_functions */ + +#ifdef __cplusplus +} +#endif + +#endif /* CY_LPCOMP_PDL_H */ + +/** \} group_lpcomp */ + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.c b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.c new file mode 100644 index 0000000000..3f49ae3d6e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.c @@ -0,0 +1,62 @@ +/***************************************************************************//** +* \file cy_lvd.c +* \version 1.0.1 +* +* The source code file for the LVD driver. +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +#include "cy_lvd.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Function Name: Cy_LVD_DeepSleepCallback +****************************************************************************//** +* +* When this function is registered by \ref Cy_SysPm_RegisterCallback - it +* automatically enables the LVD after wake up from Deep-Sleep mode. +* +* \param callbackParams The pointer to the callback parameters structure, +* see \ref cy_stc_syspm_callback_params_t. +* +* \return the SysPm callback status \ref cy_en_syspm_status_t. +* +*******************************************************************************/ +cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams) +{ + cy_en_syspm_status_t ret = CY_SYSPM_SUCCESS; + + switch(callbackParams->mode) + { + case CY_SYSPM_CHECK_READY: + case CY_SYSPM_CHECK_FAIL: + case CY_SYSPM_BEFORE_TRANSITION: + break; + + case CY_SYSPM_AFTER_TRANSITION: + Cy_LVD_Enable(); + break; + + default: + ret = CY_SYSPM_FAIL; + break; + } + + return(ret); +} + + +#ifdef __cplusplus +} +#endif + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.h b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.h new file mode 100644 index 0000000000..5c9d529006 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.h @@ -0,0 +1,433 @@ +/***************************************************************************//** +* \file cy_lvd.h +* \version 1.0.1 +* +* The header file of the LVD driver. +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + +/** +* \addtogroup group_lvd +* \{ +* The LVD driver provides an API to manage the Low Voltage Detection block. +* The LVD block provides a status of currently observed VDDD voltage +* and triggers an interrupt when the observed voltage crosses an adjusted +* threshold. +* +* \section group_lvd_configuration_considerations Configuration Considerations +* To set up an LVD, configure the voltage threshold by the +* \ref Cy_LVD_SetThreshold function, ensure that the LVD block itself and LVD +* interrupt are disabled (by the \ref Cy_LVD_Disable and +* \ref Cy_LVD_ClearInterruptMask functions correspondingly) before changing the +* threshold to prevent propagating a false interrupt. +* Then configure interrupts by the \ref Cy_LVD_SetInterruptConfig function, do +* not forget to initialise an interrupt handler (the interrupt source number +* is srss_interrupt_IRQn). +* Then enable LVD by the \ref Cy_LVD_Enable function, then wait for at least 20us +* to get the circuit stabilized and clear the possible false interrupts by the +* \ref Cy_LVD_ClearInterrupt, and finally the LVD interrupt can be enabled by +* the \ref Cy_LVD_SetInterruptMask function. +* +* For example: +* \snippet lvd_1_0_sut_00.cydsn/main_cm4.c Cy_LVD_Snippet +* +* Note that the LVD circuit is available only in Active, LPACTIVE, Sleep, and +* LPSLEEP power modes. If an LVD is required in Deep-Sleep mode, then the device +* should be configured to periodically wake up from deep sleep using a +* Deep-Sleep wakeup source. This makes sure a LVD check is performed during +* Active/LPACTIVE mode. +* +* \section group_lvd_more_information More Information +* See the LVD chapter of the device technical reference manual (TRM). +* +* \section group_lvd_MISRA MISRA-C Compliance +* The LVD driver has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
10.3RA composite expression of 'essentially unsigned' type (%1s) is being +* cast to a different type category, '%2s'.The value got from the bitfield physically can't exceed the enumeration +* that describes this bitfield. So the code is safety by design.
16.7AThe object addressed by the pointer parameter '%s' is not modified and +* so the pointer could be of type 'pointer to const'.The pointer parameter is not used or modified, as there is no need +* to do any actions with it. However, such parameter is +* required to be presented in the function, because the +* \ref Cy_LVD_DeepSleepCallback is a callback +* of \ref cy_en_syspm_status_t type. +* The SysPM driver callback function type requires implementing the +* function with the next parameters and return value:
+* cy_en_syspm_status_t (*Cy_SysPmCallback) +* (cy_stc_syspm_callback_params_t *callbackParams);
+* +* \section group_lvd_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason of Change
1.0.1Added Low Power Callback sectionDocumentation update and clarification
1.0Initial Version
+* +* \defgroup group_lvd_macros Macros +* \defgroup group_lvd_functions Functions +* \{ +* \defgroup group_lvd_functions_syspm_callback Low Power Callback +* \} +* \defgroup group_lvd_enums Enumerated Types +*/ + + +#if !defined CY_LVD_H +#define CY_LVD_H + +#include "syspm/cy_syspm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \addtogroup group_lvd_macros +* \{ +*/ + +/** The driver major version */ +#define CY_LVD_DRV_VERSION_MAJOR 1 + +/** The driver minor version */ +#define CY_LVD_DRV_VERSION_MINOR 0 + +/** The LVD driver identifier */ +#define CY_LVD_ID (CY_PDL_DRV_ID(0x39U)) + +/** Interrupt mask for \ref Cy_LVD_GetInterruptStatus(), + \ref Cy_LVD_GetInterruptMask() and + \ref Cy_LVD_GetInterruptStatusMasked() */ +#define CY_LVD_INTR (SRSS_SRSS_INTR_HVLVD1_Msk) + +/** \} group_lvd_macros */ + + +/** \addtogroup group_lvd_enums +* \{ +*/ + + +/** + * LVD reference voltage select. + */ +typedef enum +{ + CY_LVD_THRESHOLD_1_2_V = 0x0U, /**