mirror of https://github.com/ARMmbed/mbed-os.git
modify for the RWW function of Macronix Flash
rogeryou
parent
0c6753bb82
commit
0db8da1152
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@ -42,4 +42,17 @@ uint8_t _sfdp_basic_param_table[64] = {0x30, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF,
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uint8_t _sfdp_4_byte_inst_table[8] = {0x7F, 0xEF, 0xFF, 0xFF, 0x21, 0x5C, 0xDC, 0x14};
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#endif
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//#define MX_FLASH_SUPPORT_RWW 1
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#define MX25LM51245G_FLASH_SIZE 0x4000000 /* 512 MBits => 64 MBytes */
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#define MX25LM51245G_BLOCK_SIZE 0x10000 /* 1024 blocks of 64 KBytes */
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#define MX25LM51245G_SECTOR_SIZE 0x1000 /* 16384 sectors of 4 kBytes */
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#define MX25LM51245G_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */
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#define MX25LM51245G_CHUNK_SIZE 0x10 /* fred: 16 bytes */
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#ifdef MX_FLASH_SUPPORT_RWW
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#define MX25LM51245G_BANK_SIZE 0x01000000 /* fred: 16 MBytes */
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#define MX25LM51245G_BANK_SIZE_MASK ~(MX25LM51245G_BANK_SIZE - 1) /* fred: 0xFF000000 */
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#endif
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#endif // MBED_OSPI_FLASH_MX25LM51245G_H
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@ -62,6 +62,8 @@
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#define MBED_CONF_OSPIF_OSPI_FREQ 40000000
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#endif
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#define MX_FLASH_SUPPORT_RWW
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/** Enum ospif standard error codes
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*
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* @enum ospif_bd_error
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@ -381,6 +383,10 @@ private:
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// Detect 4-byte addressing mode and enable it if supported
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int _sfdp_detect_and_enable_4byte_addressing(uint8_t *basic_param_table_ptr, int basic_param_table_size);
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#ifdef MX_FLASH_SUPPORT_RWW
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bool _is_mem_ready_rww(bd_addr_t addr, uint8_t rw);
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#endif
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private:
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enum ospif_clear_protection_method_t {
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OSPIF_BP_ULBPR, // Issue global protection unlock instruction
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@ -449,6 +455,16 @@ private:
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uint32_t _init_ref_count;
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bool _is_initialized;
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#ifdef MX_FLASH_SUPPORT_RWW
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enum wait_flag {
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NOT_STARTED, // no wait is started
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WRITE_WAIT_STARTED, // write wait is started
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ERASE_WAIT_STARTED, // erase wait is started
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};
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uint32_t _busy_bank; // Current busy bank
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wait_flag _wait_flag; // wait flag
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PlatformMutex _busy_mutex;
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#endif
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};
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#endif
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@ -52,7 +52,16 @@ using namespace mbed;
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#define OSPIF_NO_QUAD_ENABLE (-1)
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// Configuration Register2 address
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#define OSPIF_CR2_OPI_EN_ADDR 0x00000000
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#define OSPIF_CR2_OPI_EN_ADDR 0x00000000
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#define OSPIF_CR2_BANK_STATUS_ADDR 0xc0000000
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#define OSPIF_CR2_RWWDI ((uint8_t)0x00) /*!< No active program or erase operation */
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#define OSPIF_CR2_RWWDS ((uint8_t)0x01) /*!< Program/erase in other bank */
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#define OSPIF_CR2_RWWBS ((uint8_t)0x03) /*!< program/erase operation in addressed bank */
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#ifdef MX_FLASH_SUPPORT_RWW
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#define MX25LM51245G_BANK_SIZE 0x01000000 /* 16 MBytes */
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#define MX25LM51245G_BANK_SIZE_MASK ~(MX25LM51245G_BANK_SIZE - 1) /* 0xFF000000 */
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#endif
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/* SFDP Header Parsing */
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/***********************/
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@ -232,6 +241,11 @@ OSPIFBlockDevice::OSPIFBlockDevice(PinName io0, PinName io1, PinName io2, PinNam
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_attempt_4_byte_addressing = true;
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_4byte_msb_reg_write_inst = OSPIF_INST_4BYTE_REG_WRITE_DEFAULT;
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_support_4_byte_inst = false;
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#ifdef MX_FLASH_SUPPORT_RWW
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_wait_flag = NOT_STARTED;
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_busy_bank = 0xffffffff;
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#endif
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}
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int OSPIFBlockDevice::init()
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@ -358,6 +372,17 @@ int OSPIFBlockDevice::deinit()
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return result;
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}
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if (false == _is_mem_ready()) {
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tr_error("Device not ready after write, failed");
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/* program_failed = true;
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status = OSPIF_BD_ERROR_READY_FAILED;
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goto exit_point;*/
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}
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#ifdef MX_FLASH_SUPPORT_RWW
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_wait_flag = NOT_STARTED;
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#endif
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change_mode(SPI);
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// Disable Device for Writing
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@ -383,6 +408,29 @@ int OSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size)
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int status = OSPIF_BD_ERROR_OK;
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tr_debug("Read Inst: 0x%xh", _read_instruction);
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#ifdef MX_FLASH_SUPPORT_RWW
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bool need_wait;
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need_wait = (_wait_flag != NOT_STARTED) && ((addr & MX25LM51245G_BANK_SIZE_MASK) == _busy_bank);
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// Wait for ready
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if (need_wait) {
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_busy_mutex.lock();
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if (_is_mem_ready_rww(addr, false) == false) {
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return OSPIF_BD_ERROR_OK;
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}
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} else {
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if (_wait_flag == WRITE_WAIT_STARTED) {
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tr_debug("\r\n RWW1 CNT");
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} else if (_wait_flag == ERASE_WAIT_STARTED) {
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tr_debug("\r\n RWE2 CNT");
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}
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}
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#endif
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_mutex.lock();
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// In DOPI mode, the number of read data should be even
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@ -397,8 +445,13 @@ int OSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size)
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_mutex.unlock();
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return status;
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#ifdef MX_FLASH_SUPPORT_RWW
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if (need_wait) {
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_busy_mutex.unlock();
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}
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#endif
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return status;
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}
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int OSPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size)
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@ -418,6 +471,16 @@ int OSPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size
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chunk = (offset + size < _page_size_bytes) ? size : (_page_size_bytes - offset);
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written_bytes = chunk;
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#ifdef MX_FLASH_SUPPORT_RWW
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_busy_mutex.lock();
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// Wait for ready
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if (_is_mem_ready_rww(addr, true) == false) {
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return OSPIF_BD_ERROR_OK;
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}
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#endif
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_mutex.lock();
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//Send WREN
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@ -437,10 +500,14 @@ int OSPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size
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goto exit_point;
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}
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buffer = static_cast<const uint8_t *>(buffer) + chunk;
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addr += chunk;
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size -= chunk;
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#ifdef MX_FLASH_SUPPORT_RWW
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_wait_flag = WRITE_WAIT_STARTED;
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_busy_bank = addr & MX25LM51245G_BANK_SIZE_MASK;
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_mutex.unlock();
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_busy_mutex.unlock();
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#else
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if (false == _is_mem_ready()) {
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tr_error("Device not ready after write, failed");
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program_failed = true;
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@ -448,6 +515,11 @@ int OSPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size
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goto exit_point;
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}
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_mutex.unlock();
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#endif
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buffer = static_cast<const uint8_t *>(buffer) + chunk;
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addr += chunk;
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size -= chunk;
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}
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exit_point:
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@ -511,6 +583,15 @@ int OSPIFBlockDevice::erase(bd_addr_t addr, bd_size_t size)
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tr_debug("Erase - Region: %d, Type:%d ",
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region, type);
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#ifdef MX_FLASH_SUPPORT_RWW
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_busy_mutex.lock();
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// Wait for ready
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if (_is_mem_ready_rww(addr, true) == false) {
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return OSPIF_BD_ERROR_OK;
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}
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#endif
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_mutex.lock();
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if (_set_write_enable() != 0) {
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@ -527,15 +608,14 @@ int OSPIFBlockDevice::erase(bd_addr_t addr, bd_size_t size)
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goto exit_point;
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}
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addr += eu_size;
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size -= eu_size;
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#ifdef MX_FLASH_SUPPORT_RWW
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_wait_flag = ERASE_WAIT_STARTED;
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_busy_bank = addr & MX25LM51245G_BANK_SIZE_MASK;
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if ((size > 0) && (addr > _sfdp_info.smptbl.region_high_boundary[region])) {
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// erase crossed to next region
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region++;
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bitfield = _sfdp_info.smptbl.region_erase_types_bitfld[region];
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}
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_mutex.unlock();
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_busy_mutex.unlock();
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#else
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if (false == _is_mem_ready()) {
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tr_error("OSPI After Erase Device not ready - failed");
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erase_failed = true;
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@ -544,6 +624,16 @@ int OSPIFBlockDevice::erase(bd_addr_t addr, bd_size_t size)
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}
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_mutex.unlock();
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#endif
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addr += eu_size;
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size -= eu_size;
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if ((size > 0) && (addr > _sfdp_info.smptbl.region_high_boundary[region])) {
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// erase crossed to next region
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region++;
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bitfield = _sfdp_info.smptbl.region_erase_types_bitfld[region];
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}
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}
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exit_point:
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@ -1537,6 +1627,51 @@ bool OSPIFBlockDevice::_is_mem_ready()
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return mem_ready;
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}
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#ifdef MX_FLASH_SUPPORT_RWW
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bool OSPIFBlockDevice::_is_mem_ready_rww(bd_addr_t addr, uint8_t rw)
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{
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uint16_t cr2_value = 0;
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bool mem_ready = true;
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static uint32_t rww_cnt = 0; // For testing
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static uint32_t rwe_cnt = 0; // For testing
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bd_addr_t bank_addr = addr & MX25LM51245G_BANK_SIZE_MASK;
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if ((_wait_flag == NOT_STARTED) || (!rw && bank_addr != _busy_bank)) {
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return mem_ready;
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}
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//Read CR2 Register 1 from device, the number of read byte need to be even in octa flash DOPI mode
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if (OSPI_STATUS_OK != _ospi_send_general_command(OSPIF_INST_RDCR2, bank_addr + OSPIF_CR2_BANK_STATUS_ADDR,
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NULL, 0,
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(char *) &cr2_value, OSPI_DEFAULT_STATUS_REGISTERS)) { // store received value in cr2_value
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tr_error("Reading CR2 Register failed");
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}
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cr2_value &= OSPIF_CR2_RWWBS;
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if ((cr2_value == OSPIF_CR2_RWWBS) || (rw && (cr2_value == OSPIF_CR2_RWWDS))) {
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// Wait until device ready
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if (false == _is_mem_ready()) {
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tr_error(" _is_mem_ready Failed");
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mem_ready = false;
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}
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_wait_flag = NOT_STARTED;
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} else if (!rw && (cr2_value == OSPIF_CR2_RWWDS)) {
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// For testing
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if (_wait_flag == WRITE_WAIT_STARTED) {
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rww_cnt++;
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tr_debug("rww_cnt = 0x%x ", rww_cnt);
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} else {
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rwe_cnt++;
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tr_debug("rwe_cnt = 0x%x ", rwe_cnt);
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}
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}
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return mem_ready;
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}
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#endif
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/***************************************************/
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/*********** OSPI Driver API Functions *************/
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/***************************************************/
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@ -1665,9 +1800,12 @@ ospi_status_t OSPIFBlockDevice::_ospi_send_general_command(ospi_inst_t instructi
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if ((_inst_width == OSPI_CFG_BUS_OCTA) || (_inst_width == OSPI_CFG_BUS_OCTA_DTR)) {
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if ((instruction == OSPIF_INST_RSR1) || (instruction == OSPIF_INST_RDID) ||
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(instruction == OSPIF_INST_RDCR2) || (instruction == OSPIF_INST_RDCR)) {
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_ospi.configure_format(_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE, 0, _data_width, _dummy_cycles);
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addr = 0;
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} else if (instruction == OSPIF_INST_WSR1) {
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_ospi.configure_format(_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE,
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0, _data_width, 4);
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if (instruction != OSPIF_INST_RDCR2) {
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addr = 0;
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}
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} else if ((instruction == OSPIF_INST_WSR1)) {
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addr = 0;
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}
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}
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@ -433,6 +433,89 @@ void test_multi_threads()
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}
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#endif
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#if defined(MX_FLASH_SUPPORT_RWW)
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void test_rww_rwe()
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{
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utest_printf("\nTest rww and rwe Starts..\n");
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TEST_SKIP_UNLESS_MESSAGE(block_device != NULL, "no block device found.");
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utest_printf("\ntest read bank1 data when write bank0\n");
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// Determine start_address in bank 0
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bd_addr_t start_address_B0 = sectors_addr[rand() % num_of_sectors];
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utest_printf("start_address_B0=0x%016" PRIx64 "\n", start_address_B0);
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// Determine start_address in bank 1
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bd_addr_t start_address_B1 = start_address_B0 | 0x1000000;
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utest_printf("start_address_B1=0x%016" PRIx64 "\n", start_address_B1);
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// Determine data_buf_size
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bd_size_t erase_size = block_device->get_erase_size(start_address_B0);
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TEST_ASSERT(erase_size > 0);
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bd_size_t data_buf_size = block_device->get_program_size();;
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// Allocate buffer for write test data
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uint8_t *data_buf = new (std::nothrow) uint8_t[data_buf_size];
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TEST_SKIP_UNLESS_MESSAGE(data_buf != NULL, "Not enough memory for test");
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// Allocate buffer for read test data
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uint8_t *out_data_buf = new (std::nothrow) uint8_t[data_buf_size];
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TEST_SKIP_UNLESS_MESSAGE(out_data_buf != NULL, "Not enough memory for test");
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// First must Erase given memory region
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utest_printf("erasing given memory region in bank0\n");
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int err = block_device->erase(start_address_B0, erase_size);
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TEST_ASSERT_EQUAL(0, err);
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utest_printf("erasing given memory region in bank1\n");
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err = block_device->erase(start_address_B1, erase_size);
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TEST_ASSERT_EQUAL(0, err);
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// Write random data to selected region to make sure data is not accidentally set to "erased" value.
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// With this pre-write, the test case will fail even if block_device->erase() is broken.
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for (bd_size_t i = 0; i < data_buf_size; i++) {
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data_buf[i] = (uint8_t) rand();
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}
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utest_printf("writing given memory region in bank1\n");
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err = block_device->program((const void *)data_buf, start_address_B1, data_buf_size);
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TEST_ASSERT_EQUAL(0, err);
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memset(out_data_buf, 0, data_buf_size);
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utest_printf("writing given memory region in bank0\n");
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err = block_device->program((const void *)data_buf, start_address_B0, data_buf_size);
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TEST_ASSERT_EQUAL(0, err);
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// Read written memory region in bank1 to verify it contains information
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// utest_printf("reading written memory region in bank1 when write bank0\n");
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err = block_device->read((void *)out_data_buf, start_address_B1, data_buf_size);
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TEST_ASSERT_EQUAL(0, err);
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// Verify erased memory region
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utest_printf("verifying written memory region\n");
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for (bd_size_t i = 0; i < data_buf_size; i++) {
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TEST_ASSERT_EQUAL(out_data_buf[i], data_buf[i]);
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}
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utest_printf("\ntest read bank1 data when erase bank0\n");
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utest_printf("erasing given memory region in bank0\n");
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memset(out_data_buf, 0, data_buf_size);
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err = block_device->erase(start_address_B0, erase_size);
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TEST_ASSERT_EQUAL(0, err);
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// Read written memory region in bank1 to verify it contains information
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utest_printf("reading written memory region in bank1 when erase bank0\n");
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err = block_device->read((void *)out_data_buf, start_address_B1, data_buf_size);
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TEST_ASSERT_EQUAL(0, err);
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delete[] out_data_buf;
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delete[] data_buf;
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}
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#endif
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void test_erase_functionality()
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{
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utest_printf("\nTest BlockDevice::get_erase_value()..\n");
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@ -816,6 +899,9 @@ template_case_t template_cases[] = {
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{"Testing BlockDevice erase functionality", test_erase_functionality, greentea_failure_handler},
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{"Testing program read small data sizes", test_program_read_small_data_sizes, greentea_failure_handler},
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{"Testing unaligned erase blocks", test_unaligned_erase_blocks, greentea_failure_handler},
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#if defined(MX_FLASH_SUPPORT_RWW)
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{"Testing read while write and read while erase", test_rww_rwe, greentea_failure_handler},
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#endif
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{"Testing Deinit block device", test_deinit_bd, greentea_failure_handler},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
|
||||
/* Max amount of flash size is 4Gbytes */
|
||||
/* hence 2^(31+1), then FLASH_SIZE_DEFAULT = 1<<31 */
|
||||
#define OSPI_FLASH_SIZE_DEFAULT 0x80000000
|
||||
#define OSPI_FLASH_SIZE_DEFAULT 0x4000000 //512Mbits
|
||||
|
||||
static uint32_t get_alt_bytes_size(const uint32_t num_bytes)
|
||||
{
|
||||
|
|
@ -252,7 +252,7 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap,
|
|||
obj->handle.Init.ClockPrescaler = 4; // default value, will be overwritten in ospi_frequency
|
||||
obj->handle.Init.FifoThreshold = 4;
|
||||
obj->handle.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE;
|
||||
obj->handle.Init.DeviceSize = POSITION_VAL(OSPI_FLASH_SIZE_DEFAULT) - 1;
|
||||
obj->handle.Init.DeviceSize = 32;
|
||||
obj->handle.Init.ChipSelectHighTime = 3;
|
||||
obj->handle.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;
|
||||
#if defined(HAL_OSPI_WRAP_NOT_SUPPORTED) // removed in STM32L4
|
||||
|
|
|
|||
Loading…
Reference in New Issue