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Merge pull request #16 from ARMmbed/nordic_sdk_integration 

Nordic sdk integration
pull/2234/head
Vincent Coubard 2016-07-04 10:37:15 +01:00 committed by GitHub
parent e5b7579bae 6a31d1abc1
commit 0d9dc1e079
361 changed files with 84971 additions and 20066 deletions
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73
hal/targets.json
View File

@ -1100,9 +1100,15 @@
"inherits": ["Target"],
"core": "Cortex-M0",
"OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
"macros": ["NRF51", "TARGET_NRF51822"],
"macros": [
"NRF51",
"TARGET_NRF51822",
"BLE_STACK_SUPPORT_REQD",
"SOFTDEVICE_PRESENT",
"S130"
],
"MERGE_BOOTLOADER": false,
"extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822"],
"extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822", "NRF5"],
"OUTPUT_EXT": "hex",
"is_disk_virtual": true,
"supported_toolchains": ["ARM", "GCC_ARM"],
@ -1110,29 +1116,9 @@
"MERGE_SOFT_DEVICE": true,
"EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
{
"boot": "s130_nrf51_1.0.0_bootloader.hex",
"name": "s130_nrf51_1.0.0_softdevice.hex",
"offset": 114688
},
{
"boot": "s110_nrf51822_8.0.0_bootloader.hex",
"name": "s110_nrf51822_8.0.0_softdevice.hex",
"offset": 98304
},
{
"boot": "s110_nrf51822_7.1.0_bootloader.hex",
"name": "s110_nrf51822_7.1.0_softdevice.hex",
"offset": 90112
},
{
"boot": "s110_nrf51822_7.0.0_bootloader.hex",
"name": "s110_nrf51822_7.0.0_softdevice.hex",
"offset": 90112
},
{
"boot": "s110_nrf51822_6.0.0_bootloader.hex",
"name": "s110_nrf51822_6.0.0_softdevice.hex",
"offset": 81920
"boot": "",
"name": "s130_nrf51_2.0.0_softdevice.hex",
"offset": 110592
}
],
"detect_code": ["1070"],
@ -1140,7 +1126,8 @@
"function": "MCU_NRF51Code.binary_hook",
"toolchains": ["ARM_STD", "GCC_ARM"]
},
"program_cycle_s": 6
"program_cycle_s": 6,
"features": ["BLE"]
},
"MCU_NRF51_16K_BASE": {
"inherits": ["MCU_NRF51"],
@ -1388,7 +1375,7 @@
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF51_32K"],
"progen": {"target": "nrf51-dk"},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"]
},
"NRF51_DK_BOOT": {
"supported_form_factors": ["ARDUINO"],
@ -1738,11 +1725,11 @@
"MCU_NRF52": {
"inherits": ["Target"],
"core": "Cortex-M4F",
"macros": ["NRF52", "TARGET_NRF52832"],
"extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832"],
"macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132"],
"extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5"],
"OUTPUT_EXT": "hex",
"is_disk_virtual": true,
"supported_toolchains": ["ARM", "GCC_ARM"],
"supported_toolchains": ["GCC_ARM"],
"public": false,
"detect_code": ["1101"],
"program_cycle_s": 6,
@ -1758,12 +1745,34 @@
"function": "MCU_NRF51Code.binary_hook",
"toolchains": ["ARM_STD", "GCC_ARM"]
},
"MERGE_BOOTLOADER": false
"MERGE_BOOTLOADER": false,
"features": ["BLE"]
},
"NRF52_DK": {
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF52"],
"progen": {"target": "nrf52-dk"},
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
"macros_add": [
"BOARD_PCA10040",
"NRF52_PAN_12",
"NRF52_PAN_15",
"NRF52_PAN_58",
"NRF52_PAN_55",
"NRF52_PAN_54",
"NRF52_PAN_31",
"NRF52_PAN_30",
"NRF52_PAN_51",
"NRF52_PAN_36",
"NRF52_PAN_53",
"S132",
"CONFIG_GPIO_AS_PINRESET",
"BLE_STACK_SUPPORT_REQD",
"SWI_DISABLE0",
"NRF52_PAN_20",
"NRF52_PAN_64",
"NRF52_PAN_62",
"NRF52_PAN_63"
],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"]
}
}

109
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h
View File

@ -1,109 +0,0 @@
/* Copyright (c) 2013, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _COMPILER_ABSTRACTION_H
#define _COMPILER_ABSTRACTION_H
/*lint ++flb "Enter library region" */
#if defined ( __CC_ARM )
#ifndef __ASM
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#endif
#ifndef __INLINE
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#endif
#ifndef __WEAK
#define __WEAK __weak /*!< weak keyword for ARM Compiler */
#endif
#define GET_SP() __current_sp() /*!> read current SP function for ARM Compiler */
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#endif
#ifndef __INLINE
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#endif
#ifndef __WEAK
#define __WEAK __weak /*!> define weak function for IAR Compiler */
#endif
#define GET_SP() __get_SP() /*!> read current SP function for IAR Compiler */
#elif defined ( __GNUC__ )
#ifndef __ASM
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#endif
#ifndef __INLINE
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak)) /*!< weak keyword for GNU Compiler */
#endif
#define GET_SP() gcc_current_sp() /*!> read current SP function for GNU Compiler */
static inline unsigned int gcc_current_sp(void)
{
register unsigned sp asm("sp");
return sp;
}
#elif defined ( __TASKING__ )
#ifndef __ASM
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#endif
#ifndef __INLINE
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak)) /*!< weak keyword for TASKING Compiler */
#endif
#define GET_SP() __get_MSP() /*!> read current SP function for TASKING Compiler */
#endif
/*lint --flb "Leave library region" */
#endif

48
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h
View File

@ -1,48 +0,0 @@
/* Copyright (c) 2013, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_H
#define NRF_H
#ifndef _WIN32
/* Family selection for main includes. NRF51 must be selected. */
#ifdef NRF51
#include "nrf51.h"
#include "nrf51_bitfields.h"
#else
#error "Device family must be defined. See nrf.h."
#endif /* NRF51 */
#include "compiler_abstraction.h"
#endif /* _WIN32 */
#endif /* NRF_H */

74
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h
View File

@ -1,74 +0,0 @@
#ifndef _NRF_DELAY_H
#define _NRF_DELAY_H
// #include "nrf.h"
/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
#if defined ( __CC_ARM )
static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
{
loop
SUBS R0, R0, #1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
BNE loop
BX LR
}
#elif defined ( __ICCARM__ )
static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
{
__ASM (
"loop:\n\t"
" SUBS R0, R0, #1\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" BNE loop\n\t");
}
#elif defined ( __GNUC__ )
__INLINE static void nrf_delay_us(uint32_t volatile number_of_us)
{
do
{
__ASM volatile (
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
"NOP\n\t"
);
} while (--number_of_us);
}
#endif
void nrf_delay_ms(uint32_t volatile number_of_ms);
#endif

187
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c
View File

@ -1,187 +0,0 @@
/* Copyright (c) 2013, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* NOTE: Template files (including this one) are application specific and therefore expected to
be copied into the application project folder prior to its use! */
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "nrf_delay.h"
#include "system_nrf51.h"
/*lint ++flb "Enter library region" */
#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
static bool is_manual_peripheral_setup_needed(void);
static bool is_disabled_in_debug_needed(void);
static void init_clock(void);
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
#elif defined ( __ICCARM__ )
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
#endif
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
void SystemInit(void)
{
#if defined(TARGET_NRF_32MHZ_XTAL)
/* For 32MHz HFCLK XTAL such as Taiyo Yuden
Physically, tiny footprint XTAL oscillate higher freq. To make BLE modules smaller, some modules
are using 32MHz XTAL.
This code wriging the value 0xFFFFFF00 to the UICR (User Information Configuration Register)
at address 0x10001008, to make nRF51 works with 32MHz system clock. This register will be overwritten
by SoftDevice to 0xFFFFFFFF, the default value. Each hex files built with mbed classic online compiler
contain SoftDevice, so that, this code run once just after the hex file will be flashed onto nRF51.
After changing the value, nRF51 need to reboot. */
if (*(uint32_t *)0x10001008 == 0xFFFFFFFF)
{
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
*(uint32_t *)0x10001008 = 0xFFFFFF00;
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
while (true){}
}
#endif
/* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
It can also be done in the application main() function. */
/* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
to enable the use of peripherals" found at Product Anomaly document for your device found at
https://www.nordicsemi.com/. The side effect of executing these instructions in the devices
that do not need it is that the new peripherals in the second generation devices (LPCOMP for
example) will not be available. */
if (is_manual_peripheral_setup_needed())
{
*(uint32_t volatile *)0x40000504 = 0xC007FFDF;
*(uint32_t volatile *)0x40006C18 = 0x00008000;
}
/* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
register is incorrect" found at Product Anomaly document four your device found at
https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
if (is_disabled_in_debug_needed())
{
NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
}
// Start the external 32khz crystal oscillator.
init_clock();
}
void init_clock(void)
{
/* For compatibility purpose, the default behaviour is to first attempt to initialise an
external clock, and after a timeout, use the internal RC one. To avoid this wait, boards that
don't have an external oscillator can set TARGET_NRF_LFCLK_RC directly. */
uint32_t i = 0;
const uint32_t polling_period = 200;
const uint32_t timeout = 1000000;
#if defined(TARGET_NRF_LFCLK_RC)
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos);
#else
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
#endif
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
NRF_CLOCK->TASKS_LFCLKSTART = 1;
/* Wait for the external oscillator to start up.
nRF51822 product specification (8.1.5) gives a typical value of 300ms for external clock
startup duration, and a maximum value of 1s. When using the internal RC source, typical delay
will be 390µs, so we use a polling period of 200µs.
We can't use us_ticker at this point, so we have to rely on a less precise method for
measuring our timeout. Because of this, the actual timeout will be slightly longer than 1
second, which isn't an issue at all, since this fallback should only be used as a safety net.
*/
for (i = 0; i < (timeout / polling_period); i++) {
if (NRF_CLOCK->EVENTS_LFCLKSTARTED != 0)
return;
nrf_delay_us(polling_period);
}
/* Fallback to internal clock. Belt and braces, since the internal clock is used by default
whilst no external source is running. This is not only a sanity check, but it also allows
code down the road (e.g. ble initialisation) to directly know which clock is used. */
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos);
NRF_CLOCK->TASKS_LFCLKSTART = 1;
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
// Do nothing.
}
}
static bool is_manual_peripheral_setup_needed(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
{
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
}
return false;
}
static bool is_disabled_in_debug_needed(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
{
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
}
return false;
}
/*lint --flb "Leave library region" */

68
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h
View File

@ -1,68 +0,0 @@
/* Copyright (c) 2013, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef SYSTEM_NRF51_H
#define SYSTEM_NRF51_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_NRF51_H */

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/sys.cpp → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/sys.cpp
View File

13
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld
View File

@ -2,8 +2,8 @@
MEMORY
{
FLASH (rx) : ORIGIN = 0x0001C000, LENGTH = 0x24000
RAM (rwx) : ORIGIN = 0x20002800, LENGTH = 0x5800
FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x25000
RAM (rwx) : ORIGIN = 0x20002ef8, LENGTH = 0x5108
}
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
@ -114,6 +114,15 @@ SECTIONS
} > RAM
__edata = .;
.fs_data :
{
PROVIDE(__start_fs_data = .);
KEEP(*(.fs_data))
PROVIDE(__stop_fs_data = .);
} > RAM
.bss :
{
. = ALIGN(4);

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld
View File

78
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/startup_NRF51822.S → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/startup_NRF51822.S
View File

@ -1,32 +1,41 @@
/*
Copyright (c) 2013, Nordic Semiconductor ASA
All rights reserved.
/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
NOTE: Template files (including this one) are application specific and therefore
@ -117,8 +126,9 @@ __Vectors:
/* Reset Handler */
.equ NRF_POWER_RAMON_ADDRESS, 0x40000524
.equ NRF_POWER_RAMON_RAMxON_ONMODE_Msk, 0x3
.equ NRF_POWER_RAMON_ADDRESS, 0x40000524
.equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
.equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
.text
.thumb
@ -129,10 +139,14 @@ __Vectors:
Reset_Handler:
.fnstart
/* Make sure ALL RAM banks are powered on */
MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R1
STR R2, [R0]
LDR R0, =NRF_POWER_RAMONB_ADDRESS
LDR R2, [R0]
ORRS R2, R1
STR R2, [R0]

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/cmsis.h
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.c → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/cmsis_nvic.c
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/cmsis_nvic.h
View File

170
hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/system_nrf51.c Normal file
View File

@ -0,0 +1,170 @@
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* NOTE: Template files (including this one) are application specific and therefore expected to
be copied into the application project folder prior to its use! */
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "system_nrf51.h"
/*lint ++flb "Enter library region" */
#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
static bool is_manual_peripheral_setup_needed(void);
static bool is_disabled_in_debug_needed(void);
static bool is_peripheral_domain_setup_needed(void);
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
#elif defined ( __ICCARM__ )
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
#endif
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
void SystemInit(void)
{
/* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
It can also be done in the application main() function. */
/* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
to enable the use of peripherals" found at Product Anomaly document for your device found at
https://www.nordicsemi.com/. The side effect of executing these instructions in the devices
that do not need it is that the new peripherals in the second generation devices (LPCOMP for
example) will not be available. */
if (is_manual_peripheral_setup_needed())
{
*(uint32_t volatile *)0x40000504 = 0xC007FFDF;
*(uint32_t volatile *)0x40006C18 = 0x00008000;
}
/* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
register is incorrect" found at Product Anomaly document for your device found at
https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
if (is_disabled_in_debug_needed())
{
NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
}
/* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices,
as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
for your device found at https://www.nordicsemi.com/. */
if (is_peripheral_domain_setup_needed()){
if (*(uint32_t volatile *)0x4006EC00 != 1){
*(uint32_t volatile *)0x4006EC00 = 0x9375;
while (*(uint32_t volatile *)0x4006EC00 != 1){
}
}
*(uint32_t volatile *)0x4006EC14 = 0xC0;
}
// Start the external 32khz crystal oscillator.
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
NRF_CLOCK->TASKS_LFCLKSTART = 1;
// Wait for the external oscillator to start up.
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
// Do nothing.
}
}
static bool is_manual_peripheral_setup_needed(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
{
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
}
return false;
}
static bool is_disabled_in_debug_needed(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
{
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
}
return false;
}
static bool is_peripheral_domain_setup_needed(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
{
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xA0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xD0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
{
return true;
}
}
return false;
}
/*lint --flb "Leave library region" */

78
hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/system_nrf51.h Normal file
View File

@ -0,0 +1,78 @@
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef SYSTEM_NRF51_H
#define SYSTEM_NRF51_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_NRF51_H */

1
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/NRF52832.ld → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/NRF52832.ld
View File

@ -83,7 +83,6 @@ SECTIONS
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)

65
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/startup_NRF52832.S → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/startup_NRF52832.S
View File

@ -1,32 +1,41 @@
/*
Copyright (c) 2013, Nordic Semiconductor ASA
All rights reserved.
/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
NOTE: Template files (including this one) are application specific and therefore

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/cmsis.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis.h
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/cmsis_nvic.c → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis_nvic.c
View File

0
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/cmsis_nvic.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis_nvic.h
View File

37
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/system_nrf52.c → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/system_nrf52.c
View File

@ -1,22 +1,28 @@
/*
* Copyright (c) Nordic Semiconductor ASA
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific prior written permission.
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -27,9 +33,10 @@
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
@ -191,11 +198,7 @@ void SystemInit(void)
SystemCoreClockUpdate();
// Start the external 32khz crystal oscillator.
#if defined(TARGET_NRF_LFCLK_RC)
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos);
#else
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
#endif
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
NRF_CLOCK->TASKS_LFCLKSTART = 1;

33
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/system_nrf52.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/system_nrf52.h
View File

@ -1,22 +1,28 @@
/*
* Copyright (c) Nordic Semiconductor ASA
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific prior written permission.
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -27,9 +33,10 @@
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
#ifndef SYSTEM_NRF52_H
#define SYSTEM_NRF52_H

33
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/compiler_abstraction.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/compiler_abstraction.h
View File

@ -1,22 +1,28 @@
/*
* Copyright (c) Nordic Semiconductor ASA
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific prior written permission.
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -27,8 +33,9 @@
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
#ifndef _COMPILER_ABSTRACTION_H
#define _COMPILER_ABSTRACTION_H

34
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/nrf.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf.h
View File

@ -1,22 +1,28 @@
/*
* Copyright (c) Nordic Semiconductor ASA
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific prior written permission.
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -27,9 +33,10 @@
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
#ifndef NRF_H
#define NRF_H
@ -65,3 +72,4 @@
#endif /* _WIN32 || __unix || __APPLE__ */
#endif /* NRF_H */

165
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51.h
View File

@ -1,33 +1,33 @@
/****************************************************************************************************//**
* @file nRF51.h
* @file nrf51.h
*
* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
* nRF51 from Nordic Semiconductor.
* nrf51 from Nordic Semiconductor.
*
* @version V522
* @date 31. October 2014
* @date 23. February 2016
*
* @note Generated with SVDConv V2.81d
* from CMSIS SVD File 'nRF51.xml' Version 522,
* @note Generated with SVDConv V2.81d
* from CMSIS SVD File 'nrf51.svd' Version 522,
*
* @par Copyright (c) 2013, Nordic Semiconductor ASA
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -38,7 +38,7 @@
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*
*******************************************************************************************************/
@ -48,7 +48,7 @@
* @{
*/
/** @addtogroup nRF51
/** @addtogroup nrf51
* @{
*/
@ -71,7 +71,7 @@ typedef enum {
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
RADIO_IRQn = 1, /*!< 1 RADIO */
UART0_IRQn = 2, /*!< 2 UART0 */
@ -117,7 +117,8 @@ typedef enum {
/** @} */ /* End of group Configuration_of_CMSIS */
#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
#include "system_nrf51.h" /*!< nRF51 System */
#include "system_nrf51.h" /*!< nrf51 System */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
@ -183,15 +184,6 @@ typedef struct {
__IO uint32_t TEP; /*!< Channel task end-point. */
} PPI_CH_Type;
typedef struct {
__I uint32_t PART; /*!< Part code */
__I uint32_t VARIANT; /*!< Part variant */
__I uint32_t PACKAGE; /*!< Package option */
__I uint32_t RAM; /*!< RAM variant */
__I uint32_t FLASH; /*!< Flash variant */
__I uint32_t RESERVED[3]; /*!< Reserved */
} FICR_INFO_Type;
/* ================================================================================ */
/* ================ POWER ================ */
@ -300,27 +292,6 @@ typedef struct { /*!< MPU Structure
} NRF_MPU_Type;
/* ================================================================================ */
/* ================ PU ================ */
/* ================================================================================ */
/**
* @brief Patch unit. (PU)
*/
typedef struct { /*!< PU Structure */
__I uint32_t RESERVED0[448];
__IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
__I uint32_t RESERVED1[24];
__IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
__I uint32_t RESERVED2[24];
__IO uint32_t PATCHEN; /*!< Patch enable register. */
__IO uint32_t PATCHENSET; /*!< Patch enable register. */
__IO uint32_t PATCHENCLR; /*!< Patch disable register. */
} NRF_PU_Type;
/* ================================================================================ */
/* ================ AMLI ================ */
/* ================================================================================ */
@ -366,7 +337,7 @@ typedef struct { /*!< RADIO Structure
__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
sample is ready for readout at the RSSISAMPLE register. */
__I uint32_t RESERVED1[2];
__IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
__IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
__I uint32_t RESERVED2[53];
__IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
__I uint32_t RESERVED3[64];
@ -374,11 +345,11 @@ typedef struct { /*!< RADIO Structure
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
__I uint32_t RESERVED4[61];
__I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
__I uint32_t CD; /*!< Carrier detect. */
__I uint32_t RESERVED5;
__I uint32_t RXMATCH; /*!< Received address. */
__I uint32_t RXCRC; /*!< Received CRC. */
__I uint32_t DAI; /*!< Device address match index. */
__I uint32_t RESERVED5[60];
__I uint32_t RESERVED6[60];
__IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
__IO uint32_t FREQUENCY; /*!< Frequency. */
__IO uint32_t TXPOWER; /*!< Output power. */
@ -397,22 +368,22 @@ typedef struct { /*!< RADIO Structure
__IO uint32_t TEST; /*!< Test features enable register. */
__IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
__I uint32_t RSSISAMPLE; /*!< RSSI sample. */
__I uint32_t RESERVED6;
__I uint32_t RESERVED7;
__I uint32_t STATE; /*!< Current radio state. */
__IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
__I uint32_t RESERVED7[2];
__I uint32_t RESERVED8[2];
__IO uint32_t BCC; /*!< Bit counter compare. */
__I uint32_t RESERVED8[39];
__I uint32_t RESERVED9[39];
__IO uint32_t DAB[8]; /*!< Device address base segment. */
__IO uint32_t DAP[8]; /*!< Device address prefix. */
__IO uint32_t DACNF; /*!< Device address match configuration. */
__I uint32_t RESERVED9[56];
__I uint32_t RESERVED10[56];
__IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
__IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
__IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
__IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
__IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
__I uint32_t RESERVED10[561];
__I uint32_t RESERVED11[561];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_RADIO_Type;
@ -571,39 +542,41 @@ typedef struct { /*!< SPIS Structure
__O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
__I uint32_t RESERVED1[54];
__IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
__I uint32_t RESERVED2[8];
__I uint32_t RESERVED2[2];
__IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
__I uint32_t RESERVED3[5];
__IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
__I uint32_t RESERVED3[53];
__I uint32_t RESERVED4[53];
__IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
__I uint32_t RESERVED4[64];
__I uint32_t RESERVED5[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
__I uint32_t RESERVED5[61];
__I uint32_t RESERVED6[61];
__I uint32_t SEMSTAT; /*!< Semaphore status. */
__I uint32_t RESERVED6[15];
__I uint32_t RESERVED7[15];
__IO uint32_t STATUS; /*!< Status from last transaction. */
__I uint32_t RESERVED7[47];
__I uint32_t RESERVED8[47];
__IO uint32_t ENABLE; /*!< Enable SPIS. */
__I uint32_t RESERVED8;
__I uint32_t RESERVED9;
__IO uint32_t PSELSCK; /*!< Pin select for SCK. */
__IO uint32_t PSELMISO; /*!< Pin select for MISO. */
__IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
__IO uint32_t PSELCSN; /*!< Pin select for CSN. */
__I uint32_t RESERVED9[7];
__I uint32_t RESERVED10[7];
__IO uint32_t RXDPTR; /*!< RX data pointer. */
__IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
__I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
__I uint32_t RESERVED10;
__I uint32_t RESERVED11;
__IO uint32_t TXDPTR; /*!< TX data pointer. */
__IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
__I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
__I uint32_t RESERVED11;
__IO uint32_t CONFIG; /*!< Configuration register. */
__I uint32_t RESERVED12;
__IO uint32_t CONFIG; /*!< Configuration register. */
__I uint32_t RESERVED13;
__IO uint32_t DEF; /*!< Default character. */
__I uint32_t RESERVED13[24];
__I uint32_t RESERVED14[24];
__IO uint32_t ORC; /*!< Over-read character. */
__I uint32_t RESERVED14[654];
__I uint32_t RESERVED15[654];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_SPIS_Type;
@ -628,35 +601,28 @@ typedef struct { /*!< SPIM Structure
__IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
__I uint32_t RESERVED3[2];
__IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
__I uint32_t RESERVED4;
__IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
__I uint32_t RESERVED5;
__I uint32_t RESERVED4[3];
__IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
__I uint32_t RESERVED6[10];
__I uint32_t RESERVED5[10];
__IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
__I uint32_t RESERVED7[44];
__IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
__I uint32_t RESERVED8[64];
__I uint32_t RESERVED6[109];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
__I uint32_t RESERVED9[125];
__I uint32_t RESERVED7[125];
__IO uint32_t ENABLE; /*!< Enable SPIM. */
__I uint32_t RESERVED10;
__I uint32_t RESERVED8;
SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
__I uint32_t RESERVED11;
__I uint32_t RXDDATA; /*!< RXD register. */
__IO uint32_t TXDDATA; /*!< TXD register. */
__I uint32_t RESERVED12;
__I uint32_t RESERVED9[4];
__IO uint32_t FREQUENCY; /*!< SPI frequency. */
__I uint32_t RESERVED13[3];
__I uint32_t RESERVED10[3];
SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
__I uint32_t RESERVED14;
__I uint32_t RESERVED11;
SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
__I uint32_t RESERVED15;
__I uint32_t RESERVED12;
__IO uint32_t CONFIG; /*!< Configuration register. */
__I uint32_t RESERVED16[26];
__I uint32_t RESERVED13[26];
__IO uint32_t ORC; /*!< Over-read character. */
__I uint32_t RESERVED17[654];
__I uint32_t RESERVED14[654];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_SPIM_Type;
@ -899,8 +865,8 @@ typedef struct { /*!< AAR Structure
__IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
__I uint32_t RESERVED5;
__IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
during resolution. A minimum of 3 bytes must be reserved. */
__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
resolution. A minimum of 3 bytes must be reserved. */
__I uint32_t RESERVED6[697];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_AAR_Type;
@ -938,8 +904,8 @@ typedef struct { /*!< CCM Structure
__IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
__IO uint32_t INPTR; /*!< Pointer to the input packet. */
__IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
during resolution. A minimum of 43 bytes must be reserved. */
__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
resolution. A minimum of 43 bytes must be reserved. */
__I uint32_t RESERVED5[697];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_CCM_Type;
@ -1087,9 +1053,13 @@ typedef struct { /*!< NVMC Structure
__I uint32_t READY; /*!< Ready flag. */
__I uint32_t RESERVED1[64];
__IO uint32_t CONFIG; /*!< Configuration register. */
__IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
union {
__IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
__IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
};
__IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
__IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
__IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
__IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
} NRF_NVMC_Type;
@ -1134,7 +1104,7 @@ typedef struct { /*!< FICR Structure
__I uint32_t PPFC; /*!< Pre-programmed factory code present. */
__I uint32_t RESERVED2;
__I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
union {
__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
kept for backward compatinility purposes. Use SIZERAMBLOCKS
@ -1155,7 +1125,6 @@ typedef struct { /*!< FICR Structure
__I uint32_t RESERVED5[10];
__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
mode. */
FICR_INFO_Type INFO; /*!< Device info */
} NRF_FICR_Type;
@ -1174,7 +1143,13 @@ typedef struct { /*!< UICR Structure
__IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
__I uint32_t RESERVED0;
__I uint32_t FWID; /*!< Firmware ID. */
__IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
union {
__IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
__IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
};
__IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
__IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
} NRF_UICR_Type;
@ -1226,7 +1201,6 @@ typedef struct { /*!< GPIO Structure
#define NRF_POWER_BASE 0x40000000UL
#define NRF_CLOCK_BASE 0x40000000UL
#define NRF_MPU_BASE 0x40000000UL
#define NRF_PU_BASE 0x40000000UL
#define NRF_AMLI_BASE 0x40000000UL
#define NRF_RADIO_BASE 0x40001000UL
#define NRF_UART0_BASE 0x40002000UL
@ -1266,7 +1240,6 @@ typedef struct { /*!< GPIO Structure
#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
@ -1300,7 +1273,7 @@ typedef struct { /*!< GPIO Structure
/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group nRF51 */
/** @} */ /* End of group nrf51 */
/** @} */ /* End of group Nordic Semiconductor */
#ifdef __cplusplus
@ -1308,5 +1281,5 @@ typedef struct { /*!< GPIO Structure
#endif
#endif /* nRF51_H */
#endif /* nrf51_H */

476
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_bitfields.h
View File

@ -1,38 +1,45 @@
/* Copyright (c) 2013, Nordic Semiconductor ASA
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __NRF51_BITS_H
#define __NRF51_BITS_H
/*lint ++flb "Enter library region */
#include <core_cm0.h>
/*lint ++flb "Enter library region" */
/* Peripheral: AAR */
/* Description: Accelerated Address Resolver. */
@ -820,6 +827,7 @@
#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
/* Peripheral: CCM */
/* Description: AES CCM Mode Encryption. */
@ -1064,8 +1072,8 @@
/* Bits 7..0 : External Xtal frequency selection. */
#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
/* Peripheral: ECB */
@ -1124,8 +1132,8 @@
/* Bits 7..0 : Pre-programmed factory code present. */
#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
/* Register: FICR_CONFIGID */
/* Description: Configuration identifier. */
@ -1162,60 +1170,6 @@
#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
/* Register: FICR_INFO_PART */
/* Description: Part code */
/* Bits 31..0 : Part code */
#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
#define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */
#define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */
#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_VARIANT */
/* Description: Part variant */
/* Bits 31..0 : Part variant */
#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */
#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */
#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */
#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_PACKAGE */
/* Description: Package option */
/* Bits 31..0 : Package option */
#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */
#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */
#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */
#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */
#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_RAM */
/* Description: RAM variant */
/* Bits 31..0 : RAM variant */
#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
#define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */
#define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */
/* Register: FICR_INFO_FLASH */
/* Description: Flash variant */
/* Bits 31..0 : Flash variant */
#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
#define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */
#define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */
/* Peripheral: GPIO */
/* Description: General purpose input and output. */
@ -2846,6 +2800,7 @@
/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */
#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
@ -3720,30 +3675,44 @@
/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */
#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */
/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */
#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */
/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */
#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */
/* Bit 3 : Reset from CPU lock-up detected. */
#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */
#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */
/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */
#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */
/* Bit 1 : Reset from watchdog detected. */
#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */
#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */
/* Bit 0 : Reset from pin-reset detected. */
#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */
#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */
/* Register: POWER_RAMSTATUS */
/* Description: Ram status register. */
@ -4636,186 +4605,6 @@
#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
/* Peripheral: PU */
/* Description: Patch unit. */
/* Register: PU_PATCHADDR */
/* Description: Relative address of patch instructions. */
/* Bits 24..0 : Relative address of patch instructions. */
#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
/* Register: PU_PATCHEN */
/* Description: Patch enable register. */
/* Bit 7 : Patch 7 enabled. */
#define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
#define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
/* Bit 6 : Patch 6 enabled. */
#define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
#define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
/* Bit 5 : Patch 5 enabled. */
#define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
#define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
/* Bit 4 : Patch 4 enabled. */
#define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
#define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
/* Bit 3 : Patch 3 enabled. */
#define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
#define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
/* Bit 2 : Patch 2 enabled. */
#define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
#define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
/* Bit 1 : Patch 1 enabled. */
#define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
#define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
/* Bit 0 : Patch 0 enabled. */
#define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
#define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
/* Register: PU_PATCHENSET */
/* Description: Patch enable register. */
/* Bit 7 : Patch 7 enabled. */
#define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
#define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
/* Bit 6 : Patch 6 enabled. */
#define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
#define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
/* Bit 5 : Patch 5 enabled. */
#define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
#define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
/* Bit 4 : Patch 4 enabled. */
#define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
#define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
/* Bit 3 : Patch 3 enabled. */
#define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
#define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
/* Bit 2 : Patch 2 enabled. */
#define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
#define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
/* Bit 1 : Patch 1 enabled. */
#define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
#define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
/* Bit 0 : Patch 0 enabled. */
#define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
#define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
/* Register: PU_PATCHENCLR */
/* Description: Patch disable register. */
/* Bit 7 : Patch 7 enabled. */
#define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
/* Bit 6 : Patch 6 enabled. */
#define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
/* Bit 5 : Patch 5 enabled. */
#define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
/* Bit 4 : Patch 4 enabled. */
#define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
/* Bit 3 : Patch 3 enabled. */
#define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
/* Bit 2 : Patch 2 enabled. */
#define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
/* Bit 1 : Patch 1 enabled. */
#define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
/* Bit 0 : Patch 0 enabled. */
#define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
#define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
/* Peripheral: QDEC */
/* Description: Rotary decoder. */
@ -5172,13 +4961,6 @@
#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
/* Register: RADIO_CD */
/* Description: Carrier detect. */
/* Bit 0 : Carrier detect. */
#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */
#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */
/* Register: RADIO_RXMATCH */
/* Description: Received address. */
@ -5213,14 +4995,14 @@
/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
/* Register: RADIO_MODE */
/* Description: Data rate and modulation. */
@ -6000,15 +5782,6 @@
/* Peripheral: SPIM */
/* Description: SPI master with easyDMA 1. */
/* Register: SPIM_SHORTS */
/* Description: Shortcuts for SPIM. */
/* Bit 17 : Shortcut between END event and START task. */
#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
/* Register: SPIM_INTENSET */
/* Description: Interrupt enable set register. */
@ -6026,13 +5799,6 @@
#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 6 : Enable interrupt on END event. */
#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 4 : Enable interrupt on ENDRX event. */
#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
@ -6064,13 +5830,6 @@
#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 6 : Disable interrupt on END event. */
#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 4 : Disable interrupt on ENDRX event. */
#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
@ -6094,20 +5853,6 @@
#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
/* Register: SPIM_RXDDATA */
/* Description: RXD register. */
/* Bits 7..0 : RX data received. Double buffered. */
#define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */
#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */
/* Register: SPIM_TXDDATA */
/* Description: TXD register. */
/* Bits 7..0 : TX data to send. Double buffered. */
#define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */
#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */
/* Register: SPIM_FREQUENCY */
/* Description: SPI frequency. */
@ -6122,43 +5867,6 @@
#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
/* Register: SPIM_CONFIG */
/* Description: Configuration register. */
/* Bit 2 : Serial clock (SCK) polarity. */
#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
/* Bit 1 : Serial clock (SCK) phase. */
#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
/* Bit 0 : Bit order. */
#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
/* Register: SPIM_ORC */
/* Description: Over-read character. */
/* Bits 7..0 : Over-read character. */
#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
/* Register: SPIM_POWER */
/* Description: Peripheral power control. */
/* Bit 0 : Peripheral power control. */
#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
/* Register: SPIM_RXD_PTR */
/* Description: Data pointer. */
@ -6201,6 +5909,43 @@
#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIM_CONFIG */
/* Description: Configuration register. */
/* Bit 2 : Serial clock (SCK) polarity. */
#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
/* Bit 1 : Serial clock (SCK) phase. */
#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
/* Bit 0 : Bit order. */
#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
/* Register: SPIM_ORC */
/* Description: Over-read character. */
/* Bits 7..0 : Over-read character. */
#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
/* Register: SPIM_POWER */
/* Description: Peripheral power control. */
/* Bit 0 : Peripheral power control. */
#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
/* Peripheral: SPIS */
/* Description: SPI slave 1. */
@ -6224,6 +5969,13 @@
#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 4 : enable interrupt on ENDRX event. */
#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 1 : Enable interrupt on END event. */
#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
@ -6241,6 +5993,13 @@
#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 4 : Disable interrupt on ENDRX event. */
#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 1 : Disable interrupt on END event. */
#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
@ -6669,6 +6428,13 @@
#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
/* Register: TWI_ENABLE */
/* Description: Enable two-wire master. */
@ -6725,13 +6491,13 @@
/* Register: UART_SHORTS */
/* Description: Shortcuts for UART. */
/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
/* Bit 3 : Shortcut between CTS event and STARTRX task. */
#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
@ -6901,7 +6667,7 @@
#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */
#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
/* Register: UART_CONFIG */
@ -6938,14 +6704,14 @@
/* Bits 15..8 : Readback protect all code in the device. */
#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
/* Register: UICR_XTALFREQ */
/* Description: Reset value for CLOCK XTALFREQ register. */
@ -6953,8 +6719,8 @@
/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
/* Register: UICR_FWID */
/* Description: Firmware ID. */

447
hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_deprecated.h Normal file
View File

@ -0,0 +1,447 @@
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF51_DEPRECATED_H
#define NRF51_DEPRECATED_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and
* nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
*/
/* NVMC */
/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
#define ERASEPROTECTEDPAGE ERASEPCR0
/* LPCOMP */
/* The interrupt ISR was renamed. Adding old name to the macros. */
#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler
#define LPCOMP_COMP_IRQn LPCOMP_IRQn
/* MPU */
/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos
#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk
#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1
#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0
/* POWER */
/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_OFFRAM3_Pos (19UL)
#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos)
#define POWER_RAMON_OFFRAM3_RAM3Off (0UL)
#define POWER_RAMON_OFFRAM3_RAM3On (1UL)
/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_OFFRAM2_Pos (18UL)
#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos)
#define POWER_RAMON_OFFRAM2_RAM2Off (0UL)
#define POWER_RAMON_OFFRAM2_RAM2On (1UL)
/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_ONRAM3_Pos (3UL)
#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos)
#define POWER_RAMON_ONRAM3_RAM3Off (0UL)
#define POWER_RAMON_ONRAM3_RAM3On (1UL)
/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_ONRAM2_Pos (2UL)
#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos)
#define POWER_RAMON_ONRAM2_RAM2Off (0UL)
#define POWER_RAMON_ONRAM2_RAM2On (1UL)
/* RADIO */
/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos
#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk
#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled
#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled
/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos
#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk
#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled
#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled
/* FICR */
/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
#define SIZERAMBLOCK0 SIZERAMBLOCKS
#define SIZERAMBLOCK1 SIZERAMBLOCKS
#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
#define DEVICEID0 DEVICEID[0]
#define DEVICEID1 DEVICEID[1]
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
#define ER0 ER[0]
#define ER1 ER[1]
#define ER2 ER[2]
#define ER3 ER[3]
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
#define IR0 IR[0]
#define IR1 IR[1]
#define IR2 IR[2]
#define IR3 IR[3]
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
#define DEVICEADDR0 DEVICEADDR[0]
#define DEVICEADDR1 DEVICEADDR[1]
/* PPI */
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
#define TASKS_CHG0EN TASKS_CHG[0].EN
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
#define TASKS_CHG1EN TASKS_CHG[1].EN
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
#define TASKS_CHG2EN TASKS_CHG[2].EN
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
#define TASKS_CHG3EN TASKS_CHG[3].EN
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
#define CH0_EEP CH[0].EEP
#define CH0_TEP CH[0].TEP
#define CH1_EEP CH[1].EEP
#define CH1_TEP CH[1].TEP
#define CH2_EEP CH[2].EEP
#define CH2_TEP CH[2].TEP
#define CH3_EEP CH[3].EEP
#define CH3_TEP CH[3].TEP
#define CH4_EEP CH[4].EEP
#define CH4_TEP CH[4].TEP
#define CH5_EEP CH[5].EEP
#define CH5_TEP CH[5].TEP
#define CH6_EEP CH[6].EEP
#define CH6_TEP CH[6].TEP
#define CH7_EEP CH[7].EEP
#define CH7_TEP CH[7].TEP
#define CH8_EEP CH[8].EEP
#define CH8_TEP CH[8].TEP
#define CH9_EEP CH[9].EEP
#define CH9_TEP CH[9].TEP
#define CH10_EEP CH[10].EEP
#define CH10_TEP CH[10].TEP
#define CH11_EEP CH[11].EEP
#define CH11_TEP CH[11].TEP
#define CH12_EEP CH[12].EEP
#define CH12_TEP CH[12].TEP
#define CH13_EEP CH[13].EEP
#define CH13_TEP CH[13].TEP
#define CH14_EEP CH[14].EEP
#define CH14_TEP CH[14].TEP
#define CH15_EEP CH[15].EEP
#define CH15_TEP CH[15].TEP
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
#define CHG0 CHG[0]
#define CHG1 CHG[1]
#define CHG2 CHG[2]
#define CHG3 CHG[3]
/* All bitfield macros for the CHGx registers therefore changed name. */
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
/*lint --flb "Leave library region" */
#endif /* NRF51_DEPRECATED_H */

34
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/nrf51_to_nrf52.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_to_nrf52.h
View File

@ -1,22 +1,28 @@
/*
* Copyright (c) Nordic Semiconductor ASA
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific prior written permission.
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -27,9 +33,10 @@
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
#ifndef NRF51_TO_NRF52_H
#define NRF51_TO_NRF52_H
@ -934,3 +941,4 @@
/*lint --flb "Leave library region" */
#endif /* NRF51_TO_NRF52_H */

49
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/nrf52.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52.h
View File

@ -1,35 +1,3 @@
/*
* Copyright (c) Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/****************************************************************************************************//**
* @file nrf52.h
@ -40,26 +8,26 @@
* @version V1
* @date 23. February 2016
*
* @note Generated with SVDConv V2.81d
* @note Generated with SVDConv V2.81d
* from CMSIS SVD File 'nrf52.svd' Version 1,
*
* @par Copyright (c) 2015, Nordic Semiconductor ASA
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -70,7 +38,7 @@
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*
*******************************************************************************************************/
@ -1822,7 +1790,7 @@ typedef struct { /*!< NVMC Structure
__I uint32_t READY; /*!< Ready flag */
__I uint32_t RESERVED1[64];
__IO uint32_t CONFIG; /*!< Configuration register */
union {
__IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area.
Equivalent to ERASEPAGE. */
@ -2154,3 +2122,4 @@ typedef struct { /*!< GPIO Structure
#endif /* nrf52_H */

33
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/nrf52_bitfields.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_bitfields.h
View File

@ -1,22 +1,28 @@
/*
* Copyright (c) Nordic Semiconductor ASA
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific prior written permission.
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -27,8 +33,9 @@
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
#ifndef __NRF52_BITS_H
#define __NRF52_BITS_H

36
hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF52832/nrf52_name_change.h → hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_name_change.h
View File

@ -1,22 +1,28 @@
/*
* Copyright (c) Nordic Semiconductor ASA
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific prior written permission.
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ -27,15 +33,16 @@
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
#ifndef NRF52_NAME_CHANGE_H
#define NRF52_NAME_CHANGE_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and
/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and
* nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
*/
@ -69,3 +76,4 @@
/*lint --flb "Leave library region" */
#endif /* NRF52_NAME_CHANGE_H */

51
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h
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@ -1,51 +0,0 @@
/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup crc_compute CRC compute
* @{
* @ingroup hci_transport
*
* @brief This module implements the CRC-16 calculation in the blocks.
*/
#ifndef CRC16_H__
#define CRC16_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**@brief Function for calculating CRC-16 in blocks.
*
* Feed each consecutive data block into this function, along with the current value of p_crc as
* returned by the previous call of this function. The first call of this function should pass NULL
* as the initial value of the crc in p_crc.
*
* @param[in] p_data The input data block for computation.
* @param[in] size The size of the input data block in bytes.
* @param[in] p_crc The previous calculated CRC-16 value or NULL if first call.
*
* @return The updated CRC-16 value, based on the input supplied.
*/
uint16_t crc16_compute(const uint8_t * p_data, uint32_t size, const uint16_t * p_crc);
#ifdef __cplusplus
}
#endif
#endif // CRC16_H__
/** @} */

92
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h
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@ -1,92 +0,0 @@
/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup app_error Common application error handler
* @{
* @ingroup app_common
*
* @brief Common application error handler and macros for utilizing a common error handler.
*/
#ifndef APP_ERROR_H__
#define APP_ERROR_H__
#include <stdint.h>
#include <stdbool.h>
#include "nrf_error.h"
#ifdef __cplusplus
extern "C" {
#endif
/**@brief Function for error handling, which is called when an error has occurred.
*
* @param[in] error_code Error code supplied to the handler.
* @param[in] line_num Line number where the handler is called.
* @param[in] p_file_name Pointer to the file name.
*/
void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
#ifdef __cplusplus
}
#endif
/**@brief Macro for calling error handler function.
*
* @param[in] ERR_CODE Error code supplied to the error handler.
*/
#ifdef DEBUG
#define APP_ERROR_HANDLER(ERR_CODE) \
do \
{ \
app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); \
} while (0)
#else
#define APP_ERROR_HANDLER(ERR_CODE) \
do \
{ \
app_error_handler((ERR_CODE), 0, 0); \
} while (0)
#endif
/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS.
*
* @param[in] ERR_CODE Error code supplied to the error handler.
*/
#define APP_ERROR_CHECK(ERR_CODE) \
do \
{ \
const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \
if (LOCAL_ERR_CODE != NRF_SUCCESS) \
{ \
APP_ERROR_HANDLER(LOCAL_ERR_CODE); \
} \
} while (0)
/**@brief Macro for calling error handler function if supplied boolean value is false.
*
* @param[in] BOOLEAN_VALUE Boolean value to be evaluated.
*/
#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \
do \
{ \
const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \
if (!LOCAL_BOOLEAN_VALUE) \
{ \
APP_ERROR_HANDLER(0); \
} \
} while (0)
#endif // APP_ERROR_H__
/** @} */

234
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h
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@ -1,234 +0,0 @@
/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
/** @file
*
* @defgroup app_util Utility Functions and Definitions
* @{
* @ingroup app_common
*
* @brief Various types and definitions available to all applications.
*/
#ifndef APP_UTIL_H__
#define APP_UTIL_H__
#include <stdint.h>
#include <stdbool.h>
#include "compiler_abstraction.h"
enum
{
UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */
UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */
UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */
};
/**@brief Macro for doing static (i.e. compile time) assertion.
*
* @note If the assertion fails when compiling using Keil, the compiler will report error message
* "error: #94: the size of an array must be greater than zero" (while gcc will list the
* symbol static_assert_failed, making the error message more readable).
* If the supplied expression can not be evaluated at compile time, Keil will report
* "error: #28: expression must have a constant value".
*
* @note The macro is intentionally implemented not using do while(0), allowing it to be used
* outside function blocks (e.g. close to global type- and variable declarations).
* If used in a code block, it must be used before any executable code in this block.
*
* @param[in] EXPR Constant expression to be verified.
*/
#if defined(__GNUC__)
#define STATIC_ASSERT(EXPR) typedef char __attribute__((unused)) static_assert_failed[(EXPR) ? 1 : -1]
#elif defined(__ICCARM__)
#define STATIC_ASSERT(EXPR) extern char static_assert_failed[(EXPR) ? 1 : -1]
#else
#define STATIC_ASSERT(EXPR) typedef char static_assert_failed[(EXPR) ? 1 : -1]
#endif
/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */
typedef uint8_t uint16_le_t[2];
/**@brief type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */
typedef uint8_t uint32_le_t[4];
/**@brief Byte array type. */
typedef struct
{
uint16_t size; /**< Number of array entries. */
uint8_t * p_data; /**< Pointer to array entries. */
} uint8_array_t;
/**@brief Perform rounded integer division (as opposed to truncating the result).
*
* @param[in] A Numerator.
* @param[in] B Denominator.
*
* @return Rounded (integer) result of dividing A by B.
*/
#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B))
/**@brief Check if the integer provided is a power of two.
*
* @param[in] A Number to be tested.
*
* @return true if value is power of two.
* @return false if value not power of two.
*/
#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) )
/**@brief To convert milliseconds to ticks.
* @param[in] TIME Number of milliseconds to convert.
* @param[in] RESOLUTION Unit to be converted to in [us/ticks].
*/
#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION))
/**@brief Perform integer division, making sure the result is rounded up.
*
* @details One typical use for this is to compute the number of objects with size B is needed to
* hold A number of bytes.
*
* @param[in] A Numerator.
* @param[in] B Denominator.
*
* @return Integer result of dividing A by B, rounded up.
*/
#define CEIL_DIV(A, B) \
/*lint -save -e573 */ \
((((A) - 1) / (B)) + 1) \
/*lint -restore */
/**@brief Function for encoding a uint16 value.
*
* @param[in] value Value to be encoded.
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
*
* @return Number of bytes written.
*/
static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data)
{
p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0);
p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8);
return sizeof(uint16_t);
}
/**@brief Function for encoding a uint32 value.
*
* @param[in] value Value to be encoded.
* @param[out] p_encoded_data Buffer where the encoded data is to be written.
*
* @return Number of bytes written.
*/
static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data)
{
p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0);
p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8);
p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16);
p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24);
return sizeof(uint32_t);
}
/**@brief Function for decoding a uint16 value.
*
* @param[in] p_encoded_data Buffer where the encoded data is stored.
*
* @return Decoded value.
*/
static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data)
{
return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) |
(((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 ));
}
/**@brief Function for decoding a uint32 value.
*
* @param[in] p_encoded_data Buffer where the encoded data is stored.
*
* @return Decoded value.
*/
static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data)
{
return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) |
(((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) |
(((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
(((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 ));
}
/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts.
*
* @details The calculation is based on a linearized version of the battery's discharge
* curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and
* is considered to be the lower boundary.
*
* The discharge curve for CR2032 is non-linear. In this model it is split into
* 4 linear sections:
* - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV)
* - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV)
* - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV)
* - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV)
*
* These numbers are by no means accurate. Temperature and
* load in the actual application is not accounted for!
*
* @param[in] mvolts The voltage in mV
*
* @return Battery level in percent.
*/
static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts)
{
uint8_t battery_level;
if (mvolts >= 3000)
{
battery_level = 100;
}
else if (mvolts > 2900)
{
battery_level = 100 - ((3000 - mvolts) * 58) / 100;
}
else if (mvolts > 2740)
{
battery_level = 42 - ((2900 - mvolts) * 24) / 160;
}
else if (mvolts > 2440)
{
battery_level = 18 - ((2740 - mvolts) * 12) / 300;
}
else if (mvolts > 2100)
{
battery_level = 6 - ((2440 - mvolts) * 6) / 340;
}
else
{
battery_level = 0;
}
return battery_level;
}
/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary.
*
* @param[in] p Pointer value to be checked.
*
* @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise.
*/
static __INLINE bool is_word_aligned(void * p)
{
return (((uintptr_t)p & 0x03) == 0);
}
#endif // APP_UTIL_H__
/** @} */

90
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_licence_agreement.txt
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@ -1,90 +0,0 @@
S110/S120/S130 license agreement
NORDIC SEMICONDUCTOR ASA SOFTDEVICE LICENSE AGREEMENT
License Agreement for the Nordic Semiconductor ASA ("Nordic") S110, S120 and S130 Bluetooth SoftDevice software packages ("SoftDevice").
You ("You" "Licensee") must carefully and thoroughly read this License Agreement ("Agreement"), and accept to adhere to this Agreement before
downloading, installing and/or using any software or content in the SoftDevice provided herewith.
YOU ACCEPT THIS LICENSE AGREEMENT BY (A) CLICKING ACCEPT OR AGREE TO THIS LICENSE AGREEMENT, WHERE THIS
OPTION IS MADE AVAILABLE TO YOU; OR (B) BY ACTUALLY USING THE SOFTDEVICE, IN THIS CASE YOU AGREE THAT THE USE OF
THE SOFTDEVICE CONSTITUTES ACCEPTANCE OF THE LICENSING AGREEMENT FROM THAT POINT ONWARDS.
IF YOU DO NOT AGREE TO BE BOUND BY THE TERMS OF THIS AGREEMENT, THEN DO NOT DOWNLOAD, INSTALL/COMPLETE
INSTALLATION OF, OR IN ANY OTHER WAY MAKE USE OF THE SOFTDEVICE.
1. Grant of License
Subject to the terms in this Agreement Nordic grants Licensee a limited, non-exclusive, non-transferable, non-sub licensable, revocable license
("License"): (a) to use the SoftDevice solely in connection with a Nordic integrated circuit, and (b) to distribute the SoftDevice solely as integrated
in Licensee Product. Licensee shall not use the SoftDevice for any purpose other than specifically authorized herein. It is a material breach of this
agreement to use or modify the SoftDevice for use on any wireless connectivity integrated circuit other than a Nordic integrated circuit.
2. Title
Nordic retains full rights, title, and ownership to the SoftDevice and any and all patents, copyrights, trade secrets, trade names, trademarks, and
other intellectual property rights in and to the SoftDevice.
3. No Modifications or Reverse Engineering
Licensee shall not, modify, reverse engineer, disassemble, decompile or otherwise attempt to discover the source code of any non-source code
parts of the SoftDevice including, but not limited to pre-compiled hex files, binaries and object code.
4. Distribution Restrictions
Except as set forward in Section 1 above, the Licensee may not disclose or distribute any or all parts of the SoftDevice to any third party.
Licensee agrees to provide reasonable security precautions to prevent unauthorized access to or use of the SoftDevice as proscribed herein.
Licensee also agrees that use of and access to the SoftDevice will be strictly limited to the employees and subcontractors of the Licensee
necessary for the performance of development, verification and production tasks under this Agreement. The Licensee is responsible for making
such employees and subcontractors comply with the obligations concerning use and non-disclosure of the SoftDevice.
5. No Other Rights
Licensee shall use the SoftDevice only in compliance with this Agreement and shall refrain from using the SoftDevice in any way that may be
contrary to this Agreement.
6. Fees
Nordic grants the License to the Licensee free of charge provided that the Licensee undertakes the obligations in the Agreement and warrants to
comply with the Agreement.
7. DISCLAIMER OF WARRANTY
THE SOFTDEVICE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND EXPRESS OR IMPLIED AND NEITHER NORDIC, ITS
LICENSORS OR AFFILIATES NOR THE COPYRIGHT HOLDERS MAKE ANY REPRESENTATIONS OR WARRANTIES, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR
THAT THE SOFTDEVICE WILL NOT INFRINGE ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS. THERE
IS NO WARRANTY BY NORDIC OR BY ANY OTHER PARTY THAT THE FUNCTIONS CONTAINED IN THE SOFTDEVICE WILL MEET THE
REQUIREMENTS OF LICENSEE OR THAT THE OPERATION OF THE SOFTDEVICE WILL BE UNINTERRUPTED OR ERROR-FREE.
LICENSEE ASSUMES ALL RESPONSIBILITY AND RISK FOR THE SELECTION OF THE SOFTDEVICE TO ACHIEVE LICENSEE’S
INTENDED RESULTS AND FOR THE INSTALLATION, USE AND RESULTS OBTAINED FROM IT.
8. No Support
Nordic is not obligated to furnish or make available to Licensee any further information, software, technical information, know-how, show-how,
bug-fixes or support. Nordic reserves the right to make changes to the SoftDevice without further notice.
9. Limitation of Liability
In no event shall Nordic, its employees or suppliers, licensors or affiliates be liable for any lost profits, revenue, sales, data or costs of
procurement of substitute goods or services, property damage, personal injury, interruption of business, loss of business information or for any
special, direct, indirect, incidental, economic, punitive, special or consequential damages, however caused and whether arising under contract,
tort, negligence, or other theory of liability arising out of the use of or inability to use the SoftDevice, even if Nordic or its employees or suppliers,
licensors or affiliates are advised of the possibility of such damages. Because some countries/states/jurisdictions do not allow the exclusion or
limitation of liability, but may allow liability to be limited, in such cases, Nordic, its employees or licensors or affiliates’ liability shall be limited to
USD 50.
10. Breach of Contract
Upon a breach of contract by the Licensee, Nordic and its licensor are entitled to damages in respect of any direct loss which can be reasonably
attributed to the breach by the Licensee. If the Licensee has acted with gross negligence or willful misconduct, the Licensee shall cover both
direct and indirect costs for Nordic and its licensors.
11. Indemnity
Licensee undertakes to indemnify, hold harmless and defend Nordic and its directors, officers, affiliates, shareholders, licensors, employees and
agents from and against any claims or lawsuits, including attorney's fees, that arise or result of the Licensee’s execution of the License and which
is not due to causes for which Nordic is responsible.
12. Governing Law
This Agreement shall be construed according to the laws of Norway, and hereby submits to the exclusive jurisdiction of the Oslo tingrett.
13. Assignment
Licensee shall not assign this Agreement or any rights or obligations hereunder without the prior written consent of Nordic.
14. Termination
Without prejudice to any other rights, Nordic may cancel this Agreement if Licensee does not abide by the terms and conditions of this
Agreement. Upon termination Licensee must promptly cease the use of the License and destroy all copies of the Licensed Technology and any
other material provided by Nordic or its affiliate, or produced by the Licensee in connection with the Agreement or the Licensed Technology.
15. Third party beneficiaries
Nordic’s licensors are intended third party beneficiaries under this Agreement.

5649
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_softdevice.hex
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90
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_licence_agreement.txt
View File

@ -1,90 +0,0 @@
S110/S120/S130 license agreement
NORDIC SEMICONDUCTOR ASA SOFTDEVICE LICENSE AGREEMENT
License Agreement for the Nordic Semiconductor ASA ("Nordic") S110, S120 and S130 Bluetooth SoftDevice software packages ("SoftDevice").
You ("You" "Licensee") must carefully and thoroughly read this License Agreement ("Agreement"), and accept to adhere to this Agreement before
downloading, installing and/or using any software or content in the SoftDevice provided herewith.
YOU ACCEPT THIS LICENSE AGREEMENT BY (A) CLICKING ACCEPT OR AGREE TO THIS LICENSE AGREEMENT, WHERE THIS
OPTION IS MADE AVAILABLE TO YOU; OR (B) BY ACTUALLY USING THE SOFTDEVICE, IN THIS CASE YOU AGREE THAT THE USE OF
THE SOFTDEVICE CONSTITUTES ACCEPTANCE OF THE LICENSING AGREEMENT FROM THAT POINT ONWARDS.
IF YOU DO NOT AGREE TO BE BOUND BY THE TERMS OF THIS AGREEMENT, THEN DO NOT DOWNLOAD, INSTALL/COMPLETE
INSTALLATION OF, OR IN ANY OTHER WAY MAKE USE OF THE SOFTDEVICE.
1. Grant of License
Subject to the terms in this Agreement Nordic grants Licensee a limited, non-exclusive, non-transferable, non-sub licensable, revocable license
("License"): (a) to use the SoftDevice solely in connection with a Nordic integrated circuit, and (b) to distribute the SoftDevice solely as integrated
in Licensee Product. Licensee shall not use the SoftDevice for any purpose other than specifically authorized herein. It is a material breach of this
agreement to use or modify the SoftDevice for use on any wireless connectivity integrated circuit other than a Nordic integrated circuit.
2. Title
Nordic retains full rights, title, and ownership to the SoftDevice and any and all patents, copyrights, trade secrets, trade names, trademarks, and
other intellectual property rights in and to the SoftDevice.
3. No Modifications or Reverse Engineering
Licensee shall not, modify, reverse engineer, disassemble, decompile or otherwise attempt to discover the source code of any non-source code
parts of the SoftDevice including, but not limited to pre-compiled hex files, binaries and object code.
4. Distribution Restrictions
Except as set forward in Section 1 above, the Licensee may not disclose or distribute any or all parts of the SoftDevice to any third party.
Licensee agrees to provide reasonable security precautions to prevent unauthorized access to or use of the SoftDevice as proscribed herein.
Licensee also agrees that use of and access to the SoftDevice will be strictly limited to the employees and subcontractors of the Licensee
necessary for the performance of development, verification and production tasks under this Agreement. The Licensee is responsible for making
such employees and subcontractors comply with the obligations concerning use and non-disclosure of the SoftDevice.
5. No Other Rights
Licensee shall use the SoftDevice only in compliance with this Agreement and shall refrain from using the SoftDevice in any way that may be
contrary to this Agreement.
6. Fees
Nordic grants the License to the Licensee free of charge provided that the Licensee undertakes the obligations in the Agreement and warrants to
comply with the Agreement.
7. DISCLAIMER OF WARRANTY
THE SOFTDEVICE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND EXPRESS OR IMPLIED AND NEITHER NORDIC, ITS
LICENSORS OR AFFILIATES NOR THE COPYRIGHT HOLDERS MAKE ANY REPRESENTATIONS OR WARRANTIES, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR
THAT THE SOFTDEVICE WILL NOT INFRINGE ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS. THERE
IS NO WARRANTY BY NORDIC OR BY ANY OTHER PARTY THAT THE FUNCTIONS CONTAINED IN THE SOFTDEVICE WILL MEET THE
REQUIREMENTS OF LICENSEE OR THAT THE OPERATION OF THE SOFTDEVICE WILL BE UNINTERRUPTED OR ERROR-FREE.
LICENSEE ASSUMES ALL RESPONSIBILITY AND RISK FOR THE SELECTION OF THE SOFTDEVICE TO ACHIEVE LICENSEE’S
INTENDED RESULTS AND FOR THE INSTALLATION, USE AND RESULTS OBTAINED FROM IT.
8. No Support
Nordic is not obligated to furnish or make available to Licensee any further information, software, technical information, know-how, show-how,
bug-fixes or support. Nordic reserves the right to make changes to the SoftDevice without further notice.
9. Limitation of Liability
In no event shall Nordic, its employees or suppliers, licensors or affiliates be liable for any lost profits, revenue, sales, data or costs of
procurement of substitute goods or services, property damage, personal injury, interruption of business, loss of business information or for any
special, direct, indirect, incidental, economic, punitive, special or consequential damages, however caused and whether arising under contract,
tort, negligence, or other theory of liability arising out of the use of or inability to use the SoftDevice, even if Nordic or its employees or suppliers,
licensors or affiliates are advised of the possibility of such damages. Because some countries/states/jurisdictions do not allow the exclusion or
limitation of liability, but may allow liability to be limited, in such cases, Nordic, its employees or licensors or affiliates’ liability shall be limited to
USD 50.
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Upon a breach of contract by the Licensee, Nordic and its licensor are entitled to damages in respect of any direct loss which can be reasonably
attributed to the breach by the Licensee. If the Licensee has acted with gross negligence or willful misconduct, the Licensee shall cover both
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15. Third party beneficiaries
Nordic’s licensors are intended third party beneficiaries under this Agreement.

6861
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_softdevice.hex
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58
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/PeripheralNames.h
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@ -1,58 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STDIO_UART_TX TX_PIN_NUMBER
#define STDIO_UART_RX RX_PIN_NUMBER
#define STDIO_UART UART_0
typedef enum {
UART_0 = (int)NRF_UART0_BASE
} UARTName;
typedef enum {
SPI_0 = (int)NRF_SPI0_BASE,
SPI_1 = (int)NRF_SPI1_BASE,
SPIS = (int)NRF_SPIS1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2
} PWMName;
typedef enum {
I2C_0 = (int)NRF_TWI0_BASE,
I2C_1 = (int)NRF_TWI1_BASE
} I2CName;
typedef enum {
ADC0_0 = (int)NRF_ADC_BASE
} ADCName;
#ifdef __cplusplus
}
#endif
#endif

30
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/PortNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0 //GPIO pins 0-31
} PortName;
#ifdef __cplusplus
}
#endif
#endif

130
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2015 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
NC = (int)0xFFFFFFFF,
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
LED1 = p4,
LED2 = p5,
LED3 = p6,
LED4 = p13,
BUTTON0 = p16,
BUTTON1 = p17,
RX_PIN_NUMBER = p23,
TX_PIN_NUMBER = p25,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
SPI_PSELMOSI0 = p24,
SPI_PSELMISO0 = p29,
SPI_PSELSS0 = p30,
SPI_PSELSCK0 = p21,
SPIS_PSELMOSI = p24,
SPIS_PSELMISO = p29,
SPIS_PSELSS = p30,
SPIS_PSELSCK = p21,
I2C_SDA0 = p22,
I2C_SCL0 = p20,
A0 = p26,
A1 = p27,
A2 = p4,
A3 = p5,
A4 = p6,
SWIO = p19,
VERF0 = p0,
// SPI for controlling internal flash, don't use it.
FLASH_SPIMOSI = 15,
FLASH_SPIMISO = 9,
FLASH_SPICS = 28,
FLASH_SPICLK = 11,
// Not connected
CTS_PIN_NUMBER= NC,
RTS_PIN_NUMBER= NC,
SPI_PSELMOSI1 = NC,
SPI_PSELMISO1 = NC,
SPI_PSELSS1 = NC,
SPI_PSELSCK1 = NC,
A5 = NC
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

106
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p5 = 5,
p8 = 8,
p9 = 9,
p11 = 11,
p12 = 12,
p15 = 15,
p16 = 16,
p18 = 18,
p20 = 20,
p21 = 21,
p24 = 24,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_5 = p5,
P0_8 = p8,
P0_9 = p9,
P0_11 = p11,
P0_12 = p12,
P0_15 = p15,
P0_16 = p16,
P0_18 = p18,
P0_20 = p20,
P0_21 = p21,
P0_24 = p24,
LED1 = p16,
LED2 = p12,
LED3 = p15,
LEDR = LED1,
LEDG = LED2,
LEDB = LED3,
BUTTON1 = p8,
BUTTON2 = p18,
RX_PIN_NUMBER = p21,
TX_PIN_NUMBER = p24,
CTS_PIN_NUMBER = p0,
RTS_PIN_NUMBER = p20,
SPI_PSELMOSI0 = p2,
SPI_PSELMISO0 = p5,
SPI_PSELSS0 = p1,
SPI_PSELSCK0 = p3,
I2C_SDA0 = p9,
I2C_SCL0 = p11,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

150
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_Y5_MBUG/PinNames.h
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@ -1,150 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
p32 = 32,
p33 = 33,
p34 = 34,
p35 = 35,
// p31=31,
// Not connected
NC = (int)0xFFFFFFFF,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
LED = p30,
LED1 = p30,
LED2 = p0,
LED3 = p8,
LED4 = NC,
BUTTON1 = p29,
BUTTON2 = p17,
RX_PIN_NUMBER = p2,
TX_PIN_NUMBER = p3,
CTS_PIN_NUMBER = p11,
RTS_PIN_NUMBER = p21,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
SPIS_PSELMOSI = p12,
SPIS_PSELMISO = p6,
SPIS_PSELSCK = p9,
I2C_SDA0 = p17,
I2C_SCL0 = p18,
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

145
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DONGLE/PinNames.h
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@ -1,145 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p28 = 28,
p29 = 29,
p30 = 30,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_28 = p28,
P0_29 = p29,
LED1 = p21,
LED2 = p22,
LED3 = p23,
LED4 = p23,
LEDR = LED1,
LEDG = LED2,
LEDB = LED3,
RX_PIN_NUMBER = p11,
TX_PIN_NUMBER = p9,
CTS_PIN_NUMBER = p10,
RTS_PIN_NUMBER = p8,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
SPI_PSELMOSI0 = p15,
SPI_PSELMISO0 = p16,
SPI_PSELSS0 = p17,
SPI_PSELSCK0 = p18,
SPI_PSELMOSI1 = p15,
SPI_PSELMISO1 = p16,
SPI_PSELSS1 = p17,
SPI_PSELSCK1 = p18,
SPIS_PSELMOSI = p15,
SPIS_PSELMISO = p16,
SPIS_PSELSS = p17,
SPIS_PSELSCK = p18,
I2C_SDA0 = p19,
I2C_SCL0 = p20,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

143
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_SEEED_TINY_BLE/PinNames.h
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@ -1,143 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
// p31=31,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
LED1 = p21,
LED2 = p22,
LED3 = p23,
LED4 = p24,
BUTTON1 = p17,
BUTTON = BUTTON1,
RX_PIN_NUMBER = p11,
TX_PIN_NUMBER = p9,
CTS_PIN_NUMBER = p10,
RTS_PIN_NUMBER = p8,
// mbed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
I2C_SDA0 = p18,
I2C_SCL0 = p19,
MPU6050_SDA_PIN = p18,
MPU6050_SCL_PIN = p19,
MPU6050_INT_PIN = p20,
BATTERY_PIN = p1,
VCC_CTRL_PIN = p30,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

58
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_api.c
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@ -1,58 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "gpio_api.h"
#include "pinmap.h"
void gpio_init(gpio_t *obj, PinName pin)
{
obj->pin = pin;
if (pin == (PinName)NC) {
return;
}
obj->mask = (1ul << pin);
obj->reg_set = &NRF_GPIO->OUTSET;
obj->reg_clr = &NRF_GPIO->OUTCLR;
obj->reg_in = &NRF_GPIO->IN;
obj->reg_dir = &NRF_GPIO->DIR;
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
{
MBED_ASSERT(obj->pin != (PinName)NC);
switch (direction) {
case PIN_INPUT:
NRF_GPIO->PIN_CNF[obj->pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
break;
case PIN_OUTPUT:
NRF_GPIO->PIN_CNF[obj->pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
break;
}
}

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hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_irq_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "mbed_error.h"
#define CHANNEL_NUM 31
static uint32_t channel_ids[CHANNEL_NUM] = {0}; //each pin will be given an id, if id is 0 the pin can be ignored.
static uint8_t channel_enabled[CHANNEL_NUM] = {0};
static uint32_t portRISE = 0;
static uint32_t portFALL = 0;
static gpio_irq_handler irq_handler;
#ifdef __cplusplus
extern "C" {
#endif
void GPIOTE_IRQHandler(void)
{
volatile uint32_t newVal = NRF_GPIO->IN;
if ((NRF_GPIOTE->EVENTS_PORT != 0) && ((NRF_GPIOTE->INTENSET & GPIOTE_INTENSET_PORT_Msk) != 0)) {
NRF_GPIOTE->EVENTS_PORT = 0;
for (uint8_t i = 0; i<31; i++) {
if (channel_ids[i]>0) {
if (channel_enabled[i]) {
if( ((newVal>>i)&1) && ( ( (NRF_GPIO->PIN_CNF[i] >>GPIO_PIN_CNF_SENSE_Pos) & GPIO_PIN_CNF_SENSE_Low) != GPIO_PIN_CNF_SENSE_Low) && ( (portRISE>>i)&1) ){
irq_handler(channel_ids[i], IRQ_RISE);
} else if ((((newVal >> i) & 1) == 0) &&
(((NRF_GPIO->PIN_CNF[i] >> GPIO_PIN_CNF_SENSE_Pos) & GPIO_PIN_CNF_SENSE_Low) == GPIO_PIN_CNF_SENSE_Low) &&
((portFALL >> i) & 1)) {
irq_handler(channel_ids[i], IRQ_FALL);
}
}
if (NRF_GPIO->PIN_CNF[i] & GPIO_PIN_CNF_SENSE_Msk) {
NRF_GPIO->PIN_CNF[i] &= ~(GPIO_PIN_CNF_SENSE_Msk);
if (newVal >> i & 1) {
NRF_GPIO->PIN_CNF[i] |= (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos);
} else {
NRF_GPIO->PIN_CNF[i] |= (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos);
}
}
}
}
}
}
#ifdef __cplusplus
}
#endif
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
if (pin == NC) {
return -1;
}
irq_handler = handler;
obj->ch = pin;
NRF_GPIOTE->EVENTS_PORT = 0;
channel_ids[pin] = id;
channel_enabled[pin] = 1;
NRF_GPIOTE->INTENSET = GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos;
NVIC_SetPriority(GPIOTE_IRQn, 3);
NVIC_EnableIRQ (GPIOTE_IRQn);
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
channel_ids[obj->ch] = 0;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
NRF_GPIO->PIN_CNF[obj->ch] &= ~(GPIO_PIN_CNF_SENSE_Msk);
if (enable) {
if (event == IRQ_RISE) {
portRISE |= (1 << obj->ch);
} else if (event == IRQ_FALL) {
portFALL |= (1 << obj->ch);
}
} else {
if (event == IRQ_RISE) {
portRISE &= ~(1 << obj->ch);
} else if (event == IRQ_FALL) {
portFALL &= ~(1 << obj->ch);
}
}
if (((portRISE >> obj->ch) & 1) || ((portFALL >> obj->ch) & 1)) {
if ((NRF_GPIO->IN >> obj->ch) & 1) {
NRF_GPIO->PIN_CNF[obj->ch] |= (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos); // | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos);
} else {
NRF_GPIO->PIN_CNF[obj->ch] |= (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos); //| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos);
}
}
}
void gpio_irq_enable(gpio_irq_t *obj)
{
channel_enabled[obj->ch] = 1;
}
void gpio_irq_disable(gpio_irq_t *obj)
{
channel_enabled[obj->ch] = 0;
}

56
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h
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@ -1,56 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_set;
__IO uint32_t *reg_clr;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
MBED_ASSERT(obj->pin != (PinName)NC);
if (value)
*obj->reg_set = obj->mask;
else
*obj->reg_clr = obj->mask;
}
static inline int gpio_read(gpio_t *obj) {
MBED_ASSERT(obj->pin != (PinName)NC);
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
static inline int gpio_is_connected(const gpio_t *obj) {
return obj->pin != (PinName)NC;
}
#ifdef __cplusplus
}
#endif
#endif

309
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c
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@ -1,309 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "i2c_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "twi_master.h"
#include "mbed_error.h"
// nRF51822's I2C_0 and SPI_0 (I2C_1, SPI_1 and SPIS1) share the same address.
// They can't be used at the same time. So we use two global variable to track the usage.
// See nRF51822 address information at nRF51822_PS v2.0.pdf - Table 15 Peripheral instance reference
volatile i2c_spi_peripheral_t i2c0_spi0_peripheral = {0, 0, 0, 0};
volatile i2c_spi_peripheral_t i2c1_spi1_peripheral = {0, 0, 0, 0};
void i2c_interface_enable(i2c_t *obj)
{
obj->i2c->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
}
void twi_master_init(i2c_t *obj, PinName sda, PinName scl, int frequency)
{
NRF_GPIO->PIN_CNF[scl] = ((GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) |
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
(GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) |
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos));
NRF_GPIO->PIN_CNF[sda] = ((GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) |
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
(GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) |
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos));
obj->i2c->PSELSCL = scl;
obj->i2c->PSELSDA = sda;
// set default frequency at 100k
i2c_frequency(obj, frequency);
i2c_interface_enable(obj);
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
NRF_TWI_Type *i2c = NULL;
if (i2c0_spi0_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_I2C &&
i2c0_spi0_peripheral.sda_mosi == (uint8_t)sda &&
i2c0_spi0_peripheral.scl_miso == (uint8_t)scl) {
// The I2C with the same pins is already initialized
i2c = (NRF_TWI_Type *)I2C_0;
obj->peripheral = 0x1;
} else if (i2c1_spi1_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_I2C &&
i2c1_spi1_peripheral.sda_mosi == (uint8_t)sda &&
i2c1_spi1_peripheral.scl_miso == (uint8_t)scl) {
// The I2C with the same pins is already initialized
i2c = (NRF_TWI_Type *)I2C_1;
obj->peripheral = 0x2;
} else if (i2c0_spi0_peripheral.usage == 0) {
i2c0_spi0_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_I2C;
i2c0_spi0_peripheral.sda_mosi = (uint8_t)sda;
i2c0_spi0_peripheral.scl_miso = (uint8_t)scl;
i2c = (NRF_TWI_Type *)I2C_0;
obj->peripheral = 0x1;
} else if (i2c1_spi1_peripheral.usage == 0) {
i2c1_spi1_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_I2C;
i2c1_spi1_peripheral.sda_mosi = (uint8_t)sda;
i2c1_spi1_peripheral.scl_miso = (uint8_t)scl;
i2c = (NRF_TWI_Type *)I2C_1;
obj->peripheral = 0x2;
} else {
// No available peripheral
error("No available I2C");
}
twi_master_init_and_clear(i2c);
obj->i2c = i2c;
obj->scl = scl;
obj->sda = sda;
obj->i2c->EVENTS_ERROR = 0;
obj->i2c->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
obj->i2c->POWER = 0;
for (int i = 0; i<100; i++) {
}
obj->i2c->POWER = 1;
twi_master_init(obj, sda, scl, 100000);
}
void i2c_reset(i2c_t *obj)
{
obj->i2c->EVENTS_ERROR = 0;
obj->i2c->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
obj->i2c->POWER = 0;
for (int i = 0; i<100; i++) {
}
obj->i2c->POWER = 1;
twi_master_init(obj, obj->sda, obj->scl, obj->freq);
}
int i2c_start(i2c_t *obj)
{
int status = 0;
i2c_reset(obj);
obj->address_set = 0;
return status;
}
int i2c_stop(i2c_t *obj)
{
int timeOut = 100000;
obj->i2c->EVENTS_STOPPED = 0;
// write the stop bit
obj->i2c->TASKS_STOP = 1;
while (!obj->i2c->EVENTS_STOPPED) {
timeOut--;
if (timeOut<0) {
return 1;
}
}
obj->address_set = 0;
i2c_reset(obj);
return 0;
}
int i2c_do_write(i2c_t *obj, int value)
{
int timeOut = 100000;
obj->i2c->TXD = value;
while (!obj->i2c->EVENTS_TXDSENT) {
timeOut--;
if (timeOut<0) {
return 1;
}
}
obj->i2c->EVENTS_TXDSENT = 0;
return 0;
}
int i2c_do_read(i2c_t *obj, char *data, int last)
{
int timeOut = 100000;
if (last) {
// To trigger stop task when a byte is received,
// must be set before resume task.
obj->i2c->SHORTS = 2;
}
obj->i2c->TASKS_RESUME = 1;
while (!obj->i2c->EVENTS_RXDREADY) {
timeOut--;
if (timeOut<0) {
return 1;
}
}
obj->i2c->EVENTS_RXDREADY = 0;
*data = obj->i2c->RXD;
return 0;
}
void i2c_frequency(i2c_t *obj, int hz)
{
if (hz<250000) {
obj->freq = 100000;
obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K100 << TWI_FREQUENCY_FREQUENCY_Pos);
} else if (hz<400000) {
obj->freq = 250000;
obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K250 << TWI_FREQUENCY_FREQUENCY_Pos);
} else {
obj->freq = 400000;
obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K400 << TWI_FREQUENCY_FREQUENCY_Pos);
}
}
int checkError(i2c_t *obj)
{
if (obj->i2c->EVENTS_ERROR == 1) {
if (obj->i2c->ERRORSRC & TWI_ERRORSRC_ANACK_Msk) {
obj->i2c->EVENTS_ERROR = 0;
obj->i2c->TASKS_STOP = 1;
return I2C_ERROR_BUS_BUSY;
}
obj->i2c->EVENTS_ERROR = 0;
obj->i2c->TASKS_STOP = 1;
return I2C_ERROR_NO_SLAVE;
}
return 0;
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
int status, count, errorResult;
obj->i2c->ADDRESS = (address >> 1);
obj->i2c->SHORTS = 1; // to trigger suspend task when a byte is received
obj->i2c->EVENTS_RXDREADY = 0;
obj->i2c->TASKS_STARTRX = 1;
// Read in all except last byte
for (count = 0; count < (length - 1); count++) {
status = i2c_do_read(obj, &data[count], 0);
if (status) {
errorResult = checkError(obj);
i2c_reset(obj);
if (errorResult<0) {
return errorResult;
}
return count;
}
}
// read in last byte
status = i2c_do_read(obj, &data[length - 1], 1);
if (status) {
i2c_reset(obj);
return length - 1;
}
// If not repeated start, send stop.
if (stop) {
while (!obj->i2c->EVENTS_STOPPED) {
}
obj->i2c->EVENTS_STOPPED = 0;
}
return length;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
int status, errorResult;
obj->i2c->ADDRESS = (address >> 1);
obj->i2c->SHORTS = 0;
obj->i2c->TASKS_STARTTX = 1;
for (int i = 0; i<length; i++) {
status = i2c_do_write(obj, data[i]);
if (status) {
i2c_reset(obj);
errorResult = checkError(obj);
if (errorResult<0) {
return errorResult;
}
return i;
}
}
// If not repeated start, send stop.
if (stop) {
if (i2c_stop(obj)) {
return I2C_ERROR_NO_SLAVE;
}
}
return length;
}
int i2c_byte_read(i2c_t *obj, int last)
{
char data;
int status;
status = i2c_do_read(obj, &data, last);
if (status) {
i2c_reset(obj);
}
return data;
}
int i2c_byte_write(i2c_t *obj, int data)
{
int status = 0;
if (!obj->address_set) {
obj->address_set = 1;
obj->i2c->ADDRESS = (data >> 1);
if (data & 1) {
obj->i2c->EVENTS_RXDREADY = 0;
obj->i2c->SHORTS = 1;
obj->i2c->TASKS_STARTRX = 1;
} else {
obj->i2c->SHORTS = 0;
obj->i2c->TASKS_STARTTX = 1;
}
} else {
status = i2c_do_write(obj, data);
if (status) {
i2c_reset(obj);
}
}
return (1 - status);
}

86
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h
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@ -1,86 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#define I2C_SPI_PERIPHERAL_FOR_I2C 1
#define I2C_SPI_PERIPHERAL_FOR_SPI 2
typedef struct {
uint8_t usage; // I2C: 1, SPI: 2
uint8_t sda_mosi;
uint8_t scl_miso;
uint8_t sclk;
} i2c_spi_peripheral_t;
struct serial_s {
NRF_UART_Type *uart;
int index;
};
struct spi_s {
NRF_SPI_Type *spi;
NRF_SPIS_Type *spis;
uint8_t peripheral;
};
struct port_s {
__IO uint32_t *reg_cnf;
__IO uint32_t *reg_out;
__I uint32_t *reg_in;
PortName port;
uint32_t mask;
};
struct pwmout_s {
PWMName pwm;
PinName pin;
};
struct i2c_s {
NRF_TWI_Type *i2c;
PinName sda;
PinName scl;
int freq;
uint8_t address_set;
uint8_t peripheral;
};
struct analogin_s {
ADCName adc;
uint8_t adc_pin;
};
struct gpio_irq_s {
uint32_t ch;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

32
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/pinmap.c
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@ -1,32 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
void pin_function(PinName pin, int function)
{
}
void pin_mode(PinName pin, PinMode mode)
{
MBED_ASSERT(pin != (PinName)NC);
uint32_t pin_number = (uint32_t)pin;
NRF_GPIO->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_PULL_Msk;
NRF_GPIO->PIN_CNF[pin_number] |= (mode << GPIO_PIN_CNF_PULL_Pos);
}

84
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/port_api.c
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@ -1,84 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
PinName port_pin(PortName port, int pin_n)
{
return (PinName)(pin_n);
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
obj->port = port;
obj->mask = mask;
obj->reg_out = &NRF_GPIO->OUT;
obj->reg_in = &NRF_GPIO->IN;
obj->reg_cnf = NRF_GPIO->PIN_CNF;
port_dir(obj, dir);
}
void port_mode(port_t *obj, PinMode mode)
{
uint32_t i;
// The mode is set per pin: reuse pinmap logic
for (i = 0; i<31; i++) {
if (obj->mask & (1 << i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir)
{
int i;
switch (dir) {
case PIN_INPUT:
for (i = 0; i<31; i++) {
if (obj->mask & (1 << i)) {
obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
}
}
break;
case PIN_OUTPUT:
for (i = 0; i<31; i++) {
if (obj->mask & (1 << i)) {
obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
}
}
break;
}
}
void port_write(port_t *obj, int value)
{
*obj->reg_out = value;
}
int port_read(port_t *obj)
{
return (*obj->reg_in);
}

380
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/pwmout_api.c
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@ -1,380 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pwmout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#define NO_PWMS 3
#define TIMER_PRECISION 4 //4us ticks
#define TIMER_PRESCALER 6 //4us ticks = 16Mhz/(2**6)
static const PinMap PinMap_PWM[] = {
{p0, PWM_1, 1},
{p1, PWM_1, 1},
{p2, PWM_1, 1},
{p3, PWM_1, 1},
{p4, PWM_1, 1},
{p5, PWM_1, 1},
{p6, PWM_1, 1},
{p7, PWM_1, 1},
{p8, PWM_1, 1},
{p9, PWM_1, 1},
{p10, PWM_1, 1},
{p11, PWM_1, 1},
{p12, PWM_1, 1},
{p13, PWM_1, 1},
{p14, PWM_1, 1},
{p15, PWM_1, 1},
{p16, PWM_1, 1},
{p17, PWM_1, 1},
{p18, PWM_1, 1},
{p19, PWM_1, 1},
{p20, PWM_1, 1},
{p21, PWM_1, 1},
{p22, PWM_1, 1},
{p23, PWM_1, 1},
{p24, PWM_1, 1},
{p25, PWM_1, 1},
{p28, PWM_1, 1},
{p29, PWM_1, 1},
{p30, PWM_1, 1},
{NC, NC, 0}
};
static NRF_TIMER_Type *Timers[1] = {
NRF_TIMER2
};
uint16_t PERIOD = 20000 / TIMER_PRECISION; //20ms
uint8_t PWM_taken[NO_PWMS] = {0, 0, 0};
uint16_t PULSE_WIDTH[NO_PWMS] = {1, 1, 1}; //set to 1 instead of 0
uint16_t ACTUAL_PULSE[NO_PWMS] = {0, 0, 0};
/** @brief Function for handling timer 2 peripheral interrupts.
*/
#ifdef __cplusplus
extern "C" {
#endif
void TIMER2_IRQHandler(void)
{
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
NRF_TIMER2->CC[3] = PERIOD;
if (PWM_taken[0]) {
NRF_TIMER2->CC[0] = PULSE_WIDTH[0];
}
if (PWM_taken[1]) {
NRF_TIMER2->CC[1] = PULSE_WIDTH[1];
}
if (PWM_taken[2]) {
NRF_TIMER2->CC[2] = PULSE_WIDTH[2];
}
NRF_TIMER2->TASKS_START = 1;
}
#ifdef __cplusplus
}
#endif
/** @brief Function for initializing the Timer peripherals.
*/
void timer_init(uint8_t pwmChoice)
{
NRF_TIMER_Type *timer = Timers[0];
timer->TASKS_STOP = 0;
if (pwmChoice == 0) {
timer->POWER = 0;
timer->POWER = 1;
timer->MODE = TIMER_MODE_MODE_Timer;
timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit << TIMER_BITMODE_BITMODE_Pos;
timer->PRESCALER = TIMER_PRESCALER;
timer->CC[3] = PERIOD;
}
timer->CC[pwmChoice] = PULSE_WIDTH[pwmChoice];
//high priority application interrupt
NVIC_SetPriority(TIMER2_IRQn, 1);
NVIC_EnableIRQ(TIMER2_IRQn);
timer->TASKS_START = 0x01;
}
static void timer_free()
{
NRF_TIMER_Type *timer = Timers[0];
for(uint8_t i = 1; i < NO_PWMS; i++){
if(PWM_taken[i]){
break;
}
if((i == NO_PWMS - 1) && (!PWM_taken[i]))
timer->TASKS_STOP = 0x01;
}
}
/** @brief Function for initializing the GPIO Tasks/Events peripheral.
*/
void gpiote_init(PinName pin, uint8_t channel_number)
{
// Connect GPIO input buffers and configure PWM_OUTPUT_PIN_NUMBER as an output.
NRF_GPIO->PIN_CNF[pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_GPIO->OUTCLR = (1UL << pin);
// Configure GPIOTE channel 0 to toggle the PWM pin state
// @note Only one GPIOTE task can be connected to an output pin.
/* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */
NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
(31UL << GPIOTE_CONFIG_PSEL_Pos) |
(GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
/* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
__NOP();
__NOP();
__NOP();
/* Launch the task to take the GPIOTE channel output to the desired level */
NRF_GPIOTE->TASKS_OUT[channel_number] = 1;
/* Finally configure the channel as the caller expects. If OUTINIT works, the channel is configured properly.
If it does not, the channel output inheritance sets the proper level. */
NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
((uint32_t)pin << GPIOTE_CONFIG_PSEL_Pos) |
((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos) |
((uint32_t)GPIOTE_CONFIG_OUTINIT_Low << GPIOTE_CONFIG_OUTINIT_Pos); // ((uint32_t)GPIOTE_CONFIG_OUTINIT_High <<
// GPIOTE_CONFIG_OUTINIT_Pos);//
/* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
__NOP();
__NOP();
__NOP();
}
static void gpiote_free(PinName pin,uint8_t channel_number)
{
NRF_GPIOTE->TASKS_OUT[channel_number] = 0;
NRF_GPIOTE->CONFIG[channel_number] = 0;
NRF_GPIO->PIN_CNF[pin] = (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
}
/** @brief Function for initializing the Programmable Peripheral Interconnect peripheral.
*/
static void ppi_init(uint8_t pwm)
{
//using ppi channels 0-7 (only 0-7 are available)
uint8_t channel_number = 2 * pwm;
NRF_TIMER_Type *timer = Timers[0];
// Configure PPI channel 0 to toggle ADVERTISING_LED_PIN_NO on every TIMER1 COMPARE[0] match
NRF_PPI->CH[channel_number].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pwm];
NRF_PPI->CH[channel_number + 1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pwm];
NRF_PPI->CH[channel_number].EEP = (uint32_t)&timer->EVENTS_COMPARE[pwm];
NRF_PPI->CH[channel_number + 1].EEP = (uint32_t)&timer->EVENTS_COMPARE[3];
// Enable PPI channels.
NRF_PPI->CHEN |= (1 << channel_number) |
(1 << (channel_number + 1));
}
static void ppi_free(uint8_t pwm)
{
//using ppi channels 0-7 (only 0-7 are available)
uint8_t channel_number = 2*pwm;
// Disable PPI channels.
NRF_PPI->CHEN &= (~(1 << channel_number))
& (~(1 << (channel_number+1)));
}
void setModulation(pwmout_t *obj, uint8_t toggle, uint8_t high)
{
if (high) {
NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos);
if (toggle) {
NRF_GPIOTE->CONFIG[obj->pwm] |= (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
} else {
NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos);
}
} else {
NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos);
if (toggle) {
NRF_GPIOTE->CONFIG[obj->pwm] |= (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
} else {
NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
}
}
}
void pwmout_init(pwmout_t *obj, PinName pin)
{
// determine the channel
uint8_t pwmOutSuccess = 0;
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
if (PWM_taken[(uint8_t)pwm]) {
for (uint8_t i = 1; !pwmOutSuccess && (i<NO_PWMS); i++) {
if (!PWM_taken[i]) {
pwm = (PWMName)i;
PWM_taken[i] = 1;
pwmOutSuccess = 1;
}
}
} else {
pwmOutSuccess = 1;
PWM_taken[(uint8_t)pwm] = 1;
}
if (!pwmOutSuccess) {
error("PwmOut pin mapping failed. All available PWM channels are in use.");
}
obj->pwm = pwm;
obj->pin = pin;
gpiote_init(pin, (uint8_t)pwm);
ppi_init((uint8_t)pwm);
if (pwm == 0) {
NRF_POWER->TASKS_CONSTLAT = 1;
}
timer_init((uint8_t)pwm);
//default to 20ms: standard for servos, and fine for e.g. brightness control
pwmout_period_ms(obj, 20);
pwmout_write (obj, 0);
}
void pwmout_free(pwmout_t* obj) {
MBED_ASSERT(obj->pwm != (PWMName)NC);
pwmout_write(obj, 0);
PWM_taken[obj->pwm] = 0;
timer_free();
ppi_free(obj->pwm);
gpiote_free(obj->pin,obj->pwm);
}
void pwmout_write(pwmout_t *obj, float value)
{
uint16_t oldPulseWidth;
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
NRF_TIMER2->TASKS_STOP = 1;
if (value < 0.0f) {
value = 0.0;
} else if (value > 1.0f) {
value = 1.0;
}
oldPulseWidth = ACTUAL_PULSE[obj->pwm];
ACTUAL_PULSE[obj->pwm] = PULSE_WIDTH[obj->pwm] = value * PERIOD;
if (PULSE_WIDTH[obj->pwm] == 0) {
PULSE_WIDTH[obj->pwm] = 1;
setModulation(obj, 0, 0);
} else if (PULSE_WIDTH[obj->pwm] == PERIOD) {
PULSE_WIDTH[obj->pwm] = PERIOD - 1;
setModulation(obj, 0, 1);
} else if ((oldPulseWidth == 0) || (oldPulseWidth == PERIOD)) {
setModulation(obj, 1, oldPulseWidth == PERIOD);
}
NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk;
NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk;
NRF_TIMER2->TASKS_START = 1;
}
float pwmout_read(pwmout_t *obj)
{
return ((float)PULSE_WIDTH[obj->pwm] / (float)PERIOD);
}
void pwmout_period(pwmout_t *obj, float seconds)
{
pwmout_period_us(obj, seconds * 1000000.0f);
}
void pwmout_period_ms(pwmout_t *obj, int ms)
{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t *obj, int us)
{
uint32_t periodInTicks = us / TIMER_PRECISION;
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
NRF_TIMER2->TASKS_STOP = 1;
if (periodInTicks>((1 << 16) - 1)) {
PERIOD = (1 << 16) - 1; //131ms
} else if (periodInTicks<5) {
PERIOD = 5;
} else {
PERIOD = periodInTicks;
}
NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk;
NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk;
NRF_TIMER2->TASKS_START = 1;
}
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
{
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
{
uint32_t pulseInTicks = us / TIMER_PRECISION;
uint16_t oldPulseWidth = ACTUAL_PULSE[obj->pwm];
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
NRF_TIMER2->TASKS_STOP = 1;
ACTUAL_PULSE[obj->pwm] = PULSE_WIDTH[obj->pwm] = pulseInTicks;
if (PULSE_WIDTH[obj->pwm] == 0) {
PULSE_WIDTH[obj->pwm] = 1;
setModulation(obj, 0, 0);
} else if (PULSE_WIDTH[obj->pwm] == PERIOD) {
PULSE_WIDTH[obj->pwm] = PERIOD - 1;
setModulation(obj, 0, 1);
} else if ((oldPulseWidth == 0) || (oldPulseWidth == PERIOD)) {
setModulation(obj, 1, oldPulseWidth == PERIOD);
}
NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk;
NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk;
NRF_TIMER2->TASKS_START = 1;
}

306
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c
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@ -1,306 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
//#include <math.h>
#include <string.h>
#include "mbed_assert.h"
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define UART_NUM 1
static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
static const int acceptedSpeeds[18][2] = {
{1200, UART_BAUDRATE_BAUDRATE_Baud1200},
{2400, UART_BAUDRATE_BAUDRATE_Baud2400},
{4800, UART_BAUDRATE_BAUDRATE_Baud4800},
{9600, UART_BAUDRATE_BAUDRATE_Baud9600},
{14400, UART_BAUDRATE_BAUDRATE_Baud14400},
{19200, UART_BAUDRATE_BAUDRATE_Baud19200},
{28800, UART_BAUDRATE_BAUDRATE_Baud28800},
{31250, (0x00800000UL) /* 31250 baud */},
{38400, UART_BAUDRATE_BAUDRATE_Baud38400},
{56000, (0x00E51000UL) /* 56000 baud */},
{57600, UART_BAUDRATE_BAUDRATE_Baud57600},
{76800, UART_BAUDRATE_BAUDRATE_Baud76800},
{115200, UART_BAUDRATE_BAUDRATE_Baud115200},
{230400, UART_BAUDRATE_BAUDRATE_Baud230400},
{250000, UART_BAUDRATE_BAUDRATE_Baud250000},
{460800, UART_BAUDRATE_BAUDRATE_Baud460800},
{921600, UART_BAUDRATE_BAUDRATE_Baud921600},
{1000000, UART_BAUDRATE_BAUDRATE_Baud1M}
};
int stdio_uart_inited = 0;
serial_t stdio_uart;
void serial_init(serial_t *obj, PinName tx, PinName rx) {
UARTName uart = UART_0;
obj->uart = (NRF_UART_Type *)uart;
//pin configurations --
NRF_GPIO->OUT |= (1 << tx);
NRF_GPIO->OUT |= (1 << RTS_PIN_NUMBER);
NRF_GPIO->DIR |= (1 << tx); //TX_PIN_NUMBER);
NRF_GPIO->DIR |= (1 << RTS_PIN_NUMBER);
NRF_GPIO->DIR &= ~(1 << rx); //RX_PIN_NUMBER);
NRF_GPIO->DIR &= ~(1 << CTS_PIN_NUMBER);
// set default baud rate and format
serial_baud (obj, 9600);
serial_format(obj, 8, ParityNone, 1);
obj->uart->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos);
obj->uart->TASKS_STARTTX = 1;
obj->uart->TASKS_STARTRX = 1;
obj->uart->EVENTS_RXDRDY = 0;
// dummy write needed or TXDRDY trails write rather than leads write.
// pins are disconnected so nothing is physically transmitted on the wire
obj->uart->PSELTXD = 0xFFFFFFFF;
obj->uart->EVENTS_TXDRDY = 0;
obj->uart->TXD = 0;
while (obj->uart->EVENTS_TXDRDY != 1);
obj->index = 0;
obj->uart->PSELRTS = RTS_PIN_NUMBER;
obj->uart->PSELTXD = tx; //TX_PIN_NUMBER;
obj->uart->PSELCTS = CTS_PIN_NUMBER;
obj->uart->PSELRXD = rx; //RX_PIN_NUMBER;
// set rx/tx pins in PullUp mode
if (tx != NC) {
pin_mode(tx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
if (uart == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
serial_irq_ids[obj->index] = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate)
{
if (baudrate<=1200) {
obj->uart->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1200;
return;
}
for (int i = 1; i<17; i++) {
if (baudrate<acceptedSpeeds[i][0]) {
obj->uart->BAUDRATE = acceptedSpeeds[i - 1][1];
return;
}
}
obj->uart->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1M;
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
// 0: 1 stop bits, 1: 2 stop bits
// int parity_enable, parity_select;
switch (parity) {
case ParityNone:
obj->uart->CONFIG = 0;
break;
default:
obj->uart->CONFIG = (UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos);
return;
}
//no Flow Control
}
//******************************************************************************
// * INTERRUPT HANDLING
//******************************************************************************
static inline void uart_irq(uint32_t iir, uint32_t index)
{
SerialIrq irq_type;
switch (iir) {
case 1:
irq_type = TxIrq;
break;
case 2:
irq_type = RxIrq;
break;
default:
return;
}
if (serial_irq_ids[index] != 0) {
irq_handler(serial_irq_ids[index], irq_type);
}
}
#ifdef __cplusplus
extern "C" {
#endif
void UART0_IRQHandler()
{
uint32_t irtype = 0;
if((NRF_UART0->INTENSET & 0x80) && NRF_UART0->EVENTS_TXDRDY) {
irtype = 1;
} else if((NRF_UART0->INTENSET & 0x04) && NRF_UART0->EVENTS_RXDRDY) {
irtype = 2;
}
uart_irq(irtype, 0);
}
#ifdef __cplusplus
}
#endif
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
switch ((int)obj->uart) {
case UART_0:
irq_n = UART0_IRQn;
break;
}
if (enable) {
switch (irq) {
case RxIrq:
obj->uart->INTENSET = (UART_INTENSET_RXDRDY_Msk);
break;
case TxIrq:
obj->uart->INTENSET = (UART_INTENSET_TXDRDY_Msk);
break;
}
NVIC_SetPriority(irq_n, 3);
NVIC_EnableIRQ(irq_n);
} else { // disable
// maseked writes to INTENSET dont disable and masked writes to
// INTENCLR seemed to clear the entire register, not bits.
// Added INTEN to memory map and seems to allow set and clearing of specific bits as desired
int all_disabled = 0;
switch (irq) {
case RxIrq:
obj->uart->INTENCLR = (UART_INTENCLR_RXDRDY_Msk);
all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_TXDRDY_Msk)) == 0;
break;
case TxIrq:
obj->uart->INTENCLR = (UART_INTENCLR_TXDRDY_Msk);
all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_RXDRDY_Msk)) == 0;
break;
}
if (all_disabled) {
NVIC_DisableIRQ(irq_n);
}
}
}
//******************************************************************************
//* READ/WRITE
//******************************************************************************
int serial_getc(serial_t *obj)
{
while (!serial_readable(obj)) {
}
obj->uart->EVENTS_RXDRDY = 0;
return (uint8_t)obj->uart->RXD;
}
void serial_putc(serial_t *obj, int c)
{
while (!serial_writable(obj)) {
}
obj->uart->EVENTS_TXDRDY = 0;
obj->uart->TXD = (uint8_t)c;
}
int serial_readable(serial_t *obj)
{
return (obj->uart->EVENTS_RXDRDY == 1);
}
int serial_writable(serial_t *obj)
{
return (obj->uart->EVENTS_TXDRDY == 1);
}
void serial_break_set(serial_t *obj)
{
obj->uart->TASKS_SUSPEND = 1;
}
void serial_break_clear(serial_t *obj)
{
obj->uart->TASKS_STARTTX = 1;
obj->uart->TASKS_STARTRX = 1;
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
if (type == FlowControlRTSCTS || type == FlowControlRTS) {
NRF_GPIO->DIR |= (1<<rxflow);
pin_mode(rxflow, PullUp);
obj->uart->PSELRTS = rxflow;
obj->uart->CONFIG |= 0x01; // Enable HWFC
}
if (type == FlowControlRTSCTS || type == FlowControlCTS) {
NRF_GPIO->DIR &= ~(1<<txflow);
pin_mode(txflow, PullUp);
obj->uart->PSELCTS = txflow;
obj->uart->CONFIG |= 0x01; // Enable HWFC;
}
if (type == FlowControlNone) {
obj->uart->PSELRTS = 0xFFFFFFFF; // Disable RTS
obj->uart->PSELCTS = 0xFFFFFFFF; // Disable CTS
obj->uart->CONFIG &= ~0x01; // Enable HWFC;
}
}
void serial_clear(serial_t *obj) {
}

286
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/spi_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//#include <math.h>
#include "mbed_assert.h"
#include "spi_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#define SPIS_MESSAGE_SIZE 1
volatile uint8_t m_tx_buf[SPIS_MESSAGE_SIZE] = {0};
volatile uint8_t m_rx_buf[SPIS_MESSAGE_SIZE] = {0};
// nRF51822's I2C_0 and SPI_0 (I2C_1, SPI_1 and SPIS1) share the same address.
// They can't be used at the same time. So we use two global variable to track the usage.
// See nRF51822 address information at nRF51822_PS v2.0.pdf - Table 15 Peripheral instance reference
extern volatile i2c_spi_peripheral_t i2c0_spi0_peripheral; // from i2c_api.c
extern volatile i2c_spi_peripheral_t i2c1_spi1_peripheral;
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
SPIName spi;
if (ssel == NC && i2c0_spi0_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI &&
i2c0_spi0_peripheral.sda_mosi == (uint8_t)mosi &&
i2c0_spi0_peripheral.scl_miso == (uint8_t)miso &&
i2c0_spi0_peripheral.sclk == (uint8_t)sclk) {
// The SPI with the same pins is already initialized
spi = SPI_0;
obj->peripheral = 0x1;
} else if (ssel == NC && i2c1_spi1_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI &&
i2c1_spi1_peripheral.sda_mosi == (uint8_t)mosi &&
i2c1_spi1_peripheral.scl_miso == (uint8_t)miso &&
i2c1_spi1_peripheral.sclk == (uint8_t)sclk) {
// The SPI with the same pins is already initialized
spi = SPI_1;
obj->peripheral = 0x2;
} else if (i2c1_spi1_peripheral.usage == 0) {
i2c1_spi1_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI;
i2c1_spi1_peripheral.sda_mosi = (uint8_t)mosi;
i2c1_spi1_peripheral.scl_miso = (uint8_t)miso;
i2c1_spi1_peripheral.sclk = (uint8_t)sclk;
spi = SPI_1;
obj->peripheral = 0x2;
} else if (i2c0_spi0_peripheral.usage == 0) {
i2c0_spi0_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI;
i2c0_spi0_peripheral.sda_mosi = (uint8_t)mosi;
i2c0_spi0_peripheral.scl_miso = (uint8_t)miso;
i2c0_spi0_peripheral.sclk = (uint8_t)sclk;
spi = SPI_0;
obj->peripheral = 0x1;
} else {
// No available peripheral
error("No available SPI");
}
if (ssel==NC) {
obj->spi = (NRF_SPI_Type *)spi;
obj->spis = (NRF_SPIS_Type *)NC;
} else {
obj->spi = (NRF_SPI_Type *)NC;
obj->spis = (NRF_SPIS_Type *)spi;
}
// pin out the spi pins
if (ssel != NC) { //slave
obj->spis->POWER = 0;
obj->spis->POWER = 1;
NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
NRF_GPIO->PIN_CNF[ssel] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
obj->spis->PSELMOSI = mosi;
obj->spis->PSELMISO = miso;
obj->spis->PSELSCK = sclk;
obj->spis->PSELCSN = ssel;
obj->spis->EVENTS_END = 0;
obj->spis->EVENTS_ACQUIRED = 0;
obj->spis->MAXRX = SPIS_MESSAGE_SIZE;
obj->spis->MAXTX = SPIS_MESSAGE_SIZE;
obj->spis->TXDPTR = (uint32_t)&m_tx_buf[0];
obj->spis->RXDPTR = (uint32_t)&m_rx_buf[0];
obj->spis->SHORTS = (SPIS_SHORTS_END_ACQUIRE_Enabled << SPIS_SHORTS_END_ACQUIRE_Pos);
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
} else { //master
obj->spi->POWER = 0;
obj->spi->POWER = 1;
//NRF_GPIO->DIR |= (1<<mosi);
NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
obj->spi->PSELMOSI = mosi;
NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
obj->spi->PSELSCK = sclk;
//NRF_GPIO->DIR &= ~(1<<miso);
NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
obj->spi->PSELMISO = miso;
obj->spi->EVENTS_READY = 0U;
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
spi_frequency(obj, 1000000);
}
}
void spi_free(spi_t *obj)
{
}
static inline void spi_disable(spi_t *obj, int slave)
{
if (slave) {
obj->spis->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
} else {
obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
}
}
static inline void spi_enable(spi_t *obj, int slave)
{
if (slave) {
obj->spis->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
} else {
obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
}
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
uint32_t config_mode = 0;
spi_disable(obj, slave);
if (bits != 8) {
error("Only 8bits SPI supported");
}
switch (mode) {
case 0:
config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
break;
case 1:
config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
break;
case 2:
config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
break;
case 3:
config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
break;
default:
error("SPI format error");
break;
}
//default to msb first
if (slave) {
obj->spis->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
} else {
obj->spi->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
}
spi_enable(obj, slave);
}
void spi_frequency(spi_t *obj, int hz)
{
if ((int)obj->spi==NC) {
return;
}
spi_disable(obj, 0);
if (hz<250000) { //125Kbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K125;
} else if (hz<500000) { //250Kbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K250;
} else if (hz<1000000) { //500Kbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K500;
} else if (hz<2000000) { //1Mbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M1;
} else if (hz<4000000) { //2Mbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M2;
} else if (hz<8000000) { //4Mbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M4;
} else { //8Mbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M8;
}
spi_enable(obj, 0);
}
static inline int spi_readable(spi_t *obj)
{
return (obj->spi->EVENTS_READY == 1);
}
static inline int spi_writeable(spi_t *obj)
{
return (obj->spi->EVENTS_READY == 0);
}
static inline int spi_read(spi_t *obj)
{
while (!spi_readable(obj)) {
}
obj->spi->EVENTS_READY = 0;
return (int)obj->spi->RXD;
}
int spi_master_write(spi_t *obj, int value)
{
while (!spi_writeable(obj)) {
}
obj->spi->TXD = (uint32_t)value;
return spi_read(obj);
}
//static inline int spis_writeable(spi_t *obj) {
// return (obj->spis->EVENTS_ACQUIRED==1);
//}
int spi_slave_receive(spi_t *obj)
{
return obj->spis->EVENTS_END;
}
int spi_slave_read(spi_t *obj)
{
return m_rx_buf[0];
}
void spi_slave_write(spi_t *obj, int value)
{
m_tx_buf[0] = value & 0xFF;
obj->spis->TASKS_RELEASE = 1;
obj->spis->EVENTS_ACQUIRED = 0;
obj->spis->EVENTS_END = 0;
}

20
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_config.h
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@ -1,20 +0,0 @@
/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef TWI_MASTER_CONFIG
#define TWI_MASTER_CONFIG
#include "PinNames.h"
#define TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER (I2C_SCL0)
#define TWI_MASTER_CONFIG_DATA_PIN_NUMBER (I2C_SDA0)
#endif

304
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.c
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/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#include "twi_master.h"
#include "twi_config.h"
#include <stdbool.h>
#include <stdint.h>
#include "nrf.h"
#include "nrf_delay.h"
/* Max cycles approximately to wait on RXDREADY and TXDREADY event,
* This is optimized way instead of using timers, this is not power aware. */
#define MAX_TIMEOUT_LOOPS (20000UL) /**< MAX while loops to wait for RXD/TXD event */
static bool twi_master_write(uint8_t * data, uint8_t data_length, bool issue_stop_condition, NRF_TWI_Type* twi)
{
uint32_t timeout = MAX_TIMEOUT_LOOPS; /* max loops to wait for EVENTS_TXDSENT event*/
if (data_length == 0)
{
/* Return false for requesting data of size 0 */
return false;
}
twi->TXD = *data++;
twi->TASKS_STARTTX = 1;
/** @snippet [TWI HW master write] */
while (true)
{
while (twi->EVENTS_TXDSENT == 0 && twi->EVENTS_ERROR == 0 && (--timeout))
{
// Do nothing.
}
if (timeout == 0 || NRF_TWI1->EVENTS_ERROR != 0)
{
// Recover the peripheral as indicated by PAN 56: "TWI: TWI module lock-up." found at
// Product Anomaly Notification document found at
// https://www.nordicsemi.com/eng/Products/Bluetooth-R-low-energy/nRF51822/#Downloads
twi->EVENTS_ERROR = 0;
twi->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
twi->POWER = 0;
nrf_delay_us(5);
twi->POWER = 1;
twi->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
(void)twi_master_init_and_clear(twi);
return false;
}
twi->EVENTS_TXDSENT = 0;
if (--data_length == 0)
{
break;
}
twi->TXD = *data++;
}
/** @snippet [TWI HW master write] */
if (issue_stop_condition)
{
twi->EVENTS_STOPPED = 0;
twi->TASKS_STOP = 1;
/* Wait until stop sequence is sent */
while(twi->EVENTS_STOPPED == 0)
{
// Do nothing.
}
}
return true;
}
/** @brief Function for read by twi_master.
*/
static bool twi_master_read(uint8_t * data, uint8_t data_length, bool issue_stop_condition, NRF_TWI_Type* twi)
{
uint32_t timeout = MAX_TIMEOUT_LOOPS; /* max loops to wait for RXDREADY event*/
if (data_length == 0)
{
/* Return false for requesting data of size 0 */
return false;
}
else if (data_length == 1)
{
NRF_PPI->CH[0].TEP = (uint32_t)&twi->TASKS_STOP;
}
else
{
NRF_PPI->CH[0].TEP = (uint32_t)&twi->TASKS_SUSPEND;
}
NRF_PPI->CHENSET = PPI_CHENSET_CH0_Msk;
twi->EVENTS_RXDREADY = 0;
twi->TASKS_STARTRX = 1;
/** @snippet [TWI HW master read] */
while (true)
{
while (twi->EVENTS_RXDREADY == 0 && NRF_TWI1->EVENTS_ERROR == 0 && (--timeout))
{
// Do nothing.
}
twi->EVENTS_RXDREADY = 0;
if (timeout == 0 || twi->EVENTS_ERROR != 0)
{
// Recover the peripheral as indicated by PAN 56: "TWI: TWI module lock-up." found at
// Product Anomaly Notification document found at
// https://www.nordicsemi.com/eng/Products/Bluetooth-R-low-energy/nRF51822/#Downloads
twi->EVENTS_ERROR = 0;
twi->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
twi->POWER = 0;
nrf_delay_us(5);
twi->POWER = 1;
twi->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
(void)twi_master_init_and_clear(twi);
return false;
}
*data++ = NRF_TWI1->RXD;
/* Configure PPI to stop TWI master before we get last BB event */
if (--data_length == 1)
{
NRF_PPI->CH[0].TEP = (uint32_t)&NRF_TWI1->TASKS_STOP;
}
if (data_length == 0)
{
break;
}
// Recover the peripheral as indicated by PAN 56: "TWI: TWI module lock-up." found at
// Product Anomaly Notification document found at
// https://www.nordicsemi.com/eng/Products/Bluetooth-R-low-energy/nRF51822/#Downloads
nrf_delay_us(20);
twi->TASKS_RESUME = 1;
}
/** @snippet [TWI HW master read] */
/* Wait until stop sequence is sent */
while(twi->EVENTS_STOPPED == 0)
{
// Do nothing.
}
twi->EVENTS_STOPPED = 0;
NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Msk;
return true;
}
/**
* @brief Function for detecting stuck slaves (SDA = 0 and SCL = 1) and tries to clear the bus.
*
* @return
* @retval false Bus is stuck.
* @retval true Bus is clear.
*/
static bool twi_master_clear_bus(NRF_TWI_Type* twi)
{
uint32_t twi_state;
bool bus_clear;
uint32_t clk_pin_config;
uint32_t data_pin_config;
// Save and disable TWI hardware so software can take control over the pins.
twi_state = twi->ENABLE;
twi->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
clk_pin_config = \
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER];
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = \
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
data_pin_config = \
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER];
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = \
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
TWI_SDA_HIGH();
TWI_SCL_HIGH();
TWI_DELAY();
if ((TWI_SDA_READ() == 1) && (TWI_SCL_READ() == 1))
{
bus_clear = true;
}
else
{
uint_fast8_t i;
bus_clear = false;
// Clock max 18 pulses worst case scenario(9 for master to send the rest of command and 9
// for slave to respond) to SCL line and wait for SDA come high.
for (i=18; i--;)
{
TWI_SCL_LOW();
TWI_DELAY();
TWI_SCL_HIGH();
TWI_DELAY();
if (TWI_SDA_READ() == 1)
{
bus_clear = true;
break;
}
}
}
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = clk_pin_config;
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = data_pin_config;
twi->ENABLE = twi_state;
return bus_clear;
}
/** @brief Function for initializing the twi_master.
*/
bool twi_master_init_and_clear(NRF_TWI_Type* twi)
{
/* To secure correct signal levels on the pins used by the TWI
master when the system is in OFF mode, and when the TWI master is
disabled, these pins must be configured in the GPIO peripheral.
*/
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = \
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = \
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
twi->EVENTS_RXDREADY = 0;
twi->EVENTS_TXDSENT = 0;
twi->PSELSCL = TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER;
twi->PSELSDA = TWI_MASTER_CONFIG_DATA_PIN_NUMBER;
twi->FREQUENCY = TWI_FREQUENCY_FREQUENCY_K100 << TWI_FREQUENCY_FREQUENCY_Pos;
NRF_PPI->CH[0].EEP = (uint32_t)&twi->EVENTS_BB;
NRF_PPI->CH[0].TEP = (uint32_t)&twi->TASKS_SUSPEND;
NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Msk;
twi->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos;
return twi_master_clear_bus(twi);
}
/** @brief Function for transfer by twi_master.
*/
bool twi_master_transfer(uint8_t address,
uint8_t * data,
uint8_t data_length,
bool issue_stop_condition,
NRF_TWI_Type* twi)
{
bool transfer_succeeded = false;
if (data_length > 0 && twi_master_clear_bus(twi))
{
twi->ADDRESS = (address >> 1);
if ((address & TWI_READ_BIT))
{
transfer_succeeded = twi_master_read(data, data_length, issue_stop_condition, twi);
}
else
{
transfer_succeeded = twi_master_write(data, data_length, issue_stop_condition, twi);
}
}
return transfer_succeeded;
}
/*lint --flb "Leave library region" */

112
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.h
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@ -1,112 +0,0 @@
/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef TWI_MASTER_H
#define TWI_MASTER_H
#ifdef __cplusplus
extern "C" {
#endif
/*lint ++flb "Enter library region" */
#include <stdbool.h>
#include <stdint.h>
#include "nrf51.h"
/** @file
* @brief Software controlled TWI Master driver.
*
*
* @defgroup lib_driver_twi_master Software controlled TWI Master driver
* @{
* @ingroup nrf_drivers
* @brief Software controlled TWI Master driver.
*
* Supported features:
* - Repeated start
* - No multi-master
* - Only 7-bit addressing
* - Supports clock stretching (with optional SMBus style slave timeout)
* - Tries to handle slaves stuck in the middle of transfer
*/
#define TWI_READ_BIT (0x01) //!< If this bit is set in the address field, transfer direction is from slave to master.
#define TWI_ISSUE_STOP ((bool)true) //!< Parameter for @ref twi_master_transfer
#define TWI_DONT_ISSUE_STOP ((bool)false) //!< Parameter for @ref twi_master_transfer
/* These macros are needed to see if the slave is stuck and we as master send dummy clock cycles to end its wait */
/*lint -e717 -save "Suppress do {} while (0) for these macros" */
/*lint ++flb "Enter library region" */
#define TWI_SCL_HIGH() do { NRF_GPIO->OUTSET = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Pulls SCL line high */
#define TWI_SCL_LOW() do { NRF_GPIO->OUTCLR = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Pulls SCL line low */
#define TWI_SDA_HIGH() do { NRF_GPIO->OUTSET = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Pulls SDA line high */
#define TWI_SDA_LOW() do { NRF_GPIO->OUTCLR = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Pulls SDA line low */
#define TWI_SDA_INPUT() do { NRF_GPIO->DIRCLR = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Configures SDA pin as input */
#define TWI_SDA_OUTPUT() do { NRF_GPIO->DIRSET = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Configures SDA pin as output */
#define TWI_SCL_OUTPUT() do { NRF_GPIO->DIRSET = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Configures SCL pin as output */
/*lint -restore */
#define TWI_SDA_READ() ((NRF_GPIO->IN >> TWI_MASTER_CONFIG_DATA_PIN_NUMBER) & 0x1UL) /*!< Reads current state of SDA */
#define TWI_SCL_READ() ((NRF_GPIO->IN >> TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER) & 0x1UL) /*!< Reads current state of SCL */
#define TWI_DELAY() nrf_delay_us(4) /*!< Time to wait when pin states are changed. For fast-mode the delay can be zero and for standard-mode 4 us delay is sufficient. */
/**
* @brief Function for initializing TWI bus IO pins and checks if the bus is operational.
*
* Both pins are configured as Standard-0, No-drive-1 (open drain).
*
* @param twi The TWI interface to use - either NRF_TWI0 or NRF_TWI1
* @return
* @retval true TWI bus is clear for transfers.
* @retval false TWI bus is stuck.
*/
bool twi_master_init_and_clear(NRF_TWI_Type* twi);
/**
* @brief Function for transferring data over TWI bus.
*
* If TWI master detects even one NACK from the slave or timeout occurs, STOP condition is issued
* and the function returns false.
* Bit 0 (@ref TWI_READ_BIT) in the address parameter controls transfer direction;
* - If 1, master reads data_length number of bytes from the slave
* - If 0, master writes data_length number of bytes to the slave.
*
* @note Make sure at least data_length number of bytes is allocated in data if TWI_READ_BIT is set.
* @note @ref TWI_ISSUE_STOP
*
* @param address Data transfer direction (LSB) / Slave address (7 MSBs).
* @param data Pointer to data.
* @param data_length Number of bytes to transfer.
* @param issue_stop_condition If @ref TWI_ISSUE_STOP, STOP condition is issued before exiting function. If @ref TWI_DONT_ISSUE_STOP, STOP condition is not issued before exiting function. If transfer failed for any reason, STOP condition will be issued in any case.
* @param twi The TWI interface to use - either NRF_TWI0 or NRF_TWI1
* @return
* @retval true Data transfer succeeded without errors.
* @retval false Data transfer failed.
*/
bool twi_master_transfer(uint8_t address, uint8_t *data, uint8_t data_length, bool issue_stop_condition, NRF_TWI_Type* twi);
/**
*@}
**/
#ifdef __cplusplus
}
#endif
/*lint --flb "Leave library region" */
#endif //TWI_MASTER_H

602
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c
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@ -1,602 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include <stdbool.h>
#include "us_ticker_api.h"
#include "cmsis.h"
#include "PeripheralNames.h"
#include "nrf_delay.h"
#include "toolchain.h"
/*
* Note: The micro-second timer API on the nRF51 platform is implemented using
* the RTC counter run at 32kHz (sourced from an external oscillator). This is
* a trade-off between precision and power. Running a normal 32-bit MCU counter
* at high frequency causes the average power consumption to rise to a few
* hundred micro-amps, which is prohibitive for typical low-power BLE
* applications.
* A 32kHz clock doesn't offer the precision needed for keeping u-second time,
* but we're assuming that this will not be a problem for the average user.
*/
#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */
#define RTC_CLOCK_FREQ (uint32_t)(32768)
#define RTC1_IRQ_PRI 3 /**< Priority of the RTC1 interrupt (used
* for checking for timeouts and executing
* timeout handlers). This must be the same
* as APP_IRQ_PRIORITY_LOW; taken from the
* Nordic SDK. */
#define MAX_RTC_TASKS_DELAY 47 /**< Maximum delay until an RTC task is executed. */
#define FUZZY_RTC_TICKS 2 /* RTC COMPARE occurs when a CC register is N and the RTC
* COUNTER value transitions from N-1 to N. If we're trying to
* setup a callback for a time which will arrive very shortly,
* there are limits to how short the callback interval may be for us
* to rely upon the RTC Compare trigger. If the COUNTER is N,
* writing N+2 to a CC register is guaranteed to trigger a COMPARE
* event at N+2. */
#define RTC_UNITS_TO_MICROSECONDS(RTC_UNITS) (((RTC_UNITS) * (uint64_t)1000000) / RTC_CLOCK_FREQ)
#define MICROSECONDS_TO_RTC_UNITS(MICROS) ((((uint64_t)(MICROS) * RTC_CLOCK_FREQ) + 999999) / 1000000)
static bool us_ticker_inited = false;
static volatile uint32_t overflowCount; /**< The number of times the 24-bit RTC counter has overflowed. */
static volatile bool us_ticker_callbackPending = false;
static uint32_t us_ticker_callbackTimestamp;
static bool os_tick_started = false; /**< flag indicating if the os_tick has started */
/**
* The value previously set in the capture compare register of channel 1
*/
static uint32_t previous_tick_cc_value = 0;
/*
RTX provide the following definitions which are used by the tick code:
* os_trv: The number (minus 1) of clock cycle between two tick.
* os_clockrate: Time duration between two ticks (in us).
* OS_Tick_Handler: The function which handle a tick event.
This function is special because it never returns.
Those definitions are used by the code which handle the os tick.
To allow compilation of us_ticker programs without RTOS, those symbols are
exported from this module as weak ones.
*/
MBED_WEAK uint32_t const os_trv;
MBED_WEAK uint32_t const os_clockrate;
MBED_WEAK void OS_Tick_Handler() { }
static inline void rtc1_enableCompareInterrupt(void)
{
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk;
}
static inline void rtc1_disableCompareInterrupt(void)
{
NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk;
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
}
static inline void rtc1_enableOverflowInterrupt(void)
{
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
NRF_RTC1->INTENSET = RTC_INTENSET_OVRFLW_Msk;
}
static inline void rtc1_disableOverflowInterrupt(void)
{
NRF_RTC1->INTENCLR = RTC_INTENSET_OVRFLW_Msk;
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
}
static inline void invokeCallback(void)
{
us_ticker_callbackPending = false;
rtc1_disableCompareInterrupt();
us_ticker_irq_handler();
}
/**
* @brief Function for starting the RTC1 timer. The RTC timer is expected to
* keep running--some interrupts may be disabled temporarily.
*/
static void rtc1_start()
{
NRF_RTC1->PRESCALER = 0; /* for no pre-scaling. */
rtc1_enableOverflowInterrupt();
NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI);
NVIC_ClearPendingIRQ(RTC1_IRQn);
NVIC_EnableIRQ(RTC1_IRQn);
NRF_RTC1->TASKS_START = 1;
nrf_delay_us(MAX_RTC_TASKS_DELAY);
}
/**
* @brief Function for stopping the RTC1 timer. We don't expect to call this.
*/
void rtc1_stop(void)
{
// If the os tick has been started, RTC1 shouldn't be stopped
// In that case, us ticker and overflow interrupt are disabled.
if (os_tick_started) {
rtc1_disableCompareInterrupt();
rtc1_disableOverflowInterrupt();
} else {
NVIC_DisableIRQ(RTC1_IRQn);
rtc1_disableCompareInterrupt();
rtc1_disableOverflowInterrupt();
NRF_RTC1->TASKS_STOP = 1;
nrf_delay_us(MAX_RTC_TASKS_DELAY);
NRF_RTC1->TASKS_CLEAR = 1;
nrf_delay_us(MAX_RTC_TASKS_DELAY);
}
}
/**
* @brief Function for returning the current value of the RTC1 counter.
*
* @return Current RTC1 counter as a 64-bit value with 56-bit precision (even
* though the underlying counter is 24-bit)
*/
static inline uint64_t rtc1_getCounter64(void)
{
if (NRF_RTC1->EVENTS_OVRFLW) {
overflowCount++;
NRF_RTC1->EVENTS_OVRFLW = 0;
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
}
return ((uint64_t)overflowCount << 24) | NRF_RTC1->COUNTER;
}
/**
* @brief Function for returning the current value of the RTC1 counter.
*
* @return Current RTC1 counter as a 32-bit value (even though the underlying counter is 24-bit)
*/
static inline uint32_t rtc1_getCounter(void)
{
return rtc1_getCounter64();
}
/**
* @brief Function for handling the RTC1 interrupt for us ticker (capture compare channel 0 and overflow).
*
* @details Checks for timeouts, and executes timeout handlers for expired timers.
*/
void us_ticker_handler(void)
{
if (NRF_RTC1->EVENTS_OVRFLW) {
overflowCount++;
NRF_RTC1->EVENTS_OVRFLW = 0;
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
}
if (NRF_RTC1->EVENTS_COMPARE[0]) {
NRF_RTC1->EVENTS_COMPARE[0] = 0;
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
if (us_ticker_callbackPending && ((int)(us_ticker_callbackTimestamp - rtc1_getCounter()) <= 0))
invokeCallback();
}
}
void us_ticker_init(void)
{
if (us_ticker_inited) {
return;
}
rtc1_start();
us_ticker_inited = true;
}
uint32_t us_ticker_read()
{
if (!us_ticker_inited) {
us_ticker_init();
}
/* Return a pseudo microsecond counter value. This is only as precise as the
* 32khz low-freq clock source, but could be adequate.*/
return RTC_UNITS_TO_MICROSECONDS(rtc1_getCounter64());
}
/**
* Setup the us_ticker callback interrupt to go at the given timestamp.
*
* @Note: Only one callback is pending at any time.
*
* @Note: If a callback is pending, and this function is called again, the new
* callback-time overrides the existing callback setting. It is the caller's
* responsibility to ensure that this function is called to setup a callback for
* the earliest timeout.
*
* @Note: If this function is used to setup an interrupt which is immediately
* pending--such as for 'now' or a time in the past,--then the callback is
* invoked a few ticks later.
*/
void us_ticker_set_interrupt(timestamp_t timestamp)
{
if (!us_ticker_inited) {
us_ticker_init();
}
/*
* The argument to this function is a 32-bit microsecond timestamp for when
* a callback should be invoked. On the nRF51, we use an RTC timer running
* at 32kHz to implement a low-power us-ticker. This results in a problem
* based on the fact that 1000000 is not a multiple of 32768.
*
* Going from a micro-second based timestamp to a 32kHz based RTC-time is a
* linear mapping; but this mapping doesn't preserve wraparounds--i.e. when
* the 32-bit micro-second timestamp wraps around unfortunately the
* underlying RTC counter doesn't. The result is that timestamp expiry
* checks on micro-second timestamps don't yield the same result when
* applied on the corresponding RTC timestamp values.
*
* One solution is to translate the incoming 32-bit timestamp into a virtual
* 64-bit timestamp based on the knowledge of system-uptime, and then use
* this wraparound-free 64-bit value to do a linear mapping to RTC time.
* System uptime on an nRF is maintained using the 24-bit RTC counter. We
* track the overflow count to extend the 24-bit hardware counter by an
* additional 32 bits. RTC_UNITS_TO_MICROSECONDS() converts this into
* microsecond units (in 64-bits).
*/
const uint64_t currentTime64 = RTC_UNITS_TO_MICROSECONDS(rtc1_getCounter64());
uint64_t timestamp64 = (currentTime64 & ~(uint64_t)0xFFFFFFFFULL) + timestamp;
if (((uint32_t)currentTime64 > 0x80000000) && (timestamp < 0x80000000)) {
timestamp64 += (uint64_t)0x100000000ULL;
}
uint32_t newCallbackTime = MICROSECONDS_TO_RTC_UNITS(timestamp64);
/* Check for repeat setup of an existing callback. This is actually not
* important; the following code should work even without this check. */
if (us_ticker_callbackPending && (newCallbackTime == us_ticker_callbackTimestamp)) {
return;
}
/* Check for callbacks which are immediately (or will *very* shortly become) pending.
* Even if they are immediately pending, they are scheduled to trigger a few
* ticks later. This keeps things simple by invoking the callback from an
* independent interrupt context. */
if ((int)(newCallbackTime - rtc1_getCounter()) <= (int)FUZZY_RTC_TICKS) {
newCallbackTime = rtc1_getCounter() + FUZZY_RTC_TICKS;
}
NRF_RTC1->CC[0] = newCallbackTime & MAX_RTC_COUNTER_VAL;
us_ticker_callbackTimestamp = newCallbackTime;
if (!us_ticker_callbackPending) {
us_ticker_callbackPending = true;
rtc1_enableCompareInterrupt();
}
}
void us_ticker_disable_interrupt(void)
{
if (us_ticker_callbackPending) {
rtc1_disableCompareInterrupt();
us_ticker_callbackPending = false;
}
}
void us_ticker_clear_interrupt(void)
{
NRF_RTC1->EVENTS_OVRFLW = 0;
NRF_RTC1->EVENTS_COMPARE[0] = 0;
}
#if defined (__CC_ARM) /* ARMCC Compiler */
__asm void RTC1_IRQHandler(void)
{
IMPORT OS_Tick_Handler
IMPORT us_ticker_handler
/**
* Chanel 1 of RTC1 is used by RTX as a systick.
* If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
* Otherwise, just execute us_ticker_handler.
* This function has to be written in assembly and tagged as naked because OS_Tick_Handler
* will never return.
* A c function would put lr on the stack before calling OS_Tick_Handler and this value
* would never been dequeued.
*
* \code
* void RTC1_IRQHandler(void) {
if(NRF_RTC1->EVENTS_COMPARE[1]) {
// never return...
OS_Tick_Handler();
} else {
us_ticker_handler();
}
}
* \endcode
*/
ldr r0,=0x40011144
ldr r1, [r0, #0]
cmp r1, #0
beq US_TICKER_HANDLER
bl OS_Tick_Handler
US_TICKER_HANDLER
push {r3, lr}
bl us_ticker_handler
pop {r3, pc}
nop /* padding */
}
#elif defined (__GNUC__) /* GNU Compiler */
__attribute__((naked)) void RTC1_IRQHandler(void)
{
/**
* Chanel 1 of RTC1 is used by RTX as a systick.
* If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
* Otherwise, just execute us_ticker_handler.
* This function has to be written in assembly and tagged as naked because OS_Tick_Handler
* will never return.
* A c function would put lr on the stack before calling OS_Tick_Handler and this value
* would never been dequeued.
*
* \code
* void RTC1_IRQHandler(void) {
if(NRF_RTC1->EVENTS_COMPARE[1]) {
// never return...
OS_Tick_Handler();
} else {
us_ticker_handler();
}
}
* \endcode
*/
__asm__ (
"ldr r0,=0x40011144\n"
"ldr r1, [r0, #0]\n"
"cmp r1, #0\n"
"beq US_TICKER_HANDLER\n"
"bl OS_Tick_Handler\n"
"US_TICKER_HANDLER:\n"
"push {r3, lr}\n"
"bl us_ticker_handler\n"
"pop {r3, pc}\n"
"nop"
);
}
#else
#error Compiler not supported.
#error Provide a definition of RTC1_IRQHandler.
/*
* Chanel 1 of RTC1 is used by RTX as a systick.
* If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
* Otherwise, just execute us_ticker_handler.
* This function has to be written in assembly and tagged as naked because OS_Tick_Handler
* will never return.
* A c function would put lr on the stack before calling OS_Tick_Handler and this value
* will never been dequeued. After a certain time a stack overflow will happen.
*
* \code
* void RTC1_IRQHandler(void) {
if(NRF_RTC1->EVENTS_COMPARE[1]) {
// never return...
OS_Tick_Handler();
} else {
us_ticker_handler();
}
}
* \endcode
*/
#endif
/**
* Return the next number of clock cycle needed for the next tick.
* @note This function has been carrefuly optimized for a systick occuring every 1000us.
*/
static uint32_t get_next_tick_cc_delta() {
uint32_t delta = 0;
if (os_clockrate != 1000) {
// In RTX, by default SYSTICK is is used.
// A tick event is generated every os_trv + 1 clock cycles of the system timer.
delta = os_trv + 1;
} else {
// If the clockrate is set to 1000us then 1000 tick should happen every second.
// Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
// If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
// generated in 32000 clock cycle instead of 32768 clock cycles.
// As a result, if a user schedule an OS timer to start in 100s, the timer will start
// instead after 97.656s
// The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768
// clock cycles.
// The strategy is simple, for 1000 ticks:
// * 768 ticks will occur 33 clock cycles after the previous tick
// * 232 ticks will occur 32 clock cycles after the previous tick
// By default every delta is equal to 33.
// Every five ticks (20%, 200 delta in one second), the delta is equal to 32
// The remaining (32) deltas equal to 32 are distributed using primes numbers.
static uint32_t counter = 0;
if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) {
delta = 32;
} else {
delta = 33;
}
++counter;
if (counter == 1000) {
counter = 0;
}
}
return delta;
}
static inline void clear_tick_interrupt() {
NRF_RTC1->EVENTS_COMPARE[1] = 0;
NRF_RTC1->EVTENCLR = (1 << 17);
}
/**
* Indicate if a value is included in a range which can be wrapped.
* @param begin start of the range
* @param end end of the range
* @param val value to check
* @return true if the value is included in the range and false otherwise.
*/
static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) {
// regular case, begin < end
// return true if begin <= val < end
if (begin < end) {
if (begin <= val && val < end) {
return true;
} else {
return false;
}
} else {
// In this case end < begin because it has wrap around the limits
// return false if end < val < begin
if (end < val && val < begin) {
return false;
} else {
return true;
}
}
}
/**
* Register the next tick.
*/
static void register_next_tick() {
previous_tick_cc_value = NRF_RTC1->CC[1];
uint32_t delta = get_next_tick_cc_delta();
uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL;
// Disable irq directly for few cycles,
// Validation of the new CC value against the COUNTER,
// Setting the new CC value and enabling CC IRQ should be an atomic operation
// Otherwise, there is a possibility to set an invalid CC value because
// the RTC1 keeps running.
// This code is very short 20-38 cycles in the worst case, it shouldn't
// disturb softdevice.
__disable_irq();
uint32_t current_counter = NRF_RTC1->COUNTER;
// If an overflow occur, set the next tick in COUNTER + delta clock cycles
if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter) == false) {
new_compare_value = current_counter + delta;
}
NRF_RTC1->CC[1] = new_compare_value;
// set the interrupt of CC channel 1 and reenable IRQs
NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE1_Msk;
__enable_irq();
}
/**
* Initialize alternative hardware timer as RTX kernel timer
* This function is directly called by RTX.
* @note this function shouldn't be called directly.
* @return IRQ number of the alternative hardware timer
*/
int os_tick_init (void)
{
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
NRF_CLOCK->TASKS_LFCLKSTART = 1;
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
// wait for the low frequency clock start
}
NRF_RTC1->PRESCALER = 0; /* for no pre-scaling. */
NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI);
NVIC_ClearPendingIRQ(RTC1_IRQn);
NVIC_EnableIRQ(RTC1_IRQn);
NRF_RTC1->TASKS_START = 1;
nrf_delay_us(MAX_RTC_TASKS_DELAY);
NRF_RTC1->CC[1] = 0;
clear_tick_interrupt();
register_next_tick();
os_tick_started = true;
return RTC1_IRQn;
}
/**
* Acknowledge the tick interrupt.
* This function is called by the function OS_Tick_Handler of RTX.
* @note this function shouldn't be called directly.
*/
void os_tick_irqack(void)
{
clear_tick_interrupt();
register_next_tick();
}
/**
* Returns the overflow flag of the alternative hardware timer.
* @note This function is exposed by RTX kernel.
* @return 1 if the timer has overflowed and 0 otherwise.
*/
uint32_t os_tick_ovf(void) {
uint32_t current_counter = NRF_RTC1->COUNTER;
uint32_t next_tick_cc_value = NRF_RTC1->CC[1];
return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1;
}
/**
* Return the value of the alternative hardware timer.
* @note The documentation is not very clear about what is expected as a result,
* is it an ascending counter, a descending one ?
* None of this is specified.
* The default systick is a descending counter and this function return values in
* descending order, even if the internal counter used is an ascending one.
* @return the value of the alternative hardware timer.
*/
uint32_t os_tick_val(void) {
uint32_t current_counter = NRF_RTC1->COUNTER;
uint32_t next_tick_cc_value = NRF_RTC1->CC[1];
// do not use os_tick_ovf because its counter value can be different
if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) {
if (next_tick_cc_value > previous_tick_cc_value) {
return next_tick_cc_value - current_counter;
} else if(current_counter <= next_tick_cc_value) {
return next_tick_cc_value - current_counter;
} else {
return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter);
}
} else {
// use (os_trv + 1) has the base step, can be totally inacurate ...
uint32_t clock_cycles_by_tick = os_trv + 1;
// if current counter has wrap arround, add the limit to it.
if (current_counter < next_tick_cc_value) {
current_counter = current_counter + MAX_RTC_COUNTER_VAL;
}
return clock_cycles_by_tick - ((current_counter - next_tick_cc_value) % clock_cycles_by_tick);
}
return 0;
}

58
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/PeripheralNames.h
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@ -1,58 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STDIO_UART_TX TX_PIN_NUMBER
#define STDIO_UART_RX RX_PIN_NUMBER
#define STDIO_UART UART_0
typedef enum {
UART_0 = (int)NRF_UART0_BASE
} UARTName;
typedef enum {
SPI_0 = (int)NRF_SPI0_BASE,
SPI_1 = (int)NRF_SPI1_BASE,
SPIS = (int)NRF_SPIS1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2
} PWMName;
typedef enum {
I2C_0 = (int)NRF_TWI0_BASE,
I2C_1 = (int)NRF_TWI1_BASE
} I2CName;
typedef enum {
ADC0_0 = (int)0
} ADCName;
#ifdef __cplusplus
}
#endif
#endif

59
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/TARGET_NRF52_DK/device.h
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@ -1,59 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 0
#define DEVICE_SERIAL 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 0
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CAN 0
#define DEVICE_RTC 0
#define DEVICE_ETHERNET 0
#define DEVICE_PWMOUT 1
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_SLEEP 1
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 0
#define DEVICE_ERROR_PATTERN 1
#define DEVICE_LOWPOWERTIMER 1
#include "objects.h"
#endif

82
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/analogin_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#define ANALOGIN_MEDIAN_FILTER 1
#define ADC_10BIT_RANGE 0x3FF
#define ADC_RANGE ADC_10BIT_RANGE
static const PinMap PinMap_ADC[] = {
{p1, ADC0_0, 4},
{p2, ADC0_0, 8},
{p3, ADC0_0, 16},
{p4, ADC0_0, 32},
{p5, ADC0_0, 64},
{p6, ADC0_0, 128},
{NC, NC, 0}
};
void analogin_init(analogin_t *obj, PinName pin)
{
// TODO: usage on nrf52 ?
#if 0
int analogInputPin = 0;
const PinMap *map = PinMap_ADC;
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); //(NRF_ADC_Type *)
MBED_ASSERT(obj->adc != (ADCName)NC);
while (map->pin != NC) {
if (map->pin == pin) {
analogInputPin = map->function;
break;
}
map++;
}
obj->adc_pin = (uint8_t)analogInputPin;
NRF_ADC->ENABLE = ADC_ENABLE_ENABLE_Enabled;
NRF_ADC->CONFIG = (ADC_CONFIG_RES_10bit << ADC_CONFIG_RES_Pos) |
(ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling << ADC_CONFIG_INPSEL_Pos) |
(ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling << ADC_CONFIG_REFSEL_Pos) |
(analogInputPin << ADC_CONFIG_PSEL_Pos) |
(ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos);
#endif
}
uint16_t analogin_read_u16(analogin_t *obj)
{
// TODO: usage on nrf52 ?
#if 0
NRF_ADC->CONFIG &= ~ADC_CONFIG_PSEL_Msk;
NRF_ADC->CONFIG |= obj->adc_pin << ADC_CONFIG_PSEL_Pos;
NRF_ADC->TASKS_START = 1;
while (((NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) >> ADC_BUSY_BUSY_Pos) == ADC_BUSY_BUSY_Busy) {
}
return (uint16_t)NRF_ADC->RESULT; // 10 bit
#endif
return 0;
}
float analogin_read(analogin_t *obj)
{
uint16_t value = analogin_read_u16(obj);
return (float)value * (1.0f / (float)ADC_RANGE);
}

58
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/gpio_api.c
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@ -1,58 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "gpio_api.h"
#include "pinmap.h"
void gpio_init(gpio_t *obj, PinName pin)
{
obj->pin = pin;
if (pin == (PinName)NC) {
return;
}
obj->mask = (1ul << pin);
obj->reg_set = &NRF_GPIO->OUTSET;
obj->reg_clr = &NRF_GPIO->OUTCLR;
obj->reg_in = &NRF_GPIO->IN;
obj->reg_dir = &NRF_GPIO->DIR;
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
{
MBED_ASSERT(obj->pin != (PinName)NC);
switch (direction) {
case PIN_INPUT:
NRF_GPIO->PIN_CNF[obj->pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
break;
case PIN_OUTPUT:
NRF_GPIO->PIN_CNF[obj->pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
break;
}
}

127
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/gpio_irq_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "mbed_error.h"
#define CHANNEL_NUM 31
static uint32_t channel_ids[CHANNEL_NUM] = {0}; //each pin will be given an id, if id is 0 the pin can be ignored.
static uint8_t channel_enabled[CHANNEL_NUM] = {0};
static uint32_t portRISE = 0;
static uint32_t portFALL = 0;
static gpio_irq_handler irq_handler;
#ifdef __cplusplus
extern "C" {
#endif
void GPIOTE_IRQHandler(void)
{
volatile uint32_t newVal = NRF_GPIO->IN;
if ((NRF_GPIOTE->EVENTS_PORT != 0) && ((NRF_GPIOTE->INTENSET & GPIOTE_INTENSET_PORT_Msk) != 0)) {
NRF_GPIOTE->EVENTS_PORT = 0;
for (uint8_t i = 0; i<31; i++) {
if (channel_ids[i]>0) {
if (channel_enabled[i]) {
if( ((newVal>>i)&1) && ( ( (NRF_GPIO->PIN_CNF[i] >>GPIO_PIN_CNF_SENSE_Pos) & GPIO_PIN_CNF_SENSE_Low) != GPIO_PIN_CNF_SENSE_Low) && ( (portRISE>>i)&1) ){
irq_handler(channel_ids[i], IRQ_RISE);
} else if ((((newVal >> i) & 1) == 0) &&
(((NRF_GPIO->PIN_CNF[i] >> GPIO_PIN_CNF_SENSE_Pos) & GPIO_PIN_CNF_SENSE_Low) == GPIO_PIN_CNF_SENSE_Low) &&
((portFALL >> i) & 1)) {
irq_handler(channel_ids[i], IRQ_FALL);
}
}
if (NRF_GPIO->PIN_CNF[i] & GPIO_PIN_CNF_SENSE_Msk) {
NRF_GPIO->PIN_CNF[i] &= ~(GPIO_PIN_CNF_SENSE_Msk);
if (newVal >> i & 1) {
NRF_GPIO->PIN_CNF[i] |= (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos);
} else {
NRF_GPIO->PIN_CNF[i] |= (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos);
}
}
}
}
}
}
#ifdef __cplusplus
}
#endif
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
if (pin == NC) {
return -1;
}
irq_handler = handler;
obj->ch = pin;
NRF_GPIOTE->EVENTS_PORT = 0;
channel_ids[pin] = id;
channel_enabled[pin] = 1;
NRF_GPIOTE->INTENSET = GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos;
NVIC_SetPriority(GPIOTE_IRQn, 3);
NVIC_EnableIRQ (GPIOTE_IRQn);
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
channel_ids[obj->ch] = 0;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
NRF_GPIO->PIN_CNF[obj->ch] &= ~(GPIO_PIN_CNF_SENSE_Msk);
if (enable) {
if (event == IRQ_RISE) {
portRISE |= (1 << obj->ch);
} else if (event == IRQ_FALL) {
portFALL |= (1 << obj->ch);
}
} else {
if (event == IRQ_RISE) {
portRISE &= ~(1 << obj->ch);
} else if (event == IRQ_FALL) {
portFALL &= ~(1 << obj->ch);
}
}
if (((portRISE >> obj->ch) & 1) || ((portFALL >> obj->ch) & 1)) {
if ((NRF_GPIO->IN >> obj->ch) & 1) {
NRF_GPIO->PIN_CNF[obj->ch] |= (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos); // | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos);
} else {
NRF_GPIO->PIN_CNF[obj->ch] |= (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos); //| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos);
}
}
}
void gpio_irq_enable(gpio_irq_t *obj)
{
channel_enabled[obj->ch] = 1;
}
void gpio_irq_disable(gpio_irq_t *obj)
{
channel_enabled[obj->ch] = 0;
}

311
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/i2c_api.c
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@ -1,311 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "mbed_error.h"
#include "i2c_api.h"
#include "cmsis.h"
#include "pinmap.h"
// nRF51822's I2C_0 and SPI_0 (I2C_1, SPI_1 and SPIS1) share the same address.
// They can't be used at the same time. So we use two global variable to track the usage.
// See nRF51822 address information at nRF51822_PS v2.0.pdf - Table 15 Peripheral instance reference
volatile i2c_spi_peripheral_t i2c0_spi0_peripheral = {0, 0, 0, 0};
volatile i2c_spi_peripheral_t i2c1_spi1_peripheral = {0, 0, 0, 0};
void i2c_interface_enable(i2c_t *obj)
{
obj->i2c->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
}
void twi_master_init(i2c_t *obj, PinName sda, PinName scl, int frequency)
{
NRF_GPIO->PIN_CNF[scl] = ((GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) |
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
(GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) |
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos));
NRF_GPIO->PIN_CNF[sda] = ((GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) |
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
(GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) |
(GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) |
(GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos));
obj->i2c->PSELSCL = scl;
obj->i2c->PSELSDA = sda;
// set default frequency at 100k
i2c_frequency(obj, frequency);
i2c_interface_enable(obj);
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
// Initialize variable to avoid compiler warnings
NRF_TWI_Type *i2c = (NRF_TWI_Type *)I2C_0;
if (i2c0_spi0_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_I2C &&
i2c0_spi0_peripheral.sda_mosi == (uint8_t)sda &&
i2c0_spi0_peripheral.scl_miso == (uint8_t)scl) {
// The I2C with the same pins is already initialized
i2c = (NRF_TWI_Type *)I2C_0;
obj->peripheral = 0x1;
} else if (i2c1_spi1_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_I2C &&
i2c1_spi1_peripheral.sda_mosi == (uint8_t)sda &&
i2c1_spi1_peripheral.scl_miso == (uint8_t)scl) {
// The I2C with the same pins is already initialized
i2c = (NRF_TWI_Type *)I2C_1;
obj->peripheral = 0x2;
} else if (i2c0_spi0_peripheral.usage == 0) {
i2c0_spi0_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_I2C;
i2c0_spi0_peripheral.sda_mosi = (uint8_t)sda;
i2c0_spi0_peripheral.scl_miso = (uint8_t)scl;
i2c = (NRF_TWI_Type *)I2C_0;
obj->peripheral = 0x1;
} else if (i2c1_spi1_peripheral.usage == 0) {
i2c1_spi1_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_I2C;
i2c1_spi1_peripheral.sda_mosi = (uint8_t)sda;
i2c1_spi1_peripheral.scl_miso = (uint8_t)scl;
i2c = (NRF_TWI_Type *)I2C_1;
obj->peripheral = 0x2;
} else {
// No available peripheral
error("No available I2C");
}
obj->i2c = i2c;
obj->scl = scl;
obj->sda = sda;
obj->i2c->EVENTS_ERROR = 0;
obj->i2c->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
// TODO: usage on nrf52 ?
// obj->i2c->POWER = 0;
for (int i = 0; i<100; i++) {
}
// TODO: usage on nrf52 ?
// obj->i2c->POWER = 1;
twi_master_init(obj, sda, scl, 100000);
}
void i2c_reset(i2c_t *obj)
{
obj->i2c->EVENTS_ERROR = 0;
obj->i2c->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos;
// TODO: usage on nrf52 ?
// obj->i2c->POWER = 0;
for (int i = 0; i<100; i++) {
}
// TODO: usage on nrf52 ?
// obj->i2c->POWER = 1;
twi_master_init(obj, obj->sda, obj->scl, obj->freq);
}
int i2c_start(i2c_t *obj)
{
int status = 0;
i2c_reset(obj);
obj->address_set = 0;
return status;
}
int i2c_stop(i2c_t *obj)
{
int timeOut = 100000;
obj->i2c->EVENTS_STOPPED = 0;
// write the stop bit
obj->i2c->TASKS_STOP = 1;
while (!obj->i2c->EVENTS_STOPPED) {
timeOut--;
if (timeOut<0) {
return 1;
}
}
obj->address_set = 0;
i2c_reset(obj);
return 0;
}
int i2c_do_write(i2c_t *obj, int value)
{
int timeOut = 100000;
obj->i2c->TXD = value;
while (!obj->i2c->EVENTS_TXDSENT) {
timeOut--;
if (timeOut<0) {
return 1;
}
}
obj->i2c->EVENTS_TXDSENT = 0;
return 0;
}
int i2c_do_read(i2c_t *obj, char *data, int last)
{
int timeOut = 100000;
if (last) {
// To trigger stop task when a byte is received,
// must be set before resume task.
obj->i2c->SHORTS = 2;
}
obj->i2c->TASKS_RESUME = 1;
while (!obj->i2c->EVENTS_RXDREADY) {
timeOut--;
if (timeOut<0) {
return 1;
}
}
obj->i2c->EVENTS_RXDREADY = 0;
*data = obj->i2c->RXD;
return 0;
}
void i2c_frequency(i2c_t *obj, int hz)
{
if (hz<250000) {
obj->freq = 100000;
obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K100 << TWI_FREQUENCY_FREQUENCY_Pos);
} else if (hz<400000) {
obj->freq = 250000;
obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K250 << TWI_FREQUENCY_FREQUENCY_Pos);
} else {
obj->freq = 400000;
obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K400 << TWI_FREQUENCY_FREQUENCY_Pos);
}
}
int checkError(i2c_t *obj)
{
if (obj->i2c->EVENTS_ERROR == 1) {
if (obj->i2c->ERRORSRC & TWI_ERRORSRC_ANACK_Msk) {
obj->i2c->EVENTS_ERROR = 0;
obj->i2c->TASKS_STOP = 1;
return I2C_ERROR_BUS_BUSY;
}
obj->i2c->EVENTS_ERROR = 0;
obj->i2c->TASKS_STOP = 1;
return I2C_ERROR_NO_SLAVE;
}
return 0;
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
int status, count, errorResult;
obj->i2c->ADDRESS = (address >> 1);
obj->i2c->SHORTS = 1; // to trigger suspend task when a byte is received
obj->i2c->EVENTS_RXDREADY = 0;
obj->i2c->TASKS_STARTRX = 1;
// Read in all except last byte
for (count = 0; count < (length - 1); count++) {
status = i2c_do_read(obj, &data[count], 0);
if (status) {
errorResult = checkError(obj);
i2c_reset(obj);
if (errorResult<0) {
return errorResult;
}
return count;
}
}
// read in last byte
status = i2c_do_read(obj, &data[length - 1], 1);
if (status) {
i2c_reset(obj);
return length - 1;
}
// If not repeated start, send stop.
if (stop) {
while (!obj->i2c->EVENTS_STOPPED) {
}
obj->i2c->EVENTS_STOPPED = 0;
}
return length;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
int status, errorResult;
obj->i2c->ADDRESS = (address >> 1);
obj->i2c->SHORTS = 0;
obj->i2c->TASKS_STARTTX = 1;
for (int i = 0; i<length; i++) {
status = i2c_do_write(obj, data[i]);
if (status) {
i2c_reset(obj);
errorResult = checkError(obj);
if (errorResult<0) {
return errorResult;
}
return i;
}
}
// If not repeated start, send stop.
if (stop) {
if (i2c_stop(obj)) {
return I2C_ERROR_NO_SLAVE;
}
}
return length;
}
int i2c_byte_read(i2c_t *obj, int last)
{
char data;
int status;
status = i2c_do_read(obj, &data, last);
if (status) {
i2c_reset(obj);
}
return data;
}
int i2c_byte_write(i2c_t *obj, int data)
{
int status = 0;
if (!obj->address_set) {
obj->address_set = 1;
obj->i2c->ADDRESS = (data >> 1);
if (data & 1) {
obj->i2c->EVENTS_RXDREADY = 0;
obj->i2c->SHORTS = 1;
obj->i2c->TASKS_STARTRX = 1;
} else {
obj->i2c->SHORTS = 0;
obj->i2c->TASKS_STARTTX = 1;
}
} else {
status = i2c_do_write(obj, data);
if (status) {
i2c_reset(obj);
}
}
return (1 - status);
}

89
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/objects.h
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@ -1,89 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#define I2C_SPI_PERIPHERAL_FOR_I2C 1
#define I2C_SPI_PERIPHERAL_FOR_SPI 2
typedef struct {
uint8_t usage; // I2C: 1, SPI: 2
uint8_t sda_mosi;
uint8_t scl_miso;
uint8_t sclk;
} i2c_spi_peripheral_t;
struct serial_s {
NRF_UART_Type *uart;
int index;
};
struct spi_s {
NRF_SPI_Type *spi;
NRF_SPIS_Type *spis;
uint8_t peripheral;
};
struct port_s {
__IO uint32_t *reg_cnf;
__IO uint32_t *reg_out;
__I uint32_t *reg_in;
PortName port;
uint32_t mask;
};
struct pwmout_s {
PWMName pwm;
PinName pin;
};
struct i2c_s {
NRF_TWI_Type *i2c;
PinName sda;
PinName scl;
int freq;
uint8_t address_set;
uint8_t peripheral;
};
struct analogin_s {
ADCName adc;
uint8_t adc_pin;
};
struct gpio_irq_s {
uint32_t ch;
};
struct sleep_s {
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

85
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/port_api.c
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@ -1,85 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
PinName port_pin(PortName port, int pin_n)
{
(void) port;
return (PinName)(pin_n);
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
obj->port = port;
obj->mask = mask;
obj->reg_out = &NRF_GPIO->OUT;
obj->reg_in = &NRF_GPIO->IN;
obj->reg_cnf = NRF_GPIO->PIN_CNF;
port_dir(obj, dir);
}
void port_mode(port_t *obj, PinMode mode)
{
uint32_t i;
// The mode is set per pin: reuse pinmap logic
for (i = 0; i<31; i++) {
if (obj->mask & (1 << i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir)
{
int i;
switch (dir) {
case PIN_INPUT:
for (i = 0; i<31; i++) {
if (obj->mask & (1 << i)) {
obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
}
}
break;
case PIN_OUTPUT:
for (i = 0; i<31; i++) {
if (obj->mask & (1 << i)) {
obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
}
}
break;
}
}
void port_write(port_t *obj, int value)
{
*obj->reg_out = value;
}
int port_read(port_t *obj)
{
return (*obj->reg_in);
}

349
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/pwmout_api.c
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@ -1,349 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "mbed_error.h"
#include "pwmout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#define NO_PWMS 3
#define TIMER_PRECISION 4 //4us ticks
#define TIMER_PRESCALER 6 //4us ticks = 16Mhz/(2**6)
static const PinMap PinMap_PWM[] = {
{p0, PWM_1, 1},
{p1, PWM_1, 1},
{p2, PWM_1, 1},
{p3, PWM_1, 1},
{p4, PWM_1, 1},
{p5, PWM_1, 1},
{p6, PWM_1, 1},
{p7, PWM_1, 1},
{p8, PWM_1, 1},
{p9, PWM_1, 1},
{p10, PWM_1, 1},
{p11, PWM_1, 1},
{p12, PWM_1, 1},
{p13, PWM_1, 1},
{p14, PWM_1, 1},
{p15, PWM_1, 1},
{p16, PWM_1, 1},
{p17, PWM_1, 1},
{p18, PWM_1, 1},
{p19, PWM_1, 1},
{p20, PWM_1, 1},
{p21, PWM_1, 1},
{p22, PWM_1, 1},
{p23, PWM_1, 1},
{p24, PWM_1, 1},
{p25, PWM_1, 1},
{p28, PWM_1, 1},
{p29, PWM_1, 1},
{p30, PWM_1, 1},
{NC, NC, 0}
};
static NRF_TIMER_Type *Timers[1] = {
NRF_TIMER2
};
uint16_t PERIOD = 20000 / TIMER_PRECISION; //20ms
uint8_t PWM_taken[NO_PWMS] = {0, 0, 0};
uint16_t PULSE_WIDTH[NO_PWMS] = {1, 1, 1}; //set to 1 instead of 0
uint16_t ACTUAL_PULSE[NO_PWMS] = {0, 0, 0};
/** @brief Function for handling timer 2 peripheral interrupts.
*/
#ifdef __cplusplus
extern "C" {
#endif
void TIMER2_IRQHandler(void)
{
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
NRF_TIMER2->CC[3] = PERIOD;
if (PWM_taken[0]) {
NRF_TIMER2->CC[0] = PULSE_WIDTH[0];
}
if (PWM_taken[1]) {
NRF_TIMER2->CC[1] = PULSE_WIDTH[1];
}
if (PWM_taken[2]) {
NRF_TIMER2->CC[2] = PULSE_WIDTH[2];
}
NRF_TIMER2->TASKS_START = 1;
}
#ifdef __cplusplus
}
#endif
/** @brief Function for initializing the Timer peripherals.
*/
void timer_init(uint8_t pwmChoice)
{
NRF_TIMER_Type *timer = Timers[0];
timer->TASKS_STOP = 0;
if (pwmChoice == 0) {
// TODO: understand this for nrf52
// timer->POWER = 0;
// timer->POWER = 1;
timer->MODE = TIMER_MODE_MODE_Timer;
timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit << TIMER_BITMODE_BITMODE_Pos;
timer->PRESCALER = TIMER_PRESCALER;
timer->CC[3] = PERIOD;
}
timer->CC[pwmChoice] = PULSE_WIDTH[pwmChoice];
//high priority application interrupt
NVIC_SetPriority(TIMER2_IRQn, 1);
NVIC_EnableIRQ(TIMER2_IRQn);
timer->TASKS_START = 0x01;
}
/** @brief Function for initializing the GPIO Tasks/Events peripheral.
*/
void gpiote_init(PinName pin, uint8_t channel_number)
{
// Connect GPIO input buffers and configure PWM_OUTPUT_PIN_NUMBER as an output.
NRF_GPIO->PIN_CNF[pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_GPIO->OUTCLR = (1UL << pin);
// Configure GPIOTE channel 0 to toggle the PWM pin state
// @note Only one GPIOTE task can be connected to an output pin.
/* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */
NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
(31UL << GPIOTE_CONFIG_PSEL_Pos) |
(GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
/* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
__NOP();
__NOP();
__NOP();
/* Launch the task to take the GPIOTE channel output to the desired level */
NRF_GPIOTE->TASKS_OUT[channel_number] = 1;
/* Finally configure the channel as the caller expects. If OUTINIT works, the channel is configured properly.
If it does not, the channel output inheritance sets the proper level. */
NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
((uint32_t)pin << GPIOTE_CONFIG_PSEL_Pos) |
((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos) |
((uint32_t)GPIOTE_CONFIG_OUTINIT_Low << GPIOTE_CONFIG_OUTINIT_Pos); // ((uint32_t)GPIOTE_CONFIG_OUTINIT_High <<
// GPIOTE_CONFIG_OUTINIT_Pos);//
/* Three NOPs are required to make sure configuration is written before setting tasks or getting events */
__NOP();
__NOP();
__NOP();
}
/** @brief Function for initializing the Programmable Peripheral Interconnect peripheral.
*/
static void ppi_init(uint8_t pwm)
{
//using ppi channels 0-7 (only 0-7 are available)
uint8_t channel_number = 2 * pwm;
NRF_TIMER_Type *timer = Timers[0];
// Configure PPI channel 0 to toggle ADVERTISING_LED_PIN_NO on every TIMER1 COMPARE[0] match
NRF_PPI->CH[channel_number].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pwm];
NRF_PPI->CH[channel_number + 1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pwm];
NRF_PPI->CH[channel_number].EEP = (uint32_t)&timer->EVENTS_COMPARE[pwm];
NRF_PPI->CH[channel_number + 1].EEP = (uint32_t)&timer->EVENTS_COMPARE[3];
// Enable PPI channels.
NRF_PPI->CHEN |= (1 << channel_number) |
(1 << (channel_number + 1));
}
void setModulation(pwmout_t *obj, uint8_t toggle, uint8_t high)
{
if (high) {
NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos);
if (toggle) {
NRF_GPIOTE->CONFIG[obj->pwm] |= (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
} else {
NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos);
}
} else {
NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos);
if (toggle) {
NRF_GPIOTE->CONFIG[obj->pwm] |= (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) |
((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
} else {
NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos);
NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos);
}
}
}
void pwmout_init(pwmout_t *obj, PinName pin)
{
// determine the channel
uint8_t pwmOutSuccess = 0;
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
if (PWM_taken[(uint8_t)pwm]) {
for (uint8_t i = 1; !pwmOutSuccess && (i<NO_PWMS); i++) {
if (!PWM_taken[i]) {
pwm = (PWMName)i;
PWM_taken[i] = 1;
pwmOutSuccess = 1;
}
}
} else {
pwmOutSuccess = 1;
PWM_taken[(uint8_t)pwm] = 1;
}
if (!pwmOutSuccess) {
error("PwmOut pin mapping failed. All available PWM channels are in use.");
}
obj->pwm = pwm;
obj->pin = pin;
gpiote_init(pin, (uint8_t)pwm);
ppi_init((uint8_t)pwm);
if (pwm == 0) {
NRF_POWER->TASKS_CONSTLAT = 1;
}
timer_init((uint8_t)pwm);
//default to 20ms: standard for servos, and fine for e.g. brightness control
pwmout_period_ms(obj, 20);
pwmout_write (obj, 0);
}
void pwmout_free(pwmout_t *obj)
{
MBED_ASSERT(obj->pwm != (PWMName)NC);
PWM_taken[obj->pwm] = 0;
pwmout_write(obj, 0);
}
void pwmout_write(pwmout_t *obj, float value)
{
uint16_t oldPulseWidth;
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
NRF_TIMER2->TASKS_STOP = 1;
if (value < 0.0f) {
value = 0.0;
} else if (value > 1.0f) {
value = 1.0;
}
oldPulseWidth = ACTUAL_PULSE[obj->pwm];
ACTUAL_PULSE[obj->pwm] = PULSE_WIDTH[obj->pwm] = value * PERIOD;
if (PULSE_WIDTH[obj->pwm] == 0) {
PULSE_WIDTH[obj->pwm] = 1;
setModulation(obj, 0, 0);
} else if (PULSE_WIDTH[obj->pwm] == PERIOD) {
PULSE_WIDTH[obj->pwm] = PERIOD - 1;
setModulation(obj, 0, 1);
} else if ((oldPulseWidth == 0) || (oldPulseWidth == PERIOD)) {
setModulation(obj, 1, oldPulseWidth == PERIOD);
}
NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk;
NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk;
NRF_TIMER2->TASKS_START = 1;
}
float pwmout_read(pwmout_t *obj)
{
return ((float)PULSE_WIDTH[obj->pwm] / (float)PERIOD);
}
void pwmout_period(pwmout_t *obj, float seconds)
{
pwmout_period_us(obj, seconds * 1000000.0f);
}
void pwmout_period_ms(pwmout_t *obj, int ms)
{
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t *obj, int us)
{
(void) obj; // Avoid compiler warnings
uint32_t periodInTicks = us / TIMER_PRECISION;
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
NRF_TIMER2->TASKS_STOP = 1;
if (periodInTicks>((1 << 16) - 1)) {
PERIOD = (1 << 16) - 1; //131ms
} else if (periodInTicks<5) {
PERIOD = 5;
} else {
PERIOD = periodInTicks;
}
NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk;
NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk;
NRF_TIMER2->TASKS_START = 1;
}
void pwmout_pulsewidth(pwmout_t *obj, float seconds)
{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
{
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t *obj, int us)
{
uint32_t pulseInTicks = us / TIMER_PRECISION;
uint16_t oldPulseWidth = ACTUAL_PULSE[obj->pwm];
NRF_TIMER2->EVENTS_COMPARE[3] = 0;
NRF_TIMER2->TASKS_STOP = 1;
ACTUAL_PULSE[obj->pwm] = PULSE_WIDTH[obj->pwm] = pulseInTicks;
if (PULSE_WIDTH[obj->pwm] == 0) {
PULSE_WIDTH[obj->pwm] = 1;
setModulation(obj, 0, 0);
} else if (PULSE_WIDTH[obj->pwm] == PERIOD) {
PULSE_WIDTH[obj->pwm] = PERIOD - 1;
setModulation(obj, 0, 1);
} else if ((oldPulseWidth == 0) || (oldPulseWidth == PERIOD)) {
setModulation(obj, 1, oldPulseWidth == PERIOD);
}
NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk;
NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk;
NRF_TIMER2->TASKS_START = 1;
}

305
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/serial_api.c
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@ -1,305 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
//#include <math.h>
#include <string.h>
#include "mbed_assert.h"
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define UART_NUM 1
static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
static const uint32_t acceptedSpeeds[17][2] = {
{1200, UART_BAUDRATE_BAUDRATE_Baud1200},
{2400, UART_BAUDRATE_BAUDRATE_Baud2400},
{4800, UART_BAUDRATE_BAUDRATE_Baud4800},
{9600, UART_BAUDRATE_BAUDRATE_Baud9600},
{14400, UART_BAUDRATE_BAUDRATE_Baud14400},
{19200, UART_BAUDRATE_BAUDRATE_Baud19200},
{28800, UART_BAUDRATE_BAUDRATE_Baud28800},
{31250, (0x00800000UL) /* 31250 baud */},
{38400, UART_BAUDRATE_BAUDRATE_Baud38400},
{57600, UART_BAUDRATE_BAUDRATE_Baud57600},
{76800, UART_BAUDRATE_BAUDRATE_Baud76800},
{115200, UART_BAUDRATE_BAUDRATE_Baud115200},
{230400, UART_BAUDRATE_BAUDRATE_Baud230400},
{250000, UART_BAUDRATE_BAUDRATE_Baud250000},
{460800, UART_BAUDRATE_BAUDRATE_Baud460800},
{921600, UART_BAUDRATE_BAUDRATE_Baud921600},
{1000000, UART_BAUDRATE_BAUDRATE_Baud1M}
};
int stdio_uart_inited = 0;
serial_t stdio_uart;
void serial_init(serial_t *obj, PinName tx, PinName rx) {
UARTName uart = UART_0;
obj->uart = (NRF_UART_Type *)uart;
//pin configurations --
NRF_GPIO->DIR |= (1 << tx); //TX_PIN_NUMBER);
NRF_GPIO->DIR |= (1 << RTS_PIN_NUMBER);
NRF_GPIO->DIR &= ~(1 << rx); //RX_PIN_NUMBER);
NRF_GPIO->DIR &= ~(1 << CTS_PIN_NUMBER);
// set default baud rate and format
serial_baud (obj, 9600);
serial_format(obj, 8, ParityNone, 1);
obj->uart->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos);
obj->uart->TASKS_STARTTX = 1;
obj->uart->TASKS_STARTRX = 1;
obj->uart->EVENTS_RXDRDY = 0;
// dummy write needed or TXDRDY trails write rather than leads write.
// pins are disconnected so nothing is physically transmitted on the wire
obj->uart->TXD = 0;
obj->index = 0;
obj->uart->PSELRTS = RTS_PIN_NUMBER;
obj->uart->PSELTXD = tx; //TX_PIN_NUMBER;
obj->uart->PSELCTS = CTS_PIN_NUMBER;
obj->uart->PSELRXD = rx; //RX_PIN_NUMBER;
// set rx/tx pins in PullUp mode
if (tx != NC) {
pin_mode(tx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
if (uart == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
serial_irq_ids[obj->index] = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate)
{
if (baudrate<=1200) {
obj->uart->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1200;
return;
}
for (int i = 1; i<17; i++) {
if (baudrate<acceptedSpeeds[i][0]) {
obj->uart->BAUDRATE = acceptedSpeeds[i - 1][1];
return;
}
}
obj->uart->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1M;
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
/* Avoid compiler warnings */
(void) data_bits;
(void) stop_bits;
// 0: 1 stop bits, 1: 2 stop bits
// int parity_enable, parity_select;
switch (parity) {
case ParityNone:
obj->uart->CONFIG = 0;
break;
default:
obj->uart->CONFIG = (UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos);
return;
}
//no Flow Control
}
//******************************************************************************
// * INTERRUPT HANDLING
//******************************************************************************
static inline void uart_irq(uint32_t iir, uint32_t index)
{
SerialIrq irq_type;
switch (iir) {
case 1:
irq_type = TxIrq;
break;
case 2:
irq_type = RxIrq;
break;
default:
return;
}
if (serial_irq_ids[index] != 0) {
irq_handler(serial_irq_ids[index], irq_type);
}
}
#ifdef __cplusplus
extern "C" {
#endif
void UART0_IRQHandler()
{
uint32_t irtype = 0;
if((NRF_UART0->INTENSET & 0x80) && NRF_UART0->EVENTS_TXDRDY) {
irtype = 1;
} else if((NRF_UART0->INTENSET & 0x04) && NRF_UART0->EVENTS_RXDRDY) {
irtype = 2;
}
uart_irq(irtype, 0);
}
#ifdef __cplusplus
}
#endif
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
switch ((int)obj->uart) {
case UART_0:
irq_n = UART0_IRQn;
break;
}
if (enable) {
switch (irq) {
case RxIrq:
obj->uart->INTENSET = (UART_INTENSET_RXDRDY_Msk);
break;
case TxIrq:
obj->uart->INTENSET = (UART_INTENSET_TXDRDY_Msk);
break;
}
NVIC_SetPriority(irq_n, 3);
NVIC_EnableIRQ(irq_n);
} else { // disable
// maseked writes to INTENSET dont disable and masked writes to
// INTENCLR seemed to clear the entire register, not bits.
// Added INTEN to memory map and seems to allow set and clearing of specific bits as desired
int all_disabled = 0;
switch (irq) {
case RxIrq:
obj->uart->INTENCLR = (UART_INTENCLR_RXDRDY_Msk);
all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_TXDRDY_Msk)) == 0;
break;
case TxIrq:
obj->uart->INTENCLR = (UART_INTENCLR_TXDRDY_Msk);
all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_RXDRDY_Msk)) == 0;
break;
}
if (all_disabled) {
NVIC_DisableIRQ(irq_n);
}
}
}
//******************************************************************************
//* READ/WRITE
//******************************************************************************
int serial_getc(serial_t *obj)
{
while (!serial_readable(obj)) {
}
obj->uart->EVENTS_RXDRDY = 0;
return (uint8_t)obj->uart->RXD;
}
void serial_putc(serial_t *obj, int c)
{
while (!serial_writable(obj)) {
}
obj->uart->EVENTS_TXDRDY = 0;
obj->uart->TXD = (uint8_t)c;
}
int serial_readable(serial_t *obj)
{
return (obj->uart->EVENTS_RXDRDY == 1);
}
int serial_writable(serial_t *obj)
{
return (obj->uart->EVENTS_TXDRDY == 1);
}
void serial_break_set(serial_t *obj)
{
obj->uart->TASKS_SUSPEND = 1;
}
void serial_break_clear(serial_t *obj)
{
obj->uart->TASKS_STARTTX = 1;
obj->uart->TASKS_STARTRX = 1;
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
if (type == FlowControlRTSCTS || type == FlowControlRTS) {
NRF_GPIO->DIR |= (1<<rxflow);
pin_mode(rxflow, PullUp);
obj->uart->PSELRTS = rxflow;
obj->uart->CONFIG |= 0x01; // Enable HWFC
}
if (type == FlowControlRTSCTS || type == FlowControlCTS) {
NRF_GPIO->DIR &= ~(1<<txflow);
pin_mode(txflow, PullUp);
obj->uart->PSELCTS = txflow;
obj->uart->CONFIG |= 0x01; // Enable HWFC;
}
if (type == FlowControlNone) {
obj->uart->PSELRTS = 0xFFFFFFFF; // Disable RTS
obj->uart->PSELCTS = 0xFFFFFFFF; // Disable CTS
obj->uart->CONFIG &= ~0x01; // Enable HWFC;
}
}
void serial_clear(serial_t *obj) {
/* Avoid compiler warnings */
(void) obj;
}

32
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/sleep.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "sleep_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
void sleep(void)
{
// ensure debug is disconnected if semihost is enabled....
NRF_POWER->TASKS_LOWPWR = 1;
// wait for interrupt
__WFE();
}
void deepsleep(void)
{
sleep();
// NRF_POWER->SYSTEMOFF=1;
}

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hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/spi_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//#include <math.h>
#include "mbed_assert.h"
#include "mbed_error.h"
#include "spi_api.h"
#include "cmsis.h"
#include "pinmap.h"
#define SPIS_MESSAGE_SIZE 1
volatile uint8_t m_tx_buf[SPIS_MESSAGE_SIZE] = {0};
volatile uint8_t m_rx_buf[SPIS_MESSAGE_SIZE] = {0};
// nRF51822's I2C_0 and SPI_0 (I2C_1, SPI_1 and SPIS1) share the same address.
// They can't be used at the same time. So we use two global variable to track the usage.
// See nRF51822 address information at nRF51822_PS v2.0.pdf - Table 15 Peripheral instance reference
extern volatile i2c_spi_peripheral_t i2c0_spi0_peripheral; // from i2c_api.c
extern volatile i2c_spi_peripheral_t i2c1_spi1_peripheral;
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
SPIName spi = SPI_0; // Initialize to avoid compiler warnings
if (ssel == NC && i2c0_spi0_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI &&
i2c0_spi0_peripheral.sda_mosi == (uint8_t)mosi &&
i2c0_spi0_peripheral.scl_miso == (uint8_t)miso &&
i2c0_spi0_peripheral.sclk == (uint8_t)sclk) {
// The SPI with the same pins is already initialized
spi = SPI_0;
obj->peripheral = 0x1;
} else if (ssel == NC && i2c1_spi1_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI &&
i2c1_spi1_peripheral.sda_mosi == (uint8_t)mosi &&
i2c1_spi1_peripheral.scl_miso == (uint8_t)miso &&
i2c1_spi1_peripheral.sclk == (uint8_t)sclk) {
// The SPI with the same pins is already initialized
spi = SPI_1;
obj->peripheral = 0x2;
} else if (i2c1_spi1_peripheral.usage == 0) {
i2c1_spi1_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI;
i2c1_spi1_peripheral.sda_mosi = (uint8_t)mosi;
i2c1_spi1_peripheral.scl_miso = (uint8_t)miso;
i2c1_spi1_peripheral.sclk = (uint8_t)sclk;
spi = SPI_1;
obj->peripheral = 0x2;
} else if (i2c0_spi0_peripheral.usage == 0) {
i2c0_spi0_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI;
i2c0_spi0_peripheral.sda_mosi = (uint8_t)mosi;
i2c0_spi0_peripheral.scl_miso = (uint8_t)miso;
i2c0_spi0_peripheral.sclk = (uint8_t)sclk;
spi = SPI_0;
obj->peripheral = 0x1;
} else {
// No available peripheral
error("No available SPI");
}
if (ssel==NC) {
obj->spi = (NRF_SPI_Type *)spi;
obj->spis = (NRF_SPIS_Type *)NC;
} else {
obj->spi = (NRF_SPI_Type *)NC;
obj->spis = (NRF_SPIS_Type *)spi;
}
//master
// TODO: understand implication of this on nrf52
// obj->spi->POWER = 0;
// obj->spi->POWER = 1;
//NRF_GPIO->DIR |= (1<<mosi);
NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
obj->spi->PSELMOSI = mosi;
NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
obj->spi->PSELSCK = sclk;
//NRF_GPIO->DIR &= ~(1<<miso);
NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
obj->spi->PSELMISO = miso;
obj->spi->EVENTS_READY = 0U;
// spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0, master
spi_frequency(obj, 1000000);
}
void spi_free(spi_t *obj)
{
(void) obj; // Avoid compiler warnings
}
static inline void spi_disable(spi_t *obj, int slave)
{
obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
}
static inline void spi_enable(spi_t *obj, int slave)
{
obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
uint32_t config_mode = 0;
spi_disable(obj, slave);
if (bits != 8) {
error("Only 8bits SPI supported");
}
switch (mode) {
case 0:
config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
break;
case 1:
config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
break;
case 2:
config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
break;
case 3:
config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
break;
default:
error("SPI format error");
break;
}
//obj->spi->CONFIG = (config_mode | (((order == SPI_MSB) ? SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst) << SPI_CONFIG_ORDER_Pos));
//default to msb first
if (slave) {
obj->spis->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
} else {
obj->spi->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
}
spi_enable(obj, slave);
}
void spi_frequency(spi_t *obj, int hz)
{
if ((int)obj->spi==NC) {
return;
}
spi_disable(obj, 0);
if (hz<250000) { //125Kbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K125;
} else if (hz<500000) { //250Kbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K250;
} else if (hz<1000000) { //500Kbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K500;
} else if (hz<2000000) { //1Mbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M1;
} else if (hz<4000000) { //2Mbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M2;
} else if (hz<8000000) { //4Mbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M4;
} else { //8Mbps
obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M8;
}
spi_enable(obj, 0);
}
static inline int spi_readable(spi_t *obj)
{
return (obj->spi->EVENTS_READY == 1);
}
static inline int spi_writeable(spi_t *obj)
{
return (obj->spi->EVENTS_READY == 0);
}
static inline int spi_read(spi_t *obj)
{
while (!spi_readable(obj)) {
}
obj->spi->EVENTS_READY = 0;
return (int)obj->spi->RXD;
}
int spi_master_write(spi_t *obj, int value)
{
while (!spi_writeable(obj)) {
}
obj->spi->TXD = (uint32_t)value;
return spi_read(obj);
}
//static inline int spis_writeable(spi_t *obj) {
// return (obj->spis->EVENTS_ACQUIRED==1);
//}
int spi_slave_receive(spi_t *obj)
{
return obj->spis->EVENTS_END;
}
int spi_slave_read(spi_t *obj)
{
(void) obj; // Avoid compiler warnings
return m_rx_buf[0];
}
void spi_slave_write(spi_t *obj, int value)
{
m_tx_buf[0] = value & 0xFF;
obj->spis->TASKS_RELEASE = 1;
obj->spis->EVENTS_ACQUIRED = 0;
obj->spis->EVENTS_END = 0;
}

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hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF52832/us_ticker.c
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include <stdbool.h>
#include "us_ticker_api.h"
#include "cmsis.h"
#include "PeripheralNames.h"
#include "nrf_delay.h"
/*
* Note: The micro-second timer API on the nRF51 platform is implemented using
* the RTC counter run at 32kHz (sourced from an external oscillator). This is
* a trade-off between precision and power. Running a normal 32-bit MCU counter
* at high frequency causes the average power consumption to rise to a few
* hundred micro-amps, which is prohibitive for typical low-power BLE
* applications.
* A 32kHz clock doesn't offer the precision needed for keeping u-second time,
* but we're assuming that this will not be a problem for the average user.
*/
#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */
#define RTC_CLOCK_FREQ (uint32_t)(32768)
#define RTC1_IRQ_PRI 3 /**< Priority of the RTC1 interrupt (used
* for checking for timeouts and executing
* timeout handlers). This must be the same
* as APP_IRQ_PRIORITY_LOW; taken from the
* Nordic SDK. */
#define MAX_RTC_TASKS_DELAY 47 /**< Maximum delay until an RTC task is executed. */
#define FUZZY_RTC_TICKS 2 /* RTC COMPARE occurs when a CC register is N and the RTC
* COUNTER value transitions from N-1 to N. If we're trying to
* setup a callback for a time which will arrive very shortly,
* there are limits to how short the callback interval may be for us
* to rely upon the RTC Compare trigger. If the COUNTER is N,
* writing N+2 to a CC register is guaranteed to trigger a COMPARE
* event at N+2. */
#define RTC_UNITS_TO_MICROSECONDS(RTC_UNITS) (((RTC_UNITS) * (uint64_t)1000000) / RTC_CLOCK_FREQ)
#define MICROSECONDS_TO_RTC_UNITS(MICROS) ((((uint64_t)(MICROS) * RTC_CLOCK_FREQ) + 999999) / 1000000)
static bool us_ticker_inited = false;
static volatile bool us_ticker_callbackPending = false;
static uint32_t us_ticker_callbackTimestamp;
volatile uint32_t overflowCount; /**< The number of times the 24-bit RTC counter has overflowed. */
static inline void rtc1_enableCompareInterrupt(void)
{
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk;
}
static inline void rtc1_disableCompareInterrupt(void)
{
NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk;
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
}
static inline void rtc1_enableOverflowInterrupt(void)
{
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
NRF_RTC1->INTENSET = RTC_INTENSET_OVRFLW_Msk;
}
static inline void rtc1_disableOverflowInterrupt(void)
{
NRF_RTC1->INTENCLR = RTC_INTENSET_OVRFLW_Msk;
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
}
static inline void invokeCallback(void)
{
us_ticker_callbackPending = false;
rtc1_disableCompareInterrupt();
us_ticker_irq_handler();
}
/**
* @brief Function for starting the RTC1 timer. The RTC timer is expected to
* keep running--some interrupts may be disabled temporarily.
*/
static void rtc1_start()
{
NRF_RTC1->PRESCALER = 0; /* for no pre-scaling. */
rtc1_enableOverflowInterrupt();
NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI);
NVIC_ClearPendingIRQ(RTC1_IRQn);
NVIC_EnableIRQ(RTC1_IRQn);
NRF_RTC1->TASKS_START = 1;
nrf_delay_us(MAX_RTC_TASKS_DELAY);
}
/**
* @brief Function for stopping the RTC1 timer. We don't expect to call this.
*/
void rtc1_stop(void)
{
NVIC_DisableIRQ(RTC1_IRQn);
rtc1_disableCompareInterrupt();
rtc1_disableOverflowInterrupt();
NRF_RTC1->TASKS_STOP = 1;
nrf_delay_us(MAX_RTC_TASKS_DELAY);
NRF_RTC1->TASKS_CLEAR = 1;
nrf_delay_us(MAX_RTC_TASKS_DELAY);
}
/**
* @brief Function for returning the current value of the RTC1 counter.
*
* @return Current RTC1 counter as a 64-bit value with 56-bit precision (even
* though the underlying counter is 24-bit)
*/
static inline uint64_t rtc1_getCounter64(void)
{
if (NRF_RTC1->EVENTS_OVRFLW) {
overflowCount++;
NRF_RTC1->EVENTS_OVRFLW = 0;
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
}
return ((uint64_t)overflowCount << 24) | NRF_RTC1->COUNTER;
}
/**
* @brief Function for returning the current value of the RTC1 counter.
*
* @return Current RTC1 counter as a 32-bit value (even though the underlying counter is 24-bit)
*/
uint32_t rtc1_getCounter(void)
{
return rtc1_getCounter64();
}
/**
* @brief Function for handling the RTC1 interrupt.
*
* @details Checks for timeouts, and executes timeout handlers for expired timers.
*/
void RTC1_IRQHandler(void)
{
if (NRF_RTC1->EVENTS_OVRFLW) {
overflowCount++;
NRF_RTC1->EVENTS_OVRFLW = 0;
NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk;
}
if (NRF_RTC1->EVENTS_COMPARE[0] && us_ticker_callbackPending && ((int)(us_ticker_callbackTimestamp - rtc1_getCounter()) <= 0)) {
NRF_RTC1->EVENTS_COMPARE[0] = 0;
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
invokeCallback();
}
if (NRF_RTC1->EVENTS_COMPARE[1]) {
// Compare[1] used by lp ticker
NRF_RTC1->EVENTS_COMPARE[1] = 0;
NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE1_Msk;
}
}
void us_ticker_init(void)
{
if (us_ticker_inited) {
return;
}
rtc1_start();
us_ticker_inited = true;
}
uint32_t us_ticker_read()
{
if (!us_ticker_inited) {
us_ticker_init();
}
/* Return a pseudo microsecond counter value. This is only as precise as the
* 32khz low-freq clock source, but could be adequate.*/
return RTC_UNITS_TO_MICROSECONDS(rtc1_getCounter64());
}
/**
* Setup the us_ticker callback interrupt to go at the given timestamp.
*
* @Note: Only one callback is pending at any time.
*
* @Note: If a callback is pending, and this function is called again, the new
* callback-time overrides the existing callback setting. It is the caller's
* responsibility to ensure that this function is called to setup a callback for
* the earliest timeout.
*
* @Note: If this function is used to setup an interrupt which is immediately
* pending--such as for 'now' or a time in the past,--then the callback is
* invoked a few ticks later.
*/
void us_ticker_set_interrupt(timestamp_t timestamp)
{
if (!us_ticker_inited) {
us_ticker_init();
}
/*
* The argument to this function is a 32-bit microsecond timestamp for when
* a callback should be invoked. On the nRF51, we use an RTC timer running
* at 32kHz to implement a low-power us-ticker. This results in a problem
* based on the fact that 1000000 is not a multiple of 32768.
*
* Going from a micro-second based timestamp to a 32kHz based RTC-time is a
* linear mapping; but this mapping doesn't preserve wraparounds--i.e. when
* the 32-bit micro-second timestamp wraps around unfortunately the
* underlying RTC counter doesn't. The result is that timestamp expiry
* checks on micro-second timestamps don't yield the same result when
* applied on the corresponding RTC timestamp values.
*
* One solution is to translate the incoming 32-bit timestamp into a virtual
* 64-bit timestamp based on the knowledge of system-uptime, and then use
* this wraparound-free 64-bit value to do a linear mapping to RTC time.
* System uptime on an nRF is maintained using the 24-bit RTC counter. We
* track the overflow count to extend the 24-bit hardware counter by an
* additional 32 bits. RTC_UNITS_TO_MICROSECONDS() converts this into
* microsecond units (in 64-bits).
*/
const uint64_t currentTime64 = RTC_UNITS_TO_MICROSECONDS(rtc1_getCounter64());
uint64_t timestamp64 = (currentTime64 & ~(uint64_t)0xFFFFFFFFULL) + timestamp;
if (((uint32_t)currentTime64 > 0x80000000) && (timestamp < 0x80000000)) {
timestamp64 += (uint64_t)0x100000000ULL;
}
uint32_t newCallbackTime = MICROSECONDS_TO_RTC_UNITS(timestamp64);
/* Check for repeat setup of an existing callback. This is actually not
* important; the following code should work even without this check. */
if (us_ticker_callbackPending && (newCallbackTime == us_ticker_callbackTimestamp)) {
return;
}
/* Check for callbacks which are immediately (or will *very* shortly become) pending.
* Even if they are immediately pending, they are scheduled to trigger a few
* ticks later. This keeps things simple by invoking the callback from an
* independent interrupt context. */
if ((int)(newCallbackTime - rtc1_getCounter()) <= (int)FUZZY_RTC_TICKS) {
newCallbackTime = rtc1_getCounter() + FUZZY_RTC_TICKS;
}
NRF_RTC1->CC[0] = newCallbackTime & MAX_RTC_COUNTER_VAL;
us_ticker_callbackTimestamp = newCallbackTime;
if (!us_ticker_callbackPending) {
us_ticker_callbackPending = true;
rtc1_enableCompareInterrupt();
}
}
void us_ticker_disable_interrupt(void)
{
if (us_ticker_callbackPending) {
rtc1_disableCompareInterrupt();
us_ticker_callbackPending = false;
}
}
void us_ticker_clear_interrupt(void)
{
NRF_RTC1->EVENTS_OVRFLW = 0;
NRF_RTC1->EVENTS_COMPARE[0] = 0;
}

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hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/PeripheralNames.h Normal file
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/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STDIO_UART_TX TX_PIN_NUMBER
#define STDIO_UART_RX RX_PIN_NUMBER
#define STDIO_UART UART_0
typedef enum {
UART_0 = (int)NRF_UART0_BASE
} UARTName;
typedef enum {
SPI_0 = (int)NRF_SPI0_BASE,
SPI_1 = (int)NRF_SPI1_BASE,
SPIS = (int)NRF_SPIS1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2
} PWMName;
typedef enum {
I2C_0 = (int)NRF_TWI0_BASE,
I2C_1 = (int)NRF_TWI1_BASE
} I2CName;
typedef enum {
ADC0_0 = (int)NRF_ADC_BASE
} ADCName;
#ifdef __cplusplus
}
#endif
#endif

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hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/PortNames.h Normal file
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/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0 //GPIO pins 0-31
} PortName;
#ifdef __cplusplus
}
#endif
#endif

45
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_ARCH_BLE/PinNames.h → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_ARCH_BLE/PinNames.h
View File

@ -1,18 +1,41 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* http://www.apache.org/licenses/LICENSE-2.0
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H

0
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_ARCH_BLE/device.h → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_ARCH_BLE/device.h
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153
hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h Normal file
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@ -0,0 +1,153 @@
/*
* Copyright (c) 2015 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
NC = (int)0xFFFFFFFF,
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
LED1 = p4,
LED2 = p5,
LED3 = p6,
LED4 = p13,
BUTTON0 = p16,
BUTTON1 = p17,
RX_PIN_NUMBER = p23,
TX_PIN_NUMBER = p25,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
SPI_PSELMOSI0 = p24,
SPI_PSELMISO0 = p29,
SPI_PSELSS0 = p30,
SPI_PSELSCK0 = p21,
SPIS_PSELMOSI = p24,
SPIS_PSELMISO = p29,
SPIS_PSELSS = p30,
SPIS_PSELSCK = p21,
I2C_SDA0 = p22,
I2C_SCL0 = p20,
A0 = p26,
A1 = p27,
A2 = p4,
A3 = p5,
A4 = p6,
SWIO = p19,
VERF0 = p0,
// SPI for controlling internal flash, don't use it.
FLASH_SPIMOSI = 15,
FLASH_SPIMISO = 9,
FLASH_SPICS = 28,
FLASH_SPICLK = 11,
// Not connected
CTS_PIN_NUMBER= NC,
RTS_PIN_NUMBER= NC,
SPI_PSELMOSI1 = NC,
SPI_PSELMISO1 = NC,
SPI_PSELSS1 = NC,
SPI_PSELSCK1 = NC,
A5 = NC
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

0
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h
View File

0
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c
View File

0
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c
View File

45
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/PinNames.h → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_HRM1017/PinNames.h
View File

@ -1,18 +1,41 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* http://www.apache.org/licenses/LICENSE-2.0
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H

0
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_HRM1017/device.h → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_HRM1017/device.h
View File

45
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_HRM1017/PinNames.h → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/PinNames.h
View File

@ -1,18 +1,41 @@
/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* http://www.apache.org/licenses/LICENSE-2.0
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H

0
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/device.h → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/device.h
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129
hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/PinNames.h Normal file
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@ -0,0 +1,129 @@
/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p5 = 5,
p8 = 8,
p9 = 9,
p11 = 11,
p12 = 12,
p15 = 15,
p16 = 16,
p18 = 18,
p20 = 20,
p21 = 21,
p24 = 24,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_5 = p5,
P0_8 = p8,
P0_9 = p9,
P0_11 = p11,
P0_12 = p12,
P0_15 = p15,
P0_16 = p16,
P0_18 = p18,
P0_20 = p20,
P0_21 = p21,
P0_24 = p24,
LED1 = p16,
LED2 = p12,
LED3 = p15,
LEDR = LED1,
LEDG = LED2,
LEDB = LED3,
BUTTON1 = p8,
BUTTON2 = p18,
RX_PIN_NUMBER = p21,
TX_PIN_NUMBER = p24,
CTS_PIN_NUMBER = p0,
RTS_PIN_NUMBER = p20,
SPI_PSELMOSI0 = p2,
SPI_PSELMISO0 = p5,
SPI_PSELSS0 = p1,
SPI_PSELSCK0 = p3,
I2C_SDA0 = p9,
I2C_SCL0 = p11,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

0
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/device.h → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/device.h
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173
hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_NRF51822_Y5_MBUG/PinNames.h Normal file
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@ -0,0 +1,173 @@
/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
p32 = 32,
p33 = 33,
p34 = 34,
p35 = 35,
// p31=31,
// Not connected
NC = (int)0xFFFFFFFF,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
LED = p30,
LED1 = p30,
LED2 = p0,
LED3 = p8,
LED4 = NC,
BUTTON1 = p29,
BUTTON2 = p17,
RX_PIN_NUMBER = p2,
TX_PIN_NUMBER = p3,
CTS_PIN_NUMBER = p11,
RTS_PIN_NUMBER = p21,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
SPIS_PSELMOSI = p12,
SPIS_PSELMISO = p6,
SPIS_PSELSCK = p9,
I2C_SDA0 = p17,
I2C_SCL0 = p18,
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

0
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_Y5_MBUG/device.h → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_NRF51822_Y5_MBUG/device.h
View File

45
hal/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_TY51822R3/PinNames.h → hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TARGET_NRF51_DK/PinNames.h
View File

@ -1,18 +1,41 @@
/* mbed Microcontroller Library
* Copyright (c) 2015 Nordic Semiconductor
/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* http://www.apache.org/licenses/LICENSE-2.0
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H

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