From 0d8d3e01dbd8398e0a2d641d8a15866219f2aee7 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Mon, 12 Feb 2018 15:49:13 +0100 Subject: [PATCH] STM32F4 Cube v1.19.0 update : ST HAL files Previous version was v1.16.0 --- .../device/Release_Notes_stm32f4xx_hal.html | 2210 ------------ .../TARGET_STM32F4/device/stm32_hal_legacy.h | 622 ++-- .../TARGET_STM32F4/device/stm32f4xx_hal.c | 128 +- .../TARGET_STM32F4/device/stm32f4xx_hal.h | 42 +- .../TARGET_STM32F4/device/stm32f4xx_hal_adc.c | 68 +- .../TARGET_STM32F4/device/stm32f4xx_hal_adc.h | 72 +- .../device/stm32f4xx_hal_adc_ex.c | 44 +- .../device/stm32f4xx_hal_adc_ex.h | 18 +- .../TARGET_STM32F4/device/stm32f4xx_hal_can.c | 3054 +++++++++-------- .../TARGET_STM32F4/device/stm32f4xx_hal_can.h | 765 ++--- .../device/stm32f4xx_hal_can_legacy.c | 1697 +++++++++ .../device/stm32f4xx_hal_can_legacy.h | 785 +++++ .../TARGET_STM32F4/device/stm32f4xx_hal_cec.c | 44 +- .../TARGET_STM32F4/device/stm32f4xx_hal_cec.h | 48 +- .../device/stm32f4xx_hal_conf.h | 9 +- .../device/stm32f4xx_hal_cortex.c | 26 +- .../device/stm32f4xx_hal_cortex.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_hal_crc.c | 24 +- .../TARGET_STM32F4/device/stm32f4xx_hal_crc.h | 12 +- .../device/stm32f4xx_hal_cryp.c | 626 ++-- .../device/stm32f4xx_hal_cryp.h | 66 +- .../device/stm32f4xx_hal_cryp_ex.c | 316 +- .../device/stm32f4xx_hal_cryp_ex.h | 6 +- .../TARGET_STM32F4/device/stm32f4xx_hal_dac.c | 70 +- .../TARGET_STM32F4/device/stm32f4xx_hal_dac.h | 38 +- .../device/stm32f4xx_hal_dac_ex.c | 38 +- .../device/stm32f4xx_hal_dac_ex.h | 2 - .../device/stm32f4xx_hal_dcmi.c | 56 +- .../device/stm32f4xx_hal_dcmi.h | 32 +- .../device/stm32f4xx_hal_dcmi_ex.c | 4 +- .../device/stm32f4xx_hal_dcmi_ex.h | 8 +- .../TARGET_STM32F4/device/stm32f4xx_hal_def.h | 13 +- .../device/stm32f4xx_hal_dfsdm.c | 398 +-- .../device/stm32f4xx_hal_dfsdm.h | 6 +- .../TARGET_STM32F4/device/stm32f4xx_hal_dma.c | 65 +- .../TARGET_STM32F4/device/stm32f4xx_hal_dma.h | 50 +- .../device/stm32f4xx_hal_dma2d.c | 154 +- .../device/stm32f4xx_hal_dma2d.h | 26 +- .../device/stm32f4xx_hal_dma_ex.c | 36 +- .../device/stm32f4xx_hal_dma_ex.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_hal_dsi.c | 1199 ++++--- .../TARGET_STM32F4/device/stm32f4xx_hal_dsi.h | 220 +- .../TARGET_STM32F4/device/stm32f4xx_hal_eth.c | 98 +- .../TARGET_STM32F4/device/stm32f4xx_hal_eth.h | 140 +- .../device/stm32f4xx_hal_flash.c | 58 +- .../device/stm32f4xx_hal_flash.h | 12 +- .../device/stm32f4xx_hal_flash_ex.c | 62 +- .../device/stm32f4xx_hal_flash_ex.h | 2 - .../device/stm32f4xx_hal_flash_ramfunc.c | 2 - .../device/stm32f4xx_hal_flash_ramfunc.h | 2 - .../device/stm32f4xx_hal_fmpi2c.c | 1165 ++++--- .../device/stm32f4xx_hal_fmpi2c.h | 249 +- .../device/stm32f4xx_hal_fmpi2c_ex.c | 47 +- .../device/stm32f4xx_hal_fmpi2c_ex.h | 17 +- .../device/stm32f4xx_hal_gpio.c | 32 +- .../device/stm32f4xx_hal_gpio.h | 12 +- .../device/stm32f4xx_hal_gpio_ex.h | 2 - .../device/stm32f4xx_hal_hash.c | 136 +- .../device/stm32f4xx_hal_hash.h | 8 +- .../device/stm32f4xx_hal_hash_ex.c | 120 +- .../device/stm32f4xx_hal_hash_ex.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_hal_hcd.c | 110 +- .../TARGET_STM32F4/device/stm32f4xx_hal_hcd.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_hal_i2c.c | 62 +- .../TARGET_STM32F4/device/stm32f4xx_hal_i2c.h | 28 +- .../device/stm32f4xx_hal_i2c_ex.c | 10 +- .../device/stm32f4xx_hal_i2c_ex.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_hal_i2s.c | 96 +- .../TARGET_STM32F4/device/stm32f4xx_hal_i2s.h | 22 +- .../device/stm32f4xx_hal_i2s_ex.c | 91 +- .../device/stm32f4xx_hal_i2s_ex.h | 21 +- .../device/stm32f4xx_hal_irda.c | 94 +- .../device/stm32f4xx_hal_irda.h | 40 +- .../device/stm32f4xx_hal_iwdg.c | 2 - .../device/stm32f4xx_hal_iwdg.h | 2 - .../device/stm32f4xx_hal_lptim.c | 122 +- .../device/stm32f4xx_hal_lptim.h | 40 +- .../device/stm32f4xx_hal_ltdc.c | 2 - .../device/stm32f4xx_hal_ltdc.h | 2 - .../device/stm32f4xx_hal_ltdc_ex.c | 2 - .../device/stm32f4xx_hal_ltdc_ex.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_hal_mmc.c | 152 +- .../TARGET_STM32F4/device/stm32f4xx_hal_mmc.h | 26 +- .../device/stm32f4xx_hal_nand.c | 114 +- .../device/stm32f4xx_hal_nand.h | 14 +- .../TARGET_STM32F4/device/stm32f4xx_hal_nor.c | 83 +- .../TARGET_STM32F4/device/stm32f4xx_hal_nor.h | 22 +- .../device/stm32f4xx_hal_pccard.c | 56 +- .../device/stm32f4xx_hal_pccard.h | 4 +- .../TARGET_STM32F4/device/stm32f4xx_hal_pcd.c | 220 +- .../TARGET_STM32F4/device/stm32f4xx_hal_pcd.h | 6 +- .../device/stm32f4xx_hal_pcd_ex.c | 30 +- .../device/stm32f4xx_hal_pcd_ex.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_hal_pwr.c | 26 +- .../TARGET_STM32F4/device/stm32f4xx_hal_pwr.h | 18 +- .../device/stm32f4xx_hal_pwr_ex.c | 10 +- .../device/stm32f4xx_hal_pwr_ex.h | 22 +- .../device/stm32f4xx_hal_qspi.c | 140 +- .../device/stm32f4xx_hal_qspi.h | 28 +- .../TARGET_STM32F4/device/stm32f4xx_hal_rcc.c | 557 +-- .../TARGET_STM32F4/device/stm32f4xx_hal_rcc.h | 251 +- .../device/stm32f4xx_hal_rcc_ex.c | 1600 +++++---- .../device/stm32f4xx_hal_rcc_ex.h | 223 +- .../TARGET_STM32F4/device/stm32f4xx_hal_rng.c | 40 +- .../TARGET_STM32F4/device/stm32f4xx_hal_rng.h | 28 +- .../TARGET_STM32F4/device/stm32f4xx_hal_rtc.c | 94 +- .../TARGET_STM32F4/device/stm32f4xx_hal_rtc.h | 40 +- .../device/stm32f4xx_hal_rtc_ex.c | 132 +- .../device/stm32f4xx_hal_rtc_ex.h | 98 +- .../TARGET_STM32F4/device/stm32f4xx_hal_sai.c | 153 +- .../TARGET_STM32F4/device/stm32f4xx_hal_sai.h | 24 +- .../device/stm32f4xx_hal_sai_ex.c | 6 +- .../device/stm32f4xx_hal_sai_ex.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_hal_sd.c | 146 +- .../TARGET_STM32F4/device/stm32f4xx_hal_sd.h | 26 +- .../device/stm32f4xx_hal_sdram.c | 106 +- .../device/stm32f4xx_hal_sdram.h | 4 +- .../device/stm32f4xx_hal_smartcard.c | 92 +- .../device/stm32f4xx_hal_smartcard.h | 44 +- .../device/stm32f4xx_hal_spdifrx.c | 94 +- .../device/stm32f4xx_hal_spdifrx.h | 26 +- .../TARGET_STM32F4/device/stm32f4xx_hal_spi.c | 180 +- .../TARGET_STM32F4/device/stm32f4xx_hal_spi.h | 34 +- .../device/stm32f4xx_hal_sram.c | 88 +- .../device/stm32f4xx_hal_sram.h | 4 +- .../TARGET_STM32F4/device/stm32f4xx_hal_tim.c | 380 +- .../TARGET_STM32F4/device/stm32f4xx_hal_tim.h | 100 +- .../device/stm32f4xx_hal_tim_ex.c | 154 +- .../device/stm32f4xx_hal_tim_ex.h | 2 - .../device/stm32f4xx_hal_uart.c | 124 +- .../device/stm32f4xx_hal_uart.h | 52 +- .../device/stm32f4xx_hal_usart.c | 153 +- .../device/stm32f4xx_hal_usart.h | 38 +- .../device/stm32f4xx_hal_wwdg.c | 4 +- .../device/stm32f4xx_hal_wwdg.h | 18 +- .../TARGET_STM32F4/device/stm32f4xx_ll_adc.c | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_adc.h | 32 +- .../TARGET_STM32F4/device/stm32f4xx_ll_bus.h | 2 - .../device/stm32f4xx_ll_cortex.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_crc.c | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_crc.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_dac.c | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_dac.h | 6 +- .../TARGET_STM32F4/device/stm32f4xx_ll_dma.c | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_dma.h | 82 +- .../device/stm32f4xx_ll_dma2d.c | 14 +- .../device/stm32f4xx_ll_dma2d.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_exti.c | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_exti.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_fmc.c | 162 +- .../TARGET_STM32F4/device/stm32f4xx_ll_fmc.h | 110 +- .../TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c | 88 +- .../TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h | 62 +- .../TARGET_STM32F4/device/stm32f4xx_ll_gpio.c | 6 +- .../TARGET_STM32F4/device/stm32f4xx_ll_gpio.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_i2c.c | 10 +- .../TARGET_STM32F4/device/stm32f4xx_ll_i2c.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_iwdg.h | 2 - .../device/stm32f4xx_ll_lptim.c | 2 - .../device/stm32f4xx_ll_lptim.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_pwr.c | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_pwr.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_rcc.c | 40 +- .../TARGET_STM32F4/device/stm32f4xx_ll_rcc.h | 39 +- .../TARGET_STM32F4/device/stm32f4xx_ll_rng.c | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_rng.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_rtc.c | 4 +- .../TARGET_STM32F4/device/stm32f4xx_ll_rtc.h | 6 +- .../device/stm32f4xx_ll_sdmmc.c | 114 +- .../device/stm32f4xx_ll_sdmmc.h | 50 +- .../TARGET_STM32F4/device/stm32f4xx_ll_spi.c | 4 +- .../TARGET_STM32F4/device/stm32f4xx_ll_spi.h | 2 - .../device/stm32f4xx_ll_system.h | 8 +- .../TARGET_STM32F4/device/stm32f4xx_ll_tim.c | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_tim.h | 10 +- .../device/stm32f4xx_ll_usart.c | 26 +- .../device/stm32f4xx_ll_usart.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_usb.c | 180 +- .../TARGET_STM32F4/device/stm32f4xx_ll_usb.h | 2 - .../device/stm32f4xx_ll_utils.c | 2 - .../device/stm32f4xx_ll_utils.h | 2 - .../TARGET_STM32F4/device/stm32f4xx_ll_wwdg.h | 2 - .../TARGET_STM32F4/device/system_stm32f4xx.c | 2 - .../{device => }/hal_init_pre.c | 2 + 184 files changed, 12210 insertions(+), 11008 deletions(-) delete mode 100644 targets/TARGET_STM/TARGET_STM32F4/device/Release_Notes_stm32f4xx_hal.html create mode 100644 targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.c create mode 100644 targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.h rename targets/TARGET_STM/TARGET_STM32F4/{device => }/hal_init_pre.c (96%) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/Release_Notes_stm32f4xx_hal.html b/targets/TARGET_STM/TARGET_STM32F4/device/Release_Notes_stm32f4xx_hal.html deleted file mode 100644 index b2626a4651..0000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/device/Release_Notes_stm32f4xx_hal.html +++ /dev/null @@ -1,2210 +0,0 @@ - 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Release Notes for STM32F4xx HAL Drivers

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Copyright - 2017 STMicroelectronics

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Update History

V1.7.1 / 14-April-2017

Main -Changes

- -
  • Update CHM UserManuals to support LL drivers
  • General updates -to fix known defects and enhancements implementation
  • HAL CAN update
    • Add - management of overrun error. 
    • Allow - possibility to receive messages from the 2 RX FIFOs in parallel via - interrupt.
    • Fix message - lost issue with specific sequence of transmit requests.
    • Handle - transmission failure with error callback, when NART is enabled.
    • Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when - timeout is reached
-
  • HAL PWR update
    • HAL_PWREx_EnterUnderDriveSTOPMode() API: remove check on UDRDY flag
-
  • LL ADC update
    • Fix wrong ADC group injected sequence configuration
      • LL_ADC_INJ_SetSequencerRanks() -and LL_ADC_INJ_GetSequencerRanks() API's update to take in -consideration the ADC number of conversions
      • Update the defined values for ADC group injected seqencer ranks 

V1.7.0 / 17-February-2017

Main -Changes

- -
  • Add Low Layer drivers allowing performance and footprint optimization
    • Low -Layer drivers APIs provide register level programming: require deep -knowledge of peripherals described in STM32F4xx Reference Manuals
    • Low -Layer drivers are available for: ADC, Cortex, CRC, DAC, DMA, -DMA2D, EXTI, GPIO, I2C, IWDG, LPTIM, PWR, RCC, RNG, RTC, SPI, TIM, -USART, WWDG peripherals and additionnal Low Level Bus, System and -Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f4xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f4xx_ll_ppp.h file must be included in user code.
  • General updates to fix known defects and enhancements implementation
  • Fix extra warnings with GCC compiler
  • HAL drivers clean up: remove double casting 'uint32_t' and 'U'
  • Add new HAL MMC driver
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
    • HAL SD update
      • Overall rework of the driver for a more efficient implementation
        • Modify initialization API and structures
        • Modify Read / Write sequences: separate transfer process and SD Cards state management 
        • Adding interrupt mode for Read / Write operations
        • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
      • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
    • HAL NAND update
      • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
      • Add new HAL_NAND_ConfigDevice API
    • HAL DFSDM update
      • Add support of Multichannel Delay feature
        • Add HAL_DFSDM_ConfigMultiChannelDelay API
        • The following APIs are moved to internal static functions: -HAL_DFSDM_ClockIn_SourceSelection, HAL_DFSDM_ClockOut_SourceSelection, -HAL_DFSDM_DataInX_SourceSelection (X=0,2,4,6), -HAL_DFSDM_BitStreamClkDistribution_Config
    • HAL I2S update
      • Add specific callback API to manage I2S full duplex end of transfer process:
        • HAL_I2S_TxCpltCallback() and -HAL_I2S_RxCpltCallback() API's will be replaced with only HAL_I2SEx_TxRxCpltCallback() API. 
  • HAL update
    • Modifiy default HAL_Delay implementation to guarantee minimum delay 
  • HAL Cortex update
    • Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f4xx_hal_cortex.h to stm32f4xx_hal_cortex.c
    • Clear the whole MPU control register in HAL_MPU_Disable() API
  • HAL FLASH update
    • IS_FLASH_ADDRESS() macro update to support OTP range
    • FLASH_Program_DoubleWord(): Replace 64-bit accesses with 2 double-words operations
  • LL GPIO update
    • Update IS_GPIO_PIN() macro implementation to be more safe
  • LL RCC update
    • Update IS_RCC_PLLQ_VALUE() macro implementation: the minimum accepted value is 2 instead of 4
    • Rename RCC_LPTIM1CLKSOURCE_PCLK define to RCC_LPTIM1CLKSOURCE_PCLK1
    • Fix -compilation issue w/ __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() and -__HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() macros for STM32F401xx devices
    • Add the following is clock enabled macros for STM32F401xx devices
      •  __HAL_RCC_SDIO_IS_CLK_ENABLED()
      • __HAL_RCC_SPI4_IS_CLK_ENABLED()
      • __HAL_RCC_TIM10_IS_CLK_ENABLED()
    • Add the following is clock enabled macros for STM32F410xx devices
      •  __HAL_RCC_CRC_IS_CLK_ENABLED()
      • __HAL_RCC_RNG_IS_CLK_ENABLED()
    • Update HAL_RCC_DeInit() to reset the RCC clock configuration to the default reset state.
    • Remove macros to configure BKPSRAM from STM32F401xx devices 
    • Update to refer to AHBPrescTable[] and APBPrescTable[] tables defined in system_stm32f4xx.c file instead of APBAHBPrescTable[] table.
  • HAL FMPI2C update
    • Add FMPI2C_FIRST_AND_NEXT_FRAME define in Sequential Transfer Options
  • HAL ADC update
    • HAL_ADCEx_InjectedConfigChannel(): update the external trigger injected condition
  • HAL DMA update
    • HAL_DMA_Init(): update to check compatibility between FIFO threshold level and size of the memory burst 
  • HAL QSPI update
    • QSPI_HandleTypeDef structure: Update transfer parameters on uint32_t instead of uint16_t
  • HAL UART/USART/IrDA/SMARTCARD update

    • DMA Receive process; the code -has been updated to clear the USART OVR flag before enabling DMA receive request.

    • UART_SetConfig() update to manage correctly USART6 instance that is not available on STM32F410Tx devices
  • HAL CAN update
    • Remove Lock mechanism from HAL_CAN_Transmit_IT() and HAL_CAN_Receive_IT() processes
  • HAL TIM update

    • Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() macro to disable Master output without check on TIM channel state. 

    • Update HAL_TIMEx_ConfigBreakDeadTime() to fix TIM BDTR register corruption.
  • HAL I2C update
    • Update -HAL_I2C_Master_Transmit() and HAL_I2C_Slave_Transmit() to avoid sending -extra bytes at the end of the transmit processes
    • Update - HAL_I2C_Mem_Read() API to fix wrong check on misused parameter “Size”
    • Update - I2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs to - enhance Master sequential reception process.
  • HAL SPI update
    • Add transfer abort APIs and associated callbacks in interrupt mode
      • HAL_SPI_Abort()
      • HAL_SPI_Abort_IT()
      • HAL_SPI_AbortCpltCallback()
  • HAL I2S update
    • Add specific callback API to manage I2S full duplex end of transfer process:
      • HAL_I2S_TxCpltCallback() and -HAL_I2S_RxCpltCallback() API's will be replaced with only HAL_I2SEx_TxRxCpltCallback() API. 
    • Update I2S Transmit/Receive polling process to manage Overrun and Underrun errors
    • Move -the I2S clock input frequency -calculation to HAL RCC driver.
    • Update the -HAL I2SEx driver to keep only full duplex feature.
    • HAL_I2S_Init() API updated to
      • Fix wrong I2S clock calculation when PCM mode is used.
      • Return state HAL_I2S_ERROR_PRESCALER when the I2S clock is wrongly configured
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  • HAL LTDC update
    • Optimize HAL_LTDC_IRQHandler() function by using direct register read
    • Rename the following API's
      • HAL_LTDC_Relaod() by HAL_LTDC_Reload() 
      • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
      • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
    • Add new defines for LTDC layers (LTDC_LAYER_1 / LTDC_LAYER_2)
    • Remove unused asserts
  • HAL USB PCD update
    • Flush all TX FIFOs on USB Reset
    • Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API's
  • LL USB update
    • Enable DMA Burst mode for USB OTG HS
    • Fix SD card detection issue
  • LL SDMMC update
    • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions

V1.6.0 / 04-November-2016

Main -Changes

- -
  • Add support of STM32F413xx and STM32F423xx devices
  • General updates to fix known defects and enhancements implementation
  • HAL CAN update
    • Update to add the support of 3 CAN management
  • HAL CRYP update
    • Update to add the support of AES features
  • HAL DFSDM update
    • Add definitions for new external trigger filters
    • Add definition for new Channels 4, 5, 6 and 7
    • Add functions and API for Filter state configuration and management
    • Add new functions: 
      • HAL_DFSDM_BitstreamClock_Start()
      • HAL_DFSDM_BitstreamClock_Stop()
      • HAL_DFSDM_BitStreamClkDistribution_Config() 
  • HAL DMA
    • Add the support of DMA Channels from 8 to 15
    • Update HAL_DMA_DeInit() function with the check on DMA stream instance
  • HAL DSI update
    • Update HAL_DSI_ConfigHostTimeouts() and HAL_DSI_Init() functions to avoid scratch in DSI_CCR register
  • HAL FLASH update
    • Enhance FLASH_WaitForLastOperation() function implementation
    • Update __HAL_FLASH_GET_FLAG() macro implementation
  • HAL GPIO update
    • Add specific alternate functions definitions
  • HAL I2C update
    • Update I2C_DMAError() function implementation to ignore DMA FIFO error
  • HAL I2S update
    • Enhance HAL_I2S_Init() implementation to test on PCM_SHORT and PCM_LONG standards
  • HAL IRDA update
    • Add new functions and call backs for Transfer Abort
      • HAL_IRDA_Abort()
      • HAL_IRDA_AbortTransmit()
      • HAL_IRDA_AbortReceive()
      • HAL_IRDA_Abort_IT()
      • HAL_IRDA_AbortTransmit_IT()
      • HAL_IRDA_AbortReceive_IT()
      • HAL_IRDA_AbortCpltCallback()
      • HAL_IRDA_AbortTransmitCpltCallback()
      • HAL_IRDA_AbortReceiveCpltCallback()
  • HAL PCD update
    • Update HAL_PCD_GetRxCount()  function implementation
  • HAL RCC update
    • Update __HAL_RCC_HSE_CONFIG() macro implementation
    • Update __HAL_RCC_LSE_CONFIG() macro implementation
  • HAL SMARTCARD update
    • Add new functions and call backs for Transfer Abort
      • HAL_ SMARTCARD_Abort()
      • HAL_ SMARTCARD_AbortTransmit()
      • HAL_ SMARTCARD_AbortReceive()
      • HAL_ SMARTCARD_Abort_IT()
      • HAL_ SMARTCARD_AbortTransmit_IT()
      • HAL_ SMARTCARD_AbortReceive_IT()
      • HAL_ SMARTCARD_AbortCpltCallback()
      • HAL_ SMARTCARD_AbortTransmitCpltCallback()
      • HAL_ SMARTCARD_AbortReceiveCpltCallback()
  • HAL TIM update
    • Update HAL_TIMEx_RemapConfig() function to manage TIM internal trigger remap: LPTIM or TIM3_TRGO
  • HAL UART update
    • Add Transfer abort functions and callbacks
  • HAL USART update
    • Add Transfer abort functions and callbacks

V1.5.2 / 22-September-2016

Main -Changes

- -
  • HAL I2C update
    • Fix wrong -behavior in consecutive transfers in case of single byte transmission (Master/Memory Receive
      interfaces)
    • Update HAL_I2C_Master_Transmit_DMA() / HAL_I2C_Master_Receive_DMA()/ HAL_I2C_Slave_Transmit_DMA()
      and HAL_I2C_Slave_Receive_DMA() to manage addressing phase through interruption instead of polling
    • Add a check on I2C handle state at start of all I2C API's to ensure that I2C is ready
    • - -

      Update I2C API's (Polling, IT and DMA interfaces) to manage I2C XferSize and XferCount handle parameters instead of API size parameter to help user to get information of counter in case of error. 

    • - -

      Update Abort functionality to manage DMA use -case

  • HAL FMPI2C update
    • Update to disable Own Address before setting the new Own Address configuration:
      • Update HAL_FMPI2C_Init() to disable FMPI2C_OARx_EN bit before any configuration in OARx registers
  • HAL CAN update
    • Update CAN receive processes to set CAN RxMsg FIFONumber parameter
  • HAL UART update
    • Update UART handle TxXferCount and RxXferCount parameters as volatile to avoid eventual issue with High Speed optimization  

V1.5.1 / 01-July-2016

Main -Changes

- -
  • HAL GPIO update
    • HAL_GPIO_Init()/HAL_GPIO_DeInit() API's: update GPIO_GET_INDEX() macro implementation to support all GPIO's
  • HAL SPI update
    • Fix regression issue: retore HAL_SPI_DMAPause() and HAL_SPI_DMAResume() API's
  • HAL RCC update
    • Fix FSMC macros compilation warnings with STM32F412Rx devices
  • HAL DMA update
    • HAL_DMA_PollFortransfer() API clean up
  • HAL PPP update(PPP refers to IRDA, UART, USART and SMARTCARD)
    • Update HAL_PPP_IRQHandler() to add a check on interrupt source before managing the error 
- - -
  • HAL QSPI update
    • Implement -workaround to fix the limitation pronounced in the Errata -sheet 2.1.8 section: In some specific cases, DMA2 data corruption -occurs when managing AHB and APB2 peripherals in a concurrent way

V1.5.0 / 06-May-2016

-

Main -Changes

- -
  • Add support of STM32F412cx, STM32F412rx, STM32F412vx and STM32F412zx devices
  • General updates to fix known defects and enhancements implementation
  • Add new HAL driver for DFSDM peripheral
  • - -Enhance HAL delay and time base implementation:
    • Add -new drivers stm32f4xx_hal_timebase_rtc_alarm_template.c and -stm32f4xx_hal_timebase_rtc_wakeup_template.c which override the native -HAL time base functions (defined as weak) to either use the RTC as time -base tick source. For more details about the usage of these drivers, -please refer to HAL\HAL_TimeBase_RTC examples and FreeRTOS-based applications
  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.4
    • HAL UART, USART, IRDA, SMARTCARD, SPI, I2C,FMPI2C, QSPI (referenced as PPP here below) drivers
      • Add PPP error management during DMA process. This requires the following updates on user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
    • HAL I2C, FMPI2C (referenced as PPP here below) drivers:
      • Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using the PPP end of transfer interrupt in the DMA transfer process. This requires the following updates on user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
    • HAL I2C driver:
      • I2C -transfer processes IT update: NACK during addressing phase is managed -through I2C Error interrupt instead of HAL state
    • HAL IWDG driver: rework overall driver for better implementation
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
    • HAL WWDG driver: rework overall driver for better implementation
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs 
      • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter)  function and API  by removing the  "counter" parameter
    • HAL QSPI driver:  Enhance the DMA transmit process by using PPP TC interrupt instead of waiting on TC flag under DMA ISR. This requires the following updates on user application:
      • Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function
      • In stm32f4xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function
    • HAL CEC driver:  Overall driver rework with compatibility break versus previous HAL version
      • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove -HAL CEC receive interrupt process function HAL_CEC_Receive_IT() -and enable the "receive"  mode during the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
  • HAL RCC update
    • Update HAL_RCC_ClockConfig() function to adjust the SystemCoreClock
    • Rename macros and Literals:
      • RCC_PERIPHCLK_CK48 by RCC_PERIPHCLK_CLK48
      • IS_RCC_CK48CLKSOURCE by IS_RCC_CLK48CLKSOURCE
      • RCC_CK48CLKSOURCE_PLLSAIP by RCC_CLK48CLKSOURCE_PLLSAIP
      • RCC_SDIOCLKSOURCE_CK48 by RCC_SDIOCLKSOURCE_CLK48
      • RCC_CK48CLKSOURCE_PLLQ by RCC_CLK48CLKSOURCE_PLLQ
    • Update HAL_RCCEx_GetPeriphCLKConfig() and HAL_RCCEx_PeriphCLKConfig() functions to support TIM Prescaler for STM32F411xx devices
    • HAL_RCCEx_PeriphCLKConfig() API: update to fix the RTC clock configuration issue
  • - -HAL CEC update
    • Overall driver rework with break of compatibility with HAL V1.4.4
      • Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' -field from the CEC_InitTypeDef structure and manage -it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • Update driver to implement the new CEC state machine:
      • Add new "rxState" field in CEC_HandleTypeDef structure to provide the CEC state information related to Rx Operations
      • Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC state information related to global Handle management and Tx Operations
      • Update CEC process to manage the new CEC states.
      • Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)
  • - -HAL UART, USART, SMARTCARD and IRDA (referenced as PPP here below) update -
    • Update Polling management:
      • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Update DMA process:
      • Update the management of PPP peripheral errors during DMA process. This requires the following updates in user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
  • HAL FMC update
    • Update FMC_NORSRAM_Init() to remove the Burst access mode configuration
    • Update FMC_SDRAM_Timing_Init() to fix initialization issue when configuring 2 SDRAM banks
  • HAL HCD update
    • Update HCD_Port_IRQHandler() to unmask disconnect IT only when the port is disabled
  • HAL I2C/FMPI2C update
    • Update Polling management:
      • The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Add the management of Abort service: Abort DMA transfer through interrupt
      • In the case of Master Abort IT transfer usage:
        • Add new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process
        • A new abort state is defined in the HAL_I2C_StateTypeDef structure
    • Add -the management of I2C peripheral errors, ACK failure and STOP condition -detection during DMA process. This requires the following updates on -user application:
      • Configure and enable the I2C IRQ in HAL_I2C_MspInit() function
      • In stm32f4xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function
      • Add and customize the Error Callback API: HAL_I2C_ErrorCallback()
      • Refer to the I2C_EEPROM or I2C_TwoBoards_ComDMA project examples usage of the API
    • NACK error during addressing phase is returned through interrupt instead of previously through I2C transfer API's
    • I2C addressing phase is updated to be managed -using interrupt instead of polling (Only for HAL I2C driver)
      • Add new static functions to manage I2C SB, ADDR and ADD10 flags
  • HAL SPI update
    • Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency
      • Polling mode:
        • Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" statement to check on RXNE/TXE flage while transferring data
      •  Interrupt mode:
        • Minimize access on SPI registers
      • All modes:
        • Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled
        • Update timeout management to check on global processes
        • Update error code management in all processes
    • Update DMA process:
      • Add the management of SPI peripheral errors during DMA process. This requires the following updates in the user application:
        • Configure and enable the SPI IRQ in HAL_SPI_MspInit() function
        • In stm32f4xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function
        • Add and customize the Error Callback API: HAL_SPI_ErrorCallback()
        • Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA
    • Fix regression in polling mode:
      • Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()
      • Add to manage properly the overrun flag at the end of a HAL_SPI_TransmitReceive()
    • Fix regression in interrupt mode:
      • Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()
      • Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()
  • HAL DMA2D update
    • Update the HAL_DMA2D_DeInit() function to:
      • Abort transfer in case of ongoing DMA2D transfer
      • Reset DMA2D control registers
    • Update HAL_DMA2D_Abort() to disable DMA2D interrupts after stopping transfer
    • Optimize HAL_DMA2D_IRQHandler() by reading status registers only once
    • Update HAL_DMA2D_ProgramLineEvent() function to:
      • Return HAL error state in case of wrong line value
      • Enable line interrupt after setting the line watermark configuration
    • Add new HAL_DMA2D_CLUTLoad() and HAL_DMA2D_CLUTLoad_IT() functions to start DMA2D CLUT loading
      • HAL_DMA2D_CLUTLoading_Abort() function to abort the DMA2D CLUT loading
      • HAL_DMA2D_CLUTLoading_Suspend() function to suspend the DMA2D CLUT loading
      • HAL_DMA2D_CLUTLoading_Resume() function to resume the DMA2D CLUT loading
    • Add new DMA2D dead time management:
      • HAL_DMA2D_EnableDeadTime() function to enable DMA2D dead time feature
      • HAL_DMA2D_DisableDeadTime() function to disable DMA2D dead time feature
      • HAL_DMA2D_ConfigDeadTime() function to configure dead time
    • Update -the name of DMA2D Input/Output color mode defines to be more clear for -user (DMA2D_INPUT_XXX for input layers Colors, DMA2D_OUTPUT_XXX for -output framebuffer Colors)
  • HAL LTDC update
    • Update HAL_LTDC_IRQHandler() to manage the case of reload interrupt
    • Add new callback API HAL_LTDC_ReloadEventCallback()
    • Add HAL_LTDC_Reload() to configure LTDC reload feature
    • Add new No Reload LTDC variant APIs
      • HAL_LTDC_ConfigLayer_NoReload() to configure the LTDC Layer according to the specified without reloading
      • HAL_LTDC_SetWindowSize_NoReload() to set the LTDC window size without reloading
      • HAL_LTDC_SetWindowPosition_NoReload() to set the LTDC window position without reloading
      • HAL_LTDC_SetPixelFormat_NoReload() to reconfigure the pixel format without reloading
      • HAL_LTDC_SetAlpha_NoReload() to reconfigure the layer alpha value without reloading
      • HAL_LTDC_SetAddress_NoReload() to reconfigure the frame buffer Address without reloading
      • HAL_LTDC_SetPitch_NoReload() to reconfigure the pitch for specific cases
      • HAL_LTDC_ConfigColorKeying_NoReload() to configure the color keying without reloading
      • HAL_LTDC_EnableColorKeying_NoReload() to enable the color keying without reloading
      • HAL_LTDC_DisableColorKeying_NoReload() to disable the color keying without reloading
      • HAL_LTDC_EnableCLUT_NoReload() to enable the color lookup table without reloading
      • HAL_LTDC_DisableCLUT_NoReload() to disable the color lookup table without reloading
      • Note: Variant -functions with “_NoReload” post fix allows to set the LTDC -configuration/settings without immediate reload. This is useful in case -when the program requires to modify several LTDC settings (on one or -both layers) then applying (reload) these settings in one shot by -calling the function “HAL_LTDC_Reload”
  • HAL RTC update 
    • Add new timeout implementation based on cpu cycles for ALRAWF, ALRBWF and WUTWF flags
  • HAL SAI update
    • Update SAI state in case of TIMEOUT error within the HAL_SAI_Transmit() / HAL_SAI_Receive()
    • Update HAL_SAI_IRQHandler:
      • Add error management in case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()
      • Add error management in case of IT
    • Move -SAI_BlockSynchroConfig() and SAI_GetInputClock() functions to -stm32f4xx_hal_sai.c/.h files (extension files are kept empty for -projects compatibility reason)
  • HAL DCMI update
    • Rename DCMI_DMAConvCplt to DCMI_DMAXferCplt
    • Update HAL_DCMI_Start_DMA() function to Enable the DCMI peripheral
    • Add new timeout implementation based on cpu cycles for DCMI stop
    • Add HAL_DCMI_Suspend() function to suspend DCMI capture
    • Add HAL_DCMI_Resume() function to resume capture after DCMI suspend
    • Update lock mechanism for DCMI process
    • Update HAL_DCMI_IRQHandler() function to:
      • Add error management in case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()
      • Optimize code by using direct register read
  • HAL DMA update
    • Add -new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to -register/unregister the different callbacks identified by the enum -typedef HAL_DMA_CallbackIDTypeDef
    • Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context
      • The new registered Abort callback is called when DMA transfer abortion is completed
    • Add the check of compatibility between FIFO threshold level and size of the memory burst in the HAL_DMA_Init() API
    • Add new Error Codes: HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and HAL_DMA_ERROR_NOT_SUPPORTED
    • Remove all DMA states related to MEM0/MEM1 in HAL_DMA_StateTypeDef
  • HAL IWDG update
    • Overall rework of the driver for a more efficient implementation
      • Remove the following APIs:
        • HAL_IWDG_Start()
        • HAL_IWDG_MspInit()
        • HAL_IWDG_GetState()
      • Update implementation:
        • HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG counter
        • HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter
      • Refer to the following example to identify the changes: IWDG_Example
  • HAL LPTIM update
    • Update HAL_LPTIM_TimeOut_Start_IT() -and HAL_LPTIM_Counter_Start_IT( ) APIs to configure WakeUp Timer EXTI -interrupt to be able to wakeup MCU from low power mode by pressing the EXTI line.
    • Update HAL_LPTIM_TimeOut_Stop_IT() -and HAL_LPTIM_Counter_Stop_IT( ) APIs to disable WakeUp Timer EXTI -interrupt. 
  • HAL NOR update
    • Update NOR_ADDR_SHIFT macro implementation
  • HAL PCD update
    • Update HAL_PCD_IRQHandler() to get HCLK frequency before setting TRDT value
  • HAL QSPI update
    • Update to manage QSPI error management during DMA process
    • Improve the DMA transmit process by using QSPI TC interrupt instead of waiting loop on TC flag under DMA ISR
    • These two improvements require the following updates on user application:
      • Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function
      • In stm32f4xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function
      • Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()
    • Add the management of non-blocking transfer abort service: HAL_QSPI_Abort_IT(). In this case the user must:
      • Add new callback HAL_QSPI_AbortCpltCallback() to inform user at the end of abort process
      • A new value of State in the HAL_QSPI_StateTypeDef provides the current state during the abort phase
    • Polling management update:
      • The Timeout value user must be estimated for the overall process duration: the Timeout measurement is cumulative. 
    • Refer to the following examples, which describe the changes:
      • QSPI_ReadWrite_DMA
      • QSPI_MemoryMapped
      • QSPI_ExecuteInPlace
    • Add two new APIs for the QSPI fifo threshold:
      • HAL_QSPI_SetFifoThreshold(): configure the FIFO threshold of the QSPI
      • HAL_QSPI_GetFifoThreshold(): give the current FIFO threshold
    • Fix wrong data size management in HAL_QSPI_Receive_DMA()
  • HAL ADC update
    • Add - new __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() macro for STM32F42x and STM32F43x - devices to provide the possibility to convert VrefInt channel when both - VrefInt and Vbat channels are selected.
  • HAL SPDIFRX update
    • Overall driver update for wait on flag management optimization 
  • HAL WWDG update 
    • Overall rework of the driver for more efficient implementation
      • Remove the following APIs:
        • HAL_WWDG_Start()
        • HAL_WWDG_Start_IT()
        • HAL_WWDG_MspDeInit()
        • HAL_WWDG_GetState()
      • Update implementation:
        • HAL_WWDG_Init()
          • A new parameter in the Init Structure: EWIMode
        • HAL_WWDG_MspInit()
        • HAL_WWDG_Refresh() 
          • This function insures the reload of the counter
          • The "counter" parameter has been removed
        • HAL_WWDG_IRQHandler()
        • HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeUpCallback()
    • Refer to the following example to identify the changes: WWDG_Example
- -

V1.4.4 / 22-January-2016

-

Main -Changes

  • - -HAL Generic update
    -
    • stm32f4xx_hal_conf_template.h
      • Optimize HSE Startup Timeout value from 5000ms to 100 ms
      • Add new define LSE_STARTUP_TIMEOUT
      • Add new define USE_SPI_CRC for code cleanup when the CRC calculation is disabled.
    • Update HAL drivers to support MISRA C 2004 rule 10.6
    • - -Add new template driver to configure timebase using TIMER :
      • stm32f4xx_hal_timebase_tim_template.c
- - - - -
  • - -HAL CAN update -
    • Update HAL_CAN_Transmit() and HAL_CAN_Transmit_IT() functions to unlock process when all Mailboxes are busy
  • - -HAL DSI update
    -
    • Update HAL_DSI_SetPHYTimings() functions to use the correct mask
  • - -HAL UART update -
    • Several update on HAL UART driver to implement the new UART state machine: 
      • Add new field in UART_HandleTypeDef structure: "rxState", UART state information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": UART state information related to global Handle management and Tx Operations
      • Update UART process to manage the new UART states.
      • Update __HAL_UART_RESET_HANDLE_STATE() macro -to handle the new UART state parameters (gState, rxState)
    • Update -UART_BRR_SAMPLING16() and UART_BRR_SAMPLING8() Macros to fix wrong baudrate -calculation.
- - - - -
  • - -HAL IRDA update -
    • Several update on HAL IRDA driver to implement the new UART state machine: 
      • Add new field in IRDA_HandleTypeDef structure: "rxState", IRDA state information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": IRDA state information related to global Handle management and Tx Operations
      • Update IRDA process to manage the new UART states.
      • Update __HAL_IRDA_RESET_HANDLE_STATE() macro -to handle the new IRDA state parameters (gState, rxState)
    • Removal of IRDA_TIMEOUT_VALUE define
    • Update IRDA_BRR() Macro to fix wrong baudrate calculation
  • - -HAL SMARTCARD update -
    • Several update on HAL SMARTCARD driver to implement the new UART state machine: 
      • Add new field in SMARTCARD_HandleTypeDef structure: "rxState", SMARTCARDstate information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": SMARTCARDstate information related to global Handle management and Tx Operations
      • Update SMARTCARD process to manage the new UART states.
      • Update __HAL_SMARTCARD_RESET_HANDLE_STATE() macro -to handle the new SMARTCARD state parameters (gState, rxState)
    • - -Update SMARTCARD_BRR() macro to fix wrong baudrate -calculation
  • - -HAL  RCC update
    • Add new default define value for HSI calibration "RCC_HSICALIBRATION_DEFAULT"
    • Optimize Internal oscillators and PLL startup timeout 
    • Update -to avoid the disable for HSE/LSE oscillators before setting the new RCC -HSE/LSE configuration and add the following notes in -HAL_RCC_OscConfig() API description:
- - - -     -              -          * @note   -Transitions LSE Bypass to -LSE On and LSE On to LSE Bypass are not - -
            -            -     *         -    supported by this API. User should request a transition to LSE Off - -
            -            -     *         -    first and then LSE On or LSE Bypass. - -
            -            -     * @note   Transition HSE Bypass to HSE On -and HSE On to HSE Bypass are not - -
            -            -     *         -    supported by this API. User should request a transition to HSE Off - - -
            -                 -*             first and then HSE On or HSE -Bypass. - - - -
    • Optimize the HAL_RCC_ClockConfig() API implementation.
  • HAL DMA2D update
    • Update -HAL_DMA2D_Abort() Function to end current DMA2D transfer properly
    • Update -HAL_DMA2D_PollForTransfer() function to add poll for background CLUT loading -(layer 0 and layer 1).
    • Update -HAL_DMA2D_PollForTransfer() to set the corresponding ErrorCode in case of error -occurrence
    • Update HAL_DMA2D_ConfigCLUT() -function to fix wrong CLUT size and color mode settings
    • Removal of useless -macro __HAL_DMA2D_DISABLE()
    • Update -HAL_DMA2D_Suspend() to manage correctly the case where no transfer is on going
    • Update -HAL_DMA2D_Resume() to manage correctly the case where no transfer is on -going
    • Update -HAL_DMA2D_Start_IT() to enable all required interrupts before enabling the -transfer.
    • Add -HAL_DMA2D_CLUTLoad_IT() Function to allow loading a CLUT with interruption -model.
    •  Update -HAL_DMA2D_IRQHandler() to manage the following cases :
      • CLUT transfer complete
      • CLUT access error
      • Transfer watermark reached
    • Add new Callback APIs:
      •  HAL_DMA2D_LineEventCallback() to signal a transfer watermark reached event
      •  HAL_DMA2D_CLUTLoadingCpltCallback() to signal a CLUT loading complete -event
    • Miscellaneous -Improvement:
      • Add "HAL_DMA2D_ERROR_CAE" new define for CLUT Access error management.
      • Add     “assert_param” used for parameters check is now done on the top of the -exported functions : before locking the process using __HAL_LOCK
- - - - - - - - -
  • - -HAL I2C update
    • Add support of I2C repeated start feature:
      • With the following new API's
        • HAL_I2C_Master_Sequential_Transmit_IT()
        • HAL_I2C_Master_Sequential_Receive_IT()
        • HAL_I2C_Master_Abort_IT()
        • HAL_I2C_Slave_Sequential_Transmit_IT()
        • HAL_I2C_Slave_Sequential_Receive_IT()
        • HAL_I2C_EnableListen_IT()
        • HAL_I2C_DisableListen_IT()
      • Add new user callbacks:
        • HAL_I2C_ListenCpltCallback()
        • HAL_I2C_AddrCallback()
    • Update to generate STOP condition when a acknowledge failure error is detected
    • Several update on HAL I2C driver to implement the new I2C state machine: 
      • Add new API to get the I2C mode: -HAL_I2C_GetMode()
      • Update I2C process to manage the new I2C states.
    • Fix wrong -behaviour in single byte transmission 
    • Update I2C_WaitOnFlagUntilTimeout() to manage the NACK feature.
    • Update  I2C -transmission process to support the case data size equal 0
  • - -HAL FMPI2C update
    • Add support of FMPI2C repeated start feature:
      • With the following new API's
        • HAL_FMPI2C_Master_Sequential_Transmit_IT()
        • HAL_FMPI2C_Master_Sequential_Receive_IT()
        • HAL_FMPI2C_Master_Abort_IT()
        • HAL_FMPI2C_Slave_Sequential_Transmit_IT()
        • HAL_FMPI2C_Slave_Sequential_Receive_IT()
        • HAL_FMPI2C_EnableListen_IT()
        • HAL_FMPI2C_DisableListen_IT()
      • Add new user callbacks:
        • HAL_FMPI2C_ListenCpltCallback()
        • HAL_FMPI2C_AddrCallback()
    • Several update on HAL I2C driver to implement the new I2C state machine: 
      • Add new API to get the FMPI2C mode: -HAL_FMPI2C_GetMode()
      • Update FMPI2C process to manage the new FMPI2C states.
  • - -HAL SPI update -
    • Major Update to improve performance in -polling/interrupt mode to reach max frequency:
      • Polling mode :
        • Replace use of SPI_WaitOnFlagUnitTimeout() funnction by "if" statement to check on RXNE/TXE flage while transferring data.
        • Use API data pointer instead of SPI handle data pointer.
        • Use a Goto implementation instead of "if..else" statements.
      • Interrupt mode
        • Minimize access on SPI registers.
        • Split the SPI modes into dedicated static functions to minimize checking statements under HAL_IRQHandler():
          • 1lines/2lines modes
          • 8 bit/ 16 bits data formats
          • CRC calculation enabled/disabled.
        • - -Remove waiting loop under ISR when closing  the communication.
          -
      • All modes:  
        • Adding switch USE_SPI_CRC to minimize number of statements when CRC calculation is disabled.
        • Update Timeout management to check on global process.
        • Update Error code management in all processes.
    • Add note to the max frequencies reached in all modes.
    • Add note about Master Receive mode restrictions :
      • Master Receive mode restriction:
        - -      (#) In Master unidirectional receive-only mode -(MSTR =1, BIDIMODE=0, RXONLY=0) or
        -          bidirectional receive -mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
        -          does not initiate a new -transfer the following procedure has to be respected:
        -          (##) HAL_SPI_DeInit()
        -          (##) HAL_SPI_Init()         -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  • - - -HAL SAI update -
    • Update for proper management of the external synchronization input selection
      • update of HAL_SAI_Init () funciton
      • update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups
    • Update SAI_SLOTACTIVE_X  defines values
    • Update HAL_SAI_Init() function for proper companding mode management
    • Update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers
    • Update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size
    • Update HAL_SAI_EnableRxMuteMode() function for proper mute management
    • Update SAI_InitPCM() function to support 24bits configuration
  • - -HAL ETH update -
    • Removal of ETH MAC debug register defines
  • - -HAL FLASH update -
    • - -Update FLASH_MassErase() function to apply correctly -voltage range parameter -
  • - -HAL I2S update -
    • - -Update I2S_DMATxCplt() and I2S_DMARxCplt() to manage -properly FullDuplex mode without any risk of missing data. -
  • - -LL FMC update -
    • - -Update the FMC_NORSRAM_Init() function to use -BurstAccessMode field properly -
  • - -LL FSMC  update -
    • - -Update the FSMC_NORSRAM_Init() function to use -BurstAccessMode field properly

V1.4.4 / 11-December-2015

Main -Changes
  • HAL Generic update
    • Update HAL -weak empty callbacks to prevent unused argument compilation warnings with some -compilers by calling the following line: -
      • UNUSED(hppp);
    • STM32Fxxx_User_Manual.chm files regenerated for HAL V1.4.3
  • HAL ETH update 
    • Update HAL_ETH_Init() function to add timeout on the Software reset management

V1.4.2 / 10-November-2015

- -

Main Changes

- - - - - - -
  • General updates to fix known defects and enhancements implementation
  • One change done on the HAL CRYP requires an update on the application code based on HAL V1.4.1
    • Update HAL_CRYP_DESECB_Decrypt() API to invert pPlainData and pCypherData parameters
  • HAL generic update
    • Update -HAL weak empty callbacks to prevent unused argument compilation -warnings with some compilers by calling the following line:
      • UNUSED(hppp);

-
  • HAL CORTEX update
    • Remove duplication for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro
  • HAL HASH update
    • Rename HAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef
    • Rename HAL_HASH_PhaseTypeDef to HAL_HASH_PhaseTypeDef
  • HAL RCC update
    • Add new macros __HAL_RCC_PPP_IS_CLK_ENABLED() to check on Clock enable/disable status
    • Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable for the SYSCFG
    • Update HAL_RCC_MCOConfig() API to use new defines for the GPIO Speed
    • Generic update to improve the PLL VCO min value(100MHz): PLLN, PLLI2S and PLLSAI min value is 50 instead of 192
  • HAL FLASH update
    • __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset  ICRST bit in the ACR register after setting it.
    • Update to support until 15 FLASH wait state (FLASH_LATENCY_15) for STM32F446xx devices
  • -

    HAL CRYP update

    • Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue
  • HAL I2S update
    • Update HAL_I2S_Init() API to call __HAL_RCC_I2S_CONFIG() macro when external I2S clock is selected
  • HAL LTDC update
    • Update HAL_LTDC_SetWindowPosition() API to configure Immediate reload register instead of vertical blanking reload register.
  • HAL TIM update
    • Update HAL_TIM_ConfigClockSource() API to check only the required parameters
  • HAL NAND update
    • Update HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() APIs to manage correctly the NAND Page access
  • HAL CAN update
    • Update to use "=" instead of "|=" to clear flags in the MSR, TSR, RF0R and RF1R registers
  • HAL HCD update
    • Fix typo in __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() macro implementation
  • HAL PCD update
    • Update HAL_PCD_IRQHandler() API to avoid issue when DMA mode enabled for Status Phase IN stage
  • LL FMC update
    • Update the FMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters
    • Update the FMC_NORSRAM_Init() API to add a check on the PageSize parameter for STM32F42/43xx devices
  • LL FSMC update
    • Update the FSMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters

V1.4.1 / 09-October-2015

- -

Main Changes

- - - - - - -
  • HAL DSI update
    • Update TCCR register assigned value in HAL_DSI_ConfigHostTimeouts() function
    • Update WPCR register assigned value -in HAL_DSI_Init(), HAL_DSI_SetSlewRateAndDelayTuning(), -HAL_DSI_SetSlewRateAndDelayTuning(), HAL_DSI_SetLowPowerRXFilter() / -HAL_DSI_SetSDD(), HAL_DSI_SetLanePinsConfiguration(), -HAL_DSI_SetPHYTimings(), HAL_DSI_ForceTXStopMode(), -HAL_DSI_ForceRXLowPower(), HAL_DSI_ForceDataLanesInRX(), -HAL_DSI_SetPullDown() and HAL_DSI_SetContentionDetectionOff() functions
    • Update DSI_HS_PM_ENABLE define value
    • Implement -workaround for the hardware limitation: “The time to activate the clock -between HS transmissions is not calculated correctly”

V1.4.0 / 14-August-2015

- -

Main Changes

- - - - - - -
  • Add support of STM32F469xx, STM32F479xx, STM32F410Cx, STM32F410Rx and STM32F410Tx  devices
  • General updates to fix known defects and enhancements implementation
  • Add new HAL drivers for DSI and LPTIM peripherals
  • HAL ADC update
    • Rename ADC_CLOCKPRESCALER_PCLK_DIV2 define to ADC_CLOCK_SYNC_PCLK_DIV2
    • Rename ADC_CLOCKPRESCALER_PCLK_DIV4 define to ADC_CLOCK_SYNC_PCLK_DIV4
    • Rename ADC_CLOCKPRESCALER_PCLK_DIV6 define to ADC_CLOCK_SYNC_PCLK_DIV6
    • Rename ADC_CLOCKPRESCALER_PCLK_DIV8 define to ADC_CLOCK_SYNC_PCLK_DIV8
  • HAL CORTEX update
    • Add specific API for MPU management
      • add MPU_Region_InitTypeDef structure
      • add new function HAL_MPU_ConfigRegion()
  • HAL DMA update
    • Overall driver update for code optimization
      • add StreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef structure
      • add DMA_Base_Registers private structure
      • add static function DMA_CalcBaseAndBitshift()
      • update HAL_DMA_Init() function to use the new added static function
      • update HAL_DMA_DeInit() function to optimize clear flag operations
      • update HAL_DMA_Start_IT() function to optimize interrupts enable
      • update HAL_DMA_PollForTransfer() function to optimize check on flags
      • update HAL_DMA_IRQHandler() function to optimize interrupt flag management
  • HAL FLASH update
    • update HAL_FLASH_Program_IT() function by removing the pending flag clear
    • update HAL_FLASH_IRQHandler() function to improve erase operation procedure
    • update FLASH_WaitForLastOperation() function by checking on end of operation flag
  • HAL GPIO update
    • Rename GPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW
    • Rename GPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM
    • Rename GPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH
    • Rename GPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH
  • HAL I2S update
    • Move I2S_Clock_Source defines to extension file to properly add the support of STM32F410xx devices
  • HAL LTDC update
    • rename HAL_LTDC_LineEvenCallback() function to HAL_LTDC_LineEventCallback()
    • add new function HAL_LTDC_SetPitch()
    • add -new functions HAL_LTDC_StructInitFromVideoConfig() and -HAL_LTDC_StructInitFromAdaptedCommandConfig() applicable only to -STM32F469xx and STM32F479xx devices
  • HAL PWR update
    • move __HAL_PWR_VOLTAGESCALING_CONFIG() macro to extension file
    • move PWR_WAKEUP_PIN2 define to extension file
    • add PWR_WAKEUP_PIN3 define, applicable only to STM32F10xx devices
    • add -new functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() and -HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), applicable only to STM32F469xx and STM32F479xx devices
  • HAL RTC update
    • Update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on the WUTWF flag
  • HAL TIM update
    • add -new defines TIM_SYSTEMBREAKINPUT_HARDFAULT,  -TIM_SYSTEMBREAKINPUT_PVD and TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD, -applicable only to STM32F410xx devices

V1.3.2 / 26-June-2015

- -

Main Changes

- - - - - - -
  • General updates to fix known defects and enhancements implementation
  • One changes done on the HAL may require an update on the application code based on HAL V1.3.1
    • HASH IT process: update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits
  • HAL RCC update
    • HAL_RCCEx_PeriphCLKConfig() updates:
      • Update -the LSE check condition after backup domain reset: update to -check LSE ready flag when LSE oscillator is already enabled -instead of check on LSE oscillator only when LSE is used as RTC clock -source
      • Use the right macro to check the PLLI2SQ parameters
  • HAL RTC update
    • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() macro: fix implementation issue
    • __HAL_RTC_ALARM_GET_IT(), -__HAL_RTC_ALARM_CLEAR_FLAG(), __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(), -__HAL_RTC_TIMESTAMP_CLEAR_FLAG() and __HAL_RTC_TAMPER_CLEAR_FLAG() -macros implementation changed: remove unused cast
    • IS_RTC_TAMPER() macro: update to use literal instead of hardcoded value 
    • Add new parameter SecondFraction in RTC_TimeTypeDef structure
    • HAL_RTC_GetTime() API update to support the new parameter SecondFraction
  • HAL ADC update
    • Add -new literal: ADC_INJECTED_SOFTWARE_START to be used as possible value -for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef -structure to select the ADC software trigger mode.
  • HAL FLASH update
    • FLASH_OB_GetRDP() API update to return uint8_t instead of FlagStatus
    •  __HAL_FLASH_GET_LATENCY() new macro add to get the flash latency
  • HAL SPI update
    • Fix the wrong definition of HAL_SPI_ERROR_FLAG literal
  • HAL I2S update
    • HAL_I2S_Transmit() API update to check on busy flag only for I2S slave mode
  • HAL CRC update
    • __HAL_CRC_SET_IDR() macro implementation change to use WRITE_REG() instead of MODIFY_REG()
  • HAL DMA2D update
    • HAL_DMA2D_ConfigLayer() API update to use "=" instead of "|=" to erase BGCOLR and FGCOLR registers before setting the new configuration
  • HAL HASH update
    • HAL_HASH_MODE_Start_IT() (MODE stands for MD5, SHA1, SHA224 and SHA36) updates:
      • Fix processing fail for small input buffers
      • Update -to unlock the process and call return HAL_OK at the end of HASH -processing to avoid incorrectly repeating software
      • Update to properly manage the HashITCounter
      • Update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits
    • __HAL_HASH_GET_FLAG() update to  check the right register when the DINNE flag  is selected
    • HAL_HASH_SHA1_Accumulate() updates:
      • Add a call to the new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size parameter. 
      • Add the following note in API description
 * @note  Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
  • HAL RTC update
    • Update to define hardware independent literals names:
      • Rename RTC_TAMPERPIN_PC13 by  RTC_TAMPERPIN_DEFAULT
      • Rename RTC_TAMPERPIN_PA0 by RTC_TAMPERPIN_POS1
      • Rename RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1
      • Rename RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT
      • Rename RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1
      • Rename RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1
  • HAL ETH update
    • Remove duplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros
    • Remove illegal space ETH_MAC_READCONTROLLER_FLUSHING macro
    • Update ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and READING_STATUS)
  • HAL PCD update
    • HAL_PCD_IRQHandler API: fix the bad Configuration of Turnaround Time
  • HAL HCD update
    • Update to use local variable in USB Host channel re-activation
  • LL FMC update
    • FMC_SDRAM_SendCommand() API: remove the following line: return HAL_ERROR;
  • LL USB update
    • USB_FlushTxFifo API: update to flush all Tx FIFO
    • Update to use local variable in USB Host channel re-activation

V1.3.1 / 25-Mars-2015

- -

Main Changes

- - - - - - -
  • HAL PWR update
    • Fix compilation issue with STM32F417xx product: update STM32F17xx by STM32F417xx
  • HAL SPI update
    • Remove unused variable to avoid warning with TrueSTUDIO 
  • HAL I2C update
    • I2C Polling/IT/DMA processes: move the wait loop on busy flag at the top of the processes, to ensure that software not perform any write access to I2C_CR1 register before hardware clearing STOP bit and to avoid also the waiting loop on BUSY flag under I2C/DMA ISR.
    • Update busy flag Timeout value
    • I2C Master Receive Processes update to disable ACK before generate the STOP 
  • HAL DAC update
    • Fix -V1.3.0 regression issue with DAC software trigger configuration

V1.3.0 / 09-Mars-2015

- -

Main Changes

- - - - - - -
  • Add support of STM32F446xx devices
  • General updates to fix known defects and enhancements implementation
  • Add new HAL drivers for CEC, QSPI, FMPI2C and SPDIFRX peripherals
  • Two changes done on the HAL requires an update on the application code based on HAL V1.2.0
    • Overall SAI driver rework to have exhaustive support of the peripheral features: details are provided in HAL SAI update section below --> Compatibility with previous version is impacted
    • CRYP driver updated to support multi instance,so user must ensure that the new parameter Instance is initalized in his application(CRYPHandle.Instance = CRYP) 
  • HAL Generic update
    • stm32f4xx_hal_def.h
      • Remove NULL definition and add include for stdio.h
    • stm32_hal_legacy.h
      • Update method to manage deference in alias implementation between all STM32 families
    • stm32f4xx_hal_ppp.c
      • HAL_PPP_Init(): update to force the HAL_PPP_STATE_RESET before calling the HAL_PPP_MspInit()
  • HAL RCC update
    • Add new function HAL_RCCEx_GetPeriphCLKFreq()
    • Move RCC_PLLInitTypeDef structure to extension file and add the new PLLR field specific to STM32F446xx devices
    • Move -the following functions to extension file and add a __weak attribute in generic -driver : this update is related to new system clock source (PLL/PLLR) added and only available for -STM32F44xx devices
      • HAL_RCC_OscConfig()
      • HAL_RCC_GetSysClockFreq()
      • HAL_RCC_GetOscConfig()
    • Move the following macro to extension file as they have device dependent implementation
      • __HAL_RCC_PLL_CONFIG() -
      • __HAL_RCC_PLLI2S_CONFIG()
      • __HAL_RCC_I2S_CONFIG()
    • Add new -structure RCC_PLLI2SInitTypeDef -containing new PLLI2S division factors -used only w/ STM32F446xx devices
    • Add new -structure RCC_PLLSAIInitTypeDef -containing new PLLSAI division factors -used only w/ STM32F446xx devices
    • Add new -RCC_PeriphCLKInitTypeDef to support the -peripheral source clock selection for (I2S, -SAI, SDIO, FMPI2C, CEC, SPDIFRX and CLK48)
    • Update -the HAL_RCCEx_PeriphCLKConfig() and -HAL_RCCEx_GetPeriphCLKConfig() -functions to support the new peripherals Clock source -selection
    • Add -__HAL_RCC_PLL_CONFIG() macro (the -number of parameter and the implementation depend on the device part -number)
    • Add -__HAL_RCC_PLLI2S_CONFIG() macro(the number of parameter and the implementation depend on -device part number)
    • Update -__HAL_RCC_PLLSAI_CONFIG() macro to -support new PLLSAI factors (PLLSAIM and -PLLSAIP)
    • Add new -macros for clock enable/Disable for the following peripherals (CEC, SPDIFRX, SAI2, -QUADSPI)
    • Add the -following new macros for clock source selection :
      • __HAL_RCC_SAI1_CONFIG() / -__HAL_RCC_GET_SAI1_SOURCE()
      • __HAL_RCC_SAI2_CONFIG() / -__HAL_RCC_GET_SAI2_SOURCE()
      • __HAL_RCC_I2S1_CONFIG() / -__HAL_RCC_GET_I2S1_SOURCE()
      • __HAL_RCC_I2S2_CONFIG() / -__HAL_RCC_GET_I2S2_SOURCE()
      • __HAL_RCC_CEC_CONFIG() / __HAL_RCC__GET_CEC_SOURCE() -
      • __HAL_RCC_FMPI2C1_CONFIG() / __HAL_RCC_GET_FMPI2C1_SOURCE() -
      • __HAL_RCC_SDIO_CONFIG() / __HAL_RCC_GET_SDIO_SOURCE() -
      • __HAL_RCC_CLK48_CONFIG() / __HAL_RCC_GET_CLK48_SOURCE() -
      • __HAL_RCC_SPDIFRXCLK_CONFIG() / -__HAL_RCC_GET_SPDIFRX_SOURCE()
    • __HAL_RCC_PPP_CLK_ENABLE(): Implement workaround to cover RCC limitation regarding peripheral enable delay
    • HAL_RCC_OscConfig() fix issues: 
      • Add a check on LSERDY flag when LSE_BYPASS is selected as new state for LSE oscillator.
    • Add new possible value RCC_PERIPHCLK_PLLI2S to be selected as PeriphClockSelection parameter -in the  RCC_PeriphCLKInitTypeDef structure to allow the -possibility to output the PLLI2S on MCO without activating the I2S or -the SAI.
    • __HAL_RCC_HSE_CONFIG()  macro: add the comment below:
- -
 * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
 *         User should request a -transition to HSE Off first and then HSE On or HSE Bypass.
    • __HAL_RCC_LSE_CONFIG()  macro: add the comment below:
- -
  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
  -*         User should request a -transition to LSE Off first and then LSE On or LSE Bypass.
    • Add the -following new macros for PLL source and PLLM selection :
      • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
      • __HAL_RCC_PLL_PLLM_CONFIG()
    • Macros rename:
      • HAL_RCC_OTGHS_FORCE_RESET() by HAL_RCC_USB_OTG_HS_FORCE_RESET()
      • HAL_RCC_OTGHS_RELEASE_RESET() by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
      • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
      • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
      • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
      • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
    • Add __HAL_RCC_SYSCLK_CONFIG() new macro to configure the system clock source (SYSCLK)
    • __HAL_RCC_GET_SYSCLK_SOURCE() updates:
      • Add new RCC Literals:
        • RCC_SYSCLKSOURCE_STATUS_HSI
        • RCC_SYSCLKSOURCE_STATUS_HSE
        • RCC_SYSCLKSOURCE_STATUS_PLLCLK
        • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
      •  Update macro description to refer to the literals above
  • HAL PWR update
    • Add new define PWR_WAKEUP_PIN2
    • Add new API to Control/Get VOS bits of CR register
      • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
      • HAL_PWREx_GetVoltageRange()
    • __HAL_PWR_ VOLTAGESCALING_CONFIG(): Implement workaround to cover VOS limitation delay when PLL is enabled after setting the VOS configuration
  • HAL GPIO update
    • Add the -new Alternate functions literals related to remap for SPI, USART, I2C, SPDIFRX, CEC and -QSPI
    • HAL_GPIO_DeInit(): -Update to check if GPIO Pin x is already used in EXTI mode on -another GPIO Port before De-Initialize the EXTI registers
  • HAL FLASH update
    • __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset  ICRST bit in the ACR register after setting it.
    • __HAL_FLASH_DATA_CACHE_RESET() macro: update to reset  DCRST bit in the ACR register after setting it.
  • HAL ADC update
    • Add new literal: ADC_SOFTWARE_START to be used as possible value for the ExternalTrigConv parameter in the ADC_InitTypeDef structure to select the ADC software trigger mode.
    • IS_ADC_CHANNEL() macro update to don't assert stop the ADC_CHANNEL_TEMPSENSOR value
    • HAL_ADC_PollForConversion(): -update to manage particular case when ADC configured in DMA mode and -ADC sequencer with several ranks and polling for end of each conversion
    • HAL_ADC_Start()/HAL_ADC_Start_IT() /HAL_ADC_Start_DMA() update:
      • unlock the process before starting the ADC software conversion.
      • Optimize the ADC stabilization delays
    • __HAL_ADC_GET_IT_SOURCE() update macro implementation
    • Add more details in 'How to use this driver' section
  • HAL DAC update
    • - -

      Add new macro to check if the specified DAC interrupt source is enabled or disabled

      -
      • __HAL_DAC_GET_IT_SOURCE()
    • HAL_DACEx_TriangleWaveGeneration() update to use DAC CR bit mask definition
    • HAL_DACEx_NoiseWaveGeneration() update to use DAC CR bit mask definition
  • HAL CAN update
    • CanTxMsgTypeDef structure: update to use uint8_t Data[8] instead of uint32_t Data[8]
    • CanRxMsgTypeDef structure: update to use uint8_t Data[8] instead of uint32_t Data[8]
  • HAL RTC update
    • Update to use CMSIS mask definition instead of hardcoded values (EXTI_IMR_IM17, EXTI_IMR_IM19..)
  • HAL LTDC update
    • LTDC_SetConfig() update to allow the drawing of partial bitmap in active layer.
  • HAL USART update
    • HAL_USART_Init() fix USART baud rate configuration issue: USART baud rate is twice Higher than expected
  • HAL SMARTCARD update
    • HAL_SMARTCARD_Transmit_IT() update to force the disable for the ERR interrupt to avoid the OVR interrupt
    • HAL_SMARTCARD_IRQHandler() update check condition for transmission end
    • Clean up: remove the following literals that aren't used in smartcard mode
      • SMARTCARD_PARITY_NONE
      • SMARTCARD_WORDLENGTH_8B
      • SMARTCARD_STOPBITS_1
      • SMARTCADR_STOPBITS_2
  • HAL SPI update
    • HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TarnsmitReceive_DMA() update to unlock the process before enabling the SPI peripheral
    • HAL_SPI_Transmit_DMA() update to manage correctly the DMA RX stream in SPI Full duplex mode
    • Section SPI_Exported_Functions_Group2 update to remove duplication in *.chm UM
  • HAL CRYP update
    • Update to manage multi instance:
      • Add new parameter Instance in the CRYP_HandleTypeDef Handle structure.
      • Add new parameter in all HAL CRYP macros
        • example: __HAL_CRYP_ENABLE()  updated by __HAL_CRYP_ENABLE(__HANDLE__)
  • HAL DCMI update
    • Add an -extension driver stm32f4xx_hal_dcmi_ex.c/h to manage the support of new Black and White feature -
    • Add  __weak attribute for HAL_DCMI_Init() function and add a new -implementation in the extension driver to manage the black and white configuration -only available in the  STM32F446xx devices. -
    • Move -DCMI_InitTypeDef structure to extension driver and add the -following new fields related to black and white feature: -ByteSelectMode, ByteSelectStart, LineSelectMode and LineSelectStart
  • HAL PCD update
    • Add the support of LPM feature
      • add PCD_LPM_StateTypeDef enum
      • update PCD_HandleTypeDef structure to support the LPM feature
      • add -new functions HAL_PCDEx_ActivateLPM(), HAL_PCDEx_DeActivateLPM() and -HAL_PCDEx_LPM_Callback() in the stm32f4xx_hal_pcd_ex.h/.c files
  • HAL TIM update
    • Add  TIM_TIM11_SPDIFRX define
  • HAL SAI update
    • Add -stm32f4xx_hal_sai_ex.h/.c files for the SAI_BlockSynchroConfig() and the -SAI_GetInputClock() management
    • Add new defines -HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_CNREADY, -HAL_SAI_ERROR_WCKCFG, HAL_SAI_ERROR_TIMEOUT in the SAI_Error_Code group -
    • Add new defines -SAI_SYNCEXT_DISABLE, SAI_SYNCEXT_IN_ENABLE, SAI_SYNCEXT_OUTBLOCKA_ENABLE, -SAI_SYNCEXT_OUTBLOCKB_ENABLE for the SAI External synchronization -
    • Add new defines -SAI_I2S_STANDARD, SAI_I2S_MSBJUSTIFIED, SAI_I2S_LSBJUSTIFIED, SAI_PCM_LONG and -SAI_PCM_SHORT for the SAI Supported protocol -
    • Add new defines -SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, -SAI_PROTOCOL_DATASIZE_24BIT and SAI_PROTOCOL_DATASIZE_32BIT for SAI protocol -data size
       -
    • Add SAI Callback -prototype definition
    • Update SAI_InitTypeDef structure by adding new fields: SynchroExt, Mckdiv, MonoStereoMode, CompandingMode, TriState
    • Update SAI_HandleTypeDef structure:
      • remove -uint16_t *pTxBuffPtr, *pRxBuffPtr, TxXferSize, RxXferSize, TxXferCount -and RxXferCount and replace them respectively by uint8_t *pBuffPtr, -uint16_t XferSize and uint16_t XferCount
      • add mutecallback field
      • add struct __SAI_HandleTypeDef *hsai field
    • Remove SAI_CLKSOURCE_PLLR and SAI_CLOCK_PLLSRC defines
    • Add SAI_CLKSOURCE_NA define
    • Add SAI_AUDIO_FREQUENCY_MCKDIV define
    • Add SAI_SPDIF_PROTOCOL define
    • Add SAI_SYNCHRONOUS_EXT define
    • Add -new functions HAL_SAI_InitProtocol(), HAL_SAI_Abort(), -HAL_SAI_EnableTxMuteMode(), HAL_SAI_DisableTxMuteMode(), -HAL_SAI_EnableRxMuteMode(), HAL_SAI_DisableRxMuteMode()
    • Update -HAL_SAI_Transmit(), HAL_SAI_Receive(), HAL_SAI_Transmit_IT(), -HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), HAL_SAI_Receive_DMA() -functions to use uint8_t *pData instead of uint16_t *pData --> This update is mainly impacting the compatibility with previous driver version.
  • HAL I2S update
    • Split the -following functions between Generic and Extended API based on full -duplex management and add the attribute __weak in the Generic API
      • HAL_I2S_Init(), HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), HAL_I2S_DMAResume(), HAL_I2S_IRQHandle()
    • Move the following static functions from generic to extension driver
      •  I2S_DMARxCplt() and I2S_DMATxCplt()
    • Remove static attribute from I2S_Transmit_IT() and I2S_Receive_IT() functions
    • Move I2SxEXT() macro to extension file
    • Add I2S_CLOCK_PLLR and I2S_CLOCK_PLLSRC defines for I2S clock source
    • Add new function I2S_GetInputClock()
  • HAL LL FMC update
    • Add WriteFifo and PageSize fields in the FMC_NORSRAM_InitTypeDef structure
    • Add -FMC_PAGE_SIZE_NONE, FMC_PAGE_SIZE_128, FMC_PAGE_SIZE_256, -FMC_PAGE_SIZE_1024, FMC_WRITE_FIFO_DISABLE, FMC_WRITE_FIFO_ENABLE -defines
    • Update FMC_NORSRAM_Init(), FMC_NORSRAM_DeInit() and FMC_NORSRAM_Extended_Timing_Init() functions
  • HAL LL USB update
    • Update USB_OTG_CfgTypeDef structure to support LPM, lpm_enable field added
    • Update USB_HostInit() and USB_DevInit() functions to support the VBUS Sensing B activation

V1.2.0 / 26-December-2014

- - - -

Main Changes

- - - - - - - - -
  • Maintenance release to fix known defects and enhancements implementation
    -
- - -
  • Macros and literals renaming to ensure compatibles - across STM32 series, backward compatibility maintained thanks to new added file stm32_hal_legacy.h under /Inc/Legacy
  • Add *.chm UM for all drivers, a UM is provided for each superset RPN
  • Update -drivers to be C++ compliant -
  • Several -update on source code formatting, for better UM generation (i.e. Doxygen tags -updated)
    • -
  • Two changes done on the HAL requires an update on the application code based on HAL V1.1.0
    -
    • -
      -
    • LSI_VALUE constant has been corrected in stm32f4xx_hal_conf.h file, its value changed from 40 KHz to 32 KHz
      • -
    -
      -
    • UART, USART, IRDA and SMARTCARD (referenced as PPP here below) drivers: in DMA transmit process, the code has been updated to avoid waiting on TC flag under DMA ISR, PPP TC interrupt is used instead. Below the update to be done on user application:
      • -
    -
      -
        -
      • Configure and enable the USART IRQ in HAL_PPP_MspInit() function
        -
        • -
      -
    -
      -
        -
      • In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • -
      -
    -
  • HAL generic update
-
    • stm32f4xx_hal_def.h
      • Update NULL definition to -fix C++ compilation issue
      • Add UNUSED() macro
      • - -

        Add a new define __NOINLINE to be used for the no inline -code independent from tool chain

        -
    • stm32f4xx_hal_conf_template.h
      • LSI_VALUE constant has been corrected, its value changed from 40 KHz to 32 -KHz
      -
    • Update all macros and literals naming to be uper case
      • -
    • ErrorCode -parameter in PPP_HandleTypeDef structure updated to uint32_t instead of enum HAL_PPP_ErrorTypeDef
      • -
    • Remove the unused FLAG and IT assert macros
      -
  • HAL ADC update
    • - -

      Fix temperature sensor channel configuration issue for STM32F427/437xx  and STM32F429/439xx devices

  • HAL DAC update
    • - -

      HAL_DAC_ConfigChannel(): -update the access to the DAC peripheral registers via the hdac handle instance

    • HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and DAC_FLAG_DMAUDR2
    • HAL_DACEx_NoiseWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration
    • HAL_DACEx_TriangleWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration
  • HAL CAN update
    • - -

      Unlock the CAN process when communication error -occurred

      -
  • HAL CORTEX update
    • Add new macro IS_NVIC_DEVICE_IRQ() to check on negative values of IRQn parameter
  • -

    HAL CRYP update

    • HAL_CRYP_DESECB_Decrypt_DMA(): fix the inverted pPlainData and pCypherData parameters issue
    • CRYPEx_GCMCCM_SetInitVector(): remove the IVSize parameter as the key length 192bits and 256bits are not supported by this version
    • Add restriction for the CCM Encrypt/Decrypt API's that only DataType equal to 8bits is supported
      -
    • HAL_CRYPEx_AESGCM_Finish():
      • Add restriction that the -implementation is limited to 32bits inputs data length  (Plain/Cyphertext, Header) compared with GCM stadards -specifications (800-38D)
      • Update Size parameter on 32bits instead of 16bits
      • Fix issue with 16-bit Data Type: update to use intrinsic __ROR() instead of __REV16()
  • -

    HAL DCMI update

    • - -

      HAL_DCMI_ConfigCROP(): Invert -assert macros to check Y0 and Ysize parameters

  • -

    HAL DMA update

    • - -

      HAL_DMA_Init(): Update to clear the DBM bit in the SxCR register before setting the new configuration

    • DMA_SetConfig(): add to clear the DBM bit in the SxCR register
  • -

    HAL FLASH update

    • Add "HAL_" prefix in the defined values for the FLASH error code
      • Example: FLASH_ERROR_PGP renamed by HAL_FLASH_ERROR_PGP
    • Clear the Flash ErrorCode in the FLASH_WaitForLastOperation() function
    • Update FLASH_SetErrorCode() function to use "|=" operant to update the Flash ErrorCode parameter in the FLASH handle
    • IS_FLASH_ADDRESS(): Update the macro check using '<=' condition instead of '<'
    • IS_OPTIONBYTE(): Update the macro check using '<=' condition instead of '<'
    • Add "FLASH_" prefix in the defined values of FLASH Type Program parameter
      -
      • Example: TYPEPROGRAM_BYTE renamed by FLASH_TYPEPROGRAM_BYTE
    • Add "FLASH_" prefix in the defined values of FLASH Type Erase parameter
      • Example: TYPEERASE_SECTORS renamed by FLASH_TYPEERASE_SECTORS
    • Add "FLASH_" prefix in the defined values of FLASH Voltage Range parameter
      • Example: VOLTAGE_RANGE_1 renamed by FLASH_VOLTAGE_RANGE_1
    • Add "OB_" prefix in the defined values of FLASH WRP State parameter
      • Example: WRPSTATE_ENABLE renamed by OB_WRPSTATE_ENABLE
    • Add "OB_" prefix in the defined values of the FLASH PCROP State parameter
      • PCROPSTATE_DISABLE  updated by OB_PCROP_STATE_DISABLE
      • PCROPSTATE_ENABLE  updated by OB_PCROP_STATE_ENABLE
    • Change "OBEX" prefix by "OPTIONBYTE" prefix in these defines:
      • OBEX_PCROP by OPTIONBYTE_PCROP 
      • OBEX_BOOTCONFIG by OPTIONBYTE_BOOTCONFIG
  • -

    HAL ETH update

    • Fix macros naming typo
- -
      • Update __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() by - __HAL_ETH_EXTI_SET_RISING_EDGE_TRIGGER()
      • Update __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() by __HAL_ETH_EXTI_SET_FALLING_EDGE_TRIGGER() -
-
  • -

    HAL PWR update

    -
    • Add new API to -manage SLEEPONEXIT and -SEVONPEND bits of SCR register
      • HAL_PWR_DisableSleepOnExit() -
      • HAL_PWR_EnableSleepOnExit() -
      • HAL_PWR_EnableSEVOnPend() -
      • HAL_PWR_DisableSEVOnPend()
    • HAL_PWR_EnterSTOPMode()
      • Update to clear the CORTEX SLEEPDEEP bit of SCR register before entering in sleep mode
      • Update -usage of __WFE() in low power entry function: if there is a pending -event, calling __WFE() will not enter the CortexM4 core to sleep mode. -The solution is to made the call below; the first __WFE() is always -ignored and clears the event if one was already pending, the second is -always applied
        -
-
__SEV()
- __WFE()
- __WFE()
    • - -

      Add new PVD configuration -modes

      -
      • PWR_PVD_MODE_NORMAL -
      • PWR_PVD_MODE_EVENT_RISING  -
      • PWR_PVD_MODE_EVENT_FALLING
      • PWR_PVD_MODE_EVENT_RISING_FALLING
    • - -

      Add new macros to manage PVD -Trigger

      -
      • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() -
      • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE( -
      • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() -
      • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
      • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() -
      • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
    • - -

      PVD macros:

      -
      • Remove the __EXTILINE__ parameter
      • Update to use prefix - "__HAL_PWR_PVD_" instead of  prefix "__HAL_PVD"
-
    • Rename HAL_PWR_PVDConfig() by HAL_PWR_ConfigPVD()
      • -
    • Rename HAL_PWREx_ActivateOverDrive() by HAL_PWREx_EnableOverDrive()
      • -
    • Rename HAL_PWREx_DeactivateOverDrive() by HAL_PWREx_DisableOverDrive()
  • HAL GPIO update
    • - -

      HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call to the CMSIS assert macro to check GPIO instance: IS_GPIO_ALL_INSTANCE() 

    • HAL_GPIO_WritePin(): update to write in BSRR register
    • Rename GPIO_GET_SOURCE() by GET_GPIO_INDEX() and move this later to file  stm32f4xx_hal_gpio_ex.h
    • Add new define for alternate function GPIO_AF5_SPI3 for STM32F429xx/439xx and STM32F427xx/437xx devices
  • HAL HASH update
    • HAL_HASH_MD5_Start_IT(): fix input address management issue
  • HAL RCC update
    • Rename the following Macros
      • __PPP_CLK_ENABLE()  by __HAL_RCC_PPP_CLK_ENABLE()
      • __PPP_CLK_DISABLE()  by __HAL_RCC_PPP_CLK_DISABLE()
      • __PPP_FORCE_RESET()  by __HAL_RCC_PPP_FORCE_RESET()
      • __PPP_RELEASE_RESET()  by __HAL_RCC_PPP_RELEASE_RESET()
      • __PPP_CLK_SLEEP_ENABLE() by __HAL_RCC_PPP_CLK_SLEEP_ENABLE()
      • __PPP_CLK_SLEEP_DISABLE() by __HAL_RCC_PPP_CLK_SLEEP_DISABLE()
    • IS_RCC_PLLSAIN_VALUE() macro: update the check condition
      -
    • Add description of RCC known Limitations
    • Rename HAL_RCC_CCSCallback() by HAL_RCC_CSSCallback()
    • HAL_RCC_OscConfig() fix issues: 
      • Remove the disable of HSE oscillator when HSE_BYPASS is used as system clock source or as PPL clock source
        -
      • Add a check on HSERDY flag when HSE_BYPASS is selected as new state for HSE oscillator.
    • Rename __HAL_RCC_I2SCLK() by __HAL_RCC_I2S_Config()
  • -

    HAL I2S update

    -
    • HAL_I2S_Init(): add check on I2S instance using CMSIS macro IS_I2S_ALL_INSTANCE() 
    • HAL_I2S_IRQHandler() update for compliancy w/ C++
    • Add use of tmpreg variable in __HAL_I2S_CLEAR_OVRFLAG() and __HAL_I2S_CLEAR_UDRFLAG() macro for compliancy with C++
    • HAL_I2S_GetError(): update to return uint32_t instead of HAL_I2S_ErrorTypeDef enumeration
  • -

    HAL I2C update

    • Update to clear the POS bit in the CR1 register at the end of HAL_I2C_Master_Read_IT() and HAL_I2C_Mem_Read_IT() process
    • Rename HAL_I2CEx_DigitalFilter_Config()  by HAL_I2CEx_ConfigDigitalFilter()
    • Rename HAL_I2CEx_AnalogFilter_Config()  by HAL_I2CEx_ConfigAnalogFilter()
    • Add use of tmpreg variable in __HAL_I2C_CLEAR_ADDRFLAG() and __HAL_I2C_CLEAR_STOPFLAG() macro for compliancy with C++
  • HAL IrDA update
    • DMA transmit process; the code -has been updated to avoid waiting on TC flag under DMA ISR, IrDA TC interrupt is used instead. Below the -update to be done on user application:
      • Configure and enable -the USART IRQ in HAL_IRDA_MspInit() function
      • In stm32f4xx_it.c file, UASRTx_IRQHandler() -function: add a call to -HAL_IRDA_IRQHandler() function
    • IT transmit process; the code -has been updated to avoid waiting on TC flag under IRDA ISR, IrDA TC interrupt is used instead. No impact on user application
    • Rename Macros: add prefix "__HAL"
      • __IRDA_ENABLE() by __HAL_IRDA_ENABLE()
      • __IRDA_DISABLE() by __HAL_IRDA_DISABLE()
    • Add new user macros to manage the sample method feature
      • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE()
      • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE()
    • HAL_IRDA_Transmit_IT(): update to remove the enable of the parity error interrupt
    • Add use of tmpreg variable in __HAL_IRDA_CLEAR_PEFLAG() macro for compliancy with C++
    • HAL_IRDA_Transmit_DMA() update to follow the right procedure "Transmission using DMA"  in the reference manual
      • Add clear the TC flag in the SR register before enabling the DMA transmit request
  • HAL IWDG update
    • Rename the defined IWDG keys: 
      • KR_KEY_RELOAD by IWDG_KEY_RELOAD
      • KR_KEY_ENABLE by IWDG_KEY_ENABLE
      • KR_KEY_EWA by IWDG_KEY_WRITE_ACCESS_ENABLE
      • KR_KEY_DWA by IWDG_KEY_WRITE_ACCESS_DISABLE
    •  Add new macros __HAL_IWDG_RESET_HANDLE_STATE() and __HAL_IWDG_CLEAR_FLAG() 
    • Update __HAL_IWDG_ENABLE_WRITE_ACCESS() and __HAL_IWDG_DISABLE_WRITE_ACCESS() as private macro

  • HAL SPI update

    • HAL_SPI_TransmitReceive_DMA() update to remove the  DMA Tx Error Callback initialization when SPI RxOnly mode is selected
    • Add use of -UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), -__HAL_SPI_CLEAR_FREFLAG() to fix "Unused variable" -warning with TrueSTUDIO.
    • Rename Literals: remove "D" from "DISABLED" and "ENABLED"
      • SPI_TIMODE_DISABLED by SPI_TIMODE_DISABLE
      • SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE
      • SPI_CRCCALCULATION_DISABLED by  SPI_CRCCALCULATION_DISABLE
      • SPI_CRCCALCULATION_ENABLED by  SPI_CRCCALCULATION_ENABLE
    • Add -use of tmpreg variable in __HAL_SPI_CLEAR_MODFFLAG(), -__HAL_SPI_CLEAR_FREFLAG() and __HAL_SPI_CLEAR_OVRFLAG() macros for compliancy with C++
  • -

    HAL SDMMC update

    • - -

      IS_SDIO_ALL_INSTANCE() - macro moved to CMSIS files

  • HAL LTDC update
    • - -

      HAL_LTDC_ConfigCLUT: optimize the function when -pixel format is LTDC_PIXEL_FORMAT_AL44 

      • Update the size of color look up table to 16 instead of 256 when -the pixel format is LTDC_PIXEL_FORMAT_AL44
        -
  • HAL NAND update
    • Rename NAND Address structure to NAND_AddressTypeDef instead of NAND_AddressTypedef
    • Update -the used algorithm of these functions
      • HAL_NAND_Read_Page()
      • HAL_NAND_Write_Page()
      • HAL_NAND_Read_SpareArea()
      • HAL_NAND_Write_SpareArea()
    • - -

      HAL_NAND_Write_Page(): move -initialization of tickstart before while loop

    • HAL_NAND_Erase_Block(): add whait until NAND status is ready before exiting this function
  • HAL NOR update
    • - -

      Rename NOR Address structure to NOR_AddressTypeDef instead of NOR_AddressTypedef

    • NOR Status literals renamed
      • NOR_SUCCESS by HAL_NOR_STATUS_SUCCESS
      • NOR_ONGOING by HAL_NOR_STATUS_ONGOING
      • NOR_ERROR by HAL_NOR_STATUS_ERROR
      • NOR_TIMEOUT by HAL_NOR_STATUS_TIMEOUT
    • - -

      HAL_NOR_GetStatus() update to fix Timeout issue and exit from waiting loop when timeout occurred

  • HAL PCCARD update
    • Rename PCCARD Address structure to HAL_PCCARD_StatusTypeDef instead of CF_StatusTypedef
    • PCCARD Status literals renamed
      • CF_SUCCESS by HAL_PCCARD_STATUS_SUCCESS
      • CF_ONGOING by HAL_PCCARD_STATUS_ONGOING
      • CF_ERROR by HAL_PCCARD_STATUS_ERROR
      • CF_TIMEOUT by HAL_PCCARD_STATUS_TIMEOUT
    • Update "CF" by "PCCARD" in functions, literals and macros
  • HAL PCD update
    • Rename functions
      • HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup()
      • HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup()
    • Rename literals
      • USB_FS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
      • USB_FS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
      • USB_FS_EXTI_TRIGGER_BOTH_EDGE() by USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
      • USB_HS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 
      • USB_HS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
      • USB_HS_EXTI_TRIGGER_BOTH_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
      • USB_HS_EXTI_LINE_WAKEUP by USB_OTG_HS_EXTI_LINE_WAKEUP
      • USB_FS_EXTI_LINE_WAKEUP by USB_OTG_FS_EXTI_LINE_WAKEUP
    • Rename USB EXTI macros (FS, HS referenced as SUBBLOCK here below) - -
      • __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() -  by  __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()  
      • __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT()
      • __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG() 
      • __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG()
      • __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE()
      • __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
      • __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
      • __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT()  - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GENERATE_SWIT()                                       -
-
  • HAL RNG update
    • Add new functions
      • - - - -

        HAL_RNG_GenerateRandomNumber(): to generate a 32-bits random number, return random value in argument and return HAL -status.

      • - -

        HAL_RNG_GenerateRandomNumber_IT(): to  start generation of the 32-bits random number, user should call the HAL_RNG_ReadLastRandomNumber() function under the HAL_RNG_ReadyCallback() to get the generated random value.

      • HAL_RNG_ReadLastRandomNumber(): to return the last random value stored in the RNG handle

    • HAL_RNG_GetRandomNumber(): return value update -(obsolete), replaced by HAL_RNG_GenerateRandomNumber()
    • - - - -

      HAL_RNG_GetRandomNumber_IT(): wrong implementation (obsolete), replaced by HAL_RNG_GenerateRandomNumber_IT()

    • - -

      __HAL_RNG_CLEAR_FLAG() macro (obsolete), replaced by new __HAL_RNG_CLEAR_IT() macro

    • Add new define for RNG ready interrupt:  RNG_IT_DRDY
  • HAL RTC update
    • HAL_RTC_GetTime() and HAL_RTC_GetDate(): add the comment below
      -
-
-
  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
-   * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
-   * Reading RTC current time locks the values in calendar shadow registers until Current date is read. 
-
-
-
    -
    • Rename literals: add prefix "__HAL"
      • FORMAT_BIN by HAL_FORMAT_BIN
      • FORMAT_BCD by HAL_FORMAT_BCD
    • Rename macros (ALARM, WAKEUPTIMER and TIMESTAMP referenced as SUBBLOCK here below)
      • __HAL_RTC_EXTI_ENABLE_IT() by  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT()
      • __HAL_RTC_EXTI_DISABLE_IT() by  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_IT()
      • - -

        __HAL_RTC_EXTI_CLEAR_FLAG() by  __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG()

      • __HAL_RTC_EXTI_GENERATE_SWIT() by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT()
    • Add new macros (ALARM, WAKEUPTIMER and TAMPER_TIMESTAMP referenced as SUBBLOCK here below)
      • __HAL_RTC_SUBBLOCK_GET_IT_SOURCE() 
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT()
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT()
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE()
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE()
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE()
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE()
      •  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE()
      •  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE()
      •  __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG()
  • HAL SAI update
    • Update SAI_STREOMODE by SAI_STEREOMODE
    • Update FIFO status Level defines in upper case
    • Rename literals: remove "D" from "DISABLED" and "ENABLED"
      • SAI_OUTPUTDRIVE_DISABLED  by SAI_OUTPUTDRIVE_DISABLE
      • SAI_OUTPUTDRIVE_ENABLED  by SAI_OUTPUTDRIVE_ENABLE
      • SAI_MASTERDIVIDER_ENABLED  by SAI_MASTERDIVIDER_ENABLE
      • SAI_MASTERDIVIDER_DISABLED  by SAI_MASTERDIVIDER_DISABLE
    -
-
  • HAL SD update
    • Rename SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS
    • SD_PowerON() updated to add 1ms required power up waiting time before starting the SD initialization sequence
    • SD_DMA_RxCplt()/SD_DMA_TxCplt(): add a call to HAL_DMA_Abort()
    • HAL_SD_ReadBlocks() update to set the defined DATA_BLOCK_SIZE as SDIO DataBlockSize parameter
    • HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() update to call the HAL_DMA_Start_IT() function with DMA Datalength set to BlockSize/4  as the DMA is configured in word 
  • HAL SMARTCARD update 
    • DMA transmit process; the code -has been updated to avoid waiting on TC flag under DMA ISR, SMARTCARD TC interrupt is used instead. Below the -update to be done on user application:
      • Configure and enable -the USART IRQ in HAL_SAMRTCARD_MspInit() function
      • In stm32f4xx_it.c file, UASRTx_IRQHandler() -function: add a call to -HAL_SMARTCARD_IRQHandler() function
    • IT transmit process; the code -has been updated to avoid waiting on TC flag under SMARTCARD ISR, SMARTCARD TC interrupt is used instead. No impact on user application
    • Rename macros: add prefix "__HAL"
      • __SMARTCARD_ENABLE() by __HAL_SMARTCARD_ENABLE()
      • __SMARTCARD_DISABLE() by __HAL_SMARTCARD_DISABLE()
      • __SMARTCARD_ENABLE_IT() by __HAL_SMARTCARD_ENABLE_IT()
      • __SMARTCARD_DISABLE_IT() by __HAL_SMARTCARD_DISABLE_IT()
      • __SMARTCARD_DMA_REQUEST_ENABLE() by __HAL_SMARTCARD_DMA_REQUEST_ENABLE()
      • __SMARTCARD_DMA_REQUEST_DISABLE() by __HAL_SMARTCARD_DMA_REQUEST_DISABLE()
    • Rename literals: remove "D" from "DISABLED" and "ENABLED"
      • SMARTCARD_NACK_ENABLED by SMARTCARD_NACK_ENABLE
      • SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE
    • Add new user macros to manage the sample method feature
      • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE()
      • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE()
    • Add use of tmpreg variable in __HAL_SMARTCARD_CLEAR_PEFLAG() macro for compliancy with C++
    • HAL_SMARTCARD_Transmit_DMA() update to follow the right procedure "Transmission using DMA"  in the reference manual
      • Add clear the TC flag in the SR register before enabling the DMA transmit request
  • HAL TIM update
    • Add TIM_CHANNEL_ALL as possible value for all Encoder Start/Stop APIs Description
    • HAL_TIM_OC_ConfigChannel() remove call to IS_TIM_FAST_STATE() assert macro
    • HAL_TIM_PWM_ConfigChannel() add a call to IS_TIM_FAST_STATE() assert macro to check the OCFastMode parameter
    • HAL_TIM_DMADelayPulseCplt() Update to set the TIM Channel before to call  HAL_TIM_PWM_PulseFinishedCallback()
    • HAL_TIM_DMACaptureCplt() update to set the TIM Channel before to call  HAL_TIM_IC_CaptureCallback()
    • TIM_ICx_ConfigChannel() update to fix Timer CCMR1 register corruption when setting ICFilter parameter
    • HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() update to abort the DMA transfer for the specifc TIM channel
    • Add new function for TIM Slave configuration in IT mode: HAL_TIM_SlaveConfigSynchronization_IT() 
    • HAL_TIMEx_ConfigBreakDeadTime() add an assert check on Break & DeadTime parameters values
    • HAL_TIMEx_OCN_Start_IT() add the enable of Break Interrupt for all output modes
    • Add new macros to ENABLE/DISABLE URS bit in TIM CR1 register:
      • __HAL_TIM_URS_ENABLE()
      • __HAL_TIM_URS_DISABLE()
    • Add new macro for TIM Edge modification: __HAL_TIM_SET_CAPTUREPOLARITY()
  • HAL UART update
    • - -

      Add IS_LIN_WORD_LENGTH() and IS_LIN_OVERSAMPLING()  macros: to -check respectively WordLength and OverSampling parameters in LIN mode

    • DMA transmit process; the code -has been updated to avoid waiting on TC flag under DMA ISR, UART TC interrupt is used instead. Below the -update to be done on user application:

      • Configure and enable -the USART IRQ in HAL_UART_MspInit() function
      • In stm32f4xx_it.c file, USARTx_IRQHandler() -function: add a call to -HAL_UART_IRQHandler() function
    • IT transmit process; the code -has been updated to avoid waiting on TC flag under UART ISR, UART TC interrupt is used instead. No impact on user application
    • Rename macros:
      • __HAL_UART_ONEBIT_ENABLE() by __HAL_UART_ONE_BIT_SAMPLE_ENABLE()
      • __HAL_UART_ONEBIT_DISABLE() by __HAL_UART_ONE_BIT_SAMPLE_DISABLE()
    • Rename literals:
      • UART_WAKEUPMETHODE_IDLELINE by UART_WAKEUPMETHOD_IDLELINE
      • UART_WAKEUPMETHODE_ADDRESSMARK by UART_WAKEUPMETHOD_ADDRESSMARK
    • Add use of tmpreg variable in __HAL_UART_CLEAR_PEFLAG() macro for compliancy with C++
    • HAL_UART_Transmit_DMA() update to follow the right procedure "Transmission using DMA" in the reference manual
      • Add clear the TC flag in the SR register before enabling the DMA transmit request
  • HAL USART update

    • DMA transmit process; the code -has been updated to avoid waiting on TC flag under DMA ISR, USART TC interrupt is used instead. Below the -update to be done on user application:

      • Configure and enable -the USART IRQ in HAL_USART_MspInit() function
      • In stm32f4xx_it.c file, USARTx_IRQHandler() -function: add a call to -HAL_USART_IRQHandler() function
    • IT transmit process; the code -has been updated to avoid waiting on TC flag under USART ISR, USART TC interrupt is used instead. No impact on user application
    • HAL_USART_Init() update to enable the USART oversampling by 8 by default in order to reach max USART frequencies
    • USART_DMAReceiveCplt() update to set the new USART state after checking on the old state
    • HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() update to follow the right procedure "Transmission using DMA"  in the reference manual
      • Add clear the TC flag in the SR register before enabling the DMA transmit request
    • Rename macros:
      • __USART_ENABLE() by __HAL_USART_ENABLE()
      • __USART_DISABLE() by __HAL_USART_DISABLE()
      • __USART_ENABLE_IT() by __HAL_USART_ENABLE_IT()
      • __USART_DISABLE_IT() by __HAL_USART_DISABLE_IT()
    • Rename literals: remove "D" from "DISABLED" and "ENABLED"
      • USART_CLOCK_DISABLED by USART_CLOCK_DISABLE
      • USART_CLOCK_ENABLED by USART_CLOCK_ENABLE
      • USARTNACK_ENABLED by USART_NACK_ENABLE
      • USARTNACK_DISABLED by USART_NACK_DISABLE
    • Add new user macros to manage the sample method feature
      • __HAL_USART_ONE_BIT_SAMPLE_ENABLE()
      • __HAL_USART_ONE_BIT_SAMPLE_DISABLE()
    • Add use of tmpreg variable in __HAL_USART_CLEAR_PEFLAG() macro for compliancy with C++
  • HAL WWDG update
    • Add new parameter in __HAL_WWDG_ENABLE_IT() macro
    • Add new macros -to manage WWDG IT & correction:
      • __HAL_WWDG_DISABLE()
      • __HAL_WWDG_DISABLE_IT()
      • __HAL_WWDG_GET_IT()
      • __HAL_WWDG_GET_IT_SOURCE()
    - - - -

    V1.1.0 / 19-June-2014

    - -

    Main Changes

    - - - - - - -
    • Add support of STM32F411xE devices
    -
      -
    • HAL generic update
      • -
        -
      • Enhance HAL delay and time base implementation
        -
        • -
      -
        -
          -
        • Systick -timer is used by default as source of time base, but user can -eventually implement his proper time base source (a general purpose -timer for example or other time source)
          • -
        -
      -
        -
          -
        • Functions -affecting time base configurations are declared as __Weak to make -override possible in case of other implementations in user file, for -more details please refer to HAL_TimeBase example
          • -
        -
      -
        -
      • Fix flag clear procedure: use atomic write operation "=" instead of ready-modify-write operation "|=" or "&="
        • -
      -
        -
      • Fix -on Timeout management, Timeout value set to 0 passed to API -automatically exits the function after checking the flag without any -wait
        • -
      -
        -
      • Common update for the following communication peripherals: SPI, UART, USART and IRDA
        • -
      -
        -
          -
        • Add DMA circular mode support
          • -
        -
      -
        -
          -
        • Remove lock from recursive process
          • -
        -
      -
        -
      • Add new macro __HAL_RESET_HANDLE_STATE to reset a given handle state
        • -
      -
        -
      • Add a new attribute for functions executed from internal SRAM and depending from Compiler implementation
        • -
      -
        -
      • When USE_RTOS == 1 (in stm32l0xx_hal_conf.h), the __HAL_LOCK() is not defined instead of being defined empty
        • -
      - -
        -
      • Miscellaneous comments and formatting update
        -
        • -
      -
        -
      • stm32f4xx_hal_conf_template.h
        • -
      -
        -
          -
        • Add a new define for LSI default value LSI_VALUE
          • -
        -
      -
        -
          -
        • Add a new define for LSE default value LSE_VALUE
          • -
        -
      -
        -
          -
        • Add a new define for Tick interrupt priority TICK_INT_PRIORITY (needed for the enhanced time base implementation)
          • -
        -
      • Important Note: aliases has been added for any API naming change, to keep compatibility with previous version
        • - -
      -
    • HAL GPIO update
      • -
        -
      • Add a new macro - __HAL_GPIO_EXTI_GENERATE_SWIT() to manage the generation of software interrupt - on selected EXTI line
        • -
      • HAL_GPIO_Init(): -use temporary variable when modifying the registers, to avoid -unexpected transition in the GPIO pin configuration
        -
        • -
      • Remove IS_GET_GPIO_PIN macro
        • -
      • Add a new function HAL_GPIO_LockPin()
        • -
      • Private Macro __HAL_GET_GPIO_SOURCE renamed into GET_GPIO_SOURCE
        • -
      • Add the support of STM32F411xx devices : add the new Alternate functions values related to new remap added for SPI, USART, I2C
        -
        • -
      • Update the following HAL GPIO macros description: rename EXTI_Linex by GPIO_PIN_x
        • -
          -
        • __HAL_GPIO_EXTI_CLEAR_IT()
          • -
        • __HAL_GPIO_EXTI_GET_IT()
          • -
        • __HAL_GPIO_EXTI_CLEAR_FLAG()
          • -
        • __HAL_GPIO_EXTI_GET_FLAG()
          • -
      -
    • -

      HAL DMA update

      • -
        -
      • Fix in HAL_DMA_PollForTransfer() to:
        • -
          -
        • set DMA error code in case of HAL_ERROR status
          -
          • -
        • set HAL Unlock before DMA state update
          • -
        -
      -
    • -

      HAL DMA2D update

      • -
        -
      • Add configuration of source address in case of A8 or A4 M2M_PFC DMA2D mode
        • -
      -
    • HAL FLASH update
      • -
    - - -
      -
      • Functions reorganization update, depending on the features supported by each STM32F4 device
        • -
      • Add new driver (stm32f4xx_hal_flash_ramfunc.h/.c) to manage function - executed from RAM, these functions are available only for STM32F411xx - Devices
        • -
          -
        • FLASH_StopFlashInterfaceClk()  : Stop the flash interface while System - Run
          • -
        • FLASH_StartFlashInterfaceClk() : - Stop the flash interface while System Run
        • FLASH_EnableFlashSleepMode() : - Enable the flash sleep while System Run
        • FLASH_DisableFlashSleepMode() - :  Disable the flash sleep while - System Run
          • -
        -
      -
    - - - - -
      -
    • HAL PWR update
      • -
    -
      -
        -
      • HAL_PWR_PVDConfig(): add clear of the EXTI trigger before new configuration
        -
        • -
      • Fix -in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which -need to be cleared at application level before to call this function
        • - -
      • HAL_PWR_EnterSLEEPMode()
        • -
          -
        • Remove disable and enable of SysTick Timer
          • -
        • Update -usage of __WFE() in low power entry function: if there is a pending -event, calling __WFE() will not enter the CortexM4 core to sleep mode. -The solution is to made the call below; the first __WFE() is always -ignored and clears the event if one was already pending, the second is -always applied
          -
          • -
        -
    -
    __SEV()
    - __WFE()
    - __WFE()
    -
      -
        -
      • Add new macro for software event generation __HAL_PVD_EXTI_GENERATE_SWIT()
        • - -
      • Remove -the following defines form Generic driver and add them under extension -driver because they are only used within extension functions.
        • -
          -
        • CR_FPDS_BB: used within HAL_PWREx_EnableFlashPowerDown() function
          • -
        -
          -
        • CSR_BRE_BB: used within HAL_PWREx_EnableBkUpReg() function
          • -
        -
      • Add the support of STM32F411xx - devices add the define STM32F411xE
        • -
          -
        • For STM32F401xC, STM32F401xE and - STM32F411xE devices add the following functions used to enable or disable - the low voltage mode for regulators
          • -
        -
          • HAL_PWREx_EnableMainRegulatorLowVoltage()
          • HAL_PWREx_DisableMainRegulatorLowVoltage()
          • HAL_PWREx_EnableLowRegulatorLowVoltage()
          • HAL_PWREx_DisableLowRegulatorLowVoltage()
        -
      • For STM32F42xxx/43xxx devices, - add a new function for Under Driver management as the macro already added - for this mode is not sufficient: HAL_PWREx_EnterUnderDriveSTOPMode()
        • - -
      - -
    -
    • HAL RCC update
        • -
      • In HAL_RCC_ClockConfig() - function: update the AHB clock divider before clock switch to new source
        • -
      • Allow to calibrate the HSI when it is used as system clock source
        -
        • -
      • Rename the following macros
        • -
          -
        • __OTGFS_FORCE_RESET ()  by __USB_OTG_FS_FORCE_RESET()
          • -
        • __OTGFS_RELEASE_RESET ()  by  - __USB_OTG_FS_RELEASE_RESET()
          • -
        • __OTGFS_CLK_SLEEP_ENABLE ()  by  - __USB_OTG_FS_CLK_SLEEP_ENABLE()
          • -
        • __OTGFS_CLK_SLEEP_DISABLE () - by  - __USB_OTG_FS_CLK_SLEEP_DISABLE()
          • -
        -
    -
      -
      • Add new field PLLI2SM in - RCC_PLLI2SInitTypeDef structure, this division factor is added for PLLI2S - VCO input clock only STM32F411xE devices => the FW compatibility is - broken vs. STM32F401xx devices
      • Update HAL_RCCEx_PeriphCLKConfig() and  HAL_RCCEx_GetPeriphCLKConfig()  functions to support the new PLLI2SM
      • Add new function to manage the - new LSE mode : HAL_RCCEx_SelectLSEMode()
      • Reorganize the macros depending - from Part number used and make them more clear
      -
    - -
      -
    • -

      HAL UART update

      - -
      • Add new macros to control CTS and RTS
         -
      • Add specific macros -to manage the flags cleared only by a software sequence -
        • __HAL_UART_CLEAR_PEFLAG() -
        -
        • __HAL_UART_CLEAR_FEFLAG() -
        -
        • __HAL_UART_CLEAR_NEFLAG() -
        -
        • __HAL_UART_CLEAR_OREFLAG() -
        • __HAL_UART_CLEAR_IDLEFLAG() -
        -
      • Add several -enhancements without affecting the driver functionalities -
        • Remove the check on -RXNE set after reading the Data in the DR register
        -
        • Update the transmit -processes to use TXE instead of TC -
        • Update HAL_UART_Transmit_IT() to enable UART_IT_TXE instead of UART_IT_TC
      -
      • -
    • -

      HAL USART update

      -
      • Add specific macros -to manage the flags cleared only by a software sequence -
        • __HAL_USART_CLEAR_PEFLAG() -
        -
        • __HAL_USART_CLEAR_FEFLAG() -
        -
        • __HAL_USART_CLEAR_NEFLAG() -
        -
        • __HAL_USART_CLEAR_OREFLAG() -
        -
        • __HAL_USART_CLEAR_IDLEFLAG()
        -
      • Update -HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC
      -
    • -

      HAL IRDA update

      -
      • Add specific macros -to manage the flags cleared only by a software sequence -
        • __HAL_IRDA_CLEAR_PEFLAG() -
        • __HAL_ IRDA -_CLEAR_FEFLAG() -
        • __HAL_ IRDA -_CLEAR_NEFLAG() -
        • __HAL_ IRDA -_CLEAR_OREFLAG() -
        • __HAL_ IRDA -_CLEAR_IDLEFLAG()
        -
      • Add several -enhancements without affecting the driver functionalities -
        • Remove the check on -RXNE set after reading the Data in the DR register
          -
        • Update HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC
        -
      • Add the following -APIs used within DMA process -
        • HAL_StatusTypeDef -HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
        -
        • HAL_StatusTypeDef -HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); -
        • HAL_StatusTypeDef -HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); -
        • void -HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); -
        • void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef -*hirda);
      -
    • -

      HAL SMARTCARD update

      -
      • Add specific macros -to manage the flags cleared only by a software sequence -
        • __HAL_SMARTCARD_CLEAR_PEFLAG() -
        -
        • __HAL_SMARTCARD_CLEAR_FEFLAG() -
        -
        • __HAL_SMARTCARD_CLEAR_NEFLAG() -
        -
        • __HAL_SMARTCARD_CLEAR_OREFLAG() -
        -
        • __HAL_SMARTCARD_CLEAR_IDLEFLAG() -
        -
      • Add several -enhancements without affecting the driver functionalities -
        • Add a new state -HAL_SMARTCARD_STATE_BUSY_TX_RX and all -processes has been updated accordingly
        -
          -
        • Update -HAL_SMARTCARD_Transmit_IT() to enable -SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC -
          • -
    -
    • HAL SPI update -
      • Bugs fix -
        • SPI interface is -used in synchronous polling mode: at high clock rates like SPI prescaler 2 and -4, calling
          HAL_SPI_TransmitReceive() returns with error HAL_TIMEOUT           -
        • HAL_SPI_TransmitReceive_DMA() does not clean -up the TX DMA, so any subsequent SPI calls return the DMA error -
        • HAL_SPI_Transmit_DMA() is failing when data -size is equal to 1 byte
        -
      • Add the following -APIs used within the DMA process
      -
        • HAL_StatusTypeDef -HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
        • HAL_StatusTypeDef -HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
        • HAL_StatusTypeDef -HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
        • void -HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
        • void -HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
        • void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef -*hspi);
    -
      -
    • HAL RNG update
      • -
        -
        • - - - -Add a conditional define to make - this driver visible for all STM32F4xx devices except STM32F401xx and - STM32F411xx Devices.
          -
        -
      -
    • HAL CRC update
      • -
        -
        • - - - -These macros are added to read/write the CRC IDR register: __HAL_CRC_SET_IDR() and __HAL_CRC_GET_IDR()
        -
      -
      -
    • HAL DAC update
      • -
        -
      • Enhance the DMA channel - configuration when used with DAC
        • -
      -
    • HAL TIM update
      • -
        - -
      • HAL_TIM_IRQHandler(): update to check the input capture channel 3 and 4 in CCMR2 instead of CCMR1
        • -
      • __HAL_TIM_PRESCALER() updated to use '=' instead of '|='
        -
        • -
      • Add the - following macro in TIM HAL driver
        • - -
      -
        • __HAL_TIM_GetCompare()
        • __HAL_TIM_GetCounter()
        • __HAL_TIM_GetAutoreload()
        • __HAL_TIM_GetClockDivision()
        • __HAL_TIM_GetICPrescaler()
      - -
    • HAL SDMMC update
      • -
        -
      • Use of CMSIS constants instead of magic values
        -
        • -
      • Miscellaneous update in functions internal coding
        -
        • -
      -
    • HAL NAND update
      • -
        -
      • Fix issue of macros returning wrong address for NAND blocks
        • -
      • Fix issue for read/write NAND page/spare area
        • -
      -
    • HAL NOR update
      • -
        -
      • Add the NOR address - bank macro used within the API
      • Update NOR API - implementation to avoid the use of NOR address bank hard coded
        • -
      - -
    • HAL HCD update
      • -
        -
      • HCD_StateTypeDef structure members renamed
        • -
      • These macro are renamed
        • -
          -
        • __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__)    by __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
          • -
        -
          -
        • __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) 
          -
          • -
        -
          -
        • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  by __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) 
          -
          • -
        -
      -
    • HAL PCD update
      • - -
        -
      • HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() renamed into HAL_PCDEx_SetTxFiFo() and HAL_PCDEx_SetRxFiFo() and moved to the extension files stm32f4xx_hal_pcd_ex.h/.c
        -
        • -
      • PCD_StateTypeDef structure members renamed
        • -
      • Fix incorrect masking of TxFIFOEmpty
        -
        • -
      • stm32f4xx_ll_usb.c: fix issue in HS mode
        -
        • -
      • New macros added
        -
        • -
          -
        • __HAL_PCD_IS_PHY_SUSPENDED()
          • -
        -
          -
        • __HAL_USB_HS_EXTI_GENERATE_SWIT()
          • -
        -
          -
        • __HAL_USB_FS_EXTI_GENERATE_SWIT()
          • -
        -
      • These macro are renamed
        • -
          -
        • __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__)    by __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)
          • -
        -
          -
        • __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) 
          -
          • -
        -
          -
        • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  by __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) 
          -
          • -
        -
          -
        • __HAL_PCD_UNGATE_CLOCK(__HANDLE__) by __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
          • -
        -
          -
        • __HAL_PCD_GATE_CLOCK(__HANDLE__) by __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)
          • -
        -
      -
    • HAL ETH update
      • -
        -
      • Update HAL_ETH_GetReceivedFrame_IT() function to return HAL_ERROR if the received packet is not complete
        • - -
      • Use HAL_Delay() instead of counting loop
        -
        • -
      •  __HAL_ETH_MAC_CLEAR_FLAG() macro is removed: the MACSR register is read only
        • -
      • Add the following macros used to - Wake up the device from STOP mode by Ethernet event :
        • - -
          -
        • __HAL_ETH_EXTI_ENABLE_IT()
          • -
        • __HAL_ETH_EXTI_DISABLE_IT()
          • -
        • __HAL_ETH_EXTI_GET_FLAG()
          • -
        • __HAL_ETH_EXTI_CLEAR_FLAG()
          • -
        • __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER()
          • -
        • __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER()
          • -
        • __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER()
          • -
        - -
      -
    • HAL WWDG update
      -
      • -
        -
      • Update macro parameters to use underscore: __XXX__
        • -
      -
        -
      • Use of CMSIS constants instead of magic values
        -
        • -
      -
        -
      • Use MODIFY_REG macro in HAL_WWDG_Init()
        • -
      -
        -
      • Add IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() and HAL_WWDG_DeInit()
        • -
      -
    • HAL IWDG update
      • -
        -
      • Use WRITE_REG instead of SET_BIT for all IWDG macros
        • -
      -
        -
      • __HAL_IWDG_CLEAR_FLAG removed: no IWDG flag cleared by access to SR register
        • -
      -
        -
      • Use MODIFY_REG macro in HAL_IWDG_Init()
        • -
      -
        -
      • Add IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init()Add the following macros used to - Wake
        • -
      - -
    -

    V1.0.0 / 18-February-2014

    - -

    Main Changes

    - - - - - - -
      -
    • First official release

    License

    -
    -
    -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
    -     -
    1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
    2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
    3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived
      -       -
    -        from this software without specific prior written permission.
    -
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    - - \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h index 2ebaffc092..0ae9d0b248 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h @@ -2,9 +2,7 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 - * @brief This file contains aliases definition for the STM32Cube HAL constants + * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention @@ -60,7 +58,7 @@ /** * @} */ - + /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ @@ -92,10 +90,10 @@ #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 @@ -111,21 +109,21 @@ #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 /** * @} */ - + /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} - */ - + */ + /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ @@ -138,7 +136,9 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -154,7 +154,7 @@ #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - + #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT @@ -226,7 +226,7 @@ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ - + #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE @@ -255,28 +255,27 @@ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - + + + /** * @} */ @@ -284,7 +283,7 @@ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ - + #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD @@ -360,11 +359,11 @@ /** * @} */ - + /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ - + #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 @@ -377,12 +376,12 @@ /** * @} */ - + /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -400,7 +399,7 @@ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ - + #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** @@ -432,18 +431,18 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) @@ -457,6 +456,78 @@ * @} */ +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) + #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE + #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE + #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET + #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET + #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE + #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE + + #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 + #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + + #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX + #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 + #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 + #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + + #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT + #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING + #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING + #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + + +#endif /* STM32H7 */ + + +/** + * @} + */ + + /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ @@ -469,7 +540,7 @@ #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - + #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD @@ -542,7 +613,7 @@ #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ @@ -572,7 +643,7 @@ /** * @} */ - + /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ @@ -596,11 +667,11 @@ #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - + #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 @@ -609,14 +680,14 @@ #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + /** * @} */ @@ -625,7 +696,7 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) +#if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** @@ -637,18 +708,18 @@ */ /* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD @@ -661,31 +732,27 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ - + #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 @@ -693,15 +760,15 @@ #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 /** * @} */ - + /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ @@ -722,7 +789,7 @@ * @} */ - + /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ @@ -740,7 +807,7 @@ /** * @} */ - + /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ @@ -756,13 +823,13 @@ /** * @} */ - + /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - + #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR @@ -863,7 +930,7 @@ * @} */ - + /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ @@ -903,7 +970,7 @@ /** * @} */ - + /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ @@ -928,7 +995,7 @@ #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U - + #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ @@ -946,9 +1013,12 @@ #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ @@ -960,7 +1030,7 @@ /** * @} */ - + /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ @@ -975,39 +1045,39 @@ /** * @} - */ - + */ + #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 /** * @} - */ + */ #endif /* STM32L4 || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1020,11 +1090,11 @@ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} - */ + */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish @@ -1034,12 +1104,12 @@ /*HASH Algorithm Selection*/ -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY @@ -1047,7 +1117,7 @@ /** * @} */ - + /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ @@ -1128,6 +1198,8 @@ #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER @@ -1141,17 +1213,17 @@ #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - + /** * @} - */ - + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ @@ -1162,7 +1234,7 @@ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} - */ + */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ @@ -1174,31 +1246,31 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ - + /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback #define HAL_LTDC_Relaod HAL_LTDC_Reload #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} - */ - - + */ + + /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1213,8 +1285,8 @@ #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} - */ - + */ + /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ @@ -1223,7 +1295,7 @@ #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK @@ -1231,6 +1303,7 @@ #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 @@ -1242,7 +1315,7 @@ * @} */ - + /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ @@ -1312,7 +1385,6 @@ #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL @@ -1339,7 +1411,7 @@ /** * @} */ - + /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ @@ -1412,7 +1484,7 @@ #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK - + #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -1599,7 +1671,7 @@ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) - + /** * @} */ @@ -1618,11 +1690,11 @@ /** * @} */ - + /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START #if defined(STM32F1) @@ -1645,11 +1717,11 @@ /** * @} */ - + /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ - + #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT @@ -1660,7 +1732,7 @@ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ - + #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE @@ -1669,7 +1741,7 @@ #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** @@ -1698,8 +1770,8 @@ /** * @} */ - - + + /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ @@ -1764,7 +1836,7 @@ #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else @@ -1772,37 +1844,37 @@ #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ -/** +/** * @} - */ - - + */ + + /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ - + #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE @@ -1819,7 +1891,7 @@ #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE @@ -2047,6 +2119,21 @@ #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE @@ -2238,13 +2325,13 @@ #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE @@ -2297,111 +2384,111 @@ #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE @@ -2409,29 +2496,28 @@ #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET @@ -2447,8 +2533,6 @@ #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE @@ -2470,8 +2554,6 @@ #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET @@ -2635,7 +2717,7 @@ #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32F7) @@ -2643,6 +2725,30 @@ #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG @@ -2696,7 +2802,12 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) +#else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL @@ -2812,17 +2923,19 @@ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ - +#if defined (STM32G0) +#else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT @@ -2858,7 +2971,7 @@ #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION @@ -2883,26 +2996,26 @@ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS -#if defined(STM32F4) +#if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn @@ -2911,8 +3024,8 @@ #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT @@ -2942,6 +3055,16 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#endif /** * @} */ @@ -2960,7 +3083,7 @@ #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} @@ -2992,7 +3115,7 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ @@ -3004,8 +3127,8 @@ #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} @@ -3110,7 +3233,7 @@ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG @@ -3119,7 +3242,7 @@ #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** @@ -3156,11 +3279,22 @@ * @} */ +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ - + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c index 9a0621de61..534c6852d6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -68,11 +66,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.7.1 + * @brief STM32F4xx HAL Driver version number V1.7.3 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ @@ -86,19 +84,19 @@ /* --- MEMRMP Register ---*/ /* Alias word address of UFB_MODE bit */ #define MEMRMP_OFFSET SYSCFG_OFFSET -#define UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE) +#define UFB_MODE_BIT_NUMBER SYSCFG_MEMRMP_UFB_MODE_Pos #define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) /* --- CMPCR Register ---*/ /* Alias word address of CMP_PD bit */ #define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U) -#define CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD) +#define CMP_PD_BIT_NUMBER SYSCFG_CMPCR_CMP_PD_Pos #define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U)) /* --- MCHDLYCR Register ---*/ /* Alias word address of BSCKSEL bit */ #define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U) -#define BSCKSEL_BIT_NUMBER POSITION_VAL(SYSCFG_MCHDLYCR_BSCKSEL) +#define BSCKSEL_BIT_NUMBER SYSCFG_MCHDLYCR_BSCKSEL_Pos #define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U)) /** * @} @@ -110,6 +108,8 @@ * @{ */ __IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ @@ -125,16 +125,16 @@ __IO uint32_t uwTick; * @verbatim =============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initializes the Flash interface the NVIC allocation and initial clock configuration. It initializes the systick also when timeout is needed and the backup domain when enabled. - (+) de-Initializes common part of the HAL - (+) Configure The time base source to have 1ms time base with a dedicated + (+) De-Initializes common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user + (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and @@ -174,23 +174,29 @@ HAL_StatusTypeDef HAL_Init(void) { /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) - __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) - __HAL_FLASH_DATA_CACHE_ENABLE(); + __HAL_FLASH_DATA_CACHE_ENABLE(); #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ + /* Set Interrupt Group Priority */ +/* MBED : moved to HAL_InitPre() */ +#if !defined (TARGET_STM32F429xI) + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); +#endif + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); - + /* Init the low level hardware */ HAL_MspInit(); - + /* Return function status */ return HAL_OK; } @@ -226,12 +232,12 @@ HAL_StatusTypeDef HAL_DeInit(void) } /** - * @brief Initializes the MSP. + * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } @@ -242,7 +248,7 @@ __weak void HAL_MspInit(void) */ __weak void HAL_MspDeInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } @@ -256,20 +262,31 @@ __weak void HAL_MspDeInit(void) * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) + * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock/1000U); + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } /* Return function status */ return HAL_OK; @@ -306,14 +323,14 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. + * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - uwTick++; + uwTick += uwTickFreq; } /** @@ -327,6 +344,44 @@ __weak uint32_t HAL_GetTick(void) return uwTick; } +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + /** * @brief This function provides minimum delay (in milliseconds) based * on variable incremented. @@ -335,20 +390,20 @@ __weak uint32_t HAL_GetTick(void) * is incremented. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. - * @param Delay: specifies the delay time length, in milliseconds. + * @param Delay specifies the delay time length, in milliseconds. * @retval None */ -__weak void HAL_Delay(__IO uint32_t Delay) +__weak void HAL_Delay(uint32_t Delay) { uint32_t tickstart = HAL_GetTick(); uint32_t wait = Delay; - - /* Add a period to guarantee minimum wait */ + + /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) { - wait++; + wait += (uint32_t)(uwTickFreq); } - + while((HAL_GetTick() - tickstart) < wait) { } @@ -392,7 +447,7 @@ __weak void HAL_ResumeTick(void) */ uint32_t HAL_GetHalVersion(void) { - return __STM32F4xx_HAL_VERSION; + return __STM32F4xx_HAL_VERSION; } /** @@ -401,7 +456,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE) >> 16U); + return((DBGMCU->IDCODE) >> 16U); } /** @@ -410,7 +465,7 @@ uint32_t HAL_GetREVID(void) */ uint32_t HAL_GetDEVID(void) { - return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); } /** @@ -491,7 +546,7 @@ void HAL_DisableCompensationCell(void) /** * @brief Return the unique device identifier (UID based on 96 bits) - * @param UID: pointer to 3 words array. + * @param UID pointer to 3 words array. * @retval Device identifier */ void HAL_GetUID(uint32_t *UID) @@ -530,7 +585,6 @@ void HAL_EnableMemorySwappingBank(void) */ void HAL_DisableMemorySwappingBank(void) { - *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE; } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h index b06d79824f..6e0019c94a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** @@ -58,6 +56,28 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** + * @} + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup HAL_Exported_Macros HAL Exported Macros * @{ @@ -183,6 +203,16 @@ * @} */ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions * @{ @@ -190,8 +220,7 @@ /** @addtogroup HAL_Exported_Functions_Group1 * @{ */ -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_InitPre(void); +/* Initialization and Configuration functions ******************************/ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); @@ -206,8 +235,11 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); */ /* Peripheral Control functions ************************************************/ void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); +void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c index 3f04fc363d..d67cff8e59 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions @@ -251,7 +249,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); * External trigger source and edge, DMA continuous request after the * last transfer and End of conversion selection). * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -329,7 +327,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -376,7 +374,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /** * @brief Initializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -391,7 +389,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /** * @brief DeInitializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -430,7 +428,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /** * @brief Enables ADC and starts conversion of the regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -536,7 +534,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) * * @note Caution: This function will stop also injected channels. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. @@ -579,9 +577,9 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -660,13 +658,13 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /** * @brief Poll for conversion event - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param EventType: the ADC event type. + * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. * @arg ADC_OVR_EVENT: ADC Overrun event. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) @@ -727,7 +725,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /** * @brief Enables the interrupt and starts ADC conversion of regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ @@ -836,7 +834,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) * * @note Caution: This function will stop also injected channels. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ @@ -873,7 +871,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) /** * @brief Handles ADC interrupt request - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1016,10 +1014,10 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /** * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -1143,7 +1141,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /** * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -1189,7 +1187,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Gets the converted value from data register of regular channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval Converted value */ @@ -1201,7 +1199,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) /** * @brief Regular conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1216,7 +1214,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Regular conversion half DMA transfer callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1231,7 +1229,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1252,7 +1250,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" * (this function is also clearing overrun flag) - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1289,9 +1287,9 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) /** * @brief Configures for the selected ADC regular channel its corresponding * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfig: ADC configuration structure. + * @param sConfig ADC configuration structure. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) @@ -1400,9 +1398,9 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure + * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure * that contains the configuration information of ADC analog watchdog. * @retval HAL status */ @@ -1484,7 +1482,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /** * @brief return the ADC state - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL state */ @@ -1496,7 +1494,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) /** * @brief Return the ADC error code - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval ADC Error Code */ @@ -1516,7 +1514,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) /** * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct without initializing the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1604,7 +1602,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1657,7 +1655,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1670,7 +1668,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.h index 851e2bd4f5..5b80503859 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention @@ -455,60 +453,60 @@ typedef struct */ /** @brief Reset ADC handle state - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) /** * @brief Enable the ADC peripheral. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) /** * @brief Disable the ADC peripheral. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) /** * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: ADC Interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC Interrupt. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) /** * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: ADC interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC interrupt. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) /** @brief Check if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: specifies the ADC interrupt source to check. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ specifies the ADC interrupt source to check. * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Clear the ADC's pending flags. - * @param __HANDLE__: specifies the ADC Handle. - * @param __FLAG__: ADC flag. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. * @retval None */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** * @brief Get the selected ADC's flag status. - * @param __HANDLE__: specifies the ADC Handle. - * @param __FLAG__: ADC flag. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) @@ -616,7 +614,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) \ @@ -626,7 +624,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Test if conversion trigger of regular group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ @@ -635,7 +633,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Test if conversion trigger of injected group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ @@ -652,7 +650,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ @@ -742,89 +740,89 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Set ADC Regular channel sequence length. - * @param _NbrOfConversion_: Regular channel sequence length. + * @param _NbrOfConversion_ Regular channel sequence length. * @retval None */ #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) /** * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_: Continuous mode. + * @param _CONTINUOUS_MODE_ Continuous mode. * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U) /** * @brief Configures the number of discontinuous conversions for the regular group channels. - * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions. + * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. * @retval None */ -#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM)) +#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos) /** * @brief Enable ADC scan mode. - * @param _SCANCONV_MODE_: Scan conversion mode. + * @param _SCANCONV_MODE_ Scan conversion mode. * @retval None */ #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U) /** * @brief Enable the ADC end of conversion selection. - * @param _EOCSelection_MODE_: End of conversion selection mode. + * @param _EOCSelection_MODE_ End of conversion selection mode. * @retval None */ #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U) /** * @brief Enable the ADC DMA continuous request. - * @param _DMAContReq_MODE_: DMA continuous request mode. + * @param _DMAContReq_MODE_ DMA continuous request mode. * @retval None */ #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U) /** * @brief Return resolution bits in CR1 register. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.c index 7f7817358a..5f3a039edd 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions @@ -170,7 +168,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); /** * @brief Enables the selected ADC software start conversion of the injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -264,7 +262,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /** * @brief Enables the interrupt and starts ADC conversion of injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. @@ -369,7 +367,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note In case of auto-injection mode, HAL_ADC_Stop must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) @@ -421,9 +419,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /** * @brief Poll for injected conversion complete - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -490,7 +488,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) @@ -545,9 +543,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /** * @brief Gets the converted value from data register of injected channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param InjectedRank: the ADC injected rank. + * @param InjectedRank the ADC injected rank. * This parameter can be one of the following values: * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected @@ -600,10 +598,10 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa * * @note Caution: This function must be used only with the ADC master. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -721,7 +719,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /** * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -774,7 +772,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results * data in the selected multi mode. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval The converted data value. */ @@ -793,7 +791,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) /** * @brief Injected conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -809,9 +807,9 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Configures for the selected ADC injected channel its corresponding * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfigInjected: ADC configuration structure for injected channel. + * @param sConfigInjected ADC configuration structure for injected channel. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) @@ -972,9 +970,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /** * @brief Configures the ADC multi-mode - * @param hadc : pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param multimode : pointer to an ADC_MultiModeTypeDef structure that contains + * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains * the configuration information for multimode. * @retval HAL status */ @@ -1021,7 +1019,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1074,7 +1072,7 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1087,7 +1085,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.h index 7717364629..523eaae090 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention @@ -232,10 +230,14 @@ typedef struct #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + defined(STM32F412Cx) #define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx || - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18) +#endif /* STM32F413xx || STM32F423xx */ #if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) @@ -377,9 +379,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @brief Set the selected injected Channel rank. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @param _JSQR_JL_: Sequence length. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @param _JSQR_JL_ Sequence length. * @retval None */ #define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_)))) @@ -387,7 +389,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1 * if available (ADC2, ADC3 availability depends on STM32 product) - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval Common control register ADC123 or ADC1 */ #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.c index d6aa756d16..10dc178d0e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.c @@ -2,82 +2,135 @@ ****************************************************************************** * @file stm32f4xx_hal_can.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 - * @brief This file provides firmware functions to manage the following + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions * + Peripheral State and Error functions * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 - and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3 - -@- In case you are using CAN2 only, you have to enable the CAN1 clock. - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - __GPIOx_CLK_ENABLE() - (++) Connect and configure the involved CAN pins to AF9 using the - following function HAL_GPIO_Init() - - (#) Initialize and configure the CAN using CAN_Init() function. - - (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() - (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. - - (#) Receive a CAN frame using HAL_CAN_Receive() function. + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. - (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be trigged by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the CAN peripheral transmission and wait the end of this operation - using HAL_CAN_Transmit(), at this stage user can specify the value of timeout - according to his end application - (+) Start the CAN peripheral reception and wait the end of this operation - using HAL_CAN_Receive(), at this stage user can specify the value of timeout - according to his end application - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() - (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() - (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine - (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_TxCpltCallback - (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_ErrorCallback - - *** CAN HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in CAN HAL driver. - - (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts - (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts - (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled - (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags - (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status - - [..] - (@) You can refer to the CAN HAL driver header file for more useful macros - @endverbatim - ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -111,1331 +164,1707 @@ * @{ */ +#if defined(CAN1) + /** @defgroup CAN CAN * @brief CAN driver modules * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @addtogroup CAN_Private_Constants +/** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TIMEOUT_VALUE 10U +#define CAN_TIMEOUT_VALUE 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup CAN_Private_Functions - * @{ - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); -/** - * @} - */ - /* Exported functions --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Functions CAN Exported Functions * @{ */ -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the CAN. - (+) De-initialize the CAN. - + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + @endverbatim * @{ */ - + /** * @brief Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - uint32_t InitStatus = CAN_INITSTATUS_FAILED; uint32_t tickstart = 0U; - + /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); - assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SJW)); - assert_param(IS_CAN_BS1(hcan->Init.BS1)); - assert_param(IS_CAN_BS2(hcan->Init.BS2)); - assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - - - if(hcan->State == HAL_CAN_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcan->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_CAN_MspInit(hcan); - } - - /* Initialize the CAN state*/ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Exit from sleep mode */ - hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - hcan->Instance->MCR |= CAN_MCR_INRQ ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - /* Set the time triggered communication mode */ - if (hcan->Init.TTCM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TTCM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (hcan->Init.ABOM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_ABOM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (hcan->Init.AWUM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_AWUM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (hcan->Init.NART == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_NART; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (hcan->Init.RFLM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_RFLM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (hcan->Init.TXFP == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TXFP; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ - ((uint32_t)hcan->Init.SJW) | \ - ((uint32_t)hcan->Init.BS1) | \ - ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1U); - - /* Request leave initialisation */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_INITSTATUS_SUCCESS; - } - } - - if(InitStatus == CAN_INITSTATUS_SUCCESS) - { - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ return HAL_ERROR; } -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) -{ - uint32_t filternbrbitpos = 0U; - CAN_TypeDef *can_ip; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); - assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); - - filternbrbitpos = 1U << sFilterConfig->FilterNumber; -#if defined (CAN3) - /* Check the CAN instance */ - if(hcan->Instance == CAN3) - { - can_ip = CAN3; + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspInit(hcan); + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } else { - can_ip = CAN1; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } -#else - can_ip = CAN1; -#endif - - /* Initialisation mode for the filter */ - can_ip->FMR |= (uint32_t)CAN_FMR_FINIT; -#if defined (CAN2) - /* Select the start slave bank */ - can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U); -#endif - - /* Filter Deactivation */ - can_ip->FA1R &= ~(uint32_t)filternbrbitpos; - - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) { - /* 16-bit scale for the filter */ - can_ip->FS1R &= ~(uint32_t)filternbrbitpos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + else { - /* 32-bit scale for the filter */ - can_ip->FS1R |= filternbrbitpos; - - /* 32-bit identifier or First 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) { - /*Id/Mask mode for the filter*/ - can_ip->FM1R &= ~(uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + else { - /*Identifier list mode for the filter*/ - can_ip->FM1R |= (uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) { - /* FIFO 0 assignation for the filter */ - can_ip->FFA1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) { - /* FIFO 1 assignation for the filter */ - can_ip->FFA1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) + else { - can_ip->FA1R |= filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } - /* Leave the initialisation mode for the filter */ - can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT); - + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + /* Return function status */ return HAL_OK; } /** - * @brief Deinitializes the CANx peripheral registers to their default reset values. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) { /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* DeInit the low level hardware */ + + /* Stop the CAN module */ + HAL_CAN_Stop(hcan); + + /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); - + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + /* Change CAN state */ hcan->State = HAL_CAN_STATE_RESET; - /* Release Lock */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_OK; } /** * @brief Initializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspDeInit could be implemented in the user file - */ + */ +} + + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) +{ + uint32_t filternbrbitpos = 0U; + CAN_TypeDef *can_ip = hcan->Instance; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + +#if defined(CAN3) + /* Check the CAN instance */ + if (hcan->Instance == CAN3) + { + /* CAN3 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); + } + else + { + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); + } +#elif defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN3) + /* Check the CAN instance */ + if (can_ip == CAN1) + { + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + } + +#elif defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif + /* Convert filter number into bit position */ + filternbrbitpos = (1U) << sFilterConfig->FilterBank; + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } } /** * @} */ -/** @defgroup CAN_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions * -@verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### Control functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Transmit a CAN frame message. - (+) Receive a CAN frame message. - (+) Enter CAN peripheral in sleep mode. - (+) Wake up the CAN peripheral from sleep mode. - + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + @endverbatim * @{ */ /** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param Timeout: Specify Timeout value + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; uint32_t tickstart = 0U; - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + if (hcan->State == HAL_CAN_STATE_READY) + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - } - - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = CAN_TXMAILBOX_0; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = CAN_TXMAILBOX_1; - } - else - { - transmitmailbox = CAN_TXMAILBOX_2; - } + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0U])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4U])); - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - /* Get tick */ tickstart = HAL_GetTick(); - - /* Check End of transmission flag */ - while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } + return HAL_ERROR; } } - /* Change CAN state */ - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_TX */ - hcan->State = HAL_CAN_STATE_READY; - break; - } + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - /* Return function status */ return HAL_ERROR; } } /** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) -{ - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { - /* Process Locked */ - __HAL_LOCK(hcan); - - /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = CAN_TXMAILBOX_0; - } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = CAN_TXMAILBOX_1; - } - else - { - transmitmailbox = CAN_TXMAILBOX_2; - } - - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0U])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4U])); - - /* Change CAN state */ - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - - /* Enable Error warning, Error passive, Bus-off, - Last error and Error Interrupts */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME); - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: FIFO Number value - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { uint32_t tickstart = 0U; - CanRxMsgTypeDef* pRxMsg = NULL; - - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Check if CAN state is not busy for RX FIFO0 */ - if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + if (hcan->State == HAL_CAN_STATE_LISTENING) { - return HAL_BUSY; - } + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Check if CAN state is not busy for RX FIFO1 */ - if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) - { - return HAL_BUSY; - } + /* Get tick */ + tickstart = HAL_GetTick(); - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - } - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; } } - } - /* Set RxMsg pointer */ - if(FIFONumber == CAN_FIFO0) - { - pRxMsg = hcan->pRxMsg; - } - else /* FIFONumber == CAN_FIFO1 */ - { - pRxMsg = hcan->pRx1Msg; - } + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - /* Get the Id */ - pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (pRxMsg->IDE == CAN_ID_STD) - { - pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); - } - else - { - pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); - } - - pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); - /* Get the FIFONumber */ - pRxMsg->FIFONumber = FIFONumber; - /* Get the data field */ - pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); - - /* Release the FIFO */ - if(FIFONumber == CAN_FIFO0) - { - /* Release FIFO0 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - } - else /* FIFONumber == CAN_FIFO1 */ - { - /* Release FIFO1 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - } - - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_RX0 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - default: /* HAL_CAN_STATE_BUSY_RX1 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Check if CAN state is not busy for RX FIFO0 */ - if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) - { - return HAL_BUSY; - } - - /* Check if CAN state is not busy for RX FIFO1 */ - if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) - { - return HAL_BUSY; - } - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - if(FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - } - } - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - /* - Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME); - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - if(FIFONumber == CAN_FIFO0) - { - /* Enable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); - } - else - { - /* Enable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enters the Sleep (low power) mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) -{ - uint32_t tickstart = 0U; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Request Sleep mode */ - hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) - { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral - * is in the normal mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) -{ - uint32_t tickstart = 0U; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Wake up request */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Sleep mode status */ - while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) - { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_ERROR; - } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handles CAN interrupt request - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) -{ - uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; - uint32_t errorcode = HAL_CAN_ERROR_NONE; - - /* Check Overrun flag for FIFO0 */ - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0); - if(tmp1 && tmp2) - { - /* Set CAN error code to FOV0 error */ - errorcode |= HAL_CAN_ERROR_FOV0; - - /* Clear FIFO0 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); - } - /* Check Overrun flag for FIFO1 */ - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1); - - if(tmp1 && tmp2) - { - /* Set CAN error code to FOV1 error */ - errorcode |= HAL_CAN_ERROR_FOV1; - - /* Clear FIFO1 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); - } - - /* Check End of transmission flag */ - if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) - { - tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0); - tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1); - tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2); - if(tmp1 || tmp2 || tmp3) - { - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0); - tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1); - tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2); - /* Check Transmit success */ - if(tmp1 || tmp2 || tmp3) - { - /* Call transmit function */ - CAN_Transmit_IT(hcan); - } - else /* Transmit failure */ - { - /* Set CAN error code to TXFAIL error */ - errorcode |= HAL_CAN_ERROR_TXFAIL; - } - - /* Clear transmission status flags (RQCPx and TXOKx) */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ - CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); - } - } - - tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0); - /* Check End of reception flag for FIFO0 */ - if((tmp1 != 0U) && tmp2) - { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO0); - } - - tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1); - /* Check End of reception flag for FIFO1 */ - if((tmp1 != 0U) && tmp2) - { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO1); - } - - /* Set error code in handle */ - hcan->ErrorCode |= errorcode; - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Error Warning Flag */ - if(tmp1 && tmp2 && tmp3) - { - /* Set CAN error code to EWG error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EWG; - } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Error Passive Flag */ - if(tmp1 && tmp2 && tmp3) - { - /* Set CAN error code to EPV error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Bus-Off Flag */ - if(tmp1 && tmp2 && tmp3) - { - /* Set CAN error code to BOF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BOF; - } - - tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Last error code Flag */ - if((!tmp1) && tmp2 && tmp3) - { - tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC; - switch(tmp1) - { - case(CAN_ESR_LEC_0): - /* Set CAN error code to STF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_STF; - break; - case(CAN_ESR_LEC_1): - /* Set CAN error code to FOR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_FOR; - break; - case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to ACK error */ - hcan->ErrorCode |= HAL_CAN_ERROR_ACK; - break; - case(CAN_ESR_LEC_2): - /* Set CAN error code to BR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BR; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to BD error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BD; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - hcan->ErrorCode |= HAL_CAN_ERROR_CRC; - break; - default: - break; - } - - /* Clear Last error code Flag */ - hcan->Instance->ESR &= ~(CAN_ESR_LEC); - } - - /* Call the Error call Back in case of Errors */ - if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) - { - /* Clear ERRI Flag */ - hcan->Instance->MSR = CAN_MSR_ERRI; - /* Set the CAN state ready to be able to start again the process */ + /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - /* - Disable FIFO 0 message pending Interrupt */ - /* - Disable FIFO 0 Overrun Interrupt */ - /* - Disable FIFO 1 message pending Interrupt */ - /* - Disable FIFO 1 Overrun Interrupt */ - /* - Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_FMP0| - CAN_IT_FOV0| - CAN_IT_FMP1| - CAN_IT_FOV1| - CAN_IT_TME); + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; - /* Call Error callback function */ - HAL_CAN_ErrorCallback(hcan); - } + return HAL_ERROR; + } } /** - * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Check if timeout is reached */ + if (++count > timeout) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + status = 1U; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) +{ + uint32_t transmitmailbox; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)) + { + /* Select an empty transmit mailbox */ + transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Store the Tx mailbox */ + *pTxMailbox = 1U << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) + { + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET) + { + freelevel++; + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } + } + + /* Return status */ + return status; +} + +/** + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. + */ +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +{ + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos; + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos; + aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos; + aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos; + aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos; + aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos; + aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos; + aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos; + aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos; + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET) + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != RESET) + { + /* Transmission Mailbox 0 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != RESET) + { + /* Transmission Mailbox 1 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != RESET) + { + /* Transmission Mailbox 2 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != RESET) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET) + { + if ((rf0rflags & CAN_RF0R_FULL0) != RESET) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET) + { + /* Receive FIFO 0 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET) + { + if ((rf1rflags & CAN_RF1R_FOVR1) != RESET) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET) + { + if ((rf1rflags & CAN_RF1R_FULL1) != RESET) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET) + { + /* Receive FIFO 1 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != RESET) + { + if ((msrflags & CAN_MSR_SLAKI) != RESET) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != RESET) + { + if ((msrflags & CAN_MSR_WKUI) != RESET) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != RESET) + { + if ((msrflags & CAN_MSR_ERRI) != RESET) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) && + ((esrflags & CAN_ESR_EWGF) != RESET)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) && + ((esrflags & CAN_ESR_EPVF) != RESET)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != RESET) && + ((esrflags & CAN_ESR_BOFF) != RESET)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) && + ((esrflags & CAN_ESR_LEC) != RESET)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + } + + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Call Error callback function */ + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxCpltCallback could be implemented in the user file + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file */ } /** - * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxCpltCallback could be implemented in the user file + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file */ } /** * @brief Error CAN callback. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1443,6 +1872,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ @@ -1452,230 +1882,110 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * @} */ -/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * -@verbatim +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim ============================================================================== ##### Peripheral State and Error functions ##### ============================================================================== [..] This subsection provides functions allowing to : - (+) Check the CAN state. - (+) Check CAN Errors detected during interrupt process - + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + @endverbatim * @{ */ /** - * @brief return the CAN state - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) { + HAL_CAN_StateTypeDef state = hcan->State; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + } + /* Return CAN state */ - return hcan->State; + return state; } /** - * @brief Return the CAN error code - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval CAN Error Code */ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) { + /* Return CAN error code */ return hcan->ErrorCode; } /** - * @} - */ -/** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) { - /* Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } + HAL_StatusTypeDef status = HAL_OK; - /* Change CAN state */ - switch(hcan->State) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_TX */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - - /* Transmission complete callback */ - HAL_CAN_TxCpltCallback(hcan); - - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number - * @retval HAL status - * @retval None - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) -{ - uint32_t tmp1 = 0U; - CanRxMsgTypeDef* pRxMsg = NULL; - - /* Set RxMsg pointer */ - if(FIFONumber == CAN_FIFO0) - { - pRxMsg = hcan->pRxMsg; - } - else /* FIFONumber == CAN_FIFO1 */ - { - pRxMsg = hcan->pRx1Msg; - } - - /* Get the Id */ - pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (pRxMsg->IDE == CAN_ID_STD) - { - pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + /* Reset CAN error code */ + hcan->ErrorCode = 0U; } else { - pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); - } - - pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FIFONumber */ - pRxMsg->FIFONumber = FIFONumber; - /* Get the FMI */ - pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); - /* Get the data field */ - pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Disable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - - /* Disable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + status = HAL_ERROR; } - tmp1 = hcan->State; - if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1)) - { - /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR); - } - - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_RX0 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - default: /* HAL_CAN_STATE_BUSY_RX1 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - - /* Receive complete callback */ - HAL_CAN_RxCpltCallback(hcan); - - /* Return function status */ - return HAL_OK; + /* Return the status */ + return status; } /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ -#endif /* HAL_CAN_MODULE_ENABLED */ /** * @} */ +#endif /* HAL_CAN_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* CAN1 */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.h index c540ce6d5a..379090a386 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.h @@ -2,13 +2,11 @@ ****************************************************************************** * @file stm32f4xx_hal_can.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    + *

    © COPYRIGHT(c) 2016 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -36,18 +34,13 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CAN_H -#define __STM32F4xx_HAL_CAN_H +#ifndef STM32F4xx_HAL_CAN_H +#define STM32F4xx_HAL_CAN_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -55,6 +48,7 @@ * @{ */ +#if defined (CAN1) /** @addtogroup CAN * @{ */ @@ -63,7 +57,6 @@ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ */ - /** * @brief HAL State structures definition */ @@ -71,59 +64,53 @@ typedef enum { HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ - HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ -}HAL_CAN_StateTypeDef; +} HAL_CAN_StateTypeDef; /** * @brief CAN init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ - uint32_t Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ - uint32_t SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ - uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set to ENABLE or DISABLE. */ + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE */ -}CAN_InitTypeDef; + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_InitTypeDef; /** * @brief CAN filter configuration structure definition @@ -132,27 +119,30 @@ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ - uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. - This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ @@ -163,95 +153,94 @@ typedef struct uint32_t FilterActivation; /*!< Enable or disable the filter. This parameter can be set to ENABLE or DISABLE. */ - uint32_t BankNumber; /*!< Select the start slave bank filter. - This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ -}CAN_FilterConfTypeDef; +} CAN_FilterTypeDef; /** - * @brief CAN Tx message structure definition + * @brief CAN Tx message header structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_Identifier_Type */ + This parameter can be a value of @ref CAN_identifier_type */ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ -}CanTxMsgTypeDef; +} CAN_TxHeaderTypeDef; /** - * @brief CAN Rx message structure definition + * @brief CAN Rx message header structure definition */ typedef struct { - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_Identifier_Type */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ - uint32_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ - uint32_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ - uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ - uint32_t FIFONumber; /*!< Specifies the receive FIFO number. - This parameter can be CAN_FIFO0 or CAN_FIFO1 */ - -}CanRxMsgTypeDef; +} CAN_RxHeaderTypeDef; /** * @brief CAN handle Structure definition */ -typedef struct +typedef struct __CAN_HandleTypeDef { - CAN_TypeDef *Instance; /*!< Register base address */ + CAN_TypeDef *Instance; /*!< Register base address */ - CAN_InitTypeDef Init; /*!< CAN required parameters */ + CAN_InitTypeDef Init; /*!< CAN required parameters */ - CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ - CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ - - __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - - HAL_LockTypeDef Lock; /*!< CAN locking object */ - - __IO uint32_t ErrorCode; /*!< CAN Error code */ - -}CAN_HandleTypeDef; +} CAN_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Constants CAN Exported Constants * @{ */ @@ -259,19 +248,30 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ -#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ -#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ -#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ -#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ -#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ -#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ -#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + /** * @} */ @@ -279,8 +279,8 @@ typedef struct /** @defgroup CAN_InitStatus CAN InitStatus * @{ */ -#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ /** * @} */ @@ -288,7 +288,7 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -296,10 +296,11 @@ typedef struct * @} */ -/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -307,10 +308,10 @@ typedef struct * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1 +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -330,10 +331,10 @@ typedef struct * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ -#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -345,11 +346,11 @@ typedef struct * @} */ -/** @defgroup CAN_filter_mode CAN Filter Mode +/** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ /** * @} */ @@ -357,8 +358,8 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ /** * @} */ @@ -366,17 +367,17 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ -/** @defgroup CAN_Identifier_Type CAN Identifier Type +/** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ -#define CAN_ID_STD 0x00000000U /*!< Standard Id */ -#define CAN_ID_EXT 0x00000004U /*!< Extended Id */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ /** * @} */ @@ -384,17 +385,27 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA 0x00000000U /*!< Data frame */ -#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ /** * @} */ -/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ +/** + * @} + */ + +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes + * @{ + */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ /** * @} */ @@ -402,80 +413,72 @@ typedef struct /** @defgroup CAN_flags CAN Flags * @{ */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ - /* Transmit Flags */ -#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */ - -#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */ -#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */ -#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */ -#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */ -#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */ - -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ /* Error Flags */ -#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */ -#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */ -#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ /** * @} */ + /** @defgroup CAN_Interrupts CAN Interrupts * @{ */ -#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ /* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ -#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ -#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ -#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ -#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ -#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ /* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ -#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ /* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ -#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ -#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ -#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ -#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ -/** - * @} - */ - -/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition - * @{ - */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ /** * @} */ @@ -484,213 +487,198 @@ typedef struct * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ -/** @brief Reset CAN handle state - * @param __HANDLE__: specifies the CAN Handle. +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. * @retval None */ #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) /** * @brief Enable the specified CAN interrupts. - * @param __HANDLE__: CAN handle - * @param __INTERRUPT__: CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** * @brief Disable the specified CAN interrupts. - * @param __HANDLE__: CAN handle - * @param __INTERRUPT__: CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) -/** - * @brief Return the number of pending received messages. - * @param __HANDLE__: CAN handle - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval The number of pending message. +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). */ -#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U))) +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) /** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__: CAN Handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Clear the specified CAN pending flag. - * @param __HANDLE__: CAN Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK)))) - -/** @brief Check if the specified CAN interrupt source is enabled or disabled. - * @param __HANDLE__: CAN Handle - * @param __INTERRUPT__: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable - * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable - * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** - * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__: CAN Handle - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval The new status of transmission (TRUE or FALSE). - */ -#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) - -/** - * @brief Release the specified receive FIFO. - * @param __HANDLE__: CAN handle - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) - -/** - * @brief Cancel a transmit request. - * @param __HANDLE__: CAN Handle - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval None - */ -#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) - -/** - * @brief Enable or disable the DBG Freeze for CAN. - * @param __HANDLE__: CAN Handle - * @param __NEWSTATE__: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) - -/** - * @} - */ + * @} + */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup CAN_Exported_Functions +/** @addtogroup CAN_Exported_Functions CAN Exported Functions * @{ */ -/** @addtogroup CAN_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ***********************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); + /** - * @} - */ + * @} + */ -/** @addtogroup CAN_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); -void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); -/** - * @} - */ -/** @addtogroup CAN_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ***************************************************/ +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); -/** - * @} - */ +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); /** - * @} - */ + * @} + */ + +/** + * @} + */ /* Private types -------------------------------------------------------------*/ /** @defgroup CAN_Private_Types CAN Private Types @@ -708,71 +696,80 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ -#define CAN_FLAG_MASK 0x000000FFU +#define CAN_FLAG_MASK (0x000000FFU) /** * @} */ -/* Private macros ------------------------------------------------------------*/ +/* Private Macros -----------------------------------------------------------*/ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ + #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU)) +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ /** * @} */ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ - -/** - * @} - */ - -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -/** - * @} - */ +#endif /* CAN1 */ /** * @} */ @@ -781,7 +778,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); } #endif -#endif /* __STM32F4xx_CAN_H */ +#endif /* STM32F4xx_HAL_CAN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.c new file mode 100644 index 0000000000..7a4cf5378e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.c @@ -0,0 +1,1697 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_can.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### User NOTE ##### + ============================================================================== + [..] + (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations. + Another HAL CAN driver version has been designed with new API's, to fix these limitations. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock using + __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 + and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3 + -@- In case you are using CAN2 only, you have to enable the CAN1 clock. + + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs using the following function: + __GPIOx_CLK_ENABLE() + (++) Connect and configure the involved CAN pins to AF9 using the + following function HAL_GPIO_Init() + + (#) Initialize and configure the CAN using CAN_Init() function. + + (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. + + (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. + + (#) Receive a CAN frame using HAL_CAN_Receive() function. + + (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using HAL_CAN_Transmit(), at this stage user can specify the value of timeout + according to his end application + (+) Start the CAN peripheral reception and wait the end of this operation + using HAL_CAN_Receive(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() + (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() + (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_TxCpltCallback + (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_ErrorCallback + + *** CAN HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN HAL driver. + + (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts + (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts + (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled + (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags + (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status + + [..] + (@) You can refer to the CAN Legacy HAL driver header file for more useful macros + + @endverbatim + + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT(c) 2017 STMicroelectronics

    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) + +#ifdef HAL_CAN_MODULE_ENABLED +/* Select HAL CAN module in stm32f4xx_hal_conf.h file: + (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations + (#) HAL_CAN_LEGACY_MODULE_ENABLED for legacy HAL CAN driver */ +#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f4xx_hal_conf.h file' +#endif /* HAL_CAN_MODULE_ENABLED */ + +#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup CAN_Private_Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup CAN_Private_Functions + * @{ + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) De-initialize the CAN. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +{ + uint32_t InitStatus = CAN_INITSTATUS_FAILED; + uint32_t tickstart = 0U; + + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SJW)); + assert_param(IS_CAN_BS1(hcan->Init.BS1)); + assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + + + if(hcan->State == HAL_CAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcan->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CAN_MspInit(hcan); + } + + /* Initialize the CAN state*/ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Exit from sleep mode */ + hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + hcan->Instance->MCR |= CAN_MCR_INRQ ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledge */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + /* Set the time triggered communication mode */ + if (hcan->Init.TTCM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TTCM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (hcan->Init.ABOM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_ABOM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AWUM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_AWUM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (hcan->Init.NART == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_NART; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.RFLM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_RFLM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TXFP == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TXFP; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ + ((uint32_t)hcan->Init.SJW) | \ + ((uint32_t)hcan->Init.BS1) | \ + ((uint32_t)hcan->Init.BS2) | \ + ((uint32_t)hcan->Init.Prescaler - 1U); + + /* Request leave initialisation */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledged */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CAN_INITSTATUS_SUCCESS; + } + } + + if(InitStatus == CAN_INITSTATUS_SUCCESS) + { + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) +{ + uint32_t filternbrbitpos = 0U; + CAN_TypeDef *can_ip; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); + + filternbrbitpos = 1U << sFilterConfig->FilterNumber; +#if defined (CAN3) + /* Check the CAN instance */ + if(hcan->Instance == CAN3) + { + can_ip = CAN3; + } + else + { + can_ip = CAN1; + } +#else + can_ip = CAN1; +#endif + + /* Initialisation mode for the filter */ + can_ip->FMR |= (uint32_t)CAN_FMR_FINIT; + +#if defined (CAN2) + /* Select the start slave bank */ + can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); + can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U); +#endif + + /* Filter Deactivation */ + can_ip->FA1R &= ~(uint32_t)filternbrbitpos; + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + can_ip->FS1R &= ~(uint32_t)filternbrbitpos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + can_ip->FS1R |= filternbrbitpos; + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /*Id/Mask mode for the filter*/ + can_ip->FM1R &= ~(uint32_t)filternbrbitpos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + can_ip->FM1R |= (uint32_t)filternbrbitpos; + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + can_ip->FFA1R &= ~(uint32_t)filternbrbitpos; + } + + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + { + /* FIFO 1 assignation for the filter */ + can_ip->FFA1R |= (uint32_t)filternbrbitpos; + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + can_ip->FA1R |= filternbrbitpos; + } + + /* Leave the initialisation mode for the filter */ + can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CANx peripheral registers to their default reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +{ + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CAN_MspDeInit(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a CAN frame message. + (+) Receive a CAN frame message. + (+) Enter CAN peripheral in sleep mode. + (+) Wake up the CAN peripheral from sleep mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + } + + /* Select one empty transmit mailbox */ + if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = CAN_TXMAILBOX_1; + } + else + { + transmitmailbox = CAN_TXMAILBOX_2; + } + + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if (hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[0U])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[4U])); + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of transmission flag */ + while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + + __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process Locked */ + __HAL_LOCK(hcan); + + /* Select one empty transmit mailbox */ + if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = CAN_TXMAILBOX_1; + } + else + { + transmitmailbox = CAN_TXMAILBOX_2; + } + + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[0U])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[4U])); + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Enable Error warning, Error passive, Bus-off, + Last error and Error Interrupts */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME); + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber FIFO Number value + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check pending message */ + while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + } + else + { + pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + } + + pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; + /* Get the data field */ + pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + + /* Release the FIFO */ + if(FIFONumber == CAN_FIFO0) + { + /* Release FIFO0 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + } + else /* FIFONumber == CAN_FIFO1 */ + { + /* Release FIFO1 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber Specify the FIFO number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Check if CAN state is not busy for RX FIFO0 */ + if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + if(FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + else + { + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enters the Sleep (low power) mode. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0U; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Request Sleep mode */ + hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral + * is in the normal mode. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0U; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Wake up request */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Sleep mode status */ + while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +{ + uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0); + if(tmp1 && tmp2) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + /* Check Overrun flag for FIFO1 */ + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1); + + if(tmp1 && tmp2) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + + /* Check End of transmission flag */ + if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + { + tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0); + tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1); + tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2); + if(tmp1 || tmp2 || tmp3) + { + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0); + tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1); + tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2); + /* Check Transmit success */ + if(tmp1 || tmp2 || tmp3) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + else /* Transmit failure */ + { + /* Set CAN error code to TXFAIL error */ + errorcode |= HAL_CAN_ERROR_TXFAIL; + } + + /* Clear transmission status flags (RQCPx and TXOKx) */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ + CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); + } + } + + tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0); + /* Check End of reception flag for FIFO0 */ + if((tmp1 != 0U) && tmp2) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO0); + } + + tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1); + /* Check End of reception flag for FIFO1 */ + if((tmp1 != 0U) && tmp2) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO1); + } + + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Error Warning Flag */ + if(tmp1 && tmp2 && tmp3) + { + /* Set CAN error code to EWG error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EWG; + } + + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Error Passive Flag */ + if(tmp1 && tmp2 && tmp3) + { + /* Set CAN error code to EPV error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EPV; + } + + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Bus-Off Flag */ + if(tmp1 && tmp2 && tmp3) + { + /* Set CAN error code to BOF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BOF; + } + + tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Last error code Flag */ + if((!tmp1) && tmp2 && tmp3) + { + tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC; + switch(tmp1) + { + case(CAN_ESR_LEC_0): + /* Set CAN error code to STF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_STF; + break; + case(CAN_ESR_LEC_1): + /* Set CAN error code to FOR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_FOR; + break; + case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to ACK error */ + hcan->ErrorCode |= HAL_CAN_ERROR_ACK; + break; + case(CAN_ESR_LEC_2): + /* Set CAN error code to BR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BR; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to BD error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BD; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + hcan->ErrorCode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + hcan->Instance->ESR &= ~(CAN_ESR_LEC); + } + + /* Call the Error call Back in case of Errors */ + if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + { + /* Clear ERRI Flag */ + hcan->Instance->MSR = CAN_MSR_ERRI; + /* Set the CAN state ready to be able to start again the process */ + hcan->State = HAL_CAN_STATE_READY; + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME); + + /* Call Error callback function */ + HAL_CAN_ErrorCallback(hcan); + } +} + +/** + * @brief Transmission complete callback in non blocking mode + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission complete callback in non blocking mode + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process + +@endverbatim + * @{ + */ + +/** + * @brief return the CAN state + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +{ + /* Return CAN state */ + return hcan->State; +} + +/** + * @brief Return the CAN error code + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + return hcan->ErrorCode; +} + +/** + * @} + */ +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + /* Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Disable Error warning, Error passive, Bus-off, Last error code + and Error Interrupts */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + + /* Transmission complete callback */ + HAL_CAN_TxCpltCallback(hcan); + + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber Specify the FIFO number + * @retval HAL status + * @retval None + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + uint32_t tmp1 = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + } + else + { + pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + } + + pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; + /* Get the FMI */ + pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + /* Get the data field */ + pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + tmp1 = hcan->State; + if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1)) + { + /* Disable Error warning, Error passive, Bus-off, Last error code + and Error Interrupts */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR); + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + + /* Receive complete callback */ + HAL_CAN_RxCpltCallback(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.h new file mode 100644 index 0000000000..aacf0f0727 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.h @@ -0,0 +1,785 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_can_legacy.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT(c) 2017 STMicroelectronics

    + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CAN_LEGACY_H +#define __STM32F4xx_HAL_CAN_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ + HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ + +}HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE */ +}CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. + This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t BankNumber; /*!< Select the start slave bank filter. + This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + +}CAN_FilterConfTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_Identifier_Type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + +}CanTxMsgTypeDef; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_Identifier_Type */ + + uint32_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FIFONumber; /*!< Specifies the receive FIFO number. + This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + +}CanRxMsgTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + + CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + HAL_LockTypeDef Lock; /*!< CAN locking object */ + + __IO uint32_t ErrorCode; /*!< CAN Error code */ + +}CAN_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ +#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ +#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ +#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ +#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ +#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN InitStatus + * @{ + */ +#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width + * @{ + */ +#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1 + * @{ + */ +#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 + * @{ + */ +#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_Identifier_Type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD 0x00000000U /*!< Standard Id */ +#define CAN_ID_EXT 0x00000004U /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA 0x00000000U /*!< Data frame */ +#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */ + +#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */ +#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */ +#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */ + +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */ +#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */ +#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */ +/** + * @} + */ + +/** @defgroup CAN_Interrupts CAN Interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ +/** + * @} + */ + +/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition + * @{ + */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macros CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state + * @param __HANDLE__ specifies the CAN Handle. + * @retval None + */ +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) + +/** + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle + * @param __INTERRUPT__ CAN Interrupt + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle + * @param __INTERRUPT__ CAN Interrupt + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** + * @brief Return the number of pending received messages. + * @param __HANDLE__ CAN handle + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval The number of pending message. + */ +#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U))) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__ CAN Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__ CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ CAN Handle + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable + * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable + * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Check the transmission status of a CAN Frame. + * @param __HANDLE__ CAN Handle + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. + * @retval The new status of transmission (TRUE or FALSE). + */ +#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + +/** + * @brief Release the specified receive FIFO. + * @param __HANDLE__ CAN handle + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) + +/** + * @brief Cancel a transmit request. + * @param __HANDLE__ CAN Handle + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. + * @retval None + */ +#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ + ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) + +/** + * @brief Enable or disable the DBG Freeze for CAN. + * @param __HANDLE__ CAN Handle + * @param __NEWSTATE__ new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFOs can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ +((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions + * @{ + */ + +/** @addtogroup CAN_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ***********************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); +void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ***************************************************/ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +#define CAN_FLAG_MASK 0x000000FFU +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ + +/** + * @} + */ + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CAN_LEGACY_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.c index 7c6a767816..b7cdf455e1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cec.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface @@ -143,7 +141,7 @@ /** * @brief Initializes the CEC mode according to the specified * parameters in the CEC_InitTypeDef and creates the associated handle . - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) @@ -213,7 +211,7 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) /** * @brief DeInitializes the CEC peripheral - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) @@ -266,8 +264,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) /** * @brief Initializes the Own Address of the CEC device - * @param hcec: CEC handle - * @param CEC_OwnAddress: The CEC own address. + * @param hcec CEC handle + * @param CEC_OwnAddress The CEC own address. * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) @@ -313,7 +311,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief CEC MSP Init - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) @@ -327,7 +325,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief CEC MSP DeInit - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) @@ -379,11 +377,11 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief Send data in interrupt mode - * @param hcec: CEC handle - * @param InitiatorAddress: Initiator logical address - * @param DestinationAddress: destination logical address - * @param pData: pointer to input byte data buffer - * @param Size: amount of data to be sent in bytes (without counting the header). + * @param hcec CEC handle + * @param InitiatorAddress Initiator logical address + * @param DestinationAddress destination logical address + * @param pData pointer to input byte data buffer + * @param Size amount of data to be sent in bytes (without counting the header). * 0 means only the header is sent (ping operation). * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status @@ -439,7 +437,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator /** * @brief Get size of the received frame. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval Frame size */ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) @@ -449,8 +447,8 @@ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) /** * @brief Change Rx Buffer. - * @param hcec: CEC handle - * @param Rxbuffer: Rx Buffer + * @param hcec CEC handle + * @param Rxbuffer Rx Buffer * @note This function can be called only inside the HAL_CEC_RxCpltCallback() * @retval Frame size */ @@ -461,7 +459,7 @@ void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer) /** * @brief This function handles CEC interrupt requests. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) @@ -566,7 +564,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Tx Transfer completed callback - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) @@ -580,8 +578,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Rx Transfer completed callback - * @param hcec: CEC handle - * @param RxFrameSize: Size of frame + * @param hcec CEC handle + * @param RxFrameSize Size of frame * @retval None */ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) @@ -596,7 +594,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize /** * @brief CEC error callbacks - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) @@ -627,7 +625,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize */ /** * @brief return the CEC state - * @param hcec: pointer to a CEC_HandleTypeDef structure that contains + * @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC module. * @retval HAL state */ @@ -642,7 +640,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) /** * @brief Return the CEC error code - * @param hcec : pointer to a CEC_HandleTypeDef structure that contains + * @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC. * @retval CEC Error Code */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h index 8a67359de8..0ce759063b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cec.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention @@ -426,7 +424,7 @@ typedef struct */ /** @brief Reset CEC handle gstate & RxState - * @param __HANDLE__: CEC handle. + * @param __HANDLE__ CEC handle. * @retval None */ #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -435,8 +433,8 @@ typedef struct } while(0) /** @brief Checks whether or not the specified CEC interrupt flag is set. - * @param __HANDLE__: specifies the CEC Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CEC Handle. + * @param __FLAG__ specifies the flag to check. * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXERR: Tx Error. * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. @@ -455,8 +453,8 @@ typedef struct #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) /** @brief Clears the interrupt or status flag when raised (write at 1) - * @param __HANDLE__: specifies the CEC Handle. - * @param __FLAG__: specifies the interrupt/status flag to clear. + * @param __HANDLE__ specifies the CEC Handle. + * @param __FLAG__ specifies the interrupt/status flag to clear. * This parameter can be one of the following values: * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXERR: Tx Error. @@ -476,8 +474,8 @@ typedef struct #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) /** @brief Enables the specified CEC interrupt. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to enable. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to enable. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -497,8 +495,8 @@ typedef struct #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) /** @brief Disables the specified CEC interrupt. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to disable. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to disable. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -518,8 +516,8 @@ typedef struct #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) /** @brief Checks whether or not the specified CEC interrupt is enabled. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to check. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to check. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -539,52 +537,52 @@ typedef struct #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) /** @brief Enables the CEC device - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) /** @brief Disables the CEC device - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) /** @brief Set Transmission Start flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) /** @brief Set Transmission End flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. */ #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) /** @brief Get Transmission Start flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval FlagStatus */ #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) /** @brief Get Transmission End flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval FlagStatus */ #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) /** @brief Clear OAR register - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) /** @brief Set OAR register (without resetting previously set address in case of multi-address mode) * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand - * @param __HANDLE__: specifies the CEC Handle. - * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position) + * @param __HANDLE__ specifies the CEC Handle. + * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) * @retval none */ #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) @@ -699,21 +697,21 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); * The message size is the payload size: without counting the header, * it varies from 0 byte (ping operation, one header only, no payload) to * 15 bytes (1 opcode and up to 14 operands following the header). - * @param __SIZE__: CEC message size. + * @param __SIZE__ CEC message size. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) /** @brief Check CEC device Own Address Register (OAR) setting. * OAR address is written in a 15-bit field within CEC_CFGR register. - * @param __ADDRESS__: CEC own address. + * @param __ADDRESS__ CEC own address. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) /** @brief Check CEC initiator or destination logical address setting. * Initiator and destination addresses are coded over 4 bits. - * @param __ADDRESS__: CEC initiator or logical address. + * @param __ADDRESS__ CEC initiator or logical address. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h index fe95369830..44179a7e50 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_conf.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -52,7 +50,8 @@ */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -#define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_MODULE_ENABLED */ +#define HAL_CAN_LEGACY_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED #define HAL_CEC_MODULE_ENABLED #define HAL_CRYP_MODULE_ENABLED @@ -273,6 +272,10 @@ #include "stm32f4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.c index c8e0c5fc48..c277ebf629 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -142,7 +140,7 @@ /** * @brief Sets the priority grouping field (preemption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. + * @param PriorityGroup The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -169,13 +167,13 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @param PreemptPriority: The preemption priority for the IRQn channel. + * @param PreemptPriority The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. + * @param SubPriority the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None @@ -240,7 +238,7 @@ void HAL_NVIC_SystemReset(void) /** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ @@ -287,7 +285,7 @@ void HAL_MPU_Disable(void) /** * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * @param MPU_Control Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE @@ -311,7 +309,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control) /** * @brief Initializes and configures the Region and the memory to be protected. - * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ @@ -367,10 +365,10 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) /** * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @param PriorityGroup: the priority grouping bits length. + * @param PriorityGroup the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -382,8 +380,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) @@ -463,7 +461,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) /** * @brief Configures the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h index 53134d313a..da3454b7ec 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.c index 32ca97cd15..89055cb722 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_crc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -105,7 +103,7 @@ /** * @brief Initializes the CRC according to the specified * parameters in the CRC_InitTypeDef and creates the associated handle. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC * @retval HAL status */ @@ -140,7 +138,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) /** * @brief DeInitializes the CRC peripheral. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC * @retval HAL status */ @@ -173,7 +171,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /** * @brief Initializes the CRC MSP. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC * @retval None */ @@ -188,7 +186,7 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) /** * @brief DeInitializes the CRC MSP. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC * @retval None */ @@ -225,10 +223,10 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) /** * @brief Computes the 32-bit CRC of 32-bit data buffer using combination * of the previous CRC value and the new one. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed + * @param pBuffer pointer to the buffer containing the data to be computed + * @param BufferLength length of the buffer to be computed * @retval 32-bit CRC */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) @@ -260,10 +258,10 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ /** * @brief Computes the 32-bit CRC of 32-bit data buffer independently * of the previous CRC value. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC - * @param pBuffer: Pointer to the buffer containing the data to be computed - * @param BufferLength: Length of the buffer to be computed + * @param pBuffer Pointer to the buffer containing the data to be computed + * @param BufferLength Length of the buffer to be computed * @retval 32-bit CRC */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) @@ -317,7 +315,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** * @brief Returns the CRC state. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC * @retval HAL state */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.h index 32c9ef5795..4b7bd9d82c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_crc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -103,29 +101,29 @@ typedef struct */ /** @brief Resets CRC handle state - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None */ #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) /** * @brief Resets CRC Data Register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None */ #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) /** * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle - * @param __VALUE__: 8-bit value to be stored in the ID register + * @param __HANDLE__ CRC handle + * @param __VALUE__ 8-bit value to be stored in the ID register * @retval None */ #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval 8-bit value of the ID register */ #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.c index f677452acd..e27d8433f7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CRYP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: @@ -155,7 +153,7 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction); /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -172,7 +170,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -195,7 +193,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) @@ -207,10 +205,10 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key + * @param Key Pointer to Key buffer + * @param KeySize Size of Key * @retval None */ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize) @@ -266,10 +264,10 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySiz /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer - * @param IVSize: Size of the InitVector/InitCounter + * @param InitVector Pointer to InitVector/InitCounter buffer + * @param IVSize Size of the InitVector/InitCounter * @retval None */ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize) @@ -305,12 +303,12 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, u /** * @brief Process Data: Writes Input data in polling mode and read the output data - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 16. - * @param Output: Pointer to the returned buffer - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer + * @param Ilength Length of the Input buffer, must be a multiple of 16. + * @param Output Pointer to the returned buffer + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -369,12 +367,12 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In /** * @brief Process Data: Write Input data in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 8 - * @param Output: Pointer to the returned buffer - * @param Timeout: Specify Timeout value + * @param Input Pointer to the Input buffer + * @param Ilength Length of the Input buffer, must be a multiple of 8 + * @param Output Pointer to the returned buffer + * @param Timeout Specify Timeout value * @retval None */ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -425,11 +423,11 @@ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Set the DMA configuration and start the DMA transfer - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param inputaddr: address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16. - * @param outputaddr: address of the Output buffer + * @param inputaddr address of the Input buffer + * @param Size Size of the Input buffer, must be a multiple of 16. + * @param outputaddr address of the Output buffer * @retval None */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -463,9 +461,9 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin /** * @brief Sets the CRYP peripheral in DES ECB mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -490,9 +488,9 @@ static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Sets the CRYP peripheral in DES CBC mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -520,9 +518,9 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Sets the CRYP peripheral in TDES ECB mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -546,9 +544,9 @@ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Sets the CRYP peripheral in TDES CBC mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -603,7 +601,7 @@ static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Initializes the CRYP according to the specified * parameters in the CRYP_InitTypeDef and creates the associated handle. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -649,7 +647,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) /** * @brief DeInitializes the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -689,7 +687,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) /** * @brief Initializes the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -704,7 +702,7 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) /** * @brief DeInitializes CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -743,12 +741,12 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -797,12 +795,12 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -854,12 +852,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -913,12 +911,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1001,12 +999,12 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1090,12 +1088,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1146,11 +1144,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1247,11 +1245,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1350,11 +1348,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1454,11 +1452,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1583,11 +1581,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1720,11 +1718,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1825,11 +1823,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1880,11 +1878,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1938,11 +1936,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1997,11 +1995,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2081,11 +2079,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2168,11 +2166,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2251,12 +2249,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2291,12 +2289,12 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -2331,12 +2329,12 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2371,12 +2369,12 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -2411,11 +2409,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2496,11 +2494,11 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2582,11 +2580,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2667,11 +2665,11 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2752,11 +2750,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2795,11 +2793,11 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2838,11 +2836,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2881,11 +2879,11 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2948,12 +2946,12 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2989,12 +2987,12 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -3030,12 +3028,12 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -3071,12 +3069,12 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -3111,11 +3109,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3196,11 +3194,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3280,11 +3278,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3364,11 +3362,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3448,11 +3446,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3491,11 +3489,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3534,11 +3532,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3577,11 +3575,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3640,7 +3638,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Input FIFO transfer completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3655,7 +3653,7 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Output FIFO transfer completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3670,7 +3668,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief CRYP error callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3702,7 +3700,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief This function handles CRYP interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3791,7 +3789,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) /** * @brief Returns the CRYP state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL state */ @@ -4092,7 +4090,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) /** * @brief DeInitialize the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -4132,7 +4130,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) /** * @brief Initialize the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4148,7 +4146,7 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) /** * @brief DeInitialize CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4188,12 +4186,12 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) /** * @brief Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4219,12 +4217,12 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4250,12 +4248,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4281,12 +4279,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4312,12 +4310,12 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4343,12 +4341,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Decrypt pCypherData in AES CTR decryption mode, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4374,11 +4372,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Encrypt pPlainData in AES ECB encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4404,11 +4402,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Encrypt pPlainData in AES CBC encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4435,11 +4433,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Encrypt pPlainData in AES CTR encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4465,11 +4463,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer. + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4495,11 +4493,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4525,11 +4523,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4555,11 +4553,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Encrypt pPlainData in AES ECB encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4588,11 +4586,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Encrypt pPlainData in AES CBC encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4619,11 +4617,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Encrypt pPlainData in AES CTR encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer. + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4650,11 +4648,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES ECB decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4681,11 +4679,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CBC decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4712,11 +4710,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CTR decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4763,7 +4761,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief CRYP error callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4779,7 +4777,7 @@ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Input DMA transfer complete callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4795,7 +4793,7 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Output DMA transfer complete callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4828,7 +4826,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Handle AES interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4913,7 +4911,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) /** * @brief Return the CRYP handle state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL state */ @@ -4925,7 +4923,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) /** * @brief Return the CRYP peripheral error. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @note The returned error is a bit-map combination of possible errors * @retval Error bit-map @@ -4950,7 +4948,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) /** * @brief Write the Key in KeyRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4991,7 +4989,7 @@ static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp) /** * @brief Write the InitVector/InitCounter in IVRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -5034,7 +5032,7 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) * @brief Handle CRYP block input/output data handling under interruption. * @note The function is called under interruption only, once * interruptions have been enabled by HAL_CRYPEx_AES_IT(). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.h index 4cd3125a5d..a67420b8f8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention @@ -260,14 +258,14 @@ typedef struct */ /** @brief Reset CRYP handle state - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__ specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) /** * @brief Enable/Disable the CRYP peripheral. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__ specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN) @@ -275,22 +273,22 @@ typedef struct /** * @brief Flush the data FIFO. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__ specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH) /** * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC. - * @param __HANDLE__: specifies the CRYP handle. - * @param MODE: The algorithm mode. + * @param __HANDLE__ specifies the CRYP handle. + * @param MODE The algorithm mode. * @retval None */ #define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE)) /** @brief Check whether the specified CRYP flag is set or not. - * @param __HANDLE__: specifies the CRYP handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CRYP handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data * or a key preparation (for AES decryption). @@ -307,8 +305,8 @@ typedef struct ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) /** @brief Check whether the specified CRYP interrupt is set or not. - * @param __HANDLE__: specifies the CRYP handle. - * @param __INTERRUPT__: specifies the interrupt to check. + * @param __HANDLE__ specifies the CRYP handle. + * @param __INTERRUPT__ specifies the interrupt to check. * This parameter can be one of the following values: * @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending * @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending @@ -318,16 +316,16 @@ typedef struct /** * @brief Enable the CRYP interrupt. - * @param __HANDLE__: specifies the CRYP handle. - * @param __INTERRUPT__: CRYP Interrupt. + * @param __HANDLE__ specifies the CRYP handle. + * @param __INTERRUPT__ CRYP Interrupt. * @retval None */ #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__)) /** * @brief Disable the CRYP interrupt. - * @param __HANDLE__: specifies the CRYP handle. - * @param __INTERRUPT__: CRYP interrupt. + * @param __HANDLE__ specifies the CRYP handle. + * @param __INTERRUPT__ CRYP interrupt. * @retval None */ #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__)) @@ -821,7 +819,7 @@ typedef struct */ /** @brief Reset CRYP handle state. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__ specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) @@ -840,7 +838,7 @@ typedef struct /** * @brief Set the algorithm operating mode. - * @param __OPERATING_MODE__: specifies the operating mode + * @param __OPERATING_MODE__ specifies the operating mode * This parameter can be one of the following values: * @arg @ref CRYP_ALGOMODE_ENCRYPT encryption * @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation @@ -853,7 +851,7 @@ typedef struct /** * @brief Set the algorithm chaining mode. - * @param __CHAINING_MODE__: specifies the chaining mode + * @param __CHAINING_MODE__ specifies the chaining mode * This parameter can be one of the following values: * @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook * @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining @@ -867,7 +865,7 @@ typedef struct /** @brief Check whether the specified CRYP status flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden * @arg @ref CRYP_IT_WRERR Write Error @@ -879,7 +877,7 @@ typedef struct /** @brief Clear the CRYP pending status flag. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear @@ -890,7 +888,7 @@ typedef struct /** @brief Check whether the specified CRYP interrupt source is enabled or not. - * @param __INTERRUPT__: CRYP interrupt source to check + * @param __INTERRUPT__ CRYP interrupt source to check * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt @@ -900,7 +898,7 @@ typedef struct /** @brief Check whether the specified CRYP interrupt is set or not. - * @param __INTERRUPT__: specifies the interrupt to check. + * @param __INTERRUPT__ specifies the interrupt to check. * This parameter can be one of the following values: * @arg @ref CRYP_IT_WRERR Write Error * @arg @ref CRYP_IT_RDERR Read Error @@ -912,7 +910,7 @@ typedef struct /** @brief Clear the CRYP pending interrupt. - * @param __INTERRUPT__: specifies the IT to clear. + * @param __INTERRUPT__ specifies the IT to clear. * This parameter can be one of the following values: * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear @@ -923,7 +921,7 @@ typedef struct /** * @brief Enable the CRYP interrupt. - * @param __INTERRUPT__: CRYP Interrupt. + * @param __INTERRUPT__ CRYP Interrupt. * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt @@ -934,7 +932,7 @@ typedef struct /** * @brief Disable the CRYP interrupt. - * @param __INTERRUPT__: CRYP Interrupt. + * @param __INTERRUPT__ CRYP Interrupt. * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt @@ -953,7 +951,7 @@ typedef struct /** * @brief Verify the key size length. - * @param __KEYSIZE__: Ciphering/deciphering algorithm key size. + * @param __KEYSIZE__ Ciphering/deciphering algorithm key size. * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid) */ #define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \ @@ -961,7 +959,7 @@ typedef struct /** * @brief Verify the input data type. - * @param __DATATYPE__: Ciphering/deciphering algorithm input data type. + * @param __DATATYPE__ Ciphering/deciphering algorithm input data type. * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) */ #define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \ @@ -971,7 +969,7 @@ typedef struct /** * @brief Verify the CRYP AES IP running mode. - * @param __MODE__: CRYP AES IP running mode. + * @param __MODE__ CRYP AES IP running mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \ @@ -979,7 +977,7 @@ typedef struct /** * @brief Verify the selected CRYP algorithm. - * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter). + * @param __ALGOMODE__ Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter). * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid) */ #define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \ @@ -990,7 +988,7 @@ typedef struct /** * @brief Verify the selected CRYP chaining algorithm. - * @param __CHAINMODE__: Selected CRYP chaining algorithm. + * @param __CHAINMODE__ Selected CRYP chaining algorithm. * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid) */ #if defined(AES_CR_NPBLB) @@ -1009,7 +1007,7 @@ typedef struct /** * @brief Verify the deciphering key write option. - * @param __WRITE__: deciphering key write option. + * @param __WRITE__ deciphering key write option. * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid) */ #define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \ @@ -1017,7 +1015,7 @@ typedef struct /** * @brief Verify the CRYP input data DMA mode. - * @param __MODE__: CRYP input data DMA mode. + * @param __MODE__ CRYP input data DMA mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \ @@ -1025,7 +1023,7 @@ typedef struct /** * @brief Verify the CRYP output data DMA mode. - * @param __MODE__: CRYP output data DMA mode. + * @param __MODE__ CRYP output data DMA mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \ @@ -1033,7 +1031,7 @@ typedef struct /** * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase. - * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase. + * @param __PHASE__ CRYP AES ciphering/deciphering/authentication algorithm phase. * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid) */ #define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.c index c5664b07ba..61e4f112f5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Extended CRYP HAL module driver * This file provides firmware functions to manage the following * functionalities of CRYP extension peripheral: @@ -147,7 +145,7 @@ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t input /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -164,7 +162,7 @@ static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -187,7 +185,7 @@ static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma) @@ -199,10 +197,10 @@ static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key + * @param Key Pointer to Key buffer + * @param KeySize Size of Key * @retval None */ static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize) @@ -258,9 +256,9 @@ static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32 /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer + * @param InitVector Pointer to InitVector/InitCounter buffer * @retval None */ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) @@ -278,12 +276,12 @@ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *Init /** * @brief Process Data: Writes Input data in polling mode and read the Output data. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer, must be a multiple of 16 - * @param Output: Pointer to the returned buffer - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer, must be a multiple of 16 + * @param Output Pointer to the returned buffer + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout) @@ -341,11 +339,11 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, ui /** * @brief Sets the header phase - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer, must be a multiple of 16 - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer, must be a multiple of 16 + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout) @@ -427,11 +425,11 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, /** * @brief Sets the DMA configuration and start the DMA transfer. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param inputaddr: Address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16 - * @param outputaddr: Address of the Output buffer + * @param inputaddr Address of the Input buffer + * @param Size Size of the Input buffer, must be a multiple of 16 + * @param outputaddr Address of the Output buffer * @retval None */ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -495,12 +493,12 @@ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t input /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -751,12 +749,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -849,12 +847,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Timeout duration + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -942,11 +940,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Computes the authentication TAG. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Size: Total length of the plain/cyphertext buffer - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration + * @param Size Total length of the plain/cyphertext buffer + * @param AuthTag Pointer to the authentication buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout) @@ -1051,10 +1049,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t S /** * @brief Computes the authentication TAG for AES CCM mode. * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt() - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration + * @param AuthTag Pointer to the authentication buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout) @@ -1143,12 +1141,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *A /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1395,11 +1393,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1546,11 +1544,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1845,11 +1843,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1993,11 +1991,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2283,11 +2281,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2380,11 +2378,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2634,11 +2632,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer. - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer. + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2724,11 +2722,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2995,7 +2993,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief This function handles CRYPEx interrupt request. - * @param hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYPEx_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3095,7 +3093,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ /** * @brief Computation completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3144,17 +3142,17 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) * @brief Carry out in polling mode the ciphering or deciphering operation according to * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. * Parameter is meaningless in case of key derivation. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption, or pointer to the derivative keys in * case of key derivation only. - * @param Timeout: Specify Timeout value + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout) @@ -3223,14 +3221,14 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, * @brief Carry out in interrupt mode the ciphering or deciphering operation according to * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in interrupt mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. * Parameter is meaningless in case of key derivation. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption, or pointer to the derivative keys in * case of key derivation only. * @retval HAL status @@ -3313,12 +3311,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD /** * @brief Carry out in DMA mode the ciphering or deciphering operation according to * hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption. * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode. * @note Supported operating modes are encryption, decryption and key derivation with decryption. @@ -3378,24 +3376,24 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /** * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases * and in case of CMAC header phase. - * @param Timeout: Specify Timeout value + * @param Timeout Specify Timeout value * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable. * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes * can be skipped by the user if so required. @@ -3860,19 +3858,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /** * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases @@ -4271,19 +4269,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /** * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases @@ -4696,9 +4694,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /** * @brief In case of message processing suspension, read the Initialization Vector. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Initialization Vector. + * @param Output Pointer to the buffer containing the saved Initialization Vector. * @note This value has to be stored for reuse by writing the AES_IVRx registers * as soon as the interrupted processing has to be resumed. * Applicable to all chaining modes. @@ -4721,9 +4719,9 @@ void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) /** * @brief In case of message processing resumption, rewrite the Initialization * Vector in the AES_IVRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved Initialization Vector to + * @param Input Pointer to the buffer containing the saved Initialization Vector to * write back in the CRYP hardware block. * @note Applicable to all chaining modes. * @note AES must be disabled when reading or resetting the IV values. @@ -4745,9 +4743,9 @@ void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input) /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Suspend Registers. + * @param Output Pointer to the buffer containing the saved Suspend Registers. * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers * as soon as the interrupted processing has to be resumed. * @retval None @@ -4793,9 +4791,9 @@ void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend * Registers in the AES_SUSPxR registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved suspend registers to + * @param Input Pointer to the buffer containing the saved suspend registers to * write back in the CRYP hardware block. * @retval None */ @@ -4823,10 +4821,10 @@ void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Key Registers. - * @param KeySize: Indicates the key size (128 or 256 bits). + * @param Output Pointer to the buffer containing the saved Key Registers. + * @param KeySize Indicates the key size (128 or 256 bits). * @note These values have to be stored for reuse by writing back the AES_KEYRx registers * as soon as the interrupted processing has to be resumed. * @retval None @@ -4859,11 +4857,11 @@ void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, ui /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key * Registers in the AES_KEYRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved key registers to + * @param Input Pointer to the buffer containing the saved key registers to * write back in the CRYP hardware block. - * @param KeySize: Indicates the key size (128 or 256 bits) + * @param KeySize Indicates the key size (128 or 256 bits) * @retval None */ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize) @@ -4894,9 +4892,9 @@ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, ui /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Control Register. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Control Register. + * @param Output Pointer to the buffer containing the saved Control Register. * @note This values has to be stored for reuse by writing back the AES_CR register * as soon as the interrupted processing has to be resumed. * @retval None @@ -4909,9 +4907,9 @@ void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output) /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control * Registers in the AES_CR register. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved Control Register to + * @param Input Pointer to the buffer containing the saved Control Register to * write back in the CRYP hardware block. * @retval None */ @@ -4925,7 +4923,7 @@ void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input) /** * @brief Request CRYP processing suspension when in polling or interruption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @note Set the handle field SuspendRequest to the appropriate value so that * the on-going CRYP processing is suspended as soon as the required @@ -4959,7 +4957,7 @@ void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp) * in the case of header phase where no output data DMA * transfer is on-going (only input data transfer is enabled * in such a case). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -5000,7 +4998,7 @@ static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma) * @brief DMA CRYP Output Data process complete callback * for GCM, GMAC or CMAC chainging modes. * @note This callback is called only in the payload phase. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -5036,7 +5034,7 @@ static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP communication error callback * for GCM, GMAC or CMAC chainging modes. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma) @@ -5055,7 +5053,7 @@ static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma) * for GCM, GMAC or CMAC chaining modes. * @note The function is called under interruption only, once * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT(). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -5511,11 +5509,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) /** * @brief Set the DMA configuration and start the DMA transfer * for GCM, GMAC or CMAC chainging modes. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param inputaddr: Address of the Input buffer. - * @param Size: Size of the Input buffer un bytes, must be a multiple of 16. - * @param outputaddr: Address of the Output buffer, null pointer when no output DMA stream + * @param inputaddr Address of the Input buffer. + * @param Size Size of the Input buffer un bytes, must be a multiple of 16. + * @param outputaddr Address of the Output buffer, null pointer when no output DMA stream * has to be configured. * @retval None */ @@ -5557,12 +5555,12 @@ static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputa /** * @brief Write/read input/output data in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer in bytes, must be a multiple of 16. - * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer in bytes, must be a multiple of 16. + * @param Output Pointer to the returned buffer. + * @param Timeout Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -5633,10 +5631,10 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In /** * @brief Read derivative key in polling mode when CRYP hardware block is set * in key derivation operating mode (mode 2). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Output Pointer to the returned buffer. + * @param Timeout Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout) @@ -5680,11 +5678,11 @@ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output /** * @brief Set the DMA configuration and start the DMA transfer. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param inputaddr: Address of the Input buffer. - * @param Size: Size of the Input buffer in bytes, must be a multiple of 16. - * @param outputaddr: Address of the Output buffer. + * @param inputaddr Address of the Input buffer. + * @param Size Size of the Input buffer in bytes, must be a multiple of 16. + * @param outputaddr Address of the Output buffer. * @retval None */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -5714,9 +5712,9 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin /** * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5742,9 +5740,9 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T /** * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5770,7 +5768,7 @@ static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uin /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -5786,7 +5784,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -5811,7 +5809,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) @@ -5827,10 +5825,10 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Last header or payload block padding when size is not a multiple of 128 bits. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param difflength: size remainder after having fed all complete 128-bit blocks. - * @param polling: specifies whether or not polling on CCF must be done after having + * @param difflength size remainder after having fed all complete 128-bit blocks. + * @param polling specifies whether or not polling on CCF must be done after having * entered a complete block. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.h index 5c6db996e1..a1ccba99d4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CRYP HAL Extension module. ****************************************************************************** * @attention @@ -100,8 +98,8 @@ /** * @brief Set the phase: Init, header, payload, final. * This is relevant only for GCM and CCM modes. - * @param __HANDLE__: specifies the CRYP handle. - * @param __PHASE__: The phase. + * @param __HANDLE__ specifies the CRYP handle. + * @param __PHASE__ The phase. * @retval None */ #define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.c index d4d656d1b2..6fe6f22bbd 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -225,7 +223,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); /** * @brief Initializes the DAC peripheral according to the specified parameters * in the DAC_InitStruct. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -262,7 +260,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) /** * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -298,7 +296,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) /** * @brief Initializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -313,7 +311,7 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) /** * @brief DeInitializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -350,9 +348,9 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -409,9 +407,9 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -434,15 +432,15 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -560,9 +558,9 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -610,9 +608,9 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -636,7 +634,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -682,7 +680,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @brief Conversion complete callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -697,7 +695,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -712,7 +710,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -727,7 +725,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -761,10 +759,10 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -812,18 +810,18 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /** * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. + * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. + * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) @@ -874,7 +872,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui /** * @brief return the DAC state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ @@ -887,7 +885,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) /** * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval DAC Error Code */ @@ -902,7 +900,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -917,7 +915,7 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -930,7 +928,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.h index c07f889296..d6f3b1fbd5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention @@ -201,42 +199,42 @@ typedef struct */ /** @brief Reset DAC handle state - * @param __HANDLE__: specifies the DAC handle. + * @param __HANDLE__ specifies the DAC handle. * @retval None */ #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) /** @brief Enable the DAC channel - * @param __HANDLE__: specifies the DAC handle. - * @param __DAC_Channel__: specifies the DAC channel + * @param __HANDLE__ specifies the DAC handle. + * @param __DAC_Channel__ specifies the DAC channel * @retval None */ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) /** @brief Disable the DAC channel - * @param __HANDLE__: specifies the DAC handle - * @param __DAC_Channel__: specifies the DAC channel. + * @param __HANDLE__ specifies the DAC handle + * @param __DAC_Channel__ specifies the DAC channel. * @retval None */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) /** @brief Enable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * @retval None */ #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) /** @brief Disable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * @retval None */ #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) /** @brief Checks if the specified DAC interrupt source is enabled or disabled. - * @param __HANDLE__: DAC handle - * @param __INTERRUPT__: DAC interrupt source to check + * @param __HANDLE__ DAC handle + * @param __INTERRUPT__ DAC interrupt source to check * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -245,8 +243,8 @@ typedef struct #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag @@ -255,8 +253,8 @@ typedef struct #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the DAC's flag. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag @@ -364,19 +362,19 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) /** @brief Set DHR12R1 alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__)) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.c index b2053ef170..d734ef51a5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -103,7 +101,7 @@ /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ @@ -121,12 +119,12 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Select max triangle amplitude. + * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 @@ -169,12 +167,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation @@ -217,15 +215,15 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t /** * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status @@ -265,7 +263,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align /** * @brief Conversion complete callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -280,7 +278,7 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -295,7 +293,7 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -310,7 +308,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -325,7 +323,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -340,7 +338,7 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -353,7 +351,7 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.h index d3410f8670..2b19647400 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.c index 421cd0d196..c34720af1e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DCMI HAL module driver * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: @@ -139,7 +137,7 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Initializes the DCMI according to the specified * parameters in the DCMI_InitTypeDef and create the associated handle. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -205,7 +203,7 @@ __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) /** * @brief Deinitializes the DCMI peripheral registers to their default reset * values. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -229,7 +227,7 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) /** * @brief Initializes the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -244,7 +242,7 @@ __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) /** * @brief DeInitializes the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -279,11 +277,11 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) /** * @brief Enables DCMI DMA request and enables DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. - * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab. - * @param pData: The destination memory Buffer address (LCD Frame buffer). - * @param Length: The length of capture to be transferred. + * @param DCMI_Mode DCMI capture mode snapshot or continuous grab. + * @param pData The destination memory Buffer address (LCD Frame buffer). + * @param Length The length of capture to be transferred. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) @@ -365,7 +363,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo /** * @brief Disable DCMI DMA request and Disable DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -417,7 +415,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) /** * @brief Suspend DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -463,7 +461,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) /** * @brief Resume DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -489,7 +487,7 @@ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) /** * @brief Handles DCMI interrupt request. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for the DCMI. * @retval None */ @@ -571,7 +569,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) /** * @brief Error DCMI callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -586,7 +584,7 @@ __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Line Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -601,7 +599,7 @@ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief VSYNC Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -616,7 +614,7 @@ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Frame Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -650,12 +648,12 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Configure the DCMI CROP coordinate. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. - * @param X0: DCMI window X offset - * @param Y0: DCMI window Y offset - * @param XSize: DCMI Pixel per line - * @param YSize: DCMI Line number + * @param X0 DCMI window X offset + * @param Y0 DCMI window Y offset + * @param XSize DCMI Pixel per line + * @param YSize DCMI Line number * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) @@ -687,7 +685,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui /** * @brief Disable the Crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -713,7 +711,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi) /** * @brief Enable the Crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -759,7 +757,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) /** * @brief Return the DCMI state - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL state */ @@ -770,7 +768,7 @@ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) /** * @brief Return the DCMI error code - * @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval DCMI Error Code */ @@ -790,7 +788,7 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -847,7 +845,7 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.h index dd2d4f3916..26359c0bed 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DCMI HAL module. ****************************************************************************** * @attention @@ -233,8 +231,8 @@ typedef struct /** @defgroup DCMI_Window_Vertical_Line DCMI Window Vertical Line * @{ */ -#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */ -#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */ +#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)DCMI_CWSIZE_VLINE_Pos /*!< Required left shift to set crop window vertical line count */ +#define DCMI_POSITION_CWSTRT_VST (uint32_t)DCMI_CWSTRT_VST_Pos /*!< Required left shift to set crop window vertical start line count */ /** * @} @@ -292,21 +290,21 @@ typedef struct */ /** @brief Reset DCMI handle state - * @param __HANDLE__: specifies the DCMI handle. + * @param __HANDLE__ specifies the DCMI handle. * @retval None */ #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) /** * @brief Enable the DCMI. - * @param __HANDLE__: DCMI handle + * @param __HANDLE__ DCMI handle * @retval None */ #define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) /** * @brief Disable the DCMI. - * @param __HANDLE__: DCMI handle + * @param __HANDLE__ DCMI handle * @retval None */ #define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) @@ -314,8 +312,8 @@ typedef struct /* Interrupt & Flag management */ /** * @brief Get the DCMI pending flag. - * @param __HANDLE__: DCMI handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ Get the specified flag. * This parameter can be one of the following values (no combination allowed) * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) @@ -338,8 +336,8 @@ typedef struct /** * @brief Clear the DCMI pending flags. - * @param __HANDLE__: DCMI handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask * @arg DCMI_FLAG_OVRRI: Overrun flag mask @@ -352,8 +350,8 @@ typedef struct /** * @brief Enable the specified DCMI interrupts. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVR: Overrun interrupt mask @@ -366,8 +364,8 @@ typedef struct /** * @brief Disable the specified DCMI interrupts. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVR: Overrun interrupt mask @@ -380,8 +378,8 @@ typedef struct /** * @brief Check whether the specified DCMI interrupt has occurred or not. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt source to check. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt source to check. * This parameter can be one of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVR: Overrun interrupt mask diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.c index 83b10a5555..02db2bd55b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DCMI Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of DCMI extension peripheral: @@ -91,7 +89,7 @@ /** * @brief Initializes the DCMI according to the specified * parameters in the DCMI_InitTypeDef and create the associated handle. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.h index 65e9aacb1d..54e55f8190 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DCMI Extension HAL module. ****************************************************************************** * @attention @@ -180,9 +178,9 @@ typedef struct /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */ -#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */ -#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */ +#define DCMI_POSITION_ESCR_LSC (uint32_t)DCMI_ESCR_LSC_Pos /*!< Required left shift to set line start delimiter */ +#define DCMI_POSITION_ESCR_LEC (uint32_t)DCMI_ESCR_LEC_Pos /*!< Required left shift to set line end delimiter */ +#define DCMI_POSITION_ESCR_FEC (uint32_t)DCMI_ESCR_FEC_Pos /*!< Required left shift to set frame end delimiter */ /* Private macro -------------------------------------------------------------*/ #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h index efa60dee6e..9b92655750 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_def.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** @@ -46,7 +44,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" +/* MBED */ #include "stm32_hal_legacy.h" +/* MBED */ #include /* Exported types ------------------------------------------------------------*/ @@ -86,7 +86,7 @@ typedef enum #define UNUSED(x) ((void)(x)) /** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. + * @param __HANDLE__ specifies the Peripheral Handle. * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter * to HAL_PPP_Init() for the first time, it is mandatory to use this macro @@ -122,6 +122,8 @@ typedef enum do{ \ (__HANDLE__)->Lock = HAL_UNLOCKED; \ }while (0U) + +/* MBED */ #if defined (__CC_ARM) #pragma diag_suppress 3731 #endif @@ -143,10 +145,11 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) } while (__STREXW(newValue, ptr)); } +/* MBED */ #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) && !defined ( __CC_ARM ) +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -157,7 +160,7 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.c index fa50f7da9b..d12ec83c2b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dfsdm.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Digital Filter for Sigma-Delta Modulators * (DFSDM) peripherals: @@ -206,27 +204,9 @@ /** @defgroup DFSDM_Private_Define DFSDM Private Define * @{ */ -#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV) -#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD) -#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR) -#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET) -#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS) -#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR) + #define DFSDM_FLTCR1_MSB_RCH_OFFSET 8U -#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH) -#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH) -#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF) -#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF) -#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF) -#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF) -#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA) -#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA) -#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT) -#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT) -#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX) -#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN) -#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT) -#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF) + #define DFSDM_MSB_MASK 0xFFFF0000U #define DFSDM_LSB_MASK 0x0000FFFFU #define DFSDM_CKAB_TIMEOUT 5000U @@ -303,7 +283,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DFSDM channel according to the specified parameters * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -375,7 +355,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); /* Set the output clock divider */ channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) << - DFSDM_CHCFGR1_CLK_DIV_OFFSET); + DFSDM_CHCFGR1_CKOUTDIV_Pos); } /* enable the DFSDM global interface */ @@ -397,12 +377,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /* Set analog watchdog parameters */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | - ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_FOSR_OFFSET)); + ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos)); /* Set channel offset and right bit shift */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); - hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) | - (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET)); + hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | + (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); /* Enable DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; @@ -441,7 +421,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); /* Set the output clock divider */ DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) << - DFSDM_CHCFGR1_CLK_DIV_OFFSET); + DFSDM_CHCFGR1_CKOUTDIV_Pos); } /* enable the DFSDM global interface */ @@ -463,12 +443,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /* Set analog watchdog parameters */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | - ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_FOSR_OFFSET)); + ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos)); /* Set channel offset and right bit shift */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); - hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) | - (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET)); + hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | + (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); /* Enable DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; @@ -485,7 +465,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /** * @brief De-initialize the DFSDM channel. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -580,7 +560,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /** * @brief Initialize the DFSDM channel MSP. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -594,7 +574,7 @@ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel /** * @brief De-initialize the DFSDM channel MSP. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -632,7 +612,7 @@ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chann * @note If clock is not available on this channel during 5 seconds, * clock absence detection will not be activated and function * will return HAL_TIMEOUT error. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -673,9 +653,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) != 0U) + while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { - filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) @@ -693,9 +673,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) != 0U) + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { - DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) @@ -719,8 +699,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm /** * @brief This function allows to poll for the clock absence detection. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_channel DFSDM channel handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, @@ -762,7 +742,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs tickstart = HAL_GetTick(); /* Wait clock absence detection */ - while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) == 0U) + while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U) { /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) @@ -776,7 +756,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs } /* Clear clock absence detection flag */ - filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); #else /* Get channel number from channel instance */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); @@ -785,7 +765,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs tickstart = HAL_GetTick(); /* Wait clock absence detection */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) == 0U) + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U) { /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) @@ -799,7 +779,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs } /* Clear clock absence detection flag */ - DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); #endif /* defined(DFSDM2_Channel0) */ /* Return function status */ return HAL_OK; @@ -808,7 +788,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief This function allows to stop clock absence detection in polling mode. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -847,7 +827,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); #else /* Stop clock absence detection */ @@ -855,7 +835,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); #endif /* DFSDM2_Channel0 */ } /* Return function status */ @@ -868,7 +848,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ * @note If clock is not available on this channel during 5 seconds, * clock absence detection will not be activated and function * will return HAL_TIMEOUT error. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -910,9 +890,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) != 0U) + while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { - filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) @@ -939,9 +919,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf tickstart = HAL_GetTick(); /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) != 0U) + while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) { - DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Check the Timeout */ if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) @@ -969,7 +949,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf /** * @brief Clock absence detection callback. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -984,7 +964,7 @@ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /** * @brief This function allows to stop clock absence detection in interrupt mode. * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -1023,7 +1003,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Disable clock absence detection interrupt */ filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); @@ -1034,7 +1014,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Disable clock absence detection interrupt */ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); @@ -1048,10 +1028,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief This function allows to start short circuit detection in polling mode. * @note Same mode has to be used for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @param Threshold : Short circuit detector threshold. + * @param hdfsdm_channel DFSDM channel handle. + * @param Threshold Short circuit detector threshold. * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal : Break signals assigned to short circuit event. + * @param BreakSignal Break signals assigned to short circuit event. * This parameter can be a values combination of @ref DFSDM_BreakSignals. * @retval HAL status */ @@ -1076,7 +1056,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ { /* Configure threshold and break signals */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); - hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \ + hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ Threshold); /* Start short circuit detection */ @@ -1088,8 +1068,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ /** * @brief This function allows to poll for the short circuit detection. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_channel DFSDM channel handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, @@ -1130,7 +1110,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd tickstart = HAL_GetTick(); /* Wait short circuit detection */ - while(((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0U) + while(((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U) { /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) @@ -1144,14 +1124,14 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd } /* Clear short circuit detection flag */ - filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); #else /* Get timeout */ tickstart = HAL_GetTick(); /* Wait short circuit detection */ - while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0U) + while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U) { /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) @@ -1165,7 +1145,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd } /* Clear short circuit detection flag */ - DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); #endif /* DFSDM2_Channel0 */ /* Return function status */ @@ -1175,7 +1155,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd /** * @brief This function allows to stop short circuit detection in polling mode. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -1214,9 +1194,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c filter0Instance = DFSDM2_Filter0; } - filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); #else - DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); #endif /* DFSDM2_Channel0*/ } /* Return function status */ @@ -1226,10 +1206,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c /** * @brief This function allows to start short circuit detection in interrupt mode. * @note Same mode has to be used for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @param Threshold : Short circuit detector threshold. + * @param hdfsdm_channel DFSDM channel handle. + * @param Threshold Short circuit detector threshold. * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal : Break signals assigned to short circuit event. + * @param BreakSignal Break signals assigned to short circuit event. * This parameter can be a values combination of @ref DFSDM_BreakSignals. * @retval HAL status */ @@ -1274,7 +1254,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Configure threshold and break signals */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); - hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \ + hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ Threshold); /* Start short circuit detection */ @@ -1286,7 +1266,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief Short circuit detection callback. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -1301,7 +1281,7 @@ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_cha /** * @brief This function allows to stop short circuit detection in interrupt mode. * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -1339,12 +1319,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd filter0Instance = DFSDM2_Filter0; } - filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); /* Disable short circuit detection interrupt */ filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); #else - DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); /* Disable short circuit detection interrupt */ DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); @@ -1356,7 +1336,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd /** * @brief This function allows to get channel analog watchdog value. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval Channel analog watchdog value. */ int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -1366,8 +1346,8 @@ int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel /** * @brief This function allows to modify channel offset value. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Offset : DFSDM channel offset. + * @param hdfsdm_channel DFSDM channel handle. + * @param Offset DFSDM channel offset. * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. * @retval HAL status. */ @@ -1390,7 +1370,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf { /* Modify channel offset */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET); - hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET); + hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos); } /* Return function status */ return status; @@ -1415,7 +1395,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf /** * @brief This function allows to get the current DFSDM channel handle state. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval DFSDM channel state. */ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -1445,7 +1425,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp /** * @brief Initialize the DFSDM filter according to the specified parameters * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1543,7 +1523,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Set filter parameters */ hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR); hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder | - ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_OFFSET) | + ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) | (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U)); /* Store regular and injected triggers and injected scan mode*/ @@ -1563,7 +1543,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief De-initializes the DFSDM filter. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1591,7 +1571,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /** * @brief Initializes the DFSDM filter MSP. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1605,7 +1585,7 @@ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief De-initializes the DFSDM filter MSP. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1638,10 +1618,10 @@ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief This function allows to select channel and to enable/disable * continuous mode for regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channel for regular conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channel for regular conversion. * This parameter can be a value of @ref DFSDM_Channel_Selection. - * @param ContinuousMode : Enable/disable continuous mode for regular conversion. + * @param ContinuousMode Enable/disable continuous mode for regular conversion. * This parameter can be a value of @ref DFSDM_ContinuousMode. * @retval HAL status */ @@ -1685,8 +1665,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to select channels for injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channels for injected conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channels for injected conversion. * This parameter can be a values combination of @ref DFSDM_Channel_Selection. * @retval HAL status */ @@ -1757,7 +1737,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h * @brief This function allows to start regular conversion in polling mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1785,8 +1765,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsd /** * @brief This function allows to poll for the end of regular conversion. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_filter DFSDM filter handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1847,7 +1827,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop regular conversion in polling mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1877,7 +1857,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm * @brief This function allows to start regular conversion in interrupt mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1908,7 +1888,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to stop regular conversion in interrupt mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1944,9 +1924,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf * Please note that data on buffer will contain signed regular conversion * value on 24 most significant bits and corresponding channel on 3 least * significant bits. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2021,9 +2001,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h * in idle state or if injected conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2094,7 +2074,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef /** * @brief This function allows to stop regular conversion in DMA mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2132,8 +2112,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to get regular conversion value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel of regular conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel of regular conversion. * @retval Regular conversion value */ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2151,7 +2131,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte /* Extract channel and regular conversion value */ *Channel = (reg & DFSDM_FLTRDATAR_RDATACH); - value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos); /* return regular conversion value */ return value; @@ -2161,7 +2141,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte * @brief This function allows to start injected conversion in polling mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2189,8 +2169,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief This function allows to poll for the end of injected conversion. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_filter DFSDM filter handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2261,7 +2241,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop injected conversion in polling mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2291,7 +2271,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd * @brief This function allows to start injected conversion in interrupt mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2322,7 +2302,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to stop injected conversion in interrupt mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2358,9 +2338,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd * Please note that data on buffer will contain signed injected conversion * value on 24 most significant bits and corresponding channel on 3 least * significant bits. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2433,9 +2413,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef * * in idle state or if regular conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2504,7 +2484,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop injected conversion in DMA mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2542,8 +2522,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to get injected conversion value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel of injected conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel of injected conversion. * @retval Injected conversion value */ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2561,7 +2541,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /* Extract channel and injected conversion value */ *Channel = (reg & DFSDM_FLTJDATAR_JDATACH); - value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos); /* return regular conversion value */ return value; @@ -2569,8 +2549,8 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /** * @brief This function allows to start filter analog watchdog in interrupt mode. - * @param hdfsdm_filter : DFSDM filter handle. - * @param awdParam : DFSDM filter analog watchdog parameters. + * @param hdfsdm_filter DFSDM filter handle. + * @param awdParam DFSDM filter analog watchdog parameters. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2602,15 +2582,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs /* Set thresholds and break signals */ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); - hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \ + hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \ awdParam->HighBreakSignal); hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); - hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \ + hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \ awdParam->LowBreakSignal); /* Set channels and interrupt for analog watchdog */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH); - hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \ + hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \ DFSDM_FLTCR2_AWDIE); } /* Return function status */ @@ -2619,7 +2599,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief This function allows to stop filter analog watchdog in interrupt mode. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2657,8 +2637,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_ /** * @brief This function allows to start extreme detector feature. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channels where extreme detector is enabled. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channels where extreme detector is enabled. * This parameter can be a values combination of @ref DFSDM_Channel_Selection. * @retval HAL status */ @@ -2682,7 +2662,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi { /* Set channels for extreme detector */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); - hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET); + hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); } /* Return function status */ return status; @@ -2690,7 +2670,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi /** * @brief This function allows to stop extreme detector feature. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2726,8 +2706,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function allows to get extreme detector maximum value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. * @retval Extreme detector maximum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ @@ -2746,7 +2726,7 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Extract channel and extreme detector maximum value */ *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH); - value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos); /* return extreme detector maximum value */ return value; @@ -2754,8 +2734,8 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief This function allows to get extreme detector minimum value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. * @retval Extreme detector minimum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ @@ -2774,7 +2754,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /* Extract channel and extreme detector minimum value */ *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH); - value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET); + value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos); /* return extreme detector minimum value */ return value; @@ -2782,7 +2762,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief This function allows to get conversion time value. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval Conversion time value * @note To get time in second, this value has to be divided by DFSDM clock frequency. */ @@ -2798,7 +2778,7 @@ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_fil reg = hdfsdm_filter->Instance->FLTCNVTIMR; /* Extract conversion time value */ - value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET); + value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos); /* return extreme detector minimum value */ return value; @@ -2806,7 +2786,7 @@ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function handles the DFSDM interrupts. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2895,7 +2875,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; if(threshold == DFSDM_AWD_HIGH_THRESHOLD) { - reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET; + reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos; } while((reg & 1U) == 0U) { @@ -2904,7 +2884,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } /* Clear analog watchdog flag */ hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \ - (1U << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \ + (1U << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \ (1U << channel); /* Call analog watchdog callback */ @@ -2918,7 +2898,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) uint32_t reg = 0U; uint32_t channel = 0U; - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET); + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); while(channel < DFSDM1_CHANNEL_NUMBER) { @@ -2929,7 +2909,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U) { /* Clear clock absence flag */ - hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Call clock absence callback */ HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]); @@ -2948,7 +2928,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) uint32_t reg = 0U; uint32_t channel = 0U; - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET); + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); while(channel < DFSDM2_CHANNEL_NUMBER) { @@ -2959,7 +2939,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) if((a_dfsdm2ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U) { /* Clear clock absence flag */ - hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel)); + hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Call clock absence callback */ HAL_DFSDM_ChannelCkabCallback(a_dfsdm2ChannelHandle[channel]); @@ -2979,7 +2959,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) uint32_t channel = 0U; /* Get channel */ - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET); + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); while((reg & 1U) == 0U) { channel++; @@ -2987,7 +2967,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } /* Clear short circuit detection flag */ - hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); /* Call short circuit detection callback */ HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]); @@ -3002,7 +2982,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) uint32_t channel = 0U; /* Get channel */ - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET); + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); while((reg & 1U) == 0U) { channel++; @@ -3010,7 +2990,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) } /* Clear short circuit detection flag */ - hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel)); + hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); /* Call short circuit detection callback */ HAL_DFSDM_ChannelScdCallback(a_dfsdm2ChannelHandle[channel]); @@ -3022,7 +3002,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) * @brief Regular conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetRegularValue. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -3036,7 +3016,7 @@ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief Half regular conversion complete callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -3052,7 +3032,7 @@ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * * @brief Injected conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetInjectedValue. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -3066,7 +3046,7 @@ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief Half injected conversion complete callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -3080,9 +3060,9 @@ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * /** * @brief Filter analog watchdog callback. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. - * @param Threshold : Low or high threshold has been reached. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. + * @param Threshold Low or high threshold has been reached. * @retval None */ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -3100,7 +3080,7 @@ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filte /** * @brief Error callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -3132,7 +3112,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function allows to get the current DFSDM filter handle state. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter state. */ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -3143,7 +3123,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to get the current DFSDM filter error. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter error code. */ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -3201,8 +3181,8 @@ void HAL_DFSDM_BitstreamClock_Stop(void) /** * @brief Disable Delay Clock for DFSDM1/2. - * @param MCHDLY: HAL_MCHDLY_CLOCK_DFSDM2. - * HAL_MCHDLY_CLOCK_DFSDM1. + * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2. + * HAL_MCHDLY_CLOCK_DFSDM1. * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called * before HAL_DFSDM_DisableDelayClock() * @retval None @@ -3228,8 +3208,8 @@ void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY) /** * @brief Enable Delay Clock for DFSDM1/2. - * @param MCHDLY: HAL_MCHDLY_CLOCK_DFSDM2. - * HAL_MCHDLY_CLOCK_DFSDM1. + * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2. + * HAL_MCHDLY_CLOCK_DFSDM1. * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called * before HAL_DFSDM_EnableDelayClock() * @retval None @@ -3248,10 +3228,10 @@ void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY) /** * @brief Select the source for CKin signals for DFSDM1/2. - * @param source: DFSDM2_CKIN_PAD. - * DFSDM2_CKIN_DM. - * DFSDM1_CKIN_PAD. - * DFSDM1_CKIN_DM. + * @param source DFSDM2_CKIN_PAD. + * DFSDM2_CKIN_DM. + * DFSDM1_CKIN_PAD. + * DFSDM1_CKIN_DM. * @retval None */ void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source) @@ -3284,7 +3264,7 @@ void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source) * @param source: DFSDM2_CKOUT_DFSDM2. * DFSDM2_CKOUT_M27. * DFSDM1_CKOUT_DFSDM1. - * DFSDM1_CKOUT_M27. + * DFSDM1_CKOUT_M27. * @retval None */ void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source) @@ -3314,10 +3294,10 @@ void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source) /** * @brief Select the source for DataIn0 signals for DFSDM1/2. - * @param source: DATAIN0_DFSDM2_PAD. - * DATAIN0_DFSDM2_DATAIN1. - * DATAIN0_DFSDM1_PAD. - * DATAIN0_DFSDM1_DATAIN1. + * @param source DATAIN0_DFSDM2_PAD. + * DATAIN0_DFSDM2_DATAIN1. + * DATAIN0_DFSDM1_PAD. + * DATAIN0_DFSDM1_DATAIN1. * @retval None */ void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source) @@ -3345,10 +3325,10 @@ void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source) /** * @brief Select the source for DataIn2 signals for DFSDM1/2. - * @param source: DATAIN2_DFSDM2_PAD. - * DATAIN2_DFSDM2_DATAIN3. - * DATAIN2_DFSDM1_PAD. - * DATAIN2_DFSDM1_DATAIN3. + * @param source DATAIN2_DFSDM2_PAD. + * DATAIN2_DFSDM2_DATAIN3. + * DATAIN2_DFSDM1_PAD. + * DATAIN2_DFSDM1_DATAIN3. * @retval None */ void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source) @@ -3376,8 +3356,8 @@ void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source) /** * @brief Select the source for DataIn4 signals for DFSDM2. - * @param source: DATAIN4_DFSDM2_PAD. - * DATAIN4_DFSDM2_DATAIN5 + * @param source DATAIN4_DFSDM2_PAD. + * DATAIN4_DFSDM2_DATAIN5 * @retval None */ void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source) @@ -3394,8 +3374,8 @@ void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source) /** * @brief Select the source for DataIn6 signals for DFSDM2. - * @param source: DATAIN6_DFSDM2_PAD. - * DATAIN6_DFSDM2_DATAIN7. + * @param source DATAIN6_DFSDM2_PAD. + * DATAIN6_DFSDM2_DATAIN7. * @retval None */ void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source) @@ -3414,18 +3394,18 @@ void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source) /** * @brief Configure the distribution of the bitstream clock gated from TIM4_OC * for DFSDM1 or TIM3_OC for DFSDM2 - * @param source: DFSDM1_CLKIN0_TIM4OC2 - * DFSDM1_CLKIN2_TIM4OC2 - * DFSDM1_CLKIN1_TIM4OC1 - * DFSDM1_CLKIN3_TIM4OC1 - * DFSDM2_CLKIN0_TIM3OC4 - * DFSDM2_CLKIN4_TIM3OC4 - * DFSDM2_CLKIN1_TIM3OC3 - * DFSDM2_CLKIN5_TIM3OC3 - * DFSDM2_CLKIN2_TIM3OC2 - * DFSDM2_CLKIN6_TIM3OC2 - * DFSDM2_CLKIN3_TIM3OC1 - * DFSDM2_CLKIN7_TIM3OC1 + * @param source DFSDM1_CLKIN0_TIM4OC2 + * DFSDM1_CLKIN2_TIM4OC2 + * DFSDM1_CLKIN1_TIM4OC1 + * DFSDM1_CLKIN3_TIM4OC1 + * DFSDM2_CLKIN0_TIM3OC4 + * DFSDM2_CLKIN4_TIM3OC4 + * DFSDM2_CLKIN1_TIM3OC3 + * DFSDM2_CLKIN5_TIM3OC3 + * DFSDM2_CLKIN2_TIM3OC2 + * DFSDM2_CLKIN6_TIM3OC2 + * DFSDM2_CLKIN3_TIM3OC1 + * DFSDM2_CLKIN7_TIM3OC1 * @retval None */ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source) @@ -3479,7 +3459,7 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source) * or demuxes: M1, M2, M3, M4, M5, M6, M7, M8, DM1, DM2, DM3, DM4, DM5, DM6, * M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 based on the * contains of the DFSDM_MultiChannelConfigTypeDef structure - * @param mchdlystruct: Structure of multi channel configuration + * @param mchdlystruct Structure of multi channel configuration * @retval None * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called * before HAL_DFSDM_ConfigMultiChannelDelay() @@ -3523,7 +3503,7 @@ void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlyst /** * @brief DMA half transfer complete callback for regular conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -3537,7 +3517,7 @@ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete callback for regular conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) @@ -3551,7 +3531,7 @@ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback for injected conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -3565,7 +3545,7 @@ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete callback for injected conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) @@ -3579,7 +3559,7 @@ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) @@ -3596,7 +3576,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function allows to get the number of injected channels. - * @param Channels : bitfield of injected channels. + * @param Channels bitfield of injected channels. * @retval Number of injected channels. */ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) @@ -3619,7 +3599,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) /** * @brief This function allows to get the channel number from channel instance. - * @param Instance : DFSDM channel instance. + * @param Instance DFSDM channel instance. * @retval Channel number. */ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) @@ -3684,7 +3664,7 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) /** * @brief This function allows to really start regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -3725,7 +3705,7 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really stop regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -3761,7 +3741,7 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really start injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -3805,7 +3785,7 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really stop injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h index db72ad9b0b..a64bcb8982 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dfsdm.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DFSDM HAL module. ****************************************************************************** * @attention @@ -692,13 +690,13 @@ typedef struct */ /** @brief Reset DFSDM channel handle state. - * @param __HANDLE__: DFSDM channel handle. + * @param __HANDLE__ DFSDM channel handle. * @retval None */ #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) /** @brief Reset DFSDM filter handle state. - * @param __HANDLE__: DFSDM filter handle. + * @param __HANDLE__ DFSDM filter handle. * @retval None */ #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c index 03092857ea..b7efc71941 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -182,7 +180,7 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and create the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ @@ -321,7 +319,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /** * @brief DeInitializes the DMA peripheral - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ @@ -408,11 +406,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /** * @brief Starts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -452,11 +450,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /** * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -512,7 +510,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /** * @brief Aborts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * * @note After disabling a DMA Stream, a check for wait until the DMA Stream is @@ -585,7 +583,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /** * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ @@ -610,13 +608,13 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) /** * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CompleteLevel: Specifies the DMA level complete. + * @param CompleteLevel Specifies the DMA level complete. * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. * This model could be used for debug purpose. * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) @@ -708,7 +706,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Clear the Direct Mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; } - tmpisr = regs->ISR; } if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) @@ -752,7 +749,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /** * @brief Handles DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ @@ -969,11 +966,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /** * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a DMA_HandleTypeDef structure as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to + * @param pCallback pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -1031,9 +1028,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call /** * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -1118,7 +1115,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca /** * @brief Returns the DMA state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL state */ @@ -1129,7 +1126,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) /** * @brief Return the DMA error code - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval DMA Error Code */ @@ -1152,11 +1149,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) /** * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -1167,7 +1164,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; - /* Peripheral to Memory */ + /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Stream destination address */ @@ -1176,7 +1173,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; } - /* Memory to Peripheral */ + /* Peripheral to Memory */ else { /* Configure DMA Stream source address */ @@ -1189,7 +1186,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /** * @brief Returns the DMA Stream base address depending on stream number - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ @@ -1217,7 +1214,7 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) /** * @brief Check compatibility between FIFO threshold level and size of the memory burst - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h index 18cc962dcd..75a8cc7f3a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -378,8 +376,8 @@ typedef struct __DMA_HandleTypeDef * @brief DMA flag definitions * @{ */ -#define DMA_FLAG_FEIF0_4 0x00800001U -#define DMA_FLAG_DMEIF0_4 0x00800004U +#define DMA_FLAG_FEIF0_4 0x00000001U +#define DMA_FLAG_DMEIF0_4 0x00000004U #define DMA_FLAG_TEIF0_4 0x00000008U #define DMA_FLAG_HTIF0_4 0x00000010U #define DMA_FLAG_TCIF0_4 0x00000020U @@ -409,14 +407,14 @@ typedef struct __DMA_HandleTypeDef /* Exported macro ------------------------------------------------------------*/ /** @brief Reset DMA handle state - * @param __HANDLE__: specifies the DMA handle. + * @param __HANDLE__ specifies the DMA handle. * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Return the current DMA Stream FIFO filled level. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The FIFO filling state. * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full * and not empty. @@ -430,14 +428,14 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Stream. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) /** * @brief Disable the specified DMA Stream. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) @@ -446,7 +444,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ @@ -466,7 +464,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream half transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ @@ -486,7 +484,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream transfer error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ @@ -506,7 +504,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream FIFO error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified FIFO error flag index. */ #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ @@ -526,7 +524,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream direct mode error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified direct mode error flag index. */ #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ @@ -546,8 +544,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Get the DMA Stream pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCIFx: Transfer complete flag. * @arg DMA_FLAG_HTIFx: Half transfer complete flag. @@ -564,8 +562,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Clear the DMA Stream pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCIFx: Transfer complete flag. * @arg DMA_FLAG_HTIFx: Half transfer complete flag. @@ -582,8 +580,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Stream interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -597,8 +595,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Disable the specified DMA Stream interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -612,8 +610,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -628,8 +626,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Writes the number of data units to be transferred on the DMA Stream. - * @param __HANDLE__: DMA handle - * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) + * @param __HANDLE__ DMA handle + * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) * Number of data items depends only on the Peripheral data format. * * @note If Peripheral data format is Bytes: number of data units is equal @@ -647,7 +645,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * * @retval The number of remaining data units in the current DMA Stream transfer. */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c index a55c463675..832c80c194 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma2d.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DMA2D HAL module driver. * This file provides firmware functions to manage the following * functionalities of the DMA2D peripheral: @@ -159,21 +157,21 @@ /** @defgroup DMA2D_Shifts DMA2D Shifts * @{ */ -#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */ -#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */ +#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)DMA2D_FGPFCCR_CS_Pos /*!< Required left shift to set foreground CLUT size */ +#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)DMA2D_BGPFCCR_CS_Pos /*!< Required left shift to set background CLUT size */ -#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */ -#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */ +#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)DMA2D_FGPFCCR_CCM_Pos /*!< Required left shift to set foreground CLUT color mode */ +#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)DMA2D_BGPFCCR_CCM_Pos /*!< Required left shift to set background CLUT color mode */ -#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */ +#define DMA2D_POSITION_AMTCR_DT (uint32_t)DMA2D_AMTCR_DT_Pos /*!< Required left shift to set deadtime value */ -#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */ -#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */ +#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)DMA2D_FGPFCCR_AM_Pos /*!< Required left shift to set foreground alpha mode */ +#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)DMA2D_BGPFCCR_AM_Pos /*!< Required left shift to set background alpha mode */ -#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */ -#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */ +#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)DMA2D_FGPFCCR_ALPHA_Pos /*!< Required left shift to set foreground alpha value */ +#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)DMA2D_BGPFCCR_ALPHA_Pos /*!< Required left shift to set background alpha value */ -#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */ +#define DMA2D_POSITION_NLR_PL (uint32_t)DMA2D_NLR_PL_Pos /*!< Required left shift to set pixels per lines value */ /** * @} */ @@ -218,7 +216,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ /** * @brief Initialize the DMA2D according to the specified * parameters in the DMA2D_InitTypeDef and create the associated handle. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ @@ -268,7 +266,7 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) /** * @brief Deinitializes the DMA2D peripheral registers to their default reset * values. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -345,7 +343,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) /** * @brief Initializes the DMA2D MSP. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -361,7 +359,7 @@ __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) /** * @brief DeInitializes the DMA2D MSP. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -415,15 +413,15 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) /** * @brief Start the DMA2D Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param pdata: Configure the source memory Buffer address if + * @param pdata Configure the source memory Buffer address if * Memory-to-Memory or Memory-to-Memory with pixel format * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -449,15 +447,15 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u /** * @brief Start the DMA2D Transfer with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param pdata: Configure the source memory Buffer address if + * @param pdata Configure the source memory Buffer address if * the Memory-to-Memory or Memory-to-Memory with pixel format * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -486,13 +484,13 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata /** * @brief Start the multi-source DMA2D Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address for the foreground layer. - * @param SrcAddress2: The source memory Buffer address for the background layer. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -521,13 +519,13 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t /** * @brief Start the multi-source DMA2D Transfer with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address for the foreground layer. - * @param SrcAddress2: The source memory Buffer address for the background layer. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -559,7 +557,7 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 /** * @brief Abort the DMA2D Transfer. - * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ @@ -608,7 +606,7 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) /** * @brief Suspend the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ @@ -658,7 +656,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) /** * @brief Resume the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ @@ -682,9 +680,9 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) /** * @brief Enable the DMA2D CLUT Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -716,11 +714,11 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay /** * @brief Start DMA2D CLUT Loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). @@ -771,11 +769,11 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT /** * @brief Start DMA2D CLUT Loading with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -831,9 +829,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC /** * @brief Abort the DMA2D CLUT loading. - * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -887,9 +885,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3 /** * @brief Suspend the DMA2D CLUT loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -944,9 +942,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin /** * @brief Resume the DMA2D CLUT loading. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -983,9 +981,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint /** * @brief Polling for transfer complete or CLUT loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) @@ -1110,7 +1108,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ } /** * @brief Handle DMA2D interrupt request. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ @@ -1270,7 +1268,7 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /** * @brief Transfer watermark callback. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -1286,7 +1284,7 @@ __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) /** * @brief CLUT Transfer Complete callback. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -1325,9 +1323,9 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) /** * @brief Configure the DMA2D Layer according to the specified * parameters in the DMA2D_InitTypeDef and create the associated handle. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -1408,11 +1406,11 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /** * @brief Configure the DMA2D CLUT Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -1462,9 +1460,9 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf /** * @brief Configure the line watermark. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param Line: Line Watermark configuration (maximum 16-bit long value expected). + * @param Line Line Watermark configuration (maximum 16-bit long value expected). * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. * @note The transfer watermark interrupt is disabled once it has occurred. * @retval HAL status @@ -1505,7 +1503,7 @@ HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32 /** * @brief Enable DMA2D dead time feature. - * @param hdma2d: DMA2D handle. + * @param hdma2d DMA2D handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) @@ -1528,7 +1526,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) /** * @brief Disable DMA2D dead time feature. - * @param hdma2d: DMA2D handle. + * @param hdma2d DMA2D handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) @@ -1553,8 +1551,8 @@ HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) * @brief Configure dead time. * @note The dead time value represents the guaranteed minimum number of cycles between * two consecutive transactions on the AHB bus. - * @param hdma2d: DMA2D handle. - * @param DeadTime: dead time value. + * @param hdma2d DMA2D handle. + * @param DeadTime dead time value. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) @@ -1597,7 +1595,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t /** * @brief Return the DMA2D state - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL state */ @@ -1608,7 +1606,7 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) /** * @brief Return the DMA2D error code - * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for DMA2D. * @retval DMA2D Error Code */ @@ -1631,12 +1629,12 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) /** * @brief Set the DMA2D transfer parameters. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the specified DMA2D. - * @param pdata: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param Width: The width of data to be transferred from source to destination. - * @param Height: The height of data to be transferred from source to destination. + * @param pdata The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param Width The width of data to be transferred from source to destination. + * @param Height The height of data to be transferred from source to destination. * @retval HAL status */ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.h index 79f6d6bba9..1853593631 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma2d.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DMA2D HAL module. ****************************************************************************** * @attention @@ -292,14 +290,14 @@ typedef struct __DMA2D_HandleTypeDef */ /** @brief Reset DMA2D handle state - * @param __HANDLE__: specifies the DMA2D handle. + * @param __HANDLE__ specifies the DMA2D handle. * @retval None */ #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) /** * @brief Enable the DMA2D. - * @param __HANDLE__: DMA2D handle + * @param __HANDLE__ DMA2D handle * @retval None. */ #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) @@ -307,8 +305,8 @@ typedef struct __DMA2D_HandleTypeDef /* Interrupt & Flag management */ /** * @brief Get the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: flag to check. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ flag to check. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag @@ -322,8 +320,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Clear the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag @@ -337,8 +335,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Enable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -352,8 +350,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Disable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -367,8 +365,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Check whether the specified DMA2D interrupt source is enabled or not. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt source to check. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. * This parameter can be one of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.c index 71e020193c..48cfd77685 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: @@ -108,12 +106,12 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres /** * @brief Starts the multi_buffer DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) @@ -162,12 +160,12 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S /** * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) @@ -243,10 +241,10 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ /** * @brief Change the memory0 or memory1 address on the fly. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param Address: The new address - * @param memory: the memory to be changed, This parameter can be one of + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of * the following values: * MEMORY0 / * MEMORY1 @@ -285,11 +283,11 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre /** * @brief Set the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.h index 501968a3e8..b32e83773a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c index 9d51d9e322..ddbb0c52eb 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c @@ -2,14 +2,12 @@ ****************************************************************************** * @file stm32f4xx_hal_dsi.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DSI HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the DSI peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State and Errors functions ****************************************************************************** * @attention @@ -39,7 +37,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -47,13 +45,14 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ -/** @addtogroup DSI - * @{ - */ #ifdef HAL_DSI_MODULE_ENABLED -#if defined(STM32F469xx) || defined(STM32F479xx) +#if defined(DSI) + +/** @addtogroup DSI + * @{ + */ /* Private types -------------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ @@ -88,16 +87,16 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32 /* Private functions ---------------------------------------------------------*/ /** * @brief Generic DSI packet header configuration - * @param DSIx: Pointer to DSI register base - * @param ChannelID: Virtual channel ID of the header packet - * @param DataType: Packet data type of the header packet + * @param DSIx Pointer to DSI register base + * @param ChannelID Virtual channel ID of the header packet + * @param DataType Packet data type of the header packet * This parameter can be any value of : * @ref DSI_SHORT_WRITE_PKT_Data_Type * or @ref DSI_LONG_WRITE_PKT_Data_Type * or @ref DSI_SHORT_READ_PKT_Data_Type * or DSI_MAX_RETURN_PKT_SIZE - * @param Data0: Word count LSB - * @param Data1: Word count MSB + * @param Data0 Word count LSB + * @param Data1 Word count MSB * @retval None */ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, @@ -118,142 +117,142 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, /** @defgroup DSI_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the DSI - (+) De-initialize the DSI + (+) De-initialize the DSI @endverbatim * @{ */ - + /** * @brief Initializes the DSI according to the specified * parameters in the DSI_InitTypeDef and create the associated handle. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains - * the PLL Clock structure definition for the DSI. + * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains + * the PLL Clock structure definition for the DSI. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) { - uint32_t tickstart = 0U; - uint32_t unitIntervalx4 = 0U; - uint32_t tempIDF = 0U; - + uint32_t tickstart; + uint32_t unitIntervalx4; + uint32_t tempIDF; + /* Check the DSI handle allocation */ if(hdsi == NULL) { return HAL_ERROR; } - + /* Check function parameters */ assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); - + if(hdsi->State == HAL_DSI_STATE_RESET) { /* Initialize the low level hardware */ HAL_DSI_MspInit(hdsi); } - + /* Change DSI peripheral state */ hdsi->State = HAL_DSI_STATE_BUSY; - + /**************** Turn on the regulator and enable the DSI PLL ****************/ - - /* Enable the regulator */ - __HAL_DSI_REG_ENABLE(hdsi); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the regulator is ready */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET) + + /* Enable the regulator */ + __HAL_DSI_REG_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the regulator is ready */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } - - /* Set the PLL division factors */ - hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); - hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U)); - - /* Enable the DSI PLL */ - __HAL_DSI_PLL_ENABLE(hdsi); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for the lock of the PLL */ - while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + } + + /* Set the PLL division factors */ + hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U)); + + /* Enable the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } - + } + /*************************** Set the PHY parameters ***************************/ - - /* D-PHY clock and digital enable*/ - hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); - - /* Clock lane configuration */ - hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); - hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); - - /* Configure the number of active data lanes */ - hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; - hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; - + + /* D-PHY clock and digital enable*/ + hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Clock lane configuration */ + hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); + hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); + + /* Configure the number of active data lanes */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; + hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; + /************************ Set the DSI clock parameters ************************/ - - /* Set the TX escape clock division factor */ - hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; - hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; - - /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ - /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ - /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ - tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U; - unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV); - - /* Set the bit period in high-speed mode */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4; - hdsi->Instance->WPCR[0U] |= unitIntervalx4; - + + /* Set the TX escape clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; + hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; + + /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ + /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ + /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ + tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U; + unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV); + + /* Set the bit period in high-speed mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4; + hdsi->Instance->WPCR[0U] |= unitIntervalx4; + /****************************** Error management *****************************/ - - /* Disable all error interrupts and reset the Error Mask */ - hdsi->Instance->IER[0U] = 0U; - hdsi->Instance->IER[1U] = 0U; - hdsi->ErrorMsk = 0U; - - /* Initialise the error code */ - hdsi->ErrorCode = HAL_DSI_ERROR_NONE; - + + /* Disable all error interrupts and reset the Error Mask */ + hdsi->Instance->IER[0U] = 0U; + hdsi->Instance->IER[1U] = 0U; + hdsi->ErrorMsk = 0U; + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + /* Initialize the DSI state*/ hdsi->State = HAL_DSI_STATE_READY; - + return HAL_OK; } /** * @brief De-initializes the DSI peripheral registers to their default reset * values. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -264,140 +263,128 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) { return HAL_ERROR; } - + /* Change DSI peripheral state */ hdsi->State = HAL_DSI_STATE_BUSY; - + /* Disable the DSI wrapper */ __HAL_DSI_WRAPPER_DISABLE(hdsi); - + /* Disable the DSI host */ __HAL_DSI_DISABLE(hdsi); - + /* D-PHY clock and digital disable */ hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); - + /* Turn off the DSI PLL */ __HAL_DSI_PLL_DISABLE(hdsi); - + /* Disable the regulator */ __HAL_DSI_REG_DISABLE(hdsi); - + /* DeInit the low level hardware */ - HAL_DSI_MspDeInit(hdsi); - + HAL_DSI_MspDeInit(hdsi); + /* Initialise the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; - + /* Initialize the DSI state*/ hdsi->State = HAL_DSI_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** - * @brief Return the DSI error code - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @brief Enable the error monitor flags + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @retval DSI Error Code - */ -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) -{ - /* Get the error code */ - return hdsi->ErrorCode; -} - -/** - * @brief Enable the error monitor flags - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ActiveErrors: indicates which error interrupts will be enabled. + * @param ActiveErrors indicates which error interrupts will be enabled. * This parameter can be any combination of @ref DSI_Error_Data_Type. - * @retval HAL status + * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) { /* Process locked */ __HAL_LOCK(hdsi); - + hdsi->Instance->IER[0U] = 0U; hdsi->Instance->IER[1U] = 0U; - + /* Store active errors to the handle */ hdsi->ErrorMsk = ActiveErrors; - + if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK; } - + if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK; } - + if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK; } - + if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK; } - + if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK; } - + if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK; } - + if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK; } - + if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK; } - + if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK; } - + if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET) { /* Enable the interrupt generation on selected errors */ hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK; } - + /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -407,12 +394,12 @@ __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) UNUSED(hdsi); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DSI_MspInit could be implemented in the user file - */ + */ } /** * @brief De-initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -428,14 +415,14 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) /** * @} */ - -/** @defgroup DSI_Group2 IO operation functions - * @brief IO operation functions + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides function allowing to: (+) Handle DSI interrupt request @@ -444,14 +431,14 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) */ /** * @brief Handles DSI interrupt request. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. * @retval HAL status */ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) { uint32_t ErrorStatus0, ErrorStatus1; - + /* Tearing Effect Interrupt management ***************************************/ if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET) { @@ -459,12 +446,12 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) { /* Clear the Tearing Effect Interrupt Flag */ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); - + /* Tearing Effect Callback */ HAL_DSI_TearingEffectCallback(hdsi); } } - + /* End of Refresh Interrupt management ***************************************/ if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET) { @@ -472,12 +459,12 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) { /* Clear the End of Refresh Interrupt Flag */ __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); - + /* End of Refresh Callback */ HAL_DSI_EndOfRefreshCallback(hdsi); } } - + /* Error Interrupts management ***********************************************/ if(hdsi->ErrorMsk != 0U) { @@ -485,57 +472,57 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) ErrorStatus0 &= hdsi->Instance->IER[0U]; ErrorStatus1 = hdsi->Instance->ISR[1U]; ErrorStatus1 &= hdsi->Instance->IER[1U]; - + if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET) { hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; } - + if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET) { hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; } - + if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET) { hdsi->ErrorCode |= HAL_DSI_ERROR_TX; } - + if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET) { hdsi->ErrorCode |= HAL_DSI_ERROR_RX; } - + if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET) { hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; } - + if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET) { hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; } - + if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET) { hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; } - + if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET) { hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; } - + if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET) { hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; } - + if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET) { hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; } - + /* Check only selected errors */ if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE) { @@ -547,7 +534,7 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) /** * @brief Tearing Effect DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -562,7 +549,7 @@ __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) /** * @brief End of Refresh DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -577,7 +564,7 @@ __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) /** * @brief Operation Error DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -595,12 +582,40 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) */ /** @defgroup DSI_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the Generic interface read-back Virtual Channel ID + (+) Select video mode and configure the corresponding parameters + (+) Configure command transmission mode: High-speed or Low-power + (+) Configure the flow control + (+) Configure the DSI PHY timer + (+) Configure the DSI HOST timeout + (+) Configure the DSI HOST timeout + (+) Start/Stop the DSI module + (+) Refresh the display in command mode + (+) Controls the display color mode in Video mode + (+) Control the display shutdown in Video mode + (+) write short DCS or short Generic command + (+) write long DCS or long Generic command + (+) Read command (DCS or generic) + (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running) + (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off) + (+) Start/Stop test pattern generation + (+) Slew-Rate And Delay Tuning + (+) Low-Power Reception Filter Tuning + (+) Activate an additional current path on all lanes to meet the SDDTx parameter + (+) Custom lane pins configuration + (+) Set custom timing for the PHY + (+) Force the Clock/Data Lane in TX Stop Mode + (+) Force LP Receiver in Low-Power Mode + (+) Force Data Lanes in RX Mode after a BTA + (+) Enable a pull-down on the lanes to prevent from floating states when unused + (+) Switch off the contention detection on data lanes @endverbatim * @{ @@ -608,39 +623,39 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) /** * @brief Configure the Generic interface read-back Virtual Channel ID. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param VirtualChannelID: Virtual channel ID + * @param VirtualChannelID Virtual channel ID * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Update the GVCID register */ hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID; hdsi->Instance->GVCIDR |= VirtualChannelID; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Select video mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains - * the DSI video mode configuration parameters + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check the parameters */ assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); @@ -660,129 +675,129 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp { assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); } - + /* Select video mode by resetting CMDM and DSIM bits */ hdsi->Instance->MCR &= ~DSI_MCR_CMDM; hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; - + /* Configure the video mode transmission type */ hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; hdsi->Instance->VMCR |= VidCfg->Mode; - + /* Configure the video packet size */ hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; hdsi->Instance->VPCR |= VidCfg->PacketSize; - + /* Set the chunks number to be transmitted through the DSI link */ hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; - + /* Set the size of the null packet */ hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; - + /* Select the virtual channel for the LTDC interface traffic */ hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; - + /* Configure the polarity of control signals */ hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); - + /* Select the color coding for the host */ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; - + /* Select the color coding for the wrapper */ hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U); - + /* Enable/disable the loosely packed variant to 18-bit configuration */ if(VidCfg->ColorCoding == DSI_RGB666) { hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; } - + /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; - + /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; - + /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; hdsi->Instance->VLCR |= VidCfg->HorizontalLine; - + /* Set the Vertical Synchronization Active (VSA) */ hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; - + /* Set the Vertical Back Porch (VBP)*/ hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; - + /* Set the Vertical Front Porch (VFP)*/ hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; - + /* Set the Vertical Active period*/ hdsi->Instance->VVACR &= ~DSI_VVACR_VA; hdsi->Instance->VVACR |= VidCfg->VerticalActive; - + /* Configure the command transmission mode */ hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; - + /* Low power largest packet size */ hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U); - + /* Low power VACT largest packet size */ hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; - + /* Enable LP transition in HFP period */ hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; - + /* Enable LP transition in HBP period */ hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; - + /* Enable LP transition in VACT period */ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; - + /* Enable LP transition in VFP period */ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; - + /* Enable LP transition in VBP period */ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; - + /* Enable LP transition in vertical sync period */ hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; - + /* Enable the request for an acknowledge response at the end of a frame */ hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Select adapted command mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains * the DSI command mode configuration parameters * @retval HAL status */ @@ -790,7 +805,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_ { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check the parameters */ assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); @@ -801,58 +816,58 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_ assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); - + /* Select command mode by setting CMDM and DSIM bits */ hdsi->Instance->MCR |= DSI_MCR_CMDM; hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; - + /* Select the virtual channel for the LTDC interface traffic */ hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; - + /* Configure the polarity of control signals */ hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); - + /* Select the color coding for the host */ hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; - + /* Select the color coding for the wrapper */ hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U); - + /* Configure the maximum allowed size for write memory command */ hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; hdsi->Instance->LCCR |= CmdCfg->CommandSize; - + /* Configure the tearing effect source and polarity and select the refresh mode */ hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol); - + /* Configure the tearing effect acknowledge request */ hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; - + /* Enable the Tearing Effect interrupt */ __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); - + /* Enable the End of Refresh interrupt */ __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Configure command transmission mode: High-speed or Low-power * and enable/disable acknowledge request after packet transmission - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains + * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains * the DSI command transmission mode configuration parameters * @retval HAL status */ @@ -860,7 +875,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe { /* Process locked */ __HAL_LOCK(hdsi); - + assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); @@ -874,7 +889,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); - + /* Select High-speed or Low-power for command transmission */ hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\ DSI_CMCR_GSW1TX |\ @@ -900,22 +915,22 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe LPCmd->LPDcsShortReadNoP |\ LPCmd->LPDcsLongWrite |\ LPCmd->LPMaxReadPacket); - + /* Configure the acknowledge request after each packet transmission */ hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Configure the flow control parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param FlowControl: flow control feature(s) to be enabled. + * @param FlowControl flow control feature(s) to be enabled. * This parameter can be any combination of @ref DSI_FlowControl. * @retval HAL status */ @@ -923,25 +938,25 @@ HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t Fl { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check the parameters */ assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); - + /* Set the DSI Host Protocol Configuration Register */ hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; hdsi->Instance->PCR |= FlowControl; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Configure the DSI PHY timer parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains + * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains * the DSI PHY timing parameters * @retval HAL status */ @@ -950,7 +965,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT uint32_t maxTime; /* Process locked */ __HAL_LOCK(hdsi); - + maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime; /* Clock lane timer configuration */ @@ -966,26 +981,26 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT */ hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U)); - + /* Data lane timer configuration */ hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U)); - + /* Configure the wait period to request HS transmission after a stop state */ hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Configure the DSI HOST timeout parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains + * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains * the DSI host timeout parameters * @retval HAL status */ @@ -993,52 +1008,52 @@ HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_T { /* Process locked */ __HAL_LOCK(hdsi); - + /* Set the timeout clock division factor */ hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U); - + /* High-speed transmission timeout */ hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT; hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U); - + /* Low-power reception timeout */ hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT; hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout; - + /* High-speed read timeout */ hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT; hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout; - + /* Low-power read timeout */ hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT; hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout; - + /* High-speed write timeout */ hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT; hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout; - + /* High-speed write presp mode */ hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM; hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode; - + /* Low-speed write timeout */ hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT; hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout; - + /* BTA timeout */ hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT; hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Start the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1046,22 +1061,22 @@ HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Enable the DSI host */ __HAL_DSI_ENABLE(hdsi); - + /* Enable the DSI wrapper */ __HAL_DSI_WRAPPER_ENABLE(hdsi); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Stop the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1069,22 +1084,22 @@ HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Disable the DSI host */ __HAL_DSI_DISABLE(hdsi); - + /* Disable the DSI wrapper */ __HAL_DSI_WRAPPER_DISABLE(hdsi); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Refresh the display in command mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1092,21 +1107,21 @@ HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Update the display */ hdsi->Instance->WCR |= DSI_WCR_LTDCEN; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Controls the display color mode in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ColorMode: Color mode (full or 8-colors). + * @param ColorMode Color mode (full or 8-colors). * This parameter can be any value of @ref DSI_Color_Mode * @retval HAL status */ @@ -1114,25 +1129,25 @@ HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check the parameters */ assert_param(IS_DSI_COLOR_MODE(ColorMode)); - + /* Update the display color mode */ hdsi->Instance->WCR &= ~DSI_WCR_COLM; hdsi->Instance->WCR |= ColorMode; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Control the display shutdown in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Shutdown: Shut-down (Display-ON or Display-OFF). + * @param Shutdown Shut-down (Display-ON or Display-OFF). * This parameter can be any value of @ref DSI_ShutDown * @retval HAL status */ @@ -1140,31 +1155,31 @@ HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check the parameters */ assert_param(IS_DSI_SHUT_DOWN(Shutdown)); - + /* Update the display Shutdown */ hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; hdsi->Instance->WCR |= Shutdown; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** - * @brief DCS or Generic short write command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @brief write short DCS or short Generic command + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI short packet data type. + * @param ChannelID Virtual channel ID. + * @param Mode DSI short packet data type. * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. - * @param Param1: DSC command or first generic parameter. + * @param Param1 DSC command or first generic parameter. * This parameter can be any value of @ref DSI_DCS_Command or a * generic command code. - * @param Param2: DSC parameter or second generic parameter. + * @param Param2 DSC parameter or second generic parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, @@ -1173,17 +1188,17 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, uint32_t Param1, uint32_t Param2) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Process locked */ __HAL_LOCK(hdsi); - + /* Check the parameters */ assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); - - /* Get tick */ + + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait for Command FIFO Empty */ while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) { @@ -1192,36 +1207,36 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } - + /* Configure the packet to send a short DCS command with 0 or 1 parameter */ DSI_ConfigPacketHeader(hdsi->Instance, ChannelID, Mode, Param1, Param2); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** - * @brief DCS or Generic long write command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @brief write long DCS or long Generic command + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI long packet data type. + * @param ChannelID Virtual channel ID. + * @param Mode DSI long packet data type. * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. - * @param NbParams: Number of parameters. - * @param Param1: DSC command or first generic parameter. - * This parameter can be any value of @ref DSI_DCS_Command or a + * @param NbParams Number of parameters. + * @param Param1 DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a * generic command code - * @param ParametersTable: Pointer to parameter values table. + * @param ParametersTable Pointer to parameter values table. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, @@ -1231,19 +1246,20 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Param1, uint8_t* ParametersTable) { - uint32_t uicounter = 0U, nbBytes = 0U, count = 0U; - uint32_t tickstart = 0U; - uint32_t fifoword = 0U; - + uint32_t uicounter, nbBytes, count; + uint32_t tickstart; + uint32_t fifoword; + uint8_t* pparams = ParametersTable; + /* Process locked */ __HAL_LOCK(hdsi); - + /* Check the parameters */ assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); - - /* Get tick */ + + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait for Command FIFO Empty */ while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET) { @@ -1252,23 +1268,23 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } - + /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/ fifoword = Param1; nbBytes = (NbParams < 3U) ? NbParams : 3U; - + for(count = 0U; count < nbBytes; count++) { - fifoword |= (((uint32_t)(*(ParametersTable + count))) << (8U + (8U*count))); + fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count))); } hdsi->Instance->GPDR = fifoword; - + uicounter = NbParams - nbBytes; - ParametersTable += nbBytes; + pparams += nbBytes; /* Set the Next parameters on the write FIFO command*/ while(uicounter != 0U) { @@ -1276,38 +1292,38 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, fifoword = 0U; for(count = 0U; count < nbBytes; count++) { - fifoword |= (((uint32_t)(*(ParametersTable + count))) << (8U*count)); + fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count)); } hdsi->Instance->GPDR = fifoword; - + uicounter -= nbBytes; - ParametersTable += nbBytes; + pparams += nbBytes; } - + /* Configure the packet to send a long DCS command */ DSI_ConfigPacketHeader(hdsi->Instance, ChannelID, Mode, ((NbParams+1U)&0x00FFU), (((NbParams+1U)&0xFF00U)>>8U)); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Read command (DCS or generic) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelNbr: Virtual channel ID - * @param Array: pointer to a buffer to store the payload of a read back operation. - * @param Size: Data size to be read (in byte). - * @param Mode: DSI read packet data type. + * @param ChannelNbr Virtual channel ID + * @param Array pointer to a buffer to store the payload of a read back operation. + * @param Size Data size to be read (in byte). + * @param Mode DSI read packet data type. * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. - * @param DCSCmd: DCS get/read command. - * @param ParametersTable: Pointer to parameter values table. + * @param DCSCmd DCS get/read command. + * @param ParametersTable Pointer to parameter values table. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, @@ -1318,20 +1334,28 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, uint32_t DCSCmd, uint8_t* ParametersTable) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + uint8_t* pdata = Array; + uint32_t datasize = Size; + /* Process locked */ __HAL_LOCK(hdsi); - + /* Check the parameters */ assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); - - if(Size > 2U) + + if(datasize > 2U) { /* set max return packet size */ - HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFFU), (((Size)>>8U)&0xFFU)); + if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } } - + /* Configure the packet to read command */ if (Mode == DSI_DCS_SHORT_PKT_READ) { @@ -1353,13 +1377,13 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - - return HAL_ERROR; + + return HAL_ERROR; } - - /* Get tick */ + + /* Get tick */ tickstart = HAL_GetTick(); - + /* Check that the payload read FIFO is not empty */ while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE) { @@ -1368,258 +1392,279 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } - + /* Get the first byte */ - *((uint32_t *)Array) = (hdsi->Instance->GPDR); - if (Size > 4U) + *((uint32_t *)pdata) = (hdsi->Instance->GPDR); + if (datasize > 4U) { - Size -= 4U; - Array += 4U; + datasize -= 4U; + pdata += 4U; } else { /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } - - /* Get tick */ + + /* Get tick */ tickstart = HAL_GetTick(); - + /* Get the remaining bytes if any */ - while(((int)(Size)) > 0U) + while(((int)(datasize)) > 0) { if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) { - *((uint32_t *)Array) = (hdsi->Instance->GPDR); - Size -= 4U; - Array += 4U; + *((uint32_t *)pdata) = (hdsi->Instance->GPDR); + datasize -= 4U; + pdata += 4U; } - + /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; - } + } } - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + /* Process locked */ __HAL_LOCK(hdsi); - + /* ULPS Request on Data Lanes */ hdsi->Instance->PUCR |= DSI_PUCR_URDL; - - /* Get tick */ + + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait until the D-PHY active lanes enter into ULPM */ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { - while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET) + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } } else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET) + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } } - + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + /* Process locked */ __HAL_LOCK(hdsi); - + /* Exit ULPS on Data Lanes */ hdsi->Instance->PUCR |= DSI_PUCR_UEDL; - - /* Get tick */ + + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait until all active lanes exit ULPM */ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { - while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } } else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } /* wait for 1 ms*/ HAL_Delay(1U); - + /* De-assert the ULPM requests and the ULPM exit bits */ hdsi->Instance->PUCR = 0U; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + /* Process locked */ __HAL_LOCK(hdsi); - + /* Clock lane configuration: no more HS request */ hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; - + /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR); - + /* ULPS Request on Clock and Data Lanes */ hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); - - /* Get tick */ + + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait until all active lanes exit ULPM */ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET) + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } } else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET) + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } } - + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + /* Turn off the DSI PLL */ __HAL_DSI_PLL_DISABLE(hdsi); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + /* Process locked */ __HAL_LOCK(hdsi); - + /* Turn on the DSI PLL */ __HAL_DSI_PLL_ENABLE(hdsi); - - /* Get tick */ + + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait for the lock of the PLL */ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) { @@ -1628,74 +1673,81 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } - + /* Exit ULPS on Clock and Data Lanes */ hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); - - /* Get tick */ + + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait until all active lanes exit ULPM */ if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } } else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) { - while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_TIMEOUT; } } } - - /* wait for 1 ms*/ + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* wait for 1 ms */ HAL_Delay(1U); - + /* De-assert the ULPM requests and the ULPM exit bits */ hdsi->Instance->PUCR = 0U; - + /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); - + /* Restore clock lane configuration to HS */ hdsi->Instance->CLCR |= DSI_CLCR_DPCC; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Start test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Mode: Pattern generator mode + * @param Mode Pattern generator mode * This parameter can be one of the following values: * 0 : Color bars (horizontal or vertical) * 1 : BER pattern (vertical only) - * @param Orientation: Pattern generator orientation + * @param Orientation Pattern generator orientation * This parameter can be one of the following values: * 0 : Vertical color bars * 1 : Horizontal color bars @@ -1705,23 +1757,23 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_ { /* Process locked */ __HAL_LOCK(hdsi); - + /* Configure pattern generator mode and orientation */ hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U)); - + /* Enable pattern generator by setting PGE bit */ hdsi->Instance->VMCR |= DSI_VMCR_PGE; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Stop test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1729,36 +1781,36 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Disable pattern generator by clearing PGE bit */ hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Set Slew-Rate And Delay Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CommDelay: Communication delay to be adjusted. + * @param CommDelay Communication delay to be adjusted. * This parameter can be any value of @ref DSI_Communication_Delay - * @param Lane: select between clock or data lanes. + * @param Lane select between clock or data lanes. * This parameter can be any value of @ref DSI_Lane_Group - * @param Value: Custom value of the slew-rate or delay + * @param Value Custom value of the slew-rate or delay * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check function parameters */ assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); assert_param(IS_DSI_LANE_GROUP(Lane)); - + switch(CommDelay) { case DSI_SLEW_RATE_HSTX: @@ -1774,6 +1826,13 @@ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uin hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL; hdsi->Instance->WPCR[1U] |= Value<<18U; } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } break; case DSI_SLEW_RATE_LPTX: if(Lane == DSI_CLOCK_LANE) @@ -1788,6 +1847,13 @@ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uin hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL; hdsi->Instance->WPCR[1U] |= Value<<8U; } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } break; case DSI_HS_DELAY: if(Lane == DSI_CLOCK_LANE) @@ -1802,90 +1868,97 @@ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uin hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL; hdsi->Instance->WPCR[1U] |= Value<<2U; } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } break; default: break; } - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Low-Power Reception Filter Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX + * @param Frequency cutoff frequency of low-pass filter at the input of LPRX * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Low-Power RX low-pass Filtering Tuning */ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT; hdsi->Instance->WPCR[1U] |= Frequency<<25U; - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Activate an additional current path on all lanes to meet the SDDTx parameter * defined in the MIPI D-PHY specification - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check function parameters */ assert_param(IS_FUNCTIONAL_STATE(State)); - + /* Activate/Disactivate additional current path on all lanes */ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC; hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Custom lane pins configuration - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CustomLane: Function to be applyed on selected lane. + * @param CustomLane Function to be applyed on selected lane. * This parameter can be any value of @ref DSI_CustomLane - * @param Lane: select between clock or data lane 0 or data lane 1. + * @param Lane select between clock or data lane 0 or data lane 1. * This parameter can be any value of @ref DSI_Lane_Select - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check function parameters */ assert_param(IS_DSI_CUSTOM_LANE(CustomLane)); assert_param(IS_DSI_LANE(Lane)); assert_param(IS_FUNCTIONAL_STATE(State)); - + switch(CustomLane) { case DSI_SWAP_LANE_PINS: - if(Lane == DSI_CLOCK_LANE) + if(Lane == DSI_CLK_LANE) { /* Swap pins on clock lane */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL; @@ -1903,9 +1976,16 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U); } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } break; case DSI_INVERT_HS_SIGNAL: - if(Lane == DSI_CLOCK_LANE) + if(Lane == DSI_CLK_LANE) { /* Invert HS signal on clock lane */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL; @@ -1923,183 +2003,190 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U); } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } break; default: break; } - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Set custom timing for the PHY - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Timing: PHY timing to be adjusted. + * @param Timing PHY timing to be adjusted. * This parameter can be any value of @ref DSI_PHY_Timing - * @param State: ENABLE or DISABLE - * @param Value: Custom value of the timing + * @param State ENABLE or DISABLE + * @param Value Custom value of the timing * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check function parameters */ assert_param(IS_DSI_PHY_TIMING(Timing)); assert_param(IS_FUNCTIONAL_STATE(State)); - + switch(Timing) { case DSI_TCLK_POST: /* Enable/Disable custom timing setting */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U); - - if(State) + + if(State != DISABLE) { /* Set custom value */ hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST; hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST; } - + break; case DSI_TLPX_CLK: /* Enable/Disable custom timing setting */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U); - - if(State) + + if(State != DISABLE) { /* Set custom value */ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC; hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC; } - + break; case DSI_THS_EXIT: /* Enable/Disable custom timing setting */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U); - - if(State) + + if(State != DISABLE) { /* Set custom value */ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT; hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT; } - + break; case DSI_TLPX_DATA: /* Enable/Disable custom timing setting */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U); - - if(State) + + if(State != DISABLE) { /* Set custom value */ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD; hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD; } - + break; case DSI_THS_ZERO: /* Enable/Disable custom timing setting */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U); - - if(State) + + if(State != DISABLE) { /* Set custom value */ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO; hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO; } - + break; case DSI_THS_TRAIL: /* Enable/Disable custom timing setting */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U); - - if(State) + + if(State != DISABLE) { /* Set custom value */ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL; hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL; } - + break; case DSI_THS_PREPARE: /* Enable/Disable custom timing setting */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U); - - if(State) + + if(State != DISABLE) { /* Set custom value */ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP; hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP; } - + break; case DSI_TCLK_ZERO: /* Enable/Disable custom timing setting */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U); - - if(State) + + if(State != DISABLE) { /* Set custom value */ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO; hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO; } - + break; case DSI_TCLK_PREPARE: /* Enable/Disable custom timing setting */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U); - - if(State) + + if(State != DISABLE) { /* Set custom value */ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP; hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP; } - + break; default: break; } - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Force the Clock/Data Lane in TX Stop Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Lane: select between clock or data lanes. + * @param Lane select between clock or data lanes. * This parameter can be any value of @ref DSI_Lane_Group - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check function parameters */ assert_param(IS_DSI_LANE_GROUP(Lane)); assert_param(IS_FUNCTIONAL_STATE(State)); - + if(Lane == DSI_CLOCK_LANE) { /* Force/Unforce the Clock Lane in TX Stop Mode */ @@ -2112,110 +2199,117 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U); } - + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** - * @brief Forces LP Receiver in Low-Power Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @brief Force LP Receiver in Low-Power Mode + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check function parameters */ assert_param(IS_FUNCTIONAL_STATE(State)); - + /* Force/Unforce LP Receiver in Low-Power Mode */ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM; hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Force Data Lanes in RX Mode after a BTA - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check function parameters */ assert_param(IS_FUNCTIONAL_STATE(State)); - + /* Force Data Lanes in RX Mode */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Enable a pull-down on the lanes to prevent from floating states when unused - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check function parameters */ assert_param(IS_FUNCTIONAL_STATE(State)); - + /* Enable/Disable pull-down on lanes */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } /** * @brief Switch off the contention detection on data lanes - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) { /* Process locked */ __HAL_LOCK(hdsi); - + /* Check function parameters */ assert_param(IS_FUNCTIONAL_STATE(State)); - + /* Contention Detection on Data Lanes OFF */ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL; hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U); - + /* Process unlocked */ __HAL_UNLOCK(hdsi); - + return HAL_OK; } @@ -2224,24 +2318,24 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun */ /** @defgroup DSI_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Check the DSI state. - (+) Get error code. + (+) Get error code. @endverbatim * @{ - */ + */ /** * @brief Return the DSI state - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL state */ @@ -2250,6 +2344,18 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) return hdsi->State; } +/** + * @brief Return the DSI error code + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval DSI Error Code + */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +{ + /* Get the error code */ + return hdsi->ErrorCode; +} + /** * @} */ @@ -2257,12 +2363,15 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) /** * @} */ -#endif /* STM32F469xx || STM32F479xx */ -#endif /* HAL_DSI_MODULE_ENABLED */ + /** * @} */ +#endif /* DSI */ + +#endif /* HAL_DSI_MODULE_ENABLED */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.h index f838c48292..9b6b78ded2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dsi.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DSI HAL module. ****************************************************************************** * @attention @@ -43,7 +41,7 @@ extern "C" { #endif -#if defined(STM32F469xx) || defined(STM32F479xx) +#if defined(DSI) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -54,10 +52,10 @@ /** @defgroup DSI DSI * @brief DSI HAL module driver * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ -/** +/** * @brief DSI Init Structure definition */ typedef struct @@ -73,8 +71,8 @@ typedef struct }DSI_InitTypeDef; -/** - * @brief DSI PLL Clock structure definition +/** + * @brief DSI PLL Clock structure definition */ typedef struct { @@ -89,95 +87,95 @@ typedef struct }DSI_PLLInitTypeDef; -/** +/** * @brief DSI Video mode configuration */ -typedef struct +typedef struct { uint32_t VirtualChannelID; /*!< Virtual channel ID */ - + uint32_t ColorCoding; /*!< Color coding for LTDC interface This parameter can be any value of @ref DSI_Color_Coding */ - + uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using 18-bit configuration). This parameter can be any value of @ref DSI_LooselyPacked */ - + uint32_t Mode; /*!< Video mode type This parameter can be any value of @ref DSI_Video_Mode_Type */ - + uint32_t PacketSize; /*!< Video packet size */ - + uint32_t NumberOfChunks; /*!< Number of chunks */ - + uint32_t NullPacketSize; /*!< Null packet size */ - + uint32_t HSPolarity; /*!< HSYNC pin polarity This parameter can be any value of @ref DSI_HSYNC_Polarity */ - + uint32_t VSPolarity; /*!< VSYNC pin polarity This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ - + uint32_t DEPolarity; /*!< Data Enable pin polarity This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ - + uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ - + uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ - + uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ - + uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ - + uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ - + uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ - + uint32_t VerticalActive; /*!< Vertical active duration */ - + uint32_t LPCommandEnable; /*!< Low-power command enable This parameter can be any value of @ref DSI_LP_Command */ - + uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that can fit in a line during VSA, VBP and VFP regions */ - + uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that can fit in a line during VACT region */ - + uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable This parameter can be any value of @ref DSI_LP_HFP */ - + uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable This parameter can be any value of @ref DSI_LP_HBP */ - + uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable This parameter can be any value of @ref DSI_LP_VACT */ - + uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable This parameter can be any value of @ref DSI_LP_VFP */ - + uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable This parameter can be any value of @ref DSI_LP_VBP */ - + uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable This parameter can be any value of @ref DSI_LP_VSYNC */ - + uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable This parameter can be any value of @ref DSI_FBTA_acknowledge */ - + }DSI_VidCfgTypeDef; -/** +/** * @brief DSI Adapted command mode configuration */ -typedef struct +typedef struct { uint32_t VirtualChannelID; /*!< Virtual channel ID */ uint32_t ColorCoding; /*!< Color coding for LTDC interface This parameter can be any value of @ref DSI_Color_Coding */ - uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in + uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in pixels. This parameter can be any value between 0x00 and 0xFFFFU */ uint32_t TearingEffectSource; /*!< Tearing effect source @@ -206,10 +204,10 @@ typedef struct }DSI_CmdCfgTypeDef; -/** +/** * @brief DSI command transmission mode configuration */ -typedef struct +typedef struct { uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ @@ -252,10 +250,10 @@ typedef struct }DSI_LPCmdTypeDef; -/** +/** * @brief DSI PHY Timings definition */ -typedef struct +typedef struct { uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed to low-power transmission */ @@ -276,10 +274,10 @@ typedef struct }DSI_PHY_TimerTypeDef; -/** +/** * @brief DSI HOST Timeouts definition */ -typedef struct +typedef struct { uint32_t TimeoutCkdiv; /*!< Time-out clock division */ @@ -305,7 +303,7 @@ typedef struct /** * @brief DSI States Structure definition */ -typedef enum +typedef enum { HAL_DSI_STATE_RESET = 0x00U, HAL_DSI_STATE_READY = 0x01U, @@ -863,7 +861,7 @@ typedef struct /** @defgroup DSI_Lane_Select DSI Lane Select * @{ */ -#define DSI_CLOCK_LANE 0x00000000U +#define DSI_CLK_LANE 0x00000000U #define DSI_DATA_LANE0 0x00000001U #define DSI_DATA_LANE1 0x00000002U /** @@ -889,67 +887,115 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** * @brief Enables the DSI host. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ -#define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN) +#define __HAL_DSI_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ + }while(0U) /** * @brief Disables the DSI host. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ -#define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN) +#define __HAL_DSI_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ + }while(0U) /** * @brief Enables the DSI wrapper. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ -#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN) +#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ + }while(0U) /** * @brief Disable the DSI wrapper. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ -#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN) +#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper disabling*/ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ + }while(0U) /** * @brief Enables the DSI PLL. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ -#define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN) +#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ + }while(0U) /** * @brief Disables the DSI PLL. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ -#define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN) +#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ + }while(0U) /** * @brief Enables the DSI regulator. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ -#define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN) +#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ + }while(0U) /** * @brief Disables the DSI regulator. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ -#define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN) +#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ + }while(0U) /** * @brief Get the DSI pending flags. - * @param __HANDLE__: DSI handle. - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: - * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag - * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag * @arg DSI_FLAG_BUSY : Busy Flag * @arg DSI_FLAG_PLLLS: PLL Lock Status * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag @@ -962,11 +1008,11 @@ typedef struct /** * @brief Clears the DSI pending flags. - * @param __HANDLE__: DSI handle. - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: - * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag - * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag @@ -976,8 +1022,8 @@ typedef struct /** * @brief Enables the specified DSI interrupts. - * @param __HANDLE__: DSI handle. - * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. + * @param __HANDLE__ DSI handle. + * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -990,8 +1036,8 @@ typedef struct /** * @brief Disables the specified DSI interrupts. - * @param __HANDLE__: DSI handle - * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -1003,9 +1049,9 @@ typedef struct #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) /** - * @brief Checks whether the specified DSI interrupt has occurred or not. - * @param __HANDLE__: DSI handle - * @param __INTERRUPT__: specifies the DSI interrupt source to check. + * @brief Checks whether the specified DSI interrupt source is enabled or not. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt source to check. * This parameter can be one of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -1093,7 +1139,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} - */ + */ /* Private defines -----------------------------------------------------------*/ /** @defgroup DSI_Private_Defines DSI Private Defines @@ -1102,8 +1148,8 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} - */ - + */ + /* Private variables ---------------------------------------------------------*/ /** @defgroup DSI_Private_Variables DSI Private Variables * @{ @@ -1111,16 +1157,16 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup DSI_Private_Constants DSI Private Constants * @{ */ -#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037U) /*!< Maximum return packet configuration */ +#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DSI_Private_Macros DSI Private Macros @@ -1204,7 +1250,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} - */ + */ /* Private functions prototypes ----------------------------------------------*/ /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes @@ -1231,8 +1277,8 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} */ -#endif /* STM32F469xx || STM32F479xx */ - +#endif /* DSI */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c index 9ee45bf123..5d0daf25f7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_eth.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: @@ -173,7 +171,7 @@ static void ETH_Delay(uint32_t mdelay); /** * @brief Initializes the Ethernet MAC and DMA according to default * parameters. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -445,7 +443,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /** * @brief De-Initializes the ETH peripheral. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -469,11 +467,11 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) /** * @brief Initializes the DMA Tx descriptors in chain mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param DMATxDescTab: Pointer to the first Tx desc list - * @param TxBuff: Pointer to the first TxBuffer list - * @param TxBuffCount: Number of the used Tx desc in the list + * @param DMATxDescTab Pointer to the first Tx desc list + * @param TxBuff Pointer to the first TxBuffer list + * @param TxBuffCount Number of the used Tx desc in the list * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) @@ -536,11 +534,11 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @brief Initializes the DMA Rx descriptors in chain mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param DMARxDescTab: Pointer to the first Rx desc list - * @param RxBuff: Pointer to the first RxBuffer list - * @param RxBuffCount: Number of the used Rx desc in the list + * @param DMARxDescTab Pointer to the first Rx desc list + * @param RxBuff Pointer to the first RxBuffer list + * @param RxBuffCount Number of the used Rx desc in the list * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) @@ -606,7 +604,7 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @brief Initializes the ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -621,7 +619,7 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) /** * @brief DeInitializes ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -663,9 +661,9 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) /** * @brief Sends an Ethernet frame. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param FrameLength: Amount of data to be sent + * @param FrameLength Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) @@ -777,7 +775,7 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL /** * @brief Checks for received frames. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -857,7 +855,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) /** * @brief Gets the Received frame in interrupt mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -942,7 +940,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) /** * @brief This function handles ETH interrupt request. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -1002,7 +1000,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) /** * @brief Tx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1017,7 +1015,7 @@ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) /** * @brief Rx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1032,7 +1030,7 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) /** * @brief Ethernet transfer error callbacks - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1047,14 +1045,14 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) /** * @brief Reads a PHY register - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. * This parameter can be one of the following values: * PHY_BCR: Transceiver Basic Control Register, * PHY_BSR: Transceiver Basic Status Register. * More PHY register could be read depending on the used PHY - * @param RegValue: PHY register value + * @param RegValue PHY register value * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) @@ -1120,13 +1118,13 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR /** * @brief Writes to a PHY register. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. * This parameter can be one of the following values: * PHY_BCR: Transceiver Control Register. * More PHY register could be written depending on the used PHY - * @param RegValue: the value to write + * @param RegValue the value to write * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) @@ -1217,7 +1215,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY /** * @brief Enables Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -1256,7 +1254,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) /** * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -1295,9 +1293,9 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) /** * @brief Set ETH MAC Configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param macconf: MAC Configuration structure + * @param macconf MAC Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) @@ -1462,9 +1460,9 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef /** * @brief Sets ETH DMA Configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param dmaconf: DMA Configuration structure + * @param dmaconf DMA Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) @@ -1570,7 +1568,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /** * @brief Return the ETH HAL state - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL state */ @@ -1594,9 +1592,9 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) /** * @brief Configures Ethernet MAC and DMA with default parameters. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param err: Ethernet Init error + * @param err Ethernet Init error * @retval HAL status */ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) @@ -1851,15 +1849,15 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /** * @brief Configures the selected MAC address. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param MacAddr: The MAC address to configure + * @param MacAddr The MAC address to configure * This parameter can be one of the following values: * @arg ETH_MAC_Address0: MAC Address0 * @arg ETH_MAC_Address1: MAC Address1 * @arg ETH_MAC_Address2: MAC Address2 * @arg ETH_MAC_Address3: MAC Address3 - * @param Addr: Pointer to MAC address buffer data (6 bytes) + * @param Addr Pointer to MAC address buffer data (6 bytes) * @retval HAL status */ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) @@ -1885,7 +1883,7 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint /** * @brief Enables the MAC transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1905,7 +1903,7 @@ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1925,7 +1923,7 @@ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the MAC reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1945,7 +1943,7 @@ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1965,7 +1963,7 @@ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1977,7 +1975,7 @@ static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the DMA transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1989,7 +1987,7 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -2001,7 +1999,7 @@ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the DMA reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -2013,7 +2011,7 @@ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) /** * @brief Clears the ETHERNET transmit FIFO. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -2033,7 +2031,7 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) /** * @brief This function provides delay (in milliseconds) based on CPU cycles method. - * @param mdelay: specifies the delay time length, in milliseconds. + * @param mdelay specifies the delay time length, in milliseconds. * @retval None */ static void ETH_Delay(uint32_t mdelay) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h index cea3199a18..d0cca21758 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_eth.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of ETH HAL module. ****************************************************************************** * @attention @@ -1589,80 +1587,80 @@ typedef struct */ /** @brief Reset ETH handle state - * @param __HANDLE__: specifies the ETH handle. + * @param __HANDLE__ specifies the ETH handle. * @retval None */ #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) /** * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag of TDES0 to check. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag of TDES0 to check. * @retval the ETH_DMATxDescFlag (SET or RESET). */ #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) /** * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag of RDES0 to check. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag of RDES0 to check. * @retval the ETH_DMATxDescFlag (SET or RESET). */ #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) /** * @brief Enables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) /** * @brief Disables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) /** * @brief Set the specified DMA Rx Desc Own bit. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) /** * @brief Returns the specified ETHERNET DMA Tx Desc collision count. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval The Transmit descriptor collision counter value. */ #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) /** * @brief Set the specified DMA Tx Desc Own bit. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) /** * @brief Enables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) /** * @brief Disables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) /** * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. - * @param __HANDLE__: ETH Handle - * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion. + * @param __HANDLE__ ETH Handle + * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. * This parameter can be one of the following values: * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum @@ -1674,36 +1672,36 @@ typedef struct /** * @brief Enables the DMA Tx Desc CRC. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) /** * @brief Disables the DMA Tx Desc CRC. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) /** * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) /** * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) /** * @brief Enables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be * enabled or disabled. * This parameter can be any combination of the following values: * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt @@ -1714,8 +1712,8 @@ typedef struct /** * @brief Disables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be * enabled or disabled. * This parameter can be any combination of the following values: * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt @@ -1726,36 +1724,36 @@ typedef struct /** * @brief Initiate a Pause Control Frame (Full-duplex only). - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) /** * @brief Checks whether the ETHERNET flow control busy bit is set or not. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval The new state of flow control busy status bit (SET or RESET). */ #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) /** * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) /** * @brief Disables the MAC BackPressure operation activation (Half-duplex only). - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) /** * @brief Checks whether the specified ETHERNET MAC flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag @@ -1768,8 +1766,8 @@ typedef struct /** * @brief Enables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be * enabled @ref ETH_DMA_Interrupts * @retval None */ @@ -1777,8 +1775,8 @@ typedef struct /** * @brief Disables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be * disabled. @ref ETH_DMA_Interrupts * @retval None */ @@ -1786,32 +1784,32 @@ typedef struct /** * @brief Clears the ETHERNET DMA IT pending bit. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts * @retval None */ #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) /** * @brief Checks whether the specified ETHERNET DMA flag is set or not. -* @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags +* @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags * @retval The new state of ETH_DMA_FLAG (SET or RESET). */ #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) /** * @brief Checks whether the specified ETHERNET DMA flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags * @retval The new state of ETH_DMA_FLAG (SET or RESET). */ #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) /** * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __OVERFLOW__: specifies the DMA overflow flag to check. + * @param __HANDLE__ ETH Handle + * @param __OVERFLOW__ specifies the DMA overflow flag to check. * This parameter can be one of the following values: * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter @@ -1821,8 +1819,8 @@ typedef struct /** * @brief Set the DMA Receive status watchdog timer register value - * @param __HANDLE__: ETH Handle - * @param __VALUE__: DMA Receive status watchdog timer register value + * @param __HANDLE__ ETH Handle + * @param __VALUE__ DMA Receive status watchdog timer register value * @retval None */ #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) @@ -1830,7 +1828,7 @@ typedef struct /** * @brief Enables any unicast packet filtered by the MAC address * recognition to be a wake-up frame. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) @@ -1838,57 +1836,57 @@ typedef struct /** * @brief Disables any unicast packet filtered by the MAC address * recognition to be a wake-up frame. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) /** * @brief Enables the MAC Wake-Up Frame Detection. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) /** * @brief Disables the MAC Wake-Up Frame Detection. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) /** * @brief Enables the MAC Magic Packet Detection. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) /** * @brief Disables the MAC Magic Packet Detection. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) /** * @brief Enables the MAC Power Down. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) /** * @brief Disables the MAC Power Down. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) /** * @brief Checks whether the specified ETHERNET PMT flag is set or not. - * @param __HANDLE__: ETH Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ ETH Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received @@ -1899,14 +1897,14 @@ typedef struct /** * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) /** * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ @@ -1914,57 +1912,57 @@ typedef struct /** * @brief Enables the MMC Counter Freeze. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) /** * @brief Disables the MMC Counter Freeze. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) /** * @brief Enables the MMC Reset On Read. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) /** * @brief Disables the MMC Reset On Read. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) /** * @brief Enables the MMC Counter Stop Rollover. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) /** * @brief Disables the MMC Counter Stop Rollover. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) /** * @brief Resets the MMC Counters. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) /** * @brief Enables the specified ETHERNET MMC Rx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value @@ -1974,8 +1972,8 @@ typedef struct #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) /** * @brief Disables the specified ETHERNET MMC Rx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value @@ -1985,8 +1983,8 @@ typedef struct #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) /** * @brief Enables the specified ETHERNET MMC Tx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value @@ -1997,8 +1995,8 @@ typedef struct /** * @brief Disables the specified ETHERNET MMC Tx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.c index d8cda32c50..a75258476b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -164,10 +162,10 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @brief Program byte, halfword, word or double word at a specified address - * @param TypeProgram: Indicate the way to program at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ @@ -222,10 +220,10 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /** * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. - * @param TypeProgram: Indicate the way to program at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed * * @retval HAL Status */ @@ -392,7 +390,7 @@ void HAL_FLASH_IRQHandler(void) /** * @brief FLASH end of operation interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * Mass Erase: Bank number which has been requested to erase * Sectors Erase: Sector which has been erased * (if 0xFFFFFFFFU, it means that all the selected sectors have been erased) @@ -410,7 +408,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /** * @brief FLASH operation error interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * Mass Erase: Bank number which has been requested to erase * Sectors Erase: Sector number which returned an error * Program: Address which was selected for data program @@ -450,18 +448,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { - if((FLASH->CR & FLASH_CR_LOCK) != RESET) + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } } - else - { - return HAL_ERROR; - } - - return HAL_OK; + + return status; } /** @@ -560,7 +562,7 @@ uint32_t HAL_FLASH_GetError(void) /** * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operationtimeout + * @param Timeout maximum flash operationtimeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) @@ -619,8 +621,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) @@ -647,8 +649,8 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_Word(uint32_t Address, uint32_t Data) @@ -672,8 +674,8 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) @@ -697,8 +699,8 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.h index 38f2db87a1..ed8538d9cf 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention @@ -189,7 +187,7 @@ typedef struct */ /** * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency + * @param __LATENCY__ FLASH Latency * The value of this parameter depend on device used within the same series * @retval none */ @@ -257,7 +255,7 @@ typedef struct }while(0U) /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_ERR: Error Interrupt @@ -267,7 +265,7 @@ typedef struct /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_ERR: Error Interrupt @@ -277,7 +275,7 @@ typedef struct /** * @brief Get the specified FLASH flag status. - * @param __FLAG__: specifies the FLASH flags to check. + * @param __FLAG__ specifies the FLASH flags to check. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP : FLASH End of Operation flag * @arg FLASH_FLAG_OPERR : FLASH operation Error flag @@ -294,7 +292,7 @@ typedef struct /** * @brief Clear the specified FLASH flags. - * @param __FLAG__: specifies the FLASH flags to clear. + * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP : FLASH End of Operation flag * @arg FLASH_FLAG_OPERR : FLASH operation Error flag diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c index 0d4f0f8381..7b5eff6949 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: @@ -168,10 +166,10 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); */ /** * @brief Perform a mass erase or erase the specified FLASH memory sectors - * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * - * @param[out] SectorError: pointer to variable that + * @param[out] SectorError pointer to variable that * contains the configuration information on faulty sector in case of error * (0xFFFFFFFFU means that all the sectors have been correctly erased) * @@ -243,7 +241,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /** * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled - * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @retval HAL Status @@ -296,7 +294,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /** * @brief Program option bytes - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval HAL Status @@ -355,7 +353,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) /** * @brief Get the Option byte configuration - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval None @@ -384,7 +382,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Program option bytes - * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that * contains the configuration information for the programming. * * @retval HAL Status @@ -440,7 +438,7 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO /** * @brief Get the OBEX byte configuration - * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that * contains the configuration information for the programming. * * @retval None @@ -538,7 +536,7 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Full erase of FLASH memory sectors - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -549,7 +547,7 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) * - * @param Banks: Banks to be erased + * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased * @arg FLASH_BANK_2: Bank2 to be erased @@ -586,9 +584,9 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /** * @brief Erase the specified FLASH memory sector - * @param Sector: FLASH sector to erase + * @param Sector FLASH sector to erase * The value of this parameter depend on device used within the same series - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -635,7 +633,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= tmp_psize; CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); - FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); FLASH->CR |= FLASH_CR_STRT; } @@ -647,13 +645,13 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 * @arg OB_WRP_SECTOR_All * @note BANK2 starts from OB_WRP_SECTOR_12 * - * @param Banks: Enable write protection on all the sectors for the specific bank + * @param Banks Enable write protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * @arg FLASH_BANK_2: WRP on all sectors of bank2 @@ -718,13 +716,13 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 * @arg OB_WRP_Sector_All * @note BANK2 starts from OB_WRP_SECTOR_12 * - * @param Banks: Disable write protection on all the sectors for the specific bank + * @param Banks Disable write protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased * @arg FLASH_BANK_2: Bank2 to be erased @@ -951,7 +949,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t Se defined(STM32F423xx) /** * @brief Mass erase of FLASH memory - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -962,7 +960,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t Se * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) * - * @param Banks: Banks to be erased + * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased * @@ -982,9 +980,9 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /** * @brief Erase the specified FLASH memory sector - * @param Sector: FLASH sector to erase + * @param Sector FLASH sector to erase * The value of this parameter depend on device used within the same series - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -1026,7 +1024,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= tmp_psize; CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); - FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); FLASH->CR |= FLASH_CR_STRT; } @@ -1038,10 +1036,10 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * The value of this parameter depend on device used within the same series * - * @param Banks: Enable write protection on all the sectors for the specific bank + * @param Banks Enable write protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * @@ -1074,10 +1072,10 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * The value of this parameter depend on device used within the same series * - * @param Banks: Enable write protection on all the sectors for the specific bank + * @param Banks Enable write protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * @@ -1167,7 +1165,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) /** * @brief Set the read protection level. - * @param Level: specifies the read protection level. + * @param Level specifies the read protection level. * This parameter can be one of the following values: * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Read protection of the memory @@ -1197,15 +1195,15 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) /** * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Iwdg: Selects the IWDG mode + * @param Iwdg Selects the IWDG mode * This parameter can be one of the following values: * @arg OB_IWDG_SW: Software IWDG selected * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop: Reset event when entering STOP mode. + * @param Stop Reset event when entering STOP mode. * This parameter can be one of the following values: * @arg OB_STOP_NO_RST: No reset generated when entering in STOP * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby: Reset event when entering Standby mode. + * @param Stdby Reset event when entering Standby mode. * This parameter can be one of the following values: * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY @@ -1238,7 +1236,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t /** * @brief Set the BOR Level. - * @param Level: specifies the Option Bytes BOR Reset Level. + * @param Level specifies the Option Bytes BOR Reset Level. * This parameter can be one of the following values: * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.h index 27df2c7ed6..d498b90c64 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.c index 0955b8009c..fab411547c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ramfunc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief FLASH RAMFUNC module driver. * This file provides a FLASH firmware functions which should be * executed from internal SRAM diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.h index 529a6d63f5..500d33adce 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ramfunc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.c index 027e1e3179..6e7a5c85ce 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_fmpi2c.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief FMPI2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (FMPI2C) peripheral: @@ -30,13 +28,13 @@ (+++) Configure the FMPI2Cx interrupt priority (+++) Enable the NVIC FMPI2C IRQ Channel (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx channel + (+++) Configure the DMA Tx or Rx stream (+++) Associate the initialized DMA handle to the hfmpi2c DMA Tx or Rx handle (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx channel + the DMA Tx or Rx stream (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure. @@ -81,20 +79,20 @@ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() - (+) End of abort process, HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback() + (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO sequential operation *** - =================================== + ============================================== [..] (@) These interfaces allow to manage a sequential transfer with a repeated start condition when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through FMPI2C_XFEROPTIONS and are listed below: + (+) Option field values are defined through @ref FMPI2C_XFEROPTIONS and are listed below: (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode (++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition @@ -107,6 +105,12 @@ (++) FMPI2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and with a final stop condition in both cases + (++) FMPI2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option FMPI2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_FMPI2C_Master_Sequential_Transmit_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME) + or HAL_FMPI2C_Master_Sequential_Receive_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME). + Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. (+) Differents sequential FMPI2C interfaces are listed below: (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Sequential_Transmit_IT() @@ -118,8 +122,6 @@ (++) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() (+++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() - (+++) mean HAL_FMPI2C_MasterTxCpltCallback() in case of previous state was master transmit - (+++) mean HAL_FMPI2C_MasterRxCpltCallback() in case of previous state was master receive (++) Enable/disable the Address listen mode in slave FMPI2C mode using HAL_FMPI2C_EnableListen_IT() HAL_FMPI2C_DisableListen_IT() (+++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). @@ -175,8 +177,8 @@ (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() - (+) End of abort process, HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback() + (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -240,7 +242,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -265,24 +267,24 @@ /** @defgroup FMPI2C_Private_Define FMPI2C Private Define * @{ */ -#define TIMING_CLEAR_MASK 0xF0FFFFFFU /*!< FMPI2C TIMING clear register Mask */ -#define FMPI2C_TIMEOUT_ADDR 10000U /*!< 10 s */ -#define FMPI2C_TIMEOUT_BUSY 25U /*!< 25 ms */ -#define FMPI2C_TIMEOUT_DIR 25U /*!< 25 ms */ -#define FMPI2C_TIMEOUT_RXNE 25U /*!< 25 ms */ -#define FMPI2C_TIMEOUT_STOPF 25U /*!< 25 ms */ -#define FMPI2C_TIMEOUT_TC 25U /*!< 25 ms */ -#define FMPI2C_TIMEOUT_TCR 25U /*!< 25 ms */ -#define FMPI2C_TIMEOUT_TXIS 25U /*!< 25 ms */ -#define FMPI2C_TIMEOUT_FLAG 25U /*!< 25 ms */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< FMPI2C TIMING clear register Mask */ +#define FMPI2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define FMPI2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define FMPI2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define FMPI2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define FMPI2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define FMPI2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define FMPI2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define FMPI2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define FMPI2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ -#define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U +#define MAX_NBYTE_SIZE 255U +#define SlaveAddr_SHIFT 7U +#define SlaveAddr_MSK 0x06U /* Private define for @ref PreviousState usage */ #define FMPI2C_STATE_MSK ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX | HAL_FMPI2C_STATE_BUSY_RX) & (~((uint32_t)HAL_FMPI2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) /*!< Default Value */ +#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) /*!< Default Value */ #define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ #define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ @@ -292,24 +294,24 @@ /* Private define to centralize the enable/disable of Interrupts */ -#define FMPI2C_XFER_TX_IT 0x00000001U -#define FMPI2C_XFER_RX_IT 0x00000002U -#define FMPI2C_XFER_LISTEN_IT 0x00000004U +#define FMPI2C_XFER_TX_IT (0x00000001U) +#define FMPI2C_XFER_RX_IT (0x00000002U) +#define FMPI2C_XFER_LISTEN_IT (0x00000004U) -#define FMPI2C_XFER_ERROR_IT 0x00000011U -#define FMPI2C_XFER_CPLT_IT 0x00000012U -#define FMPI2C_XFER_RELOAD_IT 0x00000012U +#define FMPI2C_XFER_ERROR_IT (0x00000011U) +#define FMPI2C_XFER_CPLT_IT (0x00000012U) +#define FMPI2C_XFER_RELOAD_IT (0x00000012U) /* Private define Sequential Transfer Options default/reset value */ -#define FMPI2C_NO_OPTION_FRAME 0xFFFF0000U +#define FMPI2C_NO_OPTION_FRAME (0xFFFF0000U) /** * @} */ /* Private macro -------------------------------------------------------------*/ #define FMPI2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_FMPI2C_STATE_BUSY_TX) ? \ - ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \ - ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR))) + ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) : \ + ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR))) /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -326,17 +328,17 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma); static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma); /* Private functions to handle IT transfer */ -static void FMPI2C_ITAddrCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); -static void FMPI2C_ITMasterSequentialCplt (FMPI2C_HandleTypeDef *hfmpi2c); -static void FMPI2C_ITSlaveSequentialCplt (FMPI2C_HandleTypeDef *hfmpi2c); -static void FMPI2C_ITMasterCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); -static void FMPI2C_ITSlaveCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); -static void FMPI2C_ITListenCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); -static void FMPI2C_ITError (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); +static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); +static void FMPI2C_ITMasterSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c); +static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c); +static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); +static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); +static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags); +static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_RequestMemoryRead (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); /* Private functions for FMPI2C transfer IRQ handler */ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); @@ -345,21 +347,21 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); /* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ -static HAL_StatusTypeDef FMPI2C_Enable_IRQ (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); -static HAL_StatusTypeDef FMPI2C_Disable_IRQ (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); +static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); +static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); /* Private functions to flush TXDR register */ -static void FMPI2C_Flush_TXDR (FMPI2C_HandleTypeDef *hfmpi2c); +static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c); /* Private functions to handle start, restart or stop a transfer */ -static void FMPI2C_TransferConfig (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} */ @@ -371,7 +373,7 @@ static void FMPI2C_TransferConfig (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevA */ /** @defgroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== @@ -411,7 +413,7 @@ static void FMPI2C_TransferConfig (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevA HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) { /* Check the FMPI2C handle allocation */ - if(hfmpi2c == NULL) + if (hfmpi2c == NULL) { return HAL_ERROR; } @@ -426,7 +428,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) assert_param(IS_FMPI2C_GENERAL_CALL(hfmpi2c->Init.GeneralCallMode)); assert_param(IS_FMPI2C_NO_STRETCH(hfmpi2c->Init.NoStretchMode)); - if(hfmpi2c->State == HAL_FMPI2C_STATE_RESET) + if (hfmpi2c->State == HAL_FMPI2C_STATE_RESET) { /* Allocate lock resource and initialize it */ hfmpi2c->Lock = HAL_UNLOCKED; @@ -449,21 +451,18 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) hfmpi2c->Instance->OAR1 &= ~FMPI2C_OAR1_OA1EN; /* Configure FMPI2Cx: Own Address1 and ack own address1 mode */ - if(hfmpi2c->Init.OwnAddress1 != 0U) + if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_7BIT) { - if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_7BIT) - { - hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | hfmpi2c->Init.OwnAddress1); - } - else /* FMPI2C_ADDRESSINGMODE_10BIT */ - { - hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | FMPI2C_OAR1_OA1MODE | hfmpi2c->Init.OwnAddress1); - } + hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | hfmpi2c->Init.OwnAddress1); + } + else /* FMPI2C_ADDRESSINGMODE_10BIT */ + { + hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | FMPI2C_OAR1_OA1MODE | hfmpi2c->Init.OwnAddress1); } /*---------------------------- FMPI2Cx CR2 Configuration ----------------------*/ /* Configure FMPI2Cx: Addressing Master mode */ - if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT) + if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT) { hfmpi2c->Instance->CR2 = (FMPI2C_CR2_ADD10); } @@ -501,7 +500,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c) { /* Check the FMPI2C handle allocation */ - if(hfmpi2c == NULL) + if (hfmpi2c == NULL) { return HAL_ERROR; } @@ -565,7 +564,7 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c) */ /** @defgroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions + * @brief Data transfers functions * @verbatim =============================================================================== @@ -577,7 +576,7 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c) (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function + The status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. @@ -622,7 +621,6 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c) (++) HAL_FMPI2C_SlaveTxCpltCallback() (++) HAL_FMPI2C_SlaveRxCpltCallback() (++) HAL_FMPI2C_ErrorCallback() - (++) HAL_FMPI2C_AbortCpltCallback() @endverbatim * @{ @@ -632,8 +630,8 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c) * @brief Transmits in master mode an amount of data in blocking mode. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -643,7 +641,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint { uint32_t tickstart = 0U; - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hfmpi2c); @@ -651,7 +649,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -659,7 +657,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; - + /* Prepare transfer parameters */ hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; @@ -667,7 +665,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint /* Send Slave Address */ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); @@ -678,12 +676,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE); } - while(hfmpi2c->XferSize > 0U) + while (hfmpi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -697,15 +695,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint hfmpi2c->XferCount--; hfmpi2c->XferSize--; - if((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount!=0U)) + if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); @@ -720,9 +718,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -756,8 +754,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint * @brief Receives in master mode an amount of data in blocking mode. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -767,15 +765,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 { uint32_t tickstart = 0U; - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) - { + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) + { /* Process Locked */ __HAL_LOCK(hfmpi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -791,7 +789,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 /* Send Slave Address */ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ); @@ -802,12 +800,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ); } - while(hfmpi2c->XferSize > 0U) + while (hfmpi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -822,15 +820,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 hfmpi2c->XferSize--; hfmpi2c->XferCount--; - if((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U)) + if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); @@ -845,9 +843,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -856,7 +854,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 return HAL_TIMEOUT; } } - + /* Clear STOP Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); @@ -878,7 +876,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 } /** - * @brief Transmits in slave mode an amount of data in blocking mode. + * @brief Transmits in slave mode an amount of data in blocking mode. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param pData Pointer to data buffer @@ -890,15 +888,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 { uint32_t tickstart = 0U; - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hfmpi2c); - + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -915,7 +913,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; @@ -923,13 +921,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 } /* Clear ADDR flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR); + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); /* If 10bit addressing mode is selected */ - if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT) + if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; @@ -937,26 +935,26 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 } /* Clear ADDR flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR); + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); } /* Wait until DIR flag is set Transmitter mode */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; return HAL_TIMEOUT; } - while(hfmpi2c->XferCount > 0U) + while (hfmpi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -972,16 +970,16 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 } /* Wait until STOP flag is set */ - if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; } else { @@ -990,10 +988,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 } /* Clear STOP flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF); + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + /* Wait until BUSY flag is reset */ + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; @@ -1030,9 +1028,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ { uint32_t tickstart = 0U; - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1055,7 +1053,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; @@ -1063,33 +1061,33 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ } /* Clear ADDR flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR); + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); /* Wait until DIR flag is reset Receiver mode */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; return HAL_TIMEOUT; } - while(hfmpi2c->XferCount > 0U) + while (hfmpi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; /* Store Last receive data if any */ - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR; hfmpi2c->XferCount--; } - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_TIMEOUT) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_TIMEOUT) { return HAL_TIMEOUT; } @@ -1105,12 +1103,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ } /* Wait until STOP flag is set */ - if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -1121,10 +1119,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ } /* Clear STOP flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF); + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; @@ -1152,8 +1150,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1162,9 +1160,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u { uint32_t xfermode = 0U; - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1181,8 +1179,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; - - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -1198,7 +1196,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + __HAL_UNLOCK(hfmpi2c); /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current @@ -1221,8 +1219,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1231,9 +1229,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui { uint32_t xfermode = 0U; - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1250,8 +1248,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; - - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -1265,7 +1263,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui /* Send Slave Address */ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); - + /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -1296,7 +1294,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size) { - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hfmpi2c); @@ -1336,7 +1334,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui } /** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param pData Pointer to data buffer @@ -1345,7 +1343,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size) { - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hfmpi2c); @@ -1388,8 +1386,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin * @brief Transmit in master mode an amount of data in non-blocking mode with DMA * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1398,9 +1396,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, { uint32_t xfermode = 0U; - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1417,8 +1415,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA; - - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -1429,37 +1427,60 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, xfermode = FMPI2C_AUTOEND_MODE; } - /* Set the FMPI2C DMA transfer complete callback */ - hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt; + if (hfmpi2c->XferSize > 0U) + { + /* Set the FMPI2C DMA transfer complete callback */ + hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt; - /* Set the DMA error callback */ - hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError; + /* Set the DMA error callback */ + hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError; - /* Set the unused DMA callbacks to NULL */ - hfmpi2c->hdmatx->XferHalfCpltCallback = NULL; - hfmpi2c->hdmatx->XferAbortCallback = NULL; + /* Set the unused DMA callbacks to NULL */ + hfmpi2c->hdmatx->XferHalfCpltCallback = NULL; + hfmpi2c->hdmatx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + /* Enable the DMA stream */ + HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); - /* Send Slave Address */ - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE); + /* Send Slave Address */ + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE); - /* Update XferCount value */ - hfmpi2c->XferCount -= hfmpi2c->XferSize; + /* Update XferCount value */ + hfmpi2c->XferCount -= hfmpi2c->XferSize; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - /* Note : The FMPI2C interrupts must be enabled after unlocking current process - to avoid the risk of FMPI2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); + /* Note : The FMPI2C interrupts must be enabled after unlocking current process + to avoid the risk of FMPI2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + /* Enable DMA Request */ + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + } + else + { + /* Update Transfer ISR function pointer */ + hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + /* Note : The FMPI2C interrupts must be enabled after unlocking current process + to avoid the risk of FMPI2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + } return HAL_OK; } @@ -1473,8 +1494,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, * @brief Receive in master mode an amount of data in non-blocking mode with DMA * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1483,9 +1504,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u { uint32_t xfermode = 0U; - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1502,8 +1523,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA; - - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -1514,7 +1535,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u xfermode = FMPI2C_AUTOEND_MODE; } - if(hfmpi2c->XferSize > 0U) + if (hfmpi2c->XferSize > 0U) { /* Set the FMPI2C DMA transfer complete callback */ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt; @@ -1526,12 +1547,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u hfmpi2c->hdmarx->XferHalfCpltCallback = NULL; hfmpi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); /* Send Slave Address */ - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); + /* Set NBYTES to read and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); /* Update XferCount value */ hfmpi2c->XferCount -= hfmpi2c->XferSize; @@ -1550,11 +1571,23 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u } else { - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + /* Update Transfer ISR function pointer */ + hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); + + /* Note : The FMPI2C interrupts must be enabled after unlocking current process + to avoid the risk of FMPI2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } return HAL_OK; } @@ -1574,12 +1607,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size) { - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hfmpi2c); @@ -1604,7 +1637,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u hfmpi2c->hdmatx->XferHalfCpltCallback = NULL; hfmpi2c->hdmatx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); /* Enable Address Acknowledge */ @@ -1620,7 +1653,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; return HAL_OK; } @@ -1640,12 +1673,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size) { - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hfmpi2c); @@ -1670,7 +1703,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui hfmpi2c->hdmarx->XferHalfCpltCallback = NULL; hfmpi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); /* Enable Address Acknowledge */ @@ -1699,7 +1732,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui * @brief Write an amount of data in blocking mode to a specific memory address * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1714,9 +1748,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1727,7 +1761,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1742,9 +1776,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D hfmpi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -1759,7 +1793,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D } /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */ - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); @@ -1773,9 +1807,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D do { /* Wait until TXIS flag is set */ - if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -1790,15 +1824,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D hfmpi2c->XferCount--; hfmpi2c->XferSize--; - if((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount!=0U)) + if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); @@ -1810,13 +1844,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D } } - }while(hfmpi2c->XferCount > 0U); + } + while (hfmpi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -1850,7 +1885,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D * @brief Read an amount of data in blocking mode from a specific memory address * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1865,9 +1901,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1878,7 +1914,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1893,9 +1929,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De hfmpi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -1911,7 +1947,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De /* Send Slave Address */ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ); @@ -1925,7 +1961,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De do { /* Wait until RXNE flag is set */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1935,15 +1971,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De hfmpi2c->XferSize--; hfmpi2c->XferCount--; - if((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U)) + if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); @@ -1954,13 +1990,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); } } - }while(hfmpi2c->XferCount > 0U); + } + while (hfmpi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -1993,7 +2030,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2008,14 +2046,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) + + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2035,8 +2073,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; - - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -2048,9 +2086,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ } /* Send Slave Address and Memory Address */ - if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2065,12 +2103,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ } /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP); /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + __HAL_UNLOCK(hfmpi2c); - /* Note : The FMPI2C interrupts must be enabled after unlocking current process + /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ @@ -2091,7 +2129,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2106,14 +2145,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) + + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2133,8 +2172,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; - - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -2146,9 +2185,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t } /* Send Slave Address and Memory Address */ - if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2163,7 +2202,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t } /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2182,13 +2221,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t else { return HAL_BUSY; - } + } } /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2203,14 +2243,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2230,8 +2270,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA; - - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -2243,9 +2283,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 } /* Send Slave Address and Memory Address */ - if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2269,7 +2309,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 hfmpi2c->hdmatx->XferHalfCpltCallback = NULL; hfmpi2c->hdmatx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); /* Send Slave Address */ @@ -2303,7 +2343,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2317,15 +2358,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); - - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2345,8 +2386,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA; - - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -2358,9 +2399,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ } /* Send Slave Address and Memory Address */ - if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2384,11 +2425,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ hfmpi2c->hdmarx->XferHalfCpltCallback = NULL; hfmpi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); /* Update XferCount value */ hfmpi2c->XferCount -= hfmpi2c->XferSize; @@ -2418,20 +2459,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ * @note This function is used with Memory devices * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ +{ uint32_t tickstart = 0U; __IO uint32_t FMPI2C_Trials = 0U; - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2445,16 +2487,16 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16 do { /* Generate Start */ - hfmpi2c->Instance->CR2 = FMPI2C_GENERATE_START(hfmpi2c->Init.AddressingMode,DevAddress); - + hfmpi2c->Instance->CR2 = FMPI2C_GENERATE_START(hfmpi2c->Init.AddressingMode, DevAddress); + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) && (hfmpi2c->State != HAL_FMPI2C_STATE_TIMEOUT)) + while ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) && (hfmpi2c->State != HAL_FMPI2C_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hfmpi2c->State = HAL_FMPI2C_STATE_READY; @@ -2462,14 +2504,14 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16 __HAL_UNLOCK(hfmpi2c); return HAL_TIMEOUT; } - } + } } /* Check if the NACKF flag has not been set */ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) { - /* Wait until STOPF flag is reset */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2487,8 +2529,8 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16 } else { - /* Wait until STOPF flag is reset */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2505,9 +2547,9 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16 { /* Generate Stop */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + + /* Wait until STOPF flag is reset */ + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2515,7 +2557,8 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16 /* Clear STOP Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); } - }while(FMPI2C_Trials < Trials); + } + while (FMPI2C_Trials < Trials); hfmpi2c->State = HAL_FMPI2C_STATE_READY; @@ -2535,8 +2578,8 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16 * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS @@ -2550,7 +2593,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hfmpi2c); @@ -2566,7 +2609,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; /* If size > MAX_NBYTE_SIZE, use reload mode */ - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -2576,10 +2619,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef hfmpi2c->XferSize = hfmpi2c->XferCount; xfermode = hfmpi2c->XferOptions; } - + /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if(hfmpi2c->PreviousState == FMPI2C_STATE_SLAVE_BUSY_TX) + if (hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -2588,7 +2631,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + __HAL_UNLOCK(hfmpi2c); /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current @@ -2608,8 +2651,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS @@ -2623,7 +2666,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef * /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hfmpi2c); @@ -2639,7 +2682,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef * hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; /* If hfmpi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -2652,16 +2695,16 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef * /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if(hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) + if (hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) { xferrequest = FMPI2C_NO_STARTSTOP; } /* Send Slave Address and set NBYTES to read */ - FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, xfermode, xferrequest); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + __HAL_UNLOCK(hfmpi2c); /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current @@ -2691,9 +2734,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef * /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN) + if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2706,12 +2749,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef * /* FMPI2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave RX state to TX state */ - if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN) + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN) { /* Disable associated Interrupts */ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); } - + hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX_LISTEN; hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -2726,15 +2769,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef * hfmpi2c->XferOptions = XferOptions; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; - if(FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR); + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); } /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + __HAL_UNLOCK(hfmpi2c); /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current @@ -2765,9 +2808,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *h /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN) + if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2780,12 +2823,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *h /* FMPI2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave TX state to RX state */ - if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) { /* Disable associated Interrupts */ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } - + hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX_LISTEN; hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -2800,11 +2843,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *h hfmpi2c->XferOptions = XferOptions; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; - if(FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) + if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR); + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2832,7 +2875,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *h */ HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c) { - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; @@ -2860,14 +2903,14 @@ HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c) uint32_t tmp; /* Disable Address listen mode only if a transfer is not ongoing */ - if(hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) + if (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) { tmp = (uint32_t)(hfmpi2c->State) & FMPI2C_STATE_MSK; hfmpi2c->PreviousState = tmp | (uint32_t)(hfmpi2c->Mode); hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; hfmpi2c->XferISR = NULL; - + /* Disable the Address Match interrupt */ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); @@ -2883,13 +2926,13 @@ HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c) * @brief Abort a master FMPI2C IT or DMA process communication with Interrupt. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress) { - if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER) + if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER) { /* Process Locked */ __HAL_LOCK(hfmpi2c); @@ -2908,11 +2951,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); - /* Note : The FMPI2C interrupts must be enabled after unlocking current process + /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT); - + return HAL_OK; } else @@ -2929,7 +2972,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint /** @defgroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /** * @brief This function handles FMPI2C event interrupt request. @@ -2944,7 +2987,7 @@ void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) uint32_t itsources = READ_REG(hfmpi2c->Instance->CR1); /* FMPI2C events treatment -------------------------------------*/ - if(hfmpi2c->XferISR != NULL) + if (hfmpi2c->XferISR != NULL) { hfmpi2c->XferISR(hfmpi2c, itflags, itsources); } @@ -2962,7 +3005,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) uint32_t itsources = READ_REG(hfmpi2c->Instance->CR1); /* FMPI2C Bus error interrupt occurred ------------------------------------*/ - if(((itflags & FMPI2C_FLAG_BERR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET)) + if (((itflags & FMPI2C_FLAG_BERR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR; @@ -2971,7 +3014,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) } /* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if(((itflags & FMPI2C_FLAG_OVR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET)) + if (((itflags & FMPI2C_FLAG_OVR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR; @@ -2980,7 +3023,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) } /* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if(((itflags & FMPI2C_FLAG_ARLO) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET)) + if (((itflags & FMPI2C_FLAG_ARLO) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO; @@ -2989,7 +3032,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) } /* Call the Error Callback in case of Error detected */ - if((hfmpi2c->ErrorCode & (HAL_FMPI2C_ERROR_BERR | HAL_FMPI2C_ERROR_OVR | HAL_FMPI2C_ERROR_ARLO)) != HAL_FMPI2C_ERROR_NONE) + if ((hfmpi2c->ErrorCode & (HAL_FMPI2C_ERROR_BERR | HAL_FMPI2C_ERROR_OVR | HAL_FMPI2C_ERROR_ARLO)) != HAL_FMPI2C_ERROR_NONE) { FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode); } @@ -3062,8 +3105,8 @@ __weak void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c) * @brief Slave Address Match callback. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref FMPI2C_XFEROPTIONS - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref FMPI2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_FMPI2C_AddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -3213,7 +3256,7 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c) /** * @} - */ + */ /** * @} @@ -3231,14 +3274,14 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t devaddress = 0; + uint16_t devaddress = 0U; /* Process Locked */ __HAL_LOCK(hfmpi2c); - if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET)) + if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -3251,27 +3294,27 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); } - else if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET)) { /* Read data from RXDR */ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR; hfmpi2c->XferSize--; hfmpi2c->XferCount--; } - else if(((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++); hfmpi2c->XferSize--; - hfmpi2c->XferCount--; + hfmpi2c->XferCount--; } - else if(((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET)) { - if((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U)) + if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U)) { devaddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD); - - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); @@ -3279,7 +3322,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm else { hfmpi2c->XferSize = hfmpi2c->XferCount; - if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) + if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) { FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); } @@ -3292,7 +3335,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm else { /* Call TxCpltCallback() if no stop mode is set */ - if((FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)&&(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)) + if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE) { /* Call FMPI2C Master Sequential complete process */ FMPI2C_ITMasterSequentialCplt(hfmpi2c); @@ -3305,14 +3348,23 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm } } } - else if(((ITFlags & FMPI2C_FLAG_TC) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_TC) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET)) { - if(hfmpi2c->XferCount == 0U) + if (hfmpi2c->XferCount == 0U) { - if((FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)&&(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)) + if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE) { - /* Call FMPI2C Master Sequential complete process */ - FMPI2C_ITMasterSequentialCplt(hfmpi2c); + /* Generate a stop condition in case of no transfer option */ + if (hfmpi2c->XferOptions == FMPI2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; + } + else + { + /* Call FMPI2C Master Sequential complete process */ + FMPI2C_ITMasterSequentialCplt(hfmpi2c); + } } } else @@ -3323,7 +3375,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm } } - if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET)) + if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Master complete process */ FMPI2C_ITMasterCplt(hfmpi2c, ITFlags); @@ -3343,26 +3395,26 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hfmpi2c); - - if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET)) + + if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET)) { /* Check that FMPI2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hfmpi2c->XferCount == 0U) + if (hfmpi2c->XferCount == 0U) { - if(((hfmpi2c->XferOptions == FMPI2C_FIRST_AND_LAST_FRAME) || (hfmpi2c->XferOptions == FMPI2C_LAST_FRAME)) && \ - (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)) + if (((hfmpi2c->XferOptions == FMPI2C_FIRST_AND_LAST_FRAME) || (hfmpi2c->XferOptions == FMPI2C_LAST_FRAME)) && \ + (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)) { /* Call FMPI2C Listen complete process */ FMPI2C_ITListenCplt(hfmpi2c, ITFlags); } - else if((hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) && (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)) + else if ((hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) && (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -3390,9 +3442,9 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; } } - else if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET)) { - if(hfmpi2c->XferCount > 0U) + if (hfmpi2c->XferCount > 0U) { /* Read data from RXDR */ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR; @@ -3400,24 +3452,24 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp hfmpi2c->XferCount--; } - if((hfmpi2c->XferCount == 0U) && \ - (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)) + if ((hfmpi2c->XferCount == 0U) && \ + (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)) { /* Call FMPI2C Slave Sequential complete process */ FMPI2C_ITSlaveSequentialCplt(hfmpi2c); - } + } } - else if(((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET)) { FMPI2C_ITAddrCplt(hfmpi2c, ITFlags); } - else if(((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Datas have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hfmpi2c->XferCount > 0U) + if (hfmpi2c->XferCount > 0U) { /* Write data to TXDR */ hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++); @@ -3426,7 +3478,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp } else { - if((hfmpi2c->XferOptions == FMPI2C_NEXT_FRAME) || (hfmpi2c->XferOptions == FMPI2C_FIRST_FRAME)) + if ((hfmpi2c->XferOptions == FMPI2C_NEXT_FRAME) || (hfmpi2c->XferOptions == FMPI2C_FIRST_FRAME)) { /* Last Byte is Transmitted */ /* Call FMPI2C Slave Sequential complete process */ @@ -3436,7 +3488,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp } /* Check if STOPF is set */ - if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET)) + if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Slave complete process */ FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags); @@ -3456,22 +3508,22 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) { - uint16_t devaddress = 0; + uint16_t devaddress = 0U; uint32_t xfermode = 0U; /* Process Locked */ __HAL_LOCK(hfmpi2c); - if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET)) + if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); /* Set corresponding Error Code */ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; - + /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ @@ -3480,18 +3532,18 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); } - else if(((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_TCI); - - if(hfmpi2c->XferCount != 0U) + + if (hfmpi2c->XferCount != 0U) { /* Recover Slave address */ devaddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD); - + /* Prepare the new XferSize to transfer */ - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; xfermode = FMPI2C_RELOAD_MODE; @@ -3509,7 +3561,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf hfmpi2c->XferCount -= hfmpi2c->XferSize; /* Enable DMA Request */ - if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) { hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; } @@ -3525,7 +3577,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE); } } - else if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Master complete process */ FMPI2C_ITMasterCplt(hfmpi2c, ITFlags); @@ -3545,18 +3597,18 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hfmpi2c); - - if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET)) + + if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET)) { /* Check that FMPI2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if(FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c) == 0U) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -3566,17 +3618,17 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; } } - else if(((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET)) { /* Clear ADDR flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); } - else if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET)) + else if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Slave complete process */ FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags); @@ -3592,7 +3644,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm * @brief Master sends target device address followed by internal memory address for write request. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -3601,12 +3654,12 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm */ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK) + if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -3617,7 +3670,7 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c } /* If Memory address size is 8Bit */ - if(MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); @@ -3629,9 +3682,9 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK) + if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -3640,25 +3693,26 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); } /* Wait until TCR flag is set */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } -return HAL_OK; + return HAL_OK; } /** * @brief Master sends target device address followed by internal memory address for read request. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. - * @param DevAddress Target device address + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -3667,12 +3721,12 @@ return HAL_OK; */ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK) + if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -3683,7 +3737,7 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, } /* If Memory address size is 8Bit */ - if(MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); @@ -3695,9 +3749,9 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK) + if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK) { - if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) + if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) { return HAL_ERROR; } @@ -3706,17 +3760,17 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); } /* Wait until TC flag is set */ - if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + return HAL_OK; } @@ -3733,8 +3787,11 @@ static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) uint16_t ownadd1code = 0; uint16_t ownadd2code = 0; + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + /* In case of Listen state, need to inform upper layer of address match code event */ - if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN) + if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN) { transferdirection = FMPI2C_GET_DIR(hfmpi2c); slaveaddrcode = FMPI2C_GET_ADDR_MATCH(hfmpi2c); @@ -3742,19 +3799,19 @@ static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) ownadd2code = FMPI2C_GET_OWN_ADDRESS2(hfmpi2c); /* If 10bits addressing mode is selected */ - if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT) + if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT) { - if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) { slaveaddrcode = ownadd1code; hfmpi2c->AddrEventCount++; - if(hfmpi2c->AddrEventCount == 2U) + if (hfmpi2c->AddrEventCount == 2U) { - /* Reset Address Event counter */ + /* Reset Address Event counter */ hfmpi2c->AddrEventCount = 0U; /* Clear ADDR flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR); + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3855,8 +3912,8 @@ static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c) { /* Reset FMPI2C handle mode */ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - - if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) + + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_TX, keep only HAL_FMPI2C_STATE_LISTEN */ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; @@ -3872,7 +3929,7 @@ static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c) HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c); } - else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN) + else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN) { /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_RX, keep only HAL_FMPI2C_STATE_LISTEN */ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; @@ -3908,7 +3965,7 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) hfmpi2c->XferISR = NULL; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - if((ITFlags & FMPI2C_FLAG_AF) != RESET) + if ((ITFlags & FMPI2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -3919,21 +3976,21 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); - + /* Disable Interrupts */ - FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT| FMPI2C_XFER_RX_IT); + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT); /* Call the corresponding callback to inform upper layer of End of Transfer */ - if((hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) || (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)) + if ((hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) || (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode); } /* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX */ - else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX) + else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX) { hfmpi2c->State = HAL_FMPI2C_STATE_READY; - + if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM) { hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; @@ -3956,10 +4013,10 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) } } /* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX */ - else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) { hfmpi2c->State = HAL_FMPI2C_STATE_READY; - + if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM) { hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; @@ -3993,7 +4050,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); /* Clear ADDR flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR); + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); /* Disable all interrupts */ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT); @@ -4008,52 +4065,52 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) FMPI2C_Flush_TXDR(hfmpi2c); /* If a DMA is ongoing, Update handle size context */ - if(((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) || - ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)) + if (((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) || + ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)) { hfmpi2c->XferCount = FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c); } - + /* All data are not transferred, so set error code accordingly */ - if(hfmpi2c->XferCount != 0U) + if (hfmpi2c->XferCount != 0U) { /* Set ErrorCode corresponding to a Non-Acknowledge */ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; } - + /* Store Last receive data if any */ - if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET)) + if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR; - - if((hfmpi2c->XferSize > 0U)) + + if ((hfmpi2c->XferSize > 0U)) { hfmpi2c->XferSize--; hfmpi2c->XferCount--; - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; } } - + hfmpi2c->PreviousState = FMPI2C_STATE_NONE; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; hfmpi2c->XferISR = NULL; - - if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) + + if (hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if(hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) + if (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) { /* Call FMPI2C Listen complete process */ FMPI2C_ITListenCplt(hfmpi2c, ITFlags); } } - else if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) + else if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) { hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->State = HAL_FMPI2C_STATE_READY; @@ -4065,7 +4122,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) HAL_FMPI2C_ListenCpltCallback(hfmpi2c); } /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) { hfmpi2c->State = HAL_FMPI2C_STATE_READY; @@ -4086,7 +4143,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c); } } - + /** * @brief FMPI2C Listen complete process. * @param hfmpi2c FMPI2C handle. @@ -4103,16 +4160,16 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) hfmpi2c->XferISR = NULL; /* Store Last receive data if any */ - if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET)) + if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR; - - if((hfmpi2c->XferSize > 0U)) + + if ((hfmpi2c->XferSize > 0U)) { hfmpi2c->XferSize--; hfmpi2c->XferCount--; - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; } @@ -4148,13 +4205,13 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) hfmpi2c->ErrorCode |= ErrorCode; /* Disable Interrupts */ - if((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) || - (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) || - (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)) + if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) || + (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) || + (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT); - + /* keep HAL_FMPI2C_STATE_LISTEN if set */ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; hfmpi2c->PreviousState = FMPI2C_STATE_NONE; @@ -4164,10 +4221,10 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) { /* Disable all interrupts */ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT); - + /* If state is an abort treatment on goind, don't change state */ /* This change will be do later */ - if(hfmpi2c->State != HAL_FMPI2C_STATE_ABORT) + if (hfmpi2c->State != HAL_FMPI2C_STATE_ABORT) { /* Set HAL_FMPI2C_STATE_READY */ hfmpi2c->State = HAL_FMPI2C_STATE_READY; @@ -4177,45 +4234,47 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) } /* Abort DMA TX transfer if any */ - if((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) + if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) { hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN; - /* Set the FMPI2C DMA Abort callback : + /* Set the FMPI2C DMA Abort callback : will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); - if(HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK) + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx); } } /* Abort DMA RX transfer if any */ - else if((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN) + else if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN) { hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; - /* Set the FMPI2C DMA Abort callback : + /* Set the FMPI2C DMA Abort callback : will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); - if(HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK) + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK) { - /* Call Directly XferAbortCallback function in case of error */ + /* Call Directly hfmpi2c->hdmarx->XferAbortCallback function in case of error */ hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx); } } - else if(hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) + else if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) { hfmpi2c->State = HAL_FMPI2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -4241,13 +4300,13 @@ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c) { /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET) { - hfmpi2c->Instance->TXDR = 0x00U; + hfmpi2c->Instance->TXDR = 0x00U; } /* Flush TX register if not empty */ - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXE) == RESET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXE) == RESET) { __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_TXE); } @@ -4260,13 +4319,13 @@ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c) */ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hfmpi2c->XferCount == 0U) + if (hfmpi2c->XferCount == 0U) { /* Enable STOP interrupt */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT); @@ -4278,7 +4337,7 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) hfmpi2c->pBuffPtr += hfmpi2c->XferSize; /* Set the XferSize to transfer */ - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4287,7 +4346,7 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) hfmpi2c->XferSize = hfmpi2c->XferCount; } - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); /* Enable TC interrupts */ @@ -4302,6 +4361,9 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* No specific action, Master fully manage the generation of STOP condition */ /* Mean that this generation can arrive at any time, at the end or during DMA process */ /* So STOP condition should be manage through Interrupt treatment */ @@ -4314,13 +4376,13 @@ static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hfmpi2c->XferCount == 0U) + if (hfmpi2c->XferCount == 0U) { /* Enable STOP interrupt */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT); @@ -4332,7 +4394,7 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) hfmpi2c->pBuffPtr += hfmpi2c->XferSize; /* Set the XferSize to transfer */ - if(hfmpi2c->XferCount > MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4341,7 +4403,7 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) hfmpi2c->XferSize = hfmpi2c->XferCount; } - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize); /* Enable TC interrupts */ @@ -4356,6 +4418,9 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* No specific action, Master fully manage the generation of STOP condition */ /* Mean that this generation can arrive at any time, at the end or during DMA process */ /* So STOP condition should be manage through Interrupt treatment */ @@ -4368,7 +4433,7 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; @@ -4380,12 +4445,12 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA FMPI2C communication abort callback * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; @@ -4395,10 +4460,10 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Check if come from abort from user */ - if(hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) + if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) { hfmpi2c->State = HAL_FMPI2C_STATE_READY; - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_FMPI2C_AbortCpltCallback(hfmpi2c); } @@ -4421,14 +4486,14 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status) + while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hfmpi2c->State= HAL_FMPI2C_STATE_READY; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; /* Process Unlocked */ @@ -4450,21 +4515,21 @@ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfm */ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET) + while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET) { /* Check if a NACK is detected */ - if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) + if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State= HAL_FMPI2C_STATE_READY; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; /* Process Unlocked */ @@ -4487,19 +4552,19 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef */ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) + while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ - if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) + if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State= HAL_FMPI2C_STATE_READY; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; /* Process Unlocked */ @@ -4521,38 +4586,49 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef */ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET) + while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET) { /* Check if a NACK is detected */ - if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) + if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check if a STOPF is detected */ - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET) { - /* Clear STOP Flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET) && (hfmpi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + /* Clear STOP Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); - /* Clear Configuration Register 2 */ - FMPI2C_RESET_CR2(hfmpi2c); + /* Clear Configuration Register 2 */ + FMPI2C_RESET_CR2(hfmpi2c); - hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; - hfmpi2c->State= HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + return HAL_ERROR; + } } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State= HAL_FMPI2C_STATE_READY; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -4573,18 +4649,18 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef */ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) { - if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) { /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ - while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) + while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hfmpi2c->State= HAL_FMPI2C_STATE_READY; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; /* Process Unlocked */ @@ -4607,7 +4683,7 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2 FMPI2C_RESET_CR2(hfmpi2c); hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF; - hfmpi2c->State= HAL_FMPI2C_STATE_READY; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; /* Process Unlocked */ @@ -4639,25 +4715,14 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2 */ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0U; - /* Check the parameters */ assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); - /* Get the CR2 register value */ - tmpreg = hfmpi2c->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << 16U) & FMPI2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - /* update CR2 register */ - hfmpi2c->Instance->CR2 = tmpreg; + MODIFY_REG(hfmpi2c->Instance->CR2, ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** @@ -4671,28 +4736,28 @@ static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16 { uint32_t tmpisr = 0U; - if((hfmpi2c->XferISR == FMPI2C_Master_ISR_DMA) || \ - (hfmpi2c->XferISR == FMPI2C_Slave_ISR_DMA)) + if ((hfmpi2c->XferISR == FMPI2C_Master_ISR_DMA) || \ + (hfmpi2c->XferISR == FMPI2C_Slave_ISR_DMA)) { - if((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT) + if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } - if((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT) + if ((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI; } - if((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT) + if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= FMPI2C_IT_STOPI; } - - if((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT) + + if ((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= FMPI2C_IT_TCI; @@ -4700,31 +4765,31 @@ static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16 } else { - if((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT) + if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK, and ADDR interrupts */ tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } - if((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT) + if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT) { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI; } - if((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT) + if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT) { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI; } - if((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT) + if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= FMPI2C_IT_STOPI; } } - + /* Enable interrupts only at the end */ /* to avoid the risk of FMPI2C interrupt handle execution before */ /* all interrupts requested done */ @@ -4744,49 +4809,49 @@ static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint1 { uint32_t tmpisr = 0U; - if((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT) + if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT) { /* Disable TC and TXI interrupts */ tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_TXI; - if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN) + if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } } - if((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT) + if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT) { /* Disable TC and RXI interrupts */ tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_RXI; - if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN) + if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } } - if((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT) + if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT) { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } - if((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT) + if ((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI; } - if((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT) + if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= FMPI2C_IT_STOPI; } - - if((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT) + + if ((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= FMPI2C_IT_TCI; diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.h index 8036ec4749..deacf685a6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_fmpi2c.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FMPI2C HAL module. ****************************************************************************** * @attention @@ -40,14 +38,14 @@ #define __STM32F4xx_HAL_FMPI2C_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" +#include "stm32f4xx_hal_def.h" /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -55,7 +53,7 @@ /** @addtogroup FMPI2C * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FMPI2C_Exported_Types FMPI2C Exported Types @@ -63,13 +61,13 @@ */ /** @defgroup FMPI2C_Configuration_Structure_definition FMPI2C Configuration Structure definition - * @brief FMPI2C Configuration Structure definition + * @brief FMPI2C Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the FMPI2C_TIMINGR_register value. - This parameter calculated by referring to FMPI2C initialization + This parameter calculated by referring to FMPI2C initialization section in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. @@ -93,56 +91,56 @@ typedef struct uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */ -}FMPI2C_InitTypeDef; +} FMPI2C_InitTypeDef; -/** +/** * @} */ /** @defgroup HAL_state_structure_definition HAL state structure definition * @brief HAL State structure definition - * @note HAL FMPI2C State value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : Abort (Abort user request on going) - * 10 : Timeout - * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized and ready to use. HAL FMPI2C Init function called) - * b4 (not used) - * x : Should be set to 0 - * b3 - * 0 : Ready or Busy (No Listen mode ongoing) - * 1 : Listen (IP in Address Listen Mode) - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) + * @note HAL FMPI2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 IP initilisation status\n + * 0 : Reset (IP not initialized)\n + * 1 : Init done (IP initialized and ready to use. HAL FMPI2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (IP in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (IP busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n * 1 : Busy (Tx operation ongoing) * @{ - */ + */ typedef enum { HAL_FMPI2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ HAL_FMPI2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ HAL_FMPI2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ - HAL_FMPI2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_FMPI2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ HAL_FMPI2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ HAL_FMPI2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ HAL_FMPI2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission - process is ongoing */ + process is ongoing */ HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception - process is ongoing */ + process is ongoing */ HAL_FMPI2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */ + HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */ -}HAL_FMPI2C_StateTypeDef; +} HAL_FMPI2C_StateTypeDef; /** * @} @@ -150,19 +148,19 @@ typedef enum /** @defgroup HAL_mode_structure_definition HAL mode structure definition * @brief HAL Mode structure definition - * @note HAL FMPI2C Mode value coding follow below described bitmap : - * b7 (not used) - * x : Should be set to 0 - * b6 - * 0 : None - * 1 : Memory (HAL FMPI2C communication is in Memory Mode) - * b5 - * 0 : None - * 1 : Slave (HAL FMPI2C communication is in Slave Mode) - * b4 - * 0 : None - * 1 : Master (HAL FMPI2C communication is in Master Mode) - * b3-b2-b1-b0 (not used) + * @note HAL FMPI2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL FMPI2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL FMPI2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL FMPI2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n * xxxx : Should be set to 0000 * @{ */ @@ -173,30 +171,30 @@ typedef enum HAL_FMPI2C_MODE_SLAVE = 0x20U, /*!< FMPI2C communication is in Slave Mode */ HAL_FMPI2C_MODE_MEM = 0x40U /*!< FMPI2C communication is in Memory Mode */ -}HAL_FMPI2C_ModeTypeDef; +} HAL_FMPI2C_ModeTypeDef; -/** +/** * @} */ /** @defgroup FMPI2C_Error_Code_definition FMPI2C Error Code definition - * @brief FMPI2C Error Code definition + * @brief FMPI2C Error Code definition * @{ */ -#define HAL_FMPI2C_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_FMPI2C_ERROR_BERR 0x00000001U /*!< BERR error */ -#define HAL_FMPI2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ -#define HAL_FMPI2C_ERROR_AF 0x00000004U /*!< ACKF error */ -#define HAL_FMPI2C_ERROR_OVR 0x00000008U /*!< OVR error */ -#define HAL_FMPI2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ -#define HAL_FMPI2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ -#define HAL_FMPI2C_ERROR_SIZE 0x00000040U /*!< Size Management error */ +#define HAL_FMPI2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_FMPI2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_FMPI2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_FMPI2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_FMPI2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_FMPI2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_FMPI2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_FMPI2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ /** * @} */ /** @defgroup FMPI2C_handle_Structure_definition FMPI2C handle Structure definition - * @brief FMPI2C handle Structure definition + * @brief FMPI2C handle Structure definition * @{ */ typedef struct __FMPI2C_HandleTypeDef @@ -205,33 +203,33 @@ typedef struct __FMPI2C_HandleTypeDef FMPI2C_InitTypeDef Init; /*!< FMPI2C communication parameters */ - uint8_t *pBuffPtr; /*!< Pointer to FMPI2C transfer buffer */ + uint8_t *pBuffPtr; /*!< Pointer to FMPI2C transfer buffer */ - uint16_t XferSize; /*!< FMPI2C transfer size */ + uint16_t XferSize; /*!< FMPI2C transfer size */ - __IO uint16_t XferCount; /*!< FMPI2C transfer counter */ + __IO uint16_t XferCount; /*!< FMPI2C transfer counter */ - __IO uint32_t XferOptions; /*!< FMPI2C sequantial transfer options, this parameter can + __IO uint32_t XferOptions; /*!< FMPI2C sequantial transfer options, this parameter can be a value of @ref FMPI2C_XFEROPTIONS */ - __IO uint32_t PreviousState; /*!< FMPI2C communication Previous state */ + __IO uint32_t PreviousState; /*!< FMPI2C communication Previous state */ - HAL_StatusTypeDef (*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); /*!< FMPI2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); /*!< FMPI2C transfer IRQ handler function pointer */ - DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */ - DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */ - HAL_LockTypeDef Lock; /*!< FMPI2C locking object */ + HAL_LockTypeDef Lock; /*!< FMPI2C locking object */ __IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */ __IO HAL_FMPI2C_ModeTypeDef Mode; /*!< FMPI2C communication mode */ - __IO uint32_t ErrorCode; /*!< FMPI2C Error code */ + __IO uint32_t ErrorCode; /*!< FMPI2C Error code */ - __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */ -}FMPI2C_HandleTypeDef; + __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */ +} FMPI2C_HandleTypeDef; /** * @} */ @@ -253,6 +251,7 @@ typedef struct __FMPI2C_HandleTypeDef #define FMPI2C_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE)) #define FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE) #define FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE) +#define FMPI2C_LAST_FRAME_NO_STOP ((uint32_t)FMPI2C_SOFTEND_MODE) /** * @} */ @@ -260,8 +259,8 @@ typedef struct __FMPI2C_HandleTypeDef /** @defgroup FMPI2C_ADDRESSING_MODE FMPI2C Addressing Mode * @{ */ -#define FMPI2C_ADDRESSINGMODE_7BIT 0x00000001U -#define FMPI2C_ADDRESSINGMODE_10BIT 0x00000002U +#define FMPI2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define FMPI2C_ADDRESSINGMODE_10BIT (0x00000002U) /** * @} */ @@ -269,7 +268,7 @@ typedef struct __FMPI2C_HandleTypeDef /** @defgroup FMPI2C_DUAL_ADDRESSING_MODE FMPI2C Dual Addressing Mode * @{ */ -#define FMPI2C_DUALADDRESS_DISABLE 0x00000000U +#define FMPI2C_DUALADDRESS_DISABLE (0x00000000U) #define FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN /** * @} @@ -278,7 +277,6 @@ typedef struct __FMPI2C_HandleTypeDef /** @defgroup FMPI2C_OWN_ADDRESS2_MASKS FMPI2C Own Address2 Masks * @{ */ - #define FMPI2C_OA2_NOMASK ((uint8_t)0x00) #define FMPI2C_OA2_MASK01 ((uint8_t)0x01) #define FMPI2C_OA2_MASK02 ((uint8_t)0x02) @@ -287,7 +285,6 @@ typedef struct __FMPI2C_HandleTypeDef #define FMPI2C_OA2_MASK05 ((uint8_t)0x05) #define FMPI2C_OA2_MASK06 ((uint8_t)0x06) #define FMPI2C_OA2_MASK07 ((uint8_t)0x07) - /** * @} */ @@ -295,7 +292,7 @@ typedef struct __FMPI2C_HandleTypeDef /** @defgroup FMPI2C_GENERAL_CALL_ADDRESSING_MODE FMPI2C General Call Addressing Mode * @{ */ -#define FMPI2C_GENERALCALL_DISABLE 0x00000000U +#define FMPI2C_GENERALCALL_DISABLE (0x00000000U) #define FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN /** * @} @@ -304,7 +301,7 @@ typedef struct __FMPI2C_HandleTypeDef /** @defgroup FMPI2C_NOSTRETCH_MODE FMPI2C No-Stretch Mode * @{ */ -#define FMPI2C_NOSTRETCH_DISABLE 0x00000000U +#define FMPI2C_NOSTRETCH_DISABLE (0x00000000U) #define FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH /** * @} @@ -313,19 +310,17 @@ typedef struct __FMPI2C_HandleTypeDef /** @defgroup FMPI2C_MEMORY_ADDRESS_SIZE FMPI2C Memory Address Size * @{ */ -#define FMPI2C_MEMADD_SIZE_8BIT 0x00000001U -#define FMPI2C_MEMADD_SIZE_16BIT 0x00000002U - +#define FMPI2C_MEMADD_SIZE_8BIT (0x00000001U) +#define FMPI2C_MEMADD_SIZE_16BIT (0x00000002U) /** * @} */ - -/** @defgroup FMPI2C_XferDirection FMPI2C Transfer Direction + +/** @defgroup FMPI2C_XFERDIRECTION FMPI2C Transfer Direction Master Point of View * @{ */ -#define FMPI2C_DIRECTION_RECEIVE 0x00000000U -#define FMPI2C_DIRECTION_TRANSMIT 0x00000001U - +#define FMPI2C_DIRECTION_TRANSMIT (0x00000000U) +#define FMPI2C_DIRECTION_RECEIVE (0x00000001U) /** * @} */ @@ -335,8 +330,7 @@ typedef struct __FMPI2C_HandleTypeDef */ #define FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD #define FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND -#define FMPI2C_SOFTEND_MODE 0x00000000U - +#define FMPI2C_SOFTEND_MODE (0x00000000U) /** * @} */ @@ -344,12 +338,10 @@ typedef struct __FMPI2C_HandleTypeDef /** @defgroup FMPI2C_START_STOP_MODE FMPI2C Start or Stop Mode * @{ */ - -#define FMPI2C_NO_STARTSTOP 0x00000000U -#define FMPI2C_GENERATE_STOP FMPI2C_CR2_STOP -#define FMPI2C_GENERATE_START_READ (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) -#define FMPI2C_GENERATE_START_WRITE FMPI2C_CR2_START - +#define FMPI2C_NO_STARTSTOP (0x00000000U) +#define FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) +#define FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) +#define FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /** * @} */ @@ -373,7 +365,7 @@ typedef struct __FMPI2C_HandleTypeDef /** @defgroup FMPI2C_Flag_definition FMPI2C Flag definition * @{ - */ + */ #define FMPI2C_FLAG_TXE FMPI2C_ISR_TXE #define FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS #define FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE @@ -399,7 +391,7 @@ typedef struct __FMPI2C_HandleTypeDef */ /* Exported macros -----------------------------------------------------------*/ - + /** @defgroup FMPI2C_Exported_Macros FMPI2C Exported Macros * @{ */ @@ -437,11 +429,11 @@ typedef struct __FMPI2C_HandleTypeDef * @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable * @arg @ref FMPI2C_IT_RXI RX interrupt enable * @arg @ref FMPI2C_IT_TXI TX interrupt enable - * + * * @retval None */ #define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - + /** @brief Check whether the specified FMPI2C interrupt source is enabled or not. * @param __HANDLE__ specifies the FMPI2C Handle. * @param __INTERRUPT__ specifies the FMPI2C interrupt source to check. @@ -493,16 +485,16 @@ typedef struct __FMPI2C_HandleTypeDef * @arg @ref FMPI2C_FLAG_STOPF STOP detection flag * @arg @ref FMPI2C_FLAG_BERR Bus error * @arg @ref FMPI2C_FLAG_ARLO Arbitration lost - * @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun + * @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun * @arg @ref FMPI2C_FLAG_PECERR PEC error in reception - * @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref FMPI2C_FLAG_ALERT SMBus alert * * @retval None */ #define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ : ((__HANDLE__)->Instance->ICR = (__FLAG__))) - + /** @brief Enable the specified FMPI2C peripheral. * @param __HANDLE__ specifies the FMPI2C Handle. * @retval None @@ -516,7 +508,7 @@ typedef struct __FMPI2C_HandleTypeDef #define __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) /** @brief Generate a Non-Acknowledge FMPI2C peripheral in Slave mode. - * @param __HANDLE__: specifies the FMPI2C Handle. + * @param __HANDLE__ specifies the FMPI2C Handle. * @retval None */ #define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) @@ -537,7 +529,7 @@ typedef struct __FMPI2C_HandleTypeDef */ /* Initialization and de-initialization functions******************************/ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c); -HAL_StatusTypeDef HAL_FMPI2C_DeInit (FMPI2C_HandleTypeDef *hfmpi2c); +HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c); void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c); void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c); /** @@ -548,7 +540,7 @@ void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c); * @{ */ /* IO operation functions ****************************************************/ - /******* Blocking mode: Polling */ +/******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -557,7 +549,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - /******* Non-Blocking mode: Interrupt */ +/******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); @@ -573,7 +565,7 @@ HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c); HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c); HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress); - /******* Non-Blocking mode: DMA */ +/******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); @@ -602,7 +594,7 @@ void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c); void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); /** * @} - */ + */ /** @addtogroup FMPI2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions * @{ @@ -614,11 +606,11 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); /** * @} - */ + */ /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup FMPI2C_Private_Constants FMPI2C Private Constants @@ -627,7 +619,7 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup FMPI2C_Private_Macro FMPI2C Private Macros @@ -635,19 +627,19 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); */ #define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT)) + ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT)) #define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE)) + ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE)) #define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \ - ((MASK) == FMPI2C_OA2_MASK01) || \ - ((MASK) == FMPI2C_OA2_MASK02) || \ - ((MASK) == FMPI2C_OA2_MASK03) || \ - ((MASK) == FMPI2C_OA2_MASK04) || \ - ((MASK) == FMPI2C_OA2_MASK05) || \ - ((MASK) == FMPI2C_OA2_MASK06) || \ - ((MASK) == FMPI2C_OA2_MASK07)) + ((MASK) == FMPI2C_OA2_MASK01) || \ + ((MASK) == FMPI2C_OA2_MASK02) || \ + ((MASK) == FMPI2C_OA2_MASK03) || \ + ((MASK) == FMPI2C_OA2_MASK04) || \ + ((MASK) == FMPI2C_OA2_MASK05) || \ + ((MASK) == FMPI2C_OA2_MASK06) || \ + ((MASK) == FMPI2C_OA2_MASK07)) #define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \ ((CALL) == FMPI2C_GENERALCALL_ENABLE)) @@ -671,7 +663,8 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \ ((REQUEST) == FMPI2C_NEXT_FRAME) || \ ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == FMPI2C_LAST_FRAME)) + ((REQUEST) == FMPI2C_LAST_FRAME) || \ + ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP)) #define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN))) @@ -684,14 +677,14 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); #define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) -#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8U))) -#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) +#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8U))) +#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) #define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions @@ -700,11 +693,11 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); /* Private functions are defined in stm32f4xx_hal_fmpi2c.c file */ /** * @} - */ + */ /** * @} - */ + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.c index cb31ae223f..f3846da12b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.c @@ -2,36 +2,31 @@ ****************************************************************************** * @file stm32f4xx_hal_fmpi2c_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief FMPI2C Extended HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of FMPI2C Extended peripheral: * + Extended features functions - * + * @verbatim ============================================================================== ##### FMPI2C peripheral Extended features ##### ============================================================================== - + [..] Comparing to other previous devices, the FMPI2C interface for STM32F4xx devices contains the following additional features - + (+) Possibility to disable or enable Analog Noise Filter (+) Use of a configured Digital Noise Filter - (+) Disable or enable wakeup from Stop mode - + (+) Disable or enable Fast Mode Plus + ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure Noise Filter and Wake Up Feature (#) Configure FMPI2C Analog noise filter using the function HAL_FMPI2CEx_ConfigAnalogFilter() (#) Configure FMPI2C Digital noise filter using the function HAL_FMPI2CEx_ConfigDigitalFilter() - (#) Configure the enable or disable of FMPI2C Wake Up Mode using the functions : - (++) HAL_FMPI2CEx_EnableWakeUp() - (++) HAL_FMPI2CEx_DisableWakeUp() (#) Configure the enable or disable of fast mode plus driving capability using the functions : (++) HAL_FMPI2CEx_EnableFastModePlus() - (++) HAL_FMPI2CEx_DisbleFastModePlus() + (++) HAL_FMPI2CEx_DisableFastModePlus() @endverbatim ****************************************************************************** * @attention @@ -60,7 +55,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -93,21 +88,21 @@ /** @defgroup FMPI2CEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions - * -@verbatim + * +@verbatim =============================================================================== ##### Extended features functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: - (+) Configure Noise Filters - (+) Configure Wake Up Feature + (+) Configure Noise Filters + (+) Configure Fast Mode Plus @endverbatim * @{ */ - + /** - * @brief Configure FMPI2C Analog noise filter. + * @brief Configure FMPI2C Analog noise filter. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2Cx peripheral. * @param AnalogFilter New state of the Analog filter. @@ -119,8 +114,8 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance)); assert_param(IS_FMPI2C_ANALOG_FILTER(AnalogFilter)); - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) - { + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) + { /* Process Locked */ __HAL_LOCK(hfmpi2c); @@ -142,7 +137,7 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); - return HAL_OK; + return HAL_OK; } else { @@ -151,10 +146,10 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c, } /** - * @brief Configure FMPI2C Digital noise filter. + * @brief Configure FMPI2C Digital noise filter. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2Cx peripheral. - * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter) @@ -165,7 +160,7 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance)); assert_param(IS_FMPI2C_DIGITAL_FILTER(DigitalFilter)); - if(hfmpi2c->State == HAL_FMPI2C_STATE_READY) + if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hfmpi2c); diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.h index 775d137914..210fae9ca6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_fmpi2c_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FMPI2C HAL Extended module. ****************************************************************************** * @attention @@ -40,7 +38,7 @@ #define __STM32F4xx_HAL_FMPI2C_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ @@ -55,7 +53,7 @@ /** @addtogroup FMPI2CEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -67,8 +65,8 @@ /** @defgroup FMPI2CEx_Analog_Filter FMPI2C Extended Analog Filter * @{ */ -#define FMPI2C_ANALOGFILTER_ENABLE 0x00000000U -#define FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF +#define FMPI2C_ANALOGFILTER_ENABLE 0x00000000U +#define FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF /** * @} */ @@ -84,8 +82,8 @@ /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -111,7 +109,7 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup FMPI2CEx_Private_Macro FMPI2C Extended Private Macros @@ -159,5 +157,4 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif /* __STM32F4xx_HAL_FMPI2C_EX_H */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.c index 876b37bbfd..1430d1889e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -180,9 +178,9 @@ /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ @@ -305,9 +303,9 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /** * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -386,9 +384,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /** * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: specifies the port bit to read. + * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ @@ -417,11 +415,11 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. + * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin @@ -445,9 +443,9 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin /** * @brief Toggles the specified GPIO pins. - * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: Specifies the pins to be toggled. + * @param GPIO_Pin Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -464,8 +462,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F4 family - * @param GPIO_Pin: specifies the port bit to be locked. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family + * @param GPIO_Pin specifies the port bit to be locked. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -499,7 +497,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) @@ -514,7 +512,7 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) /** * @brief EXTI line detection callbacks. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.h index b1f3269e2d..6a850df9c9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -187,7 +185,7 @@ typedef enum /** * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -195,7 +193,7 @@ typedef enum /** * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -203,7 +201,7 @@ typedef enum /** * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -211,7 +209,7 @@ typedef enum /** * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -219,7 +217,7 @@ typedef enum /** * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h index 620fa583d2..b958e4b998 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.c index 306ef388dc..54a9446ee0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_hash.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral: @@ -134,7 +132,7 @@ static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size); /** * @brief DMA HASH Input Data complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) @@ -206,7 +204,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA HASH communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void HASH_DMAError(DMA_HandleTypeDef *hdma) @@ -218,8 +216,8 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Writes the input buffer in data register. - * @param pInBuffer: Pointer to input buffer - * @param Size: The size of input buffer + * @param pInBuffer Pointer to input buffer + * @param Size The size of input buffer * @retval None */ static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size) @@ -236,8 +234,8 @@ static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size) /** * @brief Provides the message digest result. - * @param pMsgDigest: Pointer to the message digest - * @param Size: The size of the message digest in bytes + * @param pMsgDigest Pointer to the message digest + * @param Size The size of the message digest in bytes * @retval None */ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) @@ -338,7 +336,7 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) /** * @brief Initializes the HASH according to the specified parameters in the HASH_HandleTypeDef and creates the associated handle. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval HAL status */ @@ -385,7 +383,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /** * @brief DeInitializes the HASH peripheral. * @note This API must be called before starting a new processing. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval HAL status */ @@ -423,7 +421,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH MSP. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -438,7 +436,7 @@ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash) /** * @brief DeInitializes HASH MSP. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -453,7 +451,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Input data transfer complete callback. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -468,7 +466,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Data transfer Error callback. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -484,7 +482,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Digest computation complete callback. It is used only with interrupt. * @note This callback is not relevant with DMA. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -520,15 +518,15 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is multiple of 64 bytes, appending the input buffer is possible. * If the Size is not multiple of 64 bytes, the padding is managed by hardware * and appending the input buffer is no more possible. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -597,10 +595,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /** * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is multiple of 64 bytes, appending the input buffer is possible. * If the Size is not multiple of 64 bytes, the padding is managed by hardware * and appending the input buffer is no more possible. @@ -644,13 +642,13 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -719,10 +717,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /** * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted. * @retval HAL status @@ -788,12 +786,12 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p /** * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. + * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -947,12 +945,12 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB /** * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -1105,7 +1103,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief This function handles HASH interrupt request. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -1149,10 +1147,10 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to control data transfer. Use HAL_HASH_MD5_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1200,10 +1198,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief Returns the computed digest in MD5 mode - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1253,10 +1251,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu /** * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1305,10 +1303,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Returns the computed digest in SHA1 mode. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1378,13 +1376,13 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB /** * @brief Initializes the HASH peripheral in HMAC MD5 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1523,13 +1521,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /** * @brief Initializes the HASH peripheral in HMAC SHA1 mode * then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1687,10 +1685,10 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /** * @brief Initializes the HASH peripheral in HMAC MD5 mode * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1754,10 +1752,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief Initializes the HASH peripheral in HMAC SHA1 mode * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1838,7 +1836,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief return the HASH state - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval HAL state */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.h index f52880559b..cf628e53b1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_hash.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention @@ -226,13 +224,13 @@ typedef struct */ /** @brief Reset HASH handle state - * @param __HANDLE__: specifies the HASH handle. + * @param __HANDLE__ specifies the HASH handle. * @retval None */ #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET) /** @brief Check whether the specified HASH flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer. * @arg HASH_FLAG_DCIS: Digest calculation complete @@ -265,7 +263,7 @@ typedef struct /** * @brief Set the number of valid bits in last word written in Data register - * @param SIZE: size in byte of last data written in Data register. + * @param SIZE size in byte of last data written in Data register. * @retval None */ #define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.c index 887eae38c9..4d882315e8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_hash_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief HASH HAL Extension module driver. * This file provides firmware functions to manage the following * functionalities of HASH peripheral: @@ -132,8 +130,8 @@ static void HASHEx_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Writes the input buffer in data register. - * @param pInBuffer: Pointer to input buffer - * @param Size: The size of input buffer + * @param pInBuffer Pointer to input buffer + * @param Size The size of input buffer * @retval None */ static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size) @@ -150,8 +148,8 @@ static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size) /** * @brief Provides the message digest result. - * @param pMsgDigest: Pointer to the message digest - * @param Size: The size of the message digest in bytes + * @param pMsgDigest Pointer to the message digest + * @param Size The size of the message digest in bytes * @retval None */ static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size) @@ -223,7 +221,7 @@ static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size) /** * @brief DMA HASH Input Data complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma) @@ -295,7 +293,7 @@ static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA HASH communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void HASHEx_DMAError(DMA_HandleTypeDef *hdma) @@ -333,13 +331,13 @@ static void HASHEx_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Initializes the HASH peripheral in SHA224 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes. - * @param Timeout: Specify Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes. + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -409,13 +407,13 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes. - * @param Timeout: Specify Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes. + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -486,10 +484,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA224 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -532,10 +530,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_ /** * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -598,13 +596,13 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ /** * @brief Initializes the HASH peripheral in HMAC SHA224 mode * then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -742,13 +740,13 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in HMAC SHA256 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -909,12 +907,12 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -1060,12 +1058,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -1209,7 +1207,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief This function handles HASH interrupt request. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -1255,10 +1253,10 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1306,10 +1304,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Returns the computed digest in SHA224 - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1359,10 +1357,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1410,10 +1408,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Returns the computed digest in SHA256. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1483,10 +1481,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** * @brief Initializes the HASH peripheral in HMAC SHA224 mode * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1550,10 +1548,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initializes the HASH peripheral in HMAC SHA256 mode * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.h index cfba9c0ea9..c93e435c3f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of HASH HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c index af5b42aba9..d28654ea6a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_hcd.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -125,7 +123,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); /** * @brief Initialize the host driver. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) @@ -163,25 +161,25 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /** * @brief Initialize a host channel. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 - * @param epnum: Endpoint number. + * @param epnum Endpoint number. * This parameter can be a value from 1 to 15 - * @param dev_address : Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 - * @param speed: Current device speed. + * @param speed Current device speed. * This parameter can be one of these values: * HCD_SPEED_HIGH: High speed mode, * HCD_SPEED_FULL: Full speed mode, * HCD_SPEED_LOW: Low speed mode - * @param ep_type: Endpoint Type. + * @param ep_type Endpoint Type. * This parameter can be one of these values: * EP_TYPE_CTRL: Control type, * EP_TYPE_ISOC: Isochronous type, * EP_TYPE_BULK: Bulk type, * EP_TYPE_INTR: Interrupt type - * @param mps: Max Packet Size. + * @param mps Max Packet Size. * This parameter can be a value from 0 to32K * @retval HAL status */ @@ -201,12 +199,14 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ep_type = ep_type; - hhcd->hc[ch_num].ep_num = epnum & 0x7FU; - hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80U) == 0x80U); + hhcd->hc[ch_num].ep_num = epnum & 0x7F; + hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80); hhcd->hc[ch_num].speed = speed; +/* MBED */ /* reset to 0 */ hhcd->hc[ch_num].toggle_out = 0; hhcd->hc[ch_num].toggle_in = 0; +/* MBED */ status = USB_HC_Init(hhcd->Instance, ch_num, @@ -222,8 +222,8 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, /** * @brief Halt a host channel. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 * @retval HAL status */ @@ -240,7 +240,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) /** * @brief DeInitialize the host driver. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) @@ -265,7 +265,7 @@ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) /** * @brief Initialize the HCD MSP. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) @@ -279,7 +279,7 @@ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) /** * @brief DeInitialize the HCD MSP. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) @@ -311,24 +311,24 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) /** * @brief Submit a new URB for processing. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 - * @param direction: Channel number. + * @param direction Channel number. * This parameter can be one of these values: * 0 : Output / 1 : Input - * @param ep_type: Endpoint Type. + * @param ep_type Endpoint Type. * This parameter can be one of these values: * EP_TYPE_CTRL: Control type/ * EP_TYPE_ISOC: Isochronous type/ * EP_TYPE_BULK: Bulk type/ * EP_TYPE_INTR: Interrupt type/ - * @param token: Endpoint Type. + * @param token Endpoint Type. * This parameter can be one of these values: * 0: HC_PID_SETUP / 1: HC_PID_DATA1 - * @param pbuff: pointer to URB data - * @param length: Length of URB data - * @param do_ping: activate do ping protocol (for high speed only). + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). * This parameter can be one of these values: * 0 : do ping inactive / 1 : do ping active * @retval HAL status @@ -342,6 +342,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint16_t length, uint8_t do_ping) { +/* MBED */ if ((hhcd->hc[ch_num].ep_is_in != direction)) { if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)){ /* reconfigure the endpoint !!! from tx -> rx, and rx ->tx */ @@ -361,9 +362,10 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, if (direction == 1) hhcd->hc[ch_num].toggle_in=1; } } +/* MBED */ hhcd->hc[ch_num].ep_type = ep_type; - if(token == 0U) + if(token == 0) { hhcd->hc[ch_num].data_pid = HC_PID_SETUP; } @@ -397,6 +399,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].do_ping = do_ping; } } +/* MBED */ else if ((token == 1) && (direction == 1)) { if( hhcd->hc[ch_num].toggle_in == 0) @@ -408,6 +411,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } } +/* MBED */ break; case EP_TYPE_BULK: @@ -483,7 +487,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, /** * @brief Handle HCD interrupt request. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) @@ -586,7 +590,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /** * @brief SOF callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) @@ -600,7 +604,7 @@ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) /** * @brief Connection Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) @@ -614,7 +618,7 @@ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) /** * @brief Disconnection Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) @@ -628,8 +632,8 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) /** * @brief Notify URB state change callback. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @param urb_state: * This parameter can be one of these values: @@ -673,7 +677,7 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t /** * @brief Start the host driver. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) @@ -687,7 +691,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) /** * @brief Stop the host driver. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL status */ @@ -701,7 +705,7 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) /** * @brief Reset the host port. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) @@ -730,7 +734,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) /** * @brief Return the HCD handle state. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL state */ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) @@ -740,8 +744,8 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) /** * @brief Return URB state for a channel. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval URB state. * This parameter can be one of these values: @@ -760,8 +764,8 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu /** * @brief Return the last host transfer size. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval last transfer size in byte */ @@ -772,8 +776,8 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) /** * @brief Return the Host Channel state. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval Host channel state * This parameter can be one of these values: @@ -794,7 +798,7 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) /** * @brief Return the current Host frame number. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval Current Host frame number */ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) @@ -804,7 +808,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) /** * @brief Return the Host enumeration speed. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval Enumeration speed */ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) @@ -825,8 +829,8 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) */ /** * @brief Handle Host Channel IN interrupt requests. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval None */ @@ -902,7 +906,9 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) { +/* MBED */ int reactivate=0; +/* MBED */ __HAL_HCD_MASK_HALT_HC_INT(chnum); if(hhcd->hc[chnum].state == HC_XFRC) @@ -931,16 +937,20 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; +/* MBED */ if ( hhcd->hc[chnum].urb_state != URB_ERROR) { tmpreg |= USB_OTG_HCCHAR_CHENA; reactivate = 1; } +/* MBED */ USBx_HC(chnum)->HCCHAR = tmpreg; } +/* MBED */ if (hhcd->hc[chnum].state == 0) reactivate = 1; __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); if (reactivate == 0) HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +/* MBED */ } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) @@ -977,8 +987,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /** * @brief Handle Host Channel OUT interrupt requests. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval None */ @@ -1115,7 +1125,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) /** * @brief Handle Rx Queue Level interrupt requests. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) @@ -1168,7 +1178,7 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) /** * @brief Handle Host Port interrupt requests. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.h index 5e97876ed9..33722a8506 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_hcd.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c index 9e43671897..6cbbc57bec 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -349,7 +347,7 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); /** * @brief Initializes the I2C according to the specified parameters * in the I2C_InitTypeDef and create the associated handle. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -431,7 +429,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /** * @brief DeInitializes the I2C peripheral. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL status */ @@ -467,7 +465,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /** * @brief I2C MSP Init. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval None */ @@ -482,7 +480,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /** * @brief I2C MSP DeInit - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval None */ @@ -567,8 +565,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) * @brief Transmits in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -699,8 +697,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @brief Receives in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -1187,8 +1185,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1264,8 +1262,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1346,8 +1344,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition @@ -1449,8 +1447,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition @@ -1911,8 +1909,8 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) * @brief Transmit in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -2031,8 +2029,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @brief Receive in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -2152,8 +2150,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D * @note This abort can be called only if state is ready * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) @@ -3937,6 +3935,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; hi2c->XferCount--; +/* MBED */ } else if((tmp == 2U) || (tmp == 3U)) { @@ -3959,6 +3958,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) /* Enable Pos */ hi2c->Instance->CR1 |= I2C_CR1_POS; } +/* MBED */ /* Disable EVT, BUF and ERR interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); @@ -3996,6 +3996,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ uint32_t CurrentXferOptions = hi2c->XferOptions; +/* MBED */ if(hi2c->XferCount == 3U) { if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) @@ -4003,6 +4004,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) /* Disable Acknowledge */ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; } +/* MBED */ /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; @@ -4011,6 +4013,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) else if(hi2c->XferCount == 2U) { /* Prepare next transfer or stop current transfer */ +/* MBED */ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) { /* Disable Acknowledge */ @@ -4021,6 +4024,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) /* Generate ReStart */ hi2c->Instance->CR1 |= I2C_CR1_START; } +/* MBED */ } else { @@ -4684,8 +4688,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c) /** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status @@ -4760,8 +4764,8 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_ * @brief Master sends target device address for read request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status @@ -5179,7 +5183,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.h index 115a3e28d9..5452a507cf 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -348,16 +346,16 @@ typedef struct */ /** @brief Reset I2C handle state - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. * @retval None */ #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) /** @brief Enable or disable the specified I2C interrupts. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg I2C_IT_BUF: Buffer interrupt enable * @arg I2C_IT_EVT: Event interrupt enable @@ -368,9 +366,9 @@ typedef struct #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) /** @brief Checks if the specified I2C interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @param __INTERRUPT__: specifies the I2C interrupt source to check. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. * This parameter can be one of the following values: * @arg I2C_IT_BUF: Buffer interrupt enable * @arg I2C_IT_EVT: Event interrupt enable @@ -380,9 +378,9 @@ typedef struct #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified I2C flag is set or not. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2C_FLAG_SMBALERT: SMBus Alert flag * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag @@ -412,9 +410,9 @@ typedef struct ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) /** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg I2C_FLAG_SMBALERT: SMBus Alert flag * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag @@ -428,7 +426,7 @@ typedef struct #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) /** @brief Clears the I2C ADDR pending flag. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. * @retval None */ @@ -441,7 +439,7 @@ typedef struct } while(0) /** @brief Clears the I2C STOPF pending flag. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. * @retval None */ @@ -454,14 +452,14 @@ typedef struct } while(0) /** @brief Enable the I2C peripheral. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. * @retval None */ #define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) /** @brief Disable the I2C peripheral. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.c index 0f228d9cd8..de8f1602d3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief I2C Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C extension peripheral: @@ -101,9 +99,9 @@ /** * @brief Configures I2C Analog noise filter. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter: new state of the Analog filter. + * @param AnalogFilter new state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) @@ -139,9 +137,9 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t /** * @brief Configures I2C Digital noise filter. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F. + * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.h index 27990d2c5c..ff47d5cc8c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c index e3854fafa0..f80478f6ad 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -210,7 +208,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, /** * @brief Initializes the I2S according to the specified parameters * in the I2S_InitTypeDef and create the associated handle. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -407,7 +405,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /** * @brief DeInitializes the I2S peripheral - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -435,7 +433,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief I2S MSP Init - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -450,7 +448,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief I2S MSP DeInit - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -510,15 +508,15 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief Transmit an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -607,15 +605,15 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin /** * @brief Receive an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming) * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate @@ -715,10 +713,10 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -780,10 +778,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -847,10 +845,10 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u /** * @brief Transmit an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Transmit data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Transmit data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -930,10 +928,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -1020,7 +1018,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Pauses the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1056,7 +1054,7 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1106,7 +1104,7 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1160,7 +1158,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) /** * @brief This function handles I2S interrupt request. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1172,7 +1170,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Tx Transfer Half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1187,7 +1185,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Tx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1202,7 +1200,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief Rx Transfer half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1217,7 +1215,7 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief Rx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1232,7 +1230,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief I2S error callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1266,7 +1264,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief Return the I2S state - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL state */ @@ -1277,7 +1275,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) /** * @brief Return the I2S error code - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval I2S Error Code */ @@ -1298,7 +1296,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) */ /** * @brief DMA I2S transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1318,7 +1316,7 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) } /** * @brief DMA I2S transmit process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1331,7 +1329,7 @@ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1351,7 +1349,7 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1364,7 +1362,7 @@ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S communication error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1385,7 +1383,7 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1407,7 +1405,7 @@ static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1429,7 +1427,7 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) /** * @brief This function handles I2S interrupt request. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1493,11 +1491,11 @@ static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /** * @brief This function handles I2S Communication Timeout. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Timeout: Duration of the timeout + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.h index 208970f7a9..67a7ec0b25 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention @@ -310,21 +308,21 @@ typedef struct __I2S_HandleTypeDef */ /** @brief Reset I2S handle state - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) /** @brief Enable or disable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE) #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &=(uint16_t)(~SPI_I2SCFGR_I2SE)) /** @brief Enable or disable the specified I2S interrupts. - * @param __HANDLE__: specifies the I2S Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -335,9 +333,9 @@ typedef struct __I2S_HandleTypeDef #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &=(uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified I2S interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. - * @param __INTERRUPT__: specifies the I2S interrupt source to check. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -347,8 +345,8 @@ typedef struct __I2S_HandleTypeDef #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified I2S flag is set or not. - * @param __HANDLE__: specifies the I2S Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the I2S Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2S_FLAG_RXNE: Receive buffer not empty flag * @arg I2S_FLAG_TXE: Transmit buffer empty flag @@ -362,7 +360,7 @@ typedef struct __I2S_HandleTypeDef #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clears the I2S OVR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \ @@ -374,7 +372,7 @@ typedef struct __I2S_HandleTypeDef } while(0) /** @brief Clears the I2S UDR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c index 3a3129a88a..aae1ac401a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2S extension peripheral: @@ -136,6 +134,7 @@ typedef enum /** @defgroup I2SEx_Private_Functions I2S Extended Private Functions * @{ */ +static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma); static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma); static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma); static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed); @@ -199,16 +198,16 @@ static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTyp */ /** * @brief Full-Duplex Transmit/Receive data in blocking mode. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pTxData: a 16-bit pointer to the Transmit data buffer. - * @param pRxData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pTxData a 16-bit pointer to the Transmit data buffer. + * @param pRxData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -454,11 +453,11 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p /** * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pTxData: a 16-bit pointer to the Transmit data buffer. - * @param pRxData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pTxData a 16-bit pointer to the Transmit data buffer. + * @param pRxData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -610,11 +609,11 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t /** * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pTxData: a 16-bit pointer to the Transmit data buffer. - * @param pRxData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pTxData a 16-bit pointer to the Transmit data buffer. + * @param pRxData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -665,12 +664,18 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ hi2s->ErrorCode = HAL_I2S_ERROR_NONE; hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; + /* Set the I2S Rx DMA Half transfer complete callback */ + hi2s->hdmarx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt; + /* Set the I2S Rx DMA transfer complete callback */ hi2s->hdmarx->XferCpltCallback = I2SEx_TxRxDMACplt; /* Set the I2S Rx DMA error callback */ hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError; + /* Set the I2S Tx DMA Half transfer complete callback */ + hi2s->hdmatx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt; + /* Set the I2S Tx DMA transfer complete callback */ hi2s->hdmatx->XferCpltCallback = I2SEx_TxRxDMACplt; @@ -751,7 +756,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ /** * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode. - * @param hi2s: I2S handle + * @param hi2s I2S handle * @retval HAL status */ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) @@ -874,9 +879,24 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) } } +/** + * @brief Tx and Rx Transfer half completed callback + * @param hi2s I2S handle + * @retval None + */ +__weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2SEx_TxRxHalfCpltCallback could be implemented in the user file + */ +} + /** * @brief Tx and Rx Transfer completed callback - * @param hi2s: I2S handle + * @param hi2s I2S handle * @retval None */ __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s) @@ -885,7 +905,7 @@ __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s) UNUSED(hi2s); /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2SEx_TxRxCpltCallback could be implenetd in the user file + the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file */ } @@ -901,9 +921,22 @@ __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s) * @{ */ +/** + * @brief DMA I2S transmit receive process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + HAL_I2SEx_TxRxHalfCpltCallback(hi2s); +} + /** * @brief DMA I2S transmit receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -964,7 +997,7 @@ static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S communication error callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma) @@ -987,8 +1020,8 @@ static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma) /** * @brief Full-Duplex IT handler transmit function - * @param hi2s: I2S handle - * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned + * @param hi2s I2S handle + * @param i2sUsed indicate if I2Sx or I2Sx_ext is concerned * @retval None */ static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed) @@ -1033,8 +1066,8 @@ static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUse /** * @brief Full-Duplex IT handler receive function - * @param hi2s: I2S handle - * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned + * @param hi2s I2S handle + * @param i2sUsed indicate if I2Sx or I2Sx_ext is concerned * @retval None */ static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed) @@ -1079,11 +1112,11 @@ static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUse /** * @brief This function handles I2S Communication Timeout. - * @param hi2s: I2S handle - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Timeout: Duration of the timeout - * @param i2sUsed: I2S instance reference + * @param hi2s I2S handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the timeout + * @param i2sUsed I2S instance reference * @retval HAL status */ static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.h index 8b28bf1bdd..8b92e2bd0b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention @@ -64,15 +62,15 @@ #define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE)) /** @brief Enable or disable the specified I2SExt peripheral. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE) #define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE) /** @brief Enable or disable the specified I2SExt interrupts. - * @param __HANDLE__: specifies the I2S Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -83,9 +81,9 @@ #define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__)) /** @brief Checks if the specified I2SExt interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. - * @param __INTERRUPT__: specifies the I2S interrupt source to check. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -95,8 +93,8 @@ #define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified I2SExt flag is set or not. - * @param __HANDLE__: specifies the I2S Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the I2S Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2S_FLAG_RXNE: Receive buffer not empty flag * @arg I2S_FLAG_TXE: Transmit buffer empty flag @@ -110,7 +108,7 @@ #define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clears the I2SExt OVR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{ \ @@ -120,7 +118,7 @@ UNUSED(tmpreg_ovr); \ }while(0U) /** @brief Clears the I2SExt UDR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{ \ @@ -153,6 +151,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ uint16_t Size); /* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s); +void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.c index 8aaeb3fede..b9bcd63f82 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_irda.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA SIR ENDEC block (IrDA): @@ -213,7 +211,7 @@ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); /** * @brief Initializes the IRDA mode according to the specified * parameters in the IRDA_InitTypeDef and create the associated handle. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -274,7 +272,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /** * @brief DeInitializes the IRDA peripheral - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -310,7 +308,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) /** * @brief IRDA MSP Init. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -325,7 +323,7 @@ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) /** * @brief IRDA MSP DeInit. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -394,11 +392,11 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) /** * @brief Sends an amount of data in blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Specify timeout value + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -476,11 +474,11 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Specify timeout value + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -562,10 +560,10 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui /** * @brief Send an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -602,10 +600,10 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData /** * @brief Receives an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -646,10 +644,10 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /** * @brief Sends an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -709,10 +707,10 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat /** * @brief Receives an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ @@ -778,7 +776,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /** * @brief Pauses the DMA Transfer. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -815,7 +813,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) /** * @brief Resumes the DMA Transfer. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -850,7 +848,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /** * @brief Stops the DMA Transfer. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -1297,7 +1295,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) /** * @brief This function handles IRDA interrupt request. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1424,7 +1422,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /** * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion). - * @param hirda: IRDA handle. + * @param hirda IRDA handle. * @retval None */ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) @@ -1438,7 +1436,7 @@ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) /** * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion). - * @param hirda: IRDA handle. + * @param hirda IRDA handle. * @retval None */ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) @@ -1586,7 +1584,7 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Tx Transfer complete callbacks. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1601,7 +1599,7 @@ __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Tx Half Transfer completed callbacks. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1616,7 +1614,7 @@ __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Rx Transfer complete callbacks. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1631,7 +1629,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Rx Half Transfer complete callbacks. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1646,7 +1644,7 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief IRDA error callbacks. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1727,7 +1725,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Returns the IRDA state. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL state */ @@ -1742,7 +1740,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) /** * @brief Return the IARDA error code - * @param hirda : pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA. * @retval IRDA Error Code */ @@ -1757,7 +1755,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) /** * @brief DMA IRDA transmit process complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -1784,7 +1782,7 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1797,7 +1795,7 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -1825,7 +1823,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1837,7 +1835,7 @@ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) @@ -1905,7 +1903,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, /** * @brief Send an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -1953,7 +1951,7 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) /** * @brief Wraps up transmission in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -1975,7 +1973,7 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) /** * @brief Receives an amount of data in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -2042,7 +2040,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) /** * @brief Configures the IRDA peripheral. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.h index 7bf65c6bf8..2b09f15901 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_irda.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention @@ -294,7 +292,7 @@ typedef struct */ /** @brief Reset IRDA handle gstate & RxState - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -305,17 +303,17 @@ typedef struct } while(0U) /** @brief Flushs the IRDA DR register - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. */ #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) /** @brief Checks whether the specified IRDA flag is set or not. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg IRDA_FLAG_TXE: Transmit data register empty flag * @arg IRDA_FLAG_TC: Transmission Complete flag @@ -330,10 +328,10 @@ typedef struct #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** @brief Clears the specified IRDA pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg IRDA_FLAG_TC: Transmission Complete flag. * @arg IRDA_FLAG_RXNE: Receive data register not empty flag. @@ -352,7 +350,7 @@ typedef struct #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** @brief Clear the IRDA PE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -365,7 +363,7 @@ typedef struct } while(0U) /** @brief Clear the IRDA FE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -373,7 +371,7 @@ typedef struct #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the IRDA NE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -381,7 +379,7 @@ typedef struct #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the IRDA ORE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -389,7 +387,7 @@ typedef struct #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the IRDA IDLE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -397,10 +395,10 @@ typedef struct #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) /** @brief Enables or disables the specified IRDA interrupt. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __INTERRUPT__: specifies the IRDA interrupt source to check. + * @param __INTERRUPT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt * @arg IRDA_IT_TC: Transmission complete interrupt @@ -418,10 +416,10 @@ typedef struct ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK))) /** @brief Checks whether the specified IRDA interrupt has occurred or not. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __IT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt * @arg IRDA_IT_TC: Transmission complete interrupt @@ -435,19 +433,19 @@ typedef struct (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK)) /** @brief Macro to enable the IRDA's one bit sample method - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Macro to disable the IRDA's one bit sample method - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). * @retval None @@ -455,7 +453,7 @@ typedef struct #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART/USART associated to IRDA Handle - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c index acf623ebcf..672aad1624 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_iwdg.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.h index 3ab2a382ad..1f771a85c1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_iwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.c index 70d36d9bd0..2b6139e70d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_lptim.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief LPTIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Low Power Timer (LPTIM) peripheral: @@ -222,7 +220,7 @@ /** * @brief Initializes the LPTIM according to the specified parameters in the * LPTIM_InitTypeDef and creates the associated handle. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) @@ -315,7 +313,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /** * @brief DeInitializes the LPTIM peripheral. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) @@ -347,7 +345,7 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) /** * @brief Initializes the LPTIM MSP. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) @@ -361,7 +359,7 @@ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) /** * @brief DeInitializes LPTIM MSP. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) @@ -405,10 +403,10 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM PWM generation. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -446,7 +444,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /** * @brief Stops the LPTIM PWM generation. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) @@ -469,10 +467,10 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM PWM generation in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF * @retval HAL status */ @@ -529,7 +527,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /** * @brief Stops the LPTIM PWM generation in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -571,10 +569,10 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM One pulse generation. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -612,7 +610,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /** * @brief Stops the LPTIM One pulse generation. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) @@ -635,10 +633,10 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM One pulse generation in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -695,7 +693,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /** * @brief Stops the LPTIM One pulse generation in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -737,10 +735,10 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM in Set once mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -778,7 +776,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /** * @brief Stops the LPTIM Set once mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) @@ -801,10 +799,10 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM Set once mode in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -861,7 +859,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /** * @brief Stops the LPTIM Set once mode in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -903,8 +901,8 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the Encoder interface. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -955,7 +953,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /** * @brief Stops the Encoder interface. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) @@ -981,8 +979,8 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the Encoder interface in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1040,7 +1038,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /** * @brief Stops the Encoder interface in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -1074,10 +1072,10 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Starts the Timeout function. The first trigger event will start the * timer, any successive trigger event will reset the counter and * the timer restarts. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Timeout : Specifies the TimeOut value to rest the counter. + * @param Timeout Specifies the TimeOut value to rest the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1115,7 +1113,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /** * @brief Stops the Timeout function. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) @@ -1143,10 +1141,10 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Starts the Timeout function in interrupt mode. The first trigger * event will start the timer, any successive trigger event will reset * the counter and the timer restarts. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Timeout : Specifies the TimeOut value to rest the counter. + * @param Timeout Specifies the TimeOut value to rest the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1193,7 +1191,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /** * @brief Stops the Timeout function in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -1228,8 +1226,8 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the Counter mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1269,7 +1267,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /** * @brief Stops the Counter mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) @@ -1292,8 +1290,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the Counter mode in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1345,7 +1343,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /** * @brief Stops the Counter mode in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -1399,7 +1397,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief This function returns the current counter value. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval Counter value. */ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) @@ -1412,7 +1410,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) /** * @brief This function return the current Autoreload (Period) value. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval Autoreload value. */ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) @@ -1425,7 +1423,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) /** * @brief This function return the current Compare (Pulse) value. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval Compare value. */ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) @@ -1457,7 +1455,7 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) /** * @brief This function handles LPTIM interrupt request. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval None */ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) @@ -1550,7 +1548,7 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /** * @brief Compare match callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) @@ -1564,7 +1562,7 @@ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Autoreload match callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) @@ -1578,7 +1576,7 @@ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Trigger detected callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) @@ -1592,7 +1590,7 @@ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Compare write callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) @@ -1606,7 +1604,7 @@ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Autoreload write callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) @@ -1620,7 +1618,7 @@ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Direction counter changed from Down to Up callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) @@ -1634,7 +1632,7 @@ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Direction counter changed from Up to Down callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) @@ -1666,7 +1664,7 @@ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Returns the LPTIM state. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval HAL state */ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.h index 6f2a49b6db..bf71be3f0b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_lptim.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of LPTIM HAL module. ****************************************************************************** * @attention @@ -342,14 +340,14 @@ typedef struct */ /** @brief Reset LPTIM handle state - * @param __HANDLE__: LPTIM handle + * @param __HANDLE__ LPTIM handle * @retval None */ #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) /** * @brief Enable/Disable the LPTIM peripheral. - * @param __HANDLE__: LPTIM handle + * @param __HANDLE__ LPTIM handle * @retval None */ #define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) @@ -357,7 +355,7 @@ typedef struct /** * @brief Starts the LPTIM peripheral in Continuous or in single mode. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) @@ -366,24 +364,24 @@ typedef struct /** * @brief Writes the passed parameter in the Autoreload register. - * @param __HANDLE__: LPTIM handle - * @param __VALUE__ : Autoreload value + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Autoreload value * @retval None */ #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) /** * @brief Writes the passed parameter in the Compare register. - * @param __HANDLE__: LPTIM handle - * @param __VALUE__ : Compare value + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Compare value * @retval None */ #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) /** * @brief Checks whether the specified LPTIM flag is set or not. - * @param __HANDLE__: LPTIM handle - * @param __FLAG__ : LPTIM flag to check + * @param __HANDLE__ LPTIM handle + * @param __FLAG__ LPTIM flag to check * This parameter can be a value of: * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. @@ -398,8 +396,8 @@ typedef struct /** * @brief Clears the specified LPTIM flag. - * @param __HANDLE__: LPTIM handle. - * @param __FLAG__ : LPTIM flag to clear. + * @param __HANDLE__ LPTIM handle. + * @param __FLAG__ LPTIM flag to clear. * This parameter can be a value of: * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. @@ -414,8 +412,8 @@ typedef struct /** * @brief Enable the specified LPTIM interrupt. - * @param __HANDLE__ : LPTIM handle. - * @param __INTERRUPT__ : LPTIM interrupt to set. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -430,8 +428,8 @@ typedef struct /** * @brief Disable the specified LPTIM interrupt. - * @param __HANDLE__ : LPTIM handle. - * @param __INTERRUPT__ : LPTIM interrupt to set. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -446,8 +444,8 @@ typedef struct /** * @brief Checks whether the specified LPTIM interrupt is set or not. - * @param __HANDLE__ : LPTIM handle. - * @param __INTERRUPT__ : LPTIM interrupt to check. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to check. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -462,8 +460,8 @@ typedef struct #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief LPTIM Option Register - * @param __HANDLE__: LPTIM handle - * @param __VALUE__: This parameter can be a value of : + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ This parameter can be a value of : * @arg LPTIM_OP_PAD_AF * @arg LPTIM_OP_PAD_PA4 * @arg LPTIM_OP_PAD_PB9 diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.c index 14abe8b1c3..9a13148319 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief LTDC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LTDC peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.h index e18a99df05..59dc0de81f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of LTDC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.c index d9eeab916a..0e894cd50c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief LTDC Extension HAL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.h index 2485639548..1087ac9c03 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of LTDC HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.c index 6b4c063d60..d7c1f59a16 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_mmc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief MMC card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (MMC) peripheral: @@ -299,7 +297,7 @@ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); /** * @brief Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle. - * @param hmmc: Pointer to the MMC handle + * @param hmmc Pointer to the MMC handle * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) @@ -346,7 +344,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) /** * @brief Initializes the MMC Card. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @note This function initializes the MMC card. It could be used when a card re-initialization is needed. * @retval HAL status @@ -403,7 +401,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /** * @brief De-Initializes the MMC card. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) @@ -434,7 +432,7 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) /** * @brief Initializes the MMC MSP. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval None */ __weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) @@ -449,7 +447,7 @@ __weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) /** * @brief De-Initialize MMC MSP. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval None */ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) @@ -486,11 +484,11 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) * is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_MMC_GetCardState(). - * @param hmmc: Pointer to MMC handle - * @param pData: pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of MMC blocks to read - * @param Timeout: Specify timeout value + * @param hmmc Pointer to MMC handle + * @param pData pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of MMC blocks to read + * @param Timeout Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) @@ -674,11 +672,11 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui * transfer is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_MMC_GetCardState(). - * @param hmmc: Pointer to MMC handle - * @param pData: pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of MMC blocks to write - * @param Timeout: Specify timeout value + * @param hmmc Pointer to MMC handle + * @param pData pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of MMC blocks to write + * @param Timeout Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) @@ -721,7 +719,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -745,7 +743,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -780,7 +778,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_TIMEOUT; @@ -795,7 +793,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -849,10 +847,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u * HAL_MMC_GetCardState(). * @note You could also check the IT transfer process through the MMC Rx * interrupt event. - * @param hmmc: Pointer to MMC handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -906,7 +904,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -951,10 +949,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, * HAL_MMC_GetCardState(). * @note You could also check the IT transfer process through the MMC Tx * interrupt event. - * @param hmmc: Pointer to MMC handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1000,7 +998,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -1024,7 +1022,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -1054,10 +1052,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData * HAL_MMC_GetCardState(). * @note You could also check the DMA transfer process through the MMC Rx * interrupt event. - * @param hmmc: Pointer MMC handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. + * @param hmmc Pointer MMC handle + * @param pData Pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1127,7 +1125,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -1151,7 +1149,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -1172,10 +1170,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData * HAL_MMC_GetCardState(). * @note You could also check the DMA transfer process through the MMC Tx * interrupt event. - * @param hmmc: Pointer to MMC handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1231,7 +1229,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -1255,7 +1253,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -1288,9 +1286,9 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat * @brief Erases the specified memory area of the given MMC card. * @note This API should be followed by a check on the card state through * HAL_MMC_GetCardState(). - * @param hmmc: Pointer to MMC handle - * @param BlockStartAdd: Start Block address - * @param BlockEndAdd: End Block address + * @param hmmc Pointer to MMC handle + * @param BlockStartAdd Start Block address + * @param BlockEndAdd End Block address * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd) @@ -1386,7 +1384,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, /** * @brief This function handles MMC card interrupt request. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval None */ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) @@ -1608,7 +1606,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) /** * @brief return the MMC state - * @param hmmc: Pointer to mmc handle + * @param hmmc Pointer to mmc handle * @retval HAL state */ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) @@ -1618,7 +1616,7 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) /** * @brief Return the MMC error code -* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains +* @param hmmc Pointer to a MMC_HandleTypeDef structure that contains * the configuration information. * @retval MMC Error Code */ @@ -1629,7 +1627,7 @@ uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) /** * @brief Tx Transfer completed callbacks - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval None */ __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) @@ -1644,7 +1642,7 @@ uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) /** * @brief Rx Transfer completed callbacks - * @param hmmc: Pointer MMC handle + * @param hmmc Pointer MMC handle * @retval None */ __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) @@ -1659,7 +1657,7 @@ __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) /** * @brief MMC error callbacks - * @param hmmc: Pointer MMC handle + * @param hmmc Pointer MMC handle * @retval None */ __weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) @@ -1674,7 +1672,7 @@ __weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) /** * @brief MMC Abort callbacks - * @param hmmc: Pointer MMC handle + * @param hmmc Pointer MMC handle * @retval None */ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) @@ -1710,8 +1708,8 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) /** * @brief Returns information the information of the card which are stored on * the CID register. - * @param hmmc: Pointer to MMC handle - * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that + * @param hmmc Pointer to MMC handle + * @param pCID Pointer to a HAL_MMC_CIDTypedef structure that * contains all CID register parameters * @retval HAL status */ @@ -1791,8 +1789,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTyp /** * @brief Returns information the information of the card which are stored on * the CSD register. - * @param hmmc: Pointer to MMC handle - * @param pCSD: Pointer to a HAL_MMC_CardInfoTypeDef structure that + * @param hmmc Pointer to MMC handle + * @param pCSD Pointer to a HAL_MMC_CardInfoTypeDef structure that * contains all CSD register parameters * @retval HAL status */ @@ -1905,8 +1903,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp /** * @brief Gets the MMC card info. - * @param hmmc: Pointer to MMC handle - * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that + * @param hmmc Pointer to MMC handle + * @param pCardInfo Pointer to the HAL_MMC_CardInfoTypeDef structure that * will contain the MMC card status information * @retval HAL status */ @@ -1926,8 +1924,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT /** * @brief Enables wide bus operation for the requested card if supported by * card. - * @param hmmc: Pointer to MMC handle - * @param WideMode: Specifies the MMC card wide bus mode + * @param hmmc Pointer to MMC handle + * @param WideMode Specifies the MMC card wide bus mode * This parameter can be one of the following values: * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer @@ -2061,7 +2059,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 /** * @brief Gets the current mmc card data state. - * @param hmmc: pointer to MMC handle + * @param hmmc pointer to MMC handle * @retval Card state */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) @@ -2083,7 +2081,7 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) /** * @brief Abort the current transfer and disable the MMC. - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains * the configuration information for MMC module. * @retval HAL status */ @@ -2130,7 +2128,7 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) /** * @brief Abort the current transfer and disable the MMC (IT mode). - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains * the configuration information for MMC module. * @retval HAL status */ @@ -2207,7 +2205,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) /** * @brief DMA MMC transmit process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -2220,7 +2218,7 @@ static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC receive process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -2253,7 +2251,7 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC communication error callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void MMC_DMAError(DMA_HandleTypeDef *hdma) @@ -2285,7 +2283,7 @@ static void MMC_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC Tx Abort callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) @@ -2322,7 +2320,7 @@ static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC Rx Abort callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) @@ -2360,7 +2358,7 @@ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) /** * @brief Initializes the mmc card. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval MMC Card error state */ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) @@ -2441,7 +2439,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) * @brief Enquires cards about their operating voltage and configures clock * controls and stores MMC information that will be needed in future * in the MMC handle. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval error state */ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) @@ -2495,7 +2493,7 @@ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) /** * @brief Turns the SDIO output signals off. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval HAL status */ static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc) @@ -2508,8 +2506,8 @@ static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc) /** * @brief Returns the current card's status. - * @param hmmc: Pointer to MMC handle - * @param pCardStatus: pointer to the buffer that will contain the MMC card + * @param hmmc Pointer to MMC handle + * @param pCardStatus pointer to the buffer that will contain the MMC card * status (Card Status register) * @retval error state */ @@ -2537,7 +2535,7 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) /** * @brief Wrap up reading in non-blocking mode. - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains * the configuration information. * @retval HAL status */ @@ -2561,7 +2559,7 @@ static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc) /** * @brief Wrap up writing in non-blocking mode. - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains * the configuration information. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.h index c64190f6ab..6ad752cc5e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_mmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of MMC HAL module. ****************************************************************************** * @attention @@ -393,8 +391,8 @@ typedef struct /** * @brief Enable the MMC device interrupt. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -424,8 +422,8 @@ typedef struct /** * @brief Disable the MMC device interrupt. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -455,8 +453,8 @@ typedef struct /** * @brief Check whether the specified MMC flag is set or not. - * @param __HANDLE__: MMC Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ MMC Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -486,8 +484,8 @@ typedef struct /** * @brief Clear the MMC's pending flags. - * @param __HANDLE__: MMC Handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ MMC Handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -506,8 +504,8 @@ typedef struct /** * @brief Check whether the specified MMC interrupt has occurred or not. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -537,8 +535,8 @@ typedef struct /** * @brief Clear the MMC's interrupt pending bits. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.c index bb33b0da46..0c51d2bc0c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_nand.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. @@ -146,10 +144,10 @@ /** * @brief Perform NAND memory Initialization sequence - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param ComSpace_Timing: pointer to Common space timing structure - * @param AttSpace_Timing: pointer to Attribute space timing structure + * @param ComSpace_Timing pointer to Common space timing structure + * @param AttSpace_Timing pointer to Attribute space timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) @@ -188,7 +186,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT /** * @brief Perform NAND memory De-Initialization sequence - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -211,7 +209,7 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) /** * @brief NAND MSP Init - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -226,7 +224,7 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) /** * @brief NAND MSP DeInit - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -242,7 +240,7 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) /** * @brief This function handles NAND device interrupt request. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -291,7 +289,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) /** * @brief NAND interrupt feature callback - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -325,9 +323,9 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) /** * @brief Read the NAND memory electronic signature - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pNAND_ID: NAND ID structure + * @param pNAND_ID NAND ID structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) @@ -400,7 +398,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN /** * @brief NAND memory reset - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -446,9 +444,9 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) /** * @brief Configure the device: Enter the physical parameters of the device - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure + * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) @@ -466,11 +464,11 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC /** * @brief Read Page(s) from NAND memory block (8-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to destination read buffer - * @param NumPageToRead : number of pages to read from block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to destination read buffer + * @param NumPageToRead number of pages to read from block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) @@ -598,11 +596,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT /** * @brief Read Page(s) from NAND memory block (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned - * @param NumPageToRead : number of pages to read from block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned + * @param NumPageToRead number of pages to read from block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) @@ -729,11 +727,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address /** * @brief Write Page(s) to NAND memory block (8-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write - * @param NumPageToWrite : number of pages to write to block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumPageToWrite number of pages to write to block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) @@ -857,11 +855,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address /** * @brief Write Page(s) to NAND memory block (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned - * @param NumPageToWrite : number of pages to write to block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned + * @param NumPageToWrite number of pages to write to block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) @@ -984,11 +982,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres /** * @brief Read Spare area(s) from NAND memory - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write - * @param NumSpareAreaToRead: Number of spare area to read + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) @@ -1120,11 +1118,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add /** * @brief Read Spare area(s) from NAND memory (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned. - * @param NumSpareAreaToRead: Number of spare area to read + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) @@ -1256,11 +1254,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad /** * @brief Write Spare area(s) to NAND memory - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write - * @param NumSpareAreaTowrite : number of spare areas to write to block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) @@ -1388,11 +1386,11 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad /** * @brief Write Spare area(s) to NAND memory (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned. - * @param NumSpareAreaTowrite : number of spare areas to write to block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) @@ -1520,9 +1518,9 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A /** * @brief NAND memory Block erase - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure + * @param pAddress pointer to NAND address structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) @@ -1587,7 +1585,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy /** * @brief NAND memory read status - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval NAND status */ @@ -1627,9 +1625,9 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) /** * @brief Increment the NAND memory address - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure + * @param pAddress pointer to NAND address structure * @retval The new status of the increment address operation. It can be: * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address @@ -1683,7 +1681,7 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA /** * @brief Enables dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -1709,7 +1707,7 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) /** * @brief Disables dynamically FMC_NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -1735,10 +1733,10 @@ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) /** * @brief Disables dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param ECCval: pointer to ECC value - * @param Timeout: maximum timeout to wait + * @param ECCval pointer to ECC value + * @param Timeout maximum timeout to wait * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) @@ -1785,7 +1783,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, /** * @brief return the NAND state - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL state */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.h index ab07f3fed3..a0a24560b5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_nand.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention @@ -166,7 +164,7 @@ typedef struct */ /** @brief Reset NAND handle state - * @param __HANDLE__: specifies the NAND handle. + * @param __HANDLE__ specifies the NAND handle. * @retval None */ #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) @@ -299,8 +297,8 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); /** * @brief NAND memory address computation. - * @param __ADDRESS__: NAND memory address. - * @param __HANDLE__: NAND handle. + * @param __ADDRESS__ NAND memory address. + * @param __HANDLE__ NAND handle. * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ @@ -308,14 +306,14 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); /** * @brief NAND memory Column address computation. - * @param __HANDLE__: NAND handle. + * @param __HANDLE__ NAND handle. * @retval NAND Raw address value */ #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) /** * @brief NAND memory address cycling. - * @param __ADDRESS__: NAND memory address. + * @param __ADDRESS__ NAND memory address. * @retval NAND address cycling value. */ #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ @@ -325,7 +323,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); /** * @brief NAND memory Columns cycling. - * @param __ADDRESS__: NAND memory address. + * @param __ADDRESS__ NAND memory address. * @retval NAND Column address cycling value. */ #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.c index 6aa51e080d..324c42b660 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_nor.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. @@ -97,7 +95,7 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F413xx) || defined(STM32F423xx) + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -173,10 +171,10 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; /** * @brief Perform the NOR memory Initialization sequence - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Timing: pointer to NOR control timing structure - * @param ExtTiming: pointer to NOR extended mode timing structure + * @param Timing pointer to NOR control timing structure + * @param ExtTiming pointer to NOR extended mode timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) @@ -225,7 +223,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe /** * @brief Perform NOR memory De-Initialization sequence - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -248,7 +246,7 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) /** * @brief NOR MSP Init - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval None */ @@ -263,7 +261,7 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) /** * @brief NOR MSP DeInit - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval None */ @@ -278,9 +276,9 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) /** * @brief NOR MSP Wait for Ready/Busy signal - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Timeout: Maximum timeout value + * @param Timeout Maximum timeout value * @retval None */ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) @@ -314,9 +312,9 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) /** * @brief Read NOR flash IDs - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pNOR_ID : pointer to NOR ID structure + * @param pNOR_ID pointer to NOR ID structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) @@ -375,7 +373,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I /** * @brief Returns the NOR memory to Read mode. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -423,10 +421,10 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) /** * @brief Read data from NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pAddress: pointer to Device address - * @param pData : pointer to read data + * @param pAddress pointer to Device address + * @param pData pointer to read data * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) @@ -482,10 +480,10 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint /** * @brief Program data to NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pAddress: Device address - * @param pData : pointer to the data to write + * @param pAddress Device address + * @param pData pointer to the data to write * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) @@ -541,11 +539,11 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /** * @brief Reads a half-word buffer from the NOR memory. - * @param hnor: pointer to the NOR handle - * @param uwAddress: NOR memory internal address to read from. - * @param pData: pointer to the buffer that receives the data read from the + * @param hnor pointer to the NOR handle + * @param uwAddress NOR memory internal address to read from. + * @param pData pointer to the buffer that receives the data read from the * NOR memory. - * @param uwBufferSize : number of Half word to read. + * @param uwBufferSize number of Half word to read. * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) @@ -607,10 +605,10 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress /** * @brief Writes a half-word buffer to the NOR memory. This function must be used only with S29GL128P NOR memory. - * @param hnor: pointer to the NOR handle - * @param uwAddress: NOR memory internal start write address - * @param pData: pointer to source data buffer. - * @param uwBufferSize: Size of the buffer to write + * @param hnor pointer to the NOR handle + * @param uwAddress NOR memory internal start write address + * @param pData pointer to source data buffer. + * @param uwBufferSize Size of the buffer to write * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) @@ -687,10 +685,10 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /** * @brief Erase the specified block of the NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param BlockAddress : Block to erase address - * @param Address: Device address + * @param BlockAddress Block to erase address + * @param Address Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) @@ -747,9 +745,9 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /** * @brief Erase the entire NOR chip. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Address : Device address + * @param Address Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) @@ -808,9 +806,9 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) /** * @brief Read NOR flash CFI IDs - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pNOR_CFI : pointer to NOR CFI IDs structure + * @param pNOR_CFI pointer to NOR CFI IDs structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) @@ -886,7 +884,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR /** * @brief Enables dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -909,7 +907,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) /** * @brief Disables dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -954,7 +952,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) /** * @brief return the NOR controller state - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval NOR controller state */ @@ -965,10 +963,10 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) /** * @brief Returns the NOR operation status. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Address: Device address - * @param Timeout: NOR programming Timeout + * @param Address Device address + * @param Timeout NOR programming Timeout * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR * or HAL_NOR_STATUS_TIMEOUT */ @@ -1038,7 +1036,8 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ - STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */ + STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx ||\ + STM32F423xx */ #endif /* HAL_NOR_MODULE_ENABLED */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.h index d1916fe286..a7c16dfa45 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_nor.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention @@ -45,9 +43,9 @@ /* Includes ------------------------------------------------------------------*/ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F413xx) || defined(STM32F423xx) + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) @@ -65,7 +63,7 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F413xx) || defined(STM32F423xx) + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) /* Exported typedef ----------------------------------------------------------*/ /** @defgroup NOR_Exported_Types NOR Exported Types @@ -156,7 +154,7 @@ typedef struct * @{ */ /** @brief Reset NOR handle state - * @param __HANDLE__: specifies the NOR handle. + * @param __HANDLE__ specifies the NOR handle. * @retval None */ #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) @@ -265,9 +263,9 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres */ /** * @brief NOR memory address shifting. - * @param __NOR_ADDRESS__: NOR base address - * @param NOR_MEMORY_WIDTH: NOR memory width - * @param ADDRESS: NOR memory address + * @param __NOR_ADDRESS__ NOR base address + * @param NOR_MEMORY_WIDTH NOR memory width + * @param ADDRESS NOR memory address * @retval NOR shifted address value */ #define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\ @@ -275,8 +273,8 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @brief NOR memory write data to specified address. - * @param ADDRESS: NOR memory address - * @param DATA: Data to write + * @param ADDRESS NOR memory address + * @param DATA Data to write * @retval None */ #define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA)) @@ -287,7 +285,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F413xx || STM32F423xx */ + STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.c index e3edb7e161..661411349f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pccard.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief PCCARD HAL module driver. * This file provides a generic firmware to drive PCCARD memories mounted * as external device. @@ -133,11 +131,11 @@ /** * @brief Perform the PCCARD memory Initialization sequence - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. - * @param ComSpaceTiming: Common space timing structure - * @param AttSpaceTiming: Attribute space timing structure - * @param IOSpaceTiming: IO space timing structure + * @param ComSpaceTiming Common space timing structure + * @param AttSpaceTiming Attribute space timing structure + * @param IOSpaceTiming IO space timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) @@ -183,7 +181,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti /** * @brief Perform the PCCARD memory De-initialization sequence - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval HAL status */ @@ -206,7 +204,7 @@ HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard) /** * @brief PCCARD MSP Init - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval None */ @@ -221,7 +219,7 @@ __weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard) /** * @brief PCCARD MSP DeInit - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval None */ @@ -254,10 +252,10 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard) /** * @brief Read Compact Flash's ID. - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. - * @param CompactFlash_ID: Compact flash ID structure. - * @param pStatus: pointer to compact flash status + * @param CompactFlash_ID Compact flash ID structure. + * @param pStatus pointer to compact flash status * @retval HAL status * */ @@ -317,11 +315,11 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp /** * @brief Read sector from PCCARD memory - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. - * @param pBuffer: pointer to destination read buffer - * @param SectorAddress: Sector address to read - * @param pStatus: pointer to PCCARD status + * @param pBuffer pointer to destination read buffer + * @param SectorAddress Sector address to read + * @param pStatus pointer to PCCARD status * @retval HAL status */ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) @@ -393,11 +391,11 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t /** * @brief Write sector to PCCARD memory - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. - * @param pBuffer: pointer to source write buffer - * @param SectorAddress: Sector address to write - * @param pStatus: pointer to PCCARD status + * @param pBuffer pointer to source write buffer + * @param SectorAddress Sector address to write + * @param pStatus pointer to PCCARD status * @retval HAL status */ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) @@ -467,10 +465,10 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ /** * @brief Erase sector from PCCARD memory - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. - * @param SectorAddress: Sector address to erase - * @param pStatus: pointer to PCCARD status + * @param SectorAddress Sector address to erase + * @param pStatus pointer to PCCARD status * @retval HAL status */ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus) @@ -526,7 +524,7 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16 /** * @brief Reset the PCCARD memory - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval HAL status */ @@ -564,7 +562,7 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard) /** * @brief This function handles PCCARD device interrupt request. - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval HAL status */ @@ -613,7 +611,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) /** * @brief PCCARD interrupt feature callback - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval None */ @@ -647,7 +645,7 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard) /** * @brief return the PCCARD controller state - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval HAL state */ @@ -658,7 +656,7 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard) /** * @brief Get the compact flash memory status - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval New status of the PCCARD operation. This parameter can be: * - CompactFlash_TIMEOUT_ERROR: when the previous operation generate @@ -694,7 +692,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) /** * @brief Reads the Compact Flash memory status using the Read status command - * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains + * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval The status of the Compact Flash memory. This parameter can be: * - CompactFlash_BUSY: when memory is busy diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.h index 0b47429d39..d8f2f4746f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pccard.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PCCARD HAL module. ****************************************************************************** * @attention @@ -111,7 +109,7 @@ typedef struct * @{ */ /** @brief Reset PCCARD handle state - * @param __HANDLE__: specifies the PCCARD handle. + * @param __HANDLE__ specifies the PCCARD handle. * @retval None */ #define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.c index e3a683c7e1..44e191553c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -133,7 +131,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t /** * @brief Initializes the PCD according to the specified * parameters in the PCD_InitTypeDef and initialize the associated handle. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) @@ -148,6 +146,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); +/* MBED */ if(hpcd->State == HAL_PCD_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -159,6 +158,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) } hpcd->State = HAL_PCD_STATE_BUSY; +/* MBED */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); @@ -196,6 +196,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->Instance->DIEPTXF[i] = 0U; } + /* Init Device */ USB_DevInit(hpcd->Instance, hpcd->Init); @@ -223,7 +224,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes the PCD peripheral. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) @@ -249,7 +250,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) /** * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) @@ -263,7 +264,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) @@ -296,36 +297,44 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) /** * @brief Start The USB OTG Device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { +/* MBED */ //__HAL_LOCK(hpcd); +/* MBED */ USB_DevConnect (hpcd->Instance); __HAL_PCD_ENABLE(hpcd); +/* MBED */ //__HAL_UNLOCK(hpcd); +/* MBED */ return HAL_OK; } /** * @brief Stop The USB OTG Device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) { +/* MBED */ //__HAL_LOCK(hpcd); +/* MBED */ __HAL_PCD_DISABLE(hpcd); USB_StopDevice(hpcd->Instance); USB_DevDisconnect(hpcd->Instance); +/* MBED */ //__HAL_UNLOCK(hpcd); +/* MBED */ return HAL_OK; } /** * @brief Handles PCD interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) @@ -426,8 +435,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { fifoemptymsk = 0x1U << epnum; - + +/* MBED */ atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK,fifoemptymsk); +/* MBED */ CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); @@ -723,8 +734,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Data OUT stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -739,8 +750,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Data IN stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -754,7 +765,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } /** * @brief Setup stage callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) @@ -768,7 +779,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief USB Start Of Frame callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) @@ -782,7 +793,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief USB Reset callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) @@ -796,7 +807,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Suspend event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) @@ -810,7 +821,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Resume event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) @@ -824,8 +835,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Incomplete ISO OUT callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -840,8 +851,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Incomplete ISO IN callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -856,7 +867,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Connection event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) @@ -870,7 +881,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Disconnection event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) @@ -903,7 +914,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Connect the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) @@ -916,7 +927,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) /** * @brief Disconnect the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) @@ -929,8 +940,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) /** * @brief Set the USB Device address. - * @param hpcd: PCD handle - * @param address: new device address + * @param hpcd PCD handle + * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) @@ -942,10 +953,10 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) } /** * @brief Open and configure an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packet size - * @param ep_type: endpoint type + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) @@ -953,17 +964,17 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint HAL_StatusTypeDef ret = HAL_OK; USB_OTG_EPTypeDef *ep; - if ((ep_addr & 0x80U) == 0x80U) + if ((ep_addr & 0x80) == 0x80) { - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + ep = &hpcd->IN_ep[ep_addr & 0x7F]; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; } - ep->num = ep_addr & 0x7FU; + ep->num = ep_addr & 0x7F; - ep->is_in = (0x80U & ep_addr) != 0U; + ep->is_in = (0x80 & ep_addr) != 0; ep->maxpacket = ep_mps; ep->type = ep_type; if (ep->is_in) @@ -977,71 +988,77 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint ep->data_pid_start = 0U; } +/* MBED */ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]); USB_ActivateEndpoint(hpcd->Instance , ep); __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]); +/* MBED */ return ret; } /** * @brief Deactivate an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { USB_OTG_EPTypeDef *ep; - if ((ep_addr & 0x80U) == 0x80U) + if ((ep_addr & 0x80) == 0x80) { - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + ep = &hpcd->IN_ep[ep_addr & 0x7F]; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; } - ep->num = ep_addr & 0x7FU; + ep->num = ep_addr & 0x7F; - ep->is_in = (0x80U & ep_addr) != 0U; + ep->is_in = (0x80 & ep_addr) != 0; +/* MBED */ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]); USB_DeactivateEndpoint(hpcd->Instance , ep); __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]); +/* MBED */ return HAL_OK; } /** * @brief Receive an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { USB_OTG_EPTypeDef *ep; - ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; + ep = &hpcd->OUT_ep[ep_addr & 0x7F]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; ep->xfer_count = 0U; ep->is_in = 0U; - ep->num = ep_addr & 0x7FU; + ep->num = ep_addr & 0x7F; if (hpcd->Init.dma_enable == 1U) { ep->dma_addr = (uint32_t)pBuf; } +/* MBED */ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]); +/* MBED */ - if ((ep_addr & 0x7FU) == 0U) + if ((ep_addr & 0x7F) == 0) { USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); } @@ -1049,50 +1066,56 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u { USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); } +/* MBED */ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]); +/* MBED */ return HAL_OK; } /** * @brief Get Received Data Size. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval Data Size */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { +/* MBED */ return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count; +/* MBED */ } /** * @brief Send an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { USB_OTG_EPTypeDef *ep; - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + ep = &hpcd->IN_ep[ep_addr & 0x7F]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; ep->xfer_count = 0U; ep->is_in = 1U; - ep->num = ep_addr & 0x7FU; + ep->num = ep_addr & 0x7F; if (hpcd->Init.dma_enable == 1U) { ep->dma_addr = (uint32_t)pBuf; } - + +/* MBED */ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]); - - if ((ep_addr & 0x7FU) == 0U) +/* MBED */ + + if ((ep_addr & 0x7F) == 0) { USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); } @@ -1100,25 +1123,27 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, { USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable); } - + +/* MBED */ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]); - +/* MBED */ + return HAL_OK; } /** * @brief Set a STALL condition over an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { USB_OTG_EPTypeDef *ep; - if ((0x80U & ep_addr) == 0x80U) + if ((0x80 & ep_addr) == 0x80) { - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + ep = &hpcd->IN_ep[ep_addr & 0x7F]; } else { @@ -1126,34 +1151,38 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } ep->is_stall = 1U; - ep->num = ep_addr & 0x7FU; - ep->is_in = ((ep_addr & 0x80U) == 0x80U); + ep->num = ep_addr & 0x7F; + ep->is_in = ((ep_addr & 0x80) == 0x80); +/* MBED */ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]); +/* MBED */ USB_EPSetStall(hpcd->Instance , ep); - if((ep_addr & 0x7FU) == 0U) + if((ep_addr & 0x7F) == 0) { USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); } +/* MBED */ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]); +/* MBED */ return HAL_OK; } /** * @brief Clear a STALL condition over in an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { USB_OTG_EPTypeDef *ep; - if ((0x80U & ep_addr) == 0x80U) + if ((0x80 & ep_addr) == 0x80) { - ep = &hpcd->IN_ep[ep_addr & 0x7FU]; + ep = &hpcd->IN_ep[ep_addr & 0x7F]; } else { @@ -1161,42 +1190,49 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } ep->is_stall = 0U; - ep->num = ep_addr & 0x7FU; - ep->is_in = ((ep_addr & 0x80U) == 0x80U); - + ep->num = ep_addr & 0x7F; + ep->is_in = ((ep_addr & 0x80) == 0x80); + +/* MBED */ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]); USB_EPClearStall(hpcd->Instance , ep); __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]); - +/* MBED */ + return HAL_OK; } /** * @brief Flush an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { +/* MBED */ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]); - if ((ep_addr & 0x80U) == 0x80U) +/* MBED */ + + if ((ep_addr & 0x80) == 0x80) { - USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU); + USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); } else { USB_FlushRxFifo(hpcd->Instance); } - + +/* MBED */ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]); - +/* MBED */ + return HAL_OK; } /** * @brief Activate remote wakeup signalling. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) @@ -1213,7 +1249,7 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief De-activate remote wakeup signalling. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) @@ -1245,7 +1281,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief Return the PCD handle state. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL state */ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) @@ -1267,8 +1303,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) /** * @brief Check FIFO for the next packet to be loaded. - * @param hpcd: PCD handle - * @param epnum : endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) @@ -1312,7 +1348,9 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t if(len <= 0U) { fifoemptymsk = 0x1U << epnum; +/* MBED */ atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk); +/* MBED */ } return HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.h index 62dcc7f9c1..d5b8e1605b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -94,10 +92,12 @@ typedef USB_OTG_EPTypeDef PCD_EPTypeDef ; * @brief PCD Handle Structure definition */ +/* MBED */ typedef struct { HAL_LockTypeDef Lock; } PCD_EPLockDef; +/* MBED */ typedef struct { @@ -106,7 +106,9 @@ typedef struct PCD_EPTypeDef IN_ep[16U]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[16U]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ +/* MBED */ PCD_EPLockDef EPLock[15]; /*!< PCD endpoint peripheral status */ +/* MBED */ __IO PCD_StateTypeDef State; /*!< PCD communication state */ uint32_t Setup[12U]; /*!< Setup packet buffer */ #ifdef USB_OTG_GLPMCFG_LPMEN diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.c index 401fcfc231..f7d754dbc7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -83,9 +81,9 @@ /** * @brief Set Tx FIFO - * @param hpcd: PCD handle - * @param fifo: The number of Tx fifo - * @param size: Fifo size + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) @@ -126,8 +124,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin /** * @brief Set Rx FIFO - * @param hpcd: PCD handle - * @param size: Size of Rx fifo + * @param hpcd PCD handle + * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) @@ -141,7 +139,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Activate LPM feature - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) @@ -158,7 +156,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) /** * @brief Deactivate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) @@ -174,8 +172,8 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) /** * @brief Send LPM message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) @@ -189,7 +187,7 @@ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef m #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief HAL_PCDEx_BCD_VBUSDetect : handle BatteryCharging Process - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) @@ -260,7 +258,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /** * @brief HAL_PCDEx_ActivateBCD : active BatteryCharging feature - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) @@ -275,7 +273,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) /** * @brief HAL_PCDEx_DeActivateBCD : de-active BatteryCharging feature - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) @@ -288,8 +286,8 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) /** * @brief HAL_PCDEx_BatteryCharging_Callback : Send BatteryCharging message to user layer - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.h index a41478be7d..f0973c6705 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c index ec27001bb8..dffb78e25c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -168,7 +166,7 @@ void HAL_PWR_DisableBkUpAccess(void) forced in input pull-down configuration and is active on rising edges. (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 - (++) For STM32F410xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 + (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 *** Low Power modes configuration *** ===================================== @@ -260,7 +258,7 @@ void HAL_PWR_DisableBkUpAccess(void) /** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration * information for the PVD. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each @@ -326,11 +324,11 @@ void HAL_PWR_DisablePVD(void) /** * @brief Enables the Wake-up PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices - * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx devices + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) @@ -344,11 +342,11 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) /** * @brief Disables the Wake-up PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices - * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) @@ -368,13 +366,13 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) * @note In Sleep mode, the systick is stopped to avoid exit from this mode with * systick interrupt when used as time base for Timeout * - * @param Regulator: Specifies the regulator state in SLEEP mode. + * @param Regulator Specifies the regulator state in SLEEP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON * @note This parameter is not used for the STM32F4 family and is kept as parameter * just to maintain compatibility with the lower power families. - * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction. + * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction @@ -413,11 +411,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in Stop mode. + * @param Regulator Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. + * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h index 24c5034eed..c6e33f6a9e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -169,7 +167,7 @@ typedef struct */ /** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received from the WKUP pin or from the RTC alarm (Alarm A @@ -192,7 +190,7 @@ typedef struct #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag @@ -375,16 +373,16 @@ void HAL_PWR_DisableSEVOnPend(void); */ /* --- CR Register ---*/ /* Alias word address of DBP bit */ -#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)) /* Alias word address of PVDE bit */ -#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)) -/* Alias word address of PMODE bit */ -#define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE) -#define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U)) +/* Alias word address of VOS bit */ +#define VOS_BIT_NUMBER PWR_CR_VOS_Pos +#define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U)) /** * @} */ @@ -394,7 +392,7 @@ void HAL_PWR_DisableSEVOnPend(void); */ /* --- CSR Register ---*/ /* Alias word address of EWUP bit */ -#define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP) +#define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.c index 113cea58eb..b6d48b9f6b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: @@ -236,7 +234,7 @@ uint32_t HAL_PWREx_GetVoltageRange(void) #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /** * @brief Configures the main internal regulator output voltage. - * @param VoltageScaling: specifies the regulator output voltage to achieve + * @param VoltageScaling specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, @@ -281,7 +279,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Configures the main internal regulator output voltage. - * @param VoltageScaling: specifies the regulator output voltage to achieve + * @param VoltageScaling specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, @@ -561,13 +559,13 @@ HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. * - * @param Regulator: specifies the regulator state in STOP mode. + * @param Regulator specifies the regulator state in STOP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode - * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.h index 7abc24126d..16186195cc 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention @@ -126,7 +124,7 @@ #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) /** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve + * @param __REGULATOR__ specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption when the device does * not operate at the maximum frequency (refer to the datasheets for more details). * This parameter can be one of the following values: @@ -143,7 +141,7 @@ } while(0U) #else /** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve + * @param __REGULATOR__ specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption when the device does * not operate at the maximum frequency (refer to the datasheets for more details). * This parameter can be one of the following values: @@ -190,7 +188,7 @@ /** @brief Check PWR flag is set or not. * @note These macros can be used only for STM32F42xx/STM3243xx devices. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode * is ready @@ -269,23 +267,23 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /* ------------- PWR registers bit address in the alias region ---------------*/ /* --- CR Register ---*/ /* Alias word address of FPDS bit */ -#define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS) +#define FPDS_BIT_NUMBER PWR_CR_FPDS_Pos #define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U)) /* Alias word address of ODEN bit */ -#define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN) +#define ODEN_BIT_NUMBER PWR_CR_ODEN_Pos #define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U)) /* Alias word address of ODSWEN bit */ -#define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN) +#define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos #define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U)) /* Alias word address of MRLVDS bit */ -#define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS) +#define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos #define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U)) /* Alias word address of LPLVDS bit */ -#define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS) +#define LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos #define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U)) /** @@ -297,12 +295,12 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t */ /* --- CSR Register ---*/ /* Alias word address of BRE bit */ -#define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE) +#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos #define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U)) #if defined(STM32F469xx) || defined(STM32F479xx) /* Alias word address of WUPP bit */ -#define WUPP_BIT_NUMBER POSITION_VAL(PWR_CSR_WUPP) +#define WUPP_BIT_NUMBER PWR_CSR_WUPP_Pos #define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U)) #endif /* STM32F469xx || STM32F479xx */ /** diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c index 05f5f8ffd3..9ddade40fa 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_qspi.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief QSPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the QuadSPI interface (QSPI). @@ -248,7 +246,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @brief Initializes the QSPI mode according to the specified parameters * in the QSPI_InitTypeDef and creates the associated handle. - * @param hqspi: qspi handle + * @param hqspi qspi handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) @@ -327,7 +325,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitializes the QSPI peripheral - * @param hqspi: qspi handle + * @param hqspi qspi handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -361,7 +359,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief QSPI MSP Init - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) @@ -376,7 +374,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief QSPI MSP DeInit - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) @@ -415,7 +413,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief This function handles QSPI interrupt request. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None. */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -635,9 +633,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Sets the command configuration. - * @param hqspi: QSPI handle - * @param cmd : structure that contains the command configuration information - * @param Timeout : Time out duration + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param Timeout Time out duration * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -726,8 +724,8 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Sets the command configuration in interrupt mode. - * @param hqspi: QSPI handle - * @param cmd : structure that contains the command configuration information + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -835,9 +833,9 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer - * @param Timeout : Time out duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Time out duration * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -919,9 +917,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer - * @param Timeout : Time out duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Time out duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1005,8 +1003,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1065,8 +1063,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in no-blocking mode with Interrupt - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1129,8 +1127,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Sends an amount of data in non blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1285,8 +1283,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /** * @brief Receives an amount of data in non blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer. + * @param hqspi QSPI handle + * @param pData pointer to data buffer. * @note This function is used only in Indirect Read Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1470,10 +1468,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. - * @param Timeout : Time out duration + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. + * @param Timeout Time out duration * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1571,9 +1569,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1685,9 +1683,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the memory mapped configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1774,7 +1772,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callbacks - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1789,7 +1787,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1804,7 +1802,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1819,7 +1817,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callbacks. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1834,7 +1832,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callbacks. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1849,7 +1847,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Half Transfer completed callbacks. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1864,7 +1862,7 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Half Transfer completed callbacks. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1879,7 +1877,7 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callbacks - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1894,7 +1892,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callbacks - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1909,7 +1907,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callbacks - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -1945,7 +1943,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI handle state. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -1956,7 +1954,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code -* @param hqspi: QSPI handle +* @param hqspi QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -1966,7 +1964,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission -* @param hqspi: QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2019,7 +2017,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi: QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2064,8 +2062,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } /** @brief Set QSPI timeout - * @param hqspi: QSPI handle. - * @param Timeout: Timeout for the QSPI memory access. + * @param hqspi QSPI handle. + * @param Timeout Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2074,8 +2072,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi: QSPI handle. - * @param Threshold: Threshold of the Fifo (value between 1 and 16). + * @param hqspi QSPI handle. + * @param Threshold Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2092,7 +2090,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t /* Configure QSPI FIFO Threshold */ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1U) << POSITION_VAL(QUADSPI_CR_FTHRES))); + ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); } else { @@ -2107,12 +2105,12 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi: QSPI handle. + * @param hqspi QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) { - return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1U); + return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); } /** @@ -2123,7 +2121,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) /** * @brief DMA QSPI receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -2137,7 +2135,7 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) @@ -2151,7 +2149,7 @@ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI receive process half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2163,7 +2161,7 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2175,7 +2173,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) @@ -2199,7 +2197,7 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI abort complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) @@ -2233,11 +2231,11 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) } /** * @brief Wait for a flag state until timeout. - * @param hqspi: QSPI handle - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Timeout: Duration of the time out - * @param tickstart: tick start value + * @param hqspi QSPI handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the time out + * @param tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, @@ -2263,9 +2261,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information - * @param FunctionalMode: functional mode to configured + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param FunctionalMode functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h index d51be14baa..f13f15095b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_qspi.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of QSPI HAL module. ****************************************************************************** * @attention @@ -433,26 +431,26 @@ typedef struct */ /** @brief Reset QSPI handle state - * @param __HANDLE__: QSPI handle. + * @param __HANDLE__ QSPI handle. * @retval None */ #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) /** @brief Enable QSPI - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable QSPI - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enables the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Time out interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -465,8 +463,8 @@ typedef struct /** @brief Disables the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -478,8 +476,8 @@ typedef struct #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Checks whether the specified QSPI interrupt source is enabled. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Time out interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -492,8 +490,8 @@ typedef struct /** * @brief Get the selected QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI flag to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Time out flag @@ -506,8 +504,8 @@ typedef struct #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Time out flag * @arg QSPI_FLAG_SM: QSPI Status match flag diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c index b34b9543b2..1f833074f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c @@ -2,21 +2,19 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions - * - @verbatim + * + @verbatim ============================================================================== ##### RCC specific features ##### ============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; @@ -24,12 +22,12 @@ (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in input floating state, except the JTAG pins which are assigned to be used for debug purpose. - - [..] - Once the device started from reset, the user application has to: + + [..] + Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings + (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB busses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not @@ -37,17 +35,17 @@ ##### RCC Limitations ##### ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. - (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle after the clock enable bit is set on the hardware register - (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle after the clock enable bit is set on the hardware register - [..] + [..] Implemented Workaround: (+) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. @@ -81,7 +79,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -102,12 +100,11 @@ /** @addtogroup RCC_Private_Constants * @{ */ -#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ /* Private macro -------------------------------------------------------------*/ #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 +#define MCO1_PIN GPIO_PIN_8 #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() #define MCO2_GPIO_PORT GPIOC @@ -119,7 +116,7 @@ /* Private variables ---------------------------------------------------------*/ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ - */ + */ /** * @} */ @@ -130,16 +127,16 @@ * @{ */ -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to configure the internal/external oscillators - (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration @@ -152,7 +149,7 @@ (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring two different output clocks: (++) The first output is used to generate the high speed system clock (up to 168 MHz) @@ -160,10 +157,10 @@ the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System + and if a HSE clock failure occurs(HSE used directly or through PLL as System clock source), the System clocks automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M4 NMI - (Non-Maskable Interrupt) exception vector. + is generated if enabled. The interrupt is linked to the Cortex-M4 NMI + (Non-Maskable Interrupt) exception vector. (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL clock (through a configurable prescaler) on PA8 pin. @@ -171,36 +168,36 @@ (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S clock (through a configurable prescaler) on PC9 pin. - [..] System, AHB and APB busses clocks configuration + [..] System, AHB and APB busses clocks configuration (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum - frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. + frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly (refer to the product datasheets for more details). (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices, - the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. + the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly (refer to the product datasheets for more details). - + (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz, - PCLK2 84 MHz and PCLK1 42 MHz. + PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly (refer to the product datasheets for more details). - + (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz, - PCLK2 100 MHz and PCLK1 50 MHz. + PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly (refer to the product datasheets for more details). - + @endverbatim * @{ */ @@ -214,17 +211,19 @@ * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status */ -__weak void HAL_RCC_DeInit(void) -{} +__weak HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + return HAL_OK; +} /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not @@ -237,11 +236,17 @@ __weak void HAL_RCC_DeInit(void) */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - /*------------------------------- HSE Configuration ------------------------*/ + /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ @@ -259,25 +264,25 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - + /* Check the HSE State */ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ + + /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSE is bypassed or disabled */ @@ -286,7 +291,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } } @@ -297,7 +302,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) @@ -325,16 +330,16 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till HSI is ready */ + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } else @@ -344,15 +349,15 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ + + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } + } + } } } } @@ -367,58 +372,68 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick*/ + + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ + + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } + } + } } } - /*------------------------------ LSE Configuration -------------------------*/ + /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { + FlagStatus pwrclkchanged = RESET; + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; - - /* Wait for Backup domain Write protection enable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - return HAL_TIMEOUT; - } + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } } /* Set the new LSE configuration -----------------------------------------*/ @@ -428,30 +443,36 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ @@ -460,7 +481,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { + { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ @@ -469,52 +490,52 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - + /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ + + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } - } + } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ RCC_OscInitStruct->PLL.PLLM | \ - (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ - (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ)))); + (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ + (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ + + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -531,27 +552,27 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } return HAL_OK; } - + /** - * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. - * @param FLatency: FLASH Latency, this parameter depend on device selected - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * @param FLatency FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by HAL_RCC_GetHCLKFreq() function called within this function * * @note The HSI is used (enabled by hardware) as system clock source after * startup from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). - * + * * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). + * clock source is ready (clock stable after startup delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * + * occur when the clock source will be ready. + * * @note Depending on the device voltage range, the software has to set correctly * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") @@ -559,56 +580,74 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ - + /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) - { + if(FLatency > __HAL_FLASH_GET_LATENCY()) + { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } } - + /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } - - /*------------------------- SYSCLK Configuration ---------------------------*/ + + /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { + { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - + /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - /* Check the HSE ready flag */ + /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { return HAL_ERROR; } } /* PLL is selected as System Clock Source */ - else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) { - /* Check the PLL ready flag */ + /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { return HAL_ERROR; @@ -617,81 +656,49 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* HSI is selected as System Clock Source */ else { - /* Check the HSI ready flag */ + /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { return HAL_ERROR; } } - + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - /* Get Start Tick*/ + + /* Get Start Tick */ tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - + } + /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) - { + if(FLatency < __HAL_FLASH_GET_LATENCY()) + { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } - } + } - /*-------------------------- PCLK1 Configuration ---------------------------*/ + /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ + + /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); @@ -699,11 +706,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; - /* Configure the source of time base considering new system clocks settings*/ + /* Configure the source of time base considering new system clocks settings */ HAL_InitTick (TICK_INT_PRIORITY); - + return HAL_OK; } @@ -711,17 +718,17 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @} */ -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. - + @endverbatim * @{ */ @@ -729,22 +736,22 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /** * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). * @note PA8/PC9 should be configured in alternate function mode. - * @param RCC_MCOx: specifies the output direction for the clock source. + * @param RCC_MCOx specifies the output direction for the clock source. * This parameter can be one of the following values: * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). - * @param RCC_MCOSource: specifies the clock source to output. + * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx - * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCODiv: specifies the MCOx prescaler. + * @param RCC_MCODiv specifies the MCOx prescaler. * This parameter can be one of the following values: * @arg RCC_MCODIV_1: no division applied to MCOx clock * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock @@ -765,34 +772,34 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M if(RCC_MCOx == RCC_MCO1) { assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - + /* MCO1 Clock Enable */ __MCO1_CLK_ENABLE(); - - /* Configure the MCO1 pin in alternate function mode */ + + /* Configure the MCO1 pin in alternate function mode */ GPIO_InitStruct.Pin = MCO1_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Alternate = GPIO_AF0_MCO; HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); - + /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); - + /* This RCC MCO1 enable feature is available only on STM32F410xx devices */ #if defined(RCC_CFGR_MCO1EN) __HAL_RCC_MCO1_ENABLE(); -#endif /* RCC_CFGR_MCO1EN */ +#endif /* RCC_CFGR_MCO1EN */ } #if defined(RCC_CFGR_MCO2) else { assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); - + /* MCO2 Clock Enable */ __MCO2_CLK_ENABLE(); - + /* Configure the MCO2 pin in alternate function mode */ GPIO_InitStruct.Pin = MCO2_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -800,7 +807,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Alternate = GPIO_AF0_MCO; HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); - + /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U))); @@ -817,8 +824,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. * @retval None */ void HAL_RCC_EnableCSS(void) @@ -837,14 +844,14 @@ void HAL_RCC_DisableCSS(void) /** * @brief Returns the SYSCLK frequency - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. @@ -852,17 +859,17 @@ void HAL_RCC_DisableCSS(void) * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * @note The result of this function could be not correct when using fractional * value for HSE crystal. - * - * @note This function can be used by the user application to compute the + * + * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. - * + * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * + * + * * @retval SYSCLK frequency */ __weak uint32_t HAL_RCC_GetSysClockFreq(void) @@ -891,15 +898,15 @@ __weak uint32_t HAL_RCC_GetSysClockFreq(void) if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } else { /* HSI used as PLL clock source */ - pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } - pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U); - + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); + sysclockfreq = pllvco/pllp; break; } @@ -913,11 +920,11 @@ __weak uint32_t HAL_RCC_GetSysClockFreq(void) } /** - * @brief Returns the HCLK frequency + * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ @@ -927,19 +934,19 @@ uint32_t HAL_RCC_GetHCLKFreq(void) } /** - * @brief Returns the PCLK1 frequency + * @brief Returns the PCLK1 frequency * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) -{ +{ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); } /** - * @brief Returns the PCLK2 frequency + * @brief Returns the PCLK2 frequency * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency @@ -947,13 +954,13 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); -} + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); +} /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ @@ -961,7 +968,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - + /* Get the HSE configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { @@ -975,7 +982,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } - + /* Get the HSI configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) { @@ -985,9 +992,9 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); - + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + /* Get the LSE configuration -----------------------------------------------*/ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { @@ -1001,7 +1008,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } - + /* Get the LSI configuration -----------------------------------------------*/ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) { @@ -1011,7 +1018,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } - + /* Get the PLL configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) { @@ -1023,38 +1030,38 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP)); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); } /** - * @brief Configures the RCC_ClkInitStruct according to the internal + * @brief Configures the RCC_ClkInitStruct according to the internal * RCC configuration registers. - * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that * will be configured. - * @param pFLatency: Pointer on the Flash Latency. + * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ + + /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); } /** @@ -1083,7 +1090,7 @@ __weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RCC_CSSCallback could be implemented in the user file - */ + */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h index 8d38985633..fc89426f80 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -54,7 +52,7 @@ * @{ */ -/** @addtogroup RCC +/** @addtogroup RCC * @{ */ @@ -62,9 +60,9 @@ /** @defgroup RCC_Exported_Types RCC Exported Types * @{ */ - + /** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct { @@ -90,7 +88,7 @@ typedef struct }RCC_OscInitTypeDef; /** - * @brief RCC System, AHB and APB busses clock configuration structure definition + * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { @@ -212,8 +210,8 @@ typedef struct /** * @} */ - -/** @defgroup RCC_System_Clock_Source System Clock Source + +/** @defgroup RCC_System_Clock_Source System Clock Source * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for * STM32F446xx devices. * @{ @@ -253,8 +251,8 @@ typedef struct #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /** * @} - */ - + */ + /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source * @{ */ @@ -265,13 +263,15 @@ typedef struct #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /** * @} - */ + */ /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U #define RCC_RTCCLKSOURCE_LSE 0x00000100U #define RCC_RTCCLKSOURCE_LSI 0x00000200U +#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U @@ -351,7 +351,7 @@ typedef struct /** * @} */ - + /** @defgroup RCC_Flag Flags * Elements values convention: 0XXYYYYYb * - YYYYY : Flag position in the register @@ -381,7 +381,7 @@ typedef struct #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) /** * @} - */ + */ /** * @} @@ -395,8 +395,8 @@ typedef struct /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @{ */ #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ @@ -459,23 +459,23 @@ typedef struct * using it. * @{ */ -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET) -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) /** * @} - */ - + */ + /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -539,7 +539,7 @@ typedef struct #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) -#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) /** * @} */ @@ -565,15 +565,15 @@ typedef struct #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) /** * @} - */ - + */ + /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. * @{ */ @@ -660,7 +660,7 @@ typedef struct #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) -#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) @@ -669,15 +669,15 @@ typedef struct #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) -#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) /** * @} - */ - -/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset * @brief Force or release AHB1 peripheral reset. * @{ - */ + */ #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) @@ -697,11 +697,11 @@ typedef struct * @} */ -/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) @@ -710,7 +710,7 @@ typedef struct #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) @@ -722,11 +722,11 @@ typedef struct * @} */ -/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) @@ -749,7 +749,7 @@ typedef struct * @} */ -/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable +/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. @@ -831,23 +831,23 @@ typedef struct */ /** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ - */ - + * @{ + */ + /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * It is used (enabled by hardware) as system clock source after startup * from Reset, wake-up from STOP and STANDBY mode, or in case of failure * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). + * Security System CSS is enabled). * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. + * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. + * system clock source. * This parameter can be: ENABLE or DISABLE. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. + * clock cycles. */ #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) @@ -855,27 +855,27 @@ typedef struct /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICalibrationValue__: specifies the calibration trimming value. + * @param __HSICalibrationValue__ specifies the calibration trimming value. * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F. */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ - RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))) + RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos)) /** * @} */ /** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ - */ + * @{ + */ /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on + * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. * @note LSI can not be disabled if the IWDG is running. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. + * clock cycles. */ #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) @@ -884,12 +884,12 @@ typedef struct */ /** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ - */ + * @{ + */ /** * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. * User should request a transition to HSE Off first and then HSE On or HSE Bypass. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock @@ -897,11 +897,11 @@ typedef struct * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__: specifies the new state of the HSE. + * function. + * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. @@ -930,21 +930,21 @@ typedef struct */ /** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ + * @{ */ /** * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * User should request a transition to LSE Off first and then LSE On or LSE Bypass. * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using + * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). + * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. - * @param __STATE__: specifies the new state of the LSE. + * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. @@ -973,7 +973,7 @@ typedef struct */ /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration - * @{ + * @{ */ /** @brief Macros to enable or disable the RTC clock. @@ -986,34 +986,52 @@ typedef struct * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by * a Power On Reset (POR). - * @param __RTCCLKSource__: specifies the RTC clock source. + * @param __RTCCLKSource__ specifies the RTC clock source. * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. - * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. - * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] + @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wake-up source. * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. + * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). */ #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) - + #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ } while(0U) +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** + * @brief Get the RTC and HSE clock divider (RTCPRE). + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) + /** @brief Macros to force or release the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. + * @note The BKPSRAM is not affected by this reset. */ #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) @@ -1022,11 +1040,11 @@ typedef struct */ /** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ + * @{ */ /** @brief Macros to enable or disable the main PLL. - * @note After enabling the main PLL, the application software should wait on + * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL can not be disabled if it is used as system clock source @@ -1037,22 +1055,22 @@ typedef struct /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__: specifies the PLL entry clock source. + * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * + * */ #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) /** @brief Macro to configure the PLL multiplication factor. * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__: specifies the division factor for PLL VCO input clock + * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. - * + * */ #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) /** @@ -1060,16 +1078,16 @@ typedef struct */ /** @defgroup RCC_Get_Clock_source Get Clock source - * @{ + * @{ */ /** * @brief Macro to configure the system clock source. - * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. + * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. - * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This + * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This * parameter is available only for STM32F446xx devices. */ #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) @@ -1082,8 +1100,8 @@ typedef struct * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter * is available only for STM32F446xx devices. - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) /** @brief Macro to get the oscillator used as PLL clock source. * @retval The oscillator used as PLL clock source. The returned value can be one @@ -1097,9 +1115,9 @@ typedef struct */ /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ - + * @{ + */ + /** @brief Macro to configure the MCO1 clock. * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: @@ -1122,8 +1140,8 @@ typedef struct * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx - * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source * @param __MCODIV__ specifies the MCO clock prescaler. @@ -1141,7 +1159,7 @@ typedef struct /** * @} */ - + /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ @@ -1149,7 +1167,7 @@ typedef struct /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. @@ -1160,9 +1178,9 @@ typedef struct */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. @@ -1175,20 +1193,20 @@ typedef struct /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. * @arg RCC_IT_HSIRDY: HSI ready interrupt. * @arg RCC_IT_HSERDY: HSE ready interrupt. * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. * @arg RCC_IT_CSS: Clock Security System interrupt */ #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) /** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. @@ -1201,13 +1219,13 @@ typedef struct */ #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) -/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, +/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. */ #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) /** @brief Check RCC flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. @@ -1230,7 +1248,7 @@ typedef struct /** * @} */ - + /** * @} */ @@ -1242,9 +1260,9 @@ typedef struct /** @addtogroup RCC_Exported_Functions_Group1 * @{ - */ + */ /* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** @@ -1268,7 +1286,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t /* CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); -/* User Callbacks in non blocking mode (IT mode) */ +/* User Callbacks in non blocking mode (IT mode) */ void HAL_RCC_CSSCallback(void); /** @@ -1291,7 +1309,7 @@ void HAL_RCC_CSSCallback(void); * @{ */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register ---*/ +/* --- CR Register --- */ /* Alias word address of HSION bit */ #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) #define RCC_HSION_BIT_NUMBER 0x00U @@ -1303,7 +1321,7 @@ void HAL_RCC_CSSCallback(void); #define RCC_PLLON_BIT_NUMBER 0x18U #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) -/* --- BDCR Register ---*/ +/* --- BDCR Register --- */ /* Alias word address of RTCEN bit */ #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) #define RCC_RTCEN_BIT_NUMBER 0x0FU @@ -1312,7 +1330,7 @@ void HAL_RCC_CSSCallback(void); #define RCC_BDRST_BIT_NUMBER 0x10U #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) -/* --- CSR Register ---*/ +/* --- CSR Register --- */ /* Alias word address of LSION bit */ #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) #define RCC_LSION_BIT_NUMBER 0x00U @@ -1336,6 +1354,7 @@ void HAL_RCC_CSSCallback(void); #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT #define HSI_TIMEOUT_VALUE 2U /* 2 ms */ #define LSI_TIMEOUT_VALUE 2U /* 2 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ /** * @} @@ -1349,10 +1368,10 @@ void HAL_RCC_CSSCallback(void); /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ - + /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters * @{ - */ + */ #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U) #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ @@ -1407,7 +1426,7 @@ void HAL_RCC_CSSCallback(void); ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) - + #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) @@ -1433,7 +1452,7 @@ void HAL_RCC_CSSCallback(void); #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ - ((DIV) == RCC_MCODIV_5)) + ((DIV) == RCC_MCODIV_5)) #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) /** @@ -1446,7 +1465,7 @@ void HAL_RCC_CSSCallback(void); /** * @} - */ + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c index d347be9553..ab11566bc1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c @@ -2,13 +2,11 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Extension RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions - * + * ****************************************************************************** * @attention * @@ -37,7 +35,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -60,7 +58,7 @@ */ /** * @} - */ + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -69,37 +67,37 @@ * @{ */ -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Extended Peripheral Control functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. - [..] + [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) and RCC_BDCR register are set to their reset values. - + @endverbatim * @{ */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, LTDC RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status @@ -115,100 +113,100 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk uint32_t pllsaiq = 0U; uint32_t plli2sused = 0U; uint32_t pllsaiused = 0U; - + /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*------------------------ I2S APB1 configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*---------------------------- I2S APB2 configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*--------------------------- SAI1 configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); - + /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) { - pllsaiused = 1U; + pllsaiused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*-------------------------- SAI2 configuration ----------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); - + /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - + /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) { - pllsaiused = 1U; + pllsaiused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*----------------------------- RTC configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -216,7 +214,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -233,8 +231,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -247,7 +245,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } /*--------------------------------------------------------------------------*/ - + /*---------------------------- TIM configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) { @@ -255,80 +253,80 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } /*--------------------------------------------------------------------------*/ - + /*---------------------------- FMPI2C1 Configuration -----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); - + /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); } /*--------------------------------------------------------------------------*/ - + /*------------------------------ CEC Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); - + /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); } /*--------------------------------------------------------------------------*/ - + /*----------------------------- CLK48 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); - + /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); /* Enable the PLLSAI when it's used as clock source for CLK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) { - pllsaiused = 1U; + pllsaiused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*----------------------------- SDIO Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); - + /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); } /*--------------------------------------------------------------------------*/ - + /*------------------------------ SPDIFRX Configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); - + /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) { /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); + __HAL_RCC_PLLI2S_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLI2S is disabled */ @@ -338,66 +336,66 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* return in case of Timeout detected */ return HAL_TIMEOUT; - } + } } - + /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ + + /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - + /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ - plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U); - plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); + plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR); } - - /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ + + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) { /* Check for PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - + /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ - plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U); - plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - /* Configure the PLLI2S division factors */ + plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U); - plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) { /* Check for Parameters */ @@ -408,8 +406,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - + } + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); /* Get tick */ @@ -423,32 +421,32 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - } + } /*--------------------------------------------------------------------------*/ - + /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if(pllsaiused == 1U) { /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); + __HAL_RCC_PLLSAI_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - + /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ + + /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) { @@ -456,31 +454,31 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U); + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } - /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ - /* In Case of PLLI2S is selected as source clock for CLK48 */ + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ + /* In Case of PLLI2S is selected as source clock for CLK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U); - } + } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); @@ -490,11 +488,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } - } + } } return HAL_OK; } @@ -502,14 +500,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ @@ -517,53 +515,53 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 |\ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO |\ RCC_PERIPHCLK_SPDIFRX; - + /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM)); - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); /* Get the PLLSAI Clock configuration --------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM)); - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); - PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos); + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ)); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ)); + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); /* Get the SAI1 clock configuration ----------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - + /* Get the SAI2 clock configuration ----------------------------------------*/ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - + /* Get the I2S APB1 clock configuration ------------------------------------*/ PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); - + /* Get the I2S APB2 clock configuration ------------------------------------*/ PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); - + /* Get the RTC Clock configuration -----------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + /* Get the CEC clock configuration -----------------------------------------*/ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); - + /* Get the FMPI2C1 clock configuration -------------------------------------*/ PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); - + /* Get the CLK48 clock configuration ----------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - + /* Get the SDIO clock configuration ----------------------------------------*/ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); - + /* Get the SPDIFRX clock configuration -------------------------------------*/ PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); - + /* Get the TIM Prescaler configuration -------------------------------------*/ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) { @@ -576,9 +574,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock @@ -601,16 +599,16 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) switch (PeriphClk) { case RCC_PERIPHCLK_SAI1: - case RCC_PERIPHCLK_SAI2: + case RCC_PERIPHCLK_SAI2: { - saiclocksource = RCC->DCKCFGR; + saiclocksource = RCC->DCKCFGR; saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC); switch (saiclocksource) { - case 0U: /* PLLSAI is the clock source for SAI*/ + case 0U: /* PLLSAI is the clock source for SAI*/ { /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -620,22 +618,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM))); - } + } /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U; frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U); - frequency = frequency/(tmpreg1); - break; + frequency = frequency/(tmpreg1); + break; } case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/ case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/ - { + { /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -646,22 +644,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM))); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U; frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U); + tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U); frequency = frequency/(tmpreg1); - break; + break; } case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/ case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/ { /* Configure the PLLI2S division factor */ - /* PLL_VCO Input = PLL_SOURCE/PLLM */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -672,17 +670,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ /* SAI_CLK_x = PLL_VCO Output/PLLR */ tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U; frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1); - break; + break; } case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/ { frequency = EXTERNAL_CLOCK_VALUE; - break; + break; } case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/ { @@ -696,12 +694,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the PLL Source is HSE (External Clock) */ frequency = (uint32_t)(HSE_VALUE); } - break; - } + break; + } default : { break; - } + } } break; } @@ -711,8 +709,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPB1CLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -733,7 +731,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ @@ -755,7 +753,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); /* I2S_CLK = PLL_VCO Output/PLLR */ @@ -782,15 +780,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } } - break; - } + break; + } case RCC_PERIPHCLK_I2S_APB2: { /* Get the current I2S source */ srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ case RCC_I2SAPB2CLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ @@ -812,7 +810,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ @@ -834,7 +832,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); /* I2S_CLK = PLL_VCO Output/PLLR */ @@ -859,12 +857,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } } - return frequency; + return frequency; } #endif /* STM32F446xx */ @@ -872,13 +870,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, LTDC, RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status @@ -890,45 +888,45 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk uint32_t pllsaip = 0U; uint32_t pllsaiq = 0U; uint32_t pllsair = 0U; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*--------------------------- CLK48 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); - + /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); - } + } /*--------------------------------------------------------------------------*/ - + /*------------------------------ SDIO Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); - + /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); } /*--------------------------------------------------------------------------*/ - + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ /*------------------- Common configuration SAI/I2S -------------------------*/ - /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division - factor is common parameters for both peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - + /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); + __HAL_RCC_PLLI2S_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLI2S is disabled */ @@ -940,10 +938,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - + /*---------------------- I2S configuration -------------------------------*/ - /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added - only for I2S configuration */ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) { /* check for Parameters */ @@ -953,38 +951,38 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); } - - /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must - be added only for SAI configuration */ + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) { /* Check the PLLI2S division factors */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - /* Configure the PLLI2S division factors */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1); - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ + + /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) { /* Check for Parameters */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - + /* Configure the PLLI2S multiplication and division factors */ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - + } + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); /* Get tick */ @@ -1000,53 +998,53 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } /*--------------------------------------------------------------------------*/ - + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ /*----------------------- Common configuration SAI/LTDC --------------------*/ /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division - factor is common parameters for these peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || - (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || + factor is common parameters for these peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))) { /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - + /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); + __HAL_RCC_PLLSAI_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - + /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must - be added only for SAI configuration */ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) { assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U); + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair); - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair); + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); } - + /*---------------------------- LTDC configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) { @@ -1054,34 +1052,34 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U); + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR); - /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - } - + } + /*---------------------------- CLK48 configuration ------------------------*/ /* Configure the PLLSAI when it is used as clock source for CLK48 */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) && + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) { assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); - + /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair); } - + /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); /* Get tick */ @@ -1090,30 +1088,30 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } - } + } } /*--------------------------------------------------------------------------*/ - + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -1121,7 +1119,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -1132,14 +1130,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; - + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -1162,44 +1160,44 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /** - * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal + * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI |\ RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC |\ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO; - + /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); /* Get the PLLSAI Clock configuration --------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); - PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ)); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ)); + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); /* Get the RTC Clock configuration -----------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + /* Get the CLK48 clock configuration -------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - + /* Get the SDIO clock configuration ----------------------------------------*/ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); - + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) { PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; @@ -1211,9 +1209,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock * @retval Frequency in KHz @@ -1235,8 +1233,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SCLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -1257,7 +1255,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ @@ -1269,7 +1267,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } @@ -1282,13 +1280,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, LTDC RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status @@ -1304,106 +1302,106 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*----------------------------------- I2S APB1 configuration ---------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*----------------------------------- I2S APB2 configuration ---------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + #if defined(STM32F413xx) || defined(STM32F423xx) /*----------------------- SAI1 Block A configuration -----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA)) { /* Check the parameters */ assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection)); - + /* Configure SAI1 Clock source */ __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection); /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR) { - plli2sused = 1U; + plli2sused = 1U; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR) { /* Check for PLL/DIVR parameters */ assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ + + /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); } } /*--------------------------------------------------------------------------*/ - + /*---------------------- SAI1 Block B configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB)) { /* Check the parameters */ assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection)); - + /* Configure SAI1 Clock source */ __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection); /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR) { - plli2sused = 1U; + plli2sused = 1U; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR) { /* Check for PLL/DIVR parameters */ assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ + + /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); } } /*--------------------------------------------------------------------------*/ #endif /* STM32F413xx || STM32F423xx */ - + /*------------------------------------ RTC configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -1411,7 +1409,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -1428,8 +1426,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -1442,7 +1440,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } /*--------------------------------------------------------------------------*/ - + /*------------------------------------ TIM configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) { @@ -1450,46 +1448,46 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } /*--------------------------------------------------------------------------*/ - + /*------------------------------------- FMPI2C1 Configuration --------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); - + /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); } /*--------------------------------------------------------------------------*/ - + /*------------------------------------- CLK48 Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); - + /* Configure the SDIO clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); /* Enable the PLLI2S when it's used as clock source for CLK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*------------------------------------- SDIO Configuration -----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); - + /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); } /*--------------------------------------------------------------------------*/ - + /*-------------------------------------- PLLI2S Configuration --------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or I2S on APB2*/ @@ -1515,8 +1513,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*-------------------- Set the PLL I2S clock -----------------------------*/ __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection); - - /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/ + + /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) || @@ -1531,28 +1529,28 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } - + #if defined(STM32F413xx) || defined(STM32F423xx) - /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR))) + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR))) { /* Check for PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Check for PLLI2S/DIVR parameters */ assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR)); - + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ - plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); - /* Configure the PLLI2S division factors */ + plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR); - } + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR); + } #endif /* STM32F413xx || STM32F423xx */ /*----------------- In Case of PLLI2S is just selected ------------------*/ @@ -1605,8 +1603,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); } /*--------------------------------------------------------------------------*/ - -#if defined(STM32F413xx) || defined(STM32F423xx) + +#if defined(STM32F413xx) || defined(STM32F423xx) /*-------------------- DFSDM2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) { @@ -1628,13 +1626,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection); } /*--------------------------------------------------------------------------*/ - + /*---------------------------- LPTIM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); - + /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } @@ -1647,14 +1645,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg; - + /* Set all possible values for the extended clock type parameter------------*/ #if defined(STM32F413xx) || defined(STM32F423xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\ @@ -1671,26 +1669,26 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\ RCC_PERIPHCLK_DFSDM1_AUDIO; #endif /* STM32F413xx || STM32F423xx */ - - + + /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM)); - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); #if defined(STM32F413xx) || defined(STM32F423xx) /* Get the PLL/PLLI2S division factors -------------------------------------*/ - PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVR)); - PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> POSITION_VAL(RCC_DCKCFGR_PLLDIVR)); + PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos); + PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos); #endif /* STM32F413xx || STM32F423xx */ - + /* Get the I2S APB1 clock configuration ------------------------------------*/ PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); - + /* Get the I2S APB2 clock configuration ------------------------------------*/ PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); - + /* Get the RTC Clock configuration -----------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); @@ -1700,29 +1698,29 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the CLK48 clock configuration ---------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - + /* Get the SDIO clock configuration ----------------------------------------*/ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); - + /* Get the DFSDM1 clock configuration --------------------------------------*/ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); - + /* Get the DFSDM1 Audio clock configuration --------------------------------*/ PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); #if defined(STM32F413xx) || defined(STM32F423xx) /* Get the DFSDM2 clock configuration --------------------------------------*/ PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); - + /* Get the DFSDM2 Audio clock configuration --------------------------------*/ PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE(); - + /* Get the LPTIM1 clock configuration --------------------------------------*/ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - + /* Get the SAI1 Block Aclock configuration ---------------------------------*/ PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE(); - + /* Get the SAI1 Block B clock configuration --------------------------------*/ PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE(); #endif /* STM32F413xx || STM32F423xx */ @@ -1739,9 +1737,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } /** - * @brief Return the peripheral clock frequency for a given peripheral(I2S..) + * @brief Return the peripheral clock frequency for a given peripheral(I2S..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock @@ -1764,8 +1762,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPB1CLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -1792,7 +1790,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } + } } /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); @@ -1815,7 +1813,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); /* I2S_CLK = PLL_VCO Output/PLLR */ @@ -1840,7 +1838,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } @@ -1850,8 +1848,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPB2CLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -1878,7 +1876,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } + } } /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); @@ -1901,7 +1899,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); /* I2S_CLK = PLL_VCO Output/PLLR */ @@ -1926,12 +1924,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } } - return frequency; + return frequency; } #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ @@ -1939,38 +1937,38 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the * RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). - * - * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case - * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset - * + * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tickstart = 0U; uint32_t tmpreg1 = 0U; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -1978,7 +1976,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -1995,8 +1993,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -2016,24 +2014,24 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } /*--------------------------------------------------------------------------*/ - + /*---------------------------- FMPI2C1 Configuration -----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); - + /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); } /*--------------------------------------------------------------------------*/ - + /*---------------------------- LPTIM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); - + /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } @@ -2043,7 +2041,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection)); - + /* Configure the I2S clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection); } @@ -2052,9 +2050,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ @@ -2064,10 +2062,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; - + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) { PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; @@ -2082,12 +2080,12 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the I2S clock configuration -----------------------------------------*/ PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE(); - + } /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock * @retval Frequency in KHz @@ -2109,8 +2107,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPBCLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPBCLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -2131,7 +2129,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); /* I2S_CLK = PLL_VCO Output/PLLR */ @@ -2161,7 +2159,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } } - return frequency; + return frequency; } #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ @@ -2169,13 +2167,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, LTDC RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status @@ -2184,22 +2182,22 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { uint32_t tickstart = 0U; uint32_t tmpreg1 = 0U; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ /*----------------------- Common configuration SAI/I2S ---------------------*/ - /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division - factor is common parameters for both peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S)) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - + /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); + __HAL_RCC_PLLI2S_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLI2S is disabled */ @@ -2211,10 +2209,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - + /*---------------------------- I2S configuration -------------------------*/ - /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added - only for I2S configuration */ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) { /* check for Parameters */ @@ -2224,27 +2222,27 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); } - - /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must - be added only for SAI configuration */ + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) { /* Check the PLLI2S division factors */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - /* Configure the PLLI2S division factors */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1); - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); } - + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); /* Get tick */ @@ -2260,64 +2258,64 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } /*--------------------------------------------------------------------------*/ - + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ /*----------------------- Common configuration SAI/LTDC --------------------*/ /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division - factor is common parameters for both peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + factor is common parameters for both peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) { /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - + /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); + __HAL_RCC_PLLSAI_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - + /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must - be added only for SAI configuration */ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) { assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); } - + /*---------------------------- LTDC configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) { assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); - + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR); - /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - } + } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); /* Get tick */ @@ -2326,29 +2324,29 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } - } + } } /*--------------------------------------------------------------------------*/ - + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -2356,7 +2354,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -2373,8 +2371,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -2397,35 +2395,35 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /** - * @brief Configures the PeriphClkInit according to the internal + * @brief Configures the PeriphClkInit according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; - + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); /* Get the PLLSAI Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); - PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ)); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ)); + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); /* Get the RTC Clock configuration -----------------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) { PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; @@ -2437,9 +2435,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock * @retval Frequency in KHz @@ -2461,8 +2459,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SCLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -2483,7 +2481,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ @@ -2495,12 +2493,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } } - return frequency; + return frequency; } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ @@ -2509,23 +2507,23 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the * RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). - * - * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case - * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset - * + * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tickstart = 0U; uint32_t tmpreg1 = 0U; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*---------------------------- I2S configuration ---------------------------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) @@ -2533,7 +2531,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); -#if defined(STM32F411xE) +#if defined(STM32F411xE) assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); #endif /* STM32F411xE */ /* Disable the PLLI2S */ @@ -2547,13 +2545,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* return in case of Timeout detected */ return HAL_TIMEOUT; - } + } } #if defined(STM32F411xE) /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); #else /* Configure the PLLI2S division factors */ @@ -2561,7 +2559,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); #endif /* STM32F411xE */ - + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); /* Get tick */ @@ -2576,22 +2574,22 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -2599,7 +2597,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -2616,8 +2614,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -2640,22 +2638,22 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC; - + /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); #if defined(STM32F411xE) PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM); #endif /* STM32F411xE */ @@ -2673,13 +2671,13 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; } -#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ } /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock * @retval Frequency in KHz @@ -2701,8 +2699,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SCLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -2737,7 +2735,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } -#endif /* STM32F411xE */ +#endif /* STM32F411xE */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ @@ -2749,12 +2747,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } } - return frequency; + return frequency; } #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ @@ -2762,10 +2760,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Select LSE mode - * + * * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. - * - * @param Mode: specifies the LSE mode. + * + * @param Mode specifies the LSE mode. * This parameter can be one of the following values: * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection @@ -2787,20 +2785,255 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode) #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLLI2S, PLLSAI. +@endverbatim + * @{ + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Enable PLLI2S. + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM)); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ +#if defined(RCC_PLLI2SCFGR_PLLI2SP) + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); +#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLI2S division factors */ +#if defined(STM32F446xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F411xE) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#else + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#endif /* STM32F446xx */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Wait till PLLI2S is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart; + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Enable PLLSAI. + * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that + * contains the configuration information for the PLLSAI + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); +#if defined(RCC_PLLSAICFGR_PLLSAIM) + assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM)); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ +#if defined(RCC_PLLSAICFGR_PLLSAIP) + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); +#endif /* RCC_PLLSAICFGR_PLLSAIP */ +#if defined(RCC_PLLSAICFGR_PLLSAIR) + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLSAI division factors */ +#if defined(STM32F446xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \ + PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U); +#elif defined(STM32F469xx) || defined(STM32F479xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ + PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#else + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#endif /* STM32F446xx */ + + /* Enable the PLLSAI */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Wait till PLLSAI is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLSAI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +{ + uint32_t tickstart; + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @} + */ + #if defined(STM32F446xx) /** * @brief Returns the SYSCLK frequency - * + * * @note This function implementation is valid only for STM32F446xx devices. * @note This function add the PLL/PLLR System clock source * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. @@ -2808,17 +3041,17 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode) * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * @note The result of this function could be not correct when using fractional * value for HSE crystal. - * - * @note This function can be used by the user application to compute the + * + * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. - * + * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * + * + * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) @@ -2850,15 +3083,15 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } else { /* HSI used as PLL clock source */ - pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } - pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U); - + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); + sysclockfreq = pllvco/pllp; break; } @@ -2870,15 +3103,15 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } else { /* HSI used as PLL clock source */ - pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } - pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)); - + pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); + sysclockfreq = pllvco/pllr; break; } @@ -2900,11 +3133,6 @@ uint32_t HAL_RCC_GetSysClockFreq(void) * @} */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ - defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: @@ -2914,110 +3142,188 @@ uint32_t HAL_RCC_GetSysClockFreq(void) * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status */ -void HAL_RCC_DeInit(void) +HAL_StatusTypeDef HAL_RCC_DeInit(void) { - /* Set HSION bit */ - SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[4:0] bits to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); - /* Reset HSEON, CSSON, PLLON, PLLI2S bits */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_PLLI2SON); + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear HSEON, HSEBYP and CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_PLLI2S_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLI2SON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); -#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Reset PLLSAI bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); -#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - /* Reset PLLCFGR register */ - CLEAR_REG(RCC->PLLCFGR); + /* Wait till PLLSAI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLSAI_SUPPORT */ + + /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ #if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1); + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1; +#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) + RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3; #else - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2; #endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */ - /* Reset PLLI2SCFGR register */ - CLEAR_REG(RCC->PLLI2SCFGR); + /* Reset PLLI2SCFGR register to default value */ #if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ defined(STM32F423xx) || defined(STM32F446xx) - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1); + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; #elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1); + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; #elif defined(STM32F411xE) - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1); -#else - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1); + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; #endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */ /* Reset PLLSAICFGR register */ #if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - CLEAR_REG(RCC->PLLSAICFGR); - SET_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1); + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1; #elif defined(STM32F446xx) - CLEAR_REG(RCC->PLLSAICFGR); - SET_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2); + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2; #endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */ /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE); + +#if defined(RCC_CIR_PLLI2SRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +#endif /* RCC_CIR_PLLI2SRDYIE */ + +#if defined(RCC_CIR_PLLSAIRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +#endif /* RCC_CIR_PLLSAIRDYIE */ + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); + +#if defined(RCC_CIR_PLLI2SRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +#endif /* RCC_CIR_PLLI2SRDYC */ + +#if defined(RCC_CIR_PLLSAIRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +#endif /* RCC_CIR_PLLSAIRDYC */ + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } } -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || - STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || - STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE and PLL OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None - */ -void HAL_RCC_DeInit(void) -{ - /* Set HSION bit */ - SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Reset HSEON, HSEBYP, CSSON, PLLON */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON); - - /* Reset PLLCFGR register */ - CLEAR_REG(RCC->PLLCFGR); - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HSI_VALUE; -} -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not @@ -3026,17 +3332,17 @@ void HAL_RCC_DeInit(void) * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this API. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. - * @note This function add the PLL/PLLR factor management during PLL configuration this feature - * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices + * @note This function add the PLL/PLLR factor management during PLL configuration this feature + * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0U; - + uint32_t tickstart = 0U; + /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - /*------------------------------- HSE Configuration ------------------------*/ + /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ @@ -3060,20 +3366,20 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - + /* Check the HSE State */ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ + + /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else @@ -3087,7 +3393,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } } @@ -3098,7 +3404,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ @@ -3132,15 +3438,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till HSI is ready */ + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } - + } + } + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } @@ -3151,15 +3457,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ + + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } + } + } } } } @@ -3174,60 +3480,70 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ + + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } + } + } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { + FlagStatus pwrclkchanged = RESET; + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } - + /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ @@ -3235,8 +3551,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -3249,16 +3565,22 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ @@ -3267,7 +3589,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { + { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ @@ -3277,21 +3599,21 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); - + /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } - } + } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, @@ -3306,25 +3628,25 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -3343,9 +3665,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured. * * @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. * @note This function add the PLL/PLLR factor management @@ -3355,7 +3677,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - + /* Get the HSE configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { @@ -3369,7 +3691,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } - + /* Get the HSI configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) { @@ -3379,9 +3701,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); - + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + /* Get the LSE configuration -----------------------------------------------*/ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { @@ -3395,7 +3717,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } - + /* Get the LSI configuration -----------------------------------------------*/ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) { @@ -3405,7 +3727,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } - + /* Get the PLL configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) { @@ -3417,10 +3739,10 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP)); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)); - RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); } #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h index b32cc05c51..613dfb2db9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -310,6 +308,7 @@ typedef struct #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + /** * @brief PLLI2S Clock structure definition */ @@ -734,6 +733,7 @@ typedef struct /** * @} */ + #endif /* STM32F446xx */ #if defined(STM32F413xx) || defined(STM32F423xx) @@ -871,6 +871,7 @@ typedef struct #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) + /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source * @{ */ @@ -5720,32 +5721,32 @@ typedef struct defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__: specifies the division factor for PLL VCO input clock + * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. * - * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * - * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks + * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work * correctly. * - * @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. + * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. @@ -5753,33 +5754,33 @@ typedef struct */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ - ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - ((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ - ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \ - ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR)))) + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) #else /** @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__: specifies the division factor for PLL VCO input clock + * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432 * Except for STM32F411xE devices where Min_Data = 192. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices * where frequency is between 192 and 432 MHz. - * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * - * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks + * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, @@ -5789,9 +5790,9 @@ typedef struct */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ - ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - ((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ - ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ /*----------------------------------------------------------------------------*/ @@ -5816,84 +5817,84 @@ typedef struct * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API). - * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 1 MHz to limit PLLI2S jitter. * - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLI2SP__: specifies division factor for SPDIFRX Clock. + * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. * This parameter must be a number in the range {2, 4, 6, or 8}. * @note the PLLI2SP parameter is only available with STM32F446xx Devices * - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * - * @param __PLLI2SQ__: specifies the division factor for SAI clock + * @param __PLLI2SQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ - ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ - ((((__PLLI2SP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\ - ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ - ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) #elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the PLLI2S clock multiplication and division factors . * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API). - * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 1 MHz to limit PLLI2S jitter. * - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * - * @param __PLLI2SQ__: specifies the division factor for SAI clock + * @param __PLLI2SQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ - ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ - ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ - ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) #else /** @brief Macro to configure the PLLI2S clock multiplication and division factors . * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API). - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ - (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ - ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) + (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) #endif /* STM32F446xx */ #if defined(STM32F411xE) @@ -5902,24 +5903,24 @@ typedef struct * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API). - * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLLI2S jitter. - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between Min_Data = 192 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. */ #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ - ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ - ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) #endif /* STM32F411xE */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) @@ -5927,15 +5928,15 @@ typedef struct * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API) - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock. + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLI2SQ__: specifies the division factor for SAI1 clock. + * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. @@ -5958,79 +5959,79 @@ typedef struct #if defined(STM32F446xx) /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * - * @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock + * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 1 MHz to limit PLLI2S jitter. * @note The PLLSAIM parameter is only used with STM32F446xx Devices * - * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks. + * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. * This parameter must be a number in the range {2, 4, 6, or 8}. * @note the PLLSAIP parameter is only available with STM32F446xx Devices * - * @param __PLLSAIQ__: specifies the division factor for SAI clock + * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * - * @param __PLLSAIR__: specifies the division factor for LTDC clock + * @param __PLLSAIR__ specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ - ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \ - ((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | \ - ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)))) + ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ + ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) #endif /* STM32F446xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * - * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks. + * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. * This parameter must be a number in the range {2, 4, 6, or 8}. * - * @param __PLLSAIQ__: specifies the division factor for SAI clock + * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * - * @param __PLLSAIR__: specifies the division factor for LTDC clock + * @param __PLLSAIR__ specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ - (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\ - ((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\ - ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\ - ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))) + (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) #endif /* STM32F469xx || STM32F479xx */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * - * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLSAIQ__: specifies the division factor for SAI clock + * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * - * @param __PLLSAIR__: specifies the division factor for LTDC clock + * @param __PLLSAIR__ specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ - (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \ - ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) | \ - ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))) + (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ @@ -6040,14 +6041,14 @@ typedef struct #if defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. * @note This function must be called before enabling the PLLI2S. - * @param __PLLI2SDivR__: specifies the PLLI2S division factor for SAI1 clock. + * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. * This parameter must be a number between 1 and 32. * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ */ #define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) /** @brief Macro to configure the SAI clock Divider coming from PLL. - * @param __PLLDivR__: specifies the PLL division factor for SAI1 clock. + * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. * This parameter must be a number between 1 and 32. * SAI1 clock frequency = f(PLLR) / __PLLDivR__ */ @@ -6058,7 +6059,7 @@ typedef struct defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. * @note This function must be called before enabling the PLLI2S. - * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock. + * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. * This parameter must be a number between 1 and 32. * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ */ @@ -6066,7 +6067,7 @@ typedef struct /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock . + * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . * This parameter must be a number between Min_Data = 1 and Max_Data = 32. * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ */ @@ -6078,7 +6079,7 @@ typedef struct * * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock . + * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . * This parameter must be a number between Min_Data = 2 and Max_Data = 16. * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ */ @@ -6093,7 +6094,7 @@ typedef struct defined(STM32F479xx) /** @brief Macro to configure the I2S clock source (I2SCLK). * @note This function must be called before enabling the I2S APB clock. - * @param __SOURCE__: specifies the I2S clock source. + * @param __SOURCE__ specifies the I2S clock source. * This parameter can be one of the following values: * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin @@ -6117,7 +6118,7 @@ typedef struct * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI Block A clock source. + * @param __SOURCE__ specifies the SAI Block A clock source. * This parameter can be one of the following values: * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used * as SAI1 Block A clock. @@ -6132,7 +6133,7 @@ typedef struct * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI Block B clock source. + * @param __SOURCE__ specifies the SAI Block B clock source. * This parameter can be one of the following values: * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used * as SAI1 Block B clock. @@ -6149,7 +6150,7 @@ typedef struct * @note This configuration is only available with STM32F446xx Devices. * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI1 clock source. + * @param __SOURCE__ specifies the SAI1 clock source. * This parameter can be one of the following values: * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. @@ -6172,7 +6173,7 @@ typedef struct * @note This configuration is only available with STM32F446xx Devices. * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI2 clock source. + * @param __SOURCE__ specifies the SAI2 clock source. * This parameter can be one of the following values: * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. @@ -6193,7 +6194,7 @@ typedef struct /** @brief Macro to configure I2S APB1 clock source selection. * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. - * @param __SOURCE__: specifies the I2S APB1 clock source. + * @param __SOURCE__ specifies the I2S APB1 clock source. * This parameter can be one of the following values: * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. @@ -6213,7 +6214,7 @@ typedef struct /** @brief Macro to configure I2S APB2 clock source selection. * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. - * @param __SOURCE__: specifies the SAI Block A clock source. + * @param __SOURCE__ specifies the SAI Block A clock source. * This parameter can be one of the following values: * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. @@ -6232,7 +6233,7 @@ typedef struct #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) /** @brief Macro to configure the CEC clock. - * @param __SOURCE__: specifies the CEC clock source. + * @param __SOURCE__ specifies the CEC clock source. * This parameter can be one of the following values: * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock @@ -6247,7 +6248,7 @@ typedef struct #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) /** @brief Macro to configure the FMPI2C1 clock. - * @param __SOURCE__: specifies the FMPI2C1 clock source. + * @param __SOURCE__ specifies the FMPI2C1 clock source. * This parameter can be one of the following values: * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock @@ -6264,7 +6265,7 @@ typedef struct #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) /** @brief Macro to configure the CLK48 clock. - * @param __SOURCE__: specifies the CLK48 clock source. + * @param __SOURCE__ specifies the CLK48 clock source. * This parameter can be one of the following values: * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. @@ -6279,7 +6280,7 @@ typedef struct #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) /** @brief Macro to configure the SDIO clock. - * @param __SOURCE__: specifies the SDIO clock source. + * @param __SOURCE__ specifies the SDIO clock source. * This parameter can be one of the following values: * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. @@ -6294,7 +6295,7 @@ typedef struct #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) /** @brief Macro to configure the SPDIFRX clock. - * @param __SOURCE__: specifies the SPDIFRX clock source. + * @param __SOURCE__ specifies the SPDIFRX clock source. * This parameter can be one of the following values: * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. @@ -6312,7 +6313,7 @@ typedef struct #if defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macro to configure the CLK48 clock. - * @param __SOURCE__: specifies the CLK48 clock source. + * @param __SOURCE__ specifies the CLK48 clock source. * This parameter can be one of the following values: * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. @@ -6327,7 +6328,7 @@ typedef struct #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) /** @brief Macro to configure the SDIO clock. - * @param __SOURCE__: specifies the SDIO clock source. + * @param __SOURCE__ specifies the SDIO clock source. * This parameter can be one of the following values: * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. @@ -6342,7 +6343,7 @@ typedef struct #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) /** @brief Macro to configure the DSI clock. - * @param __SOURCE__: specifies the DSI clock source. + * @param __SOURCE__ specifies the DSI clock source. * This parameter can be one of the following values: * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. @@ -6361,7 +6362,7 @@ typedef struct #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the DFSDM1 clock. - * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source. + * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. * This parameter can be one of the following values: * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock. @@ -6379,7 +6380,7 @@ typedef struct /** @brief Macro to configure DFSDM1 Audio clock source selection. * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ STM32F413xx/STM32F423xx Devices. - * @param __SOURCE__: specifies the DFSDM1 Audio clock source. + * @param __SOURCE__ specifies the DFSDM1 Audio clock source. * This parameter can be one of the following values: * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock @@ -6397,7 +6398,7 @@ typedef struct #if defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the DFSDM2 clock. - * @param __DFSDM2_CLKSOURCE__: specifies the DFSDM1 clock source. + * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. * This parameter can be one of the following values: * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock. @@ -6414,7 +6415,7 @@ typedef struct /** @brief Macro to configure DFSDM1 Audio clock source selection. * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. - * @param __SOURCE__: specifies the DFSDM2 Audio clock source. + * @param __SOURCE__ specifies the DFSDM2 Audio clock source. * This parameter can be one of the following values: * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock @@ -6433,7 +6434,7 @@ typedef struct * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI Block A clock source. + * @param __SOURCE__ specifies the SAI Block A clock source. * This parameter can be one of the following values: * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. @@ -6456,7 +6457,7 @@ typedef struct * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI Block B clock source. + * @param __SOURCE__ specifies the SAI Block B clock source. * This parameter can be one of the following values: * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. @@ -6476,7 +6477,7 @@ typedef struct #define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) /** @brief Macro to configure the LPTIM1 clock. - * @param __SOURCE__: specifies the LPTIM1 clock source. + * @param __SOURCE__ specifies the LPTIM1 clock source. * This parameter can be one of the following values: * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock @@ -6496,7 +6497,7 @@ typedef struct #endif /* STM32F413xx || STM32F423xx */ /** @brief Macro to configure I2S APB1 clock source selection. - * @param __SOURCE__: specifies the I2S APB1 clock source. + * @param __SOURCE__ specifies the I2S APB1 clock source. * This parameter can be one of the following values: * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. @@ -6515,7 +6516,7 @@ typedef struct #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) /** @brief Macro to configure I2S APB2 clock source selection. - * @param __SOURCE__: specifies the I2S APB2 clock source. + * @param __SOURCE__ specifies the I2S APB2 clock source. * This parameter can be one of the following values: * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. @@ -6535,7 +6536,7 @@ typedef struct /** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). * @note This macro must be called before enabling the I2S APB clock. - * @param __SOURCE__: specifies the I2S clock source. + * @param __SOURCE__ specifies the I2S clock source. * This parameter can be one of the following values: * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin @@ -6544,7 +6545,7 @@ typedef struct #define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) /** @brief Macro to configure the FMPI2C1 clock. - * @param __SOURCE__: specifies the FMPI2C1 clock source. + * @param __SOURCE__ specifies the FMPI2C1 clock source. * This parameter can be one of the following values: * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock @@ -6561,7 +6562,7 @@ typedef struct #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) /** @brief Macro to configure the CLK48 clock. - * @param __SOURCE__: specifies the CLK48 clock source. + * @param __SOURCE__ specifies the CLK48 clock source. * This parameter can be one of the following values: * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. @@ -6576,7 +6577,7 @@ typedef struct #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) /** @brief Macro to configure the SDIO clock. - * @param __SOURCE__: specifies the SDIO clock source. + * @param __SOURCE__ specifies the SDIO clock source. * This parameter can be one of the following values: * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. @@ -6594,7 +6595,7 @@ typedef struct #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) /** @brief Macro to configure I2S clock source selection. - * @param __SOURCE__: specifies the I2S clock source. + * @param __SOURCE__ specifies the I2S clock source. * This parameter can be one of the following values: * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. @@ -6611,7 +6612,7 @@ typedef struct #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) /** @brief Macro to configure the FMPI2C1 clock. - * @param __SOURCE__: specifies the FMPI2C1 clock source. + * @param __SOURCE__ specifies the FMPI2C1 clock source. * This parameter can be one of the following values: * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock @@ -6628,7 +6629,7 @@ typedef struct #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) /** @brief Macro to configure the LPTIM1 clock. - * @param __SOURCE__: specifies the LPTIM1 clock source. + * @param __SOURCE__ specifies the LPTIM1 clock source. * This parameter can be one of the following values: * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock @@ -6654,7 +6655,7 @@ typedef struct defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the Timers clocks prescalers * @note This feature is only available with STM32F429x/439x Devices. - * @param __PRESC__ : specifies the Timers clocks prescalers selection + * @param __PRESC__ specifies the Timers clocks prescalers selection * This parameter can be one of the following values: * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is * equal to HPRE if PPREx is corresponding to division by 1 or 2, @@ -6734,6 +6735,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); defined(STM32F423xx) void HAL_RCCEx_SelectLSEMode(uint8_t Mode); #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +#if defined(RCC_PLLI2S_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); +#endif /* RCC_PLLSAI_SUPPORT */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.c index 38124aab74..f81f30ec58 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rng.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: @@ -116,7 +114,7 @@ /** * @brief Initializes the RNG peripheral and creates the associated handle. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ @@ -127,9 +125,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { return HAL_ERROR; } - - __HAL_LOCK(hrng); - + if(hrng->State == HAL_RNG_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -146,16 +142,14 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; - - __HAL_UNLOCK(hrng); - + /* Return function status */ return HAL_OK; } /** * @brief DeInitializes the RNG peripheral. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ @@ -187,7 +181,7 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) /** * @brief Initializes the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval None */ @@ -202,7 +196,7 @@ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) /** * @brief DeInitializes the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval None */ @@ -239,9 +233,9 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) * @brief Generates a 32-bit random number. * @note Each time the random number data is read the RNG_FLAG_DRDY flag * is automatically cleared. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. - * @param random32bit: pointer to generated random number variable if successful. + * @param random32bit pointer to generated random number variable if successful. * @retval HAL status */ @@ -295,7 +289,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /** * @brief Generates a 32-bit random number in interrupt mode. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ @@ -345,7 +339,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) * the RNG peripheral to reinitialize and restart the RNG. * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS * or CEIS are set. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval None @@ -388,7 +382,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /** * @brief Returns generated random number in polling mode (Obsolete) * Use HAL_RNG_GenerateRandomNumber() API instead. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval Random value */ @@ -407,7 +401,7 @@ uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) /** * @brief Returns a 32-bit random number with interrupt enabled (Obsolete), * Use HAL_RNG_GenerateRandomNumber_IT() API instead. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval 32-bit random number */ @@ -433,7 +427,7 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) /** * @brief Read latest generated random number. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval random value */ @@ -444,9 +438,9 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) /** * @brief Data Ready callback in non-blocking mode. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. - * @param random32bit: generated random number. + * @param random32bit generated random number. * @retval None */ __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) @@ -461,7 +455,7 @@ __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32 /** * @brief RNG error callbacks. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval None */ @@ -495,7 +489,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) /** * @brief Returns the RNG state. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL state */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.h index bb5bfa3488..120546a361 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rng.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention @@ -145,29 +143,29 @@ typedef struct */ /** @brief Reset RNG handle state - * @param __HANDLE__: RNG Handle + * @param __HANDLE__ RNG Handle * @retval None */ #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) /** * @brief Enables the RNG peripheral. - * @param __HANDLE__: RNG Handle + * @param __HANDLE__ RNG Handle * @retval None */ #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN) /** * @brief Disables the RNG peripheral. - * @param __HANDLE__: RNG Handle + * @param __HANDLE__ RNG Handle * @retval None */ #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN) /** * @brief Check the selected RNG flag status. - * @param __HANDLE__: RNG Handle - * @param __FLAG__: RNG flag + * @param __HANDLE__ RNG Handle + * @param __FLAG__ RNG flag * This parameter can be one of the following values: * @arg RNG_FLAG_DRDY: Data ready * @arg RNG_FLAG_CECS: Clock error current status @@ -178,8 +176,8 @@ typedef struct /** * @brief Clears the selected RNG flag status. - * @param __HANDLE__: RNG handle - * @param __FLAG__: RNG flag to clear + * @param __HANDLE__ RNG handle + * @param __FLAG__ RNG flag to clear * @note WARNING: This is a dummy macro for HAL code alignment, * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only. * @retval None @@ -190,22 +188,22 @@ typedef struct /** * @brief Enables the RNG interrupts. - * @param __HANDLE__: RNG Handle + * @param __HANDLE__ RNG Handle * @retval None */ #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) /** * @brief Disables the RNG interrupts. - * @param __HANDLE__: RNG Handle + * @param __HANDLE__ RNG Handle * @retval None */ #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE) /** * @brief Checks whether the specified RNG interrupt has occurred or not. - * @param __HANDLE__: RNG Handle - * @param __INTERRUPT__: specifies the RNG interrupt status flag to check. + * @param __HANDLE__ RNG Handle + * @param __INTERRUPT__ specifies the RNG interrupt status flag to check. * This parameter can be one of the following values: * @arg RNG_IT_DRDY: Data ready interrupt * @arg RNG_IT_CEI: Clock error interrupt @@ -216,8 +214,8 @@ typedef struct /** * @brief Clear the RNG interrupt status flags. - * @param __HANDLE__: RNG Handle - * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear. + * @param __HANDLE__ RNG Handle + * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear. * This parameter can be one of the following values: * @arg RNG_IT_CEI: Clock error interrupt * @arg RNG_IT_SEI: Seed error interrupt diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.c index 46c141b311..b9b820b668 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -196,7 +194,7 @@ /** * @brief Initializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -254,7 +252,21 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Exit Initialization mode */ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + } + hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); @@ -270,7 +282,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /** * @brief DeInitializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @note This function doesn't reset the RTC Backup Data registers. * @retval HAL status @@ -371,7 +383,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /** * @brief Initializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -386,7 +398,7 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) /** * @brief DeInitializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -419,10 +431,10 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) /** * @brief Sets RTC current time. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. + * @param sTime Pointer to Time structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -544,10 +556,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Gets RTC current time. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. + * @param sTime Pointer to Time structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -596,10 +608,10 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Sets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. + * @param sDate Pointer to date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -638,9 +650,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat else { assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - datetmpreg = RTC_Bcd2ToByte(sDate->Month); assert_param(IS_RTC_MONTH(datetmpreg)); - datetmpreg = RTC_Bcd2ToByte(sDate->Date); assert_param(IS_RTC_DATE(datetmpreg)); datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ @@ -705,10 +715,10 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat /** * @brief Gets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. + * @param sDate Pointer to Date structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -763,10 +773,10 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ /** * @brief Sets the specified RTC Alarm. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -949,10 +959,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Sets the specified RTC Alarm with Interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -1136,9 +1146,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /** * @brief Deactivate the specified RTC Alarm - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Alarm: Specifies the Alarm. + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA * @arg RTC_ALARM_B: AlarmB @@ -1228,14 +1238,14 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /** * @brief Gets the RTC Alarm value and masks. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA * @arg RTC_ALARM_B: AlarmB - * @param Format: Specifies the format of the entered parameters. + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -1288,7 +1298,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief This function handles Alarm interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -1329,7 +1339,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /** * @brief Alarm A callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -1344,9 +1354,9 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles AlarmA Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -1407,7 +1417,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1453,7 +1463,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) */ /** * @brief Returns the RTC state. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL state */ @@ -1470,7 +1480,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) * @brief Enters the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1503,7 +1513,7 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) /** * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted + * @param Value Byte to be converted * @retval Converted byte */ uint8_t RTC_ByteToBcd2(uint8_t Value) @@ -1521,7 +1531,7 @@ uint8_t RTC_ByteToBcd2(uint8_t Value) /** * @brief Converts from 2 digit BCD to Binary. - * @param Value: BCD value to be converted + * @param Value BCD value to be converted * @retval Converted word */ uint8_t RTC_Bcd2ToByte(uint8_t Value) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h index 53d79cfdd4..8744804d6b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -424,14 +422,14 @@ typedef struct */ /** @brief Reset RTC handle state - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) /** * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ @@ -442,7 +440,7 @@ typedef struct /** * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ @@ -452,36 +450,36 @@ typedef struct /** * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) /** * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) /** * @brief Enable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) /** * @brief Disable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) /** * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt @@ -491,8 +489,8 @@ typedef struct /** * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt @@ -502,8 +500,8 @@ typedef struct /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt @@ -513,8 +511,8 @@ typedef struct /** * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag to check. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF @@ -526,8 +524,8 @@ typedef struct /** * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF @@ -538,8 +536,8 @@ typedef struct /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.c index 33938459a4..3d1ec3183d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extension peripheral: @@ -138,16 +136,16 @@ /** * @brief Sets TimeStamp. * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * @arg RTC_TIMESTAMPPIN_POS1: PI8/PA0 is selected as RTC TimeStamp Pin. @@ -199,17 +197,17 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /** * @brief Sets TimeStamp with Interrupt. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx, STM32F412xx, STM32F413xx and STM32F423xx devices) @@ -269,7 +267,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /** * @brief Deactivates TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -307,11 +305,11 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Gets the RTC TimeStamp value. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTimeStamp: Pointer to Time structure - * @param sTimeStampDate: Pointer to Date structure - * @param Format: specifies the format of the entered parameters. + * @param sTimeStamp Pointer to Time structure + * @param sTimeStampDate Pointer to Date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: * RTC_FORMAT_BIN: Binary data format * RTC_FORMAT_BCD: BCD data format @@ -364,9 +362,9 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe /** * @brief Sets Tamper * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTamper: Pointer to Tamper Structure. + * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) @@ -414,9 +412,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /** * @brief Sets Tamper with interrupt. * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTamper: Pointer to RTC Tamper. + * @param sTamper Pointer to RTC Tamper. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) @@ -483,9 +481,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /** * @brief Deactivates Tamper. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Tamper: Selected tamper pin. + * @param Tamper Selected tamper pin. * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2. * @retval HAL status */ @@ -511,7 +509,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T /** * @brief This function handles TimeStamp interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -566,7 +564,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief TimeStamp callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -581,7 +579,7 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 1 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -596,7 +594,7 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 2 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -611,9 +609,9 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles TimeStamp polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -654,9 +652,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /** * @brief This function handles Tamper1 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -690,9 +688,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief This function handles Tamper2 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -744,10 +742,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief Sets wake up timer. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) @@ -835,10 +833,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /** * @brief Sets wake up timer with interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) @@ -937,7 +935,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /** * @brief Deactivates wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -992,7 +990,7 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief Gets wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval Counter value */ @@ -1004,7 +1002,7 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief This function handles Wake Up Timer interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -1032,7 +1030,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief Wake Up Timer callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -1047,9 +1045,9 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles Wake Up Timer Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -1114,12 +1112,12 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /** * @brief Writes a data in a specified RTC Backup data register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. + * @param BackupRegister RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. + * @param Data Data to be written in the specified RTC Backup data register. * @retval None */ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) @@ -1138,9 +1136,9 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 /** * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. + * @param BackupRegister RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to * specify the register. * @retval Read value @@ -1161,13 +1159,13 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) /** * @brief Sets the Coarse calibration parameters. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param CalibSign: Specifies the sign of the coarse calibration value. + * @param CalibSign Specifies the sign of the coarse calibration value. * This parameter can be one of the following values : * @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive * @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative - * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). + * @param Value value of coarse calibration expressed in ppm (coded on 5 bits). * * @note This Calibration value should be between 0 and 63 when using negative * sign with a 2-ppm step. @@ -1230,7 +1228,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t Cal /** * @brief Deactivates the Coarse calibration parameters. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1281,18 +1279,18 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) /** * @brief Sets the Smooth calibration parameters. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. + * @param SmoothCalibPeriod Select the Smooth Calibration Period. * This parameter can be can be one of the following values : * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. * This parameter can be one of the following values: * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * @param SmouthCalibMinusPulsesValue Select the value of CALM[80] bits. * This parameter can be one any value from 0 to 0x000001FF. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field @@ -1359,13 +1357,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo /** * @brief Configures the Synchronization Shift Control Settings. * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. * This parameter can be one of the following values : * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. + * @param ShiftSubFS Select the number of Second Fractions to substitute. * This parameter can be one any value from 0 to 0x7FFF. * @retval HAL status */ @@ -1456,9 +1454,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /** * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param CalibOutput: Select the Calibration output Selection . + * @param CalibOutput Select the Calibration output Selection . * This parameter can be one of the following values: * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. @@ -1499,7 +1497,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 /** * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1529,7 +1527,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) /** * @brief Enables the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1579,7 +1577,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Disable the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1629,7 +1627,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Enables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. @@ -1662,7 +1660,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) /** * @brief Disables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. @@ -1714,7 +1712,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) /** * @brief Alarm B callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -1729,9 +1727,9 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles AlarmB Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.h index f28a024a0f..d7e940b500 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention @@ -334,22 +332,22 @@ typedef struct /** * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) /** * @brief Disable the RTC Wake-up Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) /** * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer A interrupt * @retval None @@ -358,8 +356,8 @@ typedef struct /** * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer A interrupt * @retval None @@ -368,8 +366,8 @@ typedef struct /** * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer A interrupt * @retval None @@ -378,8 +376,8 @@ typedef struct /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -388,8 +386,8 @@ typedef struct /** * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to check. * This parameter can be: * @arg RTC_FLAG_WUTF * @arg RTC_FLAG_WUTWF @@ -399,8 +397,8 @@ typedef struct /** * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled. * This parameter can be: * @arg RTC_FLAG_WUTF * @retval None @@ -501,22 +499,22 @@ typedef struct /** * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) /** * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) /** * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -525,8 +523,8 @@ typedef struct /** * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -535,8 +533,8 @@ typedef struct /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -545,8 +543,8 @@ typedef struct /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -555,8 +553,8 @@ typedef struct /** * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp flag to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp flag to check. * This parameter can be: * @arg RTC_FLAG_TSF * @arg RTC_FLAG_TSOVF @@ -566,8 +564,8 @@ typedef struct /** * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. * This parameter can be: * @arg RTC_FLAG_TSF * @retval None @@ -585,14 +583,14 @@ typedef struct /** * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E)) /** * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E)) @@ -600,14 +598,14 @@ typedef struct #if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx) /** * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E)) /** * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E)) @@ -615,8 +613,8 @@ typedef struct /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * This parameter can be: * @arg RTC_IT_TAMP1 * @arg RTC_IT_TAMP2 @@ -626,8 +624,8 @@ typedef struct /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. * This parameter can be: * @arg RTC_IT_TAMP: Tamper interrupt * @retval None @@ -636,8 +634,8 @@ typedef struct /** * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled. * This parameter can be: * @arg RTC_FLAG_TAMP1F * @arg RTC_FLAG_TAMP2F @@ -647,8 +645,8 @@ typedef struct /** * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: * @arg RTC_FLAG_TAMP1F * @arg RTC_FLAG_TAMP2F @@ -757,50 +755,50 @@ typedef struct /** * @brief Enable the Coarse calibration process. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE)) /** * @brief Disable the Coarse calibration process. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE)) /** * @brief Enable the RTC calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) /** * @brief Disable the calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) /** * @brief Enable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) /** * @brief Disable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) /** * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_SHPF * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c index 8f1eced632..0fba5e62c1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sai.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SAI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Audio Interface (SAI) peripheral: @@ -208,7 +206,6 @@ typedef enum { */ #define SAI_FIFO_SIZE 8U #define SAI_DEFAULT_TIMEOUT 4U /* 4ms */ -#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT) /** * @} */ @@ -284,12 +281,12 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); * @brief Initialize the structure FrameInit, SlotInit and the low part of * Init according to the specified parameters and call the function * HAL_SAI_Init to initialize the SAI block. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol @ref SAI_Protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol one of the supported protocol @ref SAI_Protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot: Number of slot. + * @param nbslot Number of slot. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) @@ -327,7 +324,7 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco /** * @brief Initialize the SAI according to the specified parameters. * in the SAI_InitTypeDef structure and initialize the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -498,7 +495,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI peripheral. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -539,7 +536,7 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) /** * @brief Initialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -555,7 +552,7 @@ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -597,17 +594,14 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) (+) Blocking mode functions are : (++) HAL_SAI_Transmit() (++) HAL_SAI_Receive() - (++) HAL_SAI_TransmitReceive() (+) Non Blocking mode functions with Interrupt are : (++) HAL_SAI_Transmit_IT() (++) HAL_SAI_Receive_IT() - (++) HAL_SAI_TransmitReceive_IT() (+) Non Blocking mode functions with DMA are : (++) HAL_SAI_Transmit_DMA() (++) HAL_SAI_Receive_DMA() - (++) HAL_SAI_TransmitReceive_DMA() (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_SAI_TxCpltCallback() @@ -620,11 +614,11 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout) @@ -720,11 +714,11 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint /** * @brief Receive an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -818,10 +812,10 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -880,10 +874,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -940,7 +934,7 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui /** * @brief Pause the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -960,7 +954,7 @@ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) /** * @brief Resume the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -987,7 +981,7 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) /** * @brief Stop the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1019,6 +1013,9 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Disable SAI peripheral */ SAI_Disable(hsai); + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + hsai->State = HAL_SAI_STATE_READY; /* Process Unlocked */ @@ -1029,7 +1026,7 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /** * @brief Abort the current transfer and disable the SAI. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1082,10 +1079,10 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1151,10 +1148,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1220,9 +1217,9 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Enable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param val: value sent during the mute @ref SAI_Block_Mute_Value + * @param val value sent during the mute @ref SAI_Block_Mute_Value * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) @@ -1240,7 +1237,7 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val /** * @brief Disable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1256,10 +1253,10 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Enable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param callback: function called when the mute is detected. - * @param counter: number a data before mute detection max 63. + * @param callback function called when the mute is detected. + * @param counter number a data before mute detection max 63. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) @@ -1270,7 +1267,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback { /* set the mute counter */ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT); - SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET)); + SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos)); hsai->mutecallback = callback; /* enable the IT interrupt */ __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET); @@ -1281,7 +1278,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback /** * @brief Disable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1300,7 +1297,7 @@ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Handle SAI interrupt request. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1483,7 +1480,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1499,7 +1496,7 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer Half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1515,7 +1512,7 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1531,7 +1528,7 @@ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1547,7 +1544,7 @@ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief SAI error callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1583,7 +1580,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI handle state. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL state */ @@ -1594,7 +1591,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI error code. -* @param hsai: pointer to a SAI_HandleTypeDef structure that contains +* @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for the specified SAI Block. * @retval SAI Error Code */ @@ -1618,12 +1615,12 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) /** * @brief Initialize the SAI I2S protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol. - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol one of the supported protocol. + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot: number of slot minimum value is 2 and max is 16. + * @param nbslot number of slot minimum value is 2 and max is 16. * the value must be a multiple of 2. * @retval HAL status */ @@ -1713,11 +1710,11 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, /** * @brief Initialize the SAI PCM protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize - * @param nbslot: number of slot minimum value is 1 and the max is 16. + * @param protocol one of the supported protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize + * @param nbslot number of slot minimum value is 1 and the max is 16. * @retval HAL status */ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) @@ -1783,7 +1780,7 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, /** * @brief Fill the fifo. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1812,9 +1809,9 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) /** * @brief Return the interrupt flag to set according the SAI setup. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param mode: SAI_MODE_DMA or SAI_MODE_IT + * @param mode SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable */ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) @@ -1846,7 +1843,7 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) /** * @brief Disable the SAI and wait for the disabling. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1875,7 +1872,7 @@ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1899,7 +1896,7 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1924,7 +1921,7 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1949,7 +1946,7 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1975,7 +1972,7 @@ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2002,7 +1999,7 @@ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2029,7 +2026,7 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief DMA SAI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2054,7 +2051,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI transmit process half complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2067,7 +2064,7 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2090,7 +2087,7 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2103,7 +2100,7 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2134,7 +2131,7 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI Abort callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.h index b8e66699dd..bb61647f98 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sai.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention @@ -568,14 +566,14 @@ typedef struct __SAI_HandleTypeDef */ /** @brief Reset SAI handle state - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval NoneS */ #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) /** @brief Enable or disable the specified SAI interrupts. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -590,9 +588,9 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) /** @brief Check if the specified SAI interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral. - * @param __INTERRUPT__: specifies the SAI interrupt source to check. + * @param __INTERRUPT__ specifies the SAI interrupt source to check. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -606,8 +604,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SAI flag is set or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. * @arg SAI_FLAG_MUTEDET: Mute detection flag. @@ -621,8 +619,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified SAI pending flag. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun * @arg SAI_FLAG_MUTEDET: Clear Mute detection @@ -636,13 +634,13 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) /** @brief Enable SAI - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval None */ #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) /** @brief Disable SAI - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval None */ #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.c index 9e2c390e42..e2fd428c0e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sai_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SAI Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of SAI extension peripheral: @@ -109,7 +107,7 @@ /** * @brief Configure SAI Block synchronization mode - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval SAI Clock Input */ @@ -170,7 +168,7 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai) } /** * @brief Get SAI Input Clock based on SAI source clock selection - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval SAI Clock Input */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.h index c00741ef45..9fd3fe1d5c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sai_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SAI Extension HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.c index b93eaa18a7..e8e3995830 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sd.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: @@ -303,7 +301,7 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma); /** * @brief Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle. - * @param hsd: Pointer to the SD handle + * @param hsd Pointer to the SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) @@ -350,7 +348,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) /** * @brief Initializes the SD Card. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @note This function initializes the SD card. It could be used when a card re-initialization is needed. * @retval HAL status @@ -407,7 +405,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /** * @brief De-Initializes the SD card. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) @@ -438,7 +436,7 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) /** * @brief Initializes the SD MSP. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval None */ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) @@ -453,7 +451,7 @@ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) /** * @brief De-Initialize SD MSP. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval None */ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) @@ -490,11 +488,11 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) * is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @param hsd: Pointer to SD handle - * @param pData: pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of SD blocks to read - * @param Timeout: Specify timeout value + * @param hsd Pointer to SD handle + * @param pData pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of SD blocks to read + * @param Timeout Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) @@ -680,11 +678,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 * transfer is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @param hsd: Pointer to SD handle - * @param pData: pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of SD blocks to write - * @param Timeout: Specify timeout value + * @param hsd Pointer to SD handle + * @param pData pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of SD blocks to write + * @param Timeout Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) @@ -857,10 +855,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint * HAL_SD_GetCardState(). * @note You could also check the IT transfer process through the SD Rx * interrupt event. - * @param hsd: Pointer to SD handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. + * @param hsd Pointer to SD handle + * @param pData Pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -962,10 +960,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui * HAL_SD_GetCardState(). * @note You could also check the IT transfer process through the SD Tx * interrupt event. - * @param hsd: Pointer to SD handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write + * @param hsd Pointer to SD handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1068,10 +1066,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u * HAL_SD_GetCardState(). * @note You could also check the DMA transfer process through the SD Rx * interrupt event. - * @param hsd: Pointer SD handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. + * @param hsd Pointer SD handle + * @param pData Pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1185,10 +1183,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u * HAL_SD_GetCardState(). * @note You could also check the DMA transfer process through the SD Tx * interrupt event. - * @param hsd: Pointer to SD handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write + * @param hsd Pointer to SD handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1300,9 +1298,9 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, * @brief Erases the specified memory area of the given SD card. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @param hsd: Pointer to SD handle - * @param BlockStartAdd: Start Block address - * @param BlockEndAdd: End Block address + * @param hsd Pointer to SD handle + * @param BlockStartAdd Start Block address + * @param BlockEndAdd End Block address * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) @@ -1402,7 +1400,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /** * @brief This function handles SD card interrupt request. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval None */ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) @@ -1624,7 +1622,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) /** * @brief return the SD state - * @param hsd: Pointer to sd handle + * @param hsd Pointer to sd handle * @retval HAL state */ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) @@ -1634,7 +1632,7 @@ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) /** * @brief Return the SD error code -* @param hsd : Pointer to a SD_HandleTypeDef structure that contains +* @param hsd Pointer to a SD_HandleTypeDef structure that contains * the configuration information. * @retval SD Error Code */ @@ -1645,7 +1643,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) /** * @brief Tx Transfer completed callbacks - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval None */ __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) @@ -1660,7 +1658,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) /** * @brief Rx Transfer completed callbacks - * @param hsd: Pointer SD handle + * @param hsd Pointer SD handle * @retval None */ __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) @@ -1675,7 +1673,7 @@ __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) /** * @brief SD error callbacks - * @param hsd: Pointer SD handle + * @param hsd Pointer SD handle * @retval None */ __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) @@ -1690,7 +1688,7 @@ __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) /** * @brief SD Abort callbacks - * @param hsd: Pointer SD handle + * @param hsd Pointer SD handle * @retval None */ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) @@ -1726,8 +1724,8 @@ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) /** * @brief Returns information the information of the card which are stored on * the CID register. - * @param hsd: Pointer to SD handle - * @param pCID: Pointer to a HAL_SD_CIDTypeDef structure that + * @param hsd Pointer to SD handle + * @param pCID Pointer to a HAL_SD_CIDTypeDef structure that * contains all CID register parameters * @retval HAL status */ @@ -1807,8 +1805,8 @@ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef /** * @brief Returns information the information of the card which are stored on * the CSD register. - * @param hsd: Pointer to SD handle - * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that + * @param hsd Pointer to SD handle + * @param pCSD Pointer to a HAL_SD_CardCSDTypeDef structure that * contains all CSD register parameters * @retval HAL status */ @@ -1954,8 +1952,8 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef /** * @brief Gets the SD status info. - * @param hsd: Pointer to SD handle - * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that + * @param hsd Pointer to SD handle + * @param pStatus Pointer to the HAL_SD_CardStatusTypeDef structure that * will contain the SD card status information * @retval HAL status */ @@ -2042,8 +2040,8 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT /** * @brief Gets the SD card info. - * @param hsd: Pointer to SD handle - * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that + * @param hsd Pointer to SD handle + * @param pCardInfo Pointer to the HAL_SD_CardInfoTypeDef structure that * will contain the SD card status information * @retval HAL status */ @@ -2064,8 +2062,8 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeD /** * @brief Enables wide bus operation for the requested card if supported by * card. - * @param hsd: Pointer to SD handle - * @param WideMode: Specifies the SD card wide bus mode + * @param hsd Pointer to SD handle + * @param WideMode Specifies the SD card wide bus mode * This parameter can be one of the following values: * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer @@ -2141,7 +2139,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t /** * @brief Gets the current sd card data state. - * @param hsd: pointer to SD handle + * @param hsd pointer to SD handle * @retval Card state */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) @@ -2163,7 +2161,7 @@ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) /** * @brief Abort the current transfer and disable the SD. - * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * @param hsd pointer to a SD_HandleTypeDef structure that contains * the configuration information for SD module. * @retval HAL status */ @@ -2210,7 +2208,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) /** * @brief Abort the current transfer and disable the SD (IT mode). - * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * @param hsd pointer to a SD_HandleTypeDef structure that contains * the configuration information for SD module. * @retval HAL status */ @@ -2287,7 +2285,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) /** * @brief DMA SD transmit process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -2300,7 +2298,7 @@ static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SD receive process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -2333,7 +2331,7 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SD communication error callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SD_DMAError(DMA_HandleTypeDef *hdma) @@ -2365,7 +2363,7 @@ static void SD_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA SD Tx Abort callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) @@ -2402,7 +2400,7 @@ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) /** * @brief DMA SD Rx Abort callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) @@ -2440,7 +2438,7 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) /** * @brief Initializes the sd card. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval SD Card error state */ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) @@ -2529,7 +2527,7 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) * @brief Enquires cards about their operating voltage and configures clock * controls and stores SD information that will be needed in future * in the SD handle. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval error state */ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) @@ -2630,7 +2628,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /** * @brief Turns the SDIO output signals off. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval HAL status */ static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd) @@ -2643,8 +2641,8 @@ static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd) /** * @brief Send Status info command. - * @param hsd: pointer to SD handle - * @param pSDstatus: Pointer to the buffer that will contain the SD card status + * @param hsd pointer to SD handle + * @param pSDstatus Pointer to the buffer that will contain the SD card status * SD Status register) * @retval error state */ @@ -2745,8 +2743,8 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) /** * @brief Returns the current card's status. - * @param hsd: Pointer to SD handle - * @param pCardStatus: pointer to the buffer that will contain the SD card + * @param hsd Pointer to SD handle + * @param pCardStatus pointer to the buffer that will contain the SD card * status (Card Status register) * @retval error state */ @@ -2774,7 +2772,7 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) /** * @brief Enables the SDIO wide bus mode. - * @param hsd: pointer to SD handle + * @param hsd pointer to SD handle * @retval error state */ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) @@ -2821,7 +2819,7 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) /** * @brief Disables the SDIO wide bus mode. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval error state */ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) @@ -2869,8 +2867,8 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) /** * @brief Finds the SD card SCR register value. - * @param hsd: Pointer to SD handle - * @param pSCR: pointer to the buffer that will contain the SCR value + * @param hsd Pointer to SD handle + * @param pSCR pointer to the buffer that will contain the SCR value * @retval error state */ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) @@ -2960,7 +2958,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /** * @brief Wrap up reading in non-blocking mode. - * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * @param hsd pointer to a SD_HandleTypeDef structure that contains * the configuration information. * @retval HAL status */ @@ -2984,7 +2982,7 @@ static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd) /** * @brief Wrap up writing in non-blocking mode. - * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * @param hsd pointer to a SD_HandleTypeDef structure that contains * the configuration information. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.h index 0d8daacc42..ba29ad5973 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sd.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SD HAL module. ****************************************************************************** * @attention @@ -389,8 +387,8 @@ typedef struct /** * @brief Enable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -420,8 +418,8 @@ typedef struct /** * @brief Disable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -451,8 +449,8 @@ typedef struct /** * @brief Check whether the specified SD flag is set or not. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ SD Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -482,8 +480,8 @@ typedef struct /** * @brief Clear the SD's pending flags. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ SD Handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -502,8 +500,8 @@ typedef struct /** * @brief Check whether the specified SD interrupt has occurred or not. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -533,8 +531,8 @@ typedef struct /** * @brief Clear the SD's interrupt pending bits. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.c index 3d4aaa91cd..809ef0762e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sdram.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SDRAM HAL module driver. * This file provides a generic firmware to drive SDRAM memories mounted * as external device. @@ -132,9 +130,9 @@ /** * @brief Performs the SDRAM device initialization sequence. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param Timing: Pointer to SDRAM control timing structure + * @param Timing Pointer to SDRAM control timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) @@ -170,7 +168,7 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy /** * @brief Perform the SDRAM device initialization sequence. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status */ @@ -193,7 +191,7 @@ HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) /** * @brief SDRAM MSP Init. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval None */ @@ -208,7 +206,7 @@ __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) /** * @brief SDRAM MSP DeInit. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval None */ @@ -223,7 +221,7 @@ __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) /** * @brief This function handles SDRAM refresh error interrupt request. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status */ @@ -242,7 +240,7 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) /** * @brief SDRAM Refresh error callback. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval None */ @@ -257,7 +255,7 @@ __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -272,7 +270,7 @@ __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) @@ -303,11 +301,11 @@ __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) /** * @brief Reads 8-bit data buffer from the SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) @@ -343,11 +341,11 @@ HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddr /** * @brief Writes 8-bit data buffer to SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) @@ -386,11 +384,11 @@ HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Reads 16-bit data buffer from the SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) @@ -426,11 +424,11 @@ HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Writes 16-bit data buffer to SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) @@ -469,11 +467,11 @@ HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /** * @brief Reads 32-bit data buffer from the SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -509,11 +507,11 @@ HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Writes 32-bit data buffer to SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -552,11 +550,11 @@ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /** * @brief Reads a Words data from the SDRAM memory using DMA transfer. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -593,11 +591,11 @@ HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -652,7 +650,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /** * @brief Enables dynamically SDRAM write protection. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status */ @@ -678,7 +676,7 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) /** * @brief Disables dynamically SDRAM write protection. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status */ @@ -704,10 +702,10 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) /** * @brief Sends Command to the SDRAM bank. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param Command: SDRAM command structure - * @param Timeout: Timeout duration + * @param Command SDRAM command structure + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) @@ -739,9 +737,9 @@ HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_C /** * @brief Programs the SDRAM Memory Refresh rate. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param RefreshRate: The SDRAM refresh rate value + * @param RefreshRate The SDRAM refresh rate value * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) @@ -766,9 +764,9 @@ HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint /** * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param AutoRefreshNumber: The SDRAM auto Refresh number + * @param AutoRefreshNumber The SDRAM auto Refresh number * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) @@ -793,7 +791,7 @@ HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, ui /** * @brief Returns the SDRAM memory current mode. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval The SDRAM memory mode. */ @@ -824,7 +822,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) /** * @brief Returns the SDRAM state. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL state */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.h index 1ab391e43c..1eab5e4add 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sdram.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SDRAM HAL module. ****************************************************************************** * @attention @@ -103,7 +101,7 @@ typedef struct */ /** @brief Reset SDRAM handle state - * @param __HANDLE__: specifies the SDRAM handle. + * @param __HANDLE__ specifies the SDRAM handle. * @retval None */ #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c index e08f974c4c..42458facfa 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_smartcard.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -238,7 +236,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /** * @brief Initializes the SmartCard mode according to the specified * parameters in the SMARTCARD_InitTypeDef and create the associated handle . - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval HAL status */ @@ -304,7 +302,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) /** * @brief DeInitializes the USART SmartCard peripheral - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval HAL status */ @@ -339,7 +337,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) /** * @brief SMARTCARD MSP Init - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval None */ @@ -354,7 +352,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) /** * @brief SMARTCARD MSP DeInit - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval None */ @@ -425,11 +423,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) /** * @brief Send an amount of data in blocking mode - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -488,11 +486,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * /** * @brief Receive an amount of data in blocking mode - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -526,7 +524,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p { return HAL_TIMEOUT; } +/* MBED */ *pData = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); +/* MBED */ pData +=1U; } @@ -546,10 +546,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p /** * @brief Send an amount of data in non blocking mode - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) @@ -594,10 +594,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ /** * @brief Receive an amount of data in non blocking mode - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @param pData pointer to data buffer + * @param Size amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) @@ -639,10 +639,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t /** * @brief Send an amount of data in non blocking mode - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) @@ -700,10 +700,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 /** * @brief Receive an amount of data in non blocking mode - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @param pData pointer to data buffer + * @param Size amount of data to be received * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s * @retval HAL status */ @@ -1168,7 +1168,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc) /** * @brief This function handles SMARTCARD interrupt request. - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval None */ @@ -1293,7 +1293,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) /** * @brief Tx Transfer completed callbacks - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval None */ @@ -1308,7 +1308,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) /** * @brief Rx Transfer completed callbacks - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval None */ @@ -1323,7 +1323,7 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) /** * @brief SMARTCARD error callbacks - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval None */ @@ -1402,7 +1402,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc /** * @brief return the SMARTCARD state - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval HAL state */ @@ -1417,7 +1417,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) /** * @brief Return the SMARTCARD error code - * @param hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD. * @retval SMARTCARD Error Code */ @@ -1432,7 +1432,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) /** * @brief DMA SMARTCARD transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1452,7 +1452,7 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SMARTCARD receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1478,7 +1478,7 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SMARTCARD communication error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1509,11 +1509,11 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function handles SMARTCARD Communication Timeout. - * @param hsc: SMARTCARD handle - * @param Flag: specifies the SMARTCARD flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param hsc SMARTCARD handle + * @param Flag specifies the SMARTCARD flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) @@ -1545,7 +1545,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe /** * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). - * @param hsc: SMARTCARD handle. + * @param hsc SMARTCARD handle. * @retval None */ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc) @@ -1560,7 +1560,7 @@ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc) /** * @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion). - * @param hsc: SMARTCARD handle. + * @param hsc SMARTCARD handle. * @retval None */ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc) @@ -1575,7 +1575,7 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc) /** * @brief Send an amount of data in non blocking mode - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval HAL status */ @@ -1609,7 +1609,7 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) /** * @brief Wraps up transmission in non blocking mode. - * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -1631,7 +1631,7 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar /** * @brief Receive an amount of data in non blocking mode - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval HAL status */ @@ -1806,7 +1806,7 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Configure the SMARTCARD peripheral - * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.h index b9f7612c84..51d2c8239e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_smartcard.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention @@ -390,7 +388,7 @@ typedef struct */ /** @brief Reset SMARTCARD handle gstate & RxState - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -399,13 +397,13 @@ typedef struct } while(0U) /** @brief Flushs the Smartcard DR register - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. */ #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) /** @brief Checks whether the specified Smartcard flag is set or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag * @arg SMARTCARD_FLAG_TC: Transmission Complete flag @@ -420,8 +418,8 @@ typedef struct #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** @brief Clears the specified Smartcard pending flags. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg SMARTCARD_FLAG_TC: Transmission Complete flag. * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag. @@ -437,7 +435,7 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** @brief Clear the SMARTCARD PE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * SMARTCARD peripheral. * @retval None @@ -451,7 +449,7 @@ typedef struct } while(0U) /** @brief Clear the SMARTCARD FE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * SMARTCARD peripheral. * @retval None @@ -459,7 +457,7 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the SMARTCARD NE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * SMARTCARD peripheral. * @retval None @@ -467,7 +465,7 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the SMARTCARD ORE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * SMARTCARD peripheral. * @retval None @@ -475,7 +473,7 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the SMARTCARD IDLE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * SMARTCARD peripheral. * @retval None @@ -483,8 +481,8 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) /** @brief Enables or disables the specified SmartCard interrupts. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt source to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt * @arg SMARTCARD_IT_TC: Transmission complete interrupt @@ -499,8 +497,8 @@ typedef struct ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK))) /** @brief Checks whether the specified SmartCard interrupt has occurred or not. - * @param __HANDLE__: specifies the SmartCard Handle. - * @param __IT__: specifies the SMARTCARD interrupt source to check. + * @param __HANDLE__ specifies the SmartCard Handle. + * @param __IT__ specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt * @arg SMARTCARD_IT_TC: Transmission complete interrupt @@ -513,34 +511,34 @@ typedef struct #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK)) /** @brief Macro to enable the SMARTCARD's one bit sample method - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Macro to disable the SMARTCARD's one bit sample method - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable the USART associated to the SMARTCARD Handle - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) /** @brief Macros to enable or disable the SmartCard DMA request. - * @param __HANDLE__: specifies the SmartCard Handle. - * @param __REQUEST__: specifies the SmartCard DMA request. + * @param __HANDLE__ specifies the SmartCard Handle. + * @param __REQUEST__ specifies the SmartCard DMA request. * This parameter can be one of the following values: * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.c index bf451985d0..1ba35b1d86 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_spdifrx.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the SPDIFRX audio interface: * + Initialization and Configuration @@ -197,7 +195,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef * /** * @brief Initializes the SPDIFRX according to the specified parameters * in the SPDIFRX_InitTypeDef and create the associated handle. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) @@ -268,7 +266,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) /** * @brief DeInitializes the SPDIFRX peripheral - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) @@ -303,7 +301,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) /** * @brief SPDIFRX MSP Init - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) @@ -317,7 +315,7 @@ __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) /** * @brief SPDIFRX MSP DeInit - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) @@ -332,8 +330,8 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Sets the SPDIFRX dtat format according to the specified parameters * in the SPDIFRX_InitTypeDef. - * @param hspdif: SPDIFRX handle - * @param sDataFormat: SPDIFRX data format + * @param hspdif SPDIFRX handle + * @param sDataFormat SPDIFRX data format * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat) @@ -428,11 +426,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF /** * @brief Receives an amount of data (Data Flow) in blocking mode. - * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains + * @param hspdif pointer to SPDIFRX_HandleTypeDef structure that contains * the configuration information for SPDIFRX module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) @@ -490,11 +488,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin /** * @brief Receives an amount of data (Control Flow) in blocking mode. - * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains + * @param hspdif pointer to a SPDIFRX_HandleTypeDef structure that contains * the configuration information for SPDIFRX module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) @@ -551,9 +549,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, } /** * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be received . + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample to be received . * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -634,9 +632,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, /** * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample (Control Flow) to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample (Control Flow) to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -717,9 +715,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi /** * @brief Receive an amount of data (Data Flow) mode with DMA - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -804,9 +802,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, /** * @brief Receive an amount of data (Control Flow) with DMA - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data (Control Flow) sample to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data (Control Flow) sample to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -891,7 +889,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd /** * @brief stop the audio stream receive from the Media. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) @@ -920,7 +918,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) /** * @brief This function handles SPDIFRX interrupt request. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) @@ -966,7 +964,7 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Rx Transfer (Data flow) half completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -980,7 +978,7 @@ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Rx Transfer (Data flow) completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -994,7 +992,7 @@ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Rx (Control flow) Transfer half completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -1008,7 +1006,7 @@ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Rx Transfer (Control flow) completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -1022,7 +1020,7 @@ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) /** * @brief SPDIFRX error callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -1055,7 +1053,7 @@ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Return the SPDIFRX state - * @param hspdif : SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL state */ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif) @@ -1065,7 +1063,7 @@ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Return the SPDIFRX error code - * @param hspdif : SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval SPDIFRX Error Code */ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif) @@ -1079,7 +1077,7 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif) /** * @brief DMA SPDIFRX receive process (Data flow) complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -1096,7 +1094,7 @@ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPDIFRX receive process (Data flow) half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1108,7 +1106,7 @@ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPDIFRX receive process (Control flow) complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) @@ -1125,7 +1123,7 @@ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPDIFRX receive process (Control flow) half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1137,7 +1135,7 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPDIFRX communication error callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) @@ -1157,7 +1155,7 @@ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Receive an amount of data (Data Flow) with Interrupt - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) @@ -1182,7 +1180,7 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) @@ -1207,10 +1205,10 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) /** * @brief This function handles SPDIFRX Communication Timeout. - * @param hspdif: SPDIFRX handle - * @param Flag: Flag checked - * @param Status: Value of the flag expected - * @param Timeout: Duration of the timeout + * @param hspdif SPDIFRX handle + * @param Flag Flag checked + * @param Status Value of the flag expected + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.h index 6d8f577565..e2d59cc657 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_spdifrx.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SPDIFRX HAL module. ****************************************************************************** * @attention @@ -342,33 +340,33 @@ typedef struct */ /** @brief Reset SPDIFRX handle state - * @param __HANDLE__: SPDIFRX handle. + * @param __HANDLE__ SPDIFRX handle. * @retval None */ #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN) /** @brief Disable the specified SPDIFRX peripheral (IDLE State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE) /** @brief Enable the specified SPDIFRX peripheral (SYNC State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC) /** @brief Enable the specified SPDIFRX peripheral (RCV State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV) /** @brief Enable or disable the specified SPDIFRX interrupts. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SPDIFRX_IT_RXNE * @arg SPDIFRX_IT_CSRNE @@ -383,8 +381,8 @@ typedef struct #define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __INTERRUPT__ specifies the SPDIFRX interrupt source to check. * This parameter can be one of the following values: * @arg SPDIFRX_IT_RXNE * @arg SPDIFRX_IT_CSRNE @@ -398,8 +396,8 @@ typedef struct #define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified SPDIFRX flag is set or not. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPDIFRX_FLAG_RXNE * @arg SPDIFRX_FLAG_CSRNE @@ -415,8 +413,8 @@ typedef struct #define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg SPDIFRX_FLAG_PERR diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c index 86e0b29347..2d29984763 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -191,7 +189,9 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart); +/* MBED */ static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +/* MBED */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); @@ -257,7 +257,7 @@ static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Tim /** * @brief Initialize the SPI according to the specified parameters * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -339,7 +339,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /** * @brief De Initialize the SPI peripheral. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -373,7 +373,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -388,7 +388,7 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -440,11 +440,11 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) /** * @brief Transmit an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -569,7 +569,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint } /* Wait until TXE flag */ +/* MBED */ if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK) +/* MBED */ { errorcode = HAL_TIMEOUT; goto error; @@ -610,11 +612,11 @@ error: /** * @brief Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -806,12 +808,12 @@ error : /** * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received - * @param Timeout: Timeout duration + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -1003,7 +1005,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ /* Wait until TXE flag */ +/* MBED */ if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK) +/* MBED */ { errorcode = HAL_TIMEOUT; goto error; @@ -1031,10 +1035,10 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1121,10 +1125,10 @@ error : /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1212,11 +1216,11 @@ error : /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -1299,10 +1303,10 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1391,11 +1395,11 @@ error : /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer + * @param pData pointer to data buffer * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1487,12 +1491,12 @@ error: /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -1856,7 +1860,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /** * @brief Pause the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -1876,7 +1880,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) /** * @brief Resume the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -1896,7 +1900,7 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) /** * @brief Stop the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -1927,7 +1931,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) /** * @brief Handle SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ @@ -2023,7 +2027,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /** * @brief Tx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2038,7 +2042,7 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2053,7 +2057,7 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2068,7 +2072,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2083,7 +2087,7 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2098,7 +2102,7 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Half Transfer callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2113,7 +2117,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief SPI error callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2165,7 +2169,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI handle state. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI state */ @@ -2177,7 +2181,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI error code. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI error code in bitmap format */ @@ -2202,7 +2206,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) /** * @brief DMA SPI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2246,7 +2250,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2313,7 +2317,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2377,7 +2381,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2390,7 +2394,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2403,7 +2407,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2416,7 +2420,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2551,7 +2555,7 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2585,7 +2589,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2612,7 +2616,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2645,7 +2649,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2679,7 +2683,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2703,7 +2707,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2739,7 +2743,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 8-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2759,7 +2763,7 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2792,7 +2796,7 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2815,7 +2819,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2848,7 +2852,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2866,14 +2870,16 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ +/* MBED */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); +/* MBED */ SPI_CloseTx_ISR(hspi); } } /** * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2893,24 +2899,28 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ +/* MBED */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); +/* MBED */ SPI_CloseTx_ISR(hspi); } } /** * @brief Handle SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param State: flag state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { +/* MBED */ while((hspi->Instance->SR & Flag) != State) +/* MBED */ { if(Timeout != HAL_MAX_DELAY) { @@ -2948,6 +2958,7 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_OK; } +/* MBED */ /** * @brief Handle SPI Communication Timeout. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains @@ -2997,13 +3008,14 @@ static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hsp return HAL_OK; } +/* MBED */ /** * @brief Handle to check BSY flag before start a new transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3019,7 +3031,7 @@ static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Tim /** * @brief Handle the end of the RXTX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3093,7 +3105,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the RX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3142,7 +3154,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the TX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3197,7 +3209,7 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Tx or Rx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3232,7 +3244,7 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Tx or Rx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h index 9ba8dd358f..933f409995 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -308,16 +306,16 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) /** @brief Enable or disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -328,9 +326,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) /** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -340,9 +338,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -356,14 +354,14 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -376,7 +374,7 @@ typedef struct __SPI_HandleTypeDef } while(0U) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -389,7 +387,7 @@ typedef struct __SPI_HandleTypeDef } while(0U) /** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -401,14 +399,14 @@ typedef struct __SPI_HandleTypeDef }while(0U) /** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) /** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -491,21 +489,21 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); */ /** @brief Set the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) /** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.c index 9f740f6695..eb513b593d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sram.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. @@ -135,10 +133,10 @@ /** * @brief Performs the SRAM device initialization sequence - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param Timing: Pointer to SRAM control timing structure - * @param ExtTiming: Pointer to SRAM extended mode timing structure + * @param Timing Pointer to SRAM control timing structure + * @param ExtTiming Pointer to SRAM extended mode timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) @@ -174,7 +172,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp /** * @brief Performs the SRAM device De-initialization sequence. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -196,7 +194,7 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) /** * @brief SRAM MSP Init. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -211,7 +209,7 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) /** * @brief SRAM MSP DeInit. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -226,7 +224,7 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -241,7 +239,7 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete error callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -274,11 +272,11 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) /** * @brief Reads 8-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) @@ -310,11 +308,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress /** * @brief Writes 8-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) @@ -352,11 +350,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Reads 16-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) @@ -388,11 +386,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Writes 16-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) @@ -430,11 +428,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Reads 32-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -464,11 +462,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Writes 32-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -504,11 +502,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Reads a Words data from the SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -537,11 +535,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Writes a Words data buffer to SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -595,7 +593,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Enables dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -618,7 +616,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) /** * @brief Disables dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -663,7 +661,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) /** * @brief Returns the SRAM controller state - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL state */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.h index 29687ffa65..224fabcb58 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sram.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention @@ -116,7 +114,7 @@ typedef struct * @{ */ /** @brief Reset SRAM handle state - * @param __HANDLE__: SRAM handle + * @param __HANDLE__ SRAM handle * @retval None */ #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c index ea68dd1fa7..89db4b6165 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -201,7 +199,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -240,7 +238,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM Base peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -268,7 +266,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -283,7 +281,7 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -298,7 +296,7 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -322,7 +320,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -346,7 +344,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -367,7 +365,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -387,10 +385,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to peripheral. + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -434,7 +432,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -483,7 +481,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -522,7 +520,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -550,7 +548,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -565,7 +563,7 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Output Compare MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -580,9 +578,9 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -613,9 +611,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -646,9 +644,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -713,9 +711,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -780,16 +778,16 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -900,9 +898,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -995,7 +993,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1034,7 +1032,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1062,7 +1060,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1077,7 +1075,7 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM PWM MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1092,9 +1090,9 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1125,9 +1123,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1161,9 +1159,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1228,9 +1226,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1295,16 +1293,16 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1415,9 +1413,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1510,7 +1508,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1549,7 +1547,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1577,7 +1575,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM INput Capture MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1592,7 +1590,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Input Capture MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1607,9 +1605,9 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1634,9 +1632,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1661,9 +1659,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1721,9 +1719,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1782,16 +1780,16 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1898,9 +1896,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1988,9 +1986,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OnePulseMode: Select the One pulse mode. + * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. @@ -2038,7 +2036,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /** * @brief DeInitializes the TIM One Pulse - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -2066,7 +2064,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2081,7 +2079,7 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM One Pulse MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2096,9 +2094,9 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2133,9 +2131,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be disable. + * @param OutputChannel TIM Channels to be disable. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2170,9 +2168,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2213,9 +2211,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2279,9 +2277,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Encoder Interface configuration structure + * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) @@ -2369,7 +2367,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** * @brief DeInitializes the TIM Encoder interface - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -2397,7 +2395,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2412,7 +2410,7 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2427,9 +2425,9 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2470,9 +2468,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2514,9 +2512,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2563,9 +2561,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2615,16 +2613,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1: The destination Buffer address for IC1. - * @param pData2: The destination Buffer address for IC2. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) @@ -2736,9 +2734,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2804,7 +2802,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ /** * @brief This function handles TIM interrupts requests. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2960,10 +2958,10 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Output Compare configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3030,10 +3028,10 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Input Capture configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3127,10 +3125,10 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM PWM configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3226,14 +3224,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM One Pulse configuration structure - * @param OutputChannel: TIM Channels to be enabled. + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel: TIM Channels to be enabled. + * @param InputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3339,9 +3337,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write. + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write. * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3362,7 +3360,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources. + * @param BurstRequestSrc TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3371,8 +3369,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ @@ -3503,9 +3501,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM DMA Burst mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstRequestSrc: TIM DMA Request sources to disable + * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3564,9 +3562,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read. + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read. * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3587,7 +3585,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources. + * @param BurstRequestSrc TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3596,8 +3594,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ @@ -3729,9 +3727,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Stop the DMA burst reading - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstRequestSrc: TIM DMA Request sources to disable. + * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3790,9 +3788,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu /** * @brief Generate a software event - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param EventSource: specifies the event source. + * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source @@ -3833,11 +3831,11 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS /** * @brief Configures the OCRef clear feature - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel. + * @param Channel specifies the TIM Channel. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3942,9 +3940,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp /** * @brief Configures the clock source to be used - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ @@ -4099,9 +4097,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param TI1_Selection: Indicate whether or not channel 1 is connected to the + * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input @@ -4134,9 +4132,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /** * @brief Configures the TIM in Slave mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4170,8 +4168,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI /** * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4206,9 +4204,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, /** * @brief Read the captured value from Capture Compare unit - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -4299,7 +4297,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Period elapsed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4314,7 +4312,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /** * @brief Output Compare callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4329,7 +4327,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) /** * @brief Input Capture callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4344,7 +4342,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) /** * @brief PWM Pulse finished callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4359,7 +4357,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Trigger detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4374,7 +4372,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) /** * @brief Timer error callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4407,7 +4405,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Base state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4418,7 +4416,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4429,7 +4427,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM PWM state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4440,7 +4438,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Input Capture state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4451,7 +4449,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM One Pulse Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4462,7 +4460,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4476,8 +4474,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) /** * @brief Time Base configuration - * @param TIMx: TIM peripheral - * @param Structure: pointer on TIM Time Base required parameters + * @param TIMx TIM peripheral + * @param Structure pointer on TIM Time Base required parameters * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) @@ -4522,17 +4520,17 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be @@ -4578,7 +4576,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /** * @brief Time Output Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4644,7 +4642,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4678,7 +4676,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4693,7 +4691,7 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Capture complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4728,13 +4726,13 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @arg TIM_Channel_4: TIM Channel 4 - * @param ChannelState: specifies the TIM Channel CCxE bit new state. + * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. * @retval None */ @@ -4757,7 +4755,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4772,7 +4770,7 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Trigger callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4788,7 +4786,7 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) /** * @brief Time Output Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4853,7 +4851,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Output Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4921,7 +4919,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Output Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4977,9 +4975,9 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Output Compare 4 configuration - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sSlaveConfig: The slave configuration structure + * @param sSlaveConfig The slave configuration structure * @retval None */ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -5110,12 +5108,12 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5145,17 +5143,17 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be @@ -5193,12 +5191,12 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5228,17 +5226,17 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be @@ -5276,17 +5274,17 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be @@ -5324,7 +5322,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral - * @param TIM_ITRx: The Input Trigger source. + * @param TIM_ITRx The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 @@ -5353,17 +5351,17 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx) /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. + * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h index 35172181f9..0600fb28fa 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -853,21 +851,21 @@ typedef struct * @{ */ /** @brief Reset TIM handle state - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) /** * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) @@ -875,7 +873,7 @@ typedef struct /** * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ @@ -893,7 +891,7 @@ typedef struct channels have been disabled */ /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ @@ -909,15 +907,15 @@ typedef struct /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled unconditionally */ #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** @brief Enable the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -933,8 +931,8 @@ typedef struct /** @brief Disable the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -949,8 +947,8 @@ typedef struct #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** @brief Enable the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -964,8 +962,8 @@ typedef struct #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** @brief Disable the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -979,8 +977,8 @@ typedef struct #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to check. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1003,8 +1001,8 @@ typedef struct #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) /** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to clear. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1028,8 +1026,8 @@ typedef struct /** * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1044,8 +1042,8 @@ typedef struct #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1061,7 +1059,7 @@ typedef struct /** * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. @@ -1070,8 +1068,8 @@ mode. /** * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__: TIM handle. - * @param __PRESC__: specifies the Prescaler new value. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) @@ -1103,14 +1101,14 @@ mode. /** * @brief Sets the TIM Capture Compare Register value on runtime without * calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__: specifies the Capture Compare register new value. + * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ @@ -1118,8 +1116,8 @@ mode. /** * @brief Gets the TIM Capture Compare Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channel associated with the capture compare register + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value @@ -1134,15 +1132,15 @@ mode. /** * @brief Sets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __COUNTER__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Gets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) @@ -1150,8 +1148,8 @@ mode. /** * @brief Sets the TIM Autoreload Register value on runtime without calling * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __AUTORELOAD__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ @@ -1161,15 +1159,15 @@ mode. } while(0U) /** * @brief Gets the TIM Autoreload Register value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Sets the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __CKD__: specifies the clock division value. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT @@ -1184,7 +1182,7 @@ mode. } while(0U) /** * @brief Gets the TIM Clock Division value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval The clock division can be one of the following values: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT @@ -1195,14 +1193,14 @@ mode. /** * @brief Sets the TIM Input Capture prescaler on runtime without calling * another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events @@ -1218,8 +1216,8 @@ mode. /** * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value @@ -1239,7 +1237,7 @@ mode. /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @note When the USR bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) @@ -1250,7 +1248,7 @@ mode. /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @note When the USR bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): @@ -1264,14 +1262,14 @@ mode. /** * @brief Sets the TIM Capture x input polarity on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__: Polarity for TIx source + * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c index b6a3a2e485..a77b21ded0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: @@ -151,9 +149,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Hall Sensor configuration structure + * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) @@ -225,7 +223,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen /** * @brief DeInitializes the TIM Hall Sensor interface - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -253,7 +251,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -268,7 +266,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -283,7 +281,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -305,7 +303,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -327,7 +325,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -352,7 +350,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -377,10 +375,10 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -427,7 +425,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -477,14 +475,13 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -508,14 +505,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -539,14 +535,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -607,14 +602,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -678,16 +672,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -796,14 +789,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -896,14 +888,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Starts the PWM signal generation on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -926,14 +917,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -957,14 +947,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1025,14 +1014,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1096,16 +1084,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1214,14 +1201,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1304,9 +1290,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be enabled. + * @param OutputChannel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1330,9 +1316,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be disabled. + * @param OutputChannel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1360,9 +1346,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be enabled. + * @param OutputChannel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1392,9 +1378,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be disabled. + * @param OutputChannel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1454,16 +1440,16 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1504,16 +1490,16 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1558,16 +1544,16 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1611,9 +1597,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM in master mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status @@ -1649,9 +1635,9 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status */ @@ -1696,9 +1682,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Remap: specifies the TIM input remapping source. + * @param Remap specifies the TIM input remapping source. * This parameter can be one of the following values: * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. @@ -1773,7 +1759,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /** * @brief Hall commutation changed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1788,7 +1774,7 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Break detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1821,7 +1807,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Hall Sensor interface state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -1836,7 +1822,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA Commutation callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1855,12 +1841,12 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 - * @param ChannelNState: specifies the TIM Channel CCxNE bit new state. + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.h index 636e8918c4..3aa09d9e22 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.c index 40f28ea8e2..2c878307bb 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_uart.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -239,7 +237,7 @@ static void UART_SetConfig (UART_HandleTypeDef *huart); /** * @brief Initializes the UART mode according to the specified parameters in * the UART_InitTypeDef and create the associated handle. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -301,7 +299,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /** * @brief Initializes the half-duplex mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -357,9 +355,9 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initializes the LIN mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param BreakDetectLength: Specifies the LIN break detection length. + * @param BreakDetectLength Specifies the LIN break detection length. * This parameter can be one of the following values: * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection @@ -422,10 +420,10 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /** * @brief Initializes the Multi-Processor mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param Address: USART address - * @param WakeUpMethod: specifies the USART wake-up method. + * @param Address USART address + * @param WakeUpMethod specifies the USART wake-up method. * This parameter can be one of the following values: * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark @@ -490,7 +488,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /** * @brief DeInitializes the UART peripheral. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -522,7 +520,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief UART MSP Init. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -537,7 +535,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief UART MSP DeInit. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -608,11 +606,11 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief Sends an amount of data in blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -690,11 +688,11 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receives an amount of data in blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -779,10 +777,10 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Sends an amount of data in non blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -821,10 +819,10 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receives an amount of data in non blocking mode - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -866,10 +864,10 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Sends an amount of data in non blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -930,10 +928,10 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receives an amount of data in non blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ @@ -1000,7 +998,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Pauses the DMA Transfer. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1035,7 +1033,7 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /** * @brief Resumes the DMA Transfer. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1070,7 +1068,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /** * @brief Stops the DMA Transfer. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1518,7 +1516,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /** * @brief This function handles UART interrupt request. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1645,7 +1643,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Tx Transfer completed callbacks. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1660,7 +1658,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Tx Half Transfer completed callbacks. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1675,7 +1673,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Rx Transfer completed callbacks. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1690,7 +1688,7 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Half Transfer completed callbacks. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1705,7 +1703,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief UART error callbacks. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1785,7 +1783,7 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) /** * @brief Transmits break characters. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1812,7 +1810,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /** * @brief Enters the UART in mute mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1839,7 +1837,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief Exits the UART mute mode: wake up software. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1866,7 +1864,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) /** * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1901,7 +1899,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /** * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1958,7 +1956,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) /** * @brief Returns the UART state. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL state */ @@ -1973,7 +1971,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) /** * @brief Return the UART error code - * @param huart : pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ @@ -1988,7 +1986,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) /** * @brief DMA UART transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -2016,7 +2014,7 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART transmit process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2029,7 +2027,7 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -2056,7 +2054,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2069,7 +2067,7 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) @@ -2099,12 +2097,12 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function handles UART Communication Timeout. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param Flag: specifies the UART flag to check. - * @param Status: The new Flag status (SET or RESET). + * @param Flag specifies the UART flag to check. + * @param Status The new Flag status (SET or RESET). * @param Tickstart Tick start value - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) @@ -2137,7 +2135,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) @@ -2151,7 +2149,7 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) @@ -2299,7 +2297,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Sends an amount of data in non blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -2346,7 +2344,7 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) /** * @brief Wraps up transmission in non blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -2365,7 +2363,7 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) /** * @brief Receives an amount of data in non blocking mode - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -2427,7 +2425,7 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) /** * @brief Configures the UART peripheral. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.h index ba2ed4f839..16f755bc3d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_uart.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -353,7 +351,7 @@ typedef struct */ /** @brief Reset UART handle gstate & RxState - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -364,15 +362,15 @@ typedef struct } while(0U) /** @brief Flushes the UART DR register - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) /** @brief Checks whether the specified UART flag is set or not. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) * @arg UART_FLAG_LBD: LIN Break detection flag @@ -390,10 +388,10 @@ typedef struct #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** @brief Clears the specified UART pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). * @arg UART_FLAG_LBD: LIN Break detection flag. @@ -414,7 +412,7 @@ typedef struct #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** @brief Clear the UART PE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -428,7 +426,7 @@ typedef struct } while(0U) /** @brief Clear the UART FE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -436,7 +434,7 @@ typedef struct #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the UART NE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -444,7 +442,7 @@ typedef struct #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the UART ORE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -452,7 +450,7 @@ typedef struct #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -460,10 +458,10 @@ typedef struct #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Enable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __INTERRUPT__: specifies the UART interrupt source to enable. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. * This parameter can be one of the following values: * @arg UART_IT_CTS: CTS change interrupt * @arg UART_IT_LBD: LIN Break detection interrupt @@ -480,10 +478,10 @@ typedef struct (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) /** @brief Disable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __INTERRUPT__: specifies the UART interrupt source to disable. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. * This parameter can be one of the following values: * @arg UART_IT_CTS: CTS change interrupt * @arg UART_IT_LBD: LIN Break detection interrupt @@ -500,10 +498,10 @@ typedef struct ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) /** @brief Checks whether the specified UART interrupt has occurred or not. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __IT__: specifies the UART interrupt source to check. + * @param __IT__ specifies the UART interrupt source to check. * This parameter can be one of the following values: * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) * @arg UART_IT_LBD: LIN Break detection interrupt @@ -526,7 +524,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -545,7 +543,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -564,7 +562,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -583,7 +581,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -594,25 +592,25 @@ typedef struct } while(0U) /** @brief macros to enables the UART's one bit sample method - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief macros to disables the UART's one bit sample method - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) /** @brief Enable UART - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.c index bb6d980064..ab361673b4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_usart.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: @@ -221,7 +219,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /** * @brief Initializes the USART mode according to the specified * parameters in the USART_InitTypeDef and create the associated handle. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -267,7 +265,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /** * @brief DeInitializes the USART peripheral. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -301,7 +299,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief USART MSP Init. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -316,7 +314,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief USART MSP DeInit. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -396,11 +394,11 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief Simplex Send an amount of data in blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @param pTxData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pTxData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) @@ -477,11 +475,11 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Full-Duplex Receive an amount of data in blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @param pRxData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pRxData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -582,12 +580,12 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @param pTxData: Pointer to data transmitted buffer - * @param pRxData: Pointer to data received buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pTxData Pointer to data transmitted buffer + * @param pRxData Pointer to data received buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -697,10 +695,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @param pTxData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pTxData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status * @note The USART errors are not managed to avoid the overrun error. */ @@ -747,10 +745,10 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Simplex Receive an amount of data in non-blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @param pRxData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pRxData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -793,11 +791,11 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @param pTxData: Pointer to data transmitted buffer - * @param pRxData: Pointer to data received buffer - * @param Size: Amount of data to be received + * @param pTxData Pointer to data transmitted buffer + * @param pRxData Pointer to data received buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -846,10 +844,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @param pTxData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pTxData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -908,10 +906,10 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /** * @brief Full-Duplex Receive an amount of data in non-blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @param pRxData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pRxData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status * @note The USART DMA transmit stream must be configured in order to generate the clock for the slave. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. @@ -1000,11 +998,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @param pTxData: Pointer to data transmitted buffer - * @param pRxData: Pointer to data received buffer - * @param Size: Amount of data to be received + * @param pTxData Pointer to data transmitted buffer + * @param pRxData Pointer to data received buffer + * @param Size Amount of data to be received * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ @@ -1091,7 +1089,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /** * @brief Pauses the DMA Transfer. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -1111,7 +1109,7 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) /** * @brief Resumes the DMA Transfer. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -1131,7 +1129,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) /** * @brief Stops the DMA Transfer. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -1367,7 +1365,7 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) /** * @brief This function handles USART interrupt request. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1511,7 +1509,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /** * @brief Tx Transfer completed callbacks. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1526,7 +1524,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /** * @brief Tx Half Transfer completed callbacks. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1541,7 +1539,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /** * @brief Rx Transfer completed callbacks. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1556,7 +1554,7 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Half Transfer completed callbacks. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1571,7 +1569,7 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx/Rx Transfers completed callback for the non-blocking process. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1586,7 +1584,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) /** * @brief USART error callbacks. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1639,7 +1637,7 @@ __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart) /** * @brief Returns the USART state. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL state */ @@ -1650,7 +1648,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) /** * @brief Return the USART error code - * @param husart : pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART. * @retval USART Error Code */ @@ -1665,7 +1663,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) /** * @brief DMA USART transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -1697,7 +1695,7 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART transmit process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1710,7 +1708,7 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -1725,24 +1723,21 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + /* Disable the DMA transfer for the Transmit/receiver request by clearing the DMAT/DMAR bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + husart->State= HAL_USART_STATE_READY; + + /* The USART state is HAL_USART_STATE_BUSY_RX */ if(husart->State == HAL_USART_STATE_BUSY_RX) { - /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit - in the USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - husart->State= HAL_USART_STATE_READY; HAL_USART_RxCpltCallback(husart); } /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ else { - /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit - in the USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - husart->State= HAL_USART_STATE_READY; HAL_USART_TxRxCpltCallback(husart); } } @@ -1763,7 +1758,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1776,7 +1771,7 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void USART_DMAError(DMA_HandleTypeDef *hdma) @@ -1808,12 +1803,12 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function handles USART Communication Timeout. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. - * @param Flag: specifies the USART flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Tickstart: Tick start value. - * @param Timeout: Timeout duration. + * @param Flag specifies the USART flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Tickstart Tick start value. + * @param Timeout Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) @@ -1852,7 +1847,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /** * @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion). - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ static void USART_EndTxTransfer(USART_HandleTypeDef *husart) @@ -1866,7 +1861,7 @@ static void USART_EndTxTransfer(USART_HandleTypeDef *husart) /** * @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion). - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ static void USART_EndRxTransfer(USART_HandleTypeDef *husart) @@ -1970,7 +1965,7 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status * @note The USART errors are not managed to avoid the overrun error. @@ -2017,7 +2012,7 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) /** * @brief Wraps up transmission in non blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -2038,7 +2033,7 @@ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) /** * @brief Simplex Receive an amount of data in non-blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -2110,7 +2105,7 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) /** * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -2213,7 +2208,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) /** * @brief Configures the USART pferipheral. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.h index f97893e0bb..bb26dbcd09 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_usart.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of USART HAL module. ****************************************************************************** * @attention @@ -302,16 +300,16 @@ typedef struct */ /** @brief Reset USART handle state - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. * @retval None */ #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) /** @brief Checks whether the specified Smartcard flag is set or not. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg USART_FLAG_TXE: Transmit data register empty flag * @arg USART_FLAG_TC: Transmission Complete flag @@ -326,9 +324,9 @@ typedef struct #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** @brief Clears the specified Smartcard pending flags. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg USART_FLAG_TC: Transmission Complete flag. * @arg USART_FLAG_RXNE: Receive data register not empty flag. @@ -347,7 +345,7 @@ typedef struct #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** @brief Clear the USART PE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. * @retval None */ @@ -360,37 +358,37 @@ typedef struct } while(0U) /** @brief Clear the USART FE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. * @retval None */ #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the USART NE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. * @retval None */ #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the UART ORE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. * @retval None */ #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the USART IDLE pending flag. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. * @retval None */ #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Enables or disables the specified USART interrupts. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. - * @param __INTERRUPT__: specifies the USART interrupt source to check. + * @param __INTERRUPT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt @@ -409,9 +407,9 @@ typedef struct ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) /** @brief Checks whether the specified USART interrupt has occurred or not. - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral. - * @param __IT__: specifies the USART interrupt source to check. + * @param __IT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt @@ -425,26 +423,26 @@ typedef struct (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK)) /** @brief Macro to enable the USART's one bit sample method - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Macro to disable the USART's one bit sample method - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) /** @brief Enable USART - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ #define __HAL_USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable USART - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.c index e31fa9f339..40ccb3a8a1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_wwdg.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: @@ -280,7 +278,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) /** * @brief WWDG Early Wakeup callback. - * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.h index efe194a89e..046ddc2259 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_wwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention @@ -168,14 +166,14 @@ typedef struct /** * @brief Enables the WWDG peripheral. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @retval None */ #define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) /** * @brief Enables the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt @@ -196,8 +194,8 @@ typedef struct /** @brief Clear the WWDG's interrupt pending bits * bits to clear the selected interrupt pending bits. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag */ @@ -215,8 +213,8 @@ typedef struct /** * @brief Clears the WWDG's pending flags. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval None @@ -224,8 +222,8 @@ typedef struct #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** @brief Checks if the specified WWDG interrupt source is enabled or disabled. - * @param __HANDLE__: WWDG Handle. - * @param __INTERRUPT__: specifies the WWDG interrupt source to check. + * @param __HANDLE__ WWDG Handle. + * @param __INTERRUPT__ specifies the WWDG interrupt source to check. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early Wakeup Interrupt * @retval state of __INTERRUPT__ (TRUE or FALSE). diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c index 8fe0858376..da8cac28d2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_adc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief ADC LL module driver ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.h index 2cfeb23d1a..e28b75b646 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_adc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of ADC LL module. ****************************************************************************** * @attention @@ -297,7 +295,7 @@ extern "C" { * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ @@ -646,12 +644,12 @@ typedef struct #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */ #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ -#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ -#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -948,16 +946,16 @@ typedef struct #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ -#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ -#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -1166,7 +1164,7 @@ typedef struct * @note Example: * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 @@ -1639,7 +1637,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: @@ -1686,13 +1684,13 @@ typedef struct * @note ADC measurement data must correspond to a resolution of 12bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius). * On STM32F4, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV). * On STM32F4, refer to device datasheet parameter "V25". - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -3496,7 +3494,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h index b90e75a1fd..73483f1aed 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_bus.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of BUS LL module. @verbatim diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h index cbe740447c..5255c4d486 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_cortex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CORTEX LL module. @verbatim ============================================================================== diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.c index 73aaf8f775..e68f1e2168 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_crc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CRC LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.h index 711bc35486..0a00d7939b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_crc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CRC LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.c index 60d91a7b2b..7209439f40 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dac.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DAC LL module driver ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h index 988118ef23..4472e1c611 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dac.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DAC LL module. ****************************************************************************** * @attention @@ -139,7 +137,7 @@ extern "C" { * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). * @retval Pointer to register address */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ @@ -493,7 +491,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel * (unit: mVolt). * @param __DAC_RESOLUTION__ This parameter can be one of the following values: diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.c index c9c3a0e84c..0418bc5103 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dma.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DMA LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h index 4a0181741b..f478ffadd2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dma.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DMA LL module. ****************************************************************************** * @attention @@ -2097,7 +2095,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF0); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); } /** @@ -2108,7 +2106,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF1); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); } /** @@ -2119,7 +2117,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF2); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); } /** @@ -2130,7 +2128,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF3); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); } /** @@ -2141,7 +2139,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF4); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); } /** @@ -2152,7 +2150,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF5); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); } /** @@ -2163,7 +2161,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF6); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); } /** @@ -2174,7 +2172,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF7); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); } /** @@ -2185,7 +2183,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF0); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); } /** @@ -2196,7 +2194,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF1); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); } /** @@ -2207,7 +2205,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF2); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); } /** @@ -2218,7 +2216,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF3); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); } /** @@ -2229,7 +2227,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF4); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); } /** @@ -2240,7 +2238,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF5); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); } /** @@ -2251,7 +2249,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF6); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); } /** @@ -2262,7 +2260,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF7); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); } /** @@ -2273,7 +2271,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF0); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); } /** @@ -2284,7 +2282,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF1); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); } /** @@ -2295,7 +2293,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF2); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); } /** @@ -2306,7 +2304,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF3); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); } /** @@ -2317,7 +2315,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF4); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); } /** @@ -2328,7 +2326,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF5); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); } /** @@ -2339,7 +2337,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF6); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); } /** @@ -2350,7 +2348,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF7); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); } /** @@ -2361,7 +2359,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); } /** @@ -2372,7 +2370,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); } /** @@ -2383,7 +2381,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); } /** @@ -2394,7 +2392,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); } /** @@ -2405,7 +2403,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); } /** @@ -2416,7 +2414,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); } /** @@ -2427,7 +2425,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); } /** @@ -2438,7 +2436,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); } /** @@ -2449,7 +2447,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF0); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); } /** @@ -2460,7 +2458,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF1); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); } /** @@ -2471,7 +2469,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF2); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); } /** @@ -2482,7 +2480,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF3); + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); } /** @@ -2493,7 +2491,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF4); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); } /** @@ -2504,7 +2502,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF5); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); } /** @@ -2515,7 +2513,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF6); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); } /** @@ -2526,7 +2524,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF7); + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.c index c940353b05..6942f019b4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dma2d.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DMA2D LL module driver. ****************************************************************************** * @attention @@ -164,7 +162,7 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) * @note DMA2D transfers must be disabled to set initialization bits in configuration registers, * otherwise ERROR result is returned. * @param DMA2Dx DMA2D Instance - * @param DMA2D_InitStruct: pointer to a LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure * that contains the configuration information for the specified DMA2D peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content @@ -226,7 +224,7 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini /** * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value. - * @param DMA2D_InitStruct: pointer to a @ref LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -249,9 +247,9 @@ void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct) * @brief Configure the foreground or background according to the specified parameters * in the LL_DMA2D_LayerCfgTypeDef structure. * @param DMA2Dx DMA2D Instance - * @param DMA2D_LayerCfg: pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains + * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains * the configuration information for the specified layer. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval None @@ -315,7 +313,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D /** * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value. - * @param DMA2D_LayerCfg: pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure + * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -339,7 +337,7 @@ void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg) * @brief Initialize DMA2D output color register according to the specified parameters * in DMA2D_ColorStruct. * @param DMA2Dx DMA2D Instance - * @param DMA2D_ColorStruct: pointer to a LL_DMA2D_ColorTypeDef structure that contains + * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains * the color configuration information for the specified DMA2D peripheral. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.h index f1ec30fc24..3824a7d4d9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dma2d.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DMA2D LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.c index 7a3a0e9ce1..0cb4875032 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_exti.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief EXTI LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.h index 85a41c2fcf..a633c48729 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_exti.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of EXTI LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c index d4b541abdf..07ca6e4b6e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_fmc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -144,8 +142,8 @@ /** * @brief Initialize the FMC_NORSRAM device according to the specified * control parameters in the FMC_NORSRAM_InitTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Init: Pointer to NORSRAM Initialization structure + * @param Device Pointer to NORSRAM device instance + * @param Init Pointer to NORSRAM Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) @@ -255,9 +253,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini /** * @brief DeInitialize the FMC_NORSRAM peripheral - * @param Device: Pointer to NORSRAM device instance - * @param ExDevice: Pointer to NORSRAM extended mode device instance - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) @@ -291,9 +289,9 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX /** * @brief Initialize the FMC_NORSRAM Timing according to the specified * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) @@ -344,9 +342,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR /** * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) @@ -410,8 +408,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef */ /** * @brief Enables dynamically FMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) @@ -428,8 +426,8 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, /** * @brief Disables dynamically FMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) @@ -498,8 +496,8 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device /** * @brief Initializes the FMC_NAND device according to the specified * control parameters in the FMC_NAND_HandleTypeDef - * @param Device: Pointer to NAND device instance - * @param Init: Pointer to NAND Initialization structure + * @param Device Pointer to NAND device instance + * @param Init Pointer to NAND Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) @@ -542,9 +540,9 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * /** * @brief Initializes the FMC_NAND Common space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) @@ -583,9 +581,9 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC /** * @brief Initializes the FMC_NAND Attribute space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) @@ -622,8 +620,8 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, /** * @brief DeInitializes the FMC_NAND device - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) @@ -668,8 +666,8 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) /** * @brief Enables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) @@ -687,8 +685,8 @@ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) /** * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) @@ -705,10 +703,10 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) /** * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param ECCval: Pointer to ECC value - * @param Bank: NAND bank number - * @param Timeout: Timeout wait value + * @param Device Pointer to NAND device instance + * @param ECCval Pointer to ECC value + * @param Bank NAND bank number + * @param Timeout Timeout wait value * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) @@ -765,8 +763,8 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /** * @brief Initializes the FMC_NAND device according to the specified * control parameters in the FMC_NAND_HandleTypeDef - * @param Device: Pointer to NAND device instance - * @param Init: Pointer to NAND Initialization structure + * @param Device Pointer to NAND device instance + * @param Init Pointer to NAND Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) @@ -826,9 +824,9 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * /** * @brief Initializes the FMC_NAND Common space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) @@ -882,9 +880,9 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC /** * @brief Initializes the FMC_NAND Attribute space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) @@ -936,8 +934,8 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, /** * @brief DeInitializes the FMC_NAND device - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) @@ -991,8 +989,8 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) */ /** * @brief Enables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) @@ -1016,8 +1014,8 @@ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) /** * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) @@ -1041,10 +1039,10 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) /** * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param ECCval: Pointer to ECC value - * @param Bank: NAND bank number - * @param Timeout: Timeout wait value + * @param Device Pointer to NAND device instance + * @param ECCval Pointer to ECC value + * @param Bank NAND bank number + * @param Timeout Timeout wait value * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) @@ -1138,8 +1136,8 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /** * @brief Initializes the FMC_PCCARD device according to the specified * control parameters in the FMC_PCCARD_HandleTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Init: Pointer to PCCARD Initialization structure + * @param Device Pointer to PCCARD device instance + * @param Init Pointer to PCCARD Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) @@ -1157,7 +1155,7 @@ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTyp /* Clear TAR, TCLR, PWAITEN and PWID bits */ tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \ - FMC_PCR4_PWID)); + FMC_PCR4_PWID | FMC_PCR4_PTYP)); /* Set FMC_PCCARD device control parameters */ tmpr |= (uint32_t)(Init->Waitfeature |\ @@ -1173,8 +1171,8 @@ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTyp /** * @brief Initializes the FMC_PCCARD Common space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Timing: Pointer to PCCARD timing structure + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) @@ -1208,8 +1206,8 @@ HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, /** * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Timing: Pointer to PCCARD timing structure + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) @@ -1243,8 +1241,8 @@ HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Devi /** * @brief Initializes the FMC_PCCARD IO space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Timing: Pointer to PCCARD timing structure + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) @@ -1278,7 +1276,7 @@ HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC /** * @brief DeInitializes the FMC_PCCARD device - * @param Device: Pointer to PCCARD device instance + * @param Device Pointer to PCCARD device instance * @retval HAL status */ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) @@ -1347,8 +1345,8 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) /** * @brief Initializes the FMC_SDRAM device according to the specified * control parameters in the FMC_SDRAM_InitTypeDef - * @param Device: Pointer to SDRAM device instance - * @param Init: Pointer to SDRAM Initialization structure + * @param Device Pointer to SDRAM device instance + * @param Init Pointer to SDRAM Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) @@ -1427,9 +1425,9 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe /** * @brief Initializes the FMC_SDRAM device timing according to the specified * parameters in the FMC_SDRAM_TimingTypeDef - * @param Device: Pointer to SDRAM device instance - * @param Timing: Pointer to SDRAM Timing structure - * @param Bank: SDRAM bank number + * @param Device Pointer to SDRAM device instance + * @param Timing Pointer to SDRAM Timing structure + * @param Bank SDRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) @@ -1498,7 +1496,7 @@ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Tim /** * @brief DeInitializes the FMC_SDRAM peripheral - * @param Device: Pointer to SDRAM device instance + * @param Device Pointer to SDRAM device instance * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) @@ -1537,8 +1535,8 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) */ /** * @brief Enables dynamically FMC_SDRAM write protection. - * @param Device: Pointer to SDRAM device instance - * @param Bank: SDRAM bank number + * @param Device Pointer to SDRAM device instance + * @param Bank SDRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) @@ -1555,7 +1553,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, ui /** * @brief Disables dynamically FMC_SDRAM write protection. - * @param hsdram: FMC_SDRAM handle + * @param hsdram FMC_SDRAM handle * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) @@ -1572,10 +1570,10 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u /** * @brief Send Command to the FMC SDRAM bank - * @param Device: Pointer to SDRAM device instance - * @param Command: Pointer to SDRAM command structure - * @param Timing: Pointer to SDRAM Timing structure - * @param Timeout: Timeout wait value + * @param Device Pointer to SDRAM device instance + * @param Command Pointer to SDRAM command structure + * @param Timing Pointer to SDRAM Timing structure + * @param Timeout Timeout wait value * @retval HAL state */ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) @@ -1620,8 +1618,8 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com /** * @brief Program the SDRAM Memory Refresh rate. - * @param Device: Pointer to SDRAM device instance - * @param RefreshRate: The SDRAM refresh rate value. + * @param Device Pointer to SDRAM device instance + * @param RefreshRate The SDRAM refresh rate value. * @retval HAL state */ HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) @@ -1638,8 +1636,8 @@ HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32 /** * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. - * @param Device: Pointer to SDRAM device instance - * @param AutoRefreshNumber: Specifies the auto Refresh number. + * @param Device Pointer to SDRAM device instance + * @param AutoRefreshNumber Specifies the auto Refresh number. * @retval None */ HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) @@ -1656,8 +1654,8 @@ HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint /** * @brief Returns the indicated FMC SDRAM bank mode status. - * @param Device: Pointer to SDRAM device instance - * @param Bank: Defines the FMC SDRAM bank. This parameter can be + * @param Device Pointer to SDRAM device instance + * @param Bank Defines the FMC SDRAM bank. This parameter can be * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. * @retval The FMC SDRAM bank mode status, could be on of the following values: * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h index 3b65f306ca..8ea0d1f15b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_fmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FMC HAL module. ****************************************************************************** * @attention @@ -798,16 +796,16 @@ typedef struct */ /** * @brief Enable the NORSRAM device access. - * @param __INSTANCE__: FMC_NORSRAM Instance - * @param __BANK__: FMC_NORSRAM Bank + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank * @retval None */ #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) /** * @brief Disable the NORSRAM device access. - * @param __INSTANCE__: FMC_NORSRAM Instance - * @param __BANK__: FMC_NORSRAM Bank + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank * @retval None */ #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) @@ -822,24 +820,24 @@ typedef struct #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Enable the NAND device access. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank * @retval None */ #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) /** * @brief Disable the NAND device access. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank * @retval None */ #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ /** * @brief Enable the NAND device access. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank * @retval None */ #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \ @@ -847,8 +845,8 @@ typedef struct /** * @brief Disable the NAND device access. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank * @retval None */ #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \ @@ -865,14 +863,14 @@ typedef struct */ /** * @brief Enable the PCCARD device access. - * @param __INSTANCE__: FMC_PCCARD Instance + * @param __INSTANCE__ FMC_PCCARD Instance * @retval None */ #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN) /** * @brief Disable the PCCARD device access. - * @param __INSTANCE__: FMC_PCCARD Instance + * @param __INSTANCE__ FMC_PCCARD Instance * @retval None */ #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN) @@ -888,9 +886,9 @@ typedef struct #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Enable the NAND device interrupt. - * @param __INSTANCE__: FMC_NAND instance - * @param __BANK__: FMC_NAND Bank - * @param __INTERRUPT__: FMC_NAND interrupt + * @param __INSTANCE__ FMC_NAND instance + * @param __BANK__ FMC_NAND Bank + * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. @@ -901,9 +899,9 @@ typedef struct /** * @brief Disable the NAND device interrupt. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank - * @param __INTERRUPT__: FMC_NAND interrupt + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. @@ -914,9 +912,9 @@ typedef struct /** * @brief Get flag status of the NAND device. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank - * @param __FLAG__: FMC_NAND flag + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. @@ -927,9 +925,9 @@ typedef struct #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) /** * @brief Clear flag status of the NAND device. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank - * @param __FLAG__: FMC_NAND flag + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. @@ -941,9 +939,9 @@ typedef struct #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ /** * @brief Enable the NAND device interrupt. - * @param __INSTANCE__: FMC_NAND instance - * @param __BANK__: FMC_NAND Bank - * @param __INTERRUPT__: FMC_NAND interrupt + * @param __INSTANCE__ FMC_NAND instance + * @param __BANK__ FMC_NAND Bank + * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. @@ -955,9 +953,9 @@ typedef struct /** * @brief Disable the NAND device interrupt. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank - * @param __INTERRUPT__: FMC_NAND interrupt + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. @@ -969,9 +967,9 @@ typedef struct /** * @brief Get flag status of the NAND device. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank - * @param __FLAG__: FMC_NAND flag + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. @@ -983,9 +981,9 @@ typedef struct (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) /** * @brief Clear flag status of the NAND device. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank - * @param __FLAG__: FMC_NAND flag + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. @@ -1000,8 +998,8 @@ typedef struct #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** * @brief Enable the PCCARD device interrupt. - * @param __INSTANCE__: FMC_PCCARD instance - * @param __INTERRUPT__: FMC_PCCARD interrupt + * @param __INSTANCE__ FMC_PCCARD instance + * @param __INTERRUPT__ FMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. @@ -1012,8 +1010,8 @@ typedef struct /** * @brief Disable the PCCARD device interrupt. - * @param __INSTANCE__: FMC_PCCARD instance - * @param __INTERRUPT__: FMC_PCCARD interrupt + * @param __INSTANCE__ FMC_PCCARD instance + * @param __INTERRUPT__ FMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. @@ -1024,8 +1022,8 @@ typedef struct /** * @brief Get flag status of the PCCARD device. - * @param __INSTANCE__: FMC_PCCARD instance - * @param __FLAG__: FMC_PCCARD flag + * @param __INSTANCE__ FMC_PCCARD instance + * @param __FLAG__ FMC_PCCARD flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. @@ -1037,8 +1035,8 @@ typedef struct /** * @brief Clear flag status of the PCCARD device. - * @param __INSTANCE__: FMC_PCCARD instance - * @param __FLAG__: FMC_PCCARD flag + * @param __INSTANCE__ FMC_PCCARD instance + * @param __FLAG__ FMC_PCCARD flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. @@ -1051,8 +1049,8 @@ typedef struct /** * @brief Enable the SDRAM device interrupt. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __INTERRUPT__: FMC_SDRAM interrupt + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error * @retval None @@ -1061,8 +1059,8 @@ typedef struct /** * @brief Disable the SDRAM device interrupt. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __INTERRUPT__: FMC_SDRAM interrupt + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error * @retval None @@ -1071,8 +1069,8 @@ typedef struct /** * @brief Get flag status of the SDRAM device. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __FLAG__: FMC_SDRAM flag + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag * This parameter can be any combination of the following values: * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. @@ -1083,8 +1081,8 @@ typedef struct /** * @brief Clear flag status of the SDRAM device. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __FLAG__: FMC_SDRAM flag + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag * This parameter can be any combination of the following values: * @arg FMC_SDRAM_FLAG_REFRESH_ERROR * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c index 842da47795..5006cecd58 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_fsmc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief FSMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -140,8 +138,8 @@ /** * @brief Initialize the FSMC_NORSRAM device according to the specified * control parameters in the FSMC_NORSRAM_InitTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Init: Pointer to NORSRAM Initialization structure + * @param Device Pointer to NORSRAM device instance + * @param Init Pointer to NORSRAM Initialization structure * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init) @@ -248,9 +246,9 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_ /** * @brief DeInitialize the FSMC_NORSRAM peripheral - * @param Device: Pointer to NORSRAM device instance - * @param ExDevice: Pointer to NORSRAM extended mode device instance - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) @@ -285,9 +283,9 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM /** * @brief Initialize the FSMC_NORSRAM Timing according to the specified * parameters in the FSMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) @@ -340,9 +338,9 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO /** * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified * parameters in the FSMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) @@ -407,8 +405,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD /** * @brief Enables dynamically FSMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) @@ -425,8 +423,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Devic /** * @brief Disables dynamically FSMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) @@ -494,8 +492,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi /** * @brief Initializes the FSMC_NAND device according to the specified * control parameters in the FSMC_NAND_HandleTypeDef - * @param Device: Pointer to NAND device instance - * @param Init: Pointer to NAND Initialization structure + * @param Device Pointer to NAND device instance + * @param Init Pointer to NAND Initialization structure * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) @@ -553,9 +551,9 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe /** * @brief Initializes the FSMC_NAND Common space Timing according to the specified * parameters in the FSMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) @@ -607,9 +605,9 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F /** * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified * parameters in the FSMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) @@ -660,8 +658,8 @@ HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device /** * @brief DeInitializes the FSMC_NAND device - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) @@ -711,8 +709,8 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) /** * @brief Enables dynamically FSMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) @@ -732,8 +730,8 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank /** * @brief Disables dynamically FSMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) @@ -753,10 +751,10 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank /** * @brief Disables dynamically FSMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param ECCval: Pointer to ECC value - * @param Bank: NAND bank number - * @param Timeout: Timeout wait value + * @param Device Pointer to NAND device instance + * @param ECCval Pointer to ECC value + * @param Bank NAND bank number + * @param Timeout Timeout wait value * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) @@ -849,8 +847,8 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, /** * @brief Initializes the FSMC_PCCARD device according to the specified * control parameters in the FSMC_PCCARD_HandleTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Init: Pointer to PCCARD Initialization structure + * @param Device Pointer to PCCARD device instance + * @param Init Pointer to PCCARD Initialization structure * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) @@ -867,7 +865,7 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init /* Clear TAR, TCLR, PWAITEN and PWID bits */ tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \ - FSMC_PCR4_PWID)); + FSMC_PCR4_PWID | FSMC_PCR4_PTYP)); /* Set FSMC_PCCARD device control parameters */ tmpr |= (uint32_t)(Init->Waitfeature |\ @@ -883,8 +881,8 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init /** * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified * parameters in the FSMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Timing: Pointer to PCCARD timing structure + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) @@ -917,8 +915,8 @@ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Devic /** * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified * parameters in the FSMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Timing: Pointer to PCCARD timing structure + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) @@ -951,8 +949,8 @@ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *De /** * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified * parameters in the FSMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to PCCARD device instance - * @param Timing: Pointer to PCCARD timing structure + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) @@ -985,7 +983,7 @@ HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, F /** * @brief DeInitializes the FSMC_PCCARD device - * @param Device: Pointer to PCCARD device instance + * @param Device Pointer to PCCARD device instance * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h index 0977510969..65a062c992 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_fsmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FSMC HAL module. ****************************************************************************** * @attention @@ -649,16 +647,16 @@ typedef struct */ /** * @brief Enable the NORSRAM device access. - * @param __INSTANCE__: FSMC_NORSRAM Instance - * @param __BANK__: FSMC_NORSRAM Bank + * @param __INSTANCE__ FSMC_NORSRAM Instance + * @param __BANK__ FSMC_NORSRAM Bank * @retval none */ #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN) /** * @brief Disable the NORSRAM device access. - * @param __INSTANCE__: FSMC_NORSRAM Instance - * @param __BANK__: FSMC_NORSRAM Bank + * @param __INSTANCE__ FSMC_NORSRAM Instance + * @param __BANK__ FSMC_NORSRAM Bank * @retval none */ #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN) @@ -673,8 +671,8 @@ typedef struct #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /** * @brief Enable the NAND device access. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank * @retval none */ #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ @@ -682,8 +680,8 @@ typedef struct /** * @brief Disable the NAND device access. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank * @retval none */ #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \ @@ -698,14 +696,14 @@ typedef struct */ /** * @brief Enable the PCCARD device access. - * @param __INSTANCE__: FSMC_PCCARD Instance + * @param __INSTANCE__ FSMC_PCCARD Instance * @retval none */ #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) /** * @brief Disable the PCCARD device access. - * @param __INSTANCE__: FSMC_PCCARD Instance + * @param __INSTANCE__ FSMC_PCCARD Instance * @retval none */ #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) @@ -719,9 +717,9 @@ typedef struct */ /** * @brief Enable the NAND device interrupt. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @param __INTERRUPT__: FSMC_NAND interrupt + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __INTERRUPT__ FSMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. @@ -733,9 +731,9 @@ typedef struct /** * @brief Disable the NAND device interrupt. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @param __INTERRUPT__: FSMC_NAND interrupt + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __INTERRUPT__ FSMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. @@ -747,9 +745,9 @@ typedef struct /** * @brief Get flag status of the NAND device. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__ : FSMC_NAND Bank - * @param __FLAG__ : FSMC_NAND flag + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __FLAG__ FSMC_NAND flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. @@ -762,9 +760,9 @@ typedef struct /** * @brief Clear flag status of the NAND device. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @param __FLAG__: FSMC_NAND flag + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __FLAG__ FSMC_NAND flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. @@ -777,8 +775,8 @@ typedef struct /** * @brief Enable the PCCARD device interrupt. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __INTERRUPT__: FSMC_PCCARD interrupt + * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INTERRUPT__ FSMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. @@ -789,8 +787,8 @@ typedef struct /** * @brief Disable the PCCARD device interrupt. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __INTERRUPT__: FSMC_PCCARD interrupt + * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INTERRUPT__ FSMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. @@ -801,8 +799,8 @@ typedef struct /** * @brief Get flag status of the PCCARD device. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __FLAG__: FSMC_PCCARD flag + * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __FLAG__ FSMC_PCCARD flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. @@ -814,8 +812,8 @@ typedef struct /** * @brief Clear flag status of the PCCARD device. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __FLAG__: FSMC_PCCARD flag + * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __FLAG__ FSMC_PCCARD flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.c index d0b9537777..bf4cdfcb88 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_gpio.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief GPIO LL module driver. ****************************************************************************** * @attention @@ -209,7 +207,7 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) /** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. * @param GPIOx GPIO Port - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * that contains the configuration information for the specified GPIO peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content @@ -286,7 +284,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * whose fields will be set to default values. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.h index 556cb23ced..7eb8464fa2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_gpio.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of GPIO LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.c index 9ca999f7cd..0b69db8e99 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_i2c.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief I2C LL module driver. ****************************************************************************** * @attention @@ -69,9 +67,9 @@ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP)) -#define IS_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST)) +#define IS_LL_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST)) -#define IS_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \ +#define IS_LL_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \ ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9)) #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) @@ -169,8 +167,8 @@ uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) /* Check the I2C parameters from I2C_InitStruct */ assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode)); - assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle)); + assert_param(IS_LL_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed)); + assert_param(IS_LL_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle)); #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter)); assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter)); diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h index 54fea5eff5..69f44ce05b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_i2c.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of I2C LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_iwdg.h index 2ebb415dde..49a106cc05 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_iwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_iwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of IWDG LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.c index 28775f9849..82b63f5fc2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_lptim.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief LPTIM LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h index a10827e96d..6ca83de287 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_lptim.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of LPTIM LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.c index 992a83f3cd..3a04e89683 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_pwr.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief PWR LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.h index c1333adc87..e2b6b06c77 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_pwr.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PWR LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c index 80c1368a54..27ed25dc56 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_rcc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief RCC LL module driver. ****************************************************************************** * @attention @@ -208,6 +206,10 @@ ErrorStatus LL_RCC_DeInit(void) /* Set HSION bit */ LL_RCC_HSI_Enable(); + /* Wait for HSI READY bit */ + while(LL_RCC_HSI_IsReady() != 1U) + {} + /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000U); @@ -232,6 +234,10 @@ ErrorStatus LL_RCC_DeInit(void) /* Set HSITRIM bits to the reset value*/ LL_RCC_HSI_SetCalibTrimming(0x10U); + /* Wait for PLL READY bit to be reset */ + while(LL_RCC_PLL_IsReady() != 0U) + {} + /* Reset PLLCFGR register */ LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE); @@ -245,11 +251,33 @@ ErrorStatus LL_RCC_DeInit(void) LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE); #endif /* RCC_PLLSAI_SUPPORT */ - /* Reset HSEBYP bit */ - LL_RCC_HSE_DisableBypass(); - /* Disable all interrupts */ - LL_RCC_WriteReg(CIR, 0x00000000U); + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE); + +#if defined(RCC_CIR_PLLI2SRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +#endif /* RCC_CIR_PLLI2SRDYIE */ + +#if defined(RCC_CIR_PLLSAIRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +#endif /* RCC_CIR_PLLSAIRDYIE */ + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); + +#if defined(RCC_CIR_PLLI2SRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +#endif /* RCC_CIR_PLLI2SRDYC */ + +#if defined(RCC_CIR_PLLSAIRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +#endif /* RCC_CIR_PLLSAIRDYC */ + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); return SUCCESS; } diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h index ddac927182..63678d8b5b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_rcc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RCC LL module. ****************************************************************************** * @attention @@ -4853,6 +4851,31 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, #endif /* SAI1 */ #endif /* RCC_PLLCFGR_PLLR */ +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + /** * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN @@ -4967,18 +4990,6 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void) } #endif /* RCC_DCKCFGR_PLLDIVR */ -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -} - /** * @brief Get Division factor for the main PLL and other PLL * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.c index 51bf24f848..37e44eefbf 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_rng.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief RNG LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.h index 584d2c5e79..db1725d204 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_rng.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RNG LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.c index d7693e4f3e..71188f2478 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_rtc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief RTC LL module driver. ****************************************************************************** * @attention @@ -381,7 +379,7 @@ void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) * @param RTC_Format This parameter can be one of the following values: * @arg @ref LL_RTC_FORMAT_BIN * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains * the date configuration information for the RTC. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Day register is configured diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.h index 8c7cc2b30e..4fc1f9c065 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_rtc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RTC LL module. ****************************************************************************** * @attention @@ -2694,7 +2692,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) * @brief Set timestamp Pin * @rmtoll TAFCR TSINSEL LL_RTC_TS_SetPin * @param RTCx RTC Instance - * @param TSPin: specifies the RTC TimeStamp Pin. + * @param TSPin specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC TimeStamp. * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is selected as RTC TimeStamp. (*) @@ -2935,7 +2933,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_ * @brief Set Tamper Pin * @rmtoll TAFCR TAMP1INSEL LL_RTC_TAMPER_SetPin * @param RTCx RTC Instance - * @param TamperPin: specifies the RTC Tamper Pin. + * @param TamperPin specifies the RTC Tamper Pin. * This parameter can be one of the following values: * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper. * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper. (*) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.c index e0036a4ebb..555351ab50 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -227,8 +225,8 @@ static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t /** * @brief Initializes the SDMMC according to the specified * parameters in the SDMMC_InitTypeDef and create the associated handle. - * @param SDIOx: Pointer to SDMMC register base - * @param Init: SDMMC initialization structure + * @param SDIOx Pointer to SDMMC register base + * @param Init SDMMC initialization structure * @retval HAL status */ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) @@ -281,7 +279,7 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) /** * @brief Read data (word) from Rx FIFO in blocking mode (polling) - * @param SDIOx: Pointer to SDMMC register base + * @param SDIOx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) @@ -292,8 +290,8 @@ uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) /** * @brief Write data (word) to Tx FIFO in blocking mode (polling) - * @param SDIOx: Pointer to SDMMC register base - * @param pWriteData: pointer to data to write + * @param SDIOx Pointer to SDMMC register base + * @param pWriteData pointer to data to write * @retval HAL status */ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) @@ -325,7 +323,7 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) /** * @brief Set SDMMC Power state to ON. - * @param SDIOx: Pointer to SDMMC register base + * @param SDIOx Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) @@ -338,7 +336,7 @@ HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) /** * @brief Set SDMMC Power state to OFF. - * @param SDIOx: Pointer to SDMMC register base + * @param SDIOx Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) @@ -351,7 +349,7 @@ HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) /** * @brief Get SDMMC Power state. - * @param SDIOx: Pointer to SDMMC register base + * @param SDIOx Pointer to SDMMC register base * @retval Power status of the controller. The returned value can be one of the * following values: * - 0x00: Power OFF @@ -366,8 +364,8 @@ uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) /** * @brief Configure the SDMMC command path according to the specified parameters in * SDIO_CmdInitTypeDef structure and send the command - * @param SDIOx: Pointer to SDMMC register base - * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains + * @param SDIOx Pointer to SDMMC register base + * @param Command pointer to a SDIO_CmdInitTypeDef structure that contains * the configuration information for the SDMMC command * @retval HAL status */ @@ -398,7 +396,7 @@ HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Com /** * @brief Return the command index of last command for which response received - * @param SDIOx: Pointer to SDMMC register base + * @param SDIOx Pointer to SDMMC register base * @retval Command index of the last command response received */ uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) @@ -409,8 +407,8 @@ uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) /** * @brief Return the response received from the card for the last command - * @param SDIOx: Pointer to SDMMC register base - * @param Response: Specifies the SDMMC response register. + * @param SDIOx Pointer to SDMMC register base + * @param Response Specifies the SDMMC response register. * This parameter can be one of the following values: * @arg SDIO_RESP1: Response Register 1 * @arg SDIO_RESP1: Response Register 2 @@ -434,8 +432,8 @@ uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response) /** * @brief Configure the SDMMC data path according to the specified * parameters in the SDIO_DataInitTypeDef. - * @param SDIOx: Pointer to SDMMC register base - * @param Data : pointer to a SDIO_DataInitTypeDef structure + * @param SDIOx Pointer to SDMMC register base + * @param Data pointer to a SDIO_DataInitTypeDef structure * that contains the configuration information for the SDMMC data. * @retval HAL status */ @@ -471,7 +469,7 @@ HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Dat /** * @brief Returns number of remaining data bytes to be transferred. - * @param SDIOx: Pointer to SDMMC register base + * @param SDIOx Pointer to SDMMC register base * @retval Number of remaining data bytes to be transferred */ uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) @@ -481,7 +479,7 @@ uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) /** * @brief Get the FIFO data - * @param SDIOx: Pointer to SDMMC register base + * @param SDIOx Pointer to SDMMC register base * @retval Data received */ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) @@ -491,8 +489,8 @@ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) /** * @brief Sets one of the two options of inserting read wait interval. - * @param SDIOx: Pointer to SDMMC register base - * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode. + * @param SDIOx Pointer to SDMMC register base + * @param SDIO_ReadWaitMode SDMMC Read Wait operation mode. * This parameter can be: * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 @@ -530,7 +528,7 @@ HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_R /** * @brief Send the Data Block Lenght command and check the response - * @param SDIOx: Pointer to SDMMC register base + * @param SDIOx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize) @@ -554,7 +552,7 @@ uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize) /** * @brief Send the Read Single Block command and check the response - * @param SDIOx: Pointer to SDMMC register base + * @param SDIOx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) @@ -578,7 +576,7 @@ uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) /** * @brief Send the Read Multi Block command and check the response - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) @@ -602,7 +600,7 @@ uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) /** * @brief Send the Write Single Block command and check the response - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) @@ -626,7 +624,7 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) /** * @brief Send the Write Multi Block command and check the response - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) @@ -650,7 +648,7 @@ uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) /** * @brief Send the Start Address Erase command for SD and check the response - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) @@ -674,7 +672,7 @@ uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) /** * @brief Send the End Address Erase command for SD and check the response - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) @@ -698,7 +696,7 @@ uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) /** * @brief Send the Start Address Erase command and check the response - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) @@ -722,7 +720,7 @@ uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) /** * @brief Send the End Address Erase command and check the response - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) @@ -746,7 +744,7 @@ uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) /** * @brief Send the Erase command and check the response - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx) @@ -770,7 +768,7 @@ uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx) /** * @brief Send the Stop Transfer command and check the response. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx) @@ -794,8 +792,8 @@ uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx) /** * @brief Send the Select Deselect command and check the response. - * @param SDIOx: Pointer to SDIO register base - * @param addr: Address of the card to be selected + * @param SDIOx Pointer to SDIO register base + * @param addr Address of the card to be selected * @retval HAL status */ uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr) @@ -819,7 +817,7 @@ uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr) /** * @brief Send the Go Idle State command and check the response. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx) @@ -842,7 +840,7 @@ uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx) /** * @brief Send the Operating Condition command and check the response. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx) @@ -872,7 +870,7 @@ uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx) * @brief Send the Application command to verify that that the next command * is an application specific com-mand rather than a standard command * and check the response. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) @@ -899,7 +897,7 @@ uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) /** * @brief Send the command asking the accessed card to send its operating * condition register (OCR) - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType) @@ -922,7 +920,7 @@ uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType) /** * @brief Send the Bus Width command and check the response. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth) @@ -945,7 +943,7 @@ uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth) /** * @brief Send the Send SCR command and check the response. - * @param SDIOx: Pointer to SDMMC register base + * @param SDIOx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx) @@ -969,7 +967,7 @@ uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx) /** * @brief Send the Send CID command and check the response. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx) @@ -993,7 +991,7 @@ uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx) /** * @brief Send the Send CSD command and check the response. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) @@ -1017,7 +1015,7 @@ uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) /** * @brief Send the Send CSD command and check the response. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) @@ -1041,7 +1039,7 @@ uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) /** * @brief Send the Status command and check the response. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument) @@ -1064,7 +1062,7 @@ uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument) /** * @brief Send the Status register command and check the response. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx Pointer to SDIO register base * @retval HAL status */ uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx) @@ -1088,8 +1086,8 @@ uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx) /** * @brief Sends host capacity support information and activates the card's * initialization process. Send SDMMC_CMD_SEND_OP_COND command - * @param SDIOx: Pointer to SDIO register base - * @parame Argument: Argument used for the command + * @param SDIOx Pointer to SDIO register base + * @parame Argument Argument used for the command * @retval HAL status */ uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument) @@ -1112,8 +1110,8 @@ uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument) /** * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand - * @param SDIOx: Pointer to SDIO register base - * @parame Argument: Argument used for the command + * @param SDIOx Pointer to SDIO register base + * @parame Argument Argument used for the command * @retval HAL status */ uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument) @@ -1145,7 +1143,7 @@ uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument) /** * @brief Checks for error conditions for CMD0. - * @param hsd: SD handle + * @param hsd SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) @@ -1171,8 +1169,8 @@ static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) /** * @brief Checks for error conditions for R1 response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index + * @param hsd SD handle + * @param SD_CMD The sent command index * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) @@ -1301,7 +1299,7 @@ static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t /** * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param hsd: SD handle + * @param hsd SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) @@ -1343,7 +1341,7 @@ static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) /** * @brief Checks for error conditions for R3 (OCR) response. - * @param hsd: SD handle + * @param hsd SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) @@ -1379,9 +1377,9 @@ static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) /** * @brief Checks for error conditions for R6 (RCA) response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index - * @param pRCA: Pointer to the variable that will contain the SD card relative + * @param hsd SD handle + * @param SD_CMD The sent command index + * @param pRCA Pointer to the variable that will contain the SD card relative * address RCA * @retval SD Card error state */ @@ -1449,7 +1447,7 @@ static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t /** * @brief Checks for error conditions for R7 response. - * @param hsd: SD handle + * @param hsd SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h index f261debe07..b8e6296e1c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention @@ -739,35 +737,35 @@ typedef struct /** * @brief Enable the SDIO device. - * @param __INSTANCE__: SDIO Instance + * @param __INSTANCE__ SDIO Instance * @retval None */ #define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) /** * @brief Disable the SDIO device. - * @param __INSTANCE__: SDIO Instance + * @param __INSTANCE__ SDIO Instance * @retval None */ #define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) /** * @brief Enable the SDIO DMA transfer. - * @param __INSTANCE__: SDIO Instance + * @param __INSTANCE__ SDIO Instance * @retval None */ #define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) /** * @brief Disable the SDIO DMA transfer. - * @param __INSTANCE__: SDIO Instance + * @param __INSTANCE__ SDIO Instance * @retval None */ #define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) /** * @brief Enable the SDIO device interrupt. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __INTERRUPT__ specifies the SDIO interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -797,8 +795,8 @@ typedef struct /** * @brief Disable the SDIO device interrupt. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __INTERRUPT__ specifies the SDIO interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -828,8 +826,8 @@ typedef struct /** * @brief Checks whether the specified SDIO flag is set or not. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __FLAG__: specifies the flag to check. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -860,8 +858,8 @@ typedef struct /** * @brief Clears the SDIO pending flags. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __FLAG__: specifies the flag to clear. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -880,8 +878,8 @@ typedef struct /** * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__: specifies the SDIO interrupt source to check. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __INTERRUPT__ specifies the SDIO interrupt source to check. * This parameter can be one of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -911,8 +909,8 @@ typedef struct /** * @brief Clears the SDIO's interrupt pending bits. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -930,56 +928,56 @@ typedef struct /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) /** * @brief Disable Start the SD I/O Read Wait operations. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) /** * @brief Disable Stop the SD I/O Read Wait operations. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) /** * @brief Enable the SD I/O Mode Operation. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) /** * @brief Disable the SD I/O Mode Operation. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) /** * @brief Enable the SD I/O Suspend command sending. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) /** * @brief Disable the SD I/O Suspend command sending. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.c index 685a7140cc..c30e5b8a27 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_spi.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SPI LL module driver. ****************************************************************************** * @attention @@ -536,7 +534,7 @@ void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). * @param SPIx SPI Instance - * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF. + * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. * @param PrescalerParity This parameter can be one of the following values: * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h index 77085e8324..0d98b94030 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_spi.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SPI LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h index b24b8eb5c1..ca11eb767d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_system.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SYSTEM LL module. @verbatim ============================================================================== @@ -94,12 +92,14 @@ extern "C" { #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */ #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ #if defined(FSMC_Bank1) -#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ #endif /* FSMC_Bank1 */ #if defined(FMC_Bank1) -#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2 /*!< FMC/SDRAM mapped at 0x00000000 */ #endif /* FMC_Bank1 */ #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c index 16469eeaf6..583710f66a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_tim.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief TIM LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h index cecec4ba4c..d17cddf36d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_tim.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of TIM LL module. ****************************************************************************** * @attention @@ -1099,7 +1097,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) { - SET_BIT(TIMx->CR1, TIM_CR1_UDIS); + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** @@ -1110,18 +1108,18 @@ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) { - CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** * @brief Indicates whether update event generation is enabled. * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent * @param TIMx Timer instance - * @retval State of bit (1 or 0). + * @retval Inverted state of bit (0 or 1). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) { - return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); + return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.c index b68130b429..57b39270ce 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_usart.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief USART LL module driver. ****************************************************************************** * @attention @@ -75,7 +73,13 @@ /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available * divided by the smallest oversampling used on the USART (i.e. 8) */ -#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U) +#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U) + +/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ +#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ +#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ @@ -254,7 +258,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance - * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure + * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure * that contains the configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers are initialized according to USART_InitStruct content @@ -361,7 +365,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini } #endif /* UART9 */ #if defined(UART10) - else if (USARTx == UART5) + else if (USARTx == UART10) { periphclk = rcc_clocks.PCLK1_Frequency; } @@ -383,6 +387,12 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini periphclk, USART_InitStruct->OverSampling, USART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } } /* Endif (=> USART not in Disabled state => return ERROR) */ @@ -392,7 +402,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /** * @brief Set each @ref LL_USART_InitTypeDef field to default value. - * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure + * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -415,7 +425,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content @@ -476,7 +486,7 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef /** * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * whose fields will be set to default values. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.h index 9effe4f403..44ff3cb98d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_usart.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of USART LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.c index 0332ea381a..c114307b94 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -97,8 +95,8 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); /** * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -145,7 +143,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /** * @brief USB_EnableGlobalInt * Enables the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) @@ -158,7 +156,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_DisableGlobalInt * Disable the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) @@ -169,8 +167,8 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_SetCurrentMode : Set functional mode - * @param USBx : Selected device - * @param mode : current core mode + * @param USBx Selected device + * @param mode current core mode * This parameter can be one of these values: * @arg USB_OTG_DEVICE_MODE: Peripheral mode * @arg USB_OTG_HOST_MODE: Host mode @@ -197,8 +195,8 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeT /** * @brief USB_DevInit : Initializes the USB_OTG controller registers * for device mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -342,8 +340,8 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /** * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number + * @param USBx Selected device + * @param num FIFO number * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status @@ -369,7 +367,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) /** * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) @@ -393,8 +391,8 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register * depending the PHY type and the enumeration speed of the device. - * @param USBx : Selected device - * @param speed : device speed + * @param USBx Selected device + * @param speed device speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode @@ -410,7 +408,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) /** * @brief USB_GetDevSpeed :Return the Dev Speed - * @param USBx : Selected device + * @param USBx Selected device * @retval speed : device speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode @@ -440,8 +438,8 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) /** * @brief Activate and configure an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -470,8 +468,8 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy } /** * @brief Activate and configure a dedicated endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -513,8 +511,8 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB } /** * @brief De-activate and de-initialize an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -584,8 +582,8 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP /** * @brief De-activate and de-initialize a dedicated endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -656,9 +654,9 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U /** * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -708,7 +706,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) { +/* MBED */ atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1U << ep->num); +/* MBED */ } } } @@ -778,9 +778,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe /** * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -829,7 +829,9 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) { +/* MBED */ atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1U << (ep->num)); +/* MBED */ } } } @@ -866,11 +868,11 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD /** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel - * @param USBx : Selected device - * @param src : pointer to source buffer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to write - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -894,11 +896,11 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin /** * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel - * @param USBx : Selected device - * @param src : source pointer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to read - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param src source pointer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to read + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -919,8 +921,8 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) /** * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) @@ -947,8 +949,8 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef /** * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -974,7 +976,7 @@ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe /** * @brief USB_StopDevice : Stop the usb device mode - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) @@ -1003,8 +1005,8 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx : Selected device - * @param address : new device address to be assigned + * @param USBx Selected device + * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ @@ -1018,7 +1020,7 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t addre /** * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) @@ -1031,7 +1033,7 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) @@ -1044,7 +1046,7 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) @@ -1058,7 +1060,7 @@ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) @@ -1071,7 +1073,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) @@ -1084,8 +1086,8 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) /** * @brief Returns Device OUT EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number + * @param USBx Selected device + * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ @@ -1099,8 +1101,8 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) /** * @brief Returns Device IN EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number + * @param USBx Selected device + * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ @@ -1117,8 +1119,8 @@ uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) /** * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx : Selected device - * @param interrupt : interrupt flag + * @param USBx Selected device + * @param interrupt interrupt flag * @retval None */ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) @@ -1128,7 +1130,7 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) /** * @brief Returns USB core mode - * @param USBx : Selected device + * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: * 0 : Host @@ -1142,7 +1144,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) /** * @brief Activate EP0 for Setup transactions - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) @@ -1162,12 +1164,12 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) /** * @brief Prepare the EP0 to start the first control setup - * @param USBx : Selected device - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used - * @param psetup : pointer to setup packet + * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) @@ -1190,7 +1192,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin /** * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) @@ -1227,8 +1229,8 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_HostInit : Initializes the USB OTG controller registers * for Host mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -1314,8 +1316,8 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef /** * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the * HCFG register on the PHY type and set the right frame interval - * @param USBx : Selected device - * @param freq : clock frequency + * @param USBx Selected device + * @param freq clock frequency * This parameter can be one of these values: * HCFG_48_MHZ : Full Speed 48 MHz Clock * HCFG_6_MHZ : Low Speed 6 MHz Clock @@ -1339,7 +1341,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq /** * @brief USB_OTG_ResetPort : Reset Host Port - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status * @note (1)The application must wait at least 10 ms * before clearing the reset bit. @@ -1361,7 +1363,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_DriveVbus : activate or de-activate vbus - * @param state : VBUS state + * @param state VBUS state * This parameter can be one of these values: * 0 : VBUS Active * 1 : VBUS Inactive @@ -1388,7 +1390,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) /** * @brief Return Host Core speed - * @param USBx : Selected device + * @param USBx Selected device * @retval speed : Host speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode @@ -1405,7 +1407,7 @@ uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) /** * @brief Return Host Current Frame number - * @param USBx : Selected device + * @param USBx Selected device * @retval current frame number */ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) @@ -1415,25 +1417,25 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) /** * @brief Initialize a host channel - * @param USBx : Selected device - * @param ch_num : Channel number + * @param USBx Selected device + * @param ch_num Channel number * This parameter can be a value from 1 to 15 - * @param epnum : Endpoint number + * @param epnum Endpoint number * This parameter can be a value from 1 to 15 - * @param dev_address : Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 - * @param speed : Current device speed + * @param speed Current device speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode - * @param ep_type : Endpoint Type + * @param ep_type Endpoint Type * This parameter can be one of these values: * @arg EP_TYPE_CTRL: Control type * @arg EP_TYPE_ISOC: Isochronous type * @arg EP_TYPE_BULK: Bulk type * @arg EP_TYPE_INTR: Interrupt type - * @param mps : Max Packet Size + * @param mps Max Packet Size * This parameter can be a value from 0 to32K * @retval HAL state */ @@ -1529,9 +1531,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, /** * @brief Start a transfer over a host channel - * @param USBx : Selected device - * @param hc : pointer to host channel structure - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -1642,7 +1644,9 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe /* Write packet into the Tx FIFO. */ USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); +/* MBED */ hc->xfer_count = hc->xfer_len; +/* MBED */ } } @@ -1651,7 +1655,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe /** * @brief Read all host channel interrupts status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL state */ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) @@ -1661,8 +1665,8 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) /** * @brief Halt a host channel - * @param USBx : Selected device - * @param hc_num : Host Channel number + * @param USBx Selected device + * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ @@ -1722,8 +1726,8 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) /** * @brief Initiate Do Ping protocol - * @param USBx : Selected device - * @param hc_num : Host Channel number + * @param USBx Selected device + * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ @@ -1746,7 +1750,7 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) /** * @brief Stop Host Core - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL state */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.h index 2eeb11175b..1048bee537 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c index 65c05f3851..430fb02447 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_utils.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief UTILS LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.h index 21f8d49fe9..31fd3993d8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_utils.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of UTILS LL module. @verbatim ============================================================================== diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_wwdg.h index 49d2893f82..3e3b093087 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_wwdg.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_wwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of WWDG LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/system_stm32f4xx.c b/targets/TARGET_STM/TARGET_STM32F4/device/system_stm32f4xx.c index e63b31232e..7accf406e9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/system_stm32f4xx.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/system_stm32f4xx.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.c * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/hal_init_pre.c b/targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c similarity index 96% rename from targets/TARGET_STM/TARGET_STM32F4/device/hal_init_pre.c rename to targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c index 37deb42b6c..f73e97f24d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/hal_init_pre.c +++ b/targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c @@ -16,6 +16,8 @@ */ #include "stm32f4xx_hal.h" +HAL_StatusTypeDef HAL_InitPre(void); + /* this function is needed to peform hardware initialization that must happen * before the uVisor; the whole SystemInit function for the STM32F4 cannot be * put here as it depends on some APIs that need uVisor to be enabled */