diff --git a/drivers/QSPI.h b/drivers/QSPI.h
index 7b70d6ae16..73504701e4 100644
--- a/drivers/QSPI.h
+++ b/drivers/QSPI.h
@@ -102,6 +102,18 @@ public:
      *
      */
     QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
+
+    /** Create a QSPI master connected to the specified pins
+     *
+     *  io0-io3 is used to specify the Pins used for Quad SPI mode
+     *
+     *  @param pinmap reference to structure which holds static pinmap
+     *  @param mode Clock polarity and phase mode (0 - 3) of SPI
+     *         (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
+     *
+     */
+    QSPI(const qspi_pinmap_t &pinmap, int mode = 0);
+
     virtual ~QSPI()
     {
     }
@@ -222,6 +234,7 @@ protected:
     int _mode; //SPI mode
     bool _initialized;
     PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select
+    const qspi_pinmap_t *_explicit_pinmap;
 
 private:
     /* Private acquire function without locking/unlocking
@@ -229,6 +242,7 @@ private:
      */
     bool _acquire(void);
     bool _initialize();
+    bool _initialize_direct();
 
     /*
      * This function builds the qspi command struct to be send to Hal
diff --git a/drivers/source/QSPI.cpp b/drivers/source/QSPI.cpp
index b87843dfba..ed7df6e8c2 100644
--- a/drivers/source/QSPI.cpp
+++ b/drivers/source/QSPI.cpp
@@ -49,6 +49,7 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin
     _qspi_io3 = io3;
     _qspi_clk = sclk;
     _qspi_cs = ssel;
+    _explicit_pinmap = NULL;
     _inst_width = QSPI_CFG_BUS_SINGLE;
     _address_width = QSPI_CFG_BUS_SINGLE;
     _address_size = QSPI_CFG_ADDR_SIZE_24;
@@ -65,6 +66,31 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin
     MBED_ASSERT(success);
 }
 
+QSPI::QSPI(const qspi_pinmap_t &pinmap, int mode) : _qspi()
+{
+    _qspi_io0 = pinmap.data0_pin;
+    _qspi_io1 = pinmap.data1_pin;
+    _qspi_io2 = pinmap.data2_pin;
+    _qspi_io3 = pinmap.data3_pin;
+    _qspi_clk = pinmap.sclk_pin;
+    _qspi_cs = pinmap.ssel_pin;
+    _explicit_pinmap = &pinmap;
+    _inst_width = QSPI_CFG_BUS_SINGLE;
+    _address_width = QSPI_CFG_BUS_SINGLE;
+    _address_size = QSPI_CFG_ADDR_SIZE_24;
+    _alt_width = QSPI_CFG_BUS_SINGLE;
+    _alt_size = QSPI_CFG_ALT_SIZE_8;
+    _data_width = QSPI_CFG_BUS_SINGLE;
+    _num_dummy_cycles = 0;
+    _mode = mode;
+    _hz = ONE_MHZ;
+    _initialized = false;
+
+    //Go ahead init the device here with the default config
+    bool success = _initialize_direct();
+    MBED_ASSERT(success);
+}
+
 qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width, qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width, int dummy_cycles)
 {
     // Check that alt_size/alt_width are a valid combination
@@ -255,6 +281,24 @@ bool QSPI::_initialize()
     return _initialized;
 }
 
+// Note: Private helper function to initialize qspi HAL
+bool QSPI::_initialize_direct()
+{
+    if (_mode != 0 && _mode != 1) {
+        _initialized = false;
+        return _initialized;
+    }
+
+    qspi_status_t ret = qspi_init_direct(&_qspi, _explicit_pinmap, _hz, _mode);
+    if (QSPI_STATUS_OK == ret) {
+        _initialized = true;
+    } else {
+        _initialized = false;
+    }
+
+    return _initialized;
+}
+
 // Note: Private function with no locking
 bool QSPI::_acquire()
 {