diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/mbed_overrides.c
index 443d26a8fa..5e9d49122c 100644
--- a/targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/mbed_overrides.c
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351/mbed_overrides.c
@@ -33,7 +33,7 @@ void mbed_sdk_init(void)
     /* Unlock protected registers */
     SYS_UnlockReg();
 
-    /* Enable HIRC clock (Internal RC 22.1184MHz) */
+    /* Enable HIRC clock (Internal RC 12MHz) */
     CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
     /* Enable HXT clock (external XTAL 12MHz) */
     CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
@@ -41,6 +41,8 @@ void mbed_sdk_init(void)
     CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
     /* Enable LXT for RTC */
     CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
+    /* Enable HIRC48 clock (Internal RC 48MHz) */
+    CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
 
     /* Wait for HIRC clock ready */
     CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
@@ -50,13 +52,20 @@ void mbed_sdk_init(void)
     CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
     /* Wait for LXT clock ready */
     CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
+    /* Wait for HIRC48 clock ready */
+    CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
 
+    /* NOTE: There is a reset halt issue with PLL in A version. Work around it
+     *       by using HIRC48 instead of PLL as HCLK clock source. */
+#if 0
     /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
     CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
     
     /* Set core clock as 48M from PLL */
     CLK_SetCoreClock(FREQ_48MHZ);
-
+#else
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC48, CLK_CLKDIV0_HCLK(1UL));
+#endif
     
     /* Update System Core Clock */
     /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_clk.c b/targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_clk.c
index b653206960..d70b4da01d 100644
--- a/targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_clk.c
+++ b/targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_clk.c
@@ -371,9 +371,8 @@ uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
        Select HCLK clock source divider as 1
        and update system core clock
     */
-//    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
-    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC48, CLK_CLKDIV0_HCLK(1UL)); /* To use HIRC instead of PLL to avoid reset halt issue in A version */
-    
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
+  
     /* Disable HIRC if HIRC is disabled before setting core clock */
     if(u32HIRCSTB == 0UL)
     {