From 0c594858fd1f5410372488fa13a4c8e83b995044 Mon Sep 17 00:00:00 2001 From: Jeremy Brodt Date: Tue, 16 Aug 2016 09:20:46 -0500 Subject: [PATCH] Updated bit-band macros to match latest MXC convention. --- .../cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h | 8 ++++---- .../TARGET_Maxim/TARGET_MAX32600/system_max32600.c | 8 ++++---- .../cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h | 10 ++++------ .../TARGET_Maxim/TARGET_MAX32610/system_max32610.c | 8 ++++---- 4 files changed, 16 insertions(+), 18 deletions(-) diff --git a/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h b/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h index 5b50a7aabe..58a8ff40ef 100644 --- a/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h +++ b/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h @@ -656,10 +656,10 @@ typedef enum { /*******************************************************************************/ -#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) -#define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0 -#define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1 -#define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) +#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) +#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) +#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) +#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) /*******************************************************************************/ diff --git a/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c b/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c index 3d4c58687b..4467248493 100644 --- a/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c +++ b/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c @@ -130,9 +130,9 @@ void Trim_RO(void) MXC_ADCCFG->ro_cal1 = (MXC_ADCCFG->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) | ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT); MXC_ADCCFG->ro_cal0 = (MXC_ADCCFG->ro_cal0 & ~MXC_F_ADC_RO_CAL0_TRM_MU) | (0x04 << MXC_F_ADC_RO_CAL0_TRM_MU_POS); - BITBAND_SetBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS); - BITBAND_SetBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); - BITBAND_SetBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS); + MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS); + MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); + MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS); SysTick->LOAD = 1635; /* about 50ms, based on a 32KHz systick clock */ SysTick->VAL = 0; @@ -142,7 +142,7 @@ void Trim_RO(void) SysTick->CTRL = 0; trim = (MXC_ADCCFG->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> (MXC_F_ADC_RO_CAL0_RO_TRM_POS + 2); - BITBAND_ClrBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); + MXC_CLRBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); MXC_PWRSEQ->reg5 = (MXC_PWRSEQ->reg5 & ~MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) | ((trim << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF); diff --git a/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h b/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h index 182a9078fe..ca6b9ad006 100644 --- a/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h +++ b/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h @@ -109,7 +109,6 @@ typedef enum IRQn_Type { #include /* Processor and core peripherals */ #include "system_max32610.h" /* System Header */ - /* ================================================================================ */ /* ================== Device Specific Memory Section ================== */ /* ================================================================================ */ @@ -126,7 +125,6 @@ typedef enum IRQn_Type { /*******************************************************************************/ /* General Purpose I/O Ports (GPIO) */ - #define MXC_BASE_GPIO ((uint32_t)0x40000000UL) #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) #define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL) @@ -645,10 +643,10 @@ typedef enum { /*******************************************************************************/ -#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) -#define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0 -#define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1 -#define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) +#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) +#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) +#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) +#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) /*******************************************************************************/ diff --git a/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c b/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c index 0cb8492442..4109a04926 100644 --- a/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c +++ b/hal/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c @@ -130,9 +130,9 @@ void Trim_RO(void) MXC_ADCCFG->ro_cal1 = (MXC_ADCCFG->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) | ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT); MXC_ADCCFG->ro_cal0 = (MXC_ADCCFG->ro_cal0 & ~MXC_F_ADC_RO_CAL0_TRM_MU) | (0x04 << MXC_F_ADC_RO_CAL0_TRM_MU_POS); - BITBAND_SetBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS); - BITBAND_SetBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); - BITBAND_SetBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS); + MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS); + MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); + MXC_SETBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS); SysTick->LOAD = 1635; /* about 50ms, based on a 32KHz systick clock */ SysTick->VAL = 0; @@ -142,7 +142,7 @@ void Trim_RO(void) SysTick->CTRL = 0; trim = (MXC_ADCCFG->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> (MXC_F_ADC_RO_CAL0_RO_TRM_POS + 2); - BITBAND_ClrBit(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); + MXC_CLRBIT(&MXC_ADCCFG->ro_cal0, MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS); MXC_PWRSEQ->reg5 = (MXC_PWRSEQ->reg5 & ~MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF) | ((trim << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF);