mirror of https://github.com/ARMmbed/mbed-os.git
CMake: Fix selection of scatter file and startup file for DISCO_L475_IOT01A
parent
4fc678c30d
commit
0ba05246cc
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@ -5,7 +5,7 @@ function(_mbed_get_assembly_disco_l475vg_iot01a)
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if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
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set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S)
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elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
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set(STARTUP_FILE TOOLCHAIN_ARM_STD/startup_stm32l475xx.S)
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set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32l475xx.S)
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elseif(${MBED_TOOLCHAIN} STREQUAL "IAR")
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set(STARTUP_FILE TOOLCHAIN_IAR/startup_stm32l475xx.S)
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endif()
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@ -16,7 +16,7 @@ function(_mbed_set_linker_file)
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if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
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set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_GCC_ARM/STM32L475XX.ld)
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elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
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set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_ARM_STD/stm32l475xx.sct)
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set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_ARM/stm32l475xx.sct)
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elseif(${MBED_TOOLCHAIN} STREQUAL "IAR")
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set(LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/TOOLCHAIN_IAR/stm32l475xx.icf)
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endif()
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@ -1,371 +0,0 @@
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;*******************************************************************************
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;* File Name : startup_stm32l475xx.s
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;* Author : MCD Application Team
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;* Description : STM32L475xx Ultra Low Power devices vector table for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;*******************************************************************************
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;*
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;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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;* All rights reserved.</center></h2>
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;*
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;* This software component is licensed by ST under BSD 3-Clause license,
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;* the "License"; You may not use this file except in compliance with the
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;* License. You may obtain a copy of the License at:
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;* opensource.org/licenses/BSD-3-Clause
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;*
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;*******************************************************************************
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
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DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_IRQHandler ; EXTI Line2
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
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DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
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DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
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DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
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DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
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DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
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DCD ADC1_2_IRQHandler ; ADC1, ADC2
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DCD CAN1_TX_IRQHandler ; CAN1 TX
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DCD CAN1_RX0_IRQHandler ; CAN1 RX0
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DCD CAN1_RX1_IRQHandler ; CAN1 RX1
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DCD CAN1_SCE_IRQHandler ; CAN1 SCE
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
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DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
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DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; External Line[15:10]
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
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DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
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DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
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DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
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DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
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DCD ADC3_IRQHandler ; ADC3 global Interrupt
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DCD FMC_IRQHandler ; FMC
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DCD SDMMC1_IRQHandler ; SDMMC1
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DCD TIM5_IRQHandler ; TIM5
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DCD SPI3_IRQHandler ; SPI3
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DCD UART4_IRQHandler ; UART4
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DCD UART5_IRQHandler ; UART5
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
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DCD TIM7_IRQHandler ; TIM7
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DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
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DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
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DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
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DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
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DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
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DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
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DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
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DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
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DCD COMP_IRQHandler ; COMP Interrupt
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DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
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DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
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DCD OTG_FS_IRQHandler ; USB OTG FS
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DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
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DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
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DCD LPUART1_IRQHandler ; LP UART1 interrupt
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DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
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DCD I2C3_EV_IRQHandler ; I2C3 event
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DCD I2C3_ER_IRQHandler ; I2C3 error
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DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
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DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
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DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
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DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD RNG_IRQHandler ; RNG global interrupt
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DCD FPU_IRQHandler ; FPU
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_PVM_IRQHandler [WEAK]
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EXPORT TAMP_STAMP_IRQHandler [WEAK]
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EXPORT RTC_WKUP_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA1_Channel1_IRQHandler [WEAK]
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EXPORT DMA1_Channel2_IRQHandler [WEAK]
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EXPORT DMA1_Channel3_IRQHandler [WEAK]
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EXPORT DMA1_Channel4_IRQHandler [WEAK]
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EXPORT DMA1_Channel5_IRQHandler [WEAK]
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EXPORT DMA1_Channel6_IRQHandler [WEAK]
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EXPORT DMA1_Channel7_IRQHandler [WEAK]
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EXPORT ADC1_2_IRQHandler [WEAK]
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EXPORT CAN1_TX_IRQHandler [WEAK]
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EXPORT CAN1_RX0_IRQHandler [WEAK]
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EXPORT CAN1_RX1_IRQHandler [WEAK]
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EXPORT CAN1_SCE_IRQHandler [WEAK]
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EXPORT EXTI9_5_IRQHandler [WEAK]
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EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
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EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
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EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
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EXPORT TIM1_CC_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM3_IRQHandler [WEAK]
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EXPORT TIM4_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT I2C2_EV_IRQHandler [WEAK]
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EXPORT I2C2_ER_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT USART3_IRQHandler [WEAK]
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EXPORT EXTI15_10_IRQHandler [WEAK]
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EXPORT RTC_Alarm_IRQHandler [WEAK]
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EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
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EXPORT TIM8_BRK_IRQHandler [WEAK]
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EXPORT TIM8_UP_IRQHandler [WEAK]
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EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
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EXPORT TIM8_CC_IRQHandler [WEAK]
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EXPORT ADC3_IRQHandler [WEAK]
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EXPORT FMC_IRQHandler [WEAK]
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EXPORT SDMMC1_IRQHandler [WEAK]
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EXPORT TIM5_IRQHandler [WEAK]
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EXPORT SPI3_IRQHandler [WEAK]
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EXPORT UART4_IRQHandler [WEAK]
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EXPORT UART5_IRQHandler [WEAK]
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EXPORT TIM6_DAC_IRQHandler [WEAK]
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EXPORT TIM7_IRQHandler [WEAK]
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EXPORT DMA2_Channel1_IRQHandler [WEAK]
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EXPORT DMA2_Channel2_IRQHandler [WEAK]
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EXPORT DMA2_Channel3_IRQHandler [WEAK]
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EXPORT DMA2_Channel4_IRQHandler [WEAK]
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EXPORT DMA2_Channel5_IRQHandler [WEAK]
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EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
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EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
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EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
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EXPORT COMP_IRQHandler [WEAK]
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EXPORT LPTIM1_IRQHandler [WEAK]
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EXPORT LPTIM2_IRQHandler [WEAK]
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EXPORT OTG_FS_IRQHandler [WEAK]
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EXPORT DMA2_Channel6_IRQHandler [WEAK]
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EXPORT DMA2_Channel7_IRQHandler [WEAK]
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EXPORT LPUART1_IRQHandler [WEAK]
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EXPORT QUADSPI_IRQHandler [WEAK]
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EXPORT I2C3_EV_IRQHandler [WEAK]
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EXPORT I2C3_ER_IRQHandler [WEAK]
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EXPORT SAI1_IRQHandler [WEAK]
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EXPORT SAI2_IRQHandler [WEAK]
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EXPORT SWPMI1_IRQHandler [WEAK]
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EXPORT TSC_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT FPU_IRQHandler [WEAK]
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WWDG_IRQHandler
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PVD_PVM_IRQHandler
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TAMP_STAMP_IRQHandler
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RTC_WKUP_IRQHandler
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FLASH_IRQHandler
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RCC_IRQHandler
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EXTI0_IRQHandler
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EXTI1_IRQHandler
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EXTI2_IRQHandler
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EXTI3_IRQHandler
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EXTI4_IRQHandler
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DMA1_Channel1_IRQHandler
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DMA1_Channel2_IRQHandler
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DMA1_Channel3_IRQHandler
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DMA1_Channel4_IRQHandler
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DMA1_Channel5_IRQHandler
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DMA1_Channel6_IRQHandler
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DMA1_Channel7_IRQHandler
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ADC1_2_IRQHandler
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CAN1_TX_IRQHandler
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CAN1_RX0_IRQHandler
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CAN1_RX1_IRQHandler
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CAN1_SCE_IRQHandler
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EXTI9_5_IRQHandler
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TIM1_BRK_TIM15_IRQHandler
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TIM1_UP_TIM16_IRQHandler
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TIM1_TRG_COM_TIM17_IRQHandler
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TIM1_CC_IRQHandler
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TIM2_IRQHandler
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TIM3_IRQHandler
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TIM4_IRQHandler
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I2C1_EV_IRQHandler
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I2C1_ER_IRQHandler
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I2C2_EV_IRQHandler
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I2C2_ER_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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USART3_IRQHandler
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EXTI15_10_IRQHandler
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RTC_Alarm_IRQHandler
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DFSDM1_FLT3_IRQHandler
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TIM8_BRK_IRQHandler
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TIM8_UP_IRQHandler
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TIM8_TRG_COM_IRQHandler
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TIM8_CC_IRQHandler
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ADC3_IRQHandler
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FMC_IRQHandler
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SDMMC1_IRQHandler
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TIM5_IRQHandler
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SPI3_IRQHandler
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UART4_IRQHandler
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UART5_IRQHandler
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TIM6_DAC_IRQHandler
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TIM7_IRQHandler
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DMA2_Channel1_IRQHandler
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DMA2_Channel2_IRQHandler
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DMA2_Channel3_IRQHandler
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DMA2_Channel4_IRQHandler
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DMA2_Channel5_IRQHandler
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DFSDM1_FLT0_IRQHandler
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DFSDM1_FLT1_IRQHandler
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DFSDM1_FLT2_IRQHandler
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COMP_IRQHandler
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LPTIM1_IRQHandler
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LPTIM2_IRQHandler
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OTG_FS_IRQHandler
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DMA2_Channel6_IRQHandler
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DMA2_Channel7_IRQHandler
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LPUART1_IRQHandler
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QUADSPI_IRQHandler
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I2C3_EV_IRQHandler
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I2C3_ER_IRQHandler
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SAI1_IRQHandler
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SAI2_IRQHandler
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SWPMI1_IRQHandler
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TSC_IRQHandler
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RNG_IRQHandler
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FPU_IRQHandler
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B .
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ENDP
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ALIGN
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END
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;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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@ -1,78 +0,0 @@
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#! armcc -E
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; Scatter-Loading Description File
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;
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; SPDX-License-Identifier: BSD-3-Clause
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;******************************************************************************
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;* @attention
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;*
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;* Copyright (c) 2016-2020 STMicroelectronics.
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;* All rights reserved.
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;*
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;* This software component is licensed by ST under BSD 3-Clause license,
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;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
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;*
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;******************************************************************************
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#include "../cmsis_nvic.h"
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#if !defined(MBED_APP_START)
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#define MBED_APP_START MBED_ROM_START
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#endif
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE MBED_ROM_SIZE
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#endif
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#if !defined(MBED_BOOT_STACK_SIZE)
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/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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/* Round up VECTORS_SIZE to 8 bytes */
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#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
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; Crash report enabled as default
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#if !defined(MBED_CRASH_REPORT_RAM_SIZE)
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#define MBED_CRASH_REPORT_RAM_SIZE 0x100
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#endif
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;Vectors + Crash report - Fixed at start of RAM2 in sequence
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#define MBED_IRAM2_SIZE (MBED_RAM1_SIZE - VECTORS_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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#define MBED_CRASH_REPORT_RAM_START (MBED_RAM1_START + VECTORS_SIZE)
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#define MBED_IRAM2_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
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; Minimum heap should be larger then smallest RAM bank (else can use
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; that bank for heap) and less then largest RAM bank.
|
||||
#define MINIMUM_HEAP 0x12000
|
||||
|
||||
;Splitting the RW and ZI section in IRAM1 (MBED_RAM_SIZE-MINIMUM_HEAP = 0x6000 available)
|
||||
;and IRAM2 (MBED_IRAM2_SIZE = 0x7D78 available)
|
||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
|
||||
|
||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE {
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
|
||||
}
|
||||
|
||||
RW_IRAM1 MBED_RAM_START (MBED_RAM_SIZE - MINIMUM_HEAP) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
|
||||
}
|
||||
|
||||
RW_IRAM2 MBED_IRAM2_START MBED_IRAM2_SIZE {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
|
||||
}
|
||||
}
|
|
@ -1,4 +1,4 @@
|
|||
#! armcc -E
|
||||
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
|
||||
; Scatter-Loading Description File
|
||||
;
|
||||
; SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
Loading…
Reference in New Issue