mirror of https://github.com/ARMmbed/mbed-os.git
musca_a1: Add TF-M compatibility
Make the MUSCA_A1 target TF-M compatible by doing the following:
- Add flash, region definitions, and preprocessed image macros from
TF-M (at version 6e7be077eabe "Core: Add lifecycle API")
- Update the MUSCA_A1 linker script to create a flash image
compatible with TF-M.
- Update the tfm/bin_utils/assemble.py signing script to work with
preprocessed image macros rather than flat C pre-processor defines
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Jaeden Amero <jaeden.amero@arm.com>
pull/12735/head
Devaraj Ranganna
Jaeden Amero
parent
803d295d75
commit
0ad1a988ec
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@ -32,7 +32,7 @@
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MEMORY
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{
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CODE_RAM (rx) : ORIGIN = NS_CODE_START, LENGTH = ((TOTAL_CODE_SRAM_SIZE / 2) - BL2_HEADER_SIZE)
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FLASH (rx) : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
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/* Vector table is copied to RAM, so RAM address needs to be adjusted */
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RAM (rwx) : ORIGIN = NVIC_RAM_VECTOR_LIMIT, LENGTH = (NS_DATA_SIZE - NVIC_RAM_VECTOR_SIZE)
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}
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@ -46,37 +46,20 @@ ENTRY(Reset_Handler)
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SECTIONS
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{
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/* Startup section is loaded to Flash and runs from Flash */
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.startup :
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.text :
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{
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KEEP(*(.vectors))
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__Vectors_End = .;
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__Vectors_Size = __Vectors_End - __Vectors;
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__end__ = .;
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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} > CODE_RAM
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > CODE_RAM
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > CODE_RAM
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__exidx_end = .;
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/* The text section is loaded into Flash but runs from SRAM
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* The load address is aligned to 8 bytes
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*/
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.text : ALIGN(8)
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{
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*(.text*)
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/* .ctors */
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*crtbegin.o(.ctors)
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@ -95,25 +78,26 @@ SECTIONS
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*(.rodata*)
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KEEP(*(.eh_frame*))
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} >CODE_RAM
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. = ALIGN(8); /* This alignment is needed to make the section size 8 bytes aligned */
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} > FLASH
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/* Create same symbols that armclang does so that in the c files
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* we do not have to deal with the compiler type
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*/
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Image$$ER_CODE_SRAM$$Base = ADDR(.text);
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Image$$ER_CODE_SRAM$$Limit = .;
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Image$$ER_CODE_SRAM$$Length = Image$$ER_CODE_SRAM$$Limit - Image$$ER_CODE_SRAM$$Base;
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Load$$ER_CODE_SRAM$$Base = LOADADDR(.text);
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Load$$ER_CODE_SRAM$$Length = Image$$ER_CODE_SRAM$$Length;
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Load$$ER_CODE_SRAM$$Limit = Load$$ER_CODE_SRAM$$Base + Load$$ER_CODE_SRAM$$Length;
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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__exidx_end = .;
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/* To copy multiple ROM to RAM sections,
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* define etext2/data2_start/data2_end and
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* define __STARTUP_COPY_MULTIPLE in startup_cmsdk_musca_ns.S */
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.copy.table :
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{
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. = ALIGN(8);
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (__etext)
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LONG (__data_start__)
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@ -122,36 +106,37 @@ SECTIONS
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LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
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LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
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__copy_table_end__ = .;
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} > CODE_RAM
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} > FLASH
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/* To clear multiple BSS sections,
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* uncomment .zero.table section and,
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* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_musca_ns.S */
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.zero.table :
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{
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. = ALIGN(8);
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. = ALIGN(4);
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__zero_table_start__ = .;
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LONG (__bss_start__)
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LONG (__bss_end__ - __bss_start__)
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LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
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LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
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__zero_table_end__ = .;
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} > CODE_RAM
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} > FLASH
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__etext = .;
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.data : ALIGN(8)
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.data : AT (__etext)
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{
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__data_start__ = .;
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*(vtable)
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*(.data*)
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. = ALIGN(8);
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(8);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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@ -159,7 +144,7 @@ SECTIONS
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(8);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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@ -167,19 +152,19 @@ SECTIONS
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PROVIDE_HIDDEN (__fini_array_end = .);
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KEEP(*(.jcr*))
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. = ALIGN(8);
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. = ALIGN(4);
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/* All data end */
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__data_end__ = .;
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} > RAM AT>CODE_RAM
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} > RAM
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.bss :
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{
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. = ALIGN(8);
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. = ALIGN(4);
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(8);
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. = ALIGN(4);
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__bss_end__ = .;
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} > RAM
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@ -80,6 +80,6 @@
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#define USEC_REPORTED_FREQ_HZ (TIMER_FREQ_HZ >> USEC_REPORTED_SHIFT)
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#define USEC_REPORTED_BITS (32 - USEC_REPORTED_SHIFT)
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#define UART_DEFAULT_BAUD_RATE 9600U
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#define DEFAULT_UART_BAUDRATE 9600U
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#endif /* __ARM_LTD_DEVICE_CFG_H__ */
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@ -19,23 +19,25 @@
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#ifndef __FLASH_LAYOUT_H__
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#define __FLASH_LAYOUT_H__
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/* Flash layout on Musca with BL2:
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* 0x0020_0000 BL2 - MCUBoot(128 KB)
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* 0x0022_0000 Flash_area_image_0(1 MB)
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/* Flash layout on Musca with BL2 (single image boot, mandatory):
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*
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* 0x0020_0000 BL2 - MCUBoot (128 KB)
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* 0x0022_0000 Primary image area (1 MB):
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* 0x0022_0000 Secure image primary
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* 0x002A_0000 Non-secure image primary
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* 0x0032_0000 Flash_area_image_1(1 MB)
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* 0x0032_0000 Secondary image area (1 MB):
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* 0x0032_0000 Secure image secondary
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* 0x003A_0000 Non-secure image secondary
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* 0x0042_0000 Secure Storage Area(0.02 MB)
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* 0x0042_5000 NV counters area(16 Bytes)
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* 0x0042_5010 Unused
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* 0x0042_0000 Secure Storage Area (8 KB)
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* 0x0042_2000 Internal Trusted Storage Area (8 KB)
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* 0x0042_4000 NV counters area (4 KB)
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* 0x0042_5000 Unused
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*/
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/* Code SRAM layout on Musca (with BL2, which is mandatory) after the newest
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* image has been copied to SRAM:
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* 0x0000_0000 BL2 - MCUBoot(128 KB)
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* 0x0002_0000 Flash_area_newest_image(1 MB)
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* 0x0000_0000 BL2 - MCUBoot (128 KB)
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* 0x0002_0000 Flash_area_newest_image (1 MB)
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* 0x0002_0000 Secure image primary
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* 0x000A_0000 Non-secure image primary
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* 0x0012_00000 Unused
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@ -43,65 +45,124 @@
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/* This header file is included from linker scatter file as well, where only a
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* limited C constructs are allowed. Therefore it is not possible to include
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* here the platform_retarget.h to access flash related defines. To resolve this
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* some of the values are redefined here with different names, these are marked
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* with comment.
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* here the platform_base_address.h to access flash related defines. To resolve
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* this some of the values are redefined here with different names, these are
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* marked with comment.
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*/
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/* The size of a partition. This should be large enough to contain a S or NS
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* sw binary. Each FLASH_AREA_IMAGE contains two partitions. See Flash layout
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* above.
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*/
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#define FLASH_PARTITION_SIZE (0x80000) /* 512KB */
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/* Size of a Secure and of a Non-secure image */
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#define FLASH_S_PARTITION_SIZE (0x80000) /* S partition: 512 KB */
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#define FLASH_NS_PARTITION_SIZE (0x80000) /* NS partition: 512 KB */
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#define FLASH_MAX_PARTITION_SIZE ((FLASH_S_PARTITION_SIZE > \
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FLASH_NS_PARTITION_SIZE) ? \
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FLASH_S_PARTITION_SIZE : \
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FLASH_NS_PARTITION_SIZE)
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/* Sector size of the flash hardware */
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#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4KB */
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#define FLASH_TOTAL_SIZE (0x800000) /* 8MB */
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#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB */
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#define FLASH_TOTAL_SIZE (0x800000) /* 8 MB */
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/* Flash layout info for BL2 bootloader */
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#define FLASH_BASE_ADDRESS (0x10200000) /* same as FLASH0_BASE_S */
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/* Same as MPC_QSPI_RANGE_BASE_S */
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#define FLASH_BASE_ADDRESS (0x10200000)
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/* Offset and size definitions of the flash partitions that are handled by the
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* bootloader. The image swapping is done between IMAGE_0 and IMAGE_1, SCRATCH
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* is used as a temporary storage during image swapping.
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* bootloader. The image swapping is done between IMAGE_PRIMARY and
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* IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image
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* swapping.
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*/
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#define FLASH_AREA_BL2_OFFSET (0x0)
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#define FLASH_AREA_BL2_SIZE (0x20000) /* 128KB */
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#define FLASH_AREA_BL2_OFFSET (0x0)
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#define FLASH_AREA_BL2_SIZE (0x20000) /* 128KB */
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#define FLASH_AREA_IMAGE_0_OFFSET (0x20000)
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#define FLASH_AREA_IMAGE_0_SIZE (2 * FLASH_PARTITION_SIZE)
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#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)
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/* Secure + Non-secure image primary slot */
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#define FLASH_AREA_0_ID (1)
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#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE)
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#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + \
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FLASH_NS_PARTITION_SIZE)
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/* Secure + Non-secure secondary slot */
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#define FLASH_AREA_2_ID (FLASH_AREA_0_ID + 1)
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#define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE)
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#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE + \
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FLASH_NS_PARTITION_SIZE)
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/* Not used, only the RAM loading firmware upgrade operation
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* is supported on Musca-A.
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*/
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#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1)
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#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE)
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#define FLASH_AREA_SCRATCH_SIZE (0)
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/* Maximum number of image sectors supported by the bootloader. */
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#define BOOT_MAX_IMG_SECTORS ((FLASH_S_PARTITION_SIZE + \
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FLASH_NS_PARTITION_SIZE) / \
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FLASH_AREA_IMAGE_SECTOR_SIZE)
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#elif (MCUBOOT_IMAGE_NUMBER == 2)
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/* Secure image primary slot */
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#define FLASH_AREA_0_ID (1)
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#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE)
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#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE)
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/* Non-secure image primary slot */
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#define FLASH_AREA_1_ID (FLASH_AREA_0_ID + 1)
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#define FLASH_AREA_1_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE)
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#define FLASH_AREA_1_SIZE (FLASH_NS_PARTITION_SIZE)
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/* Secure image secondary slot */
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#define FLASH_AREA_2_ID (FLASH_AREA_1_ID + 1)
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#define FLASH_AREA_2_OFFSET (FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE)
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#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE)
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/* Non-secure image secondary slot */
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#define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1)
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#define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE)
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#define FLASH_AREA_3_SIZE (FLASH_NS_PARTITION_SIZE)
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/* Not used, only the RAM loading firmware upgrade operation
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* is supported on Musca-A.
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*/
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#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1)
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#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE)
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#define FLASH_AREA_SCRATCH_SIZE (0)
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/* Maximum number of image sectors supported by the bootloader. */
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#define BOOT_MAX_IMG_SECTORS (FLASH_MAX_PARTITION_SIZE / \
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FLASH_AREA_IMAGE_SECTOR_SIZE)
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#else /* MCUBOOT_IMAGE_NUMBER > 2 */
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#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!"
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#endif /* MCUBOOT_IMAGE_NUMBER */
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#define FLASH_AREA_IMAGE_1_OFFSET (0x120000)
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#define FLASH_AREA_IMAGE_1_SIZE (2 * FLASH_PARTITION_SIZE)
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/* Not used, only RAM loading is supported on Musca A1 */
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#define FLASH_AREA_IMAGE_SCRATCH_OFFSET (0x220000)
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#define FLASH_AREA_IMAGE_SCRATCH_SIZE (0)
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/*
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* Not used, only RAM loading is supported on Musca A1.
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* The maximum number of status entries supported by the bootloader.
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/* Not used, only the RAM loading firmware upgrade operation
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* is supported on Musca-A. The maximum number of status entries
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* supported by the bootloader.
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*/
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#define BOOT_STATUS_MAX_ENTRIES (0)
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/** Maximum number of image sectors supported by the bootloader. */
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#define BOOT_MAX_IMG_SECTORS ((2 * FLASH_PARTITION_SIZE) / \
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FLASH_AREA_IMAGE_SECTOR_SIZE)
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/* Secure Storage (SST) Service definitions */
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#define FLASH_SST_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + \
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FLASH_AREA_SCRATCH_SIZE)
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#define FLASH_SST_AREA_SIZE (0x2000) /* 8 KB */
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#define FLASH_SST_AREA_OFFSET (FLASH_AREA_IMAGE_SCRATCH_OFFSET + \
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FLASH_AREA_IMAGE_SCRATCH_SIZE)
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#define FLASH_SST_AREA_SIZE (0x5000) /* 20 KB */
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#define FLASH_NV_COUNTERS_AREA_OFFSET (FLASH_SST_AREA_OFFSET + \
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/* Internal Trusted Storage (ITS) Service definitions */
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#define FLASH_ITS_AREA_OFFSET (FLASH_SST_AREA_OFFSET + \
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FLASH_SST_AREA_SIZE)
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#define FLASH_NV_COUNTERS_AREA_SIZE (0x10) /* 16 Bytes */
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#define FLASH_ITS_AREA_SIZE (0x2000) /* 8 KB */
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/* Offset and size definition in flash area, used by assemble.py */
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#define SECURE_IMAGE_OFFSET 0x0
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#define SECURE_IMAGE_MAX_SIZE 0x80000
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/* NV Counters definitions */
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#define FLASH_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + \
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FLASH_ITS_AREA_SIZE)
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#define FLASH_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE)
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/* Offset and size definition in flash area used by assemble.py */
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#define SECURE_IMAGE_OFFSET (0x0)
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#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE
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#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + \
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SECURE_IMAGE_MAX_SIZE)
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#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE
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/* Image load address used by imgtool.py */
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#define IMAGE_LOAD_ADDRESS (S_SRAM_ALIAS_BASE + \
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FLASH_AREA_BL2_SIZE)
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/* Define where executable memory for the images starts and ends */
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#define IMAGE_EXECUTABLE_RAM_START (IMAGE_LOAD_ADDRESS)
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#define IMAGE_EXECUTABLE_RAM_SIZE (FLASH_S_PARTITION_SIZE + \
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FLASH_NS_PARTITION_SIZE)
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#define NON_SECURE_IMAGE_OFFSET 0x80000
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#define NON_SECURE_IMAGE_MAX_SIZE 0x80000
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#define S_QSPI_ALIAS_BASE (0x10200000)
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#define NS_QSPI_ALIAS_BASE (0x00200000)
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@ -109,45 +170,72 @@
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#define S_SRAM_ALIAS_BASE (0x10000000)
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#define NS_SRAM_ALIAS_BASE (0x00000000)
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/* Address that tells the bootloader where in SRAM to copy the image from flash
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* E.g. Lowest address = S_SRAM_ALIAS_BASE
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* + FLASH_AREA_BL2_SIZE
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* = 0x10000000 + 0x20000 = 0x10020000
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* Please make sure the value is in the form of hex. here
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*/
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#define IMAGE_LOAD_ADDRESS 0x10020000
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|
||||
/* Flash device name used by BL2 and SST
|
||||
/* Flash device name used by BL2
|
||||
* Name is defined in flash driver file: Driver_Flash.c
|
||||
*/
|
||||
#define FLASH_DEV_NAME Driver_FLASH0
|
||||
|
||||
/* Secure Storage (SST) Service definitions */
|
||||
/* Secure Storage (SST) Service definitions
|
||||
* Note: Further documentation of these definitions can be found in the
|
||||
* TF-M SST Integration Guide.
|
||||
*/
|
||||
#define SST_FLASH_DEV_NAME Driver_FLASH0
|
||||
|
||||
/* In this target the CMSIS driver requires only the offset from the base
|
||||
* address instead of the full memory address.
|
||||
*/
|
||||
#define SST_FLASH_AREA_ADDR FLASH_SST_AREA_OFFSET
|
||||
#define SST_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
|
||||
/* The sectors must be in consecutive memory location */
|
||||
#define SST_NBR_OF_SECTORS (FLASH_SST_AREA_SIZE / SST_SECTOR_SIZE)
|
||||
#define SST_FLASH_AREA_ADDR FLASH_SST_AREA_OFFSET
|
||||
/* Dedicated flash area for SST */
|
||||
#define SST_FLASH_AREA_SIZE FLASH_SST_AREA_SIZE
|
||||
#define SST_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
|
||||
/* Number of SST_SECTOR_SIZE per block */
|
||||
#define SST_SECTORS_PER_BLOCK (0x1)
|
||||
/* Specifies the smallest flash programmable unit in bytes */
|
||||
#define SST_FLASH_PROGRAM_UNIT 0x1
|
||||
#define SST_FLASH_PROGRAM_UNIT (0x1)
|
||||
/* The maximum asset size to be stored in the SST area */
|
||||
#define SST_MAX_ASSET_SIZE (512)
|
||||
/* The maximum number of assets to be stored in the SST area */
|
||||
#define SST_NUM_ASSETS (10)
|
||||
|
||||
/* Internal Trusted Storage (ITS) Service definitions
|
||||
* Note: Further documentation of these definitions can be found in the
|
||||
* TF-M ITS Integration Guide. The ITS should be in the internal flash, but is
|
||||
* allocated in the external flash just for development platforms that don't
|
||||
* have internal flash available.
|
||||
*/
|
||||
#define ITS_FLASH_DEV_NAME Driver_FLASH0
|
||||
|
||||
/* In this target the CMSIS driver requires only the offset from the base
|
||||
* address instead of the full memory address.
|
||||
*/
|
||||
#define ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET
|
||||
/* Dedicated flash area for ITS */
|
||||
#define ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE
|
||||
#define ITS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
|
||||
/* Number of ITS_SECTOR_SIZE per block */
|
||||
#define ITS_SECTORS_PER_BLOCK (0x1)
|
||||
/* Specifies the smallest flash programmable unit in bytes */
|
||||
#define ITS_FLASH_PROGRAM_UNIT (0x1)
|
||||
/* The maximum asset size to be stored in the ITS area */
|
||||
#define ITS_MAX_ASSET_SIZE (512)
|
||||
/* The maximum number of assets to be stored in the ITS area */
|
||||
#define ITS_NUM_ASSETS (10)
|
||||
|
||||
/* NV Counters definitions */
|
||||
#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
|
||||
#define TFM_NV_COUNTERS_AREA_SIZE FLASH_NV_COUNTERS_AREA_SIZE
|
||||
#define TFM_NV_COUNTERS_AREA_SIZE (0x18) /* 24 Bytes */
|
||||
#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
|
||||
#define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
|
||||
|
||||
/* Use QSPI Flash memory to store Code data */
|
||||
#define S_ROM_ALIAS_BASE (0x10200000)
|
||||
#define NS_ROM_ALIAS_BASE (0x00200000)
|
||||
|
||||
/* FIXME: Use SRAM2 memory to store RW data */
|
||||
#define S_RAM_ALIAS_BASE (0x30000000)
|
||||
#define NS_RAM_ALIAS_BASE (0x20000000)
|
||||
|
||||
/* Shared data area between bootloader and runtime firmware.
|
||||
* Shared data area is allocated at the beginning of the RAM, it is overlapping
|
||||
* with TF-M Secure code's MSP stack
|
||||
*/
|
||||
#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE
|
||||
#define BOOT_TFM_SHARED_DATA_SIZE 0x400
|
||||
#define TOTAL_ROM_SIZE (0x200000) /* 2 MB */
|
||||
#define TOTAL_RAM_SIZE (0x20000) /* 128 KB */
|
||||
|
||||
#endif /* __FLASH_LAYOUT_H__ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Arm Limited
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
enum image_attributes {
|
||||
RE_SECURE_IMAGE_OFFSET = (0x0),
|
||||
RE_SECURE_IMAGE_MAX_SIZE = (0x80000),
|
||||
RE_NON_SECURE_IMAGE_OFFSET = ((0x0) + (0x80000)),
|
||||
RE_NON_SECURE_IMAGE_MAX_SIZE = (0x80000),
|
||||
RE_IMAGE_LOAD_ADDRESS = ((0x10000000) + (0x20000)),
|
||||
RE_SIGN_BIN_SIZE = ((0x80000) + (0x80000)),
|
||||
};
|
||||
|
|
@ -21,30 +21,31 @@
|
|||
|
||||
#include "flash_layout.h"
|
||||
|
||||
#define TOTAL_ROM_SIZE (0x00200000) /* 2 MB */
|
||||
#define TOTAL_RAM_SIZE (0x00020000) /* 128KB */
|
||||
|
||||
#define BL2_HEAP_SIZE 0x0001000
|
||||
#define BL2_MSP_STACK_SIZE 0x0001000
|
||||
#define BL2_HEAP_SIZE (0x0001000)
|
||||
#define BL2_MSP_STACK_SIZE (0x0001800)
|
||||
|
||||
#define S_HEAP_SIZE 0x0004000
|
||||
#define S_MSP_STACK_SIZE_INIT 0x0000400
|
||||
#define S_MSP_STACK_SIZE 0x0000800
|
||||
#define S_PSP_STACK_SIZE 0x0000800
|
||||
#define S_HEAP_SIZE (0x0001000)
|
||||
#define S_MSP_STACK_SIZE_INIT (0x0000400)
|
||||
#define S_MSP_STACK_SIZE (0x0000800)
|
||||
#define S_PSP_STACK_SIZE (0x0000800)
|
||||
|
||||
#define NS_HEAP_SIZE 0x0001000
|
||||
#define NS_MSP_STACK_SIZE 0x0000400
|
||||
#define NS_PSP_STACK_SIZE 0x0000C00
|
||||
#define NS_HEAP_SIZE (0x0001000)
|
||||
#define NS_MSP_STACK_SIZE (0x0000400)
|
||||
#define NS_PSP_STACK_SIZE (0x0000C00)
|
||||
|
||||
/*
|
||||
* MPC granularity is 128 KB on Musca. Alignment
|
||||
/* This size of buffer is big enough to store an attestation
|
||||
* token produced by initial attestation service
|
||||
*/
|
||||
#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE (0x250)
|
||||
/* MPC granularity is 128 KB on Musca_A. Alignment
|
||||
* of partitions is defined in accordance with this constraint.
|
||||
*/
|
||||
#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_IMAGE_0_OFFSET)
|
||||
#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_IMAGE_1_OFFSET)
|
||||
#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET)
|
||||
#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET)
|
||||
|
||||
#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + \
|
||||
FLASH_PARTITION_SIZE)
|
||||
#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \
|
||||
+ FLASH_S_PARTITION_SIZE)
|
||||
|
||||
/*
|
||||
* Boot partition structure if MCUBoot is used:
|
||||
|
|
@ -59,48 +60,40 @@
|
|||
#define BL2_HEADER_SIZE (0x400)
|
||||
#define BL2_TRAILER_SIZE (0x400)
|
||||
|
||||
#define IMAGE_CODE_SIZE \
|
||||
(FLASH_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
|
||||
|
||||
#define CMSE_VENEER_REGION_SIZE (0x000001C0)
|
||||
#define IMAGE_S_CODE_SIZE \
|
||||
(FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
|
||||
|
||||
#define IMAGE_NS_CODE_SIZE \
|
||||
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
|
||||
/*
|
||||
* Since we enable/disable flash during s/ns code copy to code sram we cannot
|
||||
* access bl2 code from flash, hence we need to copy the bl2 code to code sram
|
||||
*/
|
||||
#define BL2_CODE_SRAM_ALIAS_BASE (S_SRAM_ALIAS_BASE)
|
||||
#define BL2_CODE_SRAM_ALIAS(x) (BL2_CODE_SRAM_ALIAS_BASE + x)
|
||||
#define BL2_CODE_SRAM_BASE (BL2_CODE_SRAM_ALIAS(FLASH_AREA_BL2_OFFSET))
|
||||
|
||||
/* Use QSPI Flash memory to store Code data */
|
||||
#define S_ROM_ALIAS_BASE (0x10200000)
|
||||
#define NS_ROM_ALIAS_BASE (0x00200000)
|
||||
#define CMSE_VENEER_REGION_SIZE (0x300)
|
||||
|
||||
#define S_RAM_ALIAS_BASE (0x30000000)
|
||||
#define NS_RAM_ALIAS_BASE (0x20000000)
|
||||
|
||||
/* Alias definitions for secure and non-secure areas*/
|
||||
#define S_ROM_ALIAS(x) (S_SRAM_ALIAS_BASE + x)
|
||||
#define NS_ROM_ALIAS(x) (NS_SRAM_ALIAS_BASE + x)
|
||||
#define S_ROM_ALIAS(x) (S_SRAM_ALIAS_BASE + (x))
|
||||
#define NS_ROM_ALIAS(x) (NS_SRAM_ALIAS_BASE + (x))
|
||||
|
||||
#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + x)
|
||||
#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + x)
|
||||
#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x))
|
||||
#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x))
|
||||
|
||||
/* Secure regions */
|
||||
#define S_IMAGE_PRIMARY_AREA_OFFSET \
|
||||
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
|
||||
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
|
||||
#define S_CODE_SIZE (IMAGE_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
|
||||
#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
|
||||
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
|
||||
|
||||
#define S_DATA_START (S_RAM_ALIAS(0x0))
|
||||
|
||||
#if defined(TEST_FRAMEWORK_S) || defined(TEST_FRAMEWORK_NS)
|
||||
/* Increase secure DATA area to run the regression tests on Musca A1 */
|
||||
/* Reserve 96 KB of RAM to the SPE to meet worst case scenario
|
||||
* requirements which are encountered in IPC mode and regression
|
||||
* tests enabled. Leave the remaining 32 KB to the NSPE.
|
||||
*/
|
||||
#define S_DATA_SIZE ((TOTAL_RAM_SIZE / 4) * 3)
|
||||
#else
|
||||
#define S_DATA_SIZE ((TOTAL_RAM_SIZE / 2) + 0x1000)
|
||||
#endif
|
||||
|
||||
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
|
||||
|
||||
|
|
@ -111,7 +104,7 @@
|
|||
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
|
||||
(NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
|
||||
#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
|
||||
#define NS_CODE_SIZE (IMAGE_CODE_SIZE - FLASH_AREA_BL2_SIZE)
|
||||
#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE - FLASH_AREA_BL2_SIZE)
|
||||
#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
|
||||
|
||||
#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE))
|
||||
|
|
@ -123,13 +116,14 @@
|
|||
#define NS_PARTITION_START \
|
||||
(NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
|
||||
|
||||
#define NS_PARTITION_SIZE (FLASH_PARTITION_SIZE)
|
||||
#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
|
||||
|
||||
/* Secondary partition for new images in case of firmware upgrade */
|
||||
#define SECONDARY_PARTITION_START \
|
||||
(NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET))
|
||||
|
||||
#define SECONDARY_PARTITION_SIZE (FLASH_AREA_IMAGE_1_SIZE)
|
||||
#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \
|
||||
FLASH_NS_PARTITION_SIZE)
|
||||
|
||||
/* Code SRAM area */
|
||||
#define TOTAL_CODE_SRAM_SIZE (TOTAL_ROM_SIZE)
|
||||
|
|
@ -145,6 +139,12 @@
|
|||
#define NS_CODE_SRAM_EXEC_LIMIT (NS_CODE_SRAM_EXEC_BASE + \
|
||||
(TOTAL_CODE_SRAM_SIZE / 2) - 1)
|
||||
|
||||
/* Since we enable/disable flash during s/ns code copy to code sram we cannot
|
||||
* access bl2 code from flash, hence we need to copy the bl2 code to code sram
|
||||
*/
|
||||
#define BL2_CODE_SRAM_ALIAS_BASE (S_SRAM_ALIAS_BASE)
|
||||
#define BL2_CODE_SRAM_ALIAS(x) (BL2_CODE_SRAM_ALIAS_BASE + x)
|
||||
#define BL2_CODE_SRAM_BASE (BL2_CODE_SRAM_ALIAS(FLASH_AREA_BL2_OFFSET))
|
||||
/* Bootloader regions */
|
||||
#define BL2_CODE_START (S_QSPI_ALIAS_BASE)
|
||||
#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE)
|
||||
|
|
@ -154,4 +154,12 @@
|
|||
#define BL2_DATA_SIZE (TOTAL_RAM_SIZE)
|
||||
#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1)
|
||||
|
||||
/* Shared data area between bootloader and runtime firmware.
|
||||
* Shared data area is allocated at the beginning of the RAM, it is overlapping
|
||||
* with TF-M Secure code's MSP stack
|
||||
*/
|
||||
#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE
|
||||
#define BOOT_TFM_SHARED_DATA_SIZE (0x400)
|
||||
#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \
|
||||
BOOT_TFM_SHARED_DATA_SIZE - 1)
|
||||
#endif /* __REGION_DEFS_H__ */
|
||||
|
|
|
|||
|
|
@ -27,8 +27,8 @@ import os
|
|||
import shutil
|
||||
from . import macro_parser
|
||||
|
||||
offset_re = re.compile(r"^#define ([0-9A-Z_]+)_IMAGE_OFFSET\s+((0x)?[0-9a-fA-F]+)")
|
||||
size_re = re.compile(r"^#define ([0-9A-Z_]+)_IMAGE_MAX_SIZE\s+((0x)?[0-9a-fA-F]+)")
|
||||
offset_re = re.compile(r"^\s*RE_([0-9A-Z_]+)_IMAGE_OFFSET\s*=\s*(.*)")
|
||||
size_re = re.compile(r"^\s*RE_([0-9A-Z_]+)_IMAGE_MAX_SIZE\s*=\s*(.*)")
|
||||
|
||||
class Assembly():
|
||||
def __init__(self, layout_path, output):
|
||||
|
|
|
|||
|
|
@ -40,20 +40,21 @@ def musca_tfm_bin(t_self, non_secure_bin, secure_bin):
|
|||
os.makedirs(tempdir)
|
||||
flash_layout = path_join(MUSCA_A1_BASE, 'partition', 'flash_layout.h')
|
||||
mcuboot_bin = path_join(MUSCA_A1_BASE, 'prebuilt', 'mcuboot.bin')
|
||||
image_macros = path_join(MUSCA_A1_BASE, 'partition', 'image_macros_preprocessed.c')
|
||||
ns_bin_name, ns_bin_ext = splitext(basename(non_secure_bin))
|
||||
concatenated_bin = path_join(tempdir, 'tfm_' + ns_bin_name + ns_bin_ext)
|
||||
signed_bin = path_join(tempdir, 'tfm_' + ns_bin_name + '_signed' + ns_bin_ext)
|
||||
|
||||
assert os.path.isfile(flash_layout)
|
||||
assert os.path.isfile(image_macros)
|
||||
|
||||
#1. Concatenate secure TFM and non-secure mbed binaries
|
||||
output = Assembly(flash_layout, concatenated_bin)
|
||||
output = Assembly(image_macros, concatenated_bin)
|
||||
output.add_image(secure_bin, "SECURE")
|
||||
output.add_image(non_secure_bin, "NON_SECURE")
|
||||
|
||||
#2. Run imgtool to sign the concatenated binary
|
||||
sign_args = Namespace(
|
||||
layout=flash_layout,
|
||||
layout=image_macros,
|
||||
key=path_join(SCRIPT_DIR, 'musca_a1-root-rsa-3072.pem'),
|
||||
public_key_format=None,
|
||||
align=1,
|
||||
|
|
|
|||
Loading…
Reference in New Issue