diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h
index c08e2cef5a..17f5400299 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h
@@ -110,6 +110,10 @@ typedef enum {
     DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0)
 } DMAName;
 
+typedef enum {
+    CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0)
+} CANName;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c
index 7b58a28abe..1992ecf876 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c
@@ -359,3 +359,19 @@ const PinMap PinMap_SPI_SSEL[] = {
     
     {NC,    NC,    0}
 };
+
+const PinMap PinMap_CAN_TD[] = {
+    {PC_0, CAN_0, SYS_GPC_MFPL_PC0MFP_CAN0_TXD},
+    {PA_1, CAN_0, SYS_GPA_MFPL_PA1MFP_CAN0_TXD},
+    {PA_12, CAN_0, SYS_GPA_MFPH_PA12MFP_CAN0_TXD},
+	
+    {NC,    NC,     0}
+};
+    
+const PinMap PinMap_CAN_RD[] = { 
+    {PC_1, CAN_0, SYS_GPC_MFPL_PC1MFP_CAN0_RXD},
+    {PA_0, CAN_0, SYS_GPA_MFPL_PA0MFP_CAN0_RXD},
+    {PA_13, CAN_0, SYS_GPA_MFPH_PA13MFP_CAN0_RXD},
+	
+    {NC,    NC,    0}
+};
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h
index 6c9a26b865..1f2eb94dee 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h
@@ -65,6 +65,11 @@ extern const PinMap PinMap_SD_DAT1[];
 extern const PinMap PinMap_SD_DAT2[];
 extern const PinMap PinMap_SD_DAT3[];
 
+//*** CAN ***
+
+extern PinMap const PinMap_CAN_TD[];
+extern PinMap const PinMap_CAN_RD[];
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/device.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/device.h
index 89e12ecd41..d87271b1fb 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/device.h
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/device.h
@@ -38,8 +38,6 @@
 #define DEVICE_SPI_ASYNCH       1
 #define DEVICE_SPISLAVE         1
 
-#define DEVICE_CAN              0
-
 #define DEVICE_RTC              1
 
 #define DEVICE_ETHERNET         0
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h
index e06ff861eb..eee0c0bf77 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h
@@ -123,6 +123,10 @@ struct sleep_s {
     int powerdown;
 };
 
+struct can_s {
+    CANName can;
+    char index; 
+};
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/can_api.c b/targets/TARGET_NUVOTON/TARGET_M451/can_api.c
new file mode 100644
index 0000000000..c0c6daad21
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_M451/can_api.c
@@ -0,0 +1,303 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+ #include "can_api.h"
+ #include "m451_gpio.h"
+ #include "m451_can.h"
+ 
+ #if DEVICE_CAN
+ #include <string.h>
+ #include "cmsis.h"
+ #include "pinmap.h"
+ #include "PeripheralPins.h"
+ #include "nu_modutil.h"
+ #include "nu_miscutil.h"
+ #include "nu_bitutil.h"
+ #include "critical.h"
+ 
+ #define NU_CAN_DEBUG    0
+ #define CAN_NUM         1
+ 
+ static uint32_t can_irq_ids[CAN_NUM] = {0};
+ static can_irq_handler can0_irq_handler;
+
+ 
+ static const struct nu_modinit_s can_modinit_tab[] = {
+    {CAN_0, CAN0_MODULE, 0, 0, CAN0_RST, CAN0_IRQn, NULL},
+    
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+ 
+ void can_init(can_t *obj, PinName rd, PinName td)
+ {
+    uint32_t can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+    uint32_t can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+    obj->can = (CANName)pinmap_merge(can_td, can_rd);
+    MBED_ASSERT((int)obj->can != NC);
+    
+    const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->can);
+    
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+    
+    // Enable IP clock
+    CLK_EnableModuleClock(modinit->clkidx);
+     
+    obj->index = 0;
+    
+    pinmap_pinout(td, PinMap_CAN_TD);
+    pinmap_pinout(rd, PinMap_CAN_RD);
+    
+    /* For M453 mbed Board Transmitter Setting (RS Pin) */
+    GPIO_SetMode(PA, BIT0| BIT1, GPIO_MODE_OUTPUT);    
+    PA0 = 0x00;
+    PA1 = 0x00;   
+
+    CAN_Open((CAN_T *)obj->can, 500000, CAN_NORMAL_MODE);
+    
+    can_filter(obj, 0, 0, CANStandard, 0);
+ }
+ 
+ 
+void can_free(can_t *obj)
+{
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
+    
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->can);
+    
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+    
+    CLK_DisableModuleClock(modinit->clkidx);
+}
+
+int can_frequency(can_t *obj, int hz)
+{
+    CAN_SetBaudRate((CAN_T *)obj->can, hz);
+    
+    return CAN_GetCANBitRate((CAN_T *)obj->can);
+}
+
+static void can_irq(CANName name, int id) 
+{
+    
+    CAN_T *can = (CAN_T *)NU_MODBASE(name);
+    uint32_t u8IIDRstatus;
+
+    u8IIDRstatus = can->IIDR;
+
+    if(u8IIDRstatus == 0x00008000) {      /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+        /**************************/
+        /* Status Change interrupt*/
+        /**************************/
+        if(can->STATUS & CAN_STATUS_RXOK_Msk) {
+            can->STATUS &= ~CAN_STATUS_RXOK_Msk;   /* Clear Rx Ok status*/
+            can0_irq_handler(can_irq_ids[id], IRQ_RX);
+        }
+
+        if(can->STATUS & CAN_STATUS_TXOK_Msk) {
+            can->STATUS &= ~CAN_STATUS_TXOK_Msk;    /* Clear Tx Ok status*/
+            can0_irq_handler(can_irq_ids[id], IRQ_TX);
+        }
+
+        /**************************/
+        /* Error Status interrupt */
+        /**************************/
+        if(can->STATUS & CAN_STATUS_EWARN_Msk) {
+            can0_irq_handler(can_irq_ids[id], IRQ_ERROR);
+        }
+
+        if(can->STATUS & CAN_STATUS_BOFF_Msk) {
+            can0_irq_handler(can_irq_ids[id], IRQ_BUS);
+        }
+    } else if (u8IIDRstatus!=0) {
+
+        can0_irq_handler(can_irq_ids[id], IRQ_OVERRUN);
+        
+        CAN_CLR_INT_PENDING_BIT(can, ((can->IIDR) -1));      /* Clear Interrupt Pending */
+
+    } else if(can->WU_STATUS == 1) {
+
+        can->WU_STATUS = 0;                       /* Write '0' to clear */
+        can0_irq_handler(can_irq_ids[id], IRQ_WAKEUP);
+    }
+}
+
+void CAN0_IRQHandler(void)
+{
+    can_irq(CAN_0, 0);
+}
+
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
+{
+    can0_irq_handler = handler;
+    can_irq_ids[obj->index] = id; 
+}
+
+void can_irq_free(can_t *obj)
+{
+    CAN_DisableInt((CAN_T *)obj->can, (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk));
+    
+    can_irq_ids[obj->index] = 0;
+    
+    NVIC_DisableIRQ(CAN0_IRQn);    
+}
+
+void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
+{
+    
+    CAN_EnterInitMode((CAN_T*)obj->can, ((enable != 0 )? CAN_CON_IE_Msk :0) );
+    
+    
+    switch (irq)
+    {
+        case IRQ_ERROR:
+        case IRQ_BUS:
+        case IRQ_PASSIVE:
+            ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_EIE_Msk;
+            ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
+            break;
+        
+        case IRQ_RX:
+        case IRQ_TX:
+        case IRQ_OVERRUN:
+        case IRQ_WAKEUP:
+            ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
+            break;
+        
+        default:
+            break;
+    
+    }
+
+    CAN_LeaveInitMode((CAN_T*)obj->can);
+    
+    NVIC_SetVector(CAN0_IRQn, (uint32_t)&CAN0_IRQHandler);
+    NVIC_EnableIRQ(CAN0_IRQn);
+    
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc)
+{
+    STR_CANMSG_T CMsg;
+    
+    CMsg.IdType = (uint32_t)msg.format;
+    CMsg.FrameType = (uint32_t)!msg.type;
+    CMsg.Id = msg.id;
+    CMsg.DLC = msg.len;
+    memcpy((void *)&CMsg.Data[0],(const void *)&msg.data[0], (unsigned int)8);
+
+    return CAN_Transmit((CAN_T *)(obj->can), cc, &CMsg);
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle)
+{
+    STR_CANMSG_T CMsg;
+
+    if(!CAN_Receive((CAN_T *)(obj->can), handle, &CMsg))
+    return 0;
+        
+    msg->format = (CANFormat)CMsg.IdType;
+    msg->type = (CANType)!CMsg.FrameType;
+    msg->id = CMsg.Id;
+    msg->len = CMsg.DLC;
+    memcpy(&msg->data[0], &CMsg.Data[0], 8);
+    
+    return 1;
+}
+
+int can_mode(can_t *obj, CanMode mode)
+{
+    int success = 0;
+    switch (mode)
+    {
+        case MODE_RESET:
+            CAN_LeaveTestMode((CAN_T*)obj->can);
+            success = 1;
+            break;
+        
+        case MODE_NORMAL:
+            CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_BASIC_Msk);
+            success = 1;
+            break;
+        
+        case MODE_SILENT:
+            CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk);
+            success = 1;
+            break;
+        
+        case MODE_TEST_LOCAL:
+        case MODE_TEST_GLOBAL:
+            CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_LBACK_Msk);
+            success = 1;
+            break;
+        
+        case MODE_TEST_SILENT:
+            CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
+            success = 1;
+            break;
+        
+        default:
+            success = 0;
+            break;
+        
+    }
+    
+    
+    return success;
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
+{
+    return CAN_SetRxMsg((CAN_T *)(obj->can), handle , (uint32_t)format, id);
+}
+
+
+void can_reset(can_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
+    
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->can);
+    
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+    
+}
+
+unsigned char can_rderror(can_t *obj)
+{
+    CAN_T *can = (CAN_T *)(obj->can); 
+    return ((can->ERR>>8)&0xFF);
+}
+
+unsigned char can_tderror(can_t *obj)
+{
+    CAN_T *can = (CAN_T *)(obj->can);
+    return ((can->ERR)&0xFF);
+}
+
+void can_monitor(can_t *obj, int silent)
+{
+    CAN_EnterTestMode((CAN_T *)(obj->can), CAN_TEST_SILENT_Msk);
+}
+ 
+#endif // DEVICE_CAN
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.h b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.h
index 7f661c3bb0..d2427af227 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.h
+++ b/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.h
@@ -158,7 +158,11 @@ int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint3
 int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
 int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
 int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum);
-
+uint32_t CAN_GetCANBitRate(CAN_T  *tCAN);
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);
+void CAN_LeaveInitMode(CAN_T *tCAN);
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
+void CAN_LeaveTestMode(CAN_T *tCAN);
 
 /*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
 
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h
index 2cdc0bbc45..66621e43b0 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h
@@ -116,10 +116,15 @@ typedef enum {
 } DMAName;
 
 typedef enum {
-    SD_0 = (int) NU_MODNAME(SD_BASE, 0),
-    SD_1 = (int) NU_MODNAME(SD_BASE, 1)
+    SD_0_0 = (int) NU_MODNAME(SD_BASE, 0),
+    SD_0_1 = (int) NU_MODNAME(SD_BASE, 1)
 } SDName;
 
+typedef enum {
+    CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0),
+    CAN_1 = (int) NU_MODNAME(CAN1_BASE, 0)
+} CANName;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.c
index 4ab4693a68..a609071396 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.c
@@ -451,62 +451,81 @@ const PinMap PinMap_SPI_SSEL[] = {
 //*** SD ***
 
 const PinMap PinMap_SD_CD[] = {
-    {PC_12, SD_1, SYS_GPC_MFPH_PC12MFP_SD1_CDn},
-    {PD_3, SD_0, SYS_GPD_MFPL_PD3MFP_SD0_CDn},
-    {PE_5, SD_0, SYS_GPE_MFPL_PE5MFP_SD0_CDn},
-    {PF_6, SD_0, SYS_GPF_MFPL_PF6MFP_SD0_CDn},
+    {PC_12, SD_0_1, SYS_GPC_MFPH_PC12MFP_SD1_CDn},
+    {PD_3, SD_0_0, SYS_GPD_MFPL_PD3MFP_SD0_CDn},
+    {PE_5, SD_0_0, SYS_GPE_MFPL_PE5MFP_SD0_CDn},
+    {PF_6, SD_0_0, SYS_GPF_MFPL_PF6MFP_SD0_CDn},
     
     {NC,    NC,    0}
 };
 
 const PinMap PinMap_SD_CMD[] = {
-    {PC_13, SD_1, SYS_GPC_MFPH_PC13MFP_SD1_CMD},
-    {PD_6, SD_0, SYS_GPD_MFPL_PD6MFP_SD0_CMD},
-    {PE_6, SD_0, SYS_GPE_MFPL_PE6MFP_SD0_CMD},
-    {PF_7, SD_0, SYS_GPF_MFPL_PF7MFP_SD0_CMD},
+    {PC_13, SD_0_1, SYS_GPC_MFPH_PC13MFP_SD1_CMD},
+    {PD_6, SD_0_0, SYS_GPD_MFPL_PD6MFP_SD0_CMD},
+    {PE_6, SD_0_0, SYS_GPE_MFPL_PE6MFP_SD0_CMD},
+    {PF_7, SD_0_0, SYS_GPF_MFPL_PF7MFP_SD0_CMD},
     
     {NC,    NC,    0}
 };
 
 const PinMap PinMap_SD_CLK[] = {
-    {PC_14, SD_1, SYS_GPC_MFPH_PC14MFP_SD1_CLK},
-    {PD_7, SD_0, SYS_GPD_MFPL_PD7MFP_SD0_CLK},
-    {PE_7, SD_0, SYS_GPE_MFPL_PE7MFP_SD0_CLK},
-    {PF_8, SD_0, SYS_GPF_MFPH_PF8MFP_SD0_CLK},
+    {PC_14, SD_0_1, SYS_GPC_MFPH_PC14MFP_SD1_CLK},
+    {PD_7, SD_0_0, SYS_GPD_MFPL_PD7MFP_SD0_CLK},
+    {PE_7, SD_0_0, SYS_GPE_MFPL_PE7MFP_SD0_CLK},
+    {PF_8, SD_0_0, SYS_GPF_MFPH_PF8MFP_SD0_CLK},
     
     {NC,    NC,    0}
 };
 
 const PinMap PinMap_SD_DAT0[] = {
-    {PC_9, SD_1, SYS_GPC_MFPH_PC9MFP_SD1_DAT0},
-    {PD_2, SD_1, SYS_GPD_MFPL_PD2MFP_SD1_DAT0},
-    {PE_11, SD_0, SYS_GPE_MFPH_PE11MFP_SD0_DAT0},
-    {PF_5, SD_0, SYS_GPF_MFPL_PF5MFP_SD0_DAT0},
+    {PC_9, SD_0_1, SYS_GPC_MFPH_PC9MFP_SD1_DAT0},
+    {PD_2, SD_0_1, SYS_GPD_MFPL_PD2MFP_SD1_DAT0},
+    {PE_11, SD_0_0, SYS_GPE_MFPH_PE11MFP_SD0_DAT0},
+    {PF_5, SD_0_0, SYS_GPF_MFPL_PF5MFP_SD0_DAT0},
     
     {NC,    NC,    0}
 };
 
 const PinMap PinMap_SD_DAT1[] = {
-    {PD_1, SD_1, SYS_GPD_MFPL_PD1MFP_SD1_DAT1},
-    {PE_10, SD_0, SYS_GPE_MFPH_PE10MFP_SD0_DAT1},
-    {PF_4, SD_0, SYS_GPF_MFPL_PF4MFP_SD0_DAT1},
+    {PD_1, SD_0_1, SYS_GPD_MFPL_PD1MFP_SD1_DAT1},
+    {PE_10, SD_0_0, SYS_GPE_MFPH_PE10MFP_SD0_DAT1},
+    {PF_4, SD_0_0, SYS_GPF_MFPL_PF4MFP_SD0_DAT1},
     
     
     {NC,    NC,    0}
 };
 
 const PinMap PinMap_SD_DAT2[] = {
-    {PD_0, SD_1, SYS_GPD_MFPL_PD0MFP_SD1_DAT2},
-    {PE_9, SD_0, SYS_GPE_MFPH_PE9MFP_SD0_DAT2},
-    {PF_3, SD_0, SYS_GPF_MFPL_PF3MFP_SD0_DAT2},
+    {PD_0, SD_0_1, SYS_GPD_MFPL_PD0MFP_SD1_DAT2},
+    {PE_9, SD_0_0, SYS_GPE_MFPH_PE9MFP_SD0_DAT2},
+    {PF_3, SD_0_0, SYS_GPF_MFPL_PF3MFP_SD0_DAT2},
 
     {NC,    NC,    0}
 };
 
 const PinMap PinMap_SD_DAT3[] = {
-    {PC_15, SD_1, SYS_GPC_MFPH_PC15MFP_SD1_DAT3},
-    {PE_8, SD_0, SYS_GPE_MFPH_PE8MFP_SD0_DAT3},
-    {PF_2, SD_0, SYS_GPF_MFPL_PF2MFP_SD0_DAT3},
+    {PC_15, SD_0_1, SYS_GPC_MFPH_PC15MFP_SD1_DAT3},
+    {PE_8, SD_0_0, SYS_GPE_MFPH_PE8MFP_SD0_DAT3},
+    {PF_2, SD_0_0, SYS_GPF_MFPL_PF2MFP_SD0_DAT3},
 
     {NC,    NC,    0}
 };
+
+const PinMap PinMap_CAN_TD[] = {
+    {PB_13, CAN_0, SYS_GPB_MFPH_PB13MFP_CAN0_TXD},
+    {PA_1, CAN_1, SYS_GPA_MFPL_PA1MFP_CAN1_TXD},
+    {PA_6, CAN_1, SYS_GPA_MFPL_PA6MFP_CAN1_TXD},
+    {PH_1, CAN_1, SYS_GPH_MFPL_PH1MFP_CAN1_TXD},
+        
+    {NC,    NC,     0}
+};
+
+
+const PinMap PinMap_CAN_RD[] = {
+    {PB_12, CAN_0, SYS_GPB_MFPH_PB12MFP_CAN0_RXD},
+    {PA_0, CAN_1, SYS_GPA_MFPL_PA0MFP_CAN1_RXD},
+    {PH_0, CAN_1, SYS_GPH_MFPL_PH0MFP_CAN1_RXD},
+        
+    {NC,    NC,    0}
+};
+
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.h
index 104d38ee4f..53bde3dc39 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.h
@@ -64,6 +64,10 @@ extern const PinMap PinMap_SD_DAT1[];
 extern const PinMap PinMap_SD_DAT2[];
 extern const PinMap PinMap_SD_DAT3[];
 
+//*** CAN ***
+extern const PinMap PinMap_CAN_TD[];
+extern const PinMap PinMap_CAN_RD[];
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/device.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/device.h
index 89e12ecd41..530a7a41e9 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/device.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/device.h
@@ -38,7 +38,6 @@
 #define DEVICE_SPI_ASYNCH       1
 #define DEVICE_SPISLAVE         1
 
-#define DEVICE_CAN              0
 
 #define DEVICE_RTC              1
 
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h
index dcc39b0d68..59f3d654ca 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h
@@ -128,6 +128,10 @@ struct trng_s {
     uint8_t dummy;
 };
 
+struct can_s {
+	CANName can;
+	char index; 
+};
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c
new file mode 100644
index 0000000000..dd410b7e41
--- /dev/null
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c
@@ -0,0 +1,351 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015-2016 Nuvoton
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+ #include "can_api.h"
+ #include "nuc472_gpio.h"
+ #include "nuc472_can.h"
+ 
+ #if DEVICE_CAN
+ #include <string.h>
+ #include "cmsis.h"
+ #include "pinmap.h"
+ #include "PeripheralPins.h"
+ #include "nu_modutil.h"
+ #include "nu_miscutil.h"
+ #include "nu_bitutil.h"
+ #include "critical.h"
+ 
+ #define NU_CAN_DEBUG    0
+ #define CAN_NUM         2
+ 
+ static uint32_t can_irq_ids[CAN_NUM] = {0};
+ static can_irq_handler can0_irq_handler;
+ static can_irq_handler can1_irq_handler;
+
+ 
+ static const struct nu_modinit_s can_modinit_tab[] = {
+    {CAN_0, CAN0_MODULE, 0, 0, CAN0_RST, CAN0_IRQn, NULL},
+    {CAN_1, CAN1_MODULE, 0, 0, CAN1_RST, CAN1_IRQn, NULL},
+    
+    {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
+};
+
+ 
+ void can_init(can_t *obj, PinName rd, PinName td)
+ {
+    uint32_t can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+    uint32_t can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+    obj->can = (CANName)pinmap_merge(can_td, can_rd);
+    MBED_ASSERT((int)obj->can != NC);
+    
+    const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->can);
+    
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+    
+    // Enable IP clock
+    CLK_EnableModuleClock(modinit->clkidx);
+     
+    if(obj->can == CAN_1) {
+        obj->index = 1;
+    }
+    else
+        obj->index = 0;
+    
+    pinmap_pinout(td, PinMap_CAN_TD);
+    pinmap_pinout(rd, PinMap_CAN_RD);
+    
+    /* For NCU 472 mbed Board Transmitter Setting (RS Pin) */
+    GPIO_SetMode(PA, BIT2| BIT3, GPIO_MODE_OUTPUT);    
+    PA2 = 0x00;
+    PA3 = 0x00; 
+
+    CAN_Open((CAN_T *)obj->can, 500000, CAN_NORMAL_MODE);
+    
+    can_filter(obj, 0, 0, CANStandard, 0);
+ }
+ 
+ 
+void can_free(can_t *obj)
+{
+
+    const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
+    
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->can);
+    
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+    
+    CLK_DisableModuleClock(modinit->clkidx);
+}
+
+int can_frequency(can_t *obj, int hz)
+{
+    CAN_SetBaudRate((CAN_T *)obj->can, hz);
+    
+    return CAN_GetCANBitRate((CAN_T *)obj->can);
+}
+
+static void can_irq(CANName name, int id) 
+{
+    
+    CAN_T *can = (CAN_T *)NU_MODBASE(name);
+    uint32_t u8IIDRstatus;
+
+    u8IIDRstatus = can->IIDR;
+
+    if(u8IIDRstatus == 0x00008000) {      /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+        /**************************/
+        /* Status Change interrupt*/
+        /**************************/
+        if(can->STATUS & CAN_STATUS_RXOK_Msk) {
+            can->STATUS &= ~CAN_STATUS_RXOK_Msk;   /* Clear Rx Ok status*/
+            if(id)
+                can1_irq_handler(can_irq_ids[id] , IRQ_RX);
+            else
+                can0_irq_handler(can_irq_ids[id], IRQ_RX);
+        }
+
+        if(can->STATUS & CAN_STATUS_TXOK_Msk) {
+            can->STATUS &= ~CAN_STATUS_TXOK_Msk;    /* Clear Tx Ok status*/
+            if(id)
+                can1_irq_handler(can_irq_ids[id] , IRQ_TX);
+            else
+                can0_irq_handler(can_irq_ids[id], IRQ_TX);
+
+        }
+
+        /**************************/
+        /* Error Status interrupt */
+        /**************************/
+        if(can->STATUS & CAN_STATUS_EWARN_Msk) {
+            if(id)
+                can1_irq_handler(can_irq_ids[id] , IRQ_ERROR);
+            else
+                can0_irq_handler(can_irq_ids[id], IRQ_ERROR);
+        }
+
+        if(can->STATUS & CAN_STATUS_BOFF_Msk) {
+            if(id)
+                can1_irq_handler(can_irq_ids[id] , IRQ_BUS);
+            else
+                can0_irq_handler(can_irq_ids[id], IRQ_BUS);
+        }
+    } else if (u8IIDRstatus!=0) {
+
+        if(id)
+            can1_irq_handler(can_irq_ids[id] , IRQ_OVERRUN);
+        else
+            can0_irq_handler(can_irq_ids[id], IRQ_OVERRUN);
+        
+        CAN_CLR_INT_PENDING_BIT(can, ((can->IIDR) -1));      /* Clear Interrupt Pending */
+
+    } else if(can->WU_STATUS == 1) {
+
+        can->WU_STATUS = 0;                       /* Write '0' to clear */
+        if(id)
+            can1_irq_handler(can_irq_ids[id] , IRQ_WAKEUP);
+        else
+            can0_irq_handler(can_irq_ids[id], IRQ_WAKEUP);
+    }
+}
+
+void CAN0_IRQHandler(void)
+{
+    can_irq(CAN_0, 0);
+}
+
+void CAN1_IRQHandler(void)
+{
+    can_irq(CAN_1, 1);
+}
+
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
+{
+    if(obj->index)
+        can1_irq_handler = handler;
+    else
+        can0_irq_handler = handler;
+    can_irq_ids[obj->index] = id; 
+
+}
+
+void can_irq_free(can_t *obj)
+{
+    CAN_DisableInt((CAN_T *)obj->can, (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk));
+    
+    can_irq_ids[obj->index] = 0;
+    
+    if(!obj->index)
+        NVIC_DisableIRQ(CAN0_IRQn);
+    else
+        NVIC_DisableIRQ(CAN1_IRQn);
+    
+    
+}
+
+void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
+{
+    
+    CAN_EnterInitMode((CAN_T*)obj->can);
+    
+    ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON ) | ((enable != 0 )? CAN_CON_IE_Msk :0);
+    
+    switch (irq)
+    {
+        case IRQ_ERROR:
+        case IRQ_BUS:
+        case IRQ_PASSIVE:
+            ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_EIE_Msk;
+            ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
+            break;
+        
+        case IRQ_RX:
+        case IRQ_TX:
+        case IRQ_OVERRUN:
+        case IRQ_WAKEUP:
+            ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
+            break;
+        
+        default:
+            break;
+    
+    }
+
+    CAN_LeaveInitMode((CAN_T*)obj->can);
+    
+    if(!obj->index)
+    {
+        NVIC_SetVector(CAN0_IRQn, (uint32_t)&CAN0_IRQHandler);
+        NVIC_EnableIRQ(CAN0_IRQn);
+    }
+    else
+    {
+        NVIC_SetVector(CAN1_IRQn, (uint32_t)&CAN1_IRQHandler);
+        NVIC_EnableIRQ(CAN1_IRQn);
+    }
+    
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc)
+{
+    STR_CANMSG_T CMsg;
+    
+    CMsg.IdType = (uint32_t)msg.format;
+    CMsg.FrameType = (uint32_t)!msg.type;
+    CMsg.Id = msg.id;
+    CMsg.DLC = msg.len;
+    memcpy((void *)&CMsg.Data[0],(const void *)&msg.data[0], (unsigned int)8);
+
+    return CAN_Transmit((CAN_T *)(obj->can), cc, &CMsg);
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle)
+{
+    STR_CANMSG_T CMsg;
+
+    if(!CAN_Receive((CAN_T *)(obj->can), handle, &CMsg))
+    return 0;
+        
+    msg->format = (CANFormat)CMsg.IdType;
+    msg->type = (CANType)!CMsg.FrameType;
+    msg->id = CMsg.Id;
+    msg->len = CMsg.DLC;
+    memcpy(&msg->data[0], &CMsg.Data[0], 8);
+    
+    return 1;
+}
+
+int can_mode(can_t *obj, CanMode mode)
+{
+    int success = 0;
+    switch (mode)
+    {
+        case MODE_RESET:
+            CAN_LeaveTestMode((CAN_T*)obj->can);
+            success = 1;
+            break;
+        
+        case MODE_NORMAL:
+            CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_BASIC_Msk);
+            success = 1;
+            break;
+        
+        case MODE_SILENT:
+            CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk);
+            success = 1;
+            break;
+        
+        case MODE_TEST_LOCAL:
+        case MODE_TEST_GLOBAL:
+            CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_LBACK_Msk);
+            success = 1;
+            break;
+        
+        case MODE_TEST_SILENT:
+            CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
+            success = 1;
+            break;
+        
+        default:
+            success = 0;
+            break;
+        
+    }
+    
+    
+    return success;
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
+{
+    return CAN_SetRxMsg((CAN_T *)(obj->can), handle , (uint32_t)format, id);
+}
+
+
+void can_reset(can_t *obj)
+{
+    const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
+    
+    MBED_ASSERT(modinit != NULL);
+    MBED_ASSERT(modinit->modname == obj->can);
+    
+    // Reset this module
+    SYS_ResetModule(modinit->rsetidx);
+    
+}
+
+unsigned char can_rderror(can_t *obj)
+{
+    CAN_T *can = (CAN_T *)(obj->can); 
+    return ((can->ERR>>8)&0xFF);
+}
+
+unsigned char can_tderror(can_t *obj)
+{
+    CAN_T *can = (CAN_T *)(obj->can);
+    return ((can->ERR)&0xFF);
+}
+
+void can_monitor(can_t *obj, int silent)
+{
+    CAN_EnterTestMode((CAN_T *)(obj->can), CAN_TEST_SILENT_Msk);
+}
+ 
+#endif // DEVICE_CAN
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.c b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.c
index c779e6ec95..cfdf751a99 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.c
@@ -419,6 +419,7 @@ uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
 
     SystemCoreClockUpdate();
 
+#if 0   // original implementation got 5% inaccuracy.
     u32Value = SystemCoreClock;
 
     if(u32BaudRate * 8 < (u32Value/2)) {
@@ -428,7 +429,26 @@ uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
         u8Tseg1 = 2;
         u8Tseg2 = 1;
     }
+#else
+    u32Value = SystemCoreClock / u32BaudRate;
+    /* Fix for most standard baud rates, include 125K */
 
+    u8Tseg1 = 3;
+    u8Tseg2 = 2;
+    while(1)
+    {
+        if(((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0) | (u8Tseg1 >= 15))
+            break;
+
+        u8Tseg1++;
+
+        if((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0)
+            break;
+
+        if(u8Tseg2 < 7)
+            u8Tseg2++;
+    }
+#endif
     u32Brp  = SystemCoreClock/(u32BaudRate) / (u8Tseg1 + u8Tseg2 + 3) -1;
 
     u32Value = ((uint32_t)u8Tseg2 << CAN_BTIME_TSEG2_Pos) | ((uint32_t)u8Tseg1 << CAN_BTIME_TSEG1_Pos) |
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.h
index 4d48711975..65e63fa747 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.h
@@ -150,6 +150,11 @@ int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount
 int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID);
 int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
 int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum);
+uint32_t CAN_GetCANBitRate(CAN_T  *tCAN);
+void CAN_EnterInitMode(CAN_T *tCAN);
+void CAN_LeaveInitMode(CAN_T *tCAN);
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
+void CAN_LeaveTestMode(CAN_T *tCAN);
 
 /*@}*/ /* end of group NUC472_442_CAN_EXPORTED_FUNCTIONS */
 
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.c b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.c
index 3544caf0d9..df0cd818cb 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.c
@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     PWM.c
  * @version  V1.00
- * $Revision: 22 $
- * $Date: 14/10/02 9:21a $
+ * $Revision: 26 $
+ * $Date: 15/11/18 2:34p $
  * @brief    NUC472/NUC442 PWM driver source file
  *
  * @note
@@ -52,14 +52,14 @@ uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
  * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
  *       existing frequency of other channel.
  */
-uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
-                                 uint32_t u32ChannelNum,
-                                 uint32_t u32Frequency,
-                                 uint32_t u32DutyCycle,
-                                 uint32_t u32Frequency2)
+uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
+                                  uint32_t u32ChannelNum,
+                                  uint32_t u32Frequency,
+                                  uint32_t u32DutyCycle,
+                                  uint32_t u32Frequency2)
 {
     uint32_t i;
-    uint32_t u32PWM_CLock;
+    uint32_t u32PWM_CLock = __HIRC;
     uint8_t  u8Divider = 1, u8Prescale = 0xFF;
     uint16_t u16CNR = 0xFFFF;
 
@@ -100,15 +100,15 @@ uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
         }
     } else if (pwm == PWM1) {
         if (u32ChannelNum < 2) {
-            if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 0)
+            if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
                 u32PWM_CLock = __HXT;
-            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 1)
+            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
                 u32PWM_CLock = __LXT;
-            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 2)
+            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
                 u32PWM_CLock = SystemCoreClock;
-            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 3)
+            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
                 u32PWM_CLock = __HIRC;
-            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 4)
+            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
                 u32PWM_CLock = __LIRC;
         } else if (u32ChannelNum < 4) {
             if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
@@ -207,7 +207,7 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
                                    uint32_t u32CaptureEdge)
 {
     uint32_t i;
-    uint32_t u32PWM_CLock;
+    uint32_t u32PWM_CLock = __HIRC;
     uint8_t  u8Divider = 1, u8Prescale = 0xFF;
     uint16_t u16CNR = 0xFFFF;
 
@@ -248,15 +248,15 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
         }
     } else if (pwm == PWM1) {
         if (u32ChannelNum < 2) {
-            if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 0)
+            if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
                 u32PWM_CLock = __HXT;
-            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 1)
+            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
                 u32PWM_CLock = __LXT;
-            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 2)
+            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
                 u32PWM_CLock = SystemCoreClock;
-            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 3)
+            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
                 u32PWM_CLock = __HIRC;
-            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 4)
+            else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
                 u32PWM_CLock = __LIRC;
         } else if (u32ChannelNum < 4) {
             if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
@@ -451,6 +451,7 @@ uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum)
  *                  - \ref PWM_BRK0_CPO0
  *                  - \ref PWM_BRK0_CPO1
  *                  - \ref PWM_BRK0_CPO2
+ *                  - \ref PWM_BRK1_LVDBK
  *                  - \ref PWM_BK1SEL_BKP1
  *                  - \ref PWM_BK1SEL_CPO0
  *                  - \ref PWM_BK1SEL_CPO1
@@ -463,20 +464,29 @@ void PWM_EnableFaultBrake (PWM_T *pwm,
 {
     if ((u32BrakeSource == PWM_BRK0_BKP0)||(u32BrakeSource == PWM_BRK0_CPO0)||(u32BrakeSource == PWM_BRK0_CPO1)||(u32BrakeSource == PWM_BRK0_CPO2))
         pwm->BRKCTL |= (u32BrakeSource | PWM_BRKCTL_BRK0EN_Msk);
+    else if (u32BrakeSource == PWM_BRK1_LVDBK)
+        pwm->BRKCTL |= PWM_BRKCTL_LVDBKEN_Msk;
     else
         pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BK1SEL_Msk) | u32BrakeSource | PWM_BRKCTL_BRK1EN_Msk;
+
+    pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BKOD_Msk) | (u32LevelMask << PWM_BRKCTL_BKOD_Pos);
+
 }
 
 /**
  * @brief This function clear fault brake flag
  * @param[in] pwm The base address of PWM module
- * @param[in] u32BrakeSource This parameter is not used
+ * @param[in] u32BrakeSource Fault brake source 0 or 1
+ *                           0: brake 0, 1: brake 1
  * @return None
  * @note After fault brake occurred, application must clear fault brake source before re-enable PWM output
  */
 void PWM_ClearFaultBrakeFlag (PWM_T *pwm, uint32_t u32BrakeSource)
 {
-    pwm->INTSTS = PWM_INTSTS_BRKLK0_Msk;
+    if (u32BrakeSource == 0)
+        pwm->INTSTS = (PWM_INTSTS_BRKLK0_Msk | PWM_INTSTS_BRKIF0_Msk);
+    else
+        pwm->INTSTS = PWM_INTSTS_BRKIF1_Msk;
 }
 
 /**
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.h
index a41b58cdcc..d9386a1009 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.h
@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     pwm.h
  * @version  V1.00
- * $Revision: 19 $
- * $Date: 14/10/06 1:36p $
+ * $Revision: 22 $
+ * $Date: 15/11/16 2:08p $
  * @brief    NUC472/NUC442 PWM driver header file
  *
  * @note
@@ -29,14 +29,18 @@ extern "C"
   @{
 */
 #define PWM_CHANNEL_NUM                     (6)      /*!< PWM channel number \hideinitializer */
+#define PWM_CH0                             (0UL)    /*!< PWM channel 0  \hideinitializer */
+#define PWM_CH1                             (1UL)    /*!< PWM channel 1  \hideinitializer */
+#define PWM_CH2                             (2UL)    /*!< PWM channel 2  \hideinitializer */
+#define PWM_CH3                             (3UL)    /*!< PWM channel 3  \hideinitializer */
+#define PWM_CH4                             (4UL)    /*!< PWM channel 4  \hideinitializer */
+#define PWM_CH5                             (5UL)    /*!< PWM channel 5  \hideinitializer */
 #define PWM_CH_0_MASK                       (1UL)    /*!< PWM channel 0 mask \hideinitializer */
 #define PWM_CH_1_MASK                       (2UL)    /*!< PWM channel 1 mask \hideinitializer */
 #define PWM_CH_2_MASK                       (4UL)    /*!< PWM channel 2 mask \hideinitializer */
 #define PWM_CH_3_MASK                       (8UL)    /*!< PWM channel 3 mask \hideinitializer */
 #define PWM_CH_4_MASK                       (16UL)   /*!< PWM channel 4 mask \hideinitializer */
 #define PWM_CH_5_MASK                       (32UL)   /*!< PWM channel 5 mask \hideinitializer */
-#define PWM_CH_6_MASK                       (64UL)   /*!< PWM channel 6 mask \hideinitializer */
-#define PWM_CH_7_MASK                       (128UL)  /*!< PWM channel 7 mask \hideinitializer */
 #define PWM_CLK_DIV_1                       (4UL)    /*!< PWM clock divide by 1 \hideinitializer */
 #define PWM_CLK_DIV_2                       (0UL)    /*!< PWM clock divide by 2 \hideinitializer */
 #define PWM_CLK_DIV_4                       (1UL)    /*!< PWM clock divide by 4 \hideinitializer */
@@ -48,10 +52,11 @@ extern "C"
 #define PWM_TRIGGER_ADC_FALLING_EDGE_POINT  (0x10000UL)       /*!< PWM trigger ADC while output falling edge is detected \hideinitializer */
 #define PWM_TRIGGER_ADC_CENTER_POINT        (0x100UL)         /*!< PWM trigger ADC while counter matches (CNR + 1) \hideinitializer */
 #define PWM_TRIGGER_ADC_PERIOD_POINT        (0x1UL)           /*!< PWM trigger ADC while counter down count to 0  \hideinitializer */
-#define PWM_BRK0_BKP0                       (0UL)                          /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
+#define PWM_BRK0_BKP0                       (PWM_BRKCTL_BRK0EN_Msk)                          /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
 #define PWM_BRK0_CPO0                       (PWM_BRKCTL_CPO0BKEN_Msk)      /*!< Brake0 signal source from analog comparator 0 output \hideinitializer */
 #define PWM_BRK0_CPO1                       (PWM_BRKCTL_CPO1BKEN_Msk)      /*!< Brake0 signal source from analog comparator 1 output \hideinitializer */
 #define PWM_BRK0_CPO2                       (PWM_BRKCTL_CPO2BKEN_Msk)      /*!< Brake0 signal source from analog comparator 2 output \hideinitializer */
+#define PWM_BRK1_LVDBK                      (PWM_BRKCTL_LVDBKEN_Msk)     /*!< Brake1 signal source from level detect \hideinitializer */
 #define PWM_BK1SEL_BKP1                     (0UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from external pin BKP1 \hideinitializer */
 #define PWM_BK1SEL_CPO0                     (1UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 0 output \hideinitializer */
 #define PWM_BK1SEL_CPO1                     (2UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 1 output \hideinitializer */
@@ -79,7 +84,7 @@ extern "C"
  * @return None
  * \hideinitializer
  */
-#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_OUTMODE_Msk)
+#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_OUTMODE_Msk)
 
 /**
  * @brief This macro disable complementary mode, and enable independent mode.
@@ -87,7 +92,7 @@ extern "C"
  * @return None
  * \hideinitializer
  */
-#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_OUTMODE_Msk)
+#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_OUTMODE_Msk)
 
 /**
  * @brief This macro enable group mode
@@ -95,7 +100,7 @@ extern "C"
  * @return None
  * \hideinitializer
  */
-#define PWM_ENABLE_GROUP_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_GROUPEN_Msk)
+#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_GROUPEN_Msk)
 
 /**
  * @brief This macro disable group mode
@@ -103,7 +108,7 @@ extern "C"
  * @return None
  * \hideinitializer
  */
-#define PWM_DISABLE_GROUP_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_GROUPEN_Msk)
+#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_GROUPEN_Msk)
 
 /**
  * @brief This macro enable synchronous mode
@@ -111,7 +116,7 @@ extern "C"
  * @return None
  * \hideinitializer
  */
-#define PWM_ENABLE_SYNC_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_SYNCEN_Msk)
+#define PWM_ENABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_SYNCEN_Msk)
 
 /**
  * @brief This macro disable synchronous mode, and enable independent mode.
@@ -119,7 +124,7 @@ extern "C"
  * @return None
  * \hideinitializer
  */
-#define PWM_DISABLE_SYNC_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_SYNCEN_Msk)
+#define PWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_SYNCEN_Msk)
 
 /**
  * @brief This macro enable output inverter of specified channel(s)
@@ -129,7 +134,7 @@ extern "C"
  * @return None
  * \hideinitializer
  */
-#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) (pwm->CTL |= (u32ChannelMask << PWM_CTL_PINV_Pos)
+#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->CTL = (((pwm)->CTL & ~PWM_CTL_PINV_Msk) | ((u32ChannelMask) << PWM_CTL_PINV_Pos)))
 
 /**
  * @brief This macro get captured rising data
@@ -138,7 +143,7 @@ extern "C"
  * @return None
  * \hideinitializer
  */
-#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->RCAPDAT0 + 2 * u32ChannelNum))
+#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->RCAPDAT0 + 2 * (u32ChannelNum)))
 
 /**
  * @brief This macro get captured falling data
@@ -147,7 +152,7 @@ extern "C"
  * @return None
  * \hideinitializer
  */
-#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->FCAPDAT0 + 2 * u32ChannelNum))
+#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->FCAPDAT0 + 2 * (u32ChannelNum)))
 
 /**
  * @brief This macro mask output output logic to high or low
@@ -158,7 +163,7 @@ extern "C"
  * @return None
  * \hideinitializer
  */
-#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) (pwm->MSKEN |= u32ChannelMask)
+#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) ((pwm)->MSKEN |= (u32ChannelMask))
 
 /**
  * @brief This macro set the prescaler of the selected channel
@@ -171,7 +176,7 @@ extern "C"
  * \hideinitializer
  */
 #define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
-    (pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
+    (pwm->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
 
 /**
  * @brief This macro set the divider of the selected channel
@@ -187,7 +192,7 @@ extern "C"
  * \hideinitializer
  */
 #define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
-    (pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
+    ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
 
 /**
  * @brief This macro set the duty of the selected channel
@@ -198,7 +203,7 @@ extern "C"
  * @note This new setting will take effect on next PWM period
  * \hideinitializer
  */
-#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (pwm->CMPDAT[u32ChannelNum] = (u32CMR))
+#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
 
 /**
  * @brief This macro set the period of the selected channel
@@ -210,7 +215,7 @@ extern "C"
  * @note PWM counter will stop if period length set to 0
  * \hideinitializer
  */
-#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR)  (pwm->PERIOD[u32ChannelNum] = (u32CNR))
+#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR)  ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
 
 /**
  * @brief This macro set the PWM aligned type
@@ -224,7 +229,11 @@ extern "C"
  * \hideinitializer
  */
 #define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
-    (pwm->CTL = (pwm->CTL & ~(u32ChannelMask << PWM_CTL_CNTMODE_Pos) | (u32AlignedType << PWM_CTL_CNTMODE_Pos))
+do { \
+    (pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk); \
+    if ((u32AlignedType) == PWM_CENTER_ALIGNED) \
+      (pwm)->CTL = ((pwm)->CTL | ((u32ChannelMask) << PWM_CTL_CNTTYPE_Pos)); \
+} while(0)
 
 
 uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
diff --git a/targets/targets.json b/targets/targets.json
index 953adeb8b0..2bbacc11df 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -2355,7 +2355,7 @@
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "CAN"],
         "features": ["LWIP"],
         "release_versions": ["5"],
         "device_name": "NUC472HI8AE"
@@ -2379,7 +2379,7 @@
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
         "progen": {"target": "numaker-pfm-m453"},
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "CAN"],
         "release_versions": ["2", "5"],
         "device_name": "M453VG6AE"
     },