From bd8fa4eb709a3d057660f9a03f3b27f732c928c5 Mon Sep 17 00:00:00 2001 From: Ganesh Ramachandran <30490592+ganesh-ramachandran@users.noreply.github.com> Date: Tue, 1 Aug 2017 11:26:58 +0530 Subject: [PATCH 1/7] Added Support for Toshiba TMPM066 --- .../Periph_Driver/inc/tmpm066_adc.h | 207 ++ .../Periph_Driver/inc/tmpm066_cg.h | 180 ++ .../Periph_Driver/inc/tmpm066_gpio.h | 229 ++ .../Periph_Driver/inc/tmpm066_i2c.h | 203 ++ .../Periph_Driver/inc/tmpm066_intifao.h | 100 + .../Periph_Driver/inc/tmpm066_intifsd.h | 228 ++ .../Periph_Driver/inc/tmpm066_tmr16a.h | 108 + .../Periph_Driver/inc/tmpm066_tmrb.h | 259 ++ .../Periph_Driver/inc/tmpm066_uart.h | 381 +++ .../Periph_Driver/inc/tx00_common.h | 47 + .../Periph_Driver/src/tmpm066_adc.c | 571 ++++ .../Periph_Driver/src/tmpm066_cg.c | 698 +++++ .../Periph_Driver/src/tmpm066_gpio.c | 696 +++++ .../Periph_Driver/src/tmpm066_i2c.c | 931 +++++++ .../Periph_Driver/src/tmpm066_intifao.c | 284 ++ .../Periph_Driver/src/tmpm066_intifsd.c | 368 +++ .../Periph_Driver/src/tmpm066_tmr16a.c | 195 ++ .../Periph_Driver/src/tmpm066_tmrb.c | 555 ++++ .../Periph_Driver/src/tmpm066_uart.c | 1198 +++++++++ .../TARGET_TMPM066/PeripheralNames.h | 100 + .../TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h | 115 + .../TARGET_TOSHIBA/TARGET_TMPM066/PortNames.h | 38 + .../TARGET_TMPM066/analogin_api.c | 89 + .../TARGET_TOSHIBA/TARGET_TMPM066/device.h | 24 + .../TARGET_TMPM066/device/TMPM066.h | 2287 +++++++++++++++++ .../TOOLCHAIN_ARM_STD/startup_TMPM066.S | 190 ++ .../device/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../device/TOOLCHAIN_ARM_STD/tmpm066fwug.sct | 32 + .../TOOLCHAIN_GCC_ARM/startup_TMPM066.S | 220 ++ .../device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld | 150 ++ .../device/TOOLCHAIN_IAR/startup_TMPM066.S | 281 ++ .../device/TOOLCHAIN_IAR/tmpm066fwug.icf | 31 + .../TARGET_TMPM066/device/cmsis.h | 12 + .../TARGET_TMPM066/device/cmsis_nvic.c | 33 + .../TARGET_TMPM066/device/cmsis_nvic.h | 43 + .../TARGET_TMPM066/device/system_TMPM066.c | 301 +++ .../TARGET_TMPM066/device/system_TMPM066.h | 49 + .../TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c | 96 + .../TARGET_TMPM066/gpio_irq_api.c | 246 ++ .../TARGET_TMPM066/gpio_object.h | 40 + .../TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c | 361 +++ .../TARGET_TOSHIBA/TARGET_TMPM066/objects.h | 80 + .../TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c | 106 + .../TARGET_TOSHIBA/TARGET_TMPM066/port_api.c | 124 + .../TARGET_TMPM066/pwmout_api.c | 243 ++ .../TARGET_TMPM066/serial_api.c | 253 ++ targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c | 66 + .../TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c | 103 + targets/TARGET_TOSHIBA/mbed_rtx.h | 32 + targets/targets.json | 12 + 50 files changed, 13226 insertions(+) create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_adc.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_cg.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_gpio.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_i2c.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifao.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifsd.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmr16a.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmrb.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tx00_common.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_adc.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_cg.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_gpio.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifao.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifsd.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmr16a.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmrb.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/PeripheralNames.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/PortNames.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TMPM066.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/startup_TMPM066.S create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/tmpm066fwug.sct create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/startup_TMPM066.S create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/startup_TMPM066.S create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/objects.h create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/pwmout_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c create mode 100644 targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c create mode 100644 targets/TARGET_TOSHIBA/mbed_rtx.h diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_adc.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_adc.h new file mode 100644 index 0000000000..156ec40c4b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_adc.h @@ -0,0 +1,207 @@ +/** + ******************************************************************************* + * @file tmpm066_adc.h + * @brief This file provides all the functions prototypes for ADC driver. + * @version V2.0.2.1 + * @date 2015/10/09 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TMPM066_ADC_H +#define __TMPM066_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "TMPM066.h" +#include "tx00_common.h" + +#if defined(__TMPM066_ADC_H) + +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Exported_Types + * @{ + */ + +#define ADC_CONVERSION_35_CLOCK ((uint32_t)0x00000000) /* 35.5 conversion clock */ +#define ADC_CONVERSION_42_CLOCK ((uint32_t)0x00000040) /* 42 conversion clock */ +#define ADC_CONVERSION_68_CLOCK ((uint32_t)0x00000080) /* 68 conversion clock */ +#define ADC_CONVERSION_81_CLOCK ((uint32_t)0x000000C0) /* 81 conversion clock */ +#define IS_ADC_CONVERSION_TIME(param) (((param) == ADC_CONVERSION_35_CLOCK) || \ + ((param) == ADC_CONVERSION_42_CLOCK) || \ + ((param) == ADC_CONVERSION_68_CLOCK) || \ + ((param) == ADC_CONVERSION_81_CLOCK)) + +#define ADC_FC_DIVIDE_LEVEL_1 ((uint32_t)0x00000000) +#define ADC_FC_DIVIDE_LEVEL_2 ((uint32_t)0x00000001) +#define ADC_FC_DIVIDE_LEVEL_4 ((uint32_t)0x00000002) +#define ADC_FC_DIVIDE_LEVEL_6 ((uint32_t)0x00000008) +#define ADC_FC_DIVIDE_LEVEL_8 ((uint32_t)0x00000003) +#define ADC_FC_DIVIDE_LEVEL_12 ((uint32_t)0x00000009) +#define ADC_FC_DIVIDE_LEVEL_16 ((uint32_t)0x00000004) +#define ADC_FC_DIVIDE_LEVEL_24 ((uint32_t)0x0000000A) +#define ADC_FC_DIVIDE_LEVEL_48 ((uint32_t)0x0000000B) +#define ADC_FC_DIVIDE_LEVEL_96 ((uint32_t)0x0000000C) +#define IS_ADC_PRESCALER(param) (((param) == ADC_FC_DIVIDE_LEVEL_1) || \ + ((param) == ADC_FC_DIVIDE_LEVEL_2) || \ + ((param) == ADC_FC_DIVIDE_LEVEL_4) || \ + ((param) == ADC_FC_DIVIDE_LEVEL_6) || \ + ((param) == ADC_FC_DIVIDE_LEVEL_8) || \ + ((param) == ADC_FC_DIVIDE_LEVEL_12) || \ + ((param) == ADC_FC_DIVIDE_LEVEL_16) || \ + ((param) == ADC_FC_DIVIDE_LEVEL_24) || \ + ((param) == ADC_FC_DIVIDE_LEVEL_48) || \ + ((param) == ADC_FC_DIVIDE_LEVEL_96)) + +#define ADC_INT_SINGLE ((uint32_t)0x00000000) +#define ADC_INT_CONVERSION_4 ((uint32_t)0x00000008) +#define ADC_INT_CONVERSION_8 ((uint32_t)0x00000010) +#define IS_ADC_INT_MODE(param) (((param) == ADC_INT_SINGLE) || \ + ((param) == ADC_INT_CONVERSION_4) || \ + ((param) == ADC_INT_CONVERSION_8)) + +#define ADC_AN_0 ((uint32_t)0x00000000) +#define ADC_AN_1 ((uint32_t)0x00000001) +#define ADC_AN_2 ((uint32_t)0x00000002) +#define ADC_AN_3 ((uint32_t)0x00000003) +#define ADC_AN_4 ((uint32_t)0x00000004) +#define ADC_AN_5 ((uint32_t)0x00000005) +#define ADC_AN_6 ((uint32_t)0x00000006) +#define ADC_AN_7 ((uint32_t)0x00000007) + +#define IS_ADC_INPUT_CH(param) (((param) == ADC_AN_0) || \ + ((param) == ADC_AN_1) || \ + ((param) == ADC_AN_2) || \ + ((param) == ADC_AN_3) || \ + ((param) == ADC_AN_4) || \ + ((param) == ADC_AN_5) || \ + ((param) == ADC_AN_6) || \ + ((param) == ADC_AN_7)) + + +#define ADC_CMP_0 ((uint8_t)0x00) +#define ADC_CMP_1 ((uint8_t)0x01) +#define IS_ADC_CMP(param) (((param) == ADC_CMP_0) || \ + ((param) == ADC_CMP_1)) + +#define ADC_REG_0 ((uint32_t)0x00000000) +#define ADC_REG_1 ((uint32_t)0x00000001) +#define ADC_REG_2 ((uint32_t)0x00000002) +#define ADC_REG_3 ((uint32_t)0x00000003) +#define ADC_REG_4 ((uint32_t)0x00000004) +#define ADC_REG_5 ((uint32_t)0x00000005) +#define ADC_REG_6 ((uint32_t)0x00000006) +#define ADC_REG_7 ((uint32_t)0x00000007) +#define ADC_REG_SP ((uint32_t)0x00000008) +#define IS_ADC_REG(param) ((param) <= ADC_REG_SP) + +#define IS_ADC_RESULT_CMP_REG(param) ((param) <= ADC_REG_SP) + +#define ADC_EXT_TRG ((uint32_t)0x00000000) +#define ADC_MATCH_TB_0 ((uint32_t)0x00000020) +#define IS_ADC_HW_TRG_NORMAL(param) (((param) == ADC_EXT_TRG) || \ + ((param) == ADC_MATCH_TB_0)) + +#define ADC_MATCH_TB_1 ((uint32_t)0x00000080) +#define IS_ADC_HW_TRG_TOP(param) (((param) == ADC_EXT_TRG) || \ + ((param) == ADC_MATCH_TB_1)) + +#define IS_ADC_CMP_VALUE(param) ((param) <= (uint16_t)0x03ff) + + typedef enum { + ADC_NO_OVERRUN = 0U, + ADC_OVERRUN = 1U + } ADC_OverrunState; + + typedef enum { + ADC_SCAN_4CH = 0U, + ADC_SCAN_8CH = 1U + } ADC_ChannelScanMode; +#define IS_ADC_CH_SCAN_MODE(param) (((param) == ADC_SCAN_4CH) || \ + ((param) == ADC_SCAN_8CH)) + + typedef enum { + ADC_COMPARISON_SMALLER = 0U, + ADC_COMPARISON_LARGER = 1U + } ADC_ComparisonState; +#define IS_ADC_CMP_INT(param) (((param) == ADC_COMPARISON_SMALLER) || \ + ((param) == ADC_COMPARISON_LARGER)) + + typedef struct { + WorkState ADCResultStored; /*!< ADC result storage flag */ + ADC_OverrunState ADCOverrunState; /*!< ADC overrun flag */ + uint16_t ADCResultValue; /*!< ADC result value */ + } ADC_ResultTypeDef; + +#define ADC_DMA_REQ_NORMAL ((uint8_t)0x00) +#define ADC_DMA_REQ_TOP ((uint8_t)0x01) +#define ADC_DMA_REQ_MONITOR1 ((uint8_t)0x02) +#define ADC_DMA_REQ_MONITOR2 ((uint8_t)0x03) +#define IS_ADC_DMA_REQ(param) ((param) <= ADC_DMA_REQ_MONITOR2) + + typedef union { + uint32_t All; + struct { + uint32_t NormalBusy:1; /*!< bit0, Normal A/D conversion busy flag (MOD0) */ + uint32_t NormalComplete:1; /*!< bit1, Normal AD conversion complete flag (MOD0) */ + uint32_t TopBusy:1; /*!< bit2, Top-priority A/D conversion busy flag (MOD2) */ + uint32_t TopComplete:1; /*!< bit3, Top-priority AD conversion complete flag (MOD2) */ + uint32_t Reserved:28; /*!< bit4 to bit 31, reserved */ + } Bit; + } ADC_State; + +/** @} */ +/* End of group ADC_Exported_Types */ + +/** @defgroup ADC_Exported_FunctionPrototypes + * @{ + */ + void ADC_SWReset(void); + void ADC_SetClk(uint32_t Conversion_Time, uint32_t Prescaler_Output); + void ADC_Start(void); + void ADC_SetScanMode(FunctionalState NewState); + void ADC_SetRepeatMode(FunctionalState NewState); + void ADC_SetINTMode(uint32_t INTMode); + ADC_State ADC_GetConvertState(void); + void ADC_SetInputChannel(uint32_t InputChannel); + void ADC_SetChannelScanMode(ADC_ChannelScanMode ScanMode); + void ADC_SetIdleMode(FunctionalState NewState); + void ADC_SetVref(FunctionalState NewState); + void ADC_SetInputChannelTop(uint32_t TopInputChannel); + void ADC_StartTopConvert(void); + void ADC_SetMonitor(uint8_t ADCMPx, FunctionalState NewState); + void ADC_SetResultCmpReg(uint8_t ADCMPx, uint32_t ResultComparison); + void ADC_SetMonitorINT(uint8_t ADCMPx, ADC_ComparisonState NewState); + void ADC_SetHWTrg(uint32_t HwSource, FunctionalState NewState); + void ADC_SetHWTrgTop(uint32_t HwSource, FunctionalState NewState); + ADC_ResultTypeDef ADC_GetConvertResult(uint32_t ADREGx); + void ADC_SetCmpValue(uint8_t ADCMPx, uint16_t value); + void ADC_SetDMAReq(uint8_t DMAReq, FunctionalState NewState); + +/** @} */ +/* End of group ADC_Exported_FunctionPrototypes */ + +/** @} */ +/* End of group ADC */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#endif /* (__TMPM066_ADC_H) */ + +#ifdef __cplusplus +} +#endif +#endif /* __TMPM066_ADC_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_cg.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_cg.h new file mode 100644 index 0000000000..55d4f8b5f5 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_cg.h @@ -0,0 +1,180 @@ +/** + ******************************************************************************* + * @file tmpm066_cg.h + * @brief This file provides all the functions prototypes for CG driver. + * @version V2.0.2.1 + * @date 2015/09/29 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TMPM066_CG_H +#define __TMPM066_CG_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "TMPM066.h" +#include "tx00_common.h" + +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @addtogroup CG + * @{ + */ + +/** @addtogroup CG_Exported_types + * @{ + */ + + typedef enum { + CG_DIVIDE_1 = 0U, + CG_DIVIDE_2 = 1U, + CG_DIVIDE_4 = 2U, + CG_DIVIDE_8 = 3U, + CG_DIVIDE_16 = 4U, + CG_DIVIDE_32 = 5U, + CG_DIVIDE_64 = 6U, + CG_DIVIDE_128 = 7U, + CG_DIVIDE_256 = 8U, + CG_DIVIDE_512 = 9U, + CG_DIVIDE_UNKNOWN = 10U, + CG_DIVIDE_MAX = 16U + } CG_DivideLevel; +#define IS_CG_GEAR_DIVIDE_LEVEL(param) (((param) == CG_DIVIDE_1) || \ + ((param) == CG_DIVIDE_2) || \ + ((param) == CG_DIVIDE_4) || \ + ((param) == CG_DIVIDE_8) || \ + ((param) == CG_DIVIDE_16)) + +#define IS_CG_DIVIDE_FC_LEVEL(param) (((param) == CG_DIVIDE_1) || \ + ((param) == CG_DIVIDE_2) || \ + ((param) == CG_DIVIDE_4) || \ + ((param) == CG_DIVIDE_8) || \ + ((param) == CG_DIVIDE_16) || \ + ((param) == CG_DIVIDE_32) || \ + ((param) == CG_DIVIDE_64)|| \ + ((param) == CG_DIVIDE_128) || \ + ((param) == CG_DIVIDE_256) || \ + ((param) == CG_DIVIDE_512)) + + typedef enum { + CG_FOSC_OSC_INT = 0U, + CG_FOSC_OSC_EXT = 1U, + CG_FOSC_CLKIN_EXT = 2U + } CG_FoscSrc; +#define IS_CG_FOSC_SRC(param) (((param) == CG_FOSC_OSC_EXT) || \ + ((param) == CG_FOSC_OSC_INT) || \ + ((param) == CG_FOSC_CLKIN_EXT)) + +#define IS_CG_FOSC_STATE(param) (((param) == CG_FOSC_OSC_EXT) || \ + ((param) == CG_FOSC_OSC_INT) ) + + typedef enum { + CG_WARM_UP_SRC_OSC_INT_HIGH = 0U, + CG_WARM_UP_SRC_OSC_EXT_HIGH = 1U, + } CG_WarmUpSrc; +#define IS_CG_WARM_UP_SRC(param) (((param) == CG_WARM_UP_SRC_OSC_INT_HIGH) || \ + ((param) == CG_WARM_UP_SRC_OSC_EXT_HIGH)) + + typedef enum { + CG_FC_SRC_FOSC = 0U, + CG_FC_SRC_FPLL = 1U + } CG_FcSrc; +#define IS_CG_FC_SRC(param) (((param) == CG_FC_SRC_FOSC) || \ + ((param) == CG_FC_SRC_FPLL)) + +#define CG_8M_MUL_12_FPLL (0x00C60B00UL<<8U) /* 12 fold, input 8MHz, output 96MHz */ +#define CG_10M_MUL_8_FPLL (0x00C60700UL<<8U) /* 10 fold, input 10MHz, output 80MHz */ +#define CG_12M_MUL_8_FPLL (0x00C60700UL<<8U) /* 12 fold, input 12MHz, output 96MHz */ +#define CG_16M_MUL_6_FPLL (0x00C60500UL<<8U) /* 16 fold, input 16MHz, output 96MHz */ + +#define IS_CG_FPLL_VALUE(param) (((param) == CG_8M_MUL_12_FPLL) || \ + ((param) == CG_10M_MUL_8_FPLL) || \ + ((param) == CG_12M_MUL_8_FPLL) || \ + ((param) == CG_16M_MUL_6_FPLL)) + typedef enum { + CG_STBY_MODE_IDLE = 0U, + CG_STBY_MODE_STOP1 = 1U, + CG_STBY_MODE_UNKNOWN = 2U, + CG_STBY_MODE_MAX = 4U + } CG_STBYMode; +#define IS_CG_STBY_MODE(param) (((param) == CG_STBY_MODE_STOP1) || \ + ((param) == CG_STBY_MODE_IDLE)) +#define CG_FC_PERIPH_PORTH (0x00000001U << 7U) +#define CG_FC_PERIPH_PORTJ (0x00000001U << 8U) +#define CG_FC_PERIPH_TMRB0_3 (0x00000001U << 9U) +#define CG_FC_PERIPH_TMRB4_6 (0x00000001U << 10U) +#define CG_FC_PERIPH_TMR16A (0x00000001U << 11U) +#define CG_FC_PERIPH_I2C0 (0x00000001U << 12U) +#define CG_FC_PERIPH_SIO0 (0x00000001U << 13U) +#define CG_FC_PERIPH_TSPI (0x00000001U << 14U) +#define CG_FC_PERIPH_DMAC (0x00000001U << 15U) +#define CG_FC_PERIPH_ADC (0x00000001U << 16U) +#define CG_FC_PERIPH_USBD (0x00000001U << 17U) +#define CG_FC_PERIPH_TMRD (0x00000001U << 18U) +#define CG_FC_PERIPHA_ALL (0xFFFFFFFFU) +#define IS_CG_FC_PERIPHA(param) ( ((param) >= CG_FC_PERIPH_PORTH) && ((param) <= CG_FC_PERIPH_TMRD )) + +#define CG_FC_PERIPH_TMRB7 (0x00000001U << 28U) +#define CG_FC_PERIPH_SIO1 (0x00000001U << 29U) +#define CG_FC_PERIPH_WDT (0x00000001U << 30U) +#define CG_FC_PERIPH_I2C1 (0x00000001U << 31U) +#define CG_FC_PERIPHB_ALL (0xFFFFFFFFU) +#define IS_CG_FC_PERIPHB(param) (((param) >= CG_FC_PERIPH_TMRB7)) + +#define CG_FPLL_PERIPH_TMRD (0x00000001U << 5U) +#define CG_EHCLKSEL_8_24_48MHZ (0x00000001U << 4U) +#define CG_USBSEL_PLL_CLOCKIN (0x00000001U << 1U) +#define CG_USBENA_USB (0x00000001U) +#define CG_FPLL_OPTIONAL_ALL (0x0FFFFFFFU) +#define IS_CG_FPLL_OPTIONAL(param) (((param) > 0U) && ((param) <= CG_FPLL_OPTIONAL_ALL)) + +/** @} */ +/* End of group CG_Exported_types */ + +/** @defgroup CG_Exported_FunctionPrototypes + * @{ + */ + void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc); + CG_DivideLevel CG_GetFgearLevel(void); + Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc); + CG_DivideLevel CG_GetPhiT0Level(void); + void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time); + void CG_StartWarmUp(void); + WorkState CG_GetWarmUpState(void); + Result CG_SetFPLLValue(uint32_t NewValue); + uint32_t CG_GetFPLLValue(void); + Result CG_SetPLL(FunctionalState NewState); + FunctionalState CG_GetPLLState(void); + void CG_SetFoscSrc(CG_FoscSrc Source); + CG_FoscSrc CG_GetFoscSrc(void); + void CG_SetSTBYMode(CG_STBYMode Mode); + CG_STBYMode CG_GetSTBYMode(void); + void CG_SetFcSrc(CG_FcSrc Source); + CG_FcSrc CG_GetFcSrc(void); + void CG_SetProtectCtrl(FunctionalState NewState); + void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState); + void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState); + void CG_SetFcOptional(uint32_t Periph, FunctionalState NewState); + void CG_SetADCClkSupply(FunctionalState NewState); + +/** @} */ +/* End of group CG_Exported_FunctionPrototype */ + +/** @} */ +/* End of group CG */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TMPM066_CG_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_gpio.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_gpio.h new file mode 100644 index 0000000000..6d0a86fa49 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_gpio.h @@ -0,0 +1,229 @@ +/** + ******************************************************************************* + * @file tmpm066_gpio.h + * @brief This file provides all the functions prototypes for GPIO driver. + * @version V2.0.2.1 + * @date 2015/09/29 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TMPM066_GPIO_H +#define __TMPM066_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "TMPM066.h" +#include "tx00_common.h" + +#if defined(__TMPM066_GPIO_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ +/** @addtogroup GPIO + * @{ + */ +/** @addtogroup GPIO_Parameter_Definition + * @{ + */ + + +/** @brief :The maximum number of the Function Register + * Note for porting: + * If functiong register 2 is the maximum number in + * all the GPIO port,then define FRMAX (2U) + */ +#define FRMAX (2U) /* the max number of Port I/O function register is 2 */ + + +/** @brief: define for function register + * Note for porting: + * If the maximum number of the function Register is 2, + * then you need to define 2 GPIO_FUNC_REG_x , + * the value should be increased from 0 to 1 + */ +#define GPIO_FUNC_REG_1 ((uint8_t)0x00) +#define GPIO_FUNC_REG_2 ((uint8_t)0x01) + +/** @brief :The GPIO_Port enum + * Note for porting: + * the port value order from low to high with '1' step + * and begin with "0". + */ + typedef enum { + GPIO_PA = 0U, + GPIO_PB = 1U, + GPIO_PC = 2U, + GPIO_PD = 3U, + GPIO_PE = 4U, + GPIO_PF = 5U, + GPIO_PG = 6U, + GPIO_PH = 7U, + GPIO_PJ = 8U + } GPIO_Port; + +#define IS_GPIO_PORT(param) ((param) <= GPIO_PJ) /*parameter checking for port number */ + +#define IS_GPIO_PORT_INPUT_VOLTAGE(param) (((param) == GPIO_PC) || \ + ((param) == GPIO_PD) || \ + ((param) == GPIO_PG)) + +#define RESER (8U-(FRMAX)) + + typedef struct { + __IO uint32_t DATA; + __IO uint32_t CR; + __IO uint32_t FR[FRMAX]; + uint32_t RESERVED0[RESER]; + __IO uint32_t OD; + __IO uint32_t PUP; + __IO uint32_t PDN; + __IO uint32_t SEL; + __IO uint32_t IE; + } TSB_Port_TypeDef; + + typedef struct { + uint8_t PinDATA; + uint8_t PinCR; + uint8_t PinFR[FRMAX]; + uint8_t PinOD; + uint8_t PinPUP; + uint8_t PinPDN; + uint8_t PinSEL; + uint8_t PinIE; + } GPIO_RegTypeDef; + + typedef struct { + uint8_t IOMode; /* Set the port input or output mode */ + uint8_t PullUp; /* Enable or disable Pullup function */ + uint8_t OpenDrain; /* Enable or disable open drain function */ + uint8_t PullDown; /* Enable or disable Pulldown function */ + uint8_t InputVoltage; /* Enable or disable Input Voltage function */ + } GPIO_InitTypeDef; + +#define GPIO_INPUT_MODE ((uint8_t)0x00) +#define GPIO_OUTPUT_MODE ((uint8_t)0x01) +#define GPIO_IO_MODE_NONE ((uint8_t)0x02) +#define IS_GPIO_IO_MODE_STATE(param) (((param) == GPIO_INPUT_MODE) || \ + ((param) == GPIO_OUTPUT_MODE) || \ + ((param) == GPIO_IO_MODE_NONE)) + +#define GPIO_PULLUP_DISABLE ((uint8_t)0x00) +#define GPIO_PULLUP_ENABLE ((uint8_t)0x01) +#define GPIO_PULLUP_NONE ((uint8_t)0x02) +#define IS_GPIO_PULLUP_STATE(param) (((param) == GPIO_PULLUP_ENABLE) || \ + ((param) == GPIO_PULLUP_DISABLE) || \ + ((param) == GPIO_PULLUP_NONE)) + +#define GPIO_PULLDOWN_DISABLE ((uint8_t)0x00) +#define GPIO_PULLDOWN_ENABLE ((uint8_t)0x01) +#define GPIO_PULLDOWN_NONE ((uint8_t)0x02) +#define IS_GPIO_PULLDOWN_STATE(param) (((param) == GPIO_PULLDOWN_ENABLE) || \ + ((param) == GPIO_PULLDOWN_DISABLE) || \ + ((param) == GPIO_PULLDOWN_NONE)) + +#define GPIO_OPEN_DRAIN_DISABLE ((uint8_t)0x00) +#define GPIO_OPEN_DRAIN_ENABLE ((uint8_t)0x01) +#define GPIO_OPEN_DRAIN_NONE ((uint8_t)0x02) +#define IS_GPIO_OPEN_DRAIN_STATE(param) (((param) == GPIO_OPEN_DRAIN_ENABLE) || \ + ((param) == GPIO_OPEN_DRAIN_DISABLE) || \ + ((param) == GPIO_OPEN_DRAIN_NONE)) + +#define GPIO_INPUT_VOLTAGE_3V ((uint8_t)0x00) +#define GPIO_INPUT_VOLTAGE_1V8 ((uint8_t)0x01) +#define GPIO_INPUT_VOLTAGE_NONE ((uint8_t)0x02) +#define IS_GPIO_INPUT_VOLTAGE_STATE(param) (((param) == GPIO_INPUT_VOLTAGE_3V) || \ + ((param) == GPIO_INPUT_VOLTAGE_1V8) || \ + ((param) == GPIO_INPUT_VOLTAGE_NONE)) + +#define GPIO_BIT_VALUE_1 ((uint8_t)0x01) +#define GPIO_BIT_VALUE_0 ((uint8_t)0x00) + +#define IS_GPIO_BIT_VALUE(BitValue) (((BitValue) == GPIO_BIT_VALUE_1)|| \ + ((BitValue) == GPIO_BIT_VALUE_0)) + +#define GPIO_BIT_0 ((uint8_t)0x01) +#define GPIO_BIT_1 ((uint8_t)0x02) +#define GPIO_BIT_2 ((uint8_t)0x04) +#define GPIO_BIT_3 ((uint8_t)0x08) +#define GPIO_BIT_4 ((uint8_t)0x10) +#define GPIO_BIT_5 ((uint8_t)0x20) +#define GPIO_BIT_6 ((uint8_t)0x40) +#define GPIO_BIT_7 ((uint8_t)0x80) +#define GPIO_BIT_ALL ((uint8_t)0xFF) + +#define IS_GPIO_WRITE(GPIO_x) (GPIO_SFRs[(GPIO_x)].PinCR) + +#define IS_GPIO_BIT_DATA(GPIO_x,Bit_x) ((((GPIO_SFRs[(GPIO_x)].PinDATA) & (Bit_x))&&\ + (!((uint8_t)(~(GPIO_SFRs[(GPIO_x)].PinDATA))&(Bit_x))))) + +#define IS_GPIO_BIT_OUT(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinCR &(Bit_x))&&\ + (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinCR)&(Bit_x))))) + +#define IS_GPIO_BIT_IN(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinIE &(Bit_x))&&\ + (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinIE)&(Bit_x))))) + +#define IS_GPIO_BIT_PUP(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinPUP &(Bit_x))&&\ + (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPUP)&(Bit_x))))) + +#define IS_GPIO_BIT_PDN(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinPDN &(Bit_x))&&\ + (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPDN)&(Bit_x))))) + +#define IS_GPIO_BIT_OD(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinOD &(Bit_x))&&\ + (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinOD)&(Bit_x))))) + +#define IS_GPIO_BIT_SEL(GPIO_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinSEL &(Bit_x))&&\ + (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinSEL)&(Bit_x))))) + +#define IS_GPIO_BIT_FR(GPIO_x,FuncReg_x,Bit_x) (((GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)]&(Bit_x))&&\ + (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)])&(Bit_x))))) + + +#define IS_GPIO_FUNCTION_REG(param) ((param) < (FRMAX)) + +#define IS_GPIO_BIT(param) (((param) == GPIO_BIT_0)|| \ + ((param) == GPIO_BIT_1)|| \ + ((param) == GPIO_BIT_2)|| \ + ((param) == GPIO_BIT_3)|| \ + ((param) == GPIO_BIT_4)|| \ + ((param) == GPIO_BIT_5)|| \ + ((param) == GPIO_BIT_6)|| \ + ((param) == GPIO_BIT_7)) +/** @} */ +/* End of group GPIO_Bit_Define */ + +/** @defgroup GPIO_Exported_FunctionPrototypes + * @{ + */ + uint8_t GPIO_ReadData(GPIO_Port GPIO_x); + uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x); + void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data); + void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue); + void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct); + void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x); + void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x); + void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState); + void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState); + void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState); + void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState); + void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState); + void GPIO_SetInputVoltage(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue); + void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x); + void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x); +/** @} */ +/* End of group GPIO_Exported_FunctionPrototypes */ +/** @} */ +/* End of group GPIO */ +/** @} */ +/* End of group TX00_Periph_Driver */ +#endif /* defined(__TMPM066_GPIO_H) */ + +#ifdef __cplusplus +} +#endif +#endif /* __TMPM066_GPIO_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_i2c.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_i2c.h new file mode 100644 index 0000000000..f8b73095ac --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_i2c.h @@ -0,0 +1,203 @@ +/** + ******************************************************************************* + * @file tmpm066_i2c.h + * @brief This file provides all the functions prototypes for I2C driver. + * @version V2.0.2.1 + * @date 2015/09/10 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TMPM066_I2C_H +#define __TMPM066_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif /*__cplusplus*/ + +/* Includes ------------------------------------------------------------------*/ +#include "TMPM066.h" +#include "tx00_common.h" + +#if defined(__TMPM066_I2C_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Exported_Types + * @{ + */ + typedef struct { + uint32_t I2CSelfAddr; /*!< Specify self-address of the I2C channel in I2C mode */ + uint32_t I2CDataLen; /*!< Specify data length of the I2C channel in I2C mode */ + FunctionalState I2CACKState; /*!< Enable or disable the generation of ACK clock */ + uint32_t I2CClkDiv; /*!< Select the division of the prescaler clock for generating the serial clock */ + uint32_t PrescalerClkDiv; /* Select the division of fsys for generating the fprsck */ + } I2C_InitTypeDef; + + typedef union { + uint32_t All; + struct { + uint32_t LastRxBit:1; + uint32_t GeneralCall:1; + uint32_t SlaveAddrMatch:1; + uint32_t ArbitrationLost:1; + uint32_t INTReq:1; + uint32_t BusState:1; + uint32_t TRx:1; + uint32_t MasterSlave:1; + } Bit; + } I2C_State; + +#define I2C_CHANNEL_NUMBER 2U +#define IS_I2C_PERIPH(param) (((param) == TSB_I2C0) || \ + ((param) == TSB_I2C1)) + + + + +#define I2C_DATA_LEN_8 ((uint32_t)0x00000000) +#define I2C_DATA_LEN_1 ((uint32_t)0x00000001) +#define I2C_DATA_LEN_2 ((uint32_t)0x00000002) +#define I2C_DATA_LEN_3 ((uint32_t)0x00000003) +#define I2C_DATA_LEN_4 ((uint32_t)0x00000004) +#define I2C_DATA_LEN_5 ((uint32_t)0x00000005) +#define I2C_DATA_LEN_6 ((uint32_t)0x00000006) +#define I2C_DATA_LEN_7 ((uint32_t)0x00000007) + +#define I2C_SCK_CLK_DIV_20 ((uint32_t)0x00000000) +#define I2C_SCK_CLK_DIV_24 ((uint32_t)0x00000001) +#define I2C_SCK_CLK_DIV_32 ((uint32_t)0x00000002) +#define I2C_SCK_CLK_DIV_48 ((uint32_t)0x00000003) +#define I2C_SCK_CLK_DIV_80 ((uint32_t)0x00000004) +#define I2C_SCK_CLK_DIV_144 ((uint32_t)0x00000005) +#define I2C_SCK_CLK_DIV_272 ((uint32_t)0x00000006) +#define I2C_SCK_CLK_DIV_528 ((uint32_t)0x00000007) +#define IS_I2C_SCK_CLK_DIV(param) (((param) == I2C_SCK_CLK_DIV_20) || \ + ((param) == I2C_SCK_CLK_DIV_24) || \ + ((param) == I2C_SCK_CLK_DIV_32) || \ + ((param) == I2C_SCK_CLK_DIV_48) || \ + ((param) == I2C_SCK_CLK_DIV_80) || \ + ((param) == I2C_SCK_CLK_DIV_144) || \ + ((param) == I2C_SCK_CLK_DIV_272) || \ + ((param) == I2C_SCK_CLK_DIV_528)) + +#define I2C_PRESCALER_DIV_1 ((uint32_t)0x00000001) +#define I2C_PRESCALER_DIV_2 ((uint32_t)0x00000002) +#define I2C_PRESCALER_DIV_3 ((uint32_t)0x00000003) +#define I2C_PRESCALER_DIV_4 ((uint32_t)0x00000004) +#define I2C_PRESCALER_DIV_5 ((uint32_t)0x00000005) +#define I2C_PRESCALER_DIV_6 ((uint32_t)0x00000006) +#define I2C_PRESCALER_DIV_7 ((uint32_t)0x00000007) +#define I2C_PRESCALER_DIV_8 ((uint32_t)0x00000008) +#define I2C_PRESCALER_DIV_9 ((uint32_t)0x00000009) +#define I2C_PRESCALER_DIV_10 ((uint32_t)0x0000000A) +#define I2C_PRESCALER_DIV_11 ((uint32_t)0x0000000B) +#define I2C_PRESCALER_DIV_12 ((uint32_t)0x0000000C) +#define I2C_PRESCALER_DIV_13 ((uint32_t)0x0000000D) +#define I2C_PRESCALER_DIV_14 ((uint32_t)0x0000000E) +#define I2C_PRESCALER_DIV_15 ((uint32_t)0x0000000F) +#define I2C_PRESCALER_DIV_16 ((uint32_t)0x00000010) +#define I2C_PRESCALER_DIV_17 ((uint32_t)0x00000011) +#define I2C_PRESCALER_DIV_18 ((uint32_t)0x00000012) +#define I2C_PRESCALER_DIV_19 ((uint32_t)0x00000013) +#define I2C_PRESCALER_DIV_20 ((uint32_t)0x00000014) +#define I2C_PRESCALER_DIV_21 ((uint32_t)0x00000015) +#define I2C_PRESCALER_DIV_22 ((uint32_t)0x00000016) +#define I2C_PRESCALER_DIV_23 ((uint32_t)0x00000017) +#define I2C_PRESCALER_DIV_24 ((uint32_t)0x00000018) +#define I2C_PRESCALER_DIV_25 ((uint32_t)0x00000019) +#define I2C_PRESCALER_DIV_26 ((uint32_t)0x0000001A) +#define I2C_PRESCALER_DIV_27 ((uint32_t)0x0000001B) +#define I2C_PRESCALER_DIV_28 ((uint32_t)0x0000001C) +#define I2C_PRESCALER_DIV_29 ((uint32_t)0x0000001D) +#define I2C_PRESCALER_DIV_30 ((uint32_t)0x0000001E) +#define I2C_PRESCALER_DIV_31 ((uint32_t)0x0000001F) +#define I2C_PRESCALER_DIV_32 ((uint32_t)0x00000020) + +/** @} */ +/* End of group I2C_Exported_Types */ + +/** @defgroup I2C_Exported_Macros + * @{ + */ +#define IS_PRESCALER_CLK_VALID(param1, param2) (((param1) >= I2C_PRESCALER_DIV_1) && \ + ((param1) <= I2C_PRESCALER_DIV_32) && \ + (((param2) / (param1)) > 666666U) && \ + (((param2) / (param1)) < 20000000U)) + +#define IS_I2C_DATA(param) ((param) <= (uint32_t)0x000000FF) + +#define IS_I2C_BIT_NUM(param) ((param) <= (uint32_t)0x00000007) + +#define IS_I2C_ADDR(param) (((param) < (uint32_t)0x000000FF) && \ + (!((param) & (uint32_t)0x00000001))) + +/** @} */ +/* End of group I2C_Exported_Macros */ + +/** @defgroup I2C_Exported_FunctionPrototypes + * @{ + */ + + void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct); + void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum); + void I2C_SWReset(TSB_I2C_TypeDef * I2Cx); + void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx); + void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx); + void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx); + I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx); + void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data); + uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx); + void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx); + void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock); + + void I2C_SetSELPINCDReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + void I2C_SetDMARI2CTXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + void I2C_SetDMARI2CRXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + void I2C_SetINTNACKReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + void I2C_SetINTI2CBFReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + void I2C_SetINTI2CALReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + void I2C_SetINTI2CReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + + FunctionalState I2C_GetNACKStatus(TSB_I2C_TypeDef * I2Cx); + FunctionalState I2C_GetINTI2CBFStatus(TSB_I2C_TypeDef * I2Cx); + FunctionalState I2C_GetINTI2CALStatus(TSB_I2C_TypeDef * I2Cx); + FunctionalState I2C_GetINTI2CStatus(TSB_I2C_TypeDef * I2Cx); + + void I2C_ClearINTNACKOutput(TSB_I2C_TypeDef * I2Cx); + void I2C_ClearINTI2CBFOutput(TSB_I2C_TypeDef * I2Cx); + void I2C_ClearINTI2CALOutput(TSB_I2C_TypeDef * I2Cx); + void I2C_ClearINTI2COutput(TSB_I2C_TypeDef * I2Cx); + + void I2C_SetGeneralCall(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + void I2C_DetectRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + FunctionalState I2C_GetRepeatStartDetState(TSB_I2C_TypeDef * I2Cx); + void I2C_SelectACKoutput(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + void I2C_SetRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState); + WorkState I2C_GetRepeatStartState(TSB_I2C_TypeDef * I2Cx); + + +/** @} */ +/* End of group I2C_Exported_FunctionPrototypes */ + +/** @} */ +/* End of group I2C */ + +/** @} */ +/* End of group TX00_Periph_Driver */ +#endif /* defined(__TMPM066_I2C_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TMPM066_I2C_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifao.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifao.h new file mode 100644 index 0000000000..15512150b3 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifao.h @@ -0,0 +1,100 @@ +/** + ******************************************************************************* + * @file tmpm066_intifao.h + * @brief This file provides all the functions prototypes for INTIFAO driver. + * @version V2.0.2.1 + * @date 2015/10/19 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TMPM066_INTIFAO_H +#define __TMPM066_INTIFAO_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "TMPM066.h" +#include "tx00_common.h" + +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @addtogroup INTIFAO + * @{ + */ + +/** @addtogroup INTIFAO_Exported_types + * @{ + */ + typedef struct { + uint32_t All; + } INTIFAO_IntFlag1Factor; + + typedef enum { + INTIFAO_INT_SRC_0 = 0U, + INTIFAO_INT_SRC_1 = 1U, + INTIFAO_INT_SRC_2 = 2U, + INTIFAO_INT_SRC_3 = 3U, + INTIFAO_INT_SRC_4 = 4U, + INTIFAO_INT_SRC_5 = 5U, + INTIFAO_INT_SRC_I2CS = 6U, + INTIFAO_INT_SRC_USBWKUP = 7U + } INTIFAO_INTSrc; + +#define IS_INTIFAO_INT_SRC(param) (((param) == INTIFAO_INT_SRC_0) || \ + ((param) == INTIFAO_INT_SRC_1) || \ + ((param) == INTIFAO_INT_SRC_2) || \ + ((param) == INTIFAO_INT_SRC_3) || \ + ((param) == INTIFAO_INT_SRC_4) || \ + ((param) == INTIFAO_INT_SRC_5) || \ + ((param) == INTIFAO_INT_SRC_I2CS) || \ + ((param) == INTIFAO_INT_SRC_USBWKUP)) + + typedef enum { + INTIFAO_INT_ACTIVE_STATE_L = 0x0U, + INTIFAO_INT_ACTIVE_STATE_H = 0x1U, + INTIFAO_INT_ACTIVE_STATE_FALLING = 0x2U, + INTIFAO_INT_ACTIVE_STATE_RISING = 0x3U, + INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES = 0x4U, + INTIFAO_INT_ACTIVE_STATE_INVALID = 0x5U + } INTIFAO_INTActiveState; +#define IS_INTIFAO_INT_ACTIVE_STATE(param) (((param) == INTIFAO_INT_ACTIVE_STATE_L) || \ + ((param) == INTIFAO_INT_ACTIVE_STATE_H) || \ + ((param) == INTIFAO_INT_ACTIVE_STATE_FALLING) || \ + ((param) == INTIFAO_INT_ACTIVE_STATE_RISING) || \ + ((param) == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) + +#define IS_INTIFAO_INT_I2CS_USBWKUP_ACTIVE_STATE(param) ((param) == INTIFAO_INT_ACTIVE_STATE_RISING) + +/** @} */ +/* End of group INTIFAO_Exported_types */ + +/** @defgroup INTIFAO_Exported_FunctionPrototypes + * @{ + */ + void INTIFAO_SetSTBYReleaseINTSrc(INTIFAO_INTSrc INTSource, + INTIFAO_INTActiveState ActiveState, FunctionalState NewState); + INTIFAO_INTActiveState INTIFAO_GetSTBYReleaseINTState(INTIFAO_INTSrc INTSource); + void INTIFAO_ClearINTReq(INTIFAO_INTSrc INTSource); + + INTIFAO_IntFlag1Factor INTIFAO_GetIntFlag1(void); + +/** @} */ +/* End of group INTIFAO_Exported_FunctionPrototype */ + +/** @} */ +/* End of group INTIFAO */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TMPM066_INTIFAO_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifsd.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifsd.h new file mode 100644 index 0000000000..456a51f54e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_intifsd.h @@ -0,0 +1,228 @@ +/** + ******************************************************************************* + * @file tmpm066_intifsd.h + * @brief This file provides all the functions prototypes for INTIFSD driver. + * @version V2.0.2.2 + * @date 2016/02/09 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TMPM066_INTIFSD_H +#define __TMPM066_INTIFSD_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "TMPM066.h" +#include "tx00_common.h" + +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @addtogroup INTIFSD + * @{ + */ + +/** @addtogroup INTIFSD_Exported_types + * @{ + */ + typedef union { + uint32_t All; + struct { + uint32_t Reserved1:16; + uint32_t DetectLowVoltage:1; + uint32_t DetectOverVoltage:1; + uint32_t WDT:1; + uint32_t Reserved2:13; + } Bit; + } INTIFSD_NMIFactor; + + typedef struct { + uint32_t All; + } INTIFSD_IntFlag3Factor; + + typedef struct { + uint32_t All; + } INTIFSD_IntFlag4Factor; + + typedef struct { + uint32_t All; + } INTIFSD_IntFlag5Factor; + + typedef enum { + INTIFSD_INT_SRC_LVD_PSFD = 0U, + INTIFSD_INT_SRC_LVD_PRD = 1U, + INTIFSD_INT_SRC_WDT = 2U, + INTIFSD_INT_SRC_DMAC_0 = 3U, + INTIFSD_INT_SRC_DMAC_1 = 4U, + INTIFSD_INT_SRC_DMAC_2 = 5U, + INTIFSD_INT_SRC_DMAC_3 = 6U, + INTIFSD_INT_SRC_DMAC_4 = 7U, + INTIFSD_INT_SRC_DMAC_5 = 8U, + INTIFSD_INT_SRC_DMAC_6 = 9U, + INTIFSD_INT_SRC_DMAC_7 = 10U, + INTIFSD_INT_SRC_DMAC_8 = 11U, + INTIFSD_INT_SRC_DMAC_9 = 12U, + INTIFSD_INT_SRC_DMAC_10 = 13U, + INTIFSD_INT_SRC_DMAC_11 = 14U, + INTIFSD_INT_SRC_DMAC_12 = 15U, + INTIFSD_INT_SRC_DMAC_13 = 16U, + INTIFSD_INT_SRC_DMAC_14 = 17U, + INTIFSD_INT_SRC_DMAC_15 = 18U, + INTIFSD_INT_SRC_DMAC_16 = 19U, + INTIFSD_INT_SRC_DMAC_17 = 20U, + INTIFSD_INT_SRC_DMAC_18 = 21U, + INTIFSD_INT_SRC_DMAC_19 = 22U, + INTIFSD_INT_SRC_DMAC_20 = 23U, + INTIFSD_INT_SRC_DMAC_21 = 24U, + INTIFSD_INT_SRC_DMAC_22 = 25U, + INTIFSD_INT_SRC_DMAC_23 = 26U, + INTIFSD_INT_SRC_DMAC_24 = 27U, + INTIFSD_INT_SRC_DMAC_25 = 28U, + INTIFSD_INT_SRC_DMAC_26 = 29U, + INTIFSD_INT_SRC_DMAC_27 = 30U, + INTIFSD_INT_SRC_DMAC_28 = 31U, + INTIFSD_INT_SRC_DMAC_29 = 32U, + INTIFSD_INT_SRC_DMAC_30 = 33U, + INTIFSD_INT_SRC_DMAC_31 = 34U, + INTIFSD_INT_SRC_DMAC_ERR = 35U, + INTIFSD_INT_SRC_TMRB_0_MDOVF = 36U, + INTIFSD_INT_SRC_TMRB_0_CAP0 = 37U, + INTIFSD_INT_SRC_TMRB_0_CAP1 = 38U, + INTIFSD_INT_SRC_TMRB_1_MDOVF = 39U, + INTIFSD_INT_SRC_TMRB_1_CAP0 = 40U, + INTIFSD_INT_SRC_TMRB_1_CAP1 = 41U, + INTIFSD_INT_SRC_TMRB_2_MDOVF = 42U, + INTIFSD_INT_SRC_TMRB_2_CAP0 = 43U, + INTIFSD_INT_SRC_TMRB_2_CAP1 = 44U, + INTIFSD_INT_SRC_TMRB_3_MDOVF = 45U, + INTIFSD_INT_SRC_TMRB_3_CAP0 = 46U, + INTIFSD_INT_SRC_TMRB_3_CAP1 = 47U, + INTIFSD_INT_SRC_TMRB_4_MDOVF = 48U, + INTIFSD_INT_SRC_TMRB_4_CAP0 = 49U, + INTIFSD_INT_SRC_TMRB_4_CAP1 = 50U, + INTIFSD_INT_SRC_TMRB_5_MDOVF = 51U, + INTIFSD_INT_SRC_TMRB_5_CAP0 = 52U, + INTIFSD_INT_SRC_TMRB_5_CAP1 = 53U, + INTIFSD_INT_SRC_TMRB_6_MDOVF = 54U, + INTIFSD_INT_SRC_TMRB_6_CAP0 = 55U, + INTIFSD_INT_SRC_TMRB_6_CAP1 = 56U, + INTIFSD_INT_SRC_TMRB_7_MDOVF = 57U, + INTIFSD_INT_SRC_TMRB_7_CAP0 = 58U, + INTIFSD_INT_SRC_TMRB_7_CAP1 = 59U, + INTIFSD_INT_SRC_TMRD_00 = 60U, + INTIFSD_INT_SRC_TMRD_01 = 61U, + INTIFSD_INT_SRC_TMRD_02 = 62U, + INTIFSD_INT_SRC_TMRD_03 = 63U, + INTIFSD_INT_SRC_TMRD_04 = 64U, + INTIFSD_INT_SRC_TMRD_10 = 65U, + INTIFSD_INT_SRC_TMRD_11 = 66U, + INTIFSD_INT_SRC_TMRD_12 = 67U, + INTIFSD_INT_SRC_TMRD_13 = 68U, + INTIFSD_INT_SRC_TMRD_14 = 69U + } INTIFSD_INTSrc; + +#define IS_INTIFSD_INT_SRC(param) (((param) == INTIFSD_INT_SRC_LVD_PSFD) || \ + ((param) == INTIFSD_INT_SRC_LVD_PRD) || \ + ((param) == INTIFSD_INT_SRC_WDT) || \ + ((param) == INTIFSD_INT_SRC_DMAC_0) || \ + ((param) == INTIFSD_INT_SRC_DMAC_1) || \ + ((param) == INTIFSD_INT_SRC_DMAC_2) || \ + ((param) == INTIFSD_INT_SRC_DMAC_3) || \ + ((param) == INTIFSD_INT_SRC_DMAC_4) || \ + ((param) == INTIFSD_INT_SRC_DMAC_5) || \ + ((param) == INTIFSD_INT_SRC_DMAC_6) || \ + ((param) == INTIFSD_INT_SRC_DMAC_7) || \ + ((param) == INTIFSD_INT_SRC_DMAC_8) || \ + ((param) == INTIFSD_INT_SRC_DMAC_9) || \ + ((param) == INTIFSD_INT_SRC_DMAC_10) || \ + ((param) == INTIFSD_INT_SRC_DMAC_11) || \ + ((param) == INTIFSD_INT_SRC_DMAC_12) || \ + ((param) == INTIFSD_INT_SRC_DMAC_13) || \ + ((param) == INTIFSD_INT_SRC_DMAC_14) || \ + ((param) == INTIFSD_INT_SRC_DMAC_15) || \ + ((param) == INTIFSD_INT_SRC_DMAC_16) || \ + ((param) == INTIFSD_INT_SRC_DMAC_17) || \ + ((param) == INTIFSD_INT_SRC_DMAC_18) || \ + ((param) == INTIFSD_INT_SRC_DMAC_19) || \ + ((param) == INTIFSD_INT_SRC_DMAC_20) || \ + ((param) == INTIFSD_INT_SRC_DMAC_21) || \ + ((param) == INTIFSD_INT_SRC_DMAC_22) || \ + ((param) == INTIFSD_INT_SRC_DMAC_23) || \ + ((param) == INTIFSD_INT_SRC_DMAC_24) || \ + ((param) == INTIFSD_INT_SRC_DMAC_25) || \ + ((param) == INTIFSD_INT_SRC_DMAC_26) || \ + ((param) == INTIFSD_INT_SRC_DMAC_27) || \ + ((param) == INTIFSD_INT_SRC_DMAC_28) || \ + ((param) == INTIFSD_INT_SRC_DMAC_29) || \ + ((param) == INTIFSD_INT_SRC_DMAC_30) || \ + ((param) == INTIFSD_INT_SRC_DMAC_31) || \ + ((param) == INTIFSD_INT_SRC_DMAC_ERR) || \ + ((param) == INTIFSD_INT_SRC_TMRB_0_MDOVF) || \ + ((param) == INTIFSD_INT_SRC_TMRB_0_CAP0) || \ + ((param) == INTIFSD_INT_SRC_TMRB_0_CAP1) || \ + ((param) == INTIFSD_INT_SRC_TMRB_1_MDOVF) || \ + ((param) == INTIFSD_INT_SRC_TMRB_1_CAP0) || \ + ((param) == INTIFSD_INT_SRC_TMRB_1_CAP1) || \ + ((param) == INTIFSD_INT_SRC_TMRB_2_MDOVF) || \ + ((param) == INTIFSD_INT_SRC_TMRB_2_CAP0) || \ + ((param) == INTIFSD_INT_SRC_TMRB_2_CAP1) || \ + ((param) == INTIFSD_INT_SRC_TMRB_3_MDOVF) || \ + ((param) == INTIFSD_INT_SRC_TMRB_3_CAP0) || \ + ((param) == INTIFSD_INT_SRC_TMRB_3_CAP1) || \ + ((param) == INTIFSD_INT_SRC_TMRB_4_MDOVF) || \ + ((param) == INTIFSD_INT_SRC_TMRB_4_CAP0) || \ + ((param) == INTIFSD_INT_SRC_TMRB_4_CAP1) || \ + ((param) == INTIFSD_INT_SRC_TMRB_5_MDOVF) || \ + ((param) == INTIFSD_INT_SRC_TMRB_5_CAP0) || \ + ((param) == INTIFSD_INT_SRC_TMRB_5_CAP1) || \ + ((param) == INTIFSD_INT_SRC_TMRB_6_MDOVF) || \ + ((param) == INTIFSD_INT_SRC_TMRB_6_CAP0) || \ + ((param) == INTIFSD_INT_SRC_TMRB_6_CAP1) || \ + ((param) == INTIFSD_INT_SRC_TMRB_7_MDOVF) || \ + ((param) == INTIFSD_INT_SRC_TMRB_7_CAP0) || \ + ((param) == INTIFSD_INT_SRC_TMRB_7_CAP1) || \ + ((param) == INTIFSD_INT_SRC_TMRD_00) || \ + ((param) == INTIFSD_INT_SRC_TMRD_01) || \ + ((param) == INTIFSD_INT_SRC_TMRD_02) || \ + ((param) == INTIFSD_INT_SRC_TMRD_03) || \ + ((param) == INTIFSD_INT_SRC_TMRD_04) || \ + ((param) == INTIFSD_INT_SRC_TMRD_10) || \ + ((param) == INTIFSD_INT_SRC_TMRD_11) || \ + ((param) == INTIFSD_INT_SRC_TMRD_12) || \ + ((param) == INTIFSD_INT_SRC_TMRD_13) || \ + ((param) == INTIFSD_INT_SRC_TMRD_14)) + +/** @} */ +/* End of group INTIFSD_Exported_types */ + +/** @defgroup INTIFSD_Exported_FunctionPrototypes + * @{ + */ + INTIFSD_NMIFactor INTIFSD_GetNMIFlag(void); + + void INTIFSD_ClearINTReq(INTIFSD_INTSrc INTSource); + + INTIFSD_IntFlag3Factor INTIFSD_GetIntFlag3(void); + INTIFSD_IntFlag4Factor INTIFSD_GetIntFlag4(void); + INTIFSD_IntFlag5Factor INTIFSD_GetIntFlag5(void); + +/** @} */ +/* End of group INTIFSD_Exported_FunctionPrototype */ + +/** @} */ +/* End of group INTIFSD */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TMPM066_INTIFSD_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmr16a.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmr16a.h new file mode 100644 index 0000000000..16d84c5375 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmr16a.h @@ -0,0 +1,108 @@ +/** + ******************************************************************************* + * @file tmpm066_tmr16a.h + * @brief This file provides all the functions prototypes for TMR16A driver. + * @version V2.0.2.1 + * @date 2015/10/09 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TMPM066_TMR16A_H +#define __TMPM066_TMR16A_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "TMPM066.h" +#include "tx00_common.h" + +#if defined(__TMPM066_TMR16A_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @addtogroup TMR16A + * @{ + */ + +/** @defgroup TMR16A_Exported_Types + * @{ + */ + +/** + * @brief TMR16A Flip-flop Structure definition + */ + + typedef struct { + uint32_t TMR16AFlipflopCtrl; /*!< Select TMR16A flip-flop output level */ + uint32_t TMR16AFlipflopReverseTrg; /*!< Specify TMR16A flip-flop reverse trigger */ + } TMR16A_FFOutputTypeDef; + +/** @} */ +/* End of group TMR16A_Exported_Types */ + +/** @defgroup TMR16A_Exported_Constants + * @{ + */ +#define IS_TMR16A_ALL_PERIPH(param) (((param) == TSB_T16A0) || \ + ((param) == TSB_T16A1)) + + + +#define TMR16A_SYSCK ((uint32_t)0x00000000) +#define TMR16A_PRCK ((uint32_t)0x00000001) +#define IS_TMR16A_SRCCLK(param) (((param) == TMR16A_SYSCK) || ((param) == TMR16A_PRCK)) + +#define TMR16A_RUN ((uint32_t)0x00000001) +#define TMR16A_STOP ((uint32_t)0x00000000) +#define IS_TMR16A_CMD(param) (((param) == TMR16A_RUN) || ((param) == TMR16A_STOP)) + +#define TMR16A_RUNNING_IN_CORE_HALT ((uint8_t)0x00) +#define TMR16A_STOP_IN_CORE_HALT ((uint8_t)0x02) +#define IS_TMR16A_CLK_IN_CORE_HALT(param) (((param) == TMR16A_RUNNING_IN_CORE_HALT) || \ + ((param) == TMR16A_STOP_IN_CORE_HALT)) + +#define TMR16A_FLIPFLOP_INVERT ((uint32_t)0x00000000) +#define TMR16A_FLIPFLOP_SET ((uint32_t)0x00000001) +#define TMR16A_FLIPFLOP_CLEAR ((uint32_t)0x00000002) +#define IS_TMR16A_FLIPFLOP_CTRL(param) (((param) == TMR16A_FLIPFLOP_INVERT) || \ + ((param) == TMR16A_FLIPFLOP_SET) || \ + ((param) == TMR16A_FLIPFLOP_CLEAR)) + +#define TMR16A_DISABLE_FLIPFLOP ((uint32_t)0x00000000) +#define TMR16A_FLIPFLOP_MATCH_CYCLE ((uint32_t)0x00000080) +#define IS_TMR16A_FLIPFLOP_TRG(param) (((param) == TMR16A_DISABLE_FLIPFLOP) || \ + ((param) == TMR16A_FLIPFLOP_MATCH_CYCLE)) + +#define IS_TMR16A_VALUE(param) ((param) <= 0x0000FFFFU) +#define IS_TMR16A_VALID_DUTY(param1, param2) ((param1) <= (param2)) + +/* End of group TMR16A_Exported_Constants */ +/** @defgroup TMR16A_Exported_FunctionPrototypes + * @{ + */ + void TMR16A_SetClkInCoreHalt(TSB_T16A_TypeDef * T16Ax, uint8_t ClkState); + void TMR16A_SetRunState(TSB_T16A_TypeDef * T16Ax, uint32_t Cmd); + void TMR16A_SetSrcClk(TSB_T16A_TypeDef * T16Ax, uint32_t SrcClk); + void TMR16A_SetFlipFlop(TSB_T16A_TypeDef * T16Ax, TMR16A_FFOutputTypeDef * FFStruct); + void TMR16A_ChangeCycle(TSB_T16A_TypeDef * T16Ax, uint32_t Cycle); + uint16_t TMR16A_GetCaptureValue(TSB_T16A_TypeDef * T16Ax); +/** @} */ +/* End of group TMR16A_Exported_FunctionPrototypes */ + +/** @} */ +/* End of group TMR16A */ + +/** @} */ +/* End of group TX00_Periph_Driver */ +#endif /* defined(__TMPM066_TMR16A_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TMPM066_TMR16A_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmrb.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmrb.h new file mode 100644 index 0000000000..5b1b9bdd12 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_tmrb.h @@ -0,0 +1,259 @@ +/** + ******************************************************************************* + * @file tmpm066_tmrb.h + * @brief This file provides all the functions prototypes for TMRB driver. + * @version V2.0.2.1 + * @date 2015/10/09 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TMPM066_TMRB_H +#define __TMPM066_TMRB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "TMPM066.h" +#include "tx00_common.h" + +#if defined(__TMPM066_TMRB_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ +/** @addtogroup TMRB + * @{ + */ +/** @defgroup TMRB_Exported_Types + * @{ + */ +/** + * @brief TMRB Init Structure definition + */ + typedef struct { + uint32_t Mode; /*!< Select TMRB mode between internal interval + timer mode and external event counter */ + uint32_t ClkDiv; /*!< Select the division for TMRB source clock */ + uint32_t TrailingTiming; /*!< Specify the trailingtiming value to be written + into TBnRG1 */ + uint32_t UpCntCtrl; /*!< Select up-counter work mode between + freerun and auto-reload */ + uint32_t LeadingTiming; /*!< Specify the leadingtiming value to be written + into TBnRG0 */ + } TMRB_InitTypeDef; + +/** + * @brief TMRB Flip-flop Structure definition + */ + + typedef struct { + uint32_t FlipflopCtrl; /*!< Select TMRB flip-flop output level */ + uint32_t FlipflopReverseTrg; /*!< Specify TMRB flip-flop reverse trigger */ + } TMRB_FFOutputTypeDef; + +/** + * @brief TMRB Interrupt factor Union definition + */ + typedef union { + uint32_t All; + struct { + uint32_t MatchLeadingTiming:1; + uint32_t MatchTrailingTiming:1; + uint32_t OverFlow:1; + uint32_t Reserverd:29; + } Bit; + } TMRB_INTFactor; + +/** + * @brief TMRB Interrupt masked Union definition + */ + typedef union { + uint32_t All; + struct { + uint32_t MatchLeadingTimingMask:1; + uint32_t MatchTrailingTimingMask:1; + uint32_t OverFlowMask:1; + uint32_t Reserverd:29; + } Bit; + } TMRB_INTMask; + +/** @} */ +/* End of group TMRB_Exported_Types */ + +/** @defgroup TMRB_Exported_Constants + * @{ + */ +#define IS_TMRB_ALL_PERIPH(param) (((param) == TSB_TB0) || \ + ((param) == TSB_TB1) || \ + ((param) == TSB_TB2) || \ + ((param) == TSB_TB3) || \ + ((param) == TSB_TB4) || \ + ((param) == TSB_TB5) || \ + ((param) == TSB_TB6) || \ + ((param) == TSB_TB7)) + +#define IS_TMRB_SYNC_PERIPH(param) (((param) == TSB_TB1) || \ + ((param) == TSB_TB2) || \ + ((param) == TSB_TB3) || \ + ((param) == TSB_TB5) || \ + ((param) == TSB_TB6) || \ + ((param) == TSB_TB7)) + +#define IS_TMRB_CAP_PERIPH(param) (((param) == TSB_TB0) || \ + ((param) == TSB_TB1) || \ + ((param) == TSB_TB2) || \ + ((param) == TSB_TB3) || \ + ((param) == TSB_TB4) || \ + ((param) == TSB_TB5)) + +#define TMRB_INTERVAL_TIMER ((uint32_t)0x00000001) +#define TMRB_EVENT_CNT ((uint32_t)0x00000000) +#define IS_TMRB_MODE(param) (((param) == TMRB_INTERVAL_TIMER) || \ + ((param) == TMRB_EVENT_CNT)) + +#define TMRB_CLK_DIV_2 ((uint32_t)0x00000001) +#define TMRB_CLK_DIV_8 ((uint32_t)0x00000002) +#define TMRB_CLK_DIV_32 ((uint32_t)0x00000003) +#define TMRB_CLK_DIV_64 ((uint32_t)0x00000004) +#define TMRB_CLK_DIV_128 ((uint32_t)0x00000005) +#define TMRB_CLK_DIV_256 ((uint32_t)0x00000006) +#define TMRB_CLK_DIV_512 ((uint32_t)0x00000007) +#define IS_TMRB_CLK_DIV(param) (((param) == TMRB_CLK_DIV_2) || \ + ((param) == TMRB_CLK_DIV_8) || \ + ((param) == TMRB_CLK_DIV_32) || \ + ((param) == TMRB_CLK_DIV_64) || \ + ((param) == TMRB_CLK_DIV_128) || \ + ((param) == TMRB_CLK_DIV_256) || \ + ((param) == TMRB_CLK_DIV_512)) + +#define TMRB_FREE_RUN ((uint32_t)0x00000000) +#define TMRB_AUTO_CLEAR ((uint32_t)0x00000008) +#define IS_TMRB_UC_CTRL(param) (((param) == TMRB_FREE_RUN) || \ + ((param) == TMRB_AUTO_CLEAR)) + +#define TMRB_FLIPFLOP_INVERT ((uint32_t)0x00000000) +#define TMRB_FLIPFLOP_SET ((uint32_t)0x00000001) +#define TMRB_FLIPFLOP_CLEAR ((uint32_t)0x00000002) +#define IS_TMRB_FLIPFLOP_CTRL(param) (((param) == TMRB_FLIPFLOP_INVERT) || \ + ((param) == TMRB_FLIPFLOP_SET) || \ + ((param) == TMRB_FLIPFLOP_CLEAR)) + +#define TMRB_DISABLE_FLIPFLOP ((uint32_t)0x00000000) +#define TMRB_FLIPFLOP_TAKE_CAPTURE_0 ((uint32_t)0x00000010) +#define TMRB_FLIPFLOP_TAKE_CAPTURE_1 ((uint32_t)0x00000020) +#define TMRB_FLIPFLOP_MATCH_TRAILINGTIMING ((uint32_t)0x00000008) +#define TMRB_FLIPFLOP_MATCH_LEADINGTIMING ((uint32_t)0x00000004) +#define IS_TMRB_FLIPFLOP_TRG(param) (((param) == TMRB_DISABLE_FLIPFLOP) || \ + ((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_0) || \ + ((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_1) || \ + ((param) == TMRB_FLIPFLOP_MATCH_TRAILINGTIMING) || \ + ((param) == TMRB_FLIPFLOP_MATCH_LEADINGTIMING) || \ + ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1)) || \ + ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \ + ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ + ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \ + ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ + ((param) == (TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ + ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING)) || \ + ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ + ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ + ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADINGTIMING)) || \ + ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING))) + +#define TMRB_DISABLE_CAPTURE ((uint32_t)0x00000000) +#define TMRB_CAPTURE_IN_RISING_FALLING ((uint32_t)0x00000020) +#define TMRB_CAPTURE_FF_RISING_FALLING ((uint32_t)0x00000030) +#define IS_TMRB_CAPTURE_TIMING(param) (((param) == TMRB_DISABLE_CAPTURE) || \ + ((param) == TMRB_CAPTURE_IN_RISING_FALLING) || \ + ((param) == TMRB_CAPTURE_FF_RISING_FALLING)) + +#define TMRB_RUN ((uint32_t)0x00000005) +#define TMRB_STOP ((uint32_t)0x00000000) +#define IS_TMRB_CMD(param) (((param) == TMRB_RUN) || ((param) == TMRB_STOP)) + +#define TMRB_REG_0 ((uint8_t)0x00) +#define TMRB_REG_1 ((uint8_t)0x01) +#define IS_TMRB_REG(param) (((param) == TMRB_REG_0) || ((param) == TMRB_REG_1)) + +#define TMRB_CAPTURE_0 ((uint8_t)0x00) +#define TMRB_CAPTURE_1 ((uint8_t)0x01) +#define IS_TMRB_CAPTURE_REG(param) (((param) == TMRB_CAPTURE_0) || ((param) == TMRB_CAPTURE_1)) + +#define TMRB_NO_INT_MASK ((uint32_t)0x00000000) +#define TMRB_MASK_MATCH_LEADINGTIMING_INT ((uint32_t)0x00000001) +#define TMRB_MASK_MATCH_TRAILINGTIMING_INT ((uint32_t)0x00000002) +#define TMRB_MASK_OVERFLOW_INT ((uint32_t)0x00000004) +#define IS_TMRB_INT_MASK(param) (((param) == TMRB_NO_INT_MASK) || \ + ((param) == TMRB_MASK_MATCH_LEADINGTIMING_INT) || \ + ((param) == TMRB_MASK_MATCH_TRAILINGTIMING_INT) || \ + ((param) == TMRB_MASK_OVERFLOW_INT) || \ + ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT)) || \ + ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)) || \ + ((param) == (TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT)) || \ + ((param) == (TMRB_MASK_MATCH_LEADINGTIMING_INT | TMRB_MASK_MATCH_TRAILINGTIMING_INT | TMRB_MASK_OVERFLOW_INT))) + +#define TMRB_TRG_EDGE_RISING ((uint8_t)0x00) +#define TMRB_TRG_EDGE_FALLING ((uint8_t)0x02) +#define IS_TMRB_TRG_EDGE(param) (((param) == TMRB_TRG_EDGE_RISING) || \ + ((param) == TMRB_TRG_EDGE_FALLING)) + +#define TMRB_RUNNING_IN_CORE_HALT ((uint8_t)0x00) +#define TMRB_STOP_IN_CORE_HALT ((uint8_t)0x40) +#define IS_TMRB_CLK_IN_CORE_HALT(param) (((param) == TMRB_RUNNING_IN_CORE_HALT) || \ + ((param) == TMRB_STOP_IN_CORE_HALT)) + +#define TMRB_NO_INT ((uint32_t)0x00000000) +#define IS_TMRB_VALUE(param) ((param) <= 0x0000FFFFU) +#define IS_VALID_LEADINGTIMING(param1, param2) ((param1) <= (param2)) + +#define TMRB_DMA_REQ_CMP_MATCH ((uint32_t)0x000000004) +#define TMRB_DMA_REQ_CAPTURE_1 ((uint32_t)0x000000002) +#define TMRB_DMA_REQ_CAPTURE_0 ((uint32_t)0x000000001) +#define IS_TMRB_DMA_REQ(param) (((param) == TMRB_DMA_REQ_CMP_MATCH) || \ + ((param) == TMRB_DMA_REQ_CAPTURE_1) || \ + ((param) == TMRB_DMA_REQ_CAPTURE_0)) + +/** @} */ +/* End of group TMRB_Exported_Constants */ +/** @defgroup TMRB_Exported_FunctionPrototypes + * @{ + */ + void TMRB_Enable(TSB_TB_TypeDef * TBx); + void TMRB_Disable(TSB_TB_TypeDef * TBx); + void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd); + void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct); + void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming); + void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct); + TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx); + TMRB_INTMask TMRB_GetINTMask(TSB_TB_TypeDef * TBx); + void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask); + void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming); + void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming); + uint16_t TMRB_GetRegisterValue(TSB_TB_TypeDef * TBx, uint8_t Reg); + uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx); + uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg); + void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx); + void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState); + void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState); + void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode); + void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState); + void TMRB_SetDMAReq(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t DMAReq); + +/** @} */ +/* End of group TMRB_Exported_FunctionPrototypes */ + +/** @} */ +/* End of group TMRB */ + +/** @} */ +/* End of group TX00_Periph_Driver */ +#endif /* defined(__TMPM066_TMRB_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TMPM066_TMRB_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h new file mode 100644 index 0000000000..8f5df68ef2 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h @@ -0,0 +1,381 @@ +/** + ******************************************************************************* + * @file tmpm066_uart.h + * @brief This file provides all the functions prototypes for UART driver. + * @version V2.0.2.1 + * @date 2015/09/10 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TMPM066_UART_H +#define __TMPM066_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "TMPM066.h" +#include "tx00_common.h" + +#if defined(__TMPM066_UART_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** @defgroup UART_Exported_Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ + + typedef struct { + uint32_t BaudRate; /*!< This member configures the UART communication + baud rate. */ + uint32_t DataBits; /*!< Specifies UART transfer mode, which could be + 7-bit mode, 8-bit mode or 9-bit mode. */ + uint32_t StopBits; /*!< Specifies the length of stop bit transmission + in UART mode. */ + uint32_t Parity; /*!< Specifies the parity mode which could be odd + parity, even parity or no parity. */ + uint32_t Mode; /*!< Enables or disables Receive, Transmit or + both. */ + uint32_t FlowCtrl; /*!< Specifies wether the hardware flow control + mode is enabled or disabled. */ + } UART_InitTypeDef; + + typedef struct { + uint32_t InputClkEdge; /*!< Select the input clock edge.on the SCLK output mode + this bit only can set to be 0(SIO_SCLKS_TXDF_RXDR) */ + uint32_t TIDLE; /*!< The status of TXDx pin after output of the + last bit */ + uint32_t TXDEMP; /*!< The status of TXDx pin when an under run error + is occured in SCLK input mode */ + uint32_t EHOLDTime; /*!< The last bit hold time of TXDx pin in SCLK + input mode */ + uint32_t IntervalTime; /*!< Setting interval time of continuous transmission which + could be None,1*SCLK,2*SCLK,4*SCLK,8*SCLK,16*SCLK,32*SCLK,64*SCLK. + this bit is valid only for SCLK output mode and double + buffer is enabled. */ + uint32_t TransferMode; /*!< Setting transfer mode which could be transfer prohibited, + half duplex(Receive),half duplex(Transmit) or full duplex. */ + uint32_t TransferDir; /*!< Setting transfer direction which could be + LSB_FRIST or MSB_FRIST. */ + uint32_t Mode; /*!< Enables or disables Receive, Transmit or both. */ + uint32_t DoubleBuffer; /*!< Double Buffer mode is enabled or disabled. */ + uint32_t BaudRateClock; /*!< Select the input clock for baud rate generator */ + uint32_t Divider; /*!< Division ratio "N" */ + } SIO_InitTypeDef; + +/** @} */ +/* End of group UART_Exported_Types */ + +/** @defgroup UART_Exported_Constants + * @{ + */ + +#define UART0 TSB_SC0 +#define UART1 TSB_SC1 + +#define IS_UART_PERIPH(param) (((param) == UART0) || \ + ((param) == UART1)) + +#define SIO0 TSB_SC0 +#define SIO1 TSB_SC1 + +#define IS_SIO_PERIPH(param) (((param) == SIO0) || \ + ((param) == SIO1)) + +#define UART_DATA_BITS_7 ((uint32_t)0x00000004) +#define UART_DATA_BITS_8 ((uint32_t)0x00000008) +#define UART_DATA_BITS_9 ((uint32_t)0x0000000C) +#define IS_UART_DATA_BITS(param) (((param) == UART_DATA_BITS_7) || \ + ((param) == UART_DATA_BITS_8) || \ + ((param) == UART_DATA_BITS_9)) + +#define UART_STOP_BITS_1 ((uint32_t)0x00000000) +#define UART_STOP_BITS_2 ((uint32_t)0x00000010) +#define IS_UART_STOPBITS(param) (((param) == UART_STOP_BITS_1) || \ + ((param) == UART_STOP_BITS_2)) + +#define UART_NO_PARITY ((uint32_t)0x00000000) +#define UART_EVEN_PARITY ((uint32_t)0x00000060) +#define UART_ODD_PARITY ((uint32_t)0x00000020) +#define IS_UART_PARITY(param) (((param) == UART_NO_PARITY) || \ + ((param) == UART_EVEN_PARITY) || \ + ((param) == UART_ODD_PARITY)) + +#define SIO_CLK_SCLKOUTPUT ((uint32_t)0x00000000) +#define SIO_CLK_SCLKINPUT ((uint32_t)0x00000001) +#define IS_SIO_CLK_SEL(param) (((param) == SIO_CLK_SCLKOUTPUT) || \ + ((param) == SIO_CLK_SCLKINPUT)) + +#define SIO_SCLKS_TXDF_RXDR ((uint32_t)0x00000000) +#define SIO_SCLKS_TXDR_RXDF ((uint32_t)0x00000002) +#define IS_SIO_SCLKS_TRXD(param) (((param) == SIO_SCLKS_TXDF_RXDR) || \ + ((param) == SIO_SCLKS_TXDR_RXDF)) + +#define SIO_TIDLE_LOW ((uint32_t)0x00000000) +#define SIO_TIDLE_HIGH ((uint32_t)0x00000100) +#define SIO_TIDLE_LAST ((uint32_t)0x00000200) +#define IS_SIO_TIDLE_LEVEL(param) (((param) == SIO_TIDLE_LOW) || \ + ((param) == SIO_TIDLE_HIGH) || \ + ((param) == SIO_TIDLE_LAST)) + +#define SIO_TXDEMP_LOW ((uint32_t)0x00000000) +#define SIO_TXDEMP_HIGH ((uint32_t)0x00000400) +#define IS_SIO_TXDEMP_LEVEL(param) (((param) == SIO_TXDEMP_LOW) || \ + ((param) == SIO_TXDEMP_HIGH)) + +#define SIO_EHOLD_FC_2 ((uint32_t)0x00000000) +#define SIO_EHOLD_FC_4 ((uint32_t)0x00001000) +#define SIO_EHOLD_FC_8 ((uint32_t)0x00002000) +#define SIO_EHOLD_FC_16 ((uint32_t)0x00003000) +#define SIO_EHOLD_FC_32 ((uint32_t)0x00004000) +#define SIO_EHOLD_FC_64 ((uint32_t)0x00005000) +#define SIO_EHOLD_FC_128 ((uint32_t)0x00006000) +#define IS_SIO_EHOLD_TIME(param) (((param) == SIO_EHOLD_FC_2) || \ + ((param) == SIO_EHOLD_FC_4) || \ + ((param) == SIO_EHOLD_FC_8) || \ + ((param) == SIO_EHOLD_FC_16) || \ + ((param) == SIO_EHOLD_FC_32) || \ + ((param) == SIO_EHOLD_FC_64) || \ + ((param) == SIO_EHOLD_FC_128)) + +#define SIO_SINT_TIME_NONE ((uint32_t)0x00000000) +#define SIO_SINT_TIME_SCLK_1 ((uint32_t)0x00000002) +#define SIO_SINT_TIME_SCLK_2 ((uint32_t)0x00000004) +#define SIO_SINT_TIME_SCLK_4 ((uint32_t)0x00000006) +#define SIO_SINT_TIME_SCLK_8 ((uint32_t)0x00000008) +#define SIO_SINT_TIME_SCLK_16 ((uint32_t)0x0000000A) +#define SIO_SINT_TIME_SCLK_32 ((uint32_t)0x0000000C) +#define SIO_SINT_TIME_SCLK_64 ((uint32_t)0x0000000E) +#define IS_SIO_SINT_TIME(param) (((param) == SIO_SINT_TIME_NONE) || \ + ((param) == SIO_SINT_TIME_SCLK_1) || \ + ((param) == SIO_SINT_TIME_SCLK_2) || \ + ((param) == SIO_SINT_TIME_SCLK_4) || \ + ((param) == SIO_SINT_TIME_SCLK_8) || \ + ((param) == SIO_SINT_TIME_SCLK_16) || \ + ((param) == SIO_SINT_TIME_SCLK_32) || \ + ((param) == SIO_SINT_TIME_SCLK_64)) + +#define SIO_TRANSFER_PROHIBIT ((uint32_t)0x00000000) +#define SIO_TRANSFER_HALFDPX_RX ((uint32_t)0x00000020) +#define SIO_TRANSFER_HALFDPX_TX ((uint32_t)0x00000040) +#define SIO_TRANSFER_FULLDPX ((uint32_t)0x00000060) +#define IS_SIO_TRANSFER_MODE(param) (((param) == SIO_TRANSFER_PROHIBIT) || \ + ((param) == SIO_TRANSFER_HALFDPX_RX) || \ + ((param) == SIO_TRANSFER_HALFDPX_TX) || \ + ((param) == SIO_TRANSFER_FULLDPX)) + +#define SIO_ENABLE_RX ((uint32_t)0x00000020) +#define SIO_ENABLE_TX ((uint32_t)0x00000010) +#define IS_SIO_MODE(param) (((param) == SIO_ENABLE_RX) || \ + ((param) == SIO_ENABLE_TX) || \ + ((param) == (SIO_ENABLE_TX | SIO_ENABLE_RX))) + +#define SIO_LSB_FRIST ((uint32_t)0x00000000) +#define SIO_MSB_FRIST ((uint32_t)0x00000008) +#define IS_SIO_TRANS_DIR(param) (((param) == SIO_LSB_FRIST) || \ + ((param) == SIO_MSB_FRIST)) + +#define SIO_WBUF_DISABLE ((uint32_t)0x00000000) +#define SIO_WBUF_ENABLE ((uint32_t)0x00000004) +#define IS_SIO_WBUF_SET(param) (((param) == SIO_WBUF_DISABLE) || \ + ((param) == SIO_WBUF_ENABLE)) + +#define SIO_BR_CLOCK_TS0 ((uint32_t)0x00000000) +#define SIO_BR_CLOCK_TS2 ((uint32_t)0x00000010) +#define SIO_BR_CLOCK_TS8 ((uint32_t)0x00000020) +#define SIO_BR_CLOCK_TS32 ((uint32_t)0x00000030) +#define IS_SIO_BR_CLOCK(param) (((param) == SIO_BR_CLOCK_TS0) || \ + ((param) == SIO_BR_CLOCK_TS2) || \ + ((param) == SIO_BR_CLOCK_TS8) || \ + ((param) == SIO_BR_CLOCK_TS32)) + +#define SIO_BR_DIVIDER_16 ((uint32_t)0x00000000) +#define SIO_BR_DIVIDER_1 ((uint32_t)0x00000001) +#define SIO_BR_DIVIDER_2 ((uint32_t)0x00000002) +#define SIO_BR_DIVIDER_3 ((uint32_t)0x00000003) +#define SIO_BR_DIVIDER_4 ((uint32_t)0x00000004) +#define SIO_BR_DIVIDER_5 ((uint32_t)0x00000005) +#define SIO_BR_DIVIDER_6 ((uint32_t)0x00000006) +#define SIO_BR_DIVIDER_7 ((uint32_t)0x00000007) +#define SIO_BR_DIVIDER_8 ((uint32_t)0x00000008) +#define SIO_BR_DIVIDER_9 ((uint32_t)0x00000009) +#define SIO_BR_DIVIDER_10 ((uint32_t)0x0000000A) +#define SIO_BR_DIVIDER_11 ((uint32_t)0x0000000B) +#define SIO_BR_DIVIDER_12 ((uint32_t)0x0000000C) +#define SIO_BR_DIVIDER_13 ((uint32_t)0x0000000D) +#define SIO_BR_DIVIDER_14 ((uint32_t)0x0000000E) +#define SIO_BR_DIVIDER_15 ((uint32_t)0x0000000F) +#define IS_SIO_BR_DIVIDER(param) ((param) <= SIO_BR_DIVIDER_15) + +#define IS_SIO_DATA(param) ((param) <= 0xFFU) + +#define SIO_CLOCK_T0_HALF ((uint32_t)0x00000000) +#define SIO_CLOCK_T0 ((uint32_t)0x00000002) +#define IS_SIO_CLOCK(param) (((param) == SIO_CLOCK_T0_HALF) || \ + ((param) == SIO_CLOCK_T0)) + +#define UART_ENABLE_RX ((uint32_t)0x00000020) +#define UART_ENABLE_TX ((uint32_t)0x00000010) +#define IS_UART_MODE(param) (((param) == UART_ENABLE_RX) || \ + ((param) == UART_ENABLE_TX) || \ + ((param) == (UART_ENABLE_TX | UART_ENABLE_RX))) + +#define UART_NONE_FLOW_CTRL ((uint32_t)0x00000000) +#define IS_UART_FLOW_CONTROL(param) ((param) == UART_NONE_FLOW_CTRL) + +#define IS_UART_BAUDRATE(param) (((param) >= 2400U) && \ + ((param) <= 115200U)) + +#define IS_UART_DATA(param) ((param) <= 0x01FFU) + +#define IS_UART_CLOCK(param) ((param) <= ((uint32_t)0x00000001)) +#define IS_UART_TIME(param) ((param) <= ((uint32_t)0x00000006)) +#define UART_RX ((uint32_t)0x00000020) +#define UART_TX ((uint32_t)0x00000040) +#define IS_UART_TRX(param) (((param) == UART_RX) || \ + ((param) == UART_TX)) + +#define UART_TRANSFER_PROHIBIT ((uint32_t)0x00000000) +#define UART_TRANSFER_HALFDPX_RX ((uint32_t)0x00000020) +#define UART_TRANSFER_HALFDPX_TX ((uint32_t)0x00000040) +#define UART_TRANSFER_FULLDPX ((uint32_t)0x00000060) +#define IS_UART_TRANSFER_MODE(param) (((param) == UART_TRANSFER_PROHIBIT) || \ + ((param) == UART_TRANSFER_HALFDPX_RX) || \ + ((param) == UART_TRANSFER_HALFDPX_TX) || \ + ((param) == UART_TRANSFER_FULLDPX)) + +#define UART_RXFIFO_MAX ((uint32_t)0x00000000) +#define UART_RXFIFO_RXFLEVEL ((uint32_t)0x00000010) +#define IS_UATR_RXFIFO_BYTESUSED(param) (((param) == UART_RXFIFO_MAX) || \ + ((param) == UART_RXFIFO_RXFLEVEL)) + +#define UART_RXFIFO4B_FLEVLE_4_2B ((uint32_t)0x00000000) +#define UART_RXFIFO4B_FLEVLE_1_1B ((uint32_t)0x00000001) +#define UART_RXFIFO4B_FLEVLE_2_2B ((uint32_t)0x00000002) +#define UART_RXFIFO4B_FLEVLE_3_1B ((uint32_t)0x00000003) +#define IS_UART_RXFIFO4B_FLEVLE(param) (((param) == UART_RXFIFO4B_FLEVLE_4_2B) || \ + ((param) == UART_RXFIFO4B_FLEVLE_1_1B) || \ + ((param) == UART_RXFIFO4B_FLEVLE_2_2B) || \ + ((param) == UART_RXFIFO4B_FLEVLE_3_1B)) + +#define UART_RFIS_REACH_FLEVEL ((uint32_t)0x00000000) +#define UART_RFIS_REACH_EXCEED_FLEVEL ((uint32_t)0x00000040) +#define IS_UATR_RFIS_CONDITION(param) (((param) == UART_RFIS_REACH_FLEVEL) || \ + ((param) == UART_RFIS_REACH_EXCEED_FLEVEL)) + +#define UART_TXFIFO4B_FLEVLE_0_0B ((uint32_t)0x00000000) +#define UART_TXFIFO4B_FLEVLE_1_1B ((uint32_t)0x00000001) +#define UART_TXFIFO4B_FLEVLE_2_0B ((uint32_t)0x00000002) +#define UART_TXFIFO4B_FLEVLE_3_1B ((uint32_t)0x00000003) +#define IS_UART_TXFIFO4B_FLEVLE(param) (((param) == UART_TXFIFO4B_FLEVLE_0_0B) || \ + ((param) == UART_TXFIFO4B_FLEVLE_1_1B) || \ + ((param) == UART_TXFIFO4B_FLEVLE_2_0B) || \ + ((param) == UART_TXFIFO4B_FLEVLE_3_1B)) + +#define UART_TRXFIFO_EMPTY ((uint32_t)0x00000000) +#define UART_TRXFIFO_1B ((uint32_t)0x00000001) +#define UART_TRXFIFO_2B ((uint32_t)0x00000002) +#define UART_TRXFIFO_3B ((uint32_t)0x00000003) +#define UART_TRXFIFO_4B ((uint32_t)0x00000004) + +#define UART_TFIS_REACH_FLEVEL ((uint32_t)0x00000000) +#define UART_TFIS_REACH_NOREACH_FLEVEL ((uint32_t)0x00000040) +#define IS_UATR_TFIS_CONDITION(param) (((param) == UART_TFIS_REACH_FLEVEL) || \ + ((param) == UART_TFIS_REACH_NOREACH_FLEVEL)) + +#define UART_RXFIFO_OVERRUN ((uint32_t)0x00000001) + +#define UART_TXFIFO_UNDERRUN ((uint32_t)0x00000001) + +/** @} */ +/* End of group UART_Exported_Constants */ + +/** @addtogroup UART_Exported_Types + * @{ + */ + typedef enum { + UART_NO_ERR = 0U, + UART_OVERRUN = 1U, + UART_PARITY_ERR = 2U, + UART_FRAMING_ERR = 3U, + UART_ERRS = 4U + } UART_Err; + + typedef enum { + UART_RXTXCNT_NONE = 0U, + UART_RXTXCNT_AUTODISABLE = 1U + } UART_TRxDisable; +#define IS_UATR_TRX_AUTODISABLE(param) (((param) == UART_RXTXCNT_NONE) || \ + ((param) == UART_RXTXCNT_AUTODISABLE)) + +/** @} */ +/* End of group UART_Exported_Types */ + +/** @defgroup UART_Exported_FunctionPrototypes + * @{ + */ + + void UART_Enable(TSB_SC_TypeDef * UARTx); + void UART_Disable(TSB_SC_TypeDef * UARTx); + WorkState UART_GetBufState(TSB_SC_TypeDef * UARTx, uint32_t Direction); + void UART_SWReset(TSB_SC_TypeDef * UARTx); + void UART_Init(TSB_SC_TypeDef * UARTx, UART_InitTypeDef * InitStruct); + uint32_t UART_GetRxData(TSB_SC_TypeDef * UARTx); + void UART_SetTxData(TSB_SC_TypeDef * UARTx, uint32_t Data); + void UART_DefaultConfig(TSB_SC_TypeDef * UARTx); + UART_Err UART_GetErrState(TSB_SC_TypeDef * UARTx); + void UART_SetWakeUpFunc(TSB_SC_TypeDef * UARTx, FunctionalState NewState); + void UART_SetIdleMode(TSB_SC_TypeDef * UARTx, FunctionalState NewState); + void UART_SetInputClock(TSB_SC_TypeDef * UARTx, uint32_t clock); + void UART_FIFOConfig(TSB_SC_TypeDef * UARTx, FunctionalState NewState); + void UART_SetFIFOTransferMode(TSB_SC_TypeDef * UARTx, uint32_t TransferMode); + void UART_TRxAutoDisable(TSB_SC_TypeDef * UARTx, UART_TRxDisable TRxAutoDisable); + void UART_RxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState); + void UART_TxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState); + void UART_RxFIFOByteSel(TSB_SC_TypeDef * UARTx, uint32_t BytesUsed); + void UART_RxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t RxFIFOLevel); + void UART_RxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t RxINTCondition); + void UART_RxFIFOClear(TSB_SC_TypeDef * UARTx); + void UART_TxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t TxFIFOLevel); + void UART_TxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t TxINTCondition); + void UART_TxFIFOClear(TSB_SC_TypeDef * UARTx); + void UART_TxBufferClear(TSB_SC_TypeDef * UARTx); + uint32_t UART_GetRxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx); + uint32_t UART_GetRxFIFOOverRunStatus(TSB_SC_TypeDef * UARTx); + uint32_t UART_GetTxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx); + uint32_t UART_GetTxFIFOUnderRunStatus(TSB_SC_TypeDef * UARTx); + void UART_SetRxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState); + void UART_SetTxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState); + void SIO_SetInputClock(TSB_SC_TypeDef * SIOx, uint32_t Clock); + void SIO_Enable(TSB_SC_TypeDef * SIOx); + void SIO_Disable(TSB_SC_TypeDef * SIOx); + uint8_t SIO_GetRxData(TSB_SC_TypeDef * SIOx); + void SIO_SetTxData(TSB_SC_TypeDef * SIOx, uint8_t Data); + void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitStruct); +/** @} */ +/* End of group UART_Exported_FunctionPrototypes */ + +/** @} */ +/* End of group UART */ + +/** @} */ +/* End of group TX00_Periph_Driver */ +#endif /* defined(__TMPM066_UART_H) */ + +#ifdef __cplusplus +} +#endif +#endif /* __TMPM066_UART_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tx00_common.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tx00_common.h new file mode 100644 index 0000000000..249356e870 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tx00_common.h @@ -0,0 +1,47 @@ +/** + ******************************************************************************* + * @file tx00_common.h + * @brief All common macro and definition for TX00 peripheral drivers + * @version V2.1.1 + * @date 2014/11/22 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TX00_COMMON_H +#define __TX00_COMMON_H + +typedef enum { + SUCCESS = 0U, + ERROR = 1U +} Result; + +typedef enum { + BUSY = 0U, + DONE = 1U +} WorkState; + +typedef enum { + DISABLE = 0U, + ENABLE = 1U +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +#define IS_POINTER_NOT_NULL(param) ((void*)(param) != (void*)0) + +/* + * To report the name of the source file and source line number where the + * assert_param error has occurred, "DEBUG" must be defined. And detailed + * definition of assert_failed() is needed to be implemented, which can be + * done, for example, in the main.c file. + */ +#ifdef DEBUG +void assert_failed(char *file, int32_t line); +#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) +#else +#define assert_param(expr) +#endif /* DEBUG */ + +#endif /* __TX00_COMMON_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_adc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_adc.c new file mode 100644 index 0000000000..862280b10c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_adc.c @@ -0,0 +1,571 @@ +/** + ******************************************************************************* + * @file tmpm066_adc.c + * @brief This file provides API functions for ADC driver. + * @version V2.0.2.1 + * @date 2015/10/09 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tmpm066_adc.h" + +#if defined(__TMPM066_ADC_H) + +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @defgroup ADC_Private_Defines + * @{ + */ +#define MOD0_ADS_SET ((uint32_t)0x00000001) +#define MOD0_SCAN_MASK ((uint32_t)0xFFFFFFFD) +#define MOD0_REPEAT_MASK ((uint32_t)0xFFFFFFFB) +#define MOD0_ITM_CLEAR ((uint32_t)0xFFFFFFE7) +#define MOD0_ADBFN_EOCFN_MASK ((uint32_t)0x000000C0) + +#define MOD1_ADCH_CLEAR ((uint32_t)0xFFFFFFF0) +#define MOD1_ADSCN_CLEAR ((uint32_t)0xFFFFFFCF) + +#define MOD2_HPADCH_CLEAR ((uint32_t)0xFFFFFFF0) +#define MOD2_HPADCE_SET ((uint32_t)0x00000020) +#define MOD2_ADBFHP_EOCFHP_MASK ((uint32_t)0x000000C0) + +#define MOD4_ADHTG_CLEAR ((uint32_t)0xFFFFFFEF) +#define MOD4_ADHTG_SET ((uint32_t)0x00000010) +#define MOD4_ADHS_CLEAR ((uint32_t)0xFFFFFFDF) +#define MOD4_HADHTG_CLEAR ((uint32_t)0xFFFFFFBF) +#define MOD4_HADHTG_SET ((uint32_t)0x00000040) +#define MOD4_HADHS_CLEAR ((uint32_t)0xFFFFFF7F) +#define MOD4_ADRST_MASK ((uint32_t)0xFFFFFFFC) +#define MOD4_ADRST_10 ((uint32_t)0x00000002) +#define MOD4_ADRST_01 ((uint32_t)0x00000001) + +#define ADC_CMPREG_CLEAR ((uint32_t)0xFFFFFF21) +#define ADC_REGx_ADRxRF_MASK ((uint32_t)0x00000001) +#define ADC_REGx_OVRx_MASK ((uint32_t)0x00000002) +#define ADC_REGx_RESULT_MASK ((uint32_t)0x0000FFC0) + +/** @} */ +/* End of group ADC_Private_Defines */ + +/** @defgroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** @} */ +/* End of group ADC_Private_FunctionPrototypes */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** @} */ +/* End of group ADC_Private_Functions */ + +/** @defgroup ADC_Exported_Functions + * @{ + */ + +/** + * @brief Software reset ADC function. + * @param None. + * @retval None. + */ +void ADC_SWReset(void) +{ + /* Set MOD4 = 0b10, 0b01 to reset ADC */ + TSB_AD->MOD4 = MOD4_ADRST_10; + TSB_AD->MOD4 = MOD4_ADRST_01; +} + +/** + * @brief Set A/D conversion time and prescaler output. + * @param Conversion_Time: Select the A/D conversion time. + * This parameter can be one of the following values: + * ADC_CONVERSION_35_CLOCK, ADC_CONVERSION_42_CLOCK, + * ADC_CONVERSION_68_CLOCK, ADC_CONVERSION_81_CLOCK + * @param Prescaler_Output: Select the A/D prescaler output. + * This parameter can be one of the following values: + * ADC_FC_DIVIDE_LEVEL_1, ADC_FC_DIVIDE_LEVEL_2, ADC_FC_DIVIDE_LEVEL_4, ADC_FC_DIVIDE_LEVEL_6, + * ADC_FC_DIVIDE_LEVEL_8, ADC_FC_DIVIDE_LEVEL_12, ADC_FC_DIVIDE_LEVEL_16, + * ADC_FC_DIVIDE_LEVEL_24, ADC_FC_DIVIDE_LEVEL_48, ADC_FC_DIVIDE_LEVEL_96. + * @retval None. + */ +void ADC_SetClk(uint32_t Conversion_Time, uint32_t Prescaler_Output) +{ + /* Check the parameters */ + assert_param(IS_ADC_CONVERSION_TIME(Conversion_Time)); + assert_param(IS_ADC_PRESCALER(Prescaler_Output)); + /* Set ADCLK */ + TSB_AD->CLK = Conversion_Time + Prescaler_Output; +} + +/** + * @brief Start ADC function. + * @param None. + * @retval None. + */ +void ADC_Start(void) +{ + /* Set ADMOD0 = 1 to start ADC */ + TSB_AD->MOD0 |= MOD0_ADS_SET; +} + +/** + * @brief Set ADC scan mode. + * @param NewState: Specify ADC scan mode. + * This parameter can be one of the following values: + * ENABLE or DISABLE. + * @retval None. + */ +void ADC_SetScanMode(FunctionalState NewState) +{ + /* read MOD0, and clear bit1 which is "ADMOD0" */ + uint32_t tmp = TSB_AD->MOD0 & MOD0_SCAN_MASK; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Set ADMOD0 */ + tmp |= (uint32_t) NewState << 1U; + TSB_AD->MOD0 = tmp; +} + +/** + * @brief Set ADC repeat mode. + * @param NewState: Specify ADC repeat mode. + * This parameter can be one of the following values: + * ENABLE or DISABLE. + * @retval None. + */ +void ADC_SetRepeatMode(FunctionalState NewState) +{ + /* read MOD0, and clear bit2 which is "ADMOD0" */ + uint32_t tmp = TSB_AD->MOD0 & MOD0_REPEAT_MASK; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Set ADMOD0 */ + tmp |= (uint32_t) NewState << 2U; + TSB_AD->MOD0 = tmp; +} + +/** + * @brief Set ADC interrupt mode in fixed channel repeat conversion mode. + * @param INTMode: Specify AD conversion interrupt mode. + * This parameter can be one of the following values: + * ADC_INT_SINGLE, ADC_INT_CONVERSION_4 or ADC_INT_CONVERSION_8. + * @retval None. + */ +void ADC_SetINTMode(uint32_t INTMode) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_ADC_INT_MODE(INTMode)); + /* Set ADMOD0 */ + tmp = TSB_AD->MOD0; + tmp &= MOD0_ITM_CLEAR; + tmp |= INTMode; + TSB_AD->MOD0 = tmp; +} + +/** + * @brief Read AD conversion completion/busy flag (normal and top-priority). + * @param None + * @retval A union with the state of AD conversion. + */ +ADC_State ADC_GetConvertState(void) +{ + uint32_t tmpmod0 = TSB_AD->MOD0; + uint32_t tmpmod2 = TSB_AD->MOD2; + ADC_State retval = { 0U }; + + tmpmod0 &= MOD0_ADBFN_EOCFN_MASK; + tmpmod2 &= MOD2_ADBFHP_EOCFHP_MASK; + retval.All = (tmpmod0 >> 6U) | (tmpmod2 >> 4U); + return retval; +} + +/** + * @brief Set ADC input channel. + * @param InputChannel: Analog input channel, it also related with other settings. + * This parameter can be one of the following values: + * ADC_AN_0, ADC_AN_1, ADC_AN_2, ADC_AN_3, + * ADC_AN_4, ADC_AN_5, ADC_AN_6, ADC_AN_7. + * @retval None. + */ +void ADC_SetInputChannel(uint32_t InputChannel) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_ADC_INPUT_CH(InputChannel)); + /* Set ADMOD1 */ + tmp = TSB_AD->MOD1; + tmp &= MOD1_ADCH_CLEAR; + tmp |= InputChannel; + TSB_AD->MOD1 = tmp; +} + +/** + * @brief Set ADC operation for scanning. + * @param ScanMode: Spcifiy operation mode for channel scanning. + * This parameter can be one of the following values: + * ADC_SCAN_4CH, ADC_SCAN_8CH. + * @retval None. + */ +void ADC_SetChannelScanMode(ADC_ChannelScanMode ScanMode) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_ADC_CH_SCAN_MODE(ScanMode)); + tmp = TSB_AD->MOD1; + tmp &= MOD1_ADSCN_CLEAR; + tmp |= ((uint32_t) ScanMode << 4U); + TSB_AD->MOD1 = tmp; +} + +/** + * @brief Set ADC in IDLE mode. + * @param NewState: Specify AD conversion in IDLE mode. + * This parameter can be one of the following values: + * ENABLE or DISABLE. + * @retval None. + */ +void ADC_SetIdleMode(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Set ADMOD1 */ + TSB_AD_MOD1_I2AD = NewState; +} + +/** + * @brief Set ADC VREF application. + * @param NewState: Specify ADC Vref application. + * This parameter can be one of the following values: + * ENABLE or DISABLE. + * @retval None. + */ +void ADC_SetVref(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Set ADMOD1 */ + TSB_AD_MOD1_VREFON = NewState; +} + +/** + * @brief Set ADC top-priority conversion analog input channel select. + * @param TopInputChannel: Analog input channel for top-priority conversion. + * This parameter can be one of the following values: + * ADC_AN_0, ADC_AN_1, ADC_AN_2, ADC_AN_3, + * ADC_AN_4, ADC_AN_5, ADC_AN_6, ADC_AN_7. + * @retval None. + */ +void ADC_SetInputChannelTop(uint32_t TopInputChannel) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_ADC_INPUT_CH(TopInputChannel)); + /* Set ADMOD2 */ + tmp = TSB_AD->MOD2; + tmp &= MOD2_HPADCH_CLEAR; + tmp |= TopInputChannel; + TSB_AD->MOD2 = tmp; +} + +/** + * @brief Start top-priority ADC. + * @param None. + * @retval None. + */ +void ADC_StartTopConvert(void) +{ + /* Set ADMOD2 = 1 to start top-priority ADC */ + TSB_AD->MOD2 |= MOD2_HPADCE_SET; +} + +/** + * @brief Set ADC monitor function. + * @param ADCMPx: Select ADC compare register. + * This parameter can be one of the following values: + * ADC_CMP_0 or ADC_CMP_1. + * @param NewState: Specify ADC monitor function. + * This parameter can be one of the following values: + * ENABLE or DISABLE. + * @retval None. + */ +void ADC_SetMonitor(uint8_t ADCMPx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_CMP(ADCMPx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (ADCMPx == ADC_CMP_0) { + /* Set ADMOD3 */ + TSB_AD_MOD3_ADOBSV0 = NewState; + } else { + /* Set ADMOD5 */ + TSB_AD_MOD5_ADOBSV1 = NewState; + } +} + +/** + * @brief Set ADC result output register or comparison register. + * @param ADCMPx: Select AD compare register. + * This parameter can be one of the following values: + * ADC_CMP_0 or ADC_CMP_1. + * @param ResultComparison: Set AD conversion result storage register or + * comparison register if ADC monitor function is enabled. + * This parameter can be one of the following values: + * ADC_REG_0, ADC_REG_1, ADC_REG_2, ADC_REG_3, + * ADC_REG_4, ADC_REG_5, ADC_REG_6, ADC_REG_7, ADC_REG_SP. + * @retval None. + */ +void ADC_SetResultCmpReg(uint8_t ADCMPx, uint32_t ResultComparison) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_ADC_CMP(ADCMPx)); + assert_param(IS_ADC_RESULT_CMP_REG(ResultComparison)); + if (ADC_CMP_0 == ADCMPx) { + /* Set ADMOD3 */ + tmp = TSB_AD->MOD3; + tmp &= ADC_CMPREG_CLEAR; + tmp |= ResultComparison; + TSB_AD->MOD3 = tmp; + } else { + /* Set ADMOD5 */ + tmp = TSB_AD->MOD5; + tmp &= ADC_CMPREG_CLEAR; + tmp |= ResultComparison; + TSB_AD->MOD5 = tmp; + } +} + +/** + * @brief Set ADC monitor interrupt. + * @param ADCMPx: Select ADC compare register. + * This parameter can be one of the following values: + * ADC_CMP_0 or ADC_CMP_1. + * @param NewState: Specify ADC monitor function. + * This parameter can be one of the following values: + * ADC_COMPARISON_SMALLER or ADC_COMPARISON_LARGER. + * @retval None. + */ +void ADC_SetMonitorINT(uint8_t ADCMPx, ADC_ComparisonState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_CMP(ADCMPx)); + assert_param(IS_ADC_CMP_INT(NewState)); + if (ADCMPx == ADC_CMP_0) { + /* Set ADMOD3 */ + TSB_AD_MOD3_ADOBIC0 = NewState; + } else { + /* Set ADMOD5 */ + TSB_AD_MOD5_ADOBIC1 = NewState; + } +} + +/** + * @brief Set hardware trigger for normal ADC function. + * @param HwSource: HW source for activating normal ADC. + * This parameter can be one of the following values: + * ADC_EXT_TRG or ADC_MATCH_TB_0. + * @param NewState: Specify HW for activating normal ADC. + * This parameter can be one of the following values: + * ENABLE or DISABLE. + * @retval None. + */ +void ADC_SetHWTrg(uint32_t HwSource, FunctionalState NewState) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_ADC_HW_TRG_NORMAL(HwSource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Set ADMOD4 */ + tmp = TSB_AD->MOD4; + tmp &= MOD4_ADHS_CLEAR; + tmp |= HwSource; + /* Set ADMOD4 */ + if (NewState == ENABLE) { + tmp |= MOD4_ADHTG_SET; + } else { + tmp &= MOD4_ADHTG_CLEAR; + } + TSB_AD->MOD4 = tmp & MOD4_ADRST_MASK; +} + +/** + * @brief Set hardware trigger for top-priority ADC function. + * @param HwSource: HW source for activating top-priority ADC. + * This parameter can be one of the following values: + * ADC_EXT_TRG or ADC_MATCH_TB_1. + * @param NewState: Specify HW for activating top-priority ADC. + * This parameter can be one of the following values: + * ENABLE or DISABLE. + * @retval None. + */ +void ADC_SetHWTrgTop(uint32_t HwSource, FunctionalState NewState) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_ADC_HW_TRG_TOP(HwSource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* Set ADMOD4 */ + tmp = TSB_AD->MOD4; + tmp &= MOD4_HADHS_CLEAR; + tmp |= HwSource; + /* Set ADMOD4 */ + if (NewState == ENABLE) { + tmp |= MOD4_HADHTG_SET; + } else { + tmp &= MOD4_HADHTG_CLEAR; + } + TSB_AD->MOD4 = tmp & MOD4_ADRST_MASK; +} + +/** + * @brief Read ADC result. + * @param ADREGx: ADC result register. + * This parameter can be one of the following values: + * ADC_REG_0, ADC_REG_1, ADC_REG_2, ADC_REG_3, + * ADC_REG_4, ADC_REG_5, ADC_REG_6, ADC_REG_7, ADC_REG_SP. + * @retval ADC result. + */ +ADC_ResultTypeDef ADC_GetConvertResult(uint32_t ADREGx) +{ + uint32_t tmp = 0U; + ADC_ResultTypeDef retval = { BUSY, ADC_NO_OVERRUN, 0U }; + + /* Check the parameters */ + assert_param(IS_ADC_REG(ADREGx)); + /* Read ADREGx to get ADC result */ + switch (ADREGx) { + case ADC_REG_0: + tmp = TSB_AD->REG0; + break; + case ADC_REG_1: + tmp = TSB_AD->REG1; + break; + case ADC_REG_2: + tmp = TSB_AD->REG2; + break; + case ADC_REG_3: + tmp = TSB_AD->REG3; + break; + case ADC_REG_4: + tmp = TSB_AD->REG4; + break; + case ADC_REG_5: + tmp = TSB_AD->REG5; + break; + case ADC_REG_6: + tmp = TSB_AD->REG6; + break; + case ADC_REG_7: + tmp = TSB_AD->REG7; + break; + case ADC_REG_SP: + tmp = TSB_AD->REGSP; + break; + default: /* Do nothing */ + break; + } + + if ((tmp & ADC_REGx_ADRxRF_MASK) == 0U) { + retval.ADCResultStored = BUSY; + } else { + retval.ADCResultStored = DONE; + } + + if ((tmp & ADC_REGx_OVRx_MASK) == 0U) { + retval.ADCOverrunState = ADC_NO_OVERRUN; + } else { + retval.ADCOverrunState = ADC_OVERRUN; + } + + retval.ADCResultValue = (uint16_t) tmp & ADC_REGx_RESULT_MASK; + retval.ADCResultValue >>= 6U; + + return retval; +} + +/** + * @brief Set ADC comparison register value. + * @param ADCMPx: Select AD compare register. + * This parameter can be one of the following values: + * ADC_CMP_0 or ADC_CMP_1. + * @param value: The value setting to ADC comparison register. + * @retval None. + */ +void ADC_SetCmpValue(uint8_t ADCMPx, uint16_t value) +{ + + /* Check the parameters */ + assert_param(IS_ADC_CMP(ADCMPx)); + assert_param(IS_ADC_CMP_VALUE(value)); + value <<= 6U; + if (ADCMPx == ADC_CMP_0) { + /* Set ADCMP0 */ + TSB_AD->CMP0 = value; + } else { + /* Set ADCMP1 */ + TSB_AD->CMP1 = value; + } +} + +/** + * @breif Enable or disable DMA activation factor for normal or top-priority AD conversion. + * @param DMAReq: Specify AD conversion DMA request type. + * This parameter can be one of the following values: + * ADC_DMA_REQ_NORMAL, ADC_DMA_REQ_TOP, + * ADC_DMA_REQ_MONITOR1, ADC_DMA_REQ_MONITOR2. + * @param NewState: Specify AD conversion DMA activation factor. + * This parameter can be one of the following values: + * ENABLE or DISABLE. + * @retval None. + */ +void ADC_SetDMAReq(uint8_t DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_DMA_REQ(DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + switch (DMAReq) { + case ADC_DMA_REQ_NORMAL: + TSB_AD_MOD6_ADDMA = NewState; + break; + case ADC_DMA_REQ_TOP: + TSB_AD_MOD6_ADHPDMA = NewState; + break; + case ADC_DMA_REQ_MONITOR1: + TSB_AD_MOD6_ADM0DMA = NewState; + break; + case ADC_DMA_REQ_MONITOR2: + TSB_AD_MOD6_ADM1DMA = NewState; + break; + default: + /* Do nothing */ + break; + } +} + +/** @} */ +/* End of group ADC_Exported_Functions */ + +/** @} */ +/* End of group ADC */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#endif /* defined(__TMPM066_ADC_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_cg.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_cg.c new file mode 100644 index 0000000000..7fd55c2b16 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_cg.c @@ -0,0 +1,698 @@ +/** + ******************************************************************************* + * @file tmpm066_cg.c + * @brief This file provides API functions for CG driver + * @version V2.0.2.1 + * @date 2015/09/22 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tmpm066_cg.h" + +#if defined(__TMPM066_CG_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @defgroup CG + * @brief CG driver modules + * @{ + */ + +/** @defgroup CG_Private_Defines + * @{ + */ + +#define CG_FC_GEAR_MASK ((uint32_t)0xFFFFFFF8) +#define CG_PRCK_MASK ((uint32_t)0xFFFFF0FF) +#define CG_WUP_TIME_MASK ((uint32_t)0x000FFFFF) +#define CG_WUP_COUNTER_MASK ((uint32_t)0xFFFFFEFF) +#define CG_WUP_START_SET ((uint32_t)0x00000001) +#define CG_WUEF_VALUE_MASK ((uint32_t)0x00000002) +#define CG_OSCCR_IOSCEN_SET ((uint32_t)0x00000001) +#define CG_OSCCR_IOSCEN_CLEAR ((uint32_t)0xFFFFFFFE) +#define CG_OSCCR_EOSCEN_EHOSC ((uint32_t)0x00000002) +#define CG_OSCCR_EOSCEN_NOUSE ((uint32_t)0xFFFFFFF9) +#define CG_OSCCR_EOSCEN_MASK ((uint32_t)0x00000006) +#define CG_OSCCR_EOSCEN_CLKIN ((uint32_t)0x00000004) +#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100) +#define CG_OSCCR_OSCSEL_CLEAR ((uint32_t)0xFFFFFEFF) +#define CG_OSCCR_OSCF_SET ((uint32_t)0x00000200) +#define CG_OSCCR_WUPT_MASK ((uint32_t)0x00FFFFFF) + +#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001) +#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE) +#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002) +#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD) +#define CG_PLL0SEL_PLLST_SET ((uint32_t)0x00000004) + +#define CG_PLL0SET_VALUE_MASK ((uint32_t)0xFFFFFF00) +#define CG_PLL0SEL_PLL0SET_MASK ((uint32_t)0xFFFFFF00) + +#define CG_STBY_MODE_MASK ((uint32_t)0xFFFFFFFC) +//#define CG_NMIFLG_MASK ((uint32_t)0xFFF8FFFF) + +#define FC_GEAR_1_1 ((uint32_t)0x00000000) +#define FC_GEAR_1_2 ((uint32_t)0x00000001) +#define FC_GEAR_1_4 ((uint32_t)0x00000002) +#define FC_GEAR_1_8 ((uint32_t)0x00000003) +#define FC_GEAR_1_16 ((uint32_t)0x00000004) + +#define WARM_UP_SEL_OSC_INT_HIGH ((uint32_t)0xFFFFFEFF) +#define WARM_UP_SEL_OSC_EXT_HIGH ((uint32_t)0x00000100) + +#define CG_PROTECT_SET ((uint32_t)0x000000C1) +#define CG_PROTECT_CLEAR ((uint32_t)0x0000003E) + +//#define INT_NCLR_PCLR_CLEAR ((uint8_t)0x01) +#define ADC_MOD0_BUSY_MASK ((uint32_t)0x00000040) +#define CG_SPCLKEN_ADCKEN_CLEAR ((uint32_t)0xFFFEFFFF) +#define CG_SPCLKEN_ADCKEN_SET ((uint32_t)0x00010000) + + +static CG_DivideLevel numToDivideLevel_table[CG_DIVIDE_MAX] = { + CG_DIVIDE_1, + CG_DIVIDE_2, + CG_DIVIDE_4, + CG_DIVIDE_8, + CG_DIVIDE_16, + CG_DIVIDE_32, + CG_DIVIDE_64, + CG_DIVIDE_128, + CG_DIVIDE_256, + CG_DIVIDE_512, + CG_DIVIDE_UNKNOWN, +}; + +static CG_STBYMode numToSTBYMode_table[CG_STBY_MODE_MAX] = { + CG_STBY_MODE_IDLE, + CG_STBY_MODE_STOP1, + CG_STBY_MODE_UNKNOWN, + CG_STBY_MODE_UNKNOWN, +}; + +/** @} */ +/* End of group CG_Private_Defines */ + +/** @defgroup CG_Private_FunctionPrototypes + * @{ + */ + +/** @} */ +/* End of group CG_Private_FunctionPrototypes */ + +/** @defgroup CG_Private_Functions + * @{ + */ + +/** @} */ +/* End of group CG_Private_Functions */ + +/** @defgroup CG_Exported_Functions + * @{ + */ + +/** + * @brief Set dividing level between clock fgear and fc. + * @param DivideFgearFromFc: Dividing level between fgear and fc. + * This parameter can be one of the following values: + * CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8, CG_DIVIDE_16 + * @retval None + */ +void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc) +{ + uint32_t gear = FC_GEAR_1_1; + uint32_t regval = TSB_CG->SYSCR; + + /* Check the parameters */ + assert_param(IS_CG_GEAR_DIVIDE_LEVEL(DivideFgearFromFc)); + + /* Set the value of fgear */ + switch (DivideFgearFromFc) { + case CG_DIVIDE_1: + gear = FC_GEAR_1_1; + break; + case CG_DIVIDE_2: + gear = FC_GEAR_1_2; + break; + case CG_DIVIDE_4: + gear = FC_GEAR_1_4; + break; + case CG_DIVIDE_8: + gear = FC_GEAR_1_8; + break; + case CG_DIVIDE_16: + gear = FC_GEAR_1_16; + break; + default: + /* Do nothing */ + break; + } + + regval &= CG_FC_GEAR_MASK; + regval |= gear; + TSB_CG->SYSCR = regval; +} + +/** + * @brief Get dividing level between clock fgear and fc. + * @param None + * @retval The dividing level between clock fgear and fc + * The value returned can be one of the following values: + * CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, + * CG_DIVIDE_8, CG_DIVIDE_16 or CG_DIVIDE_UNKNOWN + */ +CG_DivideLevel CG_GetFgearLevel(void) +{ + CG_DivideLevel DivideFgearFromFc = CG_DIVIDE_UNKNOWN; + uint32_t syscr = TSB_CG->SYSCR; + syscr &= (~CG_FC_GEAR_MASK); + + switch (syscr) { + case FC_GEAR_1_1: + DivideFgearFromFc = CG_DIVIDE_1; + break; + case FC_GEAR_1_2: + DivideFgearFromFc = CG_DIVIDE_2; + break; + case FC_GEAR_1_4: + DivideFgearFromFc = CG_DIVIDE_4; + break; + case FC_GEAR_1_8: + DivideFgearFromFc = CG_DIVIDE_8; + break; + case FC_GEAR_1_16: + DivideFgearFromFc = CG_DIVIDE_16; + break; + default: + /* Do nothing */ + break; + } + + return DivideFgearFromFc; +} + +/** + * @brief Set dividing level between clock PhiT0 and fc. + * @param DividePhiT0FromFc: Dividing level between PhiT0 and fc. + * This parameter can be one of the following values: + * CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8, + * CG_DIVIDE_16, CG_DIVIDE_32, CG_DIVIDE_64, CG_DIVIDE_128, + * CG_DIVIDE_256 or CG_DIVIDE_512 + * @retval Success or not + * The value returned can be one of the following values: + * SUCCESS or ERROR + */ +Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc) +{ + uint32_t fprclk = 0U; + Result retval = ERROR; + uint32_t regval = TSB_CG->SYSCR; + + /* Check the parameters */ + assert_param(IS_CG_DIVIDE_FC_LEVEL(DividePhiT0FromFc)); + + fprclk = (uint32_t) DividePhiT0FromFc; + regval &= CG_PRCK_MASK; + fprclk <<= 8U; + regval |= fprclk; + TSB_CG->SYSCR = regval; + retval = SUCCESS; + + return retval; +} + +/** + * @brief Get dividing level between clock phiT0 and fc. + * @param None + * @retval The divide level between clock phiT0 and fc + * The value returned can be one of the following values: + * CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8, + * CG_DIVIDE_16, CG_DIVIDE_32, CG_DIVIDE_64, CG_DIVIDE_128, + * CG_DIVIDE_256, CG_DIVIDE_512 or CG_DIVIDE_UNKNOWN + */ +CG_DivideLevel CG_GetPhiT0Level(void) +{ + uint32_t fprclk = 0U; + CG_DivideLevel phiT0Level = CG_DIVIDE_UNKNOWN; + + fprclk = TSB_CG->SYSCR & (~CG_PRCK_MASK); + fprclk = (uint32_t) (fprclk >> 8U); + + phiT0Level = numToDivideLevel_table[fprclk]; + + return phiT0Level; +} + +/** + * @brief Set the warm up time + * @param Source: Select source of warm-up counter + * This parameter can be one of the following values: + * CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WARM_UP_SRC_OSC_EXT_HIGH. + * Warm-up function is not necessary when using stable external clock. + * @param Time: Set number of warm-up cycle. It is between 0x0000 and 0xFFFF. + * @retval None + */ +void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time) +{ + uint32_t wupt = 0U; + uint32_t regval = TSB_CG->WUPHCR; + + /* Check the parameters */ + assert_param(IS_CG_WARM_UP_SRC(Source)); + + /* Get high 12 bits of warm-up time */ + wupt = (((uint32_t) Time) & CG_OSCCR_WUPT_MASK) << 20U; + + regval &= CG_WUP_TIME_MASK; + regval &= CG_WUP_COUNTER_MASK; + + switch (Source) { + case CG_WARM_UP_SRC_OSC_INT_HIGH: + regval |= wupt; + regval &= WARM_UP_SEL_OSC_INT_HIGH; + break; + case CG_WARM_UP_SRC_OSC_EXT_HIGH: + regval |= wupt; + regval |= WARM_UP_SEL_OSC_EXT_HIGH; + break; + default: + /* Do nothing */ + break; + } + + TSB_CG->WUPHCR = regval; +} + +/** + * @brief Start operation of warm up timer for oscillator. + * @param None + * @retval None + */ +void CG_StartWarmUp(void) +{ + uint32_t regval = TSB_CG->WUPHCR; + regval |= CG_WUP_START_SET; + TSB_CG->WUPHCR = regval; +} + +/** + * @brief Check whether warm up is completed or not. + * @param None + * @retval The state of warm-up + * The value returned can be one of the following values: + * DONE or BUSY + */ +WorkState CG_GetWarmUpState(void) +{ + WorkState state = BUSY; + uint32_t wuef = 0U; + uint32_t regval = TSB_CG->WUPHCR; + + wuef = regval & CG_WUEF_VALUE_MASK; + if (wuef == 0U) { + state = DONE; + } else { + /* Do nothing */ + } + + return state; +} + +/** + * @brief Set PLL multiplying value + * @param NewValue: PLL multiplying value + * This parameter can be one of the following values: + * CG_8M_MUL_12_FPLL, CG_10M_MUL_8_FPLL, CG_12M_MUL_8_FPLL, + * CG_16M_MUL_6_FPLL. + * @retval Success or not + * The value returned can be one of the following values: + * SUCCESS or ERROR + */ +Result CG_SetFPLLValue(uint32_t NewValue) +{ + Result retval = SUCCESS; + + /* read PLL0SEL and clear PLL0SET(bit14:0) */ + uint32_t tmp = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0SET_MASK; + + /* Check the parameters */ + assert_param(IS_CG_FPLL_VALUE(NewValue)); + + /* Don't use the PLL when internal high-speed oscillator (IHOSC) is used as system clock */ + /* When PLL is on, don't change the PLL setting value */ + if (CG_FOSC_OSC_INT == CG_GetFoscSrc()) { + retval = ERROR; + } else if (ENABLE == CG_GetPLLState()) { + retval = ERROR; + } else { + tmp |= NewValue; + TSB_CG->PLL0SEL = tmp; + } + + return retval; +} + +/** + * @brief Get the value of PLL setting + * @param None + * @retval Get the value of PLL setting. + * CG_8M_MUL_12_FPLL, CG_10M_MUL_8_FPLL, CG_12M_MUL_8_FPLL, + * CG_16M_MUL_6_FPLL. + */ +uint32_t CG_GetFPLLValue(void) +{ + uint32_t PLL0SEL = TSB_CG->PLL0SEL & CG_PLL0SET_VALUE_MASK; + + return PLL0SEL; +} + +/** + * @brief Enable PLL or disable it. + * @param NewState: New state of PLL + * This parameter can be one of the following values: + * DISABLE or ENABLE + * @retval Success or not + * The value returned can be one of the following values: + * SUCCESS or ERROR + */ +Result CG_SetPLL(FunctionalState NewState) +{ + Result retval = ERROR; + uint32_t regval = TSB_CG->PLL0SEL; + CG_FcSrc fcsrc = CG_FC_SRC_FPLL; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + regval |= CG_PLL0SEL_PLL0ON_SET; + retval = SUCCESS; + } else { + fcsrc = CG_GetFcSrc(); + if (fcsrc == CG_FC_SRC_FOSC) { /* PLL is not used. So it can be shut off */ + /* Set register to disable PLL */ + regval &= CG_PLL0SEL_PLL0ON_CLEAR; + retval = SUCCESS; + } else { /*fcsrc == CG_FC_SRC_FPLL. PLL is in use, so disabling it should be invalid */ + /* Do nothing */ + } + } + TSB_CG->PLL0SEL = regval; + return retval; +} + +/** + * @brief Get the status of PLL operation + * @param None + * @retval Run or stop + * The value returned can be one of the following values: + * ENABLE or DISABLE + */ +FunctionalState CG_GetPLLState(void) +{ + FunctionalState pllstate = DISABLE; + uint32_t regval = TSB_CG->PLL0SEL; + + regval &= CG_PLL0SEL_PLL0ON_SET; + if (regval == CG_PLL0SEL_PLL0ON_SET) { + pllstate = ENABLE; + } else { + /* Do nothing */ + } + + return pllstate; +} + + +/** + * @brief Set the source of high-speed oscillator (fosc) + * @param Source: Select clock source for fosc + * This parameter can be one of the following values: + * CG_FOSC_OSC_EXT , CG_FOSC_CLKIN_EXT or CG_FOSC_OSC_INT + * @retval None + */ +void CG_SetFoscSrc(CG_FoscSrc Source) +{ + /* Check the parameters */ + assert_param(IS_CG_FOSC_SRC(Source)); + + if (Source == CG_FOSC_OSC_INT) { + /*Selects internal high-speed oscillator */ + TSB_CG->OSCCR |= CG_OSCCR_IOSCEN_SET; + TSB_CG->OSCCR &= CG_OSCCR_OSCSEL_CLEAR; + } else { + /*Selects external high-speed oscillator */ + TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; + TSB_CG->OSCCR &= CG_OSCCR_IOSCEN_CLEAR | CG_OSCCR_EOSCEN_NOUSE; + if (Source == CG_FOSC_OSC_EXT) { + /*Selects external high-speed oscillator */ + TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_EHOSC; + } else { + /*Selects an external clock input */ + TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_CLKIN; + } + } +} + +/** + * @brief Get the source of high-speed oscillator (fosc) + * @param None + * @retval Source of fosc + * The value returned can be one of the following values: + * CG_FOSC_OSC_EXT , CG_FOSC_CLKIN_EXT or CG_FOSC_OSC_INT + */ +CG_FoscSrc CG_GetFoscSrc(void) +{ + uint32_t regval = TSB_CG->OSCCR; + uint32_t oscf = 0U; + uint32_t hoscon = 0U; + CG_FoscSrc fosc_src = CG_FOSC_CLKIN_EXT; + + oscf = regval & CG_OSCCR_OSCF_SET; + hoscon = regval & CG_OSCCR_EOSCEN_MASK; + if (oscf == 0U) { + fosc_src = CG_FOSC_OSC_INT; + } else { + if (hoscon == CG_OSCCR_EOSCEN_EHOSC) { + fosc_src = CG_FOSC_OSC_EXT; + } else { + /* Do nothing */ + } + } + + return fosc_src; +} + +/** + * @brief Set to the specified low-power mode + * @param Low power mode + * The value can be one of the following values: + * CG_STBY_MODE_STOP1, CG_STBY_MODE_IDLE. + * @retval None + */ +void CG_SetSTBYMode(CG_STBYMode Mode) +{ + uint32_t regval = TSB_CG->STBYCR; + + /* Check the parameter */ + assert_param(IS_CG_STBY_MODE(Mode)); + + regval &= CG_STBY_MODE_MASK; + regval |= (uint32_t) Mode; + + TSB_CG->STBYCR = regval; +} + +/** + * @brief Get the low-power consumption mode + * @param None + * @retval Low power mode + * The value returned can be one of the following values: + * CG_STBY_MODE_STOP1, CG_STBY_MODE_IDLE, CG_STBY_MODE_UNKNOWN. + */ +CG_STBYMode CG_GetSTBYMode(void) +{ + CG_STBYMode stby_mode = CG_STBY_MODE_UNKNOWN; + uint8_t regval = (uint8_t) (TSB_CG->STBYCR & (~CG_STBY_MODE_MASK)); + + stby_mode = numToSTBYMode_table[regval]; + + return stby_mode; +} + +/** + * @brief Set the source of fc + * @param Source: The source of fc + * This parameter can be one of the following values: + * CG_FC_SRC_FOSC or CG_FC_SRC_FPLL + * @retval None + */ +void CG_SetFcSrc(CG_FcSrc Source) +{ + uint32_t regval = TSB_CG->PLL0SEL; + + /* Check the parameters */ + assert_param(IS_CG_FC_SRC(Source)); + + if (Source == CG_FC_SRC_FOSC) { + regval &= CG_PLL0SEL_PLL0SEL_CLEAR; + } else { + regval |= CG_PLL0SEL_PLL0SEL_SET; + } + TSB_CG->PLL0SEL = regval; +} + +/** + * @brief Get the source of fc + * @param None + * @retval The source of fc + * The value returned can be one of the following values: + * CG_FC_SRC_FOSC or CG_FC_SRC_FPLL + */ +CG_FcSrc CG_GetFcSrc(void) +{ + uint32_t regval = TSB_CG->PLL0SEL; + CG_FcSrc fcsrc = CG_FC_SRC_FOSC; + + regval &= CG_PLL0SEL_PLLST_SET; + if (regval == CG_PLL0SEL_PLLST_SET) { + fcsrc = CG_FC_SRC_FPLL; + } else { + /* Do nothing */ + } + + return fcsrc; +} + +/** + * @brief Enable or disable to protect CG registers + * @param NewState: New state of the CG protect register + * This parameter can be one of the following values: + * DISABLE or ENABLE + * @retval None + */ +void CG_SetProtectCtrl(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + TSB_CG->PROTECT = CG_PROTECT_SET; + } else { + TSB_CG->PROTECT = CG_PROTECT_CLEAR; + } +} + +/** + * @brief Enable or disable supplying clock fsys to peripheries + * @param Periph: The target peripheral of CG supplies clock + * This parameter can be one of the following values or their combination: + * CG_FC_PERIPH_PORTH, CG_FC_PERIPH_PORTJ, CG_FC_PERIPH_TMRB0_3, + * CG_FC_PERIPH_TMRB4_6, CG_FC_PERIPH_TMR16A, CG_FC_PERIPH_I2C0, + * CG_FC_PERIPH_SIO0, CG_FC_PERIPH_TSPI, CG_FC_PERIPH_DMAC, + * CG_FC_PERIPH_ADC, CG_FC_PERIPH_USBD, CG_FC_PERIPH_TMRD, + * CG_FC_PERIPHA_ALL. + * @param NewState: New state of clock supply setting. + * This parameter can be one of the following values: + * DISABLE or ENABLE + * @retval None + */ +void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_CG_FC_PERIPHA(Periph)); + if (NewState == ENABLE) { /* write '1' to enable */ + TSB_CG->FSYSENA |= Periph; + } else { /* clear to '0' to disable */ + TSB_CG->FSYSENA &= ~Periph; + } +} + + /** + * @brief Enable or disable supplying clock fsys to peripheries + * @param Periph: The target peripheral of CG supplies clock + * This parameter can be one of the following values or their combination: + * CG_FC_PERIPH_TMRB7, CG_FC_PERIPH_SIO1, CG_FC_PERIPH_WDT, + * CG_FC_PERIPH_I2C1, CG_FC_PERIPHB_ALL. + * @param NewState: New state of clock supply setting. + * This parameter can be one of the following values: + * DISABLE or ENABLE + * @retval None + */ +void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_CG_FC_PERIPHB(Periph)); + if (NewState == ENABLE) { /* write '1' to enable */ + TSB_CG->FSYSENB |= Periph; + } else { /* clear to '0' to disable */ + TSB_CG->FSYSENB &= ~Periph; + } +} + + /** + * @brief Enable or disable supplying clock fsys to peripheries + * @param Periph: The target peripheral of CG supplies clock + * This parameter can be one of the following values or their combination: + * CG_FPLL_PERIPH_TMRD, CG_EHCLKSEL_8_24_48MHZ, CG_USBSEL_PLL_CLOCKIN, + * CG_FC_PERIPH_I2C1, CG_FC_PERIPHB_ALL. + * @param NewState: New state of clock supply setting. + * This parameter can be one of the following values: + * DISABLE or ENABLE + * @retval None + */ +void CG_SetFcOptional(uint32_t Periph, FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_CG_FPLL_OPTIONAL(Periph)); + if (NewState == ENABLE) { /* write '1' to enable */ + TSB_CG->EXTENDO0 |= Periph; + } else { /* clear to '0' to disable */ + TSB_CG->EXTENDO0 &= ~Periph; + } +} + +/** + * @brief Enable or disable supplying clock fsys for ADC. + * @param NewState: New state of clock fsys supply setting for ADC. + * This parameter can be one of the following values: + * ENABLE or DISABLE. + * @retval None. + */ +void CG_SetADCClkSupply(FunctionalState NewState) +{ + volatile uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Check ADC is not during conversion */ + do { + tmp = TSB_AD->MOD0 & ADC_MOD0_BUSY_MASK; + } + while (tmp); + + /* Set CGSPCLKEN */ + tmp = TSB_CG->SPCLKEN; + if (NewState == ENABLE) { + tmp |= CG_SPCLKEN_ADCKEN_SET; + } else { + tmp &= CG_SPCLKEN_ADCKEN_CLEAR; + } + TSB_CG->SPCLKEN = tmp; +} + +/** @} */ +/* End of group CG_Exported_Functions */ + +/** @} */ +/* End of group CG */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#endif /* defined(__TMPM066_CG_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_gpio.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_gpio.c new file mode 100644 index 0000000000..ab2ec589a6 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_gpio.c @@ -0,0 +1,696 @@ +/** + ******************************************************************************* + * @file tmpm066_gpio.c + * @brief This file provides API functions for GPIO driver. + * @version V2.0.2.1 + * @date 2015/09/08 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tmpm066_gpio.h" + +#if defined(__TMPM066_GPIO_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +#define GPIO_NUM (9U) /*total number of gpio */ +/** + * @brief the base address of GPIO port. + */ +const uint32_t GPIO_Base[GPIO_NUM] = { + TSB_PA_BASE, TSB_PB_BASE, TSB_PC_BASE, + TSB_PD_BASE, TSB_PE_BASE, TSB_PF_BASE, + TSB_PG_BASE, TSB_PH_BASE, TSB_PJ_BASE +}; + +/** + * @brief:Information of gpio port. + * Note: for bit0 to bit7 of each member below, its value '0' or '1' has the means: + * '0': that bit is not available + * '1': that bit is availabe + * For example, if DATA = 0x7F, it mean the bit0 to bit6 of DATA register are avaiable; +*/ +const GPIO_RegTypeDef GPIO_SFRs[GPIO_NUM] = { +/* DATA CR FR1 FR2 OD PUP PDN SEL IE */ +/* PA */ {0xFFU, 0xFFU, {0x80U, 0x00U}, 0xFFU, 0xFFU, 0xFFU, 0x00U, 0xFFU}, +/* PB */ {0x0FU, 0x0FU, {0x00U, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x00U, 0x0FU}, +/* PC */ {0x3FU, 0x3FU, {0x3FU, 0x00U}, 0x3FU, 0x3FU, 0x3FU, 0x03U, 0x3FU}, +/* PD */ {0x3FU, 0x3FU, {0x1FU, 0x0FU}, 0x3FU, 0x3FU, 0x3FU, 0x30U, 0x3FU}, +/* PE */ {0x3FU, 0x3FU, {0x3FU, 0x02U}, 0x3FU, 0x3FU, 0x3FU, 0x00U, 0x3FU}, +/* PF */ {0xFFU, 0xFFU, {0x3FU, 0x01U}, 0xFFU, 0xFFU, 0xFFU, 0x00U, 0xFFU}, +/* PG */ {0x03U, 0x03U, {0x03U, 0x00U}, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U}, +/* PH */ {0x0FU, 0x0FU, {0x0FU, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x00U, 0x0FU}, +/* PJ */ {0x0FU, 0x0FU, {0x03U, 0x00U}, 0x0FU, 0x0FU, 0x0FU, 0x0FU, 0x0FU} +}; + +/** @defgroup GPIO_Exported_Functions + * @{ + */ + +/** + * @brief Read GPIO Data register. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @retval Data:The value of DATA register. + */ +uint8_t GPIO_ReadData(GPIO_Port GPIO_x) +{ + uint8_t Data = 0U; + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + Data = (uint8_t) PORT->DATA; + return Data; +} + +/** + * @brief Read Bit of GPIO Data register. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7. + * @retval BitValue:The value of specified Bit. + * This parameter can be one of the following values: + * GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1 + */ +uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x) +{ + uint8_t Data = 0U; + uint8_t tmp = 0U; + uint8_t BitValue = 0U; + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_GPIO_BIT(Bit_x)); + assert_param(IS_GPIO_BIT_DATA(GPIO_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + Data = (uint8_t) PORT->DATA; + tmp = (uint8_t) (Data & Bit_x); + if (tmp) { + BitValue = GPIO_BIT_VALUE_1; + } else { + BitValue = GPIO_BIT_VALUE_0; + } + return (BitValue); + +} + +/** + * @brief Write specified value to GPIO DATA register. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Data: specified value will be written to GPIO DATA register. + * @retval None + */ +void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data) +{ + + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_GPIO_WRITE(GPIO_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + PORT->DATA = Data; + +} + +/** + * @brief Write to specified Bit of GPIO DATA register. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Bit_x: Select GPIO pin,which can set as output. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @param BitValue:The value of specified Bit. + * This parameter can be one of the following values: + * GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1 + * @retval None + */ +void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue) +{ + uint8_t tmp = 0U; + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_GPIO_BIT_VALUE(BitValue)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinCR; + } else { + /* Do nothing */ + } + /* Check the parameters */ + assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + tmp = GPIO_ReadData(GPIO_x); + if (BitValue) { + tmp |= Bit_x; + } else { + Bit_x = (~Bit_x); + tmp &= Bit_x; + } + PORT->DATA = tmp; +} + +/** + * @brief Initialize the specified GPIO pin. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @param GPIO_InitStruct: The structure containing basic GPIO configuration. + * @retval None + */ +void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct) +{ + uint8_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_POINTER_NOT_NULL(GPIO_InitStruct)); + assert_param(IS_GPIO_IO_MODE_STATE(GPIO_InitStruct->IOMode)); + assert_param(IS_GPIO_PULLUP_STATE(GPIO_InitStruct->PullUp)); + assert_param(IS_GPIO_PULLDOWN_STATE(GPIO_InitStruct->PullDown)); + assert_param(IS_GPIO_OPEN_DRAIN_STATE(GPIO_InitStruct->OpenDrain)); + + if ((GPIO_x == GPIO_PC) || (GPIO_x == GPIO_PD) || (GPIO_x == GPIO_PG)) { + assert_param(IS_GPIO_INPUT_VOLTAGE_STATE(GPIO_InitStruct->InputVoltage)); + } + tmp = GPIO_InitStruct->IOMode; + switch (tmp) { + case GPIO_INPUT_MODE: + GPIO_SetInput(GPIO_x, Bit_x); + break; + case GPIO_OUTPUT_MODE: + GPIO_SetOutput(GPIO_x, Bit_x); + break; + default: + /* Do nothing */ + break; + } + tmp = GPIO_InitStruct->PullUp; + switch (tmp) { + case GPIO_PULLUP_ENABLE: + GPIO_SetPullUp(GPIO_x, Bit_x, ENABLE); + break; + case GPIO_PULLUP_DISABLE: + GPIO_SetPullUp(GPIO_x, Bit_x, DISABLE); + break; + default: + /* Do nothing */ + break; + } + tmp = GPIO_InitStruct->PullDown; + switch (tmp) { + case GPIO_PULLDOWN_ENABLE: + GPIO_SetPullDown(GPIO_x, Bit_x, ENABLE); + break; + case GPIO_PULLDOWN_DISABLE: + GPIO_SetPullDown(GPIO_x, Bit_x, DISABLE); + break; + default: + /* Do nothing */ + break; + } + tmp = GPIO_InitStruct->OpenDrain; + switch (tmp) { + case GPIO_OPEN_DRAIN_ENABLE: + GPIO_SetOpenDrain(GPIO_x, Bit_x, ENABLE); + break; + case GPIO_OPEN_DRAIN_DISABLE: + GPIO_SetOpenDrain(GPIO_x, Bit_x, DISABLE); + break; + default: + /* Do nothing */ + break; + } + if ((GPIO_x == GPIO_PC) || (GPIO_x == GPIO_PD) || (GPIO_x == GPIO_PG)) { + tmp = GPIO_InitStruct->InputVoltage; + switch (tmp) { + case GPIO_INPUT_VOLTAGE_3V: + GPIO_SetInputVoltage(GPIO_x, Bit_x, GPIO_BIT_VALUE_0); + break; + case GPIO_INPUT_VOLTAGE_1V8: + GPIO_SetInputVoltage(GPIO_x, Bit_x, GPIO_BIT_VALUE_1); + break; + default: + /* Do nothing */ + break; + } + } +} + +/** + * @brief Set specified GPIO Pin as output port. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @retval None + */ +void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x) +{ + uint8_t tmp = 0U; + uint32_t i; + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinCR; + } else { + /* Do nothing */ + } + /* Check the parameters */ + assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + tmp = (~Bit_x); + for (i = 0U; i < FRMAX; i++) { + if (GPIO_SFRs[GPIO_x].PinFR[i]) { + PORT->FR[i] &= tmp; + } else { + /* Do nothing */ + } + } + if (GPIO_SFRs[GPIO_x].PinIE) { + PORT->IE &= tmp; + } else { + /* Do nothing */ + } + PORT->CR |= Bit_x; +} + +/** + * @brief Set specified GPIO Pin as input port. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @retval None + */ +void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x) +{ + uint8_t tmp = 0U; + uint32_t i; + TSB_Port_TypeDef *PORT = 0U; + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinIE; + } else { + /* Do nothing */ + } + /* Check the parameters */ + assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + tmp = (~Bit_x); + for (i = 0U; i < FRMAX; i++) { + if (GPIO_SFRs[GPIO_x].PinFR[i]) { + PORT->FR[i] &= tmp; + } else { + /* Do nothing */ + } + } + if (GPIO_SFRs[GPIO_x].PinCR) { + PORT->CR &= tmp; + } else { + /* Do nothing */ + } + PORT->IE |= Bit_x; + +} + +/** + * @brief Set or clear the bit setting in output control register. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @param NewState: The output state of the pin. + * This parameter can be one of the following values: + * ENABLE , DISABLE. + * @retval None + */ +void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState) +{ + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinCR; + } else { + /* Do nothing */ + } + /* Check the parameters */ + assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + if (NewState == ENABLE) { + PORT->CR |= Bit_x; + } else { + PORT->CR &= (~(uint32_t) Bit_x); + } + +} + +/** + * @brief Set or clear the bit setting in input control register. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @param NewState: The input state of the pin. + * This parameter can be one of the following values: + * ENABLE , DISABLE. + * @retval None + */ +void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState) +{ + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinIE; + } else { + /* Do nothing */ + } + + /* Check the parameters */ + assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x)); + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + + if (NewState == ENABLE) { + PORT->IE |= Bit_x; + } else { + PORT->IE &= (~(uint32_t) Bit_x); + } +} + +/** + * @brief Enable or Disable pull-up function of specified GPIO Pin. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @param NewState: New state of the Pull-Up function. + * This parameter can be one of the following values: + * ENABLE , DISABLE. + * @retval None + */ +void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState) +{ + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinPUP; + } else { + /* Do nothing */ + } + /* Check the parameters */ + assert_param(IS_GPIO_BIT_PUP(GPIO_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + + if (NewState == ENABLE) { + PORT->PUP |= Bit_x; + } else { + PORT->PUP &= (~(uint32_t) Bit_x); + } +} + +/** + * @brief Enable or Disable pull-down function of specified GPIO Pin. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @param NewState: New state of the Pull-Down function. + * This parameter can be one of the following values: + * ENABLE , DISABLE. + * @retval None + */ +void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState) +{ + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinPDN; + } else { + /* Do nothing */ + } + /* Check the parameters */ + assert_param(IS_GPIO_BIT_PDN(GPIO_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + + if (NewState == ENABLE) { + PORT->PDN |= Bit_x; + } else { + PORT->PDN &= (~(uint32_t) Bit_x); + } +} + +/** + * @brief Set specified GPIO Pin as open drain port or CMOS port. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @param NewState: New state of the Open Drian function. + * This parameter can be one of the following values: + * ENABLE , DISABLE. + * @retval None + */ +void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState) +{ + + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinOD; + } else { + /* Do nothing */ + } + /* Check the parameters */ + assert_param(IS_GPIO_BIT_OD(GPIO_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + + if (NewState == ENABLE) { + PORT->OD |= Bit_x; + } else { + PORT->OD &= (~(uint32_t) Bit_x); + } +} + +/** + * @brief Input voltage selection function of specified GPIO Pin. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PC, GPIO_PD, GPIO_PG. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @param BitValue:The value of specified Bit. + * This parameter can be one of the following values: + * GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1 + * @retval None + */ +void GPIO_SetInputVoltage(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue) +{ + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT_INPUT_VOLTAGE(GPIO_x)); + assert_param(IS_GPIO_BIT_VALUE(BitValue)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinSEL; + } else { + /* Do nothing */ + } + /* Check the parameters */ + assert_param(IS_GPIO_BIT_SEL(GPIO_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + + if (BitValue) { + PORT->SEL |= Bit_x; + } else { + PORT->SEL &= (~(uint8_t) Bit_x); + } +} + +/** + * @brief Enable specified GPIO Function register. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param FuncReg_x: Select Function register of GPIO. + * This parameter can be one of the following values: + * GPIO_FUNC_REG_1, GPIO_FUNC_REG_2. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @retval None + */ +void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x) +{ + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x]; + } else { + /* Do nothing */ + } + /* Check the parameters */ + assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + PORT->FR[FuncReg_x] |= Bit_x; +} + +/** + * @brief Disable specified GPIO Function register. + * @param GPIO_x: Select GPIO port. + * This parameter can be one of the following values: + * GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE, GPIO_PF, GPIO_PG, + * GPIO_PH, GPIO_PJ. + * @param FuncReg_x: Select Function register of GPIO. + * This parameter can be one of the following values: + * GPIO_FUNC_REG_1, GPIO_FUNC_REG_2. + * @param Bit_x: Select GPIO pin. + * This parameter can be one of the following values: + * GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3, + * GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL, + * or combination of the effective bits. + * @retval None + */ +void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x) +{ + TSB_Port_TypeDef *PORT = 0U; + + /* Check the parameters */ + assert_param(IS_GPIO_PORT(GPIO_x)); + assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x)); + + if (Bit_x == GPIO_BIT_ALL) { + Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x]; + } else { + /* Do nothing */ + } + /* Check the parameters */ + assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x)); + + PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x]; + + PORT->FR[FuncReg_x] &= (~(uint32_t) Bit_x); +} + +/** @} */ +/* End of group GPIO_Exported_Functions */ +/** @} */ +/* End of group GPIO */ +/** @} */ +/* End of group TX00_Periph_Driver */ +#endif /* (__TMPM066_GPIO_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c new file mode 100644 index 0000000000..2a90f4a30f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c @@ -0,0 +1,931 @@ +/** + ******************************************************************************* + * @file tmpm066_i2c.c + * @brief This file provides API functions for I2C driver. + * @version V2.0.2.1 + * @date 2015/09/10 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT. + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tmpm066_i2c.h" + +#if defined(__TMPM066_I2C_H) + +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @defgroup I2C_Private_Defines + * @{ + */ + +#define I2CCR1_BC_MASK ((uint32_t)0x0000001F) +#define I2CCR1_ACK_SET ((uint32_t)0x00000010) +#define I2CCR1_ACK_CLEAR ((uint32_t)0x000000EF) +#define I2CCR1_SCK_MASK ((uint32_t)0x000000F8) +#define I2CCR1_NOACK_MASK ((uint32_t)0x00000008) +#define I2CCR1_NOACK_ENABLE ((uint32_t)0x00000000) + +#define I2CCR2_PIN_SET ((uint32_t)0x00000010) +#define I2CCR2_I2CM_I2C ((uint32_t)0x00000008) +#define I2CCR2_SWRST_MASK ((uint32_t)0xFFFFFFFC) +#define I2CCR2_SWRST_CMD1 ((uint32_t)0x00000002) +#define I2CCR2_SWRST_CMD2 ((uint32_t)0x00000001) +#define I2CCR2_START_CONDITION ((uint32_t)0x000000F0) +#define I2CCR2_STOP_CONDITION ((uint32_t)0x000000D0) + + +#define I2CAR_SA_MASK ((uint32_t)0x000000FE) +#define I2CAR_ALS_SET ((uint32_t)0x00000001) +#define I2CAR_ALS_CLEAR ((uint32_t)0xFFFFFFFE) +#define I2C_DATA_MASK ((uint32_t)0x000000FF) + +#define I2CIE_IE_SELPINCD_SET ((uint32_t)0x00000040) +#define I2CIE_IE_DMARI2CTX_SET ((uint32_t)0x00000020) +#define I2CIE_IE_DMARI2CRX_SET ((uint32_t)0x00000010) +#define I2CIE_IE_INTNACK_SET ((uint32_t)0x00000008) +#define I2CIE_IE_INTI2CBF_SET ((uint32_t)0x00000004) +#define I2CIE_IE_INTI2CAL_SET ((uint32_t)0x00000002) +#define I2CIE_IE_INTI2C_SET ((uint32_t)0x00000001) + + +#define I2CIE_IE_SELPINCD_CLEAR ((uint32_t)0xFFFFFFBF) +#define I2CIE_IE_DMARI2CTX_CLEAR ((uint32_t)0xFFFFFFDF) +#define I2CIE_IE_DMARI2CRX_CLEAR ((uint32_t)0xFFFFFFEF) +#define I2CIE_IE_INTNACK_CLEAR ((uint32_t)0xFFFFFFF7) +#define I2CIE_IE_INTI2CBF_CLEAR ((uint32_t)0xFFFFFFFB) +#define I2CIE_IE_INTI2CAL_CLEAR ((uint32_t)0xFFFFFFFD) +#define I2CIE_IE_NTI2C_CLEAR ((uint32_t)0xFFFFFFFE) + +#define I2CST_NACK_MASK ((uint32_t)0x00000008) +#define I2CST_I2CBF_MASK ((uint32_t)0x00000004) +#define I2CST_I2CAL_MASK ((uint32_t)0x00000002) +#define I2CST_I2C_MASK ((uint32_t)0x00000001) + +#define I2CST_NACK_SET ((uint32_t)0x00000008) +#define I2CST_I2CBF_SET ((uint32_t)0x00000004) +#define I2CST_I2CAL_SET ((uint32_t)0x00000002) +#define I2CST_I2C_SET ((uint32_t)0x00000001) + +#define I2COP_GCDI_ON ((uint32_t)0x000000FB) +#define I2COP_GCDI_OFF ((uint32_t)0x00000004) + +#define I2COP_RSTA_SET ((uint32_t)0x00000008) +#define I2COP_RSTA_CLEAR ((uint32_t)0xFFFFFFF7) + +#define I2COP_MFACK_NACK ((uint32_t)0x00000001) +#define I2COP_MFACK_ACK ((uint32_t)0xFFFFFFFE) + +#define I2COP_SREN_SET ((uint32_t)0x00000002) +#define I2COP_SREN_CLEAR ((uint32_t)0xFFFFFFFD) + +#define I2CAR2_SA2EN_USE ((uint32_t)0x00000001) +#define I2CAR2_SA2EN_NOUSE ((uint32_t)0x000000FE) + +/** @} */ +/* End of group I2C_Private_Defines */ + +/** @defgroup I2C_Exported_Functions + * @{ + */ + +/** + * @brief Enable or disable the generation of ACK clock. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: New state of ACK clock. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmp = I2Cx->CR1; + if (NewState == ENABLE) { + /* Set I2CxCR1 to enable generation of ACK clock */ + tmp |= I2CCR1_ACK_SET; + } else { + /* Clear I2CxCR1 to disable generation of ACK clock */ + tmp &= I2CCR1_ACK_CLEAR; + } + I2Cx->CR1 = tmp; + +} + +/** + * @brief Initialize the specified I2C channel in I2C mode. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param InitI2CStruct: The structure containing I2C in I2C mode configuration. + * @retval None + */ +void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_POINTER_NOT_NULL(InitI2CStruct)); + assert_param(IS_I2C_ADDR(InitI2CStruct->I2CSelfAddr)); + assert_param(IS_I2C_BIT_NUM(InitI2CStruct->I2CDataLen)); + assert_param(IS_I2C_SCK_CLK_DIV(InitI2CStruct->I2CClkDiv)); + assert_param(IS_FUNCTIONAL_STATE(InitI2CStruct->I2CACKState)); + + /* Get the system clock frequency */ + SystemCoreClockUpdate(); + + /* Check the prescaler clock in the range between 50ns and 150ns */ + assert_param(IS_PRESCALER_CLK_VALID(InitI2CStruct->PrescalerClkDiv, SystemCoreClock)); + + /* Set prescaler clock */ + I2Cx->PRS = InitI2CStruct->PrescalerClkDiv % I2C_PRESCALER_DIV_32; + + /* Set selfaddress for I2Cx */ + I2Cx->AR = InitI2CStruct->I2CSelfAddr & I2CAR_SA_MASK; + + /* Set I2C bit length of transfer data */ + tmp = I2Cx->CR1 & I2CCR1_BC_MASK; + tmp |= (InitI2CStruct->I2CDataLen << 5U); + /* Set I2C clock division */ + tmp &= I2CCR1_SCK_MASK; + tmp |= InitI2CStruct->I2CClkDiv; + if (InitI2CStruct->I2CACKState) { + /* Set I2CxCR1 to enable generation of ACK clock */ + tmp |= I2CCR1_ACK_SET; + } else { + /* Clear I2CxCR1 to disable generation of ACK clock */ + tmp &= I2CCR1_ACK_CLEAR; + } + I2Cx->CR1 = tmp; + + /* Intilize I2C to I2C Slave-Rx mode */ + I2Cx->CR2 = I2CCR2_PIN_SET | I2CCR2_I2CM_I2C; +} + +/** + * @brief Specify the number of bits per transfer. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param I2CBitNum: Specify the number of bits. + * This parameter can be one of the following values: + * I2C_DATA_LEN_8, I2C_DATA_LEN_1,I2C_DATA_LEN_2,I2C_DATA_LEN_3, + * I2C_DATA_LEN_4, I2C_DATA_LEN_5,I2C_DATA_LEN_6 and I2C_DATA_LEN_7. + * @retval None + */ +void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_BIT_NUM(I2CBitNum)); + + /* Write number of bits per transfer into I2CxCR1 */ + tmp = I2Cx->CR1 & I2CCR1_BC_MASK; + tmp |= ((uint32_t) I2CBitNum << 5U); + + I2Cx->CR1 = tmp; +} + +/** + * @brief Reset the state of the specified I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval None + */ +void I2C_SWReset(TSB_I2C_TypeDef * I2Cx) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + tmp = I2Cx->CR2 & I2CCR2_SWRST_MASK; + I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD1; + I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD2; +} + +/** + * @brief Clear I2C interrupt request in I2C mode. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval None + */ +void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Set I2CxCR2 to clear request, and Set I2CxCR2 to enable I2C operation */ + tmp = I2Cx->SR; + tmp &= (uint32_t) 0x000000E0; + tmp |= (I2CCR2_PIN_SET | I2CCR2_I2CM_I2C); + I2Cx->CR2 = tmp; +} + +/** + * @brief Set I2c bus to Master mode and Generate start condition in I2C mode. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval None + */ +void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Set I2CxCR2, , and to generate start condition */ + I2Cx->CR2 = I2CCR2_START_CONDITION | I2CCR2_I2CM_I2C; +} + +/** + * @brief Set I2c bus to Master mode and Generate stop condition in I2C mode. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval None + */ +void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Set I2CxCR2, , and clear to generate stop condition */ + I2Cx->CR2 = I2CCR2_STOP_CONDITION | I2CCR2_I2CM_I2C; +} + +/** + * @brief Get the I2C channel state in I2C mode + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval The state of the I2C channel in I2C bus. + */ +I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx) +{ + I2C_State state; + state.All = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + state.All = I2Cx->SR; + state.All &= I2C_DATA_MASK; + return state; +} + + +/** + * @brief Set data to be sent and MCU starts transmission. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param Data: The data to be sent, max 0xFF. + * @retval None + */ +void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_I2C_DATA(Data)); + + /* Write data into I2CxDBR */ + I2Cx->DBR = Data; +} + +/** + * @brief Get data having been received. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval The data having been received + */ +uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx) +{ + uint32_t retval = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Save the received data */ + retval = I2Cx->DBR; + retval &= I2C_DATA_MASK; + + return retval; +} + +/** + * @brief Enable or disable I2C free data mode of the I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: New state of free data mode. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxI2CAR to use free data mode transfer in I2C mode */ + I2Cx->AR |= I2CAR_ALS_SET; + } else { + /* Clear I2CxI2CAR to not use free data mode transfer in I2C mode */ + I2Cx->AR &= I2CAR_ALS_CLEAR; + } +} + +/** + * @brief Get slave address match detection state. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval DISABLE or ENABLE. + */ +FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx) +{ + uint32_t tmp = 0U; + FunctionalState retval = DISABLE; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + tmp = I2Cx->CR1 & I2CCR1_NOACK_MASK; + if (tmp == I2CCR1_NOACK_ENABLE) { + /* the slave address match or general call detection are enabled. */ + retval = ENABLE; + } else { + /* Do nothing */ + } + return retval; +} + +/** + * @brief Set prescaler clock of the specified I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param PrescalerClock: the prescaler clock value. + * This parameter can be one of the following values: + * I2C_PRESCALER_DIV_1 to I2C_PRESCALER_DIV_32 + * @retval None + */ +void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Get the system clock frequency */ + SystemCoreClockUpdate(); + + /* Check the prescaler clock in the range between 50ns and 150ns */ + assert_param(IS_PRESCALER_CLK_VALID(PrescalerClock, SystemCoreClock)); + + /* Write prescaler clock into I2CxPRS */ + I2Cx->PRS = PrescalerClock % I2C_PRESCALER_DIV_32; +} + +/** + * @brief Enable or disable open condition of the pin. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: Specify I2C interrupt setting. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetSELPINCDReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxIE to enable pin open by reading DBR */ + I2Cx->IE |= I2CIE_IE_SELPINCD_SET; + } else { + /* Clear I2CxIE to disable pin open by reading DBR */ + I2Cx->IE &= I2CIE_IE_SELPINCD_CLEAR; + } +} + + +/** + * @brief Enable or disable a DMAC transmisstion request output. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: Specify I2C interrupt setting. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetDMARI2CTXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxIE to enable a DMAC transmisstion request */ + I2Cx->IE |= I2CIE_IE_DMARI2CTX_SET; + } else { + /* Clear I2CxIE to disable a DMAC transmisstion request */ + I2Cx->IE &= I2CIE_IE_DMARI2CTX_CLEAR; + } +} + +/** + * @brief Enable or disable a DMAC reception request output. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: Specify I2C interrupt setting. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetDMARI2CRXReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxIE to enable a DMAC reception request */ + I2Cx->IE |= I2CIE_IE_DMARI2CRX_SET; + } else { + /* Clear I2CxIE to disable a DMAC reception request */ + I2Cx->IE &= I2CIE_IE_DMARI2CRX_CLEAR; + } +} + +/** + * @brief Enable or disable NACK detection interrupt of the I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: Specify I2C interrupt setting. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetINTNACKReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxIE to enable NACK detection interrupt */ + I2Cx->IE |= I2CIE_IE_INTNACK_SET; + } else { + /* Clear I2CxIE to disable NACK detection interrupt */ + I2Cx->IE &= I2CIE_IE_INTNACK_CLEAR; + } +} + +/** + * @brief Enable or disable bus-free interrupt of the I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: Specify I2C interrupt setting. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetINTI2CBFReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxIE to enable bus-free interrupt */ + I2Cx->IE |= I2CIE_IE_INTI2CBF_SET; + } else { + /* Clear I2CxIE to disable bus-free interrupt */ + I2Cx->IE &= I2CIE_IE_INTI2CBF_CLEAR; + } +} + +/** + * @brief Enable or disable AL interrupt of the I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: Specify I2C interrupt setting. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetINTI2CALReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxIE to enable AL interrupt */ + I2Cx->IE |= I2CIE_IE_INTI2CAL_SET; + } else { + /* Clear I2CxIE to disable AL interrupt */ + I2Cx->IE &= I2CIE_IE_INTI2CAL_CLEAR; + } +} + +/** + * @brief Enable or disable I2C interrupt request of the I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: Specify I2C interrupt setting. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetINTI2CReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxIE to enable I2C interrupt request */ + I2Cx->IE |= I2CIE_IE_INTI2C_SET; + } else { + /* Clear I2CxIE to disable I2C interrupt request */ + I2Cx->IE &= I2CIE_IE_NTI2C_CLEAR; + } +} + +/** + * @brief Get NACK interrupt generation state. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval DISABLE or ENABLE. + */ +FunctionalState I2C_GetNACKStatus(TSB_I2C_TypeDef * I2Cx) +{ + uint32_t tmp = 0U; + FunctionalState retval = DISABLE; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + tmp = I2Cx->ST & I2CST_NACK_MASK; + if (tmp == I2CST_NACK_SET) { + /* the NACK interrupt has been generated */ + retval = ENABLE; + } else { + /* Do nothing */ + } + return retval; +} + +/** + * @brief Get I2CBF interrupt generation state. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval DISABLE or ENABLE. + */ +FunctionalState I2C_GetINTI2CBFStatus(TSB_I2C_TypeDef * I2Cx) +{ + uint32_t tmp = 0U; + FunctionalState retval = DISABLE; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + tmp = I2Cx->ST & I2CST_I2CBF_MASK; + if (tmp == I2CST_I2CBF_SET) { + /* the I2CBF interrupt has been generated */ + retval = ENABLE; + } else { + /* Do nothing */ + } + return retval; +} + +/** + * @brief Get I2CAL interrupt generation state. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval DISABLE or ENABLE. + */ +FunctionalState I2C_GetINTI2CALStatus(TSB_I2C_TypeDef * I2Cx) +{ + uint32_t tmp = 0U; + FunctionalState retval = DISABLE; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + tmp = I2Cx->ST & I2CST_I2CAL_MASK; + if (tmp == I2CST_I2CAL_SET) { + /* the I2CAL interrupt has been generated */ + retval = ENABLE; + } else { + /* Do nothing */ + } + return retval; +} + +/** + * @brief Get I2C interrupt generation state. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval DISABLE or ENABLE. + */ +FunctionalState I2C_GetINTI2CStatus(TSB_I2C_TypeDef * I2Cx) +{ + uint32_t tmp = 0U; + FunctionalState retval = DISABLE; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + tmp = I2Cx->ST & I2CST_I2C_MASK; + if (tmp == I2CST_I2C_SET) { + /* the I2C interrupt has been generated */ + retval = ENABLE; + } else { + /* Do nothing */ + } + return retval; +} + +/** + * @brief Clear the NACK interrupt output. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval None + */ +void I2C_ClearINTNACKOutput(TSB_I2C_TypeDef * I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Set I2CxST to clear the NACK interrupt output(INTI2Cx) */ + I2Cx->ST = I2CST_NACK_SET; +} + +/** + * @brief Clear the I2CBF interrupt output. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval None + */ +void I2C_ClearINTI2CBFOutput(TSB_I2C_TypeDef * I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Set I2CxST to clear the I2CBF interrupt output(INTI2Cx) */ + I2Cx->ST = I2CST_I2CBF_SET; +} + +/** + * @brief Clear the I2CAL interrupt output. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval None + */ +void I2C_ClearINTI2CALOutput(TSB_I2C_TypeDef * I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Set I2CxST to clear the I2CAL interrupt output(INTI2Cx) */ + I2Cx->ST = I2CST_I2CAL_SET; +} + +/** + * @brief Clear the I2C interrupt output. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval None + */ +void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + /* Set I2CxST to clear the I2C interrupt output(INTI2Cx) */ + I2Cx->ST = I2CST_I2C_SET; +} + +/** + * @brief Enable or disable general-call detection. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: New state of general call detection. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetGeneralCall(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmp = I2Cx->OP; + if (NewState == ENABLE) { + /* Clear I2CxOP, general-call detection is ON */ + tmp &= I2COP_GCDI_ON; + } else { + /* Set I2CxOP, general-call detection is OFF */ + tmp |= I2COP_GCDI_OFF; + } + I2Cx->OP = tmp; + +} + +/** + * @brief Detect or not a repeated start of the I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: New state of free data mode. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_DetectRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxI2COP to detect a repeated start */ + I2Cx->OP |= I2COP_RSTA_SET; + } else { + /* Clear I2CxI2COP to not detect a repeated start */ + I2Cx->OP &= I2COP_RSTA_CLEAR; + } +} + +/** + * @brief Get repeated start detection state. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval DISABLE or ENABLE. + */ +FunctionalState I2C_GetRepeatStartDetState(TSB_I2C_TypeDef * I2Cx) +{ + uint32_t tmp = 0U; + FunctionalState retval = DISABLE; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + tmp = I2Cx->OP & I2COP_RSTA_SET; + if (tmp == I2COP_RSTA_SET) { + /* the repeated start detection are enabled. */ + retval = ENABLE; + } else { + /* Do nothing */ + } + return retval; +} + +/** + * @brief Select an ACK output of the I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: New state of free data mode. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SelectACKoutput(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxI2COP to select NACK output */ + I2Cx->OP |= I2COP_MFACK_NACK; + } else { + /* Clear I2CxI2COP to select ACK output */ + I2Cx->OP &= I2COP_MFACK_ACK; + } +} + +/** + * @brief Enable or disable repeat start of the I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: New state of free data mode. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_SetRepeatStart(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxI2COP to enable repeat start output */ + I2Cx->OP |= I2COP_SREN_SET; + } else { + /* Clear I2CxI2COP to disable repeat start output */ + I2Cx->OP &= I2COP_SREN_CLEAR; + } +} + +/** + * @brief Get repeated start state. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @retval BUSY or DONE. + */ +WorkState I2C_GetRepeatStartState(TSB_I2C_TypeDef * I2Cx) +{ + uint32_t tmp = 0U; + WorkState retval = BUSY; + + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + + tmp = I2Cx->OP & I2COP_SREN_SET; + if (tmp == I2COP_SREN_SET) { + /* the repeated start detection has completed. */ + retval = DONE; + } else { + /* Do nothing */ + } + return retval; +} + +/** + * @brief Enable or disable using 2nd slave address of the I2C channel. + * @param I2Cx: Select the I2C channel. + * This parameter can be one of the following values: + * TSB_I2C0,TSB_I2C1 + * @param NewState: New state of free data mode. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void I2C_Set2ndSlaveAddress(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set I2CxI2CAR2 to using 2nd slave address */ + I2Cx->AR2 |= I2CAR2_SA2EN_USE; + } else { + /* Clear I2CxI2CAR2 to not using 2nd slave address */ + I2Cx->AR2 &= I2CAR2_SA2EN_NOUSE; + } +} + +/** @} */ +/* End of group I2C_Exported_Functions */ + +/** @} */ +/* End of group I2C */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#endif /* defined(__TMPM066_I2C_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifao.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifao.c new file mode 100644 index 0000000000..99199dcb12 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifao.c @@ -0,0 +1,284 @@ +/** + ******************************************************************************* + * @file tmpm066_intifao.c + * @brief This file provides API functions for INTIFAO driver + * @version V2.0.2.2 + * @date 2016/02/15 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tmpm066_intifao.h" + +#if defined(__TMPM066_INTIFAO_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @defgroup INTIFAO + * @brief INTIFAO driver modules + * @{ + */ + +/** @defgroup INTIFAO_Private_Defines + * @{ + */ +#define INT_NCLR_PCLR_CLEAR ((uint8_t)0x01) +#define INT_EN_MODE_MASK ((uint8_t)0xF0) +#define INT_MODE_MASK ((uint8_t)0x0E) + +#define INTIFAO_INTFLAG1_MASK ((uint32_t)0xFFFFFF00) + +/** @} */ +/* End of group INTIFAO_Private_Defines */ + +/** @defgroup INTIFAO_Private_FunctionPrototypes + * @{ + */ + +/** @} */ +/* End of group INTIFAO_Private_FunctionPrototypes */ + +/** @defgroup INTIFAO_Private_Functions + * @{ + */ + +/** @} */ +/* End of group INTIFAO_Private_Functions */ + +/** @defgroup INTIFAO_Exported_Functions + * @{ + */ + +/** + * @brief Setup the INT source for releasing low power mode. + * @param INTSource: Select the release INT source + * This parameter can be one of the following values: + * INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3, + * INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP. + * @param ActiveState: select the active state for release trigger + * This parameter can be one of the following values: + * INTIFAO_INT_ACTIVE_STATE_L, + * INTIFAO_INT_ACTIVE_STATE_H, + * INTIFAO_INT_ACTIVE_STATE_FALLING, + * INTIFAO_INT_ACTIVE_STATE_RISING or + * INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES. + * @param NewState: Enable or disable this release trigger + * This parameter can be one of the following values: + * DISABLE or ENABLE + * @retval None + */ +void INTIFAO_SetSTBYReleaseINTSrc(INTIFAO_INTSrc INTSource, + INTIFAO_INTActiveState ActiveState, FunctionalState NewState) +{ + uint8_t num = 0U; + uint32_t regval; + + /* Check the parameters */ + assert_param(IS_INTIFAO_INT_SRC(INTSource)); + assert_param(IS_INTIFAO_INT_ACTIVE_STATE(ActiveState)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if ((INTSource == INTIFAO_INT_SRC_I2CS) || (INTSource == INTIFAO_INT_SRC_USBWKUP)) { + assert_param(IS_INTIFAO_INT_I2CS_USBWKUP_ACTIVE_STATE(ActiveState)); + } else { + /* Do nothing */ + } + + num = (uint32_t) INTSource; + + switch (num) { + case 0U: /* STOP2INT_032 */ + regval = TSB_INTIFAO ->STOP2INT_032; + regval &= INT_EN_MODE_MASK; + regval |= NewState; + regval |= ActiveState << 1; + TSB_INTIFAO ->STOP2INT_032 = regval; + break; + case 1U: /* STOP2INT_033 */ + regval = TSB_INTIFAO ->STOP2INT_033; + regval &= INT_EN_MODE_MASK; + regval |= NewState; + regval |= ActiveState << 1; + TSB_INTIFAO ->STOP2INT_033 = regval; + break; + case 2U: /* STOP2INT_034 */ + regval = TSB_INTIFAO ->STOP2INT_034; + regval &= INT_EN_MODE_MASK; + regval |= NewState; + regval |= ActiveState << 1; + TSB_INTIFAO ->STOP2INT_034 = regval; + break; + case 3U: /* STOP2INT_035 */ + regval = TSB_INTIFAO ->STOP2INT_035; + regval &= INT_EN_MODE_MASK; + regval |= NewState; + regval |= ActiveState << 1; + TSB_INTIFAO ->STOP2INT_035 = regval; + break; + case 4U: /* STOP2INT_036 */ + regval = TSB_INTIFAO ->STOP2INT_036; + regval &= INT_EN_MODE_MASK; + regval |= NewState; + regval |= ActiveState << 1; + TSB_INTIFAO ->STOP2INT_036 = regval; + break; + case 5U: /* STOP2INT_037 */ + regval = TSB_INTIFAO ->STOP2INT_037; + regval &= INT_EN_MODE_MASK; + regval |= NewState; + regval |= ActiveState << 1; + TSB_INTIFAO ->STOP2INT_037 = regval; + break; + case 6U: /* STOP2INT_038 */ + regval = TSB_INTIFAO ->STOP2INT_038; + regval &= INT_EN_MODE_MASK; + regval |= NewState; + regval |= ActiveState << 1; + TSB_INTIFAO ->STOP2INT_038 = regval; + break; + case 7U: /* STOP2INT_039 */ + regval = TSB_INTIFAO ->STOP2INT_039; + regval &= INT_EN_MODE_MASK; + regval |= NewState; + regval |= ActiveState << 1; + TSB_INTIFAO ->STOP2INT_039 = regval; + break; + default: + /* Do nothing */ + break; + } +} + +/** + * @brief Get the active state of INT source standby clear request + * @param INTSource: Select the release INT source + * This parameter can be one of the following values: + * INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3, + * INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP. + * @retval Active state of the input INT + * The value returned can be one of the following values: + * INTIFAO_INT_ACTIVE_STATE_FALLING, INTIFAO_INT_ACTIVE_STATE_RISING, + * INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES or INTIFAO_INT_ACTIVE_STATE_INVALID + */ +INTIFAO_INTActiveState INTIFAO_GetSTBYReleaseINTState(INTIFAO_INTSrc INTSource) +{ + INTIFAO_INTActiveState int_active_state = INTIFAO_INT_ACTIVE_STATE_INVALID; + uint8_t tmp = 0U; + uint8_t num = 0U; + uint8_t regval[8] = {0}; + + /* Check the parameters */ + assert_param(IS_INTIFAO_INT_SRC(INTSource)); + + regval[0] = TSB_INTIFAO ->STOP2INT_032 & INT_MODE_MASK; + regval[1] = TSB_INTIFAO ->STOP2INT_033 & INT_MODE_MASK; + regval[2] = TSB_INTIFAO ->STOP2INT_034 & INT_MODE_MASK; + regval[3] = TSB_INTIFAO ->STOP2INT_035 & INT_MODE_MASK; + regval[4] = TSB_INTIFAO ->STOP2INT_036 & INT_MODE_MASK; + regval[5] = TSB_INTIFAO ->STOP2INT_037 & INT_MODE_MASK; + regval[6] = TSB_INTIFAO ->STOP2INT_038 & INT_MODE_MASK; + regval[7] = TSB_INTIFAO ->STOP2INT_039 & INT_MODE_MASK; + + num = (uint32_t) INTSource; + tmp = regval[num]; + tmp = tmp >>1; + switch (tmp) { + case 3U: + int_active_state = INTIFAO_INT_ACTIVE_STATE_RISING; + break; + case 2U: + int_active_state = INTIFAO_INT_ACTIVE_STATE_FALLING; + break; + case 4U: + int_active_state = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES; + break; + default: + /* Do nothing */ + break; + } + + return (int_active_state); +} + +/** + * @brief Clears the input INT request. + * @param INTSource: Select the release INT source + * This parameter can be one of the following values: + * INTIFAO_INT_SRC_0, INTIFAO_INT_SRC_1, INTIFAO_INT_SRC_2, INTIFAO_INT_SRC_3, + * INTIFAO_INT_SRC_4, INTIFAO_INT_SRC_5, INTIFAO_INT_SRC_I2CS, INTIFAO_INT_SRC_USBWKUP. + * @retval None + */ +void INTIFAO_ClearINTReq(INTIFAO_INTSrc INTSource) +{ + uint8_t num = 0U; + + /* Check the parameters */ + assert_param(IS_INTIFAO_INT_SRC(INTSource)); + + num = (uint32_t) INTSource; + switch (num) { + case 0U: /* STOP2INT_032 */ + TSB_INTIFAO_STOP2INT_032_INT032PCLR = INT_NCLR_PCLR_CLEAR; + TSB_INTIFAO_STOP2INT_032_INT032NCLR = INT_NCLR_PCLR_CLEAR; + break; + case 1U: /* STOP2INT_033 */ + TSB_INTIFAO_STOP2INT_033_INT033PCLR = INT_NCLR_PCLR_CLEAR; + TSB_INTIFAO_STOP2INT_033_INT033NCLR = INT_NCLR_PCLR_CLEAR; + break; + case 2U: /* STOP2INT_034 */ + TSB_INTIFAO_STOP2INT_034_INT034PCLR = INT_NCLR_PCLR_CLEAR; + TSB_INTIFAO_STOP2INT_034_INT034NCLR = INT_NCLR_PCLR_CLEAR; + break; + case 3U: /* STOP2INT_035 */ + TSB_INTIFAO_STOP2INT_035_INT035PCLR = INT_NCLR_PCLR_CLEAR; + TSB_INTIFAO_STOP2INT_035_INT035NCLR = INT_NCLR_PCLR_CLEAR; + break; + case 4U: /* STOP2INT_036 */ + TSB_INTIFAO_STOP2INT_036_INT036PCLR = INT_NCLR_PCLR_CLEAR; + TSB_INTIFAO_STOP2INT_036_INT036NCLR = INT_NCLR_PCLR_CLEAR; + break; + case 5U: /* STOP2INT_037 */ + TSB_INTIFAO_STOP2INT_037_INT037PCLR = INT_NCLR_PCLR_CLEAR; + TSB_INTIFAO_STOP2INT_037_INT037NCLR = INT_NCLR_PCLR_CLEAR; + break; + case 6U: /* STOP2INT_038 */ + TSB_INTIFAO_STOP2INT_038_INT038PCLR = INT_NCLR_PCLR_CLEAR; + TSB_INTIFAO_STOP2INT_038_INT038NCLR = INT_NCLR_PCLR_CLEAR; + break; + case 7U: /* STOP2INT_039 */ + TSB_INTIFAO_STOP2INT_039_INT039PCLR = INT_NCLR_PCLR_CLEAR; + TSB_INTIFAO_STOP2INT_039_INT039NCLR = INT_NCLR_PCLR_CLEAR; + break; + default: + /* Do nothing */ + break; + } +} + +/** + * @brief Get the INTFLAG1. + * @param None + * @retval INTFLAG1 flag + */ +INTIFAO_IntFlag1Factor INTIFAO_GetIntFlag1(void) +{ + INTIFAO_IntFlag1Factor intifao_intflag1_factor = { 0U }; + + intifao_intflag1_factor.All = TSB_INTIFSD->FLAG1 & (~INTIFAO_INTFLAG1_MASK); + + return intifao_intflag1_factor; +} + +/** @} */ +/* End of group INTIFAO_Exported_Functions */ + +/** @} */ +/* End of group INTIFAO */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#endif /* defined(__TMPM066_INTIFAO_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifsd.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifsd.c new file mode 100644 index 0000000000..6cd8329acd --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_intifsd.c @@ -0,0 +1,368 @@ +/** + ******************************************************************************* + * @file tmpm066_intifsd.c + * @brief This file provides API functions for INTIFSD driver + * @version V2.0.2.1 + * @date 2015/10/19 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tmpm066_intifsd.h" + +#if defined(__TMPM066_INTIFSD_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @defgroup INTIFSD + * @brief INTIFSD driver modules + * @{ + */ + +/** @defgroup INTIFSD_Private_Defines + * @{ + */ +#define INTIFSD_NMIFLG_MASK ((uint32_t)0xFFF8FFFF) + +#define INTIFSD_INTFLAG4_MASK ((uint32_t)0xE0000000) +#define INTIFSD_INTFLAG5_MASK ((uint32_t)0xFFFFFC00) + +/** @} */ +/* End of group INTIFSD_Private_Defines */ + +/** @defgroup INTIFSD_Private_FunctionPrototypes + * @{ + */ + +/** @} */ +/* End of group INTIFSD_Private_FunctionPrototypes */ + +/** @defgroup INTIFSD_Private_Functions + * @{ + */ + +/** @} */ +/* End of group INTIFSD_Private_Functions */ + +/** @defgroup INTIFSD_Exported_Functions + * @{ + */ + +/** + * @brief Get the NMI flag that shows who triggered NMI. + * @param None + * @retval NMI flag + */ +INTIFSD_NMIFactor INTIFSD_GetNMIFlag(void) +{ + INTIFSD_NMIFactor intifsd_nmi_factor = { 0U }; + + intifsd_nmi_factor.All = TSB_INTIFSD->FLAG0 & (~INTIFSD_NMIFLG_MASK); + + return intifsd_nmi_factor; +} + +/** + * @brief Get the INTFLAG3. + * @param None + * @retval INTFLAG3 flag + */ +INTIFSD_IntFlag3Factor INTIFSD_GetIntFlag3(void) +{ + INTIFSD_IntFlag3Factor intifsd_intflag3_factor = { 0U }; + + intifsd_intflag3_factor.All = TSB_INTIFSD->FLAG3; + + return intifsd_intflag3_factor; +} + +/** + * @brief Get the INTFLAG4. + * @param None + * @retval INTFLAG4 flag + */ +INTIFSD_IntFlag4Factor INTIFSD_GetIntFlag4(void) +{ + INTIFSD_IntFlag4Factor intifsd_intflag4_factor = { 0U }; + + intifsd_intflag4_factor.All = TSB_INTIFSD->FLAG4 & (~INTIFSD_INTFLAG4_MASK); + + return intifsd_intflag4_factor; +} + +/** + * @brief Get the INTFLAG5. + * @param None + * @retval INTFLAG5 flag + */ +INTIFSD_IntFlag5Factor INTIFSD_GetIntFlag5(void) +{ + INTIFSD_IntFlag5Factor intifsd_intflag5_factor = { 0U }; + + intifsd_intflag5_factor.All = TSB_INTIFSD->FLAG5 & (~INTIFSD_INTFLAG5_MASK); + + return intifsd_intflag5_factor; +} + +/** + * @brief Clears the input INT request. + * @param INTSource: Select the release INT source + * This parameter can be one of the following values: + * INTIFSD_INT_SRC_LVD_PSFD, INTIFSD_INT_SRC_LVD_PRD, INTIFSD_INT_SRC_WDT, INTIFSD_INT_SRC_DMAC_0, + * INTIFSD_INT_SRC_DMAC_1, INTIFSD_INT_SRC_DMAC_2, INTIFSD_INT_SRC_DMAC_3, INTIFSD_INT_SRC_DMAC_4, + * INTIFSD_INT_SRC_DMAC_5, INTIFSD_INT_SRC_DMAC_6, INTIFSD_INT_SRC_DMAC_7, INTIFSD_INT_SRC_DMAC_8, + * INTIFSD_INT_SRC_DMAC_9, INTIFSD_INT_SRC_DMAC_10, INTIFSD_INT_SRC_DMAC_11, INTIFSD_INT_SRC_DMAC_12, + * INTIFSD_INT_SRC_DMAC_13, INTIFSD_INT_SRC_DMAC_14, INTIFSD_INT_SRC_DMAC_15, INTIFSD_INT_SRC_DMAC_16, + * INTIFSD_INT_SRC_DMAC_17, INTIFSD_INT_SRC_DMAC_18, INTIFSD_INT_SRC_DMAC_19, INTIFSD_INT_SRC_DMAC_20, + * INTIFSD_INT_SRC_DMAC_21, INTIFSD_INT_SRC_DMAC_22, INTIFSD_INT_SRC_DMAC_23, INTIFSD_INT_SRC_DMAC_24, + * INTIFSD_INT_SRC_DMAC_25, INTIFSD_INT_SRC_DMAC_26, INTIFSD_INT_SRC_DMAC_27, INTIFSD_INT_SRC_DMAC_28, + * INTIFSD_INT_SRC_DMAC_29, INTIFSD_INT_SRC_DMAC_30, INTIFSD_INT_SRC_DMAC_31, INTIFSD_INT_SRC_DMAC_ERR, + * INTIFSD_INT_SRC_TMRB_0_MDOVF, INTIFSD_INT_SRC_TMRB_0_CAP0, INTIFSD_INT_SRC_TMRB_0_CAP1, INTIFSD_INT_SRC_TMRB_1_MDOVF, + * INTIFSD_INT_SRC_TMRB_1_CAP0, INTIFSD_INT_SRC_TMRB_1_CAP1, INTIFSD_INT_SRC_TMRB_2_MDOVF, INTIFSD_INT_SRC_TMRB_2_CAP0, + * INTIFSD_INT_SRC_TMRB_2_CAP1, INTIFSD_INT_SRC_TMRB_3_MDOVF, INTIFSD_INT_SRC_TMRB_3_CAP0, INTIFSD_INT_SRC_TMRB_3_CAP1, + * INTIFSD_INT_SRC_TMRB_4_MDOVF,INTIFSD_INT_SRC_TMRB_4_CAP0, INTIFSD_INT_SRC_TMRB_4_CAP1, INTIFSD_INT_SRC_TMRB_5_MDOVF, + * INTIFSD_INT_SRC_TMRB_5_CAP0, INTIFSD_INT_SRC_TMRB_5_CAP1, INTIFSD_INT_SRC_TMRB_6_MDOVF, INTIFSD_INT_SRC_TMRB_6_CAP0, + * INTIFSD_INT_SRC_TMRB_6_CAP1, INTIFSD_INT_SRC_TMRB_7_MDOVF, INTIFSD_INT_SRC_TMRB_7_CAP0, INTIFSD_INT_SRC_TMRB_7_CAP1, + * INTIFSD_INT_SRC_TMRD_00, INTIFSD_INT_SRC_TMRD_01, INTIFSD_INT_SRC_TMRD_02, INTIFSD_INT_SRC_TMRD_03, + * INTIFSD_INT_SRC_TMRD_04, INTIFSD_INT_SRC_TMRD_10, INTIFSD_INT_SRC_TMRD_11, INTIFSD_INT_SRC_TMRD_12, + * INTIFSD_INT_SRC_TMRD_13, INTIFSD_INT_SRC_TMRD_14. + * @retval None + */ +void INTIFSD_ClearINTReq(INTIFSD_INTSrc INTSource) +{ + uint8_t num = 0U; + + /* Check the parameters */ + assert_param(IS_INTIFSD_INT_SRC(INTSource)); + + num = (uint32_t) INTSource; + switch (num) { + case 0U: /* STOP1INT_016 */ + TSB_INTIFSD->STOP1INT_016 |= 0xC0; + break; + case 1U: /* STOP1INT_017 */ + TSB_INTIFSD->STOP1INT_017 |= 0xC0; + break; + case 2U: /* IDLEINT_018 */ + TSB_INTIFSD->IDLEINT_018 |= 0xC0; + break; + case 3U: /* IDLEINT_096 */ + TSB_INTIFSD->IDLEINT_096 |= 0xC0; + break; + case 4U: /* IDLEINT_097 */ + TSB_INTIFSD->IDLEINT_097 |= 0xC0; + break; + case 5U: /* IDLEINT_098 */ + TSB_INTIFSD->IDLEINT_098 |= 0xC0; + break; + case 6U: /* IDLEINT_099 */ + TSB_INTIFSD->IDLEINT_099 |= 0xC0; + break; + case 7U: /* IDLEINT_100 */ + TSB_INTIFSD->IDLEINT_100 |= 0xC0; + break; + case 8U: /* IDLEINT_101 */ + TSB_INTIFSD->IDLEINT_101 |= 0xC0; + break; + case 9U: /* IDLEINT_102 */ + TSB_INTIFSD->IDLEINT_102 |= 0xC0; + break; + case 10U: /* IDLEINT_103 */ + TSB_INTIFSD->IDLEINT_103 |= 0xC0; + break; + case 11U: /* IDLEINT_104 */ + TSB_INTIFSD->IDLEINT_104 |= 0xC0; + break; + case 12U: /* IDLEINT_105 */ + TSB_INTIFSD->IDLEINT_105 |= 0xC0; + break; + case 13U: /* IDLEINT_106 */ + TSB_INTIFSD->IDLEINT_106 |= 0xC0; + break; + case 14U: /* IDLEINT_107 */ + TSB_INTIFSD->IDLEINT_107 |= 0xC0; + break; + case 15U: /* IDLEINT_108 */ + TSB_INTIFSD->IDLEINT_108 |= 0xC0; + break; + case 16U: /* IDLEINT_109 */ + TSB_INTIFSD->IDLEINT_109 |= 0xC0; + break; + case 17U: /* IDLEINT_110 */ + TSB_INTIFSD->IDLEINT_110 |= 0xC0; + break; + case 18U: /* IDLEINT_111 */ + TSB_INTIFSD->IDLEINT_111 |= 0xC0; + break; + case 19U: /* IDLEINT_112 */ + TSB_INTIFSD->IDLEINT_112 |= 0xC0; + break; + case 20U: /* IDLEINT_113 */ + TSB_INTIFSD->IDLEINT_113 |= 0xC0; + break; + case 21U: /* IDLEINT_114 */ + TSB_INTIFSD->IDLEINT_114 |= 0xC0; + break; + case 22U: /* IDLEINT_115 */ + TSB_INTIFSD->IDLEINT_115 |= 0xC0; + break; + case 23U: /* IDLEINT_116 */ + TSB_INTIFSD->IDLEINT_116 |= 0xC0; + break; + case 24U: /* IDLEINT_117 */ + TSB_INTIFSD->IDLEINT_117 |= 0xC0; + break; + case 25U: /* IDLEINT_118 */ + TSB_INTIFSD->IDLEINT_118 |= 0xC0; + break; + case 26U: /* IDLEINT_119 */ + TSB_INTIFSD->IDLEINT_119 |= 0xC0; + break; + case 27U: /* IDLEINT_120 */ + TSB_INTIFSD->IDLEINT_120 |= 0xC0; + break; + case 28U: /* IDLEINT_121 */ + TSB_INTIFSD->IDLEINT_121 |= 0xC0; + break; + case 29U: /* IDLEINT_122 */ + TSB_INTIFSD->IDLEINT_122 |= 0xC0; + break; + case 30U: /* IDLEINT_123 */ + TSB_INTIFSD->IDLEINT_123 |= 0xC0; + break; + case 31U: /* IDLEINT_124 */ + TSB_INTIFSD->IDLEINT_124 |= 0xC0; + break; + case 32U: /* IDLEINT_125 */ + TSB_INTIFSD->IDLEINT_125 |= 0xC0; + break; + case 33U: /* IDLEINT_126 */ + TSB_INTIFSD->IDLEINT_126 |= 0xC0; + break; + case 34U: /* IDLEINT_127 */ + TSB_INTIFSD->IDLEINT_127 |= 0xC0; + break; + case 35U: /* IDLEINT_128 */ + TSB_INTIFSD->IDLEINT_128 |= 0xC0; + break; + case 36U: /* IDLEINT_129 */ + TSB_INTIFSD->IDLEINT_129 |= 0xC0; + break; + case 37U: /* IDLEINT_130 */ + TSB_INTIFSD->IDLEINT_130 |= 0xC0; + break; + case 38U: /* IDLEINT_131 */ + TSB_INTIFSD->IDLEINT_131 |= 0xC0; + break; + case 39U: /* IDLEINT_132 */ + TSB_INTIFSD->IDLEINT_132 |= 0xC0; + break; + case 40U: /* IDLEINT_133 */ + TSB_INTIFSD->IDLEINT_133 |= 0xC0; + break; + case 41U: /* IDLEINT_134 */ + TSB_INTIFSD->IDLEINT_134 |= 0xC0; + break; + case 42U: /* IDLEINT_135 */ + TSB_INTIFSD->IDLEINT_135 |= 0xC0; + break; + case 43U: /* IDLEINT_136 */ + TSB_INTIFSD->IDLEINT_136 |= 0xC0; + break; + case 44U: /* IDLEINT_137 */ + TSB_INTIFSD->IDLEINT_137 |= 0xC0; + break; + case 45U: /* IDLEINT_138 */ + TSB_INTIFSD->IDLEINT_138 |= 0xC0; + break; + case 46U: /* IDLEINT_139 */ + TSB_INTIFSD->IDLEINT_139 |= 0xC0; + break; + case 47U: /* IDLEINT_140 */ + TSB_INTIFSD->IDLEINT_140 |= 0xC0; + break; + case 48U: /* IDLEINT_141 */ + TSB_INTIFSD->IDLEINT_141 |= 0xC0; + break; + case 49U: /* IDLEINT_142 */ + TSB_INTIFSD->IDLEINT_142 |= 0xC0; + break; + case 50U: /* IDLEINT_143 */ + TSB_INTIFSD->IDLEINT_143 |= 0xC0; + break; + case 51U: /* IDLEINT_144 */ + TSB_INTIFSD->IDLEINT_144 |= 0xC0; + break; + case 52U: /* IDLEINT_145 */ + TSB_INTIFSD->IDLEINT_145 |= 0xC0; + break; + case 53U: /* IDLEINT_146 */ + TSB_INTIFSD->IDLEINT_146 |= 0xC0; + break; + case 54U: /* IDLEINT_147 */ + TSB_INTIFSD->IDLEINT_147 |= 0xC0; + break; + case 55U: /* IDLEINT_148 */ + TSB_INTIFSD->IDLEINT_148 |= 0xC0; + break; + case 56U: /* IDLEINT_149 */ + TSB_INTIFSD->IDLEINT_149 |= 0xC0; + break; + case 57U: /* IDLEINT_150 */ + TSB_INTIFSD->IDLEINT_150 |= 0xC0; + break; + case 58U: /* IDLEINT_151 */ + TSB_INTIFSD->IDLEINT_151 |= 0xC0; + break; + case 59U: /* IDLEINT_152 */ + TSB_INTIFSD->IDLEINT_152 |= 0xC0; + break; + case 60U: /* IDLEINT_160 */ + TSB_INTIFSD->IDLEINT_160 |= 0xC0; + break; + case 61U: /* IDLEINT_161 */ + TSB_INTIFSD->IDLEINT_161 |= 0xC0; + break; + case 62U: /* IDLEINT_162 */ + TSB_INTIFSD->IDLEINT_162 |= 0xC0; + break; + case 63U: /* IDLEINT_163 */ + TSB_INTIFSD->IDLEINT_163 |= 0xC0; + break; + case 64U: /* IDLEINT_164 */ + TSB_INTIFSD->IDLEINT_164 |= 0xC0; + break; + case 65U: /* IDLEINT_165 */ + TSB_INTIFSD->IDLEINT_165 |= 0xC0; + break; + case 66U: /* IDLEINT_166 */ + TSB_INTIFSD->IDLEINT_166 |= 0xC0; + break; + case 67U: /* IDLEINT_167 */ + TSB_INTIFSD->IDLEINT_167 |= 0xC0; + break; + case 68U: /* IDLEINT_168 */ + TSB_INTIFSD->IDLEINT_168 |= 0xC0; + break; + case 69U: /* IDLEINT_169 */ + TSB_INTIFSD->IDLEINT_169 |= 0xC0; + break; + default: + /* Do nothing */ + break; + } +} + +/** @} */ +/* End of group INTIFSD_Exported_Functions */ + +/** @} */ +/* End of group INTIFSD */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#endif /* defined(__TMPM066_INTIFSD_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmr16a.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmr16a.c new file mode 100644 index 0000000000..32f1f1f403 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmr16a.c @@ -0,0 +1,195 @@ +/** + ******************************************************************************* + * @file tmpm066_tmr16a.c + * @brief This file provides API functions for TMR16A driver. + * @version V2.0.2.1 + * @date 2015/10/09 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tmpm066_tmr16a.h" + +#if defined(__TMPM066_TMR16A_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @defgroup TMR16A + * @brief TMR16A driver modules + * @{ + */ + +/** @defgroup TMR16A_Private_Defines + * @{ + */ +#define CR_CLK_SYSCK ((uint32_t)0xFFFFFFFE) +#define CR_CLK_PRCK ((uint32_t)0x00000001) +#define CR_FF_MASK ((uint32_t)0xFFFFFF4F) + +#define CP_CP_CLEAR ((uint32_t)0xFFFF0000) +/** @} */ +/* End of group TMR16A_Private_Defines */ + +/** @defgroup TMR16A_Private_FunctionPrototypes + * @{ + */ + +/** @} */ +/* End of group TMR16A_Private_FunctionPrototypes */ + +/** @defgroup TMR16A_Private_Functions + * @{ + */ + +/** @} */ +/* End of group TMR16A_Private_Functions */ + +/** @defgroup TMR16A_Exported_Functions + * @{ + */ + +/** + * @brief Start or stop counter of the specified TMR16A channel. + * @param T16Ax: Select the TMR16A channel. + * This parameter can be one of the following values: + * TSB_T16A0, TSB_T16A1. + * @param Cmd: The command for the counter. + * This parameter can be TMR16A_RUN or TMR16A_STOP. + * @retval None + */ +void TMR16A_SetRunState(TSB_T16A_TypeDef * T16Ax, uint32_t Cmd) +{ + /* Check the parameters */ + assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); + assert_param(IS_TMR16A_CMD(Cmd)); + + /* Write command into RUN register */ + T16Ax->RUN = Cmd; +} + +/** + * @brief Specifies a source clock. + * @param T16Ax: Select the TMR16A channel. + * This parameter can be one of the following values: + * TSB_T16A0, TSB_T16A1. + * @param SrcClk: The command for the counter. + * This parameter can be TMR16A_SYSCK or TMR16A_PRCK. + * @retval None + */ +void TMR16A_SetSrcClk(TSB_T16A_TypeDef * T16Ax, uint32_t SrcClk) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); + assert_param(IS_TMR16A_SRCCLK(SrcClk)); + + tmp = T16Ax->CR; + /* Write Sorce clock into register */ + if (SrcClk == TMR16A_PRCK) { + /* Set T16AxCR Source clock to PRCK */ + tmp |= CR_CLK_PRCK; + } else { + /* Clear T16AxCR Source clock to SYSCK */ + tmp &= CR_CLK_SYSCK; + } + T16Ax->CR = tmp; +} + +/** + * @brief Configure the flip-flop function. + * @param T16Ax: Select the TMR16A channel. + * This parameter can be one of the following values: + * TSB_T16A0, TSB_T16A1. + * @param FFStruct: The structure containing TMR16A flip-flop configuration + * @retval None + */ +void TMR16A_SetFlipFlop(TSB_T16A_TypeDef * T16Ax, TMR16A_FFOutputTypeDef * FFStruct) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_POINTER_NOT_NULL(FFStruct)); + assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); + assert_param(IS_TMR16A_FLIPFLOP_CTRL(FFStruct->TMR16AFlipflopCtrl)); + assert_param(IS_TMR16A_FLIPFLOP_TRG(FFStruct->TMR16AFlipflopReverseTrg)); + + /* Configure the flip-flop function of T16Ax */ + tmp = T16Ax->CR; + tmp &= CR_FF_MASK; + tmp |= (FFStruct->TMR16AFlipflopCtrl | FFStruct->TMR16AFlipflopReverseTrg); + T16Ax->CR = tmp; +} + +/** + * @brief Change cycle value of T16Ax. + * @param T16Ax: Select the TMR16A channel. + * This parameter can be one of the following values: + * TSB_T16A0, TSB_T16A1. + * @param Cycle: New cycle value, max 0xFFFF. + * @retval None + */ +void TMR16A_ChangeCycle(TSB_T16A_TypeDef * T16Ax, uint32_t Cycle) +{ + /* Check the parameters */ + assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); + assert_param(IS_TMR16A_VALUE(Cycle)); + + /* Write cycle into RG1 */ + T16Ax->RG = Cycle; +} + +/** + * @brief Get TMR16A capture value of T16Ax. + * @param T16Ax: Select the TMR16A channel. + * This parameter can be one of the following values: + * TSB_T16A0, TSB_T16A1. + * @retval Capture value of T16Ax + */ +uint16_t TMR16A_GetCaptureValue(TSB_T16A_TypeDef * T16Ax) +{ + uint16_t CapVal; + + /* Check the parameters */ + assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); + + CapVal = (uint16_t) T16Ax->CP; + + return CapVal; +} + +/** + * @brief Enable or disable clock operation during debug HALT. + * @param T16Ax: Select the TMR16A channel. + * This parameter can be one of the following values: + * TSB_T16A0, TSB_T16A1. + * @param ClkState: Timer state in HALT mode. + * This parameter can be TMR16A_RUNNING_IN_CORE_HALT or TMR16A_STOP_IN_CORE_HALT. + * @retval None + */ +void TMR16A_SetClkInCoreHalt(TSB_T16A_TypeDef * T16Ax, uint8_t ClkState) +{ + /* Check the parameters */ + assert_param(IS_TMR16A_ALL_PERIPH(T16Ax)); + assert_param(IS_TMR16A_CLK_IN_CORE_HALT(ClkState)); + + if (ClkState == TMR16A_STOP_IN_CORE_HALT) { + /* Set T16AEN */ + T16Ax->EN |= (uint32_t) TMR16A_STOP_IN_CORE_HALT; + } else { + /* Clear T16AEN */ + T16Ax->EN &= ~(uint32_t) TMR16A_STOP_IN_CORE_HALT; + } +} + +/** @} */ +/* End of group TMR16A_Exported_Functions */ + +/** @} */ +/* End of group TMR16A */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#endif /* defined(__TMPM066_TMR16A_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmrb.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmrb.c new file mode 100644 index 0000000000..b72b987b9d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_tmrb.c @@ -0,0 +1,555 @@ +/** + ******************************************************************************* + * @file tmpm066_tmrb.c + * @brief This file provides API functions for TMRB driver. + * @version V2.0.2.1 + * @date 2015/10/09 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tmpm066_tmrb.h" + +#if defined (__TMPM066_TMRB_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @defgroup TMRB + * @brief TMRB driver modules + * @{ + */ + +/** @defgroup TMRB_Private_Defines + * @{ + */ + +#define EN_TBEN_SET ((uint32_t)0x00000080) +#define EN_TBEN_CLEAR ((uint32_t)0xFFFFFF7F) + +#define CR_TBSYNC_SET ((uint32_t)0x00000020) +#define CR_TBSYNC_CLEAR ((uint32_t)0xFFFFFFDF) +#define CR_TBWBF_SET ((uint32_t)0x00000080) +#define CR_TBWBF_CLEAR ((uint32_t)0xFFFFFF7F) +#define CR_CSSEL_SET ((uint32_t)0x00000001) +#define CR_CSSEL_CLEAR ((uint32_t)0xFFFFFFFE) +#define CR_TRGSEL_CLEAR ((uint32_t)0xFFFFFFFD) +#define CR_BIT6_CLEAR ((uint32_t)0xFFFFFFBF) + +#define MOD_BIT7_CLEAR ((uint32_t)0xFFFFFF7F) +#define MOD_CLK_CLE_CLEAR ((uint32_t)0xFFFFFFF0) +#define MOD_TBCPM_CLEAR ((uint32_t)0xFFFFFF8F) +#define MOD_TBCP_SET ((uint32_t)0x00000040) +#define MOD_TBCP_CLEAR ((uint32_t)0xFFFFFFBF) + +#define TB_ST_MASK ((uint32_t)0x00000007) +#define TB_IM_MASK ((uint32_t)0x00000007) + +/** @} */ +/* End of group TMRB_Private_Defines */ + +/** @defgroup TMRB_Private_FunctionPrototypes + * @{ + */ + +/** @} */ +/* End of group TMRB_Private_FunctionPrototypes */ + +/** @defgroup TMRB_Private_Functions + * @{ + */ + +/** @} */ +/* End of group TMRB_Private_Functions */ + +/** @defgroup TMRB_Exported_Functions + * @{ + */ + +/** + * @brief Enable the specified TMRB channel. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @retval None + */ +void TMRB_Enable(TSB_TB_TypeDef * TBx) +{ + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + /* Set TBxEN to enable TBx */ + TBx->EN |= EN_TBEN_SET; +} + +/** + * @brief Disable the specified TMRB channel. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @retval None + */ +void TMRB_Disable(TSB_TB_TypeDef * TBx) +{ + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + /* Clear TBxEN to disable TBx */ + TBx->EN &= EN_TBEN_CLEAR; +} + +/** + * @brief Start or stop counter of the specified TMRB channel. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param Cmd: The command for the counter. + * This parameter can be TMRB_RUN or TMRB_STOP. + * @retval None + */ +void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd) +{ + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_TMRB_CMD(Cmd)); + + /* Write command into RUN register */ + TBx->RUN = Cmd; +} + +/** + * @brief Initialize the specified TMRB channel. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param InitStruct: The structure containing basic TMRB configuration. + * @retval None + */ +void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_POINTER_NOT_NULL(InitStruct)); + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_TMRB_MODE(InitStruct->Mode)); + if (InitStruct->Mode != 0U) { + assert_param(IS_TMRB_CLK_DIV(InitStruct->ClkDiv)); + } else { + /* Do nothing */ + } + assert_param(IS_TMRB_VALUE(InitStruct->TrailingTiming)); + assert_param(IS_TMRB_UC_CTRL(InitStruct->UpCntCtrl)); + assert_param(IS_TMRB_VALUE(InitStruct->LeadingTiming)); + assert_param(IS_VALID_LEADINGTIMING(InitStruct->LeadingTiming, InitStruct->TrailingTiming)); + + /* Configure source clock for TBx */ + tmp = TBx->MOD; + tmp &= MOD_BIT7_CLEAR; + tmp &= MOD_CLK_CLE_CLEAR; + if (InitStruct->Mode != 0U) { + /* Use internal clock, set the prescaler */ + tmp |= InitStruct->ClkDiv; + } else { + /* Use external clock */ + tmp |= InitStruct->Mode; + } + /* Set up-counter running mode */ + tmp |= InitStruct->UpCntCtrl; + tmp |= MOD_TBCP_SET; + TBx->MOD = tmp; + + /* Write leadingtiming into RG0 */ + TBx->RG0 = InitStruct->LeadingTiming; + + /* Write trailingtiminginto RG1 */ + TBx->RG1 = InitStruct->TrailingTiming; +} + +/** + * @brief Configure the capture timing. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5. + * @param CaptureTiming: Specify TMRB capture timing. + * This parameter can be one of the following values: + * TMRB_DISABLE_CAPTURE, TMRB_CAPTURE_IN_RISING_FALLING, TMRB_CAPTURE_FF_RISING_FALLING. + * @retval None + */ +void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_TMRB_CAP_PERIPH(TBx)); + assert_param(IS_TMRB_CAPTURE_TIMING(CaptureTiming)); + + /* Configure capture timing */ + tmp = TBx->MOD; + tmp &= MOD_BIT7_CLEAR; + tmp &= MOD_TBCPM_CLEAR; + tmp |= CaptureTiming; + tmp |= MOD_TBCP_SET; + TBx->MOD = tmp; +} + +/** + * @brief Configure the flip-flop function. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param FFStruct: The structure containing TMRB flip-flop configuration + * @retval None + */ +void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct) +{ + /* Check the parameters */ + assert_param(IS_POINTER_NOT_NULL(FFStruct)); + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_TMRB_FLIPFLOP_CTRL(FFStruct->FlipflopCtrl)); + assert_param(IS_TMRB_FLIPFLOP_TRG(FFStruct->FlipflopReverseTrg)); + + /* Configure the flip-flop function of TBx */ + TBx->FFCR = (FFStruct->FlipflopCtrl | FFStruct->FlipflopReverseTrg); +} + +/** + * @brief Indicate what causes the interrupt. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @retval The interrupt factor of TBx. + */ +TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx) +{ + TMRB_INTFactor retval = { 0U }; + + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + + retval.All = TBx->ST & TB_ST_MASK; + return retval; +} + +/** + * @brief Indicate what interrupt cause source be masked. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @retval The masked interrupt cause source of TBx. + */ +TMRB_INTMask TMRB_GetINTMask(TSB_TB_TypeDef * TBx) +{ + TMRB_INTMask retval = { 0U }; + + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + + retval.All = TBx->IM & TB_IM_MASK; + return retval; +} + +/** + * @brief Mask some TMRB interrupts. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param INTMask: Select the mask of TMRB interrupt. + * This parameter can be one of the following values: + * TMRB_NO_INT_MASK, TMRB_MASK_MATCH_LEADINGTIMING_INT, TMRB_MASK_MATCH_TRAILINGTIMING_INT, + * or TMRB_MASK_OVERFLOW_INT. + * @retval None + */ +void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask) +{ + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_TMRB_INT_MASK(INTMask)); + + /* Mask the specified interrupt */ + TBx->IM = INTMask; +} + +/** + * @brief Change leadingtiming value of TBx. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param LeadingTiming: New leadingtiming value, max 0xFFFF. + * @retval None + */ +void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming) +{ + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_TMRB_VALUE(LeadingTiming)); + assert_param(IS_VALID_LEADINGTIMING(LeadingTiming, TBx->RG1)); + + /* Write leadingtiming into RG0 */ + TBx->RG0 = LeadingTiming; +} + +/** + * @brief Change trailingtiming value of TBx. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param TrailingTiming: New trailingtiming value, max 0xFFFF. + * @retval None + */ +void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming) +{ + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_TMRB_VALUE(TrailingTiming)); + assert_param(IS_VALID_LEADINGTIMING(TBx->RG0, TrailingTiming)); + + /* Write trailingtiming into RG1 */ + TBx->RG1 = TrailingTiming; +} + +/** + * @brief Get TMRB register value of TBx. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param Reg: Select the timer register to read. + * This parameter can be: TMRB_REG_0 or TMRB_REG_1. + * @retval Register value of TBx + */ +uint16_t TMRB_GetRegisterValue(TSB_TB_TypeDef * TBx, uint8_t Reg) +{ + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_TMRB_REG(Reg)); + + return Reg ? (uint16_t) TBx->RG1 : (uint16_t) TBx->RG0; +} + +/** + * @brief Get up-counter value of TBx. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @retval Up-counter value of TBx + */ +uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx) +{ + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + + /* Return up-counter value */ + return (uint16_t) TBx->UC; +} + +/** + * @brief Get TMRB capture value of TBx. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5. + * @param CapReg: Select the capture register to read. + * This parameter can be: TMRB_CAPTURE_0 or TMRB_CAPTURE_1. + * @retval Capture value of TBx + */ +uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg) +{ + /* Check the parameters */ + assert_param(IS_TMRB_CAP_PERIPH(TBx)); + assert_param(IS_TMRB_CAPTURE_REG(CapReg)); + + return CapReg ? (uint16_t) TBx->CP1 : (uint16_t) TBx->CP0; +} + +/** + * @brief Capture counter by software and take them into capture register 0. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5. + * @retval None + */ +void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_TMRB_CAP_PERIPH(TBx)); + + /* Set software capture */ + tmp = TBx->MOD; + tmp &= MOD_BIT7_CLEAR; + TBx->MOD = tmp & MOD_TBCP_CLEAR; +} + +/** + * @brief Enable or disable the synchronous mode of specified TMRB channel. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB5, TSB_TB6, TSB_TB7. + * @param NewState: New state of TBx synchronous mode. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_TMRB_SYNC_PERIPH(TBx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmp = TBx->CR; + tmp &= CR_BIT6_CLEAR; + if (NewState == ENABLE) { + /* Set TBxCR to make TBx running in synchronous mode */ + TBx->CR = tmp | CR_TBSYNC_SET; + } else { + /* Clear TBxCR to make TBx running in individual mode */ + TBx->CR = tmp & CR_TBSYNC_CLEAR; + } +} + +/** + * @brief Enable or disable double buffer of TBx. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param NewState: New state of TBx double buffer. + * This parameter can be ENABLE or DISABLE. + * @retval None + */ +void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmp = TBx->CR; + tmp &= CR_BIT6_CLEAR; + if (NewState == ENABLE) { + /* Set TBxCR to enable TBx double buffer */ + TBx->CR = tmp | CR_TBWBF_SET; + } else { + /* Clear TBxCR to disable TBx double buffer */ + TBx->CR = tmp & CR_TBWBF_CLEAR; + } +} + +/** + * @brief Enable or disable external trigger to start count and set the active edge. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param NewState: New state of external trigger. + * This parameter can be ENABLE or DISABLE. + * @param TrgMode: Active edge of the external trigger signal. + * This parameter can be TMRB_TRG_EDGE_RISING or TMRB_TRG_EDGE_FALLING. + * @retval None + */ +void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_TMRB_TRG_EDGE(TrgMode)); + + tmp = TBx->CR; + tmp &= CR_BIT6_CLEAR; + if (NewState == ENABLE) { + /* Set TBxCR to choose external trigger */ + tmp |= CR_CSSEL_SET; + } else { + /* Clear TBxCR to choose software start */ + tmp &= CR_CSSEL_CLEAR; + } + + /* external trigger selection */ + tmp &= CR_TRGSEL_CLEAR; + tmp |= (uint32_t) TrgMode; + TBx->CR = tmp; +} + +/** + * @brief Enable or disable clock operation during debug HALT. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param ClkState: Timer state in HALT mode. + * This parameter can be TMRB_RUNNING_IN_CORE_HALT or TMRB_STOP_IN_CORE_HALT. + * @retval None + */ +void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState) +{ + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_TMRB_CLK_IN_CORE_HALT(ClkState)); + + if (ClkState == TMRB_STOP_IN_CORE_HALT) { + /* Set TBxEN */ + TBx->EN |= (uint32_t) TMRB_STOP_IN_CORE_HALT; + } else { + /* Clear TBxEN */ + TBx->EN &= ~(uint32_t) TMRB_STOP_IN_CORE_HALT; + } +} + +/** + * @brief Enable or disable DMA request. + * @param TBx: Select the TMRB channel. + * This parameter can be one of the following values: + * TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, + * TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7. + * @param NewState: New state of DMA request. + * This parameter can be ENABLE or DISABLE. + * @param DMAReq: DMA request. + * This parameter can be TMRB_DMA_REQ_CMP_MATCH, TMRB_DMA_REQ_CAPTURE_1 or TMRB_DMA_REQ_CAPTURE_0. + * @retval None + */ +void TMRB_SetDMAReq(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t DMAReq) +{ + /* Check the parameters */ + assert_param(IS_TMRB_ALL_PERIPH(TBx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_TMRB_DMA_REQ(DMAReq)); + + if (NewState == ENABLE) { + /* set TBxDMA(n can be 0,1,2) */ + TBx->DMA |= (uint32_t) DMAReq; + } else { + /* clear TBxDMA(n can be 0,1,2) */ + TBx->DMA &= ~((uint32_t) DMAReq); + } +} + + +/** @} */ +/* End of group TMRB_Exported_Functions */ + +/** @} */ +/* End of group TMRB */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#endif /* defined(__TMPM066_TMRB_H) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c new file mode 100644 index 0000000000..2dd7cc1b8c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c @@ -0,0 +1,1198 @@ + +/** + ******************************************************************************* + * @file tmpm066_uart.c + * @brief This file provides API functions for UART driver. + * @version V2.0.2.1 + * @date 2015/09/10 + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tmpm066_uart.h" + +#if defined(__TMPM066_UART_H) +/** @addtogroup TX00_Periph_Driver + * @{ + */ + +/** @defgroup UART + * @brief UART driver modules + * @{ + */ + +/** @defgroup UART_Private_Defines + * @{ + */ +#define EN_SIOE_SET ((uint32_t)0x00000001) +#define EN_SIOE_CLEAR ((uint32_t)0xFFFFFFFE) +#define EN_BRCKSEL_MASK ((uint32_t)0xFFFFFFFD) + +#define CR_PARITY_MASK ((uint32_t)0x0000779F) +#define CR_ERROR_MASK ((uint32_t)0x0000001C) +#define CR_OERR_FLAG ((uint8_t)0x10) +#define CR_PERR_FLAG ((uint8_t)0x08) +#define CR_FERR_FLAG ((uint8_t)0x04) +#define CR_IOC_MASK ((uint32_t)0x000077FE) +#define CR_SCLKS_MASK ((uint32_t)0x000077FD) +#define CR_TIDLE_MASK ((uint32_t)0x000074FF) +#define CR_TXDEMP_MASK ((uint32_t)0x000073FF) +#define CR_EHOLD_MASK ((uint32_t)0x000007FF) + +#define MOD0_CTSE_MASK ((uint32_t)0x000000BF) +#define MOD0_RXE_CLEAR ((uint32_t)0x000000DF) +#define MOD0_WU_SET ((uint32_t)0x00000010) +#define MOD0_WU_CLEAR ((uint32_t)0x000000EF) +#define MOD0_SM_MASK ((uint32_t)0x000000F3) +#define MOD0_SC_MASK ((uint32_t)0x000000FC) +#define MOD0_SC_BRG ((uint32_t)0x00000001) + +#define MOD1_I2SC_SET ((uint32_t)0x00000080) +#define MOD1_I2SC_CLEAR ((uint32_t)0x0000007F) +#define MOD1_TXE_CLEAR ((uint32_t)0x000000EF) +#define MOD1_CLEAR ((uint32_t)0x000000FE) +#define MOD1_FDPX_CLEAR ((uint32_t)0x0000009F) +#define MOD1_SINT_MASK ((uint32_t)0x000000F1) + +#define MOD2_BUF_MASK ((uint32_t)0x000000C0) +#define MOD2_TBEMP_FLAG ((uint8_t)0x80) +#define MOD2_RBFLL_FLAG ((uint8_t)0x40) +#define MOD2_SBLEN_MASK ((uint32_t)0x000000EF) +#define MOD2_DRCHG_MASK ((uint32_t)0x000000F7) +#define MOD2_WBUF_SET ((uint32_t)0x00000004) +#define MOD2_WBUF_MASK ((uint32_t)0x000000FB) +#define MOD2_SWRST_MASK ((uint32_t)0x000000FC) +#define MOD2_SWRST_CMD1 ((uint32_t)0x00000002) +#define MOD2_SWRST_CMD2 ((uint32_t)0x00000001) + +#define BRCR_BRADDE_SET ((uint32_t)0x00000040) +#define BRCR_BRCK_MASK ((uint32_t)0x000000CF) +#define BRCR_BRS_MASK ((uint32_t)0x000000F0) +#define BRCR_CLEAR ((uint32_t)0x0000007F) + +#define BRADD_BRK_MASK ((uint32_t)0x00000000) + +#define FCNF_BIT567_CLEAR ((uint32_t)0x0000001F) +#define FCNF_RFST_CLEAR ((uint32_t)0x000000EF) +#define FCNF_TFIE_SET ((uint32_t)0x00000008) +#define FCNF_TFIE_CLEAR ((uint32_t)0x00000017) +#define FCNF_RFIE_SET ((uint32_t)0x00000004) +#define FCNF_RFIE_CLEAR ((uint32_t)0x0000001B) +#define FCNF_RXTXCNT_SET ((uint32_t)0x00000002) +#define FCNF_RXTXCNT_CLEAR ((uint32_t)0x0000001D) +#define FCNF_CNFG_SET ((uint32_t)0x00000001) +#define FCNF_CNFG_CLEAR ((uint32_t)0x0000001E) + +#define RFC_4B_RIL_CLEAR ((uint32_t)0x000000FC) +#define TFC_4B_TIL_CLEAR ((uint32_t)0x000001FC) +#define RFC_RFIS_CLEAR ((uint32_t)0x000000BF) +#define TFC_TFIS_CLEAR ((uint32_t)0x000001BF) +#define TRFC_TRFCS_SET ((uint32_t)0x00000080) +#define TFC_TBCLR_SET ((uint32_t)0x00000100) + +#define TRXST_TUR_ROR_MASK ((uint32_t)0x00000080) +#define TRXST_4B_TRLVL_MASK ((uint32_t)0x00000007) + +#define DMA_EN0_SET ((uint32_t)0x00000001) +#define DMA_EN0_CLEAR ((uint32_t)0x00000002) + +#define DMA_EN1_SET ((uint32_t)0x00000002) +#define DMA_EN1_CLEAR ((uint32_t)0x00000001) + +/** @} */ +/* End of group UART_Private_Defines */ + +/** @defgroup UART_Private_FunctionPrototypes + * @{ + */ + +/** @} */ +/* End of group UART_Private_FunctionPrototypes */ + +/** @defgroup UART_Private_Functions + * @{ + */ + +/** @} */ +/* End of group UART_Private_Functions */ + +/** @defgroup UART_Exported_Functions + * @{ + */ + +/** + * @brief Enable the specified UART channel. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval None + */ +void UART_Enable(TSB_SC_TypeDef * UARTx) +{ + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + /* Set SCxEN to enable UARTx */ + UARTx->EN |= EN_SIOE_SET; +} + +/** + * @brief Disable the specified UART channel. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval None + */ +void UART_Disable(TSB_SC_TypeDef * UARTx) +{ + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + /* Clear SCxEN to disable UARTx */ + UARTx->EN &= EN_SIOE_CLEAR; +} + +/** + * @brief Indicate whether the transfer buffer is full or not. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param Direction: Select the direction of transfer. + * This parameter can be UART_RX or UART_TX. + * @retval The transfer buffer status. + * The value returned can be one of the followings: + * BUSY or DONE. + */ +WorkState UART_GetBufState(TSB_SC_TypeDef * UARTx, uint32_t Direction) +{ + uint8_t tmp = 0U; + WorkState retval = BUSY; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UART_TRX(Direction)); + + tmp = ((uint8_t) (UARTx->MOD2 & MOD2_BUF_MASK)); + switch (Direction) { + case UART_TX: + if ((tmp & MOD2_TBEMP_FLAG) == MOD2_TBEMP_FLAG) { + /* Return Tx buffer empty if the flag is set */ + retval = DONE; + } else { + /* Do nothing */ + } + break; + case UART_RX: + if ((tmp & MOD2_RBFLL_FLAG) == MOD2_RBFLL_FLAG) { + /* Return Rx buffer full if the flag is set */ + retval = DONE; + } else { + /* Do nothing */ + } + break; + default: /* Do nothing */ + break; + } + + return retval; +} + +/** + * @brief Reset the specified UART channel. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval None + */ +void UART_SWReset(TSB_SC_TypeDef * UARTx) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + /* Write software-reset command */ + tmp = UARTx->MOD2; + tmp &= MOD2_SWRST_MASK; + UARTx->MOD2 = tmp | MOD2_SWRST_CMD1; + tmp &= MOD2_SWRST_MASK; + UARTx->MOD2 = tmp | MOD2_SWRST_CMD2; +} + +/** + * @brief Initialize the specified UART channel. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param InitStruct: The structure containing basic UART configuration. + * @retval None + * @note UART_SetInputClock need to use before UART_Init. + */ +void UART_Init(TSB_SC_TypeDef * UARTx, UART_InitTypeDef * InitStruct) +{ + uint32_t T0 = 0U; + uint32_t T = 0U; + uint32_t t = 0U; + uint32_t N = 0U; + uint32_t K = 0U; + uint32_t tmp = 0U; + uint32_t divider = 0U; + const uint32_t a = 1U; + const uint32_t b = 4U; + /* Check the parameters */ + assert_param(IS_POINTER_NOT_NULL(InitStruct)); + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UART_BAUDRATE(InitStruct->BaudRate)); + assert_param(IS_UART_DATA_BITS(InitStruct->DataBits)); + assert_param(IS_UART_STOPBITS(InitStruct->StopBits)); + assert_param(IS_UART_PARITY(InitStruct->Parity)); + assert_param(IS_UART_MODE(InitStruct->Mode)); + assert_param(IS_UART_FLOW_CONTROL(InitStruct->FlowCtrl)); + + /* Configure the flow control */ + tmp = UARTx->MOD0; + tmp &= MOD0_SM_MASK; + tmp &= MOD0_CTSE_MASK; + tmp &= MOD0_SC_MASK; + tmp |= (InitStruct->DataBits | InitStruct->FlowCtrl); + /* Use baud rate generator */ + tmp |= MOD0_SC_BRG; + UARTx->MOD0 = tmp; + + /* Set the stop bit */ + tmp = UARTx->MOD2; + tmp &= MOD2_SBLEN_MASK; + tmp |= InitStruct->StopBits; + tmp |= MOD2_WBUF_SET; + UARTx->MOD2 = tmp; + + /* Enable or disable parity check */ + tmp = UARTx->CR; + tmp &= CR_PARITY_MASK; + tmp |= InitStruct->Parity; + UARTx->CR = tmp; + + /* Get the peripheral I/O clock frequency */ + SystemCoreClockUpdate(); + T0 = SystemCoreClock / (a << ((TSB_CG->SYSCR >> 8U) & 0xFU)); + if (UARTx->EN & (0x1U << 1)) { + T0 *= 2U; + } else { + /* Do nothing */ + } + /* Baud rate setting */ + while ((divider < 200U) || (divider > 1600U)) { + if (t == 0U) { + T = 2U; + } else { + if (T < 128U) { + T = T * b; + } else { + /* Do nothing */ + } + } + divider = (100U * (T0 >> 4U)) / (InitStruct->BaudRate * T); + t++; + } + N = divider / 100U; + /* K value setting */ + if ((divider - (N * 100U)) == 0) { + /* Do nothing */ + } else { + K = (16U * (100U - (divider - (N * 100U)))) / 100U; + if (K < 1U) { + K = 1U; + } else { + /* Do nothing */ + } + tmp = UARTx->BRADD; + tmp &= BRADD_BRK_MASK; + tmp |= (K & 0x0FU); + UARTx->BRADD = tmp; + } + /* N value, , setting */ + /* */ + tmp = UARTx->BRCR; + if ((divider - (N * 100U)) == 0) { + tmp &= ~BRCR_BRADDE_SET; + } else { + tmp |= BRCR_BRADDE_SET; + } + tmp &= BRCR_BRCK_MASK; + tmp &= BRCR_BRS_MASK; + tmp |= (((t - 1U) & 3U) << 4U); + tmp |= (N & 0x0FU); + tmp &= BRCR_CLEAR; + UARTx->BRCR = tmp; + + tmp = UARTx->MOD1; + /* Enable or disable transmission or reception */ + switch (InitStruct->Mode) { + case UART_ENABLE_RX: + UARTx->MOD0 |= InitStruct->Mode; + tmp &= MOD1_TXE_CLEAR; + break; + case UART_ENABLE_TX: + tmp |= InitStruct->Mode; + UARTx->MOD0 &= MOD0_RXE_CLEAR; + break; + default: + UARTx->MOD0 |= UART_ENABLE_RX; + tmp |= UART_ENABLE_TX; + break; + } + tmp &= MOD1_CLEAR; + UARTx->MOD1 = tmp; +} + +/** + * @brief Get received data of the specified UART channel. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval The received data + */ +uint32_t UART_GetRxData(TSB_SC_TypeDef * UARTx) +{ + uint32_t retval = 0U; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + /* Return received data */ + retval = (UARTx->CR & 0x80U) << 1U; + retval = retval | (UARTx->BUF & 0xFFU); + + return retval; +} + +/** + * @brief Set data to be sent and start transmitting via the specified + UART channel. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param Data: the data to be sent. + * @retval None + */ +void UART_SetTxData(TSB_SC_TypeDef * UARTx, uint32_t Data) +{ + uint32_t tmp = UARTx->MOD0 & 0x7FU; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UART_DATA(Data)); + + /* Write MSB to SCxMOD0 at first if in 9-bit mode */ + tmp |= ((Data & 0x100U) >> 1U); + UARTx->MOD0 = tmp; + + UARTx->BUF = Data & 0xFFU; +} + +/** + * @brief Initialize the specified UART channel in default configuration. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval None + */ +void UART_DefaultConfig(TSB_SC_TypeDef * UARTx) +{ + UART_InitTypeDef uartdefault; + uartdefault.BaudRate = 115200U; + uartdefault.DataBits = UART_DATA_BITS_8; + uartdefault.StopBits = UART_STOP_BITS_1; + uartdefault.Parity = UART_NO_PARITY; + uartdefault.Mode = UART_ENABLE_RX | UART_ENABLE_TX; + uartdefault.FlowCtrl = UART_NONE_FLOW_CTRL; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + /* Enable the selected UART channel */ + UART_Enable(UARTx); + /* Select baud rate generator as UART source clcok */ + /* Set baud rate as 115200bps */ + /* Select 8-bit UART mode */ + /* Select 1-bit stop */ + /* No parity check */ + /* No flow control */ + /* Enable both transmission and reception */ + UART_Init(UARTx, &uartdefault); +} + +/** + * @brief Indicate UART transfer error. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval The error flag. + * The value returned can be one of the followings: + * UART_NO_ERR, UART_OVERRUN, UART_PARITY_ERR, UART_FRAMING_ERR or UART_ERRS. + */ +UART_Err UART_GetErrState(TSB_SC_TypeDef * UARTx) +{ + uint8_t tmp = 0U; + UART_Err retval = UART_NO_ERR; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + tmp = ((uint8_t) (UARTx->CR & CR_ERROR_MASK)); + switch (tmp) { + case CR_OERR_FLAG: /* Check overrun flag */ + retval = UART_OVERRUN; + break; + case CR_PERR_FLAG: /* Check parity flag */ + retval = UART_PARITY_ERR; + break; + case CR_FERR_FLAG: /* Check framing flag */ + retval = UART_FRAMING_ERR; + break; + default: + if (tmp != 0U) { + /* more than one error */ + retval = UART_ERRS; + } else { + /* Do nothing */ + } + break; + } + return retval; +} + +/** + * @brief Enable or disable the wake-up function in 9-bit UART mode + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param NewState: New state of this function. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_SetWakeUpFunc(TSB_SC_TypeDef * UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set SCxMOD0 to enable wake-up function */ + UARTx->MOD0 |= MOD0_WU_SET; + } else { + /* Clear SCxMOD0 to disable wake-up function */ + UARTx->MOD0 &= MOD0_WU_CLEAR; + } +} + +/** + * @brief Enable or disable the specified UART channel when system is in IDLE + mode. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param NewState: New state of the UART channel in IDLE. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_SetIdleMode(TSB_SC_TypeDef * UARTx, FunctionalState NewState) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmp = UARTx->MOD1; + if (NewState == ENABLE) { + /* Set SCxMOD1 to enable UARTx running in IDLE */ + tmp |= MOD1_I2SC_SET; + } else { + /* Clear SCxMOD1 to disable UARTx running in IDLE */ + tmp &= MOD1_I2SC_CLEAR; + } + tmp &= MOD1_CLEAR; + UARTx->MOD1 = tmp; +} + +/** + * @brief Selects input clock for prescaler. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param clock: Selects input clock for prescaler as PhiT0/2 or PhiT0. + * This parameter can be: + * 0: PhiT0/2 + * 1: PhiT0 + * @retval None + * @note UART_SetInputClock need to use before UART_Init. + */ +void UART_SetInputClock(TSB_SC_TypeDef * UARTx, uint32_t clock) +{ + uint32_t tmp = 0U; + + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UART_CLOCK(clock)); + + tmp = UARTx->EN; + tmp &= EN_BRCKSEL_MASK; + tmp |= (uint32_t) (clock << 1U); + UARTx->EN = tmp; +} + +/** + * @brief Enable or disable the FIFO of specified UART channel. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param NewState: New state of the UART FIFO. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_FIFOConfig(TSB_SC_TypeDef * UARTx, FunctionalState NewState) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmp = UARTx->FCNF; + tmp &= FCNF_BIT567_CLEAR; + if (NewState == ENABLE) { + /* Set SCxFCNF to enable UARTx FIFO */ + UARTx->FCNF = tmp | FCNF_CNFG_SET; + } else { + /* Clear SCxFCNF to disable UARTx FIFO */ + UARTx->FCNF = tmp & FCNF_CNFG_CLEAR; + } +} + +/** + * @brief Transfer mode setting. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param TransferMode: Transfer mode. + * This parameter can be: UART_TRANSFER_PROHIBIT, UART_TRANSFER_HALFDPX_RX, + * UART_TRANSFER_HALFDPX_TX or UART_TRANSFER_FULLDPX. + * @retval None + */ +void UART_SetFIFOTransferMode(TSB_SC_TypeDef * UARTx, uint32_t TransferMode) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UART_TRANSFER_MODE(TransferMode)); + + tmp = UARTx->MOD1; + tmp &= MOD1_FDPX_CLEAR; + tmp |= TransferMode; + UARTx->MOD1 = tmp; +} + +/** + * @brief Controls automatic disabling of transmission and reception. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param TRxAutoDisable: Disabling transmission and reception or not. + * This parameter can be: UART_RXTXCNT_NONE or UART_RXTXCNT_AUTODISABLE . + * @retval None + */ +void UART_TRxAutoDisable(TSB_SC_TypeDef * UARTx, UART_TRxDisable TRxAutoDisable) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UATR_TRX_AUTODISABLE(TRxAutoDisable)); + + tmp = UARTx->FCNF; + tmp &= FCNF_BIT567_CLEAR; + if (TRxAutoDisable == UART_RXTXCNT_AUTODISABLE) { + /* Set SCxFCNF to automatic disabling of transmission and reception */ + UARTx->FCNF = tmp | FCNF_RXTXCNT_SET; + } else { + /* Clear SCxFCNF to do none */ + UARTx->FCNF = tmp & FCNF_RXTXCNT_CLEAR; + } +} + +/** + * @brief Enable or disable receive interrupt for receive FIFO. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param NewState: New state of receive interrupt for receive FIFO. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_RxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmp = UARTx->FCNF; + tmp &= FCNF_BIT567_CLEAR; + if (NewState == ENABLE) { + /* Set SCxFCNF to enable receive FIFO interrupt */ + UARTx->FCNF = tmp | FCNF_RFIE_SET; + } else { + /* Clear SCxFCNF to disable receive FIFO interrupt */ + UARTx->FCNF = tmp & FCNF_RFIE_CLEAR; + } +} + +/** + * @brief Enable or disable transmit interrupt for transmit FIFO. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param NewState: New state of transmit interrupt for transmit FIFO. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_TxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmp = UARTx->FCNF; + tmp &= FCNF_BIT567_CLEAR; + if (NewState == ENABLE) { + /* Set SCxFCNF to enable transmit FIFO interrupt */ + UARTx->FCNF = tmp | FCNF_TFIE_SET; + } else { + /* Clear SCxFCNF to disable transmit FIFO interrupt */ + UARTx->FCNF = tmp & FCNF_TFIE_CLEAR; + } +} + +/** + * @brief Bytes used in receive FIFO. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param BytesUsed: Bytes used in receive FIFO. + * This parameter can be: UART_RXFIFO_MAX or UART_RXFIFO_RXFLEVEL. + * @retval None + */ +void UART_RxFIFOByteSel(TSB_SC_TypeDef * UARTx, uint32_t BytesUsed) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UATR_RXFIFO_BYTESUSED(BytesUsed)); + + tmp = UARTx->FCNF; + tmp &= FCNF_BIT567_CLEAR; + tmp &= FCNF_RFST_CLEAR; + tmp |= BytesUsed; + UARTx->FCNF = tmp; +} + +/** + * @brief Receive FIFO fill level to generate receive interrupts. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param RxFIFOLevel: Receive FIFO fill level. + * This parameter can be one of the following values: + * UART_RXFIFO4B_FLEVLE_4_2B, UART_RXFIFO4B_FLEVLE_1_1B, + * UART_RXFIFO4B_FLEVLE_2_2B or UART_RXFIFO4B_FLEVLE_3_1B. + * @retval None + */ +void UART_RxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t RxFIFOLevel) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UART_RXFIFO4B_FLEVLE(RxFIFOLevel)); + + tmp = UARTx->RFC; + tmp &= RFC_4B_RIL_CLEAR; + tmp |= RxFIFOLevel; + UARTx->RFC = tmp; +} + +/** + * @brief Select RX interrupt generation condition. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param RxINTCondition: RX interrupt generation condition. + * This parameter can be: UART_RFIS_REACH_FLEVEL or UART_RFIS_REACH_EXCEED_FLEVEL. + * @retval None + */ +void UART_RxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t RxINTCondition) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UATR_RFIS_CONDITION(RxINTCondition)); + + tmp = UARTx->RFC; + tmp &= RFC_RFIS_CLEAR; + tmp |= RxINTCondition; + UARTx->RFC = tmp; +} + +/** + * @brief Receive FIFO clear. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval None + */ +void UART_RxFIFOClear(TSB_SC_TypeDef * UARTx) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + tmp = UARTx->RFC; + tmp |= TRFC_TRFCS_SET; + UARTx->RFC = tmp; +} + +/** + * @brief Transmit FIFO fill level to generate transmit interrupts. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param TxFIFOLevel: Transmit FIFO fill level. + * This parameter can be one of the following values: + * UART_TXFIFO4B_FLEVLE_0_0B, UART_TXFIFO4B_FLEVLE_1_1B, + * UART_TXFIFO4B_FLEVLE_2_0B or UART_TXFIFO4B_FLEVLE_3_1B. + * @retval None + */ +void UART_TxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t TxFIFOLevel) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UART_TXFIFO4B_FLEVLE(TxFIFOLevel)); + + + tmp = UARTx->TFC; + tmp &= TFC_4B_TIL_CLEAR; + tmp |= TxFIFOLevel; + UARTx->TFC = tmp; +} + +/** + * @brief Select TX interrupt generation condition. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param TxINTCondition: TX interrupt generation condition. + * This parameter can be: UART_TFIS_REACH_FLEVEL or UART_TFIS_REACH_NOREACH_FLEVEL. + * @retval None + */ +void UART_TxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t TxINTCondition) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_UATR_TFIS_CONDITION(TxINTCondition)); + + tmp = UARTx->TFC; + tmp &= TFC_TFIS_CLEAR; + tmp |= TxINTCondition; + UARTx->TFC = tmp; +} + +/** + * @brief Transmit FIFO clear. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval None + */ +void UART_TxFIFOClear(TSB_SC_TypeDef * UARTx) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + tmp = UARTx->TFC; + tmp |= TRFC_TRFCS_SET; + UARTx->TFC = tmp; +} + +/** + * @brief Transmit buffer clear. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval None + */ +void UART_TxBufferClear(TSB_SC_TypeDef * UARTx) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + tmp = UARTx->TFC; + tmp |= TFC_TBCLR_SET; + UARTx->TFC = tmp; +} + +/** + * @brief Status of receive FIFO fill level. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval Receive FIFO fill level status. + */ +uint32_t UART_GetRxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + tmp = UARTx->RST; + tmp &= TRXST_4B_TRLVL_MASK; + /* Return the value */ + return tmp; +} + +/** + * @brief Receive FIFO overrun. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval Receive FIFO overrun status. + */ +uint32_t UART_GetRxFIFOOverRunStatus(TSB_SC_TypeDef * UARTx) +{ + uint32_t tmp = 0U; + uint32_t regval = 0U; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + tmp = UARTx->RST; + if ((tmp & TRXST_TUR_ROR_MASK) == TRXST_TUR_ROR_MASK) { + regval = UART_RXFIFO_OVERRUN; + } else { + /* Do nothing */ + } + /* Return the value */ + return regval; +} + +/** + * @brief Status of transmit FIFO fill level. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval Transmit FIFO fill level status. + */ +uint32_t UART_GetTxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx) +{ + uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + tmp = UARTx->TST; + tmp &= TRXST_4B_TRLVL_MASK; + /* Return the value */ + return tmp; +} + +/** + * @brief Transmit FIFO under run. + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @retval Transmit FIFO under run status. + */ +uint32_t UART_GetTxFIFOUnderRunStatus(TSB_SC_TypeDef * UARTx) +{ + uint32_t tmp = 0U; + uint32_t regval = 0U; + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + + tmp = UARTx->TST; + if ((tmp & TRXST_TUR_ROR_MASK) == TRXST_TUR_ROR_MASK) { + regval = UART_TXFIFO_UNDERRUN; + } else { + /* Do nothing */ + } + /* Return the value */ + return regval; +} + +/** + * @brief Enable or disable the specified UART channel DMA Request By + receive interrupt INTRX + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param NewState: New state of the UART channel in IDLE. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_SetRxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set SCxDMA to enable UARTx DMA Request */ + UARTx->DMA |= DMA_EN1_SET; + } else { + /* Clear SCxDMA to disable UARTx DMA Request */ + UARTx->DMA &= DMA_EN1_CLEAR; + } +} + +/** + * @brief Enable or disable the specified UART channel DMA Request By + receive interrupt INTTX + * @param UARTx: Select the UART channel. + * This parameter can be one of the following values: + * UART0,UART1. + * @param NewState: New state of the UART channel in IDLE. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_SetTxDMAReq(TSB_SC_TypeDef * UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + /* Set SCxDMA to enable UARTx DMA Request */ + UARTx->DMA |= DMA_EN0_SET; + } else { + /* Clear SCxDMA to disable UARTx DMA Request */ + UARTx->DMA &= DMA_EN0_CLEAR; + } +} + +/** + * @brief Selects input clock for prescaler. + * @param SIOx: Select the SIO channel. + * This parameter can be one of the following values: + * SIO0,SIO1. + * @param clock: Selects input clock for prescaler as PhiT0/2 or PhiT0. + * This parameter can be: + * SIO_CLOCK_T0_HALF (PhiT0/2)or SIO_CLOCK_T0(PhiT0) + * @retval None + * @note SIO_SetInputClock need to use before SIO_Init. + */ +void SIO_SetInputClock(TSB_SC_TypeDef * SIOx, uint32_t Clock) +{ + uint32_t tmp = 0U; + assert_param(IS_SIO_PERIPH(SIOx)); + assert_param(IS_SIO_CLOCK(Clock)); + + tmp = SIOx->EN; + tmp &= EN_BRCKSEL_MASK; + tmp |= Clock; + SIOx->EN = tmp; +} + +/** + * @brief Enable the specified SIO channel. + * @param SIOx: Select the SIO channel. + * This parameter can be one of the following values: + * SIO0,SIO1. + * @retval None + */ +void SIO_Enable(TSB_SC_TypeDef * SIOx) +{ + /* Check the parameters */ + assert_param(IS_SIO_PERIPH(SIOx)); + /* Set SCxEN to enable SIOx */ + SIOx->EN |= EN_SIOE_SET; +} + +/** + * @brief Disable the specified SIO channel. + * @param SIOx: Select the SIO channel. + * This parameter can be one of the following values: + * SIO0,SIO1. + * @retval None + */ +void SIO_Disable(TSB_SC_TypeDef * SIOx) +{ + /* Check the parameters */ + assert_param(IS_SIO_PERIPH(SIOx)); + /* Clear SCxEN to disable SIOx */ + SIOx->EN &= EN_SIOE_CLEAR; +} + +/** + * @brief Get received data of the specified SIO channel. + * @param SIOx: Select the SIO channel. + * This parameter can be one of the following values: + * SIO0,SIO1. + * @retval The received data + */ +uint8_t SIO_GetRxData(TSB_SC_TypeDef * SIOx) +{ + uint8_t retval = 0U; + /* Check the parameters */ + assert_param(IS_SIO_PERIPH(SIOx)); + + /* Return received data */ + retval = (uint8_t) SIOx->BUF; + + return retval; +} + +/** + * @brief Set data to be sent and start transmitting via the specified + SIO channel. + * @param SIOx: Select the SIO channel. + * This parameter can be one of the following values: + * SIO0,SIO1. + * @param Data: the data to be sent. + * @retval None + */ +void SIO_SetTxData(TSB_SC_TypeDef * SIOx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_SIO_PERIPH(SIOx)); + + SIOx->BUF = (uint32_t) Data; +} + +/** + * @brief Initialize the specified SIO channel. + * @param SIOx: Select the SIO channel. + * This parameter can be one of the following values: + * SIO0,SIO1. + * @param IOClkSel: Selecting clock. + * This parameter can be one of the following values: + * SIO_CLK_SCLKOUTPUT or SIO_CLK_SCLKINPUT. + * @param InitStruct: The structure containing basic SIO configuration. + * @retval None + * @note SIO_SetInputClock need to use before SIO_Init. + */ +void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitStruct) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_POINTER_NOT_NULL(InitStruct)); + assert_param(IS_SIO_PERIPH(SIOx)); + assert_param(IS_SIO_CLK_SEL(IOClkSel)); + assert_param(IS_SIO_SCLKS_TRXD(InitStruct->InputClkEdge)); + assert_param(IS_SIO_TIDLE_LEVEL(InitStruct->TIDLE)); + assert_param(IS_SIO_TRANSFER_MODE(InitStruct->TransferMode)); + assert_param(IS_SIO_TRANS_DIR(InitStruct->TransferDir)); + assert_param(IS_SIO_MODE(InitStruct->Mode)); + assert_param(IS_SIO_WBUF_SET(InitStruct->DoubleBuffer)); + if (IOClkSel == SIO_CLK_SCLKINPUT) { + /* Only used for SCLK pin input mode */ + assert_param(IS_SIO_TXDEMP_LEVEL(InitStruct->TXDEMP)); + assert_param(IS_SIO_EHOLD_TIME(InitStruct->EHOLDTime)); + } else { + /* Only used for baud rate generator(SCLK pin output) mode */ + assert_param(IS_SIO_SINT_TIME(InitStruct->IntervalTime)); + assert_param(IS_SIO_BR_CLOCK(InitStruct->BaudRateClock)); + assert_param(IS_SIO_BR_DIVIDER(InitStruct->Divider)); + } + + /* Configure the transfer mode to I/O interface mode */ + tmp = SIOx->MOD0; + tmp &= MOD0_SM_MASK; + SIOx->MOD0 = tmp; + + /* Selecting the clock(SCLK input or output),input clock edge + for I/O interface mode */ + tmp = SIOx->CR; + tmp &= (CR_IOC_MASK & CR_SCLKS_MASK & CR_TIDLE_MASK); + tmp |= (IOClkSel | InitStruct->InputClkEdge | InitStruct->TIDLE); + + /* Set status of TXDx pin when an under run error is occured + and The last bit hold time of TXDx pin in SCLK input mode */ + if (IOClkSel == SIO_CLK_SCLKINPUT) { + tmp &= (CR_TXDEMP_MASK & CR_EHOLD_MASK); + tmp |= (InitStruct->TXDEMP | InitStruct->EHOLDTime); + } else { + /* Do nothing */ + } + SIOx->CR = tmp; + + /* Set the transfer mode and interval time */ + tmp = SIOx->MOD1; + tmp &= MOD1_FDPX_CLEAR; + tmp |= InitStruct->TransferMode; + /* Set the interval time that valid only for SCLK output mode and double + buffer is enabled */ + if ((IOClkSel == SIO_CLK_SCLKOUTPUT) && (InitStruct->DoubleBuffer == SIO_WBUF_ENABLE)) { + tmp &= MOD1_SINT_MASK; + tmp |= InitStruct->IntervalTime; + } else { + /* Do nothing */ + } + tmp &= MOD1_CLEAR; + SIOx->MOD1 = tmp; + + /* Set the transfer direction and double buffer */ + tmp = SIOx->MOD2; + tmp &= MOD2_DRCHG_MASK; + tmp &= MOD2_WBUF_MASK; + tmp |= (InitStruct->TransferDir | InitStruct->DoubleBuffer); + SIOx->MOD2 = tmp; + + /* Select the input clock for baud rate generator and setting + Division ratio "N" */ + tmp = SIOx->BRCR; + if (IOClkSel == SIO_CLK_SCLKOUTPUT) { + tmp &= BRCR_BRCK_MASK; + tmp &= BRCR_BRS_MASK; + tmp |= (InitStruct->BaudRateClock | InitStruct->Divider); + } else { + /* Do nothing */ + } + tmp &= BRCR_CLEAR; + SIOx->BRCR = tmp; + + /* Enable or disable transmission or reception and both */ + tmp = SIOx->MOD1; + switch (InitStruct->Mode) { + case SIO_ENABLE_RX: + SIOx->MOD0 |= InitStruct->Mode; + tmp &= MOD1_TXE_CLEAR; + break; + case SIO_ENABLE_TX: + tmp |= InitStruct->Mode; + SIOx->MOD0 &= MOD0_RXE_CLEAR; + break; + default: + SIOx->MOD0 |= SIO_ENABLE_RX; + tmp |= SIO_ENABLE_TX; + break; + } + tmp &= MOD1_CLEAR; + SIOx->MOD1 = tmp; +} + +/** @} */ +/* End of group UART_Exported_Functions */ + +/** @} */ +/* End of group UART */ + +/** @} */ +/* End of group TX00_Periph_Driver */ + +#endif /* defined(__TMPM066_UART_H)) */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PeripheralNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PeripheralNames.h new file mode 100644 index 0000000000..0bb14ed38b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PeripheralNames.h @@ -0,0 +1,100 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SERIAL_0 = 0, + SERIAL_1, + INVALID_SERIAL = (int)NC +} UARTName; + +typedef enum { + ADC_A0 = 0, + ADC_A1, + ADC_A2, + ADC_A3, + ADC_A4, + ADC_A5, + ADC_A6, + ADC_A7, + INVALID_ADC = (int)NC +} ADCName; + +typedef enum { + I2C_0 = 0, + I2C_1, + INVALID_I2C = (int)NC +} I2CName; + +typedef enum { + PWM_0 = 0, + PWM_1, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + INVALID_PWM = (int)NC +} PWMName; + +typedef enum { + GPIO_IRQ_0 = 0, + GPIO_IRQ_1, + GPIO_IRQ_2, + GPIO_IRQ_3, + GPIO_IRQ_4, + GPIO_IRQ_5, + INVALID_GPIO_IRQ = (int)NC +} GPIO_IRQName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART SERIAL_0 + +#define MBED_UART0 PC2, PC3 +#define MBED_UART1 PE2, PE1 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C0 PC1, PC0 +#define MBED_I2C1 PG1, PG0 + +#define MBED_ANALOGIN0 A0 +#define MBED_ANALOGIN1 A1 +#define MBED_ANALOGIN2 A2 +#define MBED_ANALOGIN3 A3 +#define MBED_ANALOGIN4 A4 +#define MBED_ANALOGIN5 A5 + +#define MBED_PWMOUT0 PD1 +#define MBED_PWMOUT1 PD2 +#define MBED_PWMOUT2 PD3 +#define MBED_PWMOUT3 PF4 +#define MBED_PWMOUT4 PF5 +#define MBED_PWMOUT5 PJ0 +#define MBED_PWMOUT6 PJ1 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h new file mode 100644 index 0000000000..a791c3f4ea --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h @@ -0,0 +1,115 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xF) +#define PIN_POS(X) ((uint32_t)(X) & 0x7) + +// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction +#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0)) +#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) +#define PIN_DIR(X) ((X) & 0xffff) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INOUT +} PinDirection; + +typedef enum { + // TMPM066 Pin Names + PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PB0 = 1 << 3, PB1, PB2, PB3, + PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, + PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, + PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, + PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PG0 = 6 << 3, PG1, + PH0 = 7 << 3, PH1, PH2, PH3, + PJ0 = 8 << 3, PJ1, PJ2, PJ3, + + // Other mbed Pin Names + LED1 = PB0, + LED2 = PB1, + LED3 = LED1, + LED4 = LED2, + + // External data bus Pin Names + D0 = PE1, + D1 = PE2, + D2 = PE0, + D3 = PD1, + D4 = PJ1, + D5 = PD2, + D6 = PD3, + D7 = PJ2, + D8 = PJ3, + D9 = PF4, + D10 = PF0, + D11 = PF1, + D12 = PF2, + D13 = PF3, + D14 = PC1, + D15 = PC0, + + // Analogue out pins + A0 = PA2, + A1 = PA3, + A2 = PA4, + A3 = PA5, + A4 = PA6, + A5 = PA7, + + // DAP_UART + USBTX = PC2, + USBRX = PC3, + MBEDIF_TXD = USBTX, + MBEDIF_RXD = USBRX, + + // Switches + SW1 = PB2, + SW2 = PB3, + + // I2C pins + SDA = PC1, + SCL = PC0, + I2C_SDA = SDA, + I2C_SCL = SCL, + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + +typedef enum { + PullUp = 0, + PullDown, + PullNone, + OpenDrain, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PortNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PortNames.h new file mode 100644 index 0000000000..97ab0cc533 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PortNames.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB, + PortC, + PortD, + PortE, + PortF, + PortG, + PortH, + PortJ +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c new file mode 100644 index 0000000000..3c8e19ced4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c @@ -0,0 +1,89 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogin_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_wait_api.h" + +#define ADC_10BIT_RANGE 0x3FF + +static const PinMap PinMap_ADC[] = { + {PA0, ADC_A0, PIN_DATA(0, 0)}, + {PA1, ADC_A1, PIN_DATA(0, 0)}, + {PA2, ADC_A2, PIN_DATA(0, 0)}, + {PA3, ADC_A3, PIN_DATA(0, 0)}, + {PA4, ADC_A4, PIN_DATA(0, 0)}, + {PA5, ADC_A5, PIN_DATA(0, 0)}, + {PA6, ADC_A6, PIN_DATA(0, 0)}, + {PA7, ADC_A7, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +void analogin_init(analogin_t *obj, PinName pin) +{ + // Check that pin belong to ADC module + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + // enable clock supply to ADC + CG_SetFcPeriphA(CG_FC_PERIPH_ADC, ENABLE); + CG_SetADCClkSupply(ENABLE); + // Set pin function as ADC + pinmap_pinout(pin, PinMap_ADC); + // Software reset ADC + ADC_SWReset(); + // Set sample hold time and pre-scale clock + ADC_SetClk(ADC_CONVERSION_81_CLOCK, ADC_FC_DIVIDE_LEVEL_8); + // Set input channel + ADC_SetInputChannel(obj->adc); + // Turn VREF on + ADC_SetVref(ENABLE); + // Use fixed-channel single conversion mode + ADC_SetRepeatMode(DISABLE); + ADC_SetScanMode(DISABLE); +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + ADC_ResultTypeDef ret; + + // Assert that ADC channel is valid + MBED_ASSERT(obj->adc != (ADCName) NC); + + // Set input channel + ADC_SetInputChannel(obj->adc); + // Enable Vref + ADC_SetVref(ENABLE); + // Wait at least 3us to ensure the voltage is stable + wait_us(10U); + // Start ADC conversion + ADC_Start(); + // Wait until AD conversion complete + while(ADC_GetConvertState().Bit.NormalComplete != 1) { + // Do nothing + } + // Convert result + ret = ADC_GetConvertResult(obj->adc); + // Disable Vref to go into standby mode + ADC_SetVref(DISABLE); + return (uint16_t)ret.ADCResultValue; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = analogin_read_u16(obj); + return (float)(value * (1.0f / (float)ADC_10BIT_RANGE)); +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h new file mode 100644 index 0000000000..ab04cd5c0f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 32 + +#include "objects.h" +#include "stddef.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TMPM066.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TMPM066.h new file mode 100644 index 0000000000..75017f2f05 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TMPM066.h @@ -0,0 +1,2287 @@ +/** + ******************************************************************************* + * @file TMPM066.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM066' Device Series + * @version V2.0.2.2 (Tentative) + * @date 2016/02/15 + * + *(C)Copyright TOSHIBA CORPORATION 2016 All rights reserved + ******************************************************************************* + */ + +/** @addtogroup TOSHIBA_TX00_MICROCONTROLLER + * @{ + */ + +/** @addtogroup TMPM066 + * @{ + */ + +#ifndef __TMPM066_H__ +#define __TMPM066_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/** Interrupt Number Definition */ + typedef enum IRQn { +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** TMPM066 Specific Interrupt Numbers *******************************************************************/ + INT0_IRQn = 0, /*!< Interrupt Pin0 */ + INT1_IRQn = 1, /*!< Interrupt Pin1 */ + INT2_IRQn = 2, /*!< Interrupt Pin2 */ + INT3_IRQn = 3, /*!< Interrupt Pin3 */ + INT4_IRQn = 4, /*!< Interrupt Pin4 */ + INT5_IRQn = 5, /*!< Interrupt Pin5 */ + INTRX0_IRQn = 6, /*!< Serial reception interrupt(channel0) */ + INTTX0_IRQn = 7, /*!< Serial transmission interrupt(channel0) */ + INTRX1_IRQn = 8, /*!< Serial reception interrupt(channel1) */ + INTTX1_IRQn = 9, /*!< Serial transmission interrupt(channel1) */ + INTSPIRX_IRQn = 10, /*!< SPI serial reception interrupt */ + INTSPITX_IRQn = 11, /*!< SPI serial transmission interrupt */ + INTSPIERR_IRQn = 12, /*!< SPI serial error interrupt */ + INTI2C0_IRQn = 13, /*!< Serial bus interface (channel.0) */ + INTI2C1_IRQn = 14, /*!< Serial bus interface (channel.1) */ + INTDMA_IRQn = 15, /*!< DMAC interrupt */ + INT16A0_IRQn = 16, /*!< 16-bit TMR16A match detection (channel.0) */ + INT16A1_IRQn = 17, /*!< 16-bit TMR16A match detection (channel.1) */ + INTTB0_IRQn = 18, /*!< 16-bit TMRB interrupt(channel.0) */ + INTTB1_IRQn = 19, /*!< 16-bit TMRB interrupt(channel.1) */ + INTTB2_IRQn = 20, /*!< 16-bit TMRB interrupt(channel.2) */ + INTTB3_IRQn = 21, /*!< 16-bit TMRB interrupt(channel.3) */ + INTTB4_IRQn = 22, /*!< 16-bit TMRB interrupt(channel.4) */ + INTTB5_IRQn = 23, /*!< 16-bit TMRB interrupt(channel.5) */ + INTTB6_IRQn = 24, /*!< 16-bit TMRB interrupt(channel.6) */ + INTTB7_IRQn = 25, /*!< 16-bit TMRB interrupt(channel.7) */ + INTI2CS_IRQn = 26, /*!< Serial bus interface for Wakeup(channel.1) */ + INTTMRD_IRQn = 27, /*!< TMRD interrupt */ + INTUSB_IRQn = 28, /*!< USB interrupt */ + INTUSBWKUP_IRQn = 29, /*!< USB wakeup interrupt */ + INTADHP_IRQn = 30, /*!< High Priority A/D conversion interrupt */ + INTAD_IRQn = 31 /*!< Normal A/D conversion completion interrupt */ + } IRQn_Type; + +/** Processor and Core Peripheral Section */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + /** @} *//* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_TMPM066.h" /* TMPM066 System */ + +/** @addtogroup Device_Peripheral_registers + * @{ + */ + +/** Device Specific Peripheral registers structures */ + +/** + * @brief UDC2 AHB Bridge + */ + typedef struct { + __IO uint32_t INTSTS; /*!< Interrupt Status Register */ + __IO uint32_t INTENB; /*!< Interrupt Enable Register */ + __IO uint32_t MWTOUT; /*!< Master Write Timeout Register */ + __IO uint32_t C2STSET; /*!< UDC2 setting */ + __IO uint32_t MSTSET; /*!< DMAC setting */ + __IO uint32_t DMACRDREQ; /*!< DMAC Read request */ + __I uint32_t DMACRDVL; /*!< DMAC Read Value */ + __IO uint32_t UDC2RDREQ; /*!< UDC2 Read Request */ + __I uint32_t UDC2RDVL; /*!< UDC2 Read Value */ + uint32_t RESERVED0[6]; + __IO uint32_t ARBTSET; /*!< Arbiter Setting */ + __IO uint32_t MWSADR; /*!< Master Write Start Address */ + __IO uint32_t MWEADR; /*!< Master Write End Address */ + __I uint32_t MWCADR; /*!< Master Write Current Address */ + __I uint32_t MWAHBADR; /*!< Master Write AHB Address */ + __IO uint32_t MRSADR; /*!< Master Read Start Address */ + __IO uint32_t MREADR; /*!< Master Read End Address */ + __I uint32_t MRCADR; /*!< Master Read Current Address */ + __I uint32_t MRAHBADR; /*!< Master Read AHB Address */ + uint32_t RESERVED1[8]; + __IO uint32_t PWCTL; /*!< Power Detect Control */ + __I uint32_t MSTSTS; /*!< Master Status */ + __I uint32_t TOUTCNT; /*!< Timeout Count */ + } TSB_UDFS_TypeDef; + +/** + * @brief UDC2(USB -Spec2.0 Device contoller) + */ + typedef struct { + __IO uint32_t ADR; /*!< UDC2 Address State */ + __IO uint32_t FRM; /*!< UDC2 Frame */ + uint32_t RESERVED0; + __IO uint32_t CMD; /*!< UDC2 Command */ + __I uint32_t BRQ; /*!< UDC2 bRequest-bmRequest Type */ + __I uint32_t WVL; /*!< UDC2 wValue */ + __I uint32_t WIDX; /*!< UDC2 wIndex */ + __I uint32_t WLGTH; /*!< UDC2 wLength */ + __IO uint32_t INT; /*!< UDC2 INT */ + __IO uint32_t INTEP; /*!< UDC2 INT_EP */ + __IO uint32_t INTEPMSK; /*!< UDC2 INT_EP_MASK */ + __IO uint32_t INTRX0; /*!< UDC2 INT RX DATA0 */ + __IO uint32_t EP0MSZ; /*!< UDC2 EP0 Max Packet Size */ + __I uint32_t EP0STS; /*!< UDC2 EP0 Status */ + __I uint32_t EP0DSZ; /*!< UDC2 EP0 Data Size */ + __IO uint32_t EP0FIFO; /*!< UDC2 EP0 FIFO */ + __IO uint32_t EP1MSZ; /*!< UDC2 EP1 Max Packet Size */ + __IO uint32_t EP1STS; /*!< UDC2 EP1 Status */ + __I uint32_t EP1DSZ; /*!< UDC2 EP1 Data Size */ + __IO uint32_t EP1FIFO; /*!< UDC2 EP1 FIFO */ + __IO uint32_t EP2MSZ; /*!< UDC2 EP2 Max Packet Size */ + __IO uint32_t EP2STS; /*!< UDC2 EP2 Status */ + __I uint32_t EP2DSZ; /*!< UDC2 EP2 Data Size */ + __IO uint32_t EP2FIFO; /*!< UDC2 EP2 FIFO */ + __IO uint32_t EP3MSZ; /*!< UDC2 EP3 Max Packet Size */ + __IO uint32_t EP3STS; /*!< UDC2 EP3 Status */ + __I uint32_t EP3DSZ; /*!< UDC2 EP3 Data Size */ + __IO uint32_t EP3FIFO; /*!< UDC2 EP3 FIFO */ + __IO uint32_t EP4MSZ; /*!< UDC2 EP4 Max Packet Size */ + __IO uint32_t EP4STS; /*!< UDC2 EP4 Status */ + __I uint32_t EP4DSZ; /*!< UDC2 EP4 Data Size */ + __IO uint32_t EP4FIFO; /*!< UDC2 EP4 FIFO */ + uint32_t RESERVED1[44]; + __IO uint32_t INTNAK; /*!< UDC2 INT NAK */ + __IO uint32_t INTNAKMSK; /*!< UDC2 INT NAK MASK */ + } TSB_UDFS2_TypeDef; + +/** + * @brief AO Area register1 + */ + typedef struct { + uint8_t RESERVED0[32]; + __IO uint8_t STOP2INT_032; /*!< STOP2INT I/F Control Register in AO Area */ + __IO uint8_t STOP2INT_033; /*!< STOP2INT I/F Control Register in AO Area */ + __IO uint8_t STOP2INT_034; /*!< STOP2INT I/F Control Register in AO Area */ + __IO uint8_t STOP2INT_035; /*!< STOP2INT I/F Control Register in AO Area */ + __IO uint8_t STOP2INT_036; /*!< STOP2INT I/F Control Register in AO Area */ + __IO uint8_t STOP2INT_037; /*!< STOP2INT I/F Control Register in AO Area */ + __IO uint8_t STOP2INT_038; /*!< STOP2INT I/F Control Register in AO Area */ + __IO uint8_t STOP2INT_039; /*!< STOP2INT I/F Control Register in AO Area */ + } TSB_INTIFAO_TypeDef; + +/** + * @brief AO Area register2 + */ + typedef struct { + uint8_t RESERVED0[2]; + __IO uint8_t RSTFLG; /*!< Reset Flag register */ + __IO uint8_t RSTFLG1; /*!< Reset Flag1 register */ + } TSB_AOREG_TypeDef; + +/** + * @brief I2C Wakeup I/F register + */ + typedef struct { + __IO uint8_t WUPCR1; /*!< I2C Wakeup control register1 */ + __IO uint8_t WUPCR2; /*!< I2C Wakeup control register2 */ + __IO uint8_t WUPCR3; /*!< I2C Wakeup control register3 */ + __I uint8_t WUPSL; /*!< I2C Wakeup Status register */ + } TSB_I2CS_TypeDef; + +/** + * @brief DMA Controller + */ + typedef struct { + __I uint32_t STATUS; /*!< DMA Status Register */ + __O uint32_t CFG; /*!< DMA Configuration Register */ + __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */ + __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base + Pointer Register */ + uint32_t RESERVED0; + __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */ + __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */ + __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */ + __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */ + __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */ + __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */ + __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */ + __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */ + __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */ + __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */ + __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */ + uint32_t RESERVED1[3]; + __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */ + } TSB_DMA_TypeDef; + +/** + * @brief Timer D (Unit0) + */ + typedef struct { + __O uint32_t RUN; /*!< Timer Run Register (Unit0) */ + __IO uint32_t CR; /*!< Timer Control Register (Unit0) */ + __IO uint32_t MOD; /*!< Timer Mode Register (Unit0) */ + __IO uint32_t DMA; /*!< DMA Request Enable Register (Unit0) */ + uint32_t RESERVED0; + __IO uint32_t RG0; /*!< Timer Register0 (Unit0) */ + __IO uint32_t RG1; /*!< Timer Register1 (Unit0) */ + __IO uint32_t RG2; /*!< Timer Register2 (Unit0) */ + __IO uint32_t RG3; /*!< Timer Register3 (Unit0) */ + __IO uint32_t RG4; /*!< Timer Register4 (Unit0) */ + __IO uint32_t RG5; /*!< Timer Register5 (Unit0) */ + uint32_t RESERVED1[13]; + __IO uint32_t HSWB0; /*!< H-SW Control Circuit Register Buffer0 (Unit0) */ + __IO uint32_t HSWB1; /*!< H-SW Control Circuit Register Buffer1 (Unit0) */ + uint32_t RESERVED2[43]; + __I uint32_t CP0; /*!< Compare Register0 (Unit0) */ + __I uint32_t CP1; /*!< Compare Register1 (Unit0) */ + __I uint32_t CP2; /*!< Compare Register2 (Unit0) */ + __I uint32_t CP3; /*!< Compare Register3 (Unit0) */ + __I uint32_t CP4; /*!< Compare Register4 (Unit0) */ + __I uint32_t CP5; /*!< Compare Register5 (Unit0) */ + uint32_t RESERVED3[13]; + __I uint32_t HSW0; /*!< H-SW Control Circuit Register (Unit0) */ + __I uint32_t HSW1; /*!< H-SW Control Circuit Register (Unit0) */ + } TSB_TD0_TypeDef; + +/** + * @brief Timer D common + */ + typedef struct { + __IO uint32_t BCR; /*!< Update Flag Setting Register */ + uint32_t RESERVED0[3]; + __IO uint32_t EN; /*!< Timer Enable Register */ + __IO uint32_t CONF; /*!< Timer Configuration Register */ + } TSB_TD_TypeDef; + +/** + * @brief Timer D (Unit1) + */ + typedef struct { + __IO uint32_t RG0; /*!< Timer Register0 (Unit1) */ + __IO uint32_t RG1; /*!< Timer Register1 (Unit1) */ + __IO uint32_t RG2; /*!< Timer Register2 (Unit1) */ + __IO uint32_t RG3; /*!< Timer Register3 (Unit1) */ + __IO uint32_t RG4; /*!< Timer Register4 (Unit1) */ + uint32_t RESERVED0[10]; + __IO uint32_t HSWB0; /*!< H-SW Control Circuit Register Buffer0 (Unit1) */ + __IO uint32_t HSWB1; /*!< H-SW Control Circuit Register Buffer1 (Unit1) */ + uint32_t RESERVED1[36]; + __O uint32_t RUN; /*!< Timer Run Register (Unit1) */ + __IO uint32_t CR; /*!< Timer Control Register (Unit1) */ + __IO uint32_t MOD; /*!< Timer Mode Register (Unit1) */ + __IO uint32_t DMA; /*!< DMA Request Enable Register (Unit1) */ + uint32_t RESERVED2[7]; + __I uint32_t CP0; /*!< Compare Register0 (Unit1) */ + __I uint32_t CP1; /*!< Compare Register1 (Unit1) */ + __I uint32_t CP2; /*!< Compare Register2 (Unit1) */ + __I uint32_t CP3; /*!< Compare Register3 (Unit1) */ + __I uint32_t CP4; /*!< Compare Register4 (Unit1) */ + uint32_t RESERVED3[10]; + __I uint32_t HSW0; /*!< H-SW Control Circuit Register (Unit1) */ + __I uint32_t HSW1; /*!< H-SW Control Circuit Register (Unit1) */ + } TSB_TD1_TypeDef; + +/** + * @brief 16-bit TimerA + */ + typedef struct { + __IO uint32_t EN; /*!< Enable Register */ + __IO uint32_t RUN; /*!< RUN Register */ + __IO uint32_t CR; /*!< Control Register */ + __IO uint32_t RG; /*!< Timer Register */ + __I uint32_t CP; /*!< Capture Register */ + } TSB_T16A_TypeDef; + +/** + * @brief Serial Interface (TSPI) + */ + typedef struct { + __IO uint32_t CR0; /*!< TSPI Control Register 0 */ + __IO uint32_t CR1; /*!< TSPI Control Register 1 */ + __IO uint32_t CR2; /*!< TSPI Control Register 2 */ + __IO uint32_t CR3; /*!< TSPI Control Register 3 */ + __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ + __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ + __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ + uint32_t RESERVED0[57]; + __IO uint32_t DR; /*!< TSPI Data Register */ + uint32_t RESERVED1[63]; + __IO uint32_t SR; /*!< TSPI Status Register */ + __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ + } TSB_TSPI_TypeDef; + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#pragma anon_unions +#elif (defined (__ICCARM__)) /* ICC Compiler */ +#pragma language=extended +#endif + +/** + * @brief I2C + */ + typedef struct { + __IO uint32_t CR1; /*!< I2C Control Register 1 */ + __IO uint32_t DBR; /*!< Data Buffer Register */ + __IO uint32_t AR; /*!< Bus address Register */ + union { + __O uint32_t CR2; /*!< Control Register 2 */ + __I uint32_t SR; /*!< Status Register */ + }; + __IO uint32_t PRS; /*!< Prescaler clcok setting Register */ + __IO uint32_t IE; /*!< Interrupt Enable Register */ + __IO uint32_t ST; /*!< Interrupt Register */ + __IO uint32_t OP; /*!< Optiononal Function register */ + __I uint32_t PM; /*!< Bus Monitor register */ + __IO uint32_t AR2; /*!< Second Slave address register */ + } TSB_I2C_TypeDef; + +/** + * @brief Port A + */ + typedef struct { + __IO uint32_t DATA; /*!< PA Data Register */ + __IO uint32_t CR; /*!< PA Control Register */ + __IO uint32_t FR1; /*!< PA Function Register 1 */ + uint32_t RESERVED0[7]; + __IO uint32_t OD; /*!< PA Open Drain Control Register */ + __IO uint32_t PUP; /*!< PA Pull-up Control Register */ + __IO uint32_t PDN; /*!< PA Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PA Input Enable Control Register */ + } TSB_PA_TypeDef; + +/** + * @brief Port B + */ + typedef struct { + __IO uint32_t DATA; /*!< PB Data Register */ + __IO uint32_t CR; /*!< PB Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< PB Open Drain Control Register */ + __IO uint32_t PUP; /*!< PB Pull-up Control Register */ + __IO uint32_t PDN; /*!< PB Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PB Input Enable Control Register */ + } TSB_PB_TypeDef; + +/** + * @brief Port C + */ + typedef struct { + __IO uint32_t DATA; /*!< PC Data Register */ + __IO uint32_t CR; /*!< PC Control Register */ + __IO uint32_t FR1; /*!< PC Function Register 1 */ + uint32_t RESERVED0[7]; + __IO uint32_t OD; /*!< PC Open Drain Control Register */ + __IO uint32_t PUP; /*!< PC Pull-up Control Register */ + __IO uint32_t PDN; /*!< PC Pull-Down Control Register */ + __IO uint32_t SEL; /*!< PC input voltage selection Register */ + __IO uint32_t IE; /*!< PC Input Enable Control Register */ + } TSB_PC_TypeDef; + +/** + * @brief Port D + */ + typedef struct { + __IO uint32_t DATA; /*!< PD Data Register */ + __IO uint32_t CR; /*!< PD Control Register */ + __IO uint32_t FR1; /*!< PD Function Register 1 */ + __IO uint32_t FR2; /*!< PD Function Register 2 */ + uint32_t RESERVED0[6]; + __IO uint32_t OD; /*!< PD Open Drain Control Register */ + __IO uint32_t PUP; /*!< PD Pull-up Control Register */ + __IO uint32_t PDN; /*!< PD Pull-Down Control Register */ + __IO uint32_t SEL; /*!< PD input voltage selection Register */ + __IO uint32_t IE; /*!< PD Input Enable Control Register */ + } TSB_PD_TypeDef; + +/** + * @brief Port E + */ + typedef struct { + __IO uint32_t DATA; /*!< PE Data Register */ + __IO uint32_t CR; /*!< PE Control Register */ + __IO uint32_t FR1; /*!< PE Function Register 1 */ + __IO uint32_t FR2; /*!< PE Function Register 2 */ + uint32_t RESERVED0[6]; + __IO uint32_t OD; /*!< PE Open Drain Control Register */ + __IO uint32_t PUP; /*!< PE Pull-up Control Register */ + __IO uint32_t PDN; /*!< PE Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PE Input Enable Control Register */ + } TSB_PE_TypeDef; + +/** + * @brief Port F + */ + typedef struct { + __IO uint32_t DATA; /*!< PF Data Register */ + __IO uint32_t CR; /*!< PF Control Register */ + __IO uint32_t FR1; /*!< PF Function Register 1 */ + __IO uint32_t FR2; /*!< PF Function Register 2 */ + uint32_t RESERVED0[6]; + __IO uint32_t OD; /*!< PF Open Drain Control Register */ + __IO uint32_t PUP; /*!< PF Pull-up Control Register */ + __IO uint32_t PDN; /*!< PF Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PF Input Enable Control Register */ + } TSB_PF_TypeDef; + +/** + * @brief Port G + */ + typedef struct { + __IO uint32_t DATA; /*!< PG Data Register */ + __IO uint32_t CR; /*!< PG Control Register */ + __IO uint32_t FR1; /*!< PG Function Register 1 */ + uint32_t RESERVED0[7]; + __IO uint32_t OD; /*!< PG Open Drain Control Register */ + __IO uint32_t PUP; /*!< PG Pull-up Control Register */ + __IO uint32_t PDN; /*!< PG Pull-Down Control Register */ + __IO uint32_t SEL; /*!< PG input voltage selection Register */ + __IO uint32_t IE; /*!< PG Input Enable Control Register */ + } TSB_PG_TypeDef; + +/** + * @brief Port H + */ + typedef struct { + __IO uint32_t DATA; /*!< PH Data Register */ + __IO uint32_t CR; /*!< PH Control Register */ + __IO uint32_t FR1; /*!< PF Function Register 1 */ + uint32_t RESERVED0[7]; + __IO uint32_t OD; /*!< PH Open Drain Control Register */ + __IO uint32_t PUP; /*!< PH Pull-up Control Register */ + __IO uint32_t PDN; /*!< PH Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PH Input Enable Control Register */ + } TSB_PH_TypeDef; + +/** + * @brief Port J + */ + typedef struct { + __IO uint32_t DATA; /*!< PJ Data Register */ + __IO uint32_t CR; /*!< PJ Control Register */ + __IO uint32_t FR1; /*!< PJ Function Register 1 */ + uint32_t RESERVED0[7]; + __IO uint32_t OD; /*!< PJ Open Drain Control Register */ + __IO uint32_t PUP; /*!< PJ Pull-up Control Register */ + __IO uint32_t PDN; /*!< PJ Pull-Down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< PJ Input Enable Control Register */ + } TSB_PJ_TypeDef; + +/** + * @brief 16-bit Timer/Event Counter (TB) + */ + typedef struct { + __IO uint32_t EN; /*!< TB Enable Register */ + __IO uint32_t RUN; /*!< TB RUN Register */ + __IO uint32_t CR; /*!< TB Control Register */ + __IO uint32_t MOD; /*!< TB Mode Register */ + __IO uint32_t FFCR; /*!< TB Flip-Flop Control Register */ + __I uint32_t ST; /*!< TB Status Register */ + __IO uint32_t IM; /*!< TB Interrupt Mask Register */ + __I uint32_t UC; /*!< TB Read Capture Register */ + __IO uint32_t RG0; /*!< TB RG0 Timer Register */ + __IO uint32_t RG1; /*!< TB RG1 Timer Register */ + __I uint32_t CP0; /*!< TB CP0 Capture Register */ + __I uint32_t CP1; /*!< TB CP1 Capture Register */ + __IO uint32_t DMA; /*!< TB DMA Enable Register */ + } TSB_TB_TypeDef; + +/** + * @brief SC + */ + typedef struct { + __IO uint32_t EN; /*!< SC Enable Register */ + __IO uint32_t BUF; /*!< SC Buffer Register */ + __IO uint32_t CR; /*!< SC Control Register */ + __IO uint32_t MOD0; /*!< SC Mode Control Register 0 */ + __IO uint32_t BRCR; /*!< SC Baud Rate Generator Control Register */ + __IO uint32_t BRADD; /*!< SC Baud Rate Generator Control Register 2 */ + __IO uint32_t MOD1; /*!< SC Mode Control Register 1 */ + __IO uint32_t MOD2; /*!< SC Mode Control Register 2 */ + __IO uint32_t RFC; /*!< SC RX FIFO Configuration Register */ + __IO uint32_t TFC; /*!< SC TX FIFO Configuration Register */ + __I uint32_t RST; /*!< SC RX FIFO Status Register */ + __I uint32_t TST; /*!< SC TX FIFO Status Register */ + __IO uint32_t FCNF; /*!< SC FIFO Configuration Register */ + __IO uint32_t DMA; /*!< SC DMA Request Register */ + } TSB_SC_TypeDef; + +/** + * @brief WDT + */ + typedef struct { + __IO uint32_t MOD; /*!< WD Mode Register */ + __O uint32_t CR; /*!< WD Control Register */ + __I uint32_t FLG; /*!< WD Flag Register */ + } TSB_WD_TypeDef; + +/** + * @brief CG + */ + typedef struct { + __IO uint32_t PROTECT; /*!< Protect Register */ + __IO uint32_t OSCCR; /*!< Oscillation Control Register */ + __IO uint32_t SYSCR; /*!< System clock control register */ + __IO uint32_t STBYCR; /*!< Standby Control Register */ + uint32_t RESERVED0[4]; + __IO uint32_t PLL0SEL; /*!< PLL select register for fsys */ + uint32_t RESERVED1[3]; + __IO uint32_t WUPHCR; /*!< Warmup register for HOSC */ + uint32_t RESERVED2[7]; + __IO uint32_t FSYSENA; /*!< output control register A for fsys clock */ + __O uint32_t FSYSENB; /*!< output control register B for fsys clock */ + uint32_t RESERVED3; + __IO uint32_t SPCLKEN; /*!< Output control register for ADC and TRACE CLOCK */ + __IO uint32_t EXTENDO0; /*!< Optional Function setting Register */ + } TSB_CG_TypeDef; + +/** + * @brief LVD + */ + typedef struct { + __IO uint32_t CR0; /*!< LVD Control register0 */ + __IO uint32_t CR1; /*!< LVD Control register1 */ + } TSB_LVD_TypeDef; + +/** + * @brief SD Area register1 + */ + typedef struct { + uint8_t RESERVED0[16]; + __IO uint8_t STOP1INT_016; /*!< STOP1INT(NMI_LVD) I/F Control Register in SD Area */ + __IO uint8_t STOP1INT_017; /*!< STOP1INT(NMI_LVD) I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_018; /*!< ILDEINT(NMI_WDT) I/F Control Register in SD Area */ + uint8_t RESERVED1[77]; + __IO uint8_t IDLEINT_096; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_097; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_098; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_099; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_100; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_101; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_102; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_103; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_104; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_105; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_106; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_107; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_108; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_109; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_110; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_111; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_112; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_113; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_114; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_115; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_116; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_117; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_118; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_119; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_120; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_121; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_122; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_123; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_124; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_125; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_126; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_127; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_128; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_129; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_130; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_131; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_132; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_133; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_134; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_135; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_136; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_137; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_138; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_139; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_140; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_141; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_142; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_143; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_144; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_145; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_146; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_147; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_148; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_149; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_150; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_151; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_152; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_153; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_154; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_155; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_156; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_157; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_158; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_159; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_160; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_161; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_162; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_163; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_164; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_165; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_166; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_167; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_168; /*!< IDLEINT I/F Control Register in SD Area */ + __IO uint8_t IDLEINT_169; /*!< IDLEINT I/F Control Register in SD Area */ + uint32_t RESERVED2[21]; + __I uint32_t FLAG0; /*!< NMI interrupt status flag register */ + __I uint32_t FLAG1; /*!< interrupt status flag register1 for AO area */ + uint32_t RESERVED3; + __I uint32_t FLAG3; /*!< interrupt status flag register3 for SD area */ + __I uint32_t FLAG4; /*!< interrupt status flag register4 for SD area */ + __I uint32_t FLAG5; /*!< interrupt status flag register5 for SD area */ + } TSB_INTIFSD_TypeDef; + +/** + * @brief ADC + */ + typedef struct { + __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ + __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ + __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ + __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ + __IO uint32_t MOD3; /*!< AD Mode Control Register 3 */ + __IO uint32_t MOD4; /*!< AD Mode Control Register 4 */ + __IO uint32_t MOD5; /*!< AD Mode Control Register 5 */ + __IO uint32_t MOD6; /*!< AD Mode Control Register 6 */ + uint32_t RESERVED0[4]; + __I uint32_t REG0; /*!< AD Conversion Result Register 0 */ + __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ + __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ + __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ + __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ + __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ + __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ + __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ + uint32_t RESERVED1[4]; + __I uint32_t REGSP; /*!< AD Conversion Result Register SP */ + __IO uint32_t CMP0; /*!< AD Conversion Result comparing register0 */ + __IO uint32_t CMP1; /*!< AD Conversion result comparing register1 */ + } TSB_AD_TypeDef; + +/** + * @brief FC + */ + typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t SECBIT; /*!< FC Security Bit Register */ + uint32_t RESERVED1[3]; + __I uint32_t SR; /*!< FC Flash Status Register */ + uint32_t RESERVED2[3]; + __I uint32_t PSRA; /*!< FC Protect status register */ + uint32_t RESERVED3; + __IO uint32_t PMRA; /*!< FC Protect Mask register */ + } TSB_FC_TypeDef; + + +/* Memory map */ +#define FLASH_BASE (0x00000000UL) +#define RAM_BASE (0x20000000UL) +#define PERI_BASE (0x40000000UL) + + +#define TSB_UDFS_BASE (PERI_BASE + 0x0008000UL) +#define TSB_UDFS2_BASE (PERI_BASE + 0x0008200UL) +#define TSB_INTIFAO_BASE (PERI_BASE + 0x0038000UL) +#define TSB_AOREG_BASE (PERI_BASE + 0x0038400UL) +#define TSB_I2CS_BASE (PERI_BASE + 0x0038800UL) +#define TSB_DMA_BASE (PERI_BASE + 0x004C000UL) +#define TSB_TD0_BASE (PERI_BASE + 0x0058000UL) +#define TSB_TD_BASE (PERI_BASE + 0x0058040UL) +#define TSB_TD1_BASE (PERI_BASE + 0x005802CUL) +#define TSB_T16A0_BASE (PERI_BASE + 0x008D000UL) +#define TSB_T16A1_BASE (PERI_BASE + 0x008E000UL) +#define TSB_TSPI0_BASE (PERI_BASE + 0x0098000UL) +#define TSB_I2C0_BASE (PERI_BASE + 0x00A0000UL) +#define TSB_I2C1_BASE (PERI_BASE + 0x00A1000UL) +#define TSB_PA_BASE (PERI_BASE + 0x00C0000UL) +#define TSB_PB_BASE (PERI_BASE + 0x00C0100UL) +#define TSB_PC_BASE (PERI_BASE + 0x00C0200UL) +#define TSB_PD_BASE (PERI_BASE + 0x00C0300UL) +#define TSB_PE_BASE (PERI_BASE + 0x00C0400UL) +#define TSB_PF_BASE (PERI_BASE + 0x00C0500UL) +#define TSB_PG_BASE (PERI_BASE + 0x00C0600UL) +#define TSB_PH_BASE (PERI_BASE + 0x00C0700UL) +#define TSB_PJ_BASE (PERI_BASE + 0x00C0800UL) +#define TSB_TB0_BASE (PERI_BASE + 0x00C4000UL) +#define TSB_TB1_BASE (PERI_BASE + 0x00C4100UL) +#define TSB_TB2_BASE (PERI_BASE + 0x00C4200UL) +#define TSB_TB3_BASE (PERI_BASE + 0x00C4300UL) +#define TSB_TB4_BASE (PERI_BASE + 0x00C4400UL) +#define TSB_TB5_BASE (PERI_BASE + 0x00C4500UL) +#define TSB_TB6_BASE (PERI_BASE + 0x00C4600UL) +#define TSB_TB7_BASE (PERI_BASE + 0x00C4700UL) +#define TSB_SC0_BASE (PERI_BASE + 0x00E1000UL) +#define TSB_SC1_BASE (PERI_BASE + 0x00E1100UL) +#define TSB_WD_BASE (PERI_BASE + 0x00F2000UL) +#define TSB_CG_BASE (PERI_BASE + 0x00F3000UL) +#define TSB_LVD_BASE (PERI_BASE + 0x00F4000UL) +#define TSB_INTIFSD_BASE (PERI_BASE + 0x00F4E00UL) +#define TSB_AD_BASE (PERI_BASE + 0x00FC000UL) +#define TSB_FC_BASE (PERI_BASE + 0x1FFF000UL) + + +/* Peripheral declaration */ +#define TSB_UDFS (( TSB_UDFS_TypeDef *) TSB_UDFS_BASE) +#define TSB_UDFS2 (( TSB_UDFS2_TypeDef *) TSB_UDFS2_BASE) +#define TSB_INTIFAO ((TSB_INTIFAO_TypeDef *)TSB_INTIFAO_BASE) +#define TSB_AOREG (( TSB_AOREG_TypeDef *) TSB_AOREG_BASE) +#define TSB_I2CS (( TSB_I2CS_TypeDef *) TSB_I2CS_BASE) +#define TSB_DMA (( TSB_DMA_TypeDef *) TSB_DMA_BASE) +#define TSB_TD0 (( TSB_TD0_TypeDef *) TSB_TD0_BASE) +#define TSB_TD (( TSB_TD_TypeDef *) TSB_TD_BASE) +#define TSB_TD1 (( TSB_TD1_TypeDef *) TSB_TD1_BASE) +#define TSB_T16A0 (( TSB_T16A_TypeDef *) TSB_T16A0_BASE) +#define TSB_T16A1 (( TSB_T16A_TypeDef *) TSB_T16A1_BASE) +#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) +#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) +#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) +#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) +#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) +#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) +#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) +#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) +#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) +#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) +#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) +#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) +#define TSB_TB0 (( TSB_TB_TypeDef *) TSB_TB0_BASE) +#define TSB_TB1 (( TSB_TB_TypeDef *) TSB_TB1_BASE) +#define TSB_TB2 (( TSB_TB_TypeDef *) TSB_TB2_BASE) +#define TSB_TB3 (( TSB_TB_TypeDef *) TSB_TB3_BASE) +#define TSB_TB4 (( TSB_TB_TypeDef *) TSB_TB4_BASE) +#define TSB_TB5 (( TSB_TB_TypeDef *) TSB_TB5_BASE) +#define TSB_TB6 (( TSB_TB_TypeDef *) TSB_TB6_BASE) +#define TSB_TB7 (( TSB_TB_TypeDef *) TSB_TB7_BASE) +#define TSB_SC0 (( TSB_SC_TypeDef *) TSB_SC0_BASE) +#define TSB_SC1 (( TSB_SC_TypeDef *) TSB_SC1_BASE) +#define TSB_WD (( TSB_WD_TypeDef *) TSB_WD_BASE) +#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) +#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) +#define TSB_INTIFSD ((TSB_INTIFSD_TypeDef *)TSB_INTIFSD_BASE) +#define TSB_AD (( TSB_AD_TypeDef *) TSB_AD_BASE) +#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) + + +/* Bit-Band for Device Specific Peripheral Registers */ +#define BITBAND_OFFSET (0x02000000UL) +#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) +#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) + + + +/* UDC2 AHB Bridge */ +#define TSB_UDFS_INTSTS_INT_SETUP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,0))) +#define TSB_UDFS_INTSTS_INT_STATUS_NAK (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,1))) +#define TSB_UDFS_INTSTS_INT_STATUS (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,2))) +#define TSB_UDFS_INTSTS_INT_RX_ZERO (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,3))) +#define TSB_UDFS_INTSTS_INT_SOF (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,4))) +#define TSB_UDFS_INTSTS_INT_EP0 (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,5))) +#define TSB_UDFS_INTSTS_INT_EP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,6))) +#define TSB_UDFS_INTSTS_INT_NAK (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,7))) +#define TSB_UDFS_INTSTS_INT_SUSPEND_RESUME (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,8))) +#define TSB_UDFS_INTSTS_INT_USB_RESET (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,9))) +#define TSB_UDFS_INTSTS_INT_USB_RESET_END (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,10))) +#define TSB_UDFS_INTSTS_INT_MW_SET_ADD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,17))) +#define TSB_UDFS_INTSTS_INT_MW_END_ADD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,18))) +#define TSB_UDFS_INTSTS_INT_MW_TIMEOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,19))) +#define TSB_UDFS_INTSTS_INT_MW_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,20))) +#define TSB_UDFS_INTSTS_INT_MR_END_ADD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,21))) +#define TSB_UDFS_INTSTS_INT_MR_EP_DSET (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,22))) +#define TSB_UDFS_INTSTS_INT_MR_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,23))) +#define TSB_UDFS_INTSTS_INT_UDC2_REGINT__RD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,24))) +#define TSB_UDFS_INTSTS_INT_DMAC_REG_RD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,25))) +#define TSB_UDFS_INTSTS_INT_POWERDETECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,28))) +#define TSB_UDFS_INTSTS_INT_MW_RERROR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTSTS,29))) +#define TSB_UDFS_INTENB_SUSPEND_RESUME_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,8))) +#define TSB_UDFS_INTENB_RESET_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,9))) +#define TSB_UDFS_INTENB_RESET_END_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,10))) +#define TSB_UDFS_INTENB_MW_SET_ADD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,17))) +#define TSB_UDFS_INTENB_MW_END_ADD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,18))) +#define TSB_UDFS_INTENB_MW_TIMEOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,19))) +#define TSB_UDFS_INTENB_MW_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,20))) +#define TSB_UDFS_INTENB_MR_END_ADD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,21))) +#define TSB_UDFS_INTENB_MR_EP_DSET_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,22))) +#define TSB_UDFS_INTENB_MR_AHBERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,23))) +#define TSB_UDFS_INTENB_UDC2_REG_RD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,24))) +#define TSB_UDFS_INTENB_DMAC_REG_RD_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,25))) +#define TSB_UDFS_INTENB_POWER_DETECT_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,28))) +#define TSB_UDFS_INTENB_MW_RERROR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->INTENB,29))) +#define TSB_UDFS_MWTOUT_TIMEOUT_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->MWTOUT,0))) +#define TSB_UDFS_C2STSET_TX0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->C2STSET,0))) +#define TSB_UDFS_C2STSET_EOPB_ENABLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->C2STSET,4))) +#define TSB_UDFS_DMACRDREQ_DMARDCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->DMACRDREQ,30))) +#define TSB_UDFS_DMACRDREQ_DMARDREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->DMACRDREQ,31))) +#define TSB_UDFS_UDC2RDREQ_UDC2RDCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->UDC2RDREQ,30))) +#define TSB_UDFS_UDC2RDREQ_UDC2RDREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->UDC2RDREQ,31))) +#define TSB_UDFS_ARBTSET_ABTMOD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->ARBTSET,28))) +#define TSB_UDFS_ARBTSET_ABT_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->ARBTSET,31))) +#define TSB_UDFS_PWCTL_USB_RESET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,0))) +#define TSB_UDFS_PWCTL_PW_RESETB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,1))) +#define TSB_UDFS_PWCTL_PW_DETECT (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,2))) +#define TSB_UDFS_PWCTL_PHY_SUSPEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,3))) +#define TSB_UDFS_PWCTL_SUSPEND_X (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,4))) +#define TSB_UDFS_PWCTL_PHY_RESETB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,5))) +#define TSB_UDFS_PWCTL_PHY_REMOTE_WKUP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,6))) +#define TSB_UDFS_PWCTL_WAKEUP_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS->PWCTL,7))) +#define TSB_UDFS_MSTSTS_MWEPDSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,0))) +#define TSB_UDFS_MSTSTS_MREPDSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,1))) +#define TSB_UDFS_MSTSTS_MWBFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,2))) +#define TSB_UDFS_MSTSTS_MRBFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,3))) +#define TSB_UDFS_MSTSTS_MREPEMPTY (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS->MSTSTS,4))) + + +/* UDC2(USB -Spec2.0 Device contoller) */ +#define TSB_UDFS2_ADR_SUSPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,11))) +#define TSB_UDFS2_ADR_EP_BI_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,14))) +#define TSB_UDFS2_ADR_STAGE_ERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->ADR,15))) +#define TSB_UDFS2_FRM_CREATE_SOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->FRM,15))) +#define TSB_UDFS2_CMD_INT_TOGGLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->CMD,15))) +#define TSB_UDFS2_BRQ_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->BRQ,7))) +#define TSB_UDFS2_INT_I_SETUP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,0))) +#define TSB_UDFS2_INT_I_STATUS_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,1))) +#define TSB_UDFS2_INT_I_STATUS (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,2))) +#define TSB_UDFS2_INT_I_RX_DATA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,3))) +#define TSB_UDFS2_INT_I_SOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,4))) +#define TSB_UDFS2_INT_I_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,5))) +#define TSB_UDFS2_INT_I_EP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,6))) +#define TSB_UDFS2_INT_I_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,7))) +#define TSB_UDFS2_INT_M_SETUP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,8))) +#define TSB_UDFS2_INT_M_STATUS_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,9))) +#define TSB_UDFS2_INT_M_STATUS (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,10))) +#define TSB_UDFS2_INT_M_RX_DATA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,11))) +#define TSB_UDFS2_INT_M_SOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,12))) +#define TSB_UDFS2_INT_M_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,13))) +#define TSB_UDFS2_INT_M_EP (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,14))) +#define TSB_UDFS2_INT_M_NAK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INT,15))) +#define TSB_UDFS2_INTEP_I_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,1))) +#define TSB_UDFS2_INTEP_I_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,2))) +#define TSB_UDFS2_INTEP_I_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,3))) +#define TSB_UDFS2_INTEP_I_EP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEP,4))) +#define TSB_UDFS2_INTEPMSK_M_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,0))) +#define TSB_UDFS2_INTEPMSK_M_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,1))) +#define TSB_UDFS2_INTEPMSK_M_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,2))) +#define TSB_UDFS2_INTEPMSK_M_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,3))) +#define TSB_UDFS2_INTEPMSK_M_EP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTEPMSK,4))) +#define TSB_UDFS2_INTRX0_RX_D0_EP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,0))) +#define TSB_UDFS2_INTRX0_RX_D0_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,1))) +#define TSB_UDFS2_INTRX0_RX_D0_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,2))) +#define TSB_UDFS2_INTRX0_RX_D0_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,3))) +#define TSB_UDFS2_INTRX0_RX_D0_EP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTRX0,4))) +#define TSB_UDFS2_EP0MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0MSZ,12))) +#define TSB_UDFS2_EP0MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0MSZ,15))) +#define TSB_UDFS2_EP0STS_EP0_MASK (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP0STS,15))) +#define TSB_UDFS2_EP1MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1MSZ,12))) +#define TSB_UDFS2_EP1MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1MSZ,15))) +#define TSB_UDFS2_EP1STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,7))) +#define TSB_UDFS2_EP1STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,8))) +#define TSB_UDFS2_EP1STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,14))) +#define TSB_UDFS2_EP1STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP1STS,15))) +#define TSB_UDFS2_EP2MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2MSZ,12))) +#define TSB_UDFS2_EP2MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2MSZ,15))) +#define TSB_UDFS2_EP2STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,7))) +#define TSB_UDFS2_EP2STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,8))) +#define TSB_UDFS2_EP2STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,14))) +#define TSB_UDFS2_EP2STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP2STS,15))) +#define TSB_UDFS2_EP3MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3MSZ,12))) +#define TSB_UDFS2_EP3MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3MSZ,15))) +#define TSB_UDFS2_EP3STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,7))) +#define TSB_UDFS2_EP3STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,8))) +#define TSB_UDFS2_EP3STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,14))) +#define TSB_UDFS2_EP3STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP3STS,15))) +#define TSB_UDFS2_EP4MSZ_DSET (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4MSZ,12))) +#define TSB_UDFS2_EP4MSZ_TX_0DATA (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4MSZ,15))) +#define TSB_UDFS2_EP4STS_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,7))) +#define TSB_UDFS2_EP4STS_DISABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,8))) +#define TSB_UDFS2_EP4STS_BUS_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,14))) +#define TSB_UDFS2_EP4STS_PKT_MODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->EP4STS,15))) +#define TSB_UDFS2_INTNAK_I_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,1))) +#define TSB_UDFS2_INTNAK_I_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,2))) +#define TSB_UDFS2_INTNAK_I_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAK,3))) +#define TSB_UDFS2_INTNAKMSK_M_EP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,1))) +#define TSB_UDFS2_INTNAKMSK_M_EP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,2))) +#define TSB_UDFS2_INTNAKMSK_M_EP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_UDFS2->INTNAKMSK,3))) + + +/* AO Area register1 */ +#define TSB_INTIFAO_STOP2INT_032_INT032EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,0))) +#define TSB_INTIFAO_STOP2INT_032_INT032PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,4))) +#define TSB_INTIFAO_STOP2INT_032_INT032NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,5))) +#define TSB_INTIFAO_STOP2INT_032_INT032PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,6))) +#define TSB_INTIFAO_STOP2INT_032_INT032NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_032,7))) +#define TSB_INTIFAO_STOP2INT_033_INT033EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,0))) +#define TSB_INTIFAO_STOP2INT_033_INT033PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,4))) +#define TSB_INTIFAO_STOP2INT_033_INT033NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,5))) +#define TSB_INTIFAO_STOP2INT_033_INT033PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,6))) +#define TSB_INTIFAO_STOP2INT_033_INT033NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_033,7))) +#define TSB_INTIFAO_STOP2INT_034_INT034EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,0))) +#define TSB_INTIFAO_STOP2INT_034_INT034PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,4))) +#define TSB_INTIFAO_STOP2INT_034_INT034NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,5))) +#define TSB_INTIFAO_STOP2INT_034_INT034PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,6))) +#define TSB_INTIFAO_STOP2INT_034_INT034NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_034,7))) +#define TSB_INTIFAO_STOP2INT_035_INT035EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,0))) +#define TSB_INTIFAO_STOP2INT_035_INT035PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,4))) +#define TSB_INTIFAO_STOP2INT_035_INT035NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,5))) +#define TSB_INTIFAO_STOP2INT_035_INT035PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,6))) +#define TSB_INTIFAO_STOP2INT_035_INT035NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_035,7))) +#define TSB_INTIFAO_STOP2INT_036_INT036EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,0))) +#define TSB_INTIFAO_STOP2INT_036_INT036PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,4))) +#define TSB_INTIFAO_STOP2INT_036_INT036NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,5))) +#define TSB_INTIFAO_STOP2INT_036_INT036PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,6))) +#define TSB_INTIFAO_STOP2INT_036_INT036NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_036,7))) +#define TSB_INTIFAO_STOP2INT_037_INT037EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,0))) +#define TSB_INTIFAO_STOP2INT_037_INT037PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,4))) +#define TSB_INTIFAO_STOP2INT_037_INT037NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,5))) +#define TSB_INTIFAO_STOP2INT_037_INT037PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,6))) +#define TSB_INTIFAO_STOP2INT_037_INT037NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_037,7))) +#define TSB_INTIFAO_STOP2INT_038_INT038EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,0))) +#define TSB_INTIFAO_STOP2INT_038_INT038PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,4))) +#define TSB_INTIFAO_STOP2INT_038_INT038NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,5))) +#define TSB_INTIFAO_STOP2INT_038_INT038PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,6))) +#define TSB_INTIFAO_STOP2INT_038_INT038NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_038,7))) +#define TSB_INTIFAO_STOP2INT_039_INT039EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,0))) +#define TSB_INTIFAO_STOP2INT_039_INT039PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,4))) +#define TSB_INTIFAO_STOP2INT_039_INT039NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,5))) +#define TSB_INTIFAO_STOP2INT_039_INT039PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,6))) +#define TSB_INTIFAO_STOP2INT_039_INT039NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFAO->STOP2INT_039,7))) + + +/* AO Area register2 */ +#define TSB_AOREG_RSTFLG_PORF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,0))) +#define TSB_AOREG_RSTFLG_PINRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,3))) +#define TSB_AOREG_RSTFLG_LVDRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG,5))) +#define TSB_AOREG_RSTFLG1_SYSRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG1,0))) +#define TSB_AOREG_RSTFLG1_WDTRSTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_AOREG->RSTFLG1,2))) + + +/* I2C Wakeup I/F register */ +#define TSB_I2CS_WUPCR1_INTEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,0))) +#define TSB_I2CS_WUPCR1_GC (*((uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,1))) +#define TSB_I2CS_WUPCR1_RW (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,3))) +#define TSB_I2CS_WUPCR1_I2RES (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,4))) +#define TSB_I2CS_WUPCR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,5))) +#define TSB_I2CS_WUPCR1_SGCDI (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,6))) +#define TSB_I2CS_WUPCR1_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR1,7))) +#define TSB_I2CS_WUPCR3_WUPSA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPCR3,0))) +#define TSB_I2CS_WUPSL_WUPSA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPSL,1))) +#define TSB_I2CS_WUPSL_WUPSA2 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2CS->WUPSL,2))) + + +/* DMA Controller */ +#define TSB_DMA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMA->STATUS,0))) +#define TSB_DMA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMA->CFG,0))) +#define TSB_DMA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMA->ERRCLR,0))) + + +/* Timer D (Unit0) */ +#define TSB_TD0_RUN_TDRUN (*((__O uint32_t *)BITBAND_PERI(&TSB_TD0->RUN,0))) +#define TSB_TD0_CR_TDRDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,2))) +#define TSB_TD0_CR_TDMDPT00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,4))) +#define TSB_TD0_CR_TDMDPT01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->CR,8))) +#define TSB_TD0_MOD_TDCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,4))) +#define TSB_TD0_MOD_TDIV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,6))) +#define TSB_TD0_MOD_TDIV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->MOD,7))) +#define TSB_TD0_DMA_DMAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->DMA,0))) +#define TSB_TD0_RG2_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->RG2,31))) +#define TSB_TD0_RG4_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->RG4,31))) +#define TSB_TD0_HSWB0_OUTV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->HSWB0,2))) +#define TSB_TD0_HSWB1_OUTV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD0->HSWB1,2))) +#define TSB_TD0_CP2_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->CP2,31))) +#define TSB_TD0_CP4_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->CP4,31))) +#define TSB_TD0_HSW0_OUTV0 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->HSW0,2))) +#define TSB_TD0_HSW1_OUTV1 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD0->HSW1,2))) + + +/* Timer D common */ +#define TSB_TD_BCR_TDSFT00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,0))) +#define TSB_TD_BCR_TDSFT01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,1))) +#define TSB_TD_BCR_TDSFT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,2))) +#define TSB_TD_BCR_TDSFT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,3))) +#define TSB_TD_BCR_PHSCHG (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->BCR,4))) +#define TSB_TD_EN_TDHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,5))) +#define TSB_TD_EN_TDEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,6))) +#define TSB_TD_EN_TDEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD->EN,7))) + + +/* Timer D (Unit1) */ +#define TSB_TD1_RG2_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->RG2,31))) +#define TSB_TD1_RG4_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->RG4,31))) +#define TSB_TD1_HSWB0_OUTV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->HSWB0,2))) +#define TSB_TD1_HSWB1_OUTV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->HSWB1,2))) +#define TSB_TD1_RUN_TDRUN (*((__O uint32_t *)BITBAND_PERI(&TSB_TD1->RUN,0))) +#define TSB_TD1_CR_TDRDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,2))) +#define TSB_TD1_CR_TDMDPT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,4))) +#define TSB_TD1_CR_TDMDPT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->CR,8))) +#define TSB_TD1_MOD_TDCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,4))) +#define TSB_TD1_MOD_TDIV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,6))) +#define TSB_TD1_MOD_TDIV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->MOD,7))) +#define TSB_TD1_DMA_DMAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TD1->DMA,0))) +#define TSB_TD1_CP2_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->CP2,31))) +#define TSB_TD1_CP4_DIR (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->CP4,31))) +#define TSB_TD1_HSW0_OUTV0 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->HSW0,2))) +#define TSB_TD1_HSW1_OUTV1 (*((__I uint32_t *)BITBAND_PERI(&TSB_TD1->HSW1,2))) + + +/* 16-bit TimerA */ +#define TSB_T16A0_EN_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->EN,1))) +#define TSB_T16A0_RUN_RUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->RUN,0))) +#define TSB_T16A0_CR_CLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->CR,0))) +#define TSB_T16A0_CR_FFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A0->CR,7))) + +#define TSB_T16A1_EN_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->EN,1))) +#define TSB_T16A1_RUN_RUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->RUN,0))) +#define TSB_T16A1_CR_CLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->CR,0))) +#define TSB_T16A1_CR_FFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_T16A1->CR,7))) + + +/* Serial Interface (TSPI) */ +#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) +#define TSB_TSPI0_CR1_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,8))) +#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) +#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) +#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) +#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) +#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) +#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) +#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) +#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) +#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) +#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) +#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) +#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) +#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) +#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,8))) +#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) +#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) +#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) +#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) +#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) +#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) +#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) +#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) +#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) +#define TSB_TSPI0_SR_INTTXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) +#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) +#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) +#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) +#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,9))) +#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,10))) +#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,11))) + + +/* I2C */ +#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) +#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) +#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) +#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) +#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) +#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) +#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) +#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) +#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) +#define TSB_I2C0_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) +#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) +#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) +#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) +#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) +#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) +#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) +#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) +#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) +#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) +#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) +#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) +#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) +#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) +#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) +#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) +#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) +#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) +#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) +#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) +#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) +#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) +#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) +#define TSB_I2C0_OP_SAST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) +#define TSB_I2C0_OP_SA2ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) +#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) +#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) +#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) + +#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) +#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) +#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) +#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) +#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) +#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) +#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) +#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) +#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) +#define TSB_I2C1_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) +#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) +#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) +#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) +#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) +#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) +#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) +#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) +#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) +#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) +#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) +#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) +#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) +#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) +#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) +#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) +#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) +#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) +#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) +#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) +#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) +#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) +#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) +#define TSB_I2C1_OP_SAST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) +#define TSB_I2C1_OP_SA2ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) +#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) +#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) +#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) + + +/* Port A */ +#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) +#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) +#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) +#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) +#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) +#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) +#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) +#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) +#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) +#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) +#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) +#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) +#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) +#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) +#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) +#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) +#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) +#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) +#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) +#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) +#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) +#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) +#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) +#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) +#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) +#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) +#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) +#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) +#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) +#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) +#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) +#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) +#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) +#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) +#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) +#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) +#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) +#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) +#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) +#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) +#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) +#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) +#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) +#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) +#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) +#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) +#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) +#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) +#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) + + +/* Port B */ +#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) +#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) +#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) +#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) +#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) +#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) +#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) +#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) +#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) +#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) +#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) +#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) +#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) +#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) +#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) +#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) +#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) +#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) +#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) +#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) +#define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0))) +#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) +#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) +#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) + + +/* Port C */ +#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) +#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) +#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) +#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) +#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) +#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) +#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) +#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) +#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) +#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) +#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) +#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) +#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) +#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) +#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2))) +#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3))) +#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) +#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) +#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) +#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) +#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) +#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) +#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) +#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) +#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) +#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) +#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) +#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) +#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) +#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) +#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) +#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) +#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) +#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) +#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) +#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) +#define TSB_PC_SEL_PC0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->SEL,0))) +#define TSB_PC_SEL_PC1SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->SEL,1))) +#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) +#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) +#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) +#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) +#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) +#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) + + +/* Port D */ +#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) +#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) +#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) +#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) +#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) +#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) +#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) +#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) +#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) +#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) +#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) +#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) +#define TSB_PD_FR1_PD0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,0))) +#define TSB_PD_FR1_PD1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1))) +#define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2))) +#define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3))) +#define TSB_PD_FR1_PD4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4))) +#define TSB_PD_FR2_PD0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,0))) +#define TSB_PD_FR2_PD1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,1))) +#define TSB_PD_FR2_PD2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,2))) +#define TSB_PD_FR2_PD3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,3))) +#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) +#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) +#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) +#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) +#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) +#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) +#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) +#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) +#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) +#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) +#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) +#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) +#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) +#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) +#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) +#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) +#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) +#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) +#define TSB_PD_SEL_PD4SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->SEL,4))) +#define TSB_PD_SEL_PD5SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->SEL,5))) +#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) +#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) +#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) +#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) +#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) +#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) + + +/* Port E */ +#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) +#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) +#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) +#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) +#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) +#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) +#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) +#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) +#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) +#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) +#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) +#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) +#define TSB_PE_FR1_PE0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,0))) +#define TSB_PE_FR1_PE1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1))) +#define TSB_PE_FR1_PE2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2))) +#define TSB_PE_FR1_PE3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3))) +#define TSB_PE_FR1_PE4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4))) +#define TSB_PE_FR1_PE5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5))) +#define TSB_PE_FR2_PE1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,1))) +#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) +#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) +#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) +#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) +#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) +#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) +#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) +#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) +#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) +#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) +#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) +#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) +#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) +#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) +#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) +#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) +#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) +#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) +#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) +#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) +#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) +#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) +#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) +#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) + + +/* Port F */ +#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) +#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) +#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) +#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) +#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) +#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) +#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) +#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) +#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) +#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) +#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) +#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) +#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) +#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) +#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) +#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) +#define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0))) +#define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1))) +#define TSB_PF_FR1_PF2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,2))) +#define TSB_PF_FR1_PF3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,3))) +#define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4))) +#define TSB_PF_FR1_PF5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5))) +#define TSB_PF_FR2_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,0))) +#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) +#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) +#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) +#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) +#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) +#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) +#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) +#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) +#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) +#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) +#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) +#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) +#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) +#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) +#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) +#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) +#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) +#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) +#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) +#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) +#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) +#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) +#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) +#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) +#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) +#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) +#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) +#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) +#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) +#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) +#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) +#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) + + +/* Port G */ +#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) +#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) +#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) +#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) +#define TSB_PG_FR1_PG0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0))) +#define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1))) +#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) +#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) +#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) +#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) +#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) +#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) +#define TSB_PG_SEL_PG0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->SEL,0))) +#define TSB_PG_SEL_PG1SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->SEL,1))) +#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) +#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) + + +/* Port H */ +#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) +#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) +#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) +#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) +#define TSB_PH_CR_PH0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0))) +#define TSB_PH_CR_PH1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1))) +#define TSB_PH_CR_PH2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2))) +#define TSB_PH_CR_PH3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3))) +#define TSB_PH_FR1_PH0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0))) +#define TSB_PH_FR1_PH1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1))) +#define TSB_PH_FR1_PH2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2))) +#define TSB_PH_FR1_PH3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3))) +#define TSB_PH_OD_PH0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0))) +#define TSB_PH_OD_PH1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1))) +#define TSB_PH_OD_PH2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2))) +#define TSB_PH_OD_PH3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3))) +#define TSB_PH_PUP_PH0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0))) +#define TSB_PH_PUP_PH1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1))) +#define TSB_PH_PUP_PH2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2))) +#define TSB_PH_PUP_PH3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3))) +#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) +#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) +#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) +#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) +#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) +#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) +#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) +#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) + + +/* Port J */ +#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) +#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) +#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) +#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) +#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) +#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) +#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) +#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) +#define TSB_PJ_FR1_PJ0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,0))) +#define TSB_PJ_FR1_PJ1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,1))) +#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) +#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) +#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) +#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) +#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) +#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) +#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) +#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) +#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) +#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) +#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) +#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) +#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) +#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) +#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) +#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) + + +/* 16-bit Timer/Event Counter (TB) */ +#define TSB_TB0_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->EN,6))) +#define TSB_TB0_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->EN,7))) +#define TSB_TB0_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->RUN,0))) +#define TSB_TB0_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->RUN,2))) +#define TSB_TB0_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,0))) +#define TSB_TB0_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,1))) +#define TSB_TB0_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,5))) +#define TSB_TB0_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,7))) +#define TSB_TB0_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->MOD,3))) +#define TSB_TB0_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB0->MOD,6))) +#define TSB_TB0_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,2))) +#define TSB_TB0_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,3))) +#define TSB_TB0_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,4))) +#define TSB_TB0_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,5))) +#define TSB_TB0_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,0))) +#define TSB_TB0_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,1))) +#define TSB_TB0_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,2))) +#define TSB_TB0_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,0))) +#define TSB_TB0_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,1))) +#define TSB_TB0_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->DMA,2))) + +#define TSB_TB1_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->EN,6))) +#define TSB_TB1_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->EN,7))) +#define TSB_TB1_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->RUN,0))) +#define TSB_TB1_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->RUN,2))) +#define TSB_TB1_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,0))) +#define TSB_TB1_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,1))) +#define TSB_TB1_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,5))) +#define TSB_TB1_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,7))) +#define TSB_TB1_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->MOD,3))) +#define TSB_TB1_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB1->MOD,6))) +#define TSB_TB1_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,2))) +#define TSB_TB1_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,3))) +#define TSB_TB1_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,4))) +#define TSB_TB1_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,5))) +#define TSB_TB1_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,0))) +#define TSB_TB1_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,1))) +#define TSB_TB1_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,2))) +#define TSB_TB1_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,0))) +#define TSB_TB1_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,1))) +#define TSB_TB1_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->DMA,2))) + +#define TSB_TB2_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->EN,6))) +#define TSB_TB2_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->EN,7))) +#define TSB_TB2_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->RUN,0))) +#define TSB_TB2_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->RUN,2))) +#define TSB_TB2_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,0))) +#define TSB_TB2_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,1))) +#define TSB_TB2_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,5))) +#define TSB_TB2_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,7))) +#define TSB_TB2_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->MOD,3))) +#define TSB_TB2_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB2->MOD,6))) +#define TSB_TB2_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,2))) +#define TSB_TB2_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,3))) +#define TSB_TB2_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,4))) +#define TSB_TB2_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,5))) +#define TSB_TB2_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,0))) +#define TSB_TB2_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,1))) +#define TSB_TB2_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,2))) +#define TSB_TB2_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,0))) +#define TSB_TB2_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,1))) +#define TSB_TB2_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->DMA,2))) + +#define TSB_TB3_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->EN,6))) +#define TSB_TB3_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->EN,7))) +#define TSB_TB3_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->RUN,0))) +#define TSB_TB3_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->RUN,2))) +#define TSB_TB3_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,0))) +#define TSB_TB3_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,1))) +#define TSB_TB3_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,5))) +#define TSB_TB3_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,7))) +#define TSB_TB3_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->MOD,3))) +#define TSB_TB3_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB3->MOD,6))) +#define TSB_TB3_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,2))) +#define TSB_TB3_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,3))) +#define TSB_TB3_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,4))) +#define TSB_TB3_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,5))) +#define TSB_TB3_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,0))) +#define TSB_TB3_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,1))) +#define TSB_TB3_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,2))) +#define TSB_TB3_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,0))) +#define TSB_TB3_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,1))) +#define TSB_TB3_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->DMA,2))) + +#define TSB_TB4_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->EN,6))) +#define TSB_TB4_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->EN,7))) +#define TSB_TB4_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->RUN,0))) +#define TSB_TB4_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->RUN,2))) +#define TSB_TB4_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,0))) +#define TSB_TB4_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,1))) +#define TSB_TB4_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,5))) +#define TSB_TB4_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,7))) +#define TSB_TB4_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->MOD,3))) +#define TSB_TB4_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB4->MOD,6))) +#define TSB_TB4_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,2))) +#define TSB_TB4_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,3))) +#define TSB_TB4_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,4))) +#define TSB_TB4_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,5))) +#define TSB_TB4_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,0))) +#define TSB_TB4_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,1))) +#define TSB_TB4_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,2))) +#define TSB_TB4_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,0))) +#define TSB_TB4_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,1))) +#define TSB_TB4_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->DMA,2))) + +#define TSB_TB5_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->EN,6))) +#define TSB_TB5_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->EN,7))) +#define TSB_TB5_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->RUN,0))) +#define TSB_TB5_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->RUN,2))) +#define TSB_TB5_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,0))) +#define TSB_TB5_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,1))) +#define TSB_TB5_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,5))) +#define TSB_TB5_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,7))) +#define TSB_TB5_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->MOD,3))) +#define TSB_TB5_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB5->MOD,6))) +#define TSB_TB5_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,2))) +#define TSB_TB5_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,3))) +#define TSB_TB5_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,4))) +#define TSB_TB5_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,5))) +#define TSB_TB5_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,0))) +#define TSB_TB5_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,1))) +#define TSB_TB5_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,2))) +#define TSB_TB5_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,0))) +#define TSB_TB5_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,1))) +#define TSB_TB5_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->DMA,2))) + +#define TSB_TB6_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->EN,6))) +#define TSB_TB6_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->EN,7))) +#define TSB_TB6_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->RUN,0))) +#define TSB_TB6_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->RUN,2))) +#define TSB_TB6_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,0))) +#define TSB_TB6_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,1))) +#define TSB_TB6_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,5))) +#define TSB_TB6_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,7))) +#define TSB_TB6_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->MOD,3))) +#define TSB_TB6_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB6->MOD,6))) +#define TSB_TB6_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,2))) +#define TSB_TB6_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,3))) +#define TSB_TB6_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,4))) +#define TSB_TB6_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,5))) +#define TSB_TB6_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,0))) +#define TSB_TB6_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,1))) +#define TSB_TB6_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,2))) +#define TSB_TB6_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,0))) +#define TSB_TB6_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,1))) +#define TSB_TB6_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->DMA,2))) + +#define TSB_TB7_EN_TBHALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->EN,6))) +#define TSB_TB7_EN_TBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->EN,7))) +#define TSB_TB7_RUN_TBRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->RUN,0))) +#define TSB_TB7_RUN_TBPRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->RUN,2))) +#define TSB_TB7_CR_CSSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,0))) +#define TSB_TB7_CR_TRGSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,1))) +#define TSB_TB7_CR_TBSYNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,5))) +#define TSB_TB7_CR_TBWBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,7))) +#define TSB_TB7_MOD_TBCLE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->MOD,3))) +#define TSB_TB7_MOD_TBCP (*((__O uint32_t *)BITBAND_PERI(&TSB_TB7->MOD,6))) +#define TSB_TB7_FFCR_TBE0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,2))) +#define TSB_TB7_FFCR_TBE1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,3))) +#define TSB_TB7_FFCR_TBC0T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,4))) +#define TSB_TB7_FFCR_TBC1T1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,5))) +#define TSB_TB7_IM_TBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,0))) +#define TSB_TB7_IM_TBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,1))) +#define TSB_TB7_IM_TBIMOF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,2))) +#define TSB_TB7_DMA_TBDMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,0))) +#define TSB_TB7_DMA_TBDMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,1))) +#define TSB_TB7_DMA_TBDMAEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->DMA,2))) + + +/* SC */ +#define TSB_SC0_EN_SIOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->EN,0))) +#define TSB_SC0_EN_BRCKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->EN,1))) +#define TSB_SC0_MOD0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,4))) +#define TSB_SC0_MOD0_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,5))) +#define TSB_SC0_MOD0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,6))) +#define TSB_SC0_MOD0_TB8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,7))) +#define TSB_SC0_BRCR_BRADDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->BRCR,6))) +#define TSB_SC0_MOD1_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD1,4))) +#define TSB_SC0_MOD2_WBUF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,2))) +#define TSB_SC0_MOD2_DRCHG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,3))) +#define TSB_SC0_MOD2_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,4))) +#define TSB_SC0_MOD2_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,5))) +#define TSB_SC0_MOD2_RBFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,6))) +#define TSB_SC0_MOD2_TBEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,7))) +#define TSB_SC0_RST_ROR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->RST,7))) +#define TSB_SC0_TST_TUR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC0->TST,7))) +#define TSB_SC0_FCNF_CNFG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,0))) +#define TSB_SC0_FCNF_RXTXCNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,1))) +#define TSB_SC0_FCNF_RFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,2))) +#define TSB_SC0_FCNF_TFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,3))) +#define TSB_SC0_FCNF_RFST (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,4))) +#define TSB_SC0_DMA_DMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->DMA,0))) +#define TSB_SC0_DMA_DMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->DMA,1))) + +#define TSB_SC1_EN_SIOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->EN,0))) +#define TSB_SC1_EN_BRCKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->EN,1))) +#define TSB_SC1_MOD0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,4))) +#define TSB_SC1_MOD0_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,5))) +#define TSB_SC1_MOD0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,6))) +#define TSB_SC1_MOD0_TB8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,7))) +#define TSB_SC1_BRCR_BRADDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->BRCR,6))) +#define TSB_SC1_MOD1_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD1,4))) +#define TSB_SC1_MOD2_WBUF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,2))) +#define TSB_SC1_MOD2_DRCHG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,3))) +#define TSB_SC1_MOD2_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,4))) +#define TSB_SC1_MOD2_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,5))) +#define TSB_SC1_MOD2_RBFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,6))) +#define TSB_SC1_MOD2_TBEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,7))) +#define TSB_SC1_RST_ROR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->RST,7))) +#define TSB_SC1_TST_TUR (*((__I uint32_t *)BITBAND_PERI(&TSB_SC1->TST,7))) +#define TSB_SC1_FCNF_CNFG (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,0))) +#define TSB_SC1_FCNF_RXTXCNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,1))) +#define TSB_SC1_FCNF_RFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,2))) +#define TSB_SC1_FCNF_TFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,3))) +#define TSB_SC1_FCNF_RFST (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,4))) +#define TSB_SC1_DMA_DMAEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->DMA,0))) +#define TSB_SC1_DMA_DMAEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->DMA,1))) + + +/* WDT */ +#define TSB_WD_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,1))) +#define TSB_WD_MOD_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,7))) +#define TSB_WD_FLG_FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_WD->FLG,0))) + + +/* CG */ +#define TSB_CG_OSCCR_IOSCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) +#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) +#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) +#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) +#define TSB_CG_PLL0SEL_PPL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) +#define TSB_CG_PLL0SEL_PLL0ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) +#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) +#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) +#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) +#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) +#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) +#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) +#define TSB_CG_FSYSENA_IPENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,10))) +#define TSB_CG_FSYSENA_IPENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,11))) +#define TSB_CG_FSYSENA_IPENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,12))) +#define TSB_CG_FSYSENA_IPENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,13))) +#define TSB_CG_FSYSENA_IPENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,14))) +#define TSB_CG_FSYSENA_IPENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,15))) +#define TSB_CG_FSYSENA_IPENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,16))) +#define TSB_CG_FSYSENA_IPENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,17))) +#define TSB_CG_FSYSENA_IPENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,18))) +#define TSB_CG_FSYSENB_IPENB28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,28))) +#define TSB_CG_FSYSENB_IPENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,29))) +#define TSB_CG_FSYSENB_IPENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,30))) +#define TSB_CG_FSYSENB_IPENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENB,31))) +#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) +#define TSB_CG_EXTENDO0_USBENA (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,0))) +#define TSB_CG_EXTENDO0_USBSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,1))) +#define TSB_CG_EXTENDO0_EHCLKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,4))) +#define TSB_CG_EXTENDO0_DCLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTENDO0,5))) + + +/* LVD */ +#define TSB_LVD_CR0_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,0))) +#define TSB_LVD_CR0_INTSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,4))) +#define TSB_LVD_CR0_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,5))) +#define TSB_LVD_CR0_RSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,6))) +#define TSB_LVD_CR0_ST (*((__I uint32_t *)BITBAND_PERI(&TSB_LVD->CR0,7))) +#define TSB_LVD_CR1_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,0))) +#define TSB_LVD_CR1_INTSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,4))) +#define TSB_LVD_CR1_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,5))) +#define TSB_LVD_CR1_RSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,6))) +#define TSB_LVD_CR1_ST (*((__I uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,7))) + + +/* SD Area register1 */ +#define TSB_INTIFSD_STOP1INT_016_INT016EN (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,0))) +#define TSB_INTIFSD_STOP1INT_016_INT016PFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,4))) +#define TSB_INTIFSD_STOP1INT_016_INT016NFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,5))) +#define TSB_INTIFSD_STOP1INT_016_INT016PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,6))) +#define TSB_INTIFSD_STOP1INT_016_INT016NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_016,7))) +#define TSB_INTIFSD_STOP1INT_017_INT017EN (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,0))) +#define TSB_INTIFSD_STOP1INT_017_INT017PFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,4))) +#define TSB_INTIFSD_STOP1INT_017_INT017NFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,5))) +#define TSB_INTIFSD_STOP1INT_017_INT017PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,6))) +#define TSB_INTIFSD_STOP1INT_017_INT017NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->STOP1INT_017,7))) +#define TSB_INTIFSD_IDLEINT_018_INT018EN (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,0))) +#define TSB_INTIFSD_IDLEINT_018_INT018PFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,4))) +#define TSB_INTIFSD_IDLEINT_018_INT018NFLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,5))) +#define TSB_INTIFSD_IDLEINT_018_INT018PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,6))) +#define TSB_INTIFSD_IDLEINT_018_INT018NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_018,7))) +#define TSB_INTIFSD_IDLEINT_096_INT096EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,0))) +#define TSB_INTIFSD_IDLEINT_096_INT096PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,4))) +#define TSB_INTIFSD_IDLEINT_096_INT096NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,5))) +#define TSB_INTIFSD_IDLEINT_096_INT096PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,6))) +#define TSB_INTIFSD_IDLEINT_096_INT096NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_096,7))) +#define TSB_INTIFSD_IDLEINT_097_INT097EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,0))) +#define TSB_INTIFSD_IDLEINT_097_INT097PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,4))) +#define TSB_INTIFSD_IDLEINT_097_INT097NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,5))) +#define TSB_INTIFSD_IDLEINT_097_INT097PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,6))) +#define TSB_INTIFSD_IDLEINT_097_INT097NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_097,7))) +#define TSB_INTIFSD_IDLEINT_098_INT098EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,0))) +#define TSB_INTIFSD_IDLEINT_098_INT098PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,4))) +#define TSB_INTIFSD_IDLEINT_098_INT098NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,5))) +#define TSB_INTIFSD_IDLEINT_098_INT098PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,6))) +#define TSB_INTIFSD_IDLEINT_098_INT098NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_098,7))) +#define TSB_INTIFSD_IDLEINT_099_INT099EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,0))) +#define TSB_INTIFSD_IDLEINT_099_INT099PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,4))) +#define TSB_INTIFSD_IDLEINT_099_INT099NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,5))) +#define TSB_INTIFSD_IDLEINT_099_INT099PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,6))) +#define TSB_INTIFSD_IDLEINT_099_INT099NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_099,7))) +#define TSB_INTIFSD_IDLEINT_100_INT100EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,0))) +#define TSB_INTIFSD_IDLEINT_100_INT100PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,4))) +#define TSB_INTIFSD_IDLEINT_100_INT100NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,5))) +#define TSB_INTIFSD_IDLEINT_100_INT100PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,6))) +#define TSB_INTIFSD_IDLEINT_100_INT100NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_100,7))) +#define TSB_INTIFSD_IDLEINT_101_INT101EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,0))) +#define TSB_INTIFSD_IDLEINT_101_INT101PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,4))) +#define TSB_INTIFSD_IDLEINT_101_INT101NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,5))) +#define TSB_INTIFSD_IDLEINT_101_INT101PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,6))) +#define TSB_INTIFSD_IDLEINT_101_INT101NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_101,7))) +#define TSB_INTIFSD_IDLEINT_102_INT102EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,0))) +#define TSB_INTIFSD_IDLEINT_102_INT102PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,4))) +#define TSB_INTIFSD_IDLEINT_102_INT102NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,5))) +#define TSB_INTIFSD_IDLEINT_102_INT102PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,6))) +#define TSB_INTIFSD_IDLEINT_102_INT102NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_102,7))) +#define TSB_INTIFSD_IDLEINT_103_INT103EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,0))) +#define TSB_INTIFSD_IDLEINT_103_INT103PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,4))) +#define TSB_INTIFSD_IDLEINT_103_INT103NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,5))) +#define TSB_INTIFSD_IDLEINT_103_INT103PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,6))) +#define TSB_INTIFSD_IDLEINT_103_INT103NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_103,7))) +#define TSB_INTIFSD_IDLEINT_104_INT104EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,0))) +#define TSB_INTIFSD_IDLEINT_104_INT104PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,4))) +#define TSB_INTIFSD_IDLEINT_104_INT104NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,5))) +#define TSB_INTIFSD_IDLEINT_104_INT104PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,6))) +#define TSB_INTIFSD_IDLEINT_104_INT104NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_104,7))) +#define TSB_INTIFSD_IDLEINT_105_INT105EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,0))) +#define TSB_INTIFSD_IDLEINT_105_INT105PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,4))) +#define TSB_INTIFSD_IDLEINT_105_INT105NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,5))) +#define TSB_INTIFSD_IDLEINT_105_INT105PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,6))) +#define TSB_INTIFSD_IDLEINT_105_INT105NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_105,7))) +#define TSB_INTIFSD_IDLEINT_106_INT106EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,0))) +#define TSB_INTIFSD_IDLEINT_106_INT106PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,4))) +#define TSB_INTIFSD_IDLEINT_106_INT106NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,5))) +#define TSB_INTIFSD_IDLEINT_106_INT106PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,6))) +#define TSB_INTIFSD_IDLEINT_106_INT106NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_106,7))) +#define TSB_INTIFSD_IDLEINT_107_INT107EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,0))) +#define TSB_INTIFSD_IDLEINT_107_INT107PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,4))) +#define TSB_INTIFSD_IDLEINT_107_INT107NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,5))) +#define TSB_INTIFSD_IDLEINT_107_INT107PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,6))) +#define TSB_INTIFSD_IDLEINT_107_INT107NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_107,7))) +#define TSB_INTIFSD_IDLEINT_108_INT108EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,0))) +#define TSB_INTIFSD_IDLEINT_108_INT108PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,4))) +#define TSB_INTIFSD_IDLEINT_108_INT108NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,5))) +#define TSB_INTIFSD_IDLEINT_108_INT108PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,6))) +#define TSB_INTIFSD_IDLEINT_108_INT108NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_108,7))) +#define TSB_INTIFSD_IDLEINT_109_INT109EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,0))) +#define TSB_INTIFSD_IDLEINT_109_INT109PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,4))) +#define TSB_INTIFSD_IDLEINT_109_INT109NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,5))) +#define TSB_INTIFSD_IDLEINT_109_INT109PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,6))) +#define TSB_INTIFSD_IDLEINT_109_INT109NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_109,7))) +#define TSB_INTIFSD_IDLEINT_110_INT110EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,0))) +#define TSB_INTIFSD_IDLEINT_110_INT110PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,4))) +#define TSB_INTIFSD_IDLEINT_110_INT110NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,5))) +#define TSB_INTIFSD_IDLEINT_110_INT110PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,6))) +#define TSB_INTIFSD_IDLEINT_110_INT110NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_110,7))) +#define TSB_INTIFSD_IDLEINT_111_INT111EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,0))) +#define TSB_INTIFSD_IDLEINT_111_INT111PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,4))) +#define TSB_INTIFSD_IDLEINT_111_INT111NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,5))) +#define TSB_INTIFSD_IDLEINT_111_INT111PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,6))) +#define TSB_INTIFSD_IDLEINT_111_INT111NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_111,7))) +#define TSB_INTIFSD_IDLEINT_112_INT112EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,0))) +#define TSB_INTIFSD_IDLEINT_112_INT112PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,4))) +#define TSB_INTIFSD_IDLEINT_112_INT112NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,5))) +#define TSB_INTIFSD_IDLEINT_112_INT112PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,6))) +#define TSB_INTIFSD_IDLEINT_112_INT112NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_112,7))) +#define TSB_INTIFSD_IDLEINT_113_INT113EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,0))) +#define TSB_INTIFSD_IDLEINT_113_INT113PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,4))) +#define TSB_INTIFSD_IDLEINT_113_INT113NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,5))) +#define TSB_INTIFSD_IDLEINT_113_INT113PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,6))) +#define TSB_INTIFSD_IDLEINT_113_INT113NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_113,7))) +#define TSB_INTIFSD_IDLEINT_114_INT114EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,0))) +#define TSB_INTIFSD_IDLEINT_114_INT114PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,4))) +#define TSB_INTIFSD_IDLEINT_114_INT114NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,5))) +#define TSB_INTIFSD_IDLEINT_114_INT114PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,6))) +#define TSB_INTIFSD_IDLEINT_114_INT114NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_114,7))) +#define TSB_INTIFSD_IDLEINT_115_INT115EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,0))) +#define TSB_INTIFSD_IDLEINT_115_INT115PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,4))) +#define TSB_INTIFSD_IDLEINT_115_INT115NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,5))) +#define TSB_INTIFSD_IDLEINT_115_INT115PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,6))) +#define TSB_INTIFSD_IDLEINT_115_INT115NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_115,7))) +#define TSB_INTIFSD_IDLEINT_116_INT116EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,0))) +#define TSB_INTIFSD_IDLEINT_116_INT116PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,4))) +#define TSB_INTIFSD_IDLEINT_116_INT116NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,5))) +#define TSB_INTIFSD_IDLEINT_116_INT116PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,6))) +#define TSB_INTIFSD_IDLEINT_116_INT116NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_116,7))) +#define TSB_INTIFSD_IDLEINT_117_INT117EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,0))) +#define TSB_INTIFSD_IDLEINT_117_INT117PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,4))) +#define TSB_INTIFSD_IDLEINT_117_INT117NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,5))) +#define TSB_INTIFSD_IDLEINT_117_INT117PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,6))) +#define TSB_INTIFSD_IDLEINT_117_INT117NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_117,7))) +#define TSB_INTIFSD_IDLEINT_118_INT118EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,0))) +#define TSB_INTIFSD_IDLEINT_118_INT118PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,4))) +#define TSB_INTIFSD_IDLEINT_118_INT118NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,5))) +#define TSB_INTIFSD_IDLEINT_118_INT118PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,6))) +#define TSB_INTIFSD_IDLEINT_118_INT118NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_118,7))) +#define TSB_INTIFSD_IDLEINT_119_INT119EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,0))) +#define TSB_INTIFSD_IDLEINT_119_INT119PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,4))) +#define TSB_INTIFSD_IDLEINT_119_INT119NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,5))) +#define TSB_INTIFSD_IDLEINT_119_INT119PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,6))) +#define TSB_INTIFSD_IDLEINT_119_INT119NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_119,7))) +#define TSB_INTIFSD_IDLEINT_120_INT120EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,0))) +#define TSB_INTIFSD_IDLEINT_120_INT120PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,4))) +#define TSB_INTIFSD_IDLEINT_120_INT120NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,5))) +#define TSB_INTIFSD_IDLEINT_120_INT120PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,6))) +#define TSB_INTIFSD_IDLEINT_120_INT120NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_120,7))) +#define TSB_INTIFSD_IDLEINT_121_INT121EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,0))) +#define TSB_INTIFSD_IDLEINT_121_INT121PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,4))) +#define TSB_INTIFSD_IDLEINT_121_INT121NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,5))) +#define TSB_INTIFSD_IDLEINT_121_INT121PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,6))) +#define TSB_INTIFSD_IDLEINT_121_INT121NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_121,7))) +#define TSB_INTIFSD_IDLEINT_122_INT122EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,0))) +#define TSB_INTIFSD_IDLEINT_122_INT122PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,4))) +#define TSB_INTIFSD_IDLEINT_122_INT122NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,5))) +#define TSB_INTIFSD_IDLEINT_122_INT122PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,6))) +#define TSB_INTIFSD_IDLEINT_122_INT122NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_122,7))) +#define TSB_INTIFSD_IDLEINT_123_INT123EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,0))) +#define TSB_INTIFSD_IDLEINT_123_INT123PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,4))) +#define TSB_INTIFSD_IDLEINT_123_INT123NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,5))) +#define TSB_INTIFSD_IDLEINT_123_INT123PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,6))) +#define TSB_INTIFSD_IDLEINT_123_INT123NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_123,7))) +#define TSB_INTIFSD_IDLEINT_124_INT124EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,0))) +#define TSB_INTIFSD_IDLEINT_124_INT124PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,4))) +#define TSB_INTIFSD_IDLEINT_124_INT124NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,5))) +#define TSB_INTIFSD_IDLEINT_124_INT124PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,6))) +#define TSB_INTIFSD_IDLEINT_124_INT124NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_124,7))) +#define TSB_INTIFSD_IDLEINT_125_INT125EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,0))) +#define TSB_INTIFSD_IDLEINT_125_INT125PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,4))) +#define TSB_INTIFSD_IDLEINT_125_INT125NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,5))) +#define TSB_INTIFSD_IDLEINT_125_INT125PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,6))) +#define TSB_INTIFSD_IDLEINT_125_INT125NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_125,7))) +#define TSB_INTIFSD_IDLEINT_126_INT126EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,0))) +#define TSB_INTIFSD_IDLEINT_126_INT126PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,4))) +#define TSB_INTIFSD_IDLEINT_126_INT126NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,5))) +#define TSB_INTIFSD_IDLEINT_126_INT126PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,6))) +#define TSB_INTIFSD_IDLEINT_126_INT126NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_126,7))) +#define TSB_INTIFSD_IDLEINT_127_INT127EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,0))) +#define TSB_INTIFSD_IDLEINT_127_INT127PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,4))) +#define TSB_INTIFSD_IDLEINT_127_INT127NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,5))) +#define TSB_INTIFSD_IDLEINT_127_INT127PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,6))) +#define TSB_INTIFSD_IDLEINT_127_INT127NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_127,7))) +#define TSB_INTIFSD_IDLEINT_128_INT128EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,0))) +#define TSB_INTIFSD_IDLEINT_128_INT128PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,4))) +#define TSB_INTIFSD_IDLEINT_128_INT128NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,5))) +#define TSB_INTIFSD_IDLEINT_128_INT128PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,6))) +#define TSB_INTIFSD_IDLEINT_128_INT128NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_128,7))) +#define TSB_INTIFSD_IDLEINT_129_INT129EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,0))) +#define TSB_INTIFSD_IDLEINT_129_INT129PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,4))) +#define TSB_INTIFSD_IDLEINT_129_INT129NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,5))) +#define TSB_INTIFSD_IDLEINT_129_INT129PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,6))) +#define TSB_INTIFSD_IDLEINT_129_INT129NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_129,7))) +#define TSB_INTIFSD_IDLEINT_130_INT130EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,0))) +#define TSB_INTIFSD_IDLEINT_130_INT130PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,4))) +#define TSB_INTIFSD_IDLEINT_130_INT130NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,5))) +#define TSB_INTIFSD_IDLEINT_130_INT130PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,6))) +#define TSB_INTIFSD_IDLEINT_130_INT130NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_130,7))) +#define TSB_INTIFSD_IDLEINT_131_INT131EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,0))) +#define TSB_INTIFSD_IDLEINT_131_INT131PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,4))) +#define TSB_INTIFSD_IDLEINT_131_INT131NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,5))) +#define TSB_INTIFSD_IDLEINT_131_INT131PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,6))) +#define TSB_INTIFSD_IDLEINT_131_INT131NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_131,7))) +#define TSB_INTIFSD_IDLEINT_132_INT132EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,0))) +#define TSB_INTIFSD_IDLEINT_132_INT132PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,4))) +#define TSB_INTIFSD_IDLEINT_132_INT132NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,5))) +#define TSB_INTIFSD_IDLEINT_132_INT132PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,6))) +#define TSB_INTIFSD_IDLEINT_132_INT132NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_132,7))) +#define TSB_INTIFSD_IDLEINT_133_INT133EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,0))) +#define TSB_INTIFSD_IDLEINT_133_INT133PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,4))) +#define TSB_INTIFSD_IDLEINT_133_INT133NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,5))) +#define TSB_INTIFSD_IDLEINT_133_INT133PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,6))) +#define TSB_INTIFSD_IDLEINT_133_INT133NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_133,7))) +#define TSB_INTIFSD_IDLEINT_134_INT134EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,0))) +#define TSB_INTIFSD_IDLEINT_134_INT134PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,4))) +#define TSB_INTIFSD_IDLEINT_134_INT134NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,5))) +#define TSB_INTIFSD_IDLEINT_134_INT134PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,6))) +#define TSB_INTIFSD_IDLEINT_134_INT134NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_134,7))) +#define TSB_INTIFSD_IDLEINT_135_INT135EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,0))) +#define TSB_INTIFSD_IDLEINT_135_INT135PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,4))) +#define TSB_INTIFSD_IDLEINT_135_INT135NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,5))) +#define TSB_INTIFSD_IDLEINT_135_INT135PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,6))) +#define TSB_INTIFSD_IDLEINT_135_INT135NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_135,7))) +#define TSB_INTIFSD_IDLEINT_136_INT136EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,0))) +#define TSB_INTIFSD_IDLEINT_136_INT136PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,4))) +#define TSB_INTIFSD_IDLEINT_136_INT136NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,5))) +#define TSB_INTIFSD_IDLEINT_136_INT136PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,6))) +#define TSB_INTIFSD_IDLEINT_136_INT136NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_136,7))) +#define TSB_INTIFSD_IDLEINT_137_INT137EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,0))) +#define TSB_INTIFSD_IDLEINT_137_INT137PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,4))) +#define TSB_INTIFSD_IDLEINT_137_INT137NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,5))) +#define TSB_INTIFSD_IDLEINT_137_INT137PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,6))) +#define TSB_INTIFSD_IDLEINT_137_INT137NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_137,7))) +#define TSB_INTIFSD_IDLEINT_138_INT138EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,0))) +#define TSB_INTIFSD_IDLEINT_138_INT138PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,4))) +#define TSB_INTIFSD_IDLEINT_138_INT138NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,5))) +#define TSB_INTIFSD_IDLEINT_138_INT138PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,6))) +#define TSB_INTIFSD_IDLEINT_138_INT138NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_138,7))) +#define TSB_INTIFSD_IDLEINT_139_INT139EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,0))) +#define TSB_INTIFSD_IDLEINT_139_INT139PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,4))) +#define TSB_INTIFSD_IDLEINT_139_INT139NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,5))) +#define TSB_INTIFSD_IDLEINT_139_INT139PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,6))) +#define TSB_INTIFSD_IDLEINT_139_INT139NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_139,7))) +#define TSB_INTIFSD_IDLEINT_140_INT140EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,0))) +#define TSB_INTIFSD_IDLEINT_140_INT140PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,4))) +#define TSB_INTIFSD_IDLEINT_140_INT140NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,5))) +#define TSB_INTIFSD_IDLEINT_140_INT140PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,6))) +#define TSB_INTIFSD_IDLEINT_140_INT140NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_140,7))) +#define TSB_INTIFSD_IDLEINT_141_INT141EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,0))) +#define TSB_INTIFSD_IDLEINT_141_INT141PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,4))) +#define TSB_INTIFSD_IDLEINT_141_INT141NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,5))) +#define TSB_INTIFSD_IDLEINT_141_INT141PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,6))) +#define TSB_INTIFSD_IDLEINT_141_INT141NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_141,7))) +#define TSB_INTIFSD_IDLEINT_142_INT142EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,0))) +#define TSB_INTIFSD_IDLEINT_142_INT142PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,4))) +#define TSB_INTIFSD_IDLEINT_142_INT142NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,5))) +#define TSB_INTIFSD_IDLEINT_142_INT142PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,6))) +#define TSB_INTIFSD_IDLEINT_142_INT142NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_142,7))) +#define TSB_INTIFSD_IDLEINT_143_INT143EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,0))) +#define TSB_INTIFSD_IDLEINT_143_INT143PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,4))) +#define TSB_INTIFSD_IDLEINT_143_INT143NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,5))) +#define TSB_INTIFSD_IDLEINT_143_INT143PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,6))) +#define TSB_INTIFSD_IDLEINT_143_INT143NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_143,7))) +#define TSB_INTIFSD_IDLEINT_144_INT144EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,0))) +#define TSB_INTIFSD_IDLEINT_144_INT144PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,4))) +#define TSB_INTIFSD_IDLEINT_144_INT144NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,5))) +#define TSB_INTIFSD_IDLEINT_144_INT144PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,6))) +#define TSB_INTIFSD_IDLEINT_144_INT144NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_144,7))) +#define TSB_INTIFSD_IDLEINT_145_INT145EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,0))) +#define TSB_INTIFSD_IDLEINT_145_INT145PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,4))) +#define TSB_INTIFSD_IDLEINT_145_INT145NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,5))) +#define TSB_INTIFSD_IDLEINT_145_INT145PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,6))) +#define TSB_INTIFSD_IDLEINT_145_INT145NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_145,7))) +#define TSB_INTIFSD_IDLEINT_146_INT146EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,0))) +#define TSB_INTIFSD_IDLEINT_146_INT146PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,4))) +#define TSB_INTIFSD_IDLEINT_146_INT146NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,5))) +#define TSB_INTIFSD_IDLEINT_146_INT146PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,6))) +#define TSB_INTIFSD_IDLEINT_146_INT146NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_146,7))) +#define TSB_INTIFSD_IDLEINT_147_INT147EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,0))) +#define TSB_INTIFSD_IDLEINT_147_INT147PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,4))) +#define TSB_INTIFSD_IDLEINT_147_INT147NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,5))) +#define TSB_INTIFSD_IDLEINT_147_INT147PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,6))) +#define TSB_INTIFSD_IDLEINT_147_INT147NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_147,7))) +#define TSB_INTIFSD_IDLEINT_148_INT148EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,0))) +#define TSB_INTIFSD_IDLEINT_148_INT148PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,4))) +#define TSB_INTIFSD_IDLEINT_148_INT148NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,5))) +#define TSB_INTIFSD_IDLEINT_148_INT148PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,6))) +#define TSB_INTIFSD_IDLEINT_148_INT148NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_148,7))) +#define TSB_INTIFSD_IDLEINT_149_INT149EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,0))) +#define TSB_INTIFSD_IDLEINT_149_INT149PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,4))) +#define TSB_INTIFSD_IDLEINT_149_INT149NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,5))) +#define TSB_INTIFSD_IDLEINT_149_INT149PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,6))) +#define TSB_INTIFSD_IDLEINT_149_INT149NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_149,7))) +#define TSB_INTIFSD_IDLEINT_150_INT150EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,0))) +#define TSB_INTIFSD_IDLEINT_150_INT150PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,4))) +#define TSB_INTIFSD_IDLEINT_150_INT150NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,5))) +#define TSB_INTIFSD_IDLEINT_150_INT150PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,6))) +#define TSB_INTIFSD_IDLEINT_150_INT150NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_150,7))) +#define TSB_INTIFSD_IDLEINT_151_INT151EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,0))) +#define TSB_INTIFSD_IDLEINT_151_INT151PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,4))) +#define TSB_INTIFSD_IDLEINT_151_INT151NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,5))) +#define TSB_INTIFSD_IDLEINT_151_INT151PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,6))) +#define TSB_INTIFSD_IDLEINT_151_INT151NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_151,7))) +#define TSB_INTIFSD_IDLEINT_152_INT152EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,0))) +#define TSB_INTIFSD_IDLEINT_152_INT152PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,4))) +#define TSB_INTIFSD_IDLEINT_152_INT152NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,5))) +#define TSB_INTIFSD_IDLEINT_152_INT152PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,6))) +#define TSB_INTIFSD_IDLEINT_152_INT152NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_152,7))) +#define TSB_INTIFSD_IDLEINT_153_INT153EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,0))) +#define TSB_INTIFSD_IDLEINT_153_INT153PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,4))) +#define TSB_INTIFSD_IDLEINT_153_INT153NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,5))) +#define TSB_INTIFSD_IDLEINT_153_INT153PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,6))) +#define TSB_INTIFSD_IDLEINT_153_INT153NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_153,7))) +#define TSB_INTIFSD_IDLEINT_154_INT154EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,0))) +#define TSB_INTIFSD_IDLEINT_154_INT154PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,4))) +#define TSB_INTIFSD_IDLEINT_154_INT154NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,5))) +#define TSB_INTIFSD_IDLEINT_154_INT154PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,6))) +#define TSB_INTIFSD_IDLEINT_154_INT154NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_154,7))) +#define TSB_INTIFSD_IDLEINT_155_INT155EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,0))) +#define TSB_INTIFSD_IDLEINT_155_INT155PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,4))) +#define TSB_INTIFSD_IDLEINT_155_INT155NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,5))) +#define TSB_INTIFSD_IDLEINT_155_INT155PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,6))) +#define TSB_INTIFSD_IDLEINT_155_INT155NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_155,7))) +#define TSB_INTIFSD_IDLEINT_156_INT156EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,0))) +#define TSB_INTIFSD_IDLEINT_156_INT156PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,4))) +#define TSB_INTIFSD_IDLEINT_156_INT156NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,5))) +#define TSB_INTIFSD_IDLEINT_156_INT156PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,6))) +#define TSB_INTIFSD_IDLEINT_156_INT156NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_156,7))) +#define TSB_INTIFSD_IDLEINT_157_INT157EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,0))) +#define TSB_INTIFSD_IDLEINT_157_INT157PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,4))) +#define TSB_INTIFSD_IDLEINT_157_INT157NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,5))) +#define TSB_INTIFSD_IDLEINT_157_INT157PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,6))) +#define TSB_INTIFSD_IDLEINT_157_INT157NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_157,7))) +#define TSB_INTIFSD_IDLEINT_158_INT158EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,0))) +#define TSB_INTIFSD_IDLEINT_158_INT158PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,4))) +#define TSB_INTIFSD_IDLEINT_158_INT158NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,5))) +#define TSB_INTIFSD_IDLEINT_158_INT158PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,6))) +#define TSB_INTIFSD_IDLEINT_158_INT158NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_158,7))) +#define TSB_INTIFSD_IDLEINT_159_INT159EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,0))) +#define TSB_INTIFSD_IDLEINT_159_INT159PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,4))) +#define TSB_INTIFSD_IDLEINT_159_INT159NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,5))) +#define TSB_INTIFSD_IDLEINT_159_INT159PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,6))) +#define TSB_INTIFSD_IDLEINT_159_INT159NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_159,7))) +#define TSB_INTIFSD_IDLEINT_160_INT160EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,0))) +#define TSB_INTIFSD_IDLEINT_160_INT160PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,4))) +#define TSB_INTIFSD_IDLEINT_160_INT160NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,5))) +#define TSB_INTIFSD_IDLEINT_160_INT160PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,6))) +#define TSB_INTIFSD_IDLEINT_160_INT160NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_160,7))) +#define TSB_INTIFSD_IDLEINT_161_INT161EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,0))) +#define TSB_INTIFSD_IDLEINT_161_INT161PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,4))) +#define TSB_INTIFSD_IDLEINT_161_INT161NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,5))) +#define TSB_INTIFSD_IDLEINT_161_INT161PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,6))) +#define TSB_INTIFSD_IDLEINT_161_INT161NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_161,7))) +#define TSB_INTIFSD_IDLEINT_162_INT162EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,0))) +#define TSB_INTIFSD_IDLEINT_162_INT162PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,4))) +#define TSB_INTIFSD_IDLEINT_162_INT162NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,5))) +#define TSB_INTIFSD_IDLEINT_162_INT162PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,6))) +#define TSB_INTIFSD_IDLEINT_162_INT162NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_162,7))) +#define TSB_INTIFSD_IDLEINT_163_INT163EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,0))) +#define TSB_INTIFSD_IDLEINT_163_INT163PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,4))) +#define TSB_INTIFSD_IDLEINT_163_INT163NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,5))) +#define TSB_INTIFSD_IDLEINT_163_INT163PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,6))) +#define TSB_INTIFSD_IDLEINT_163_INT163NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_163,7))) +#define TSB_INTIFSD_IDLEINT_164_INT164EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,0))) +#define TSB_INTIFSD_IDLEINT_164_INT164PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,4))) +#define TSB_INTIFSD_IDLEINT_164_INT164NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,5))) +#define TSB_INTIFSD_IDLEINT_164_INT164PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,6))) +#define TSB_INTIFSD_IDLEINT_164_INT164NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_164,7))) +#define TSB_INTIFSD_IDLEINT_165_INT165EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,0))) +#define TSB_INTIFSD_IDLEINT_165_INT165PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,4))) +#define TSB_INTIFSD_IDLEINT_165_INT165NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,5))) +#define TSB_INTIFSD_IDLEINT_165_INT165PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,6))) +#define TSB_INTIFSD_IDLEINT_165_INT165NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_165,7))) +#define TSB_INTIFSD_IDLEINT_166_INT166EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,0))) +#define TSB_INTIFSD_IDLEINT_166_INT166PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,4))) +#define TSB_INTIFSD_IDLEINT_166_INT166NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,5))) +#define TSB_INTIFSD_IDLEINT_166_INT166PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,6))) +#define TSB_INTIFSD_IDLEINT_166_INT166NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_166,7))) +#define TSB_INTIFSD_IDLEINT_167_INT167EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,0))) +#define TSB_INTIFSD_IDLEINT_167_INT167PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,4))) +#define TSB_INTIFSD_IDLEINT_167_INT167NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,5))) +#define TSB_INTIFSD_IDLEINT_167_INT167PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,6))) +#define TSB_INTIFSD_IDLEINT_167_INT167NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_167,7))) +#define TSB_INTIFSD_IDLEINT_168_INT168EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,0))) +#define TSB_INTIFSD_IDLEINT_168_INT168PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,4))) +#define TSB_INTIFSD_IDLEINT_168_INT168NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,5))) +#define TSB_INTIFSD_IDLEINT_168_INT168PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,6))) +#define TSB_INTIFSD_IDLEINT_168_INT168NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_168,7))) +#define TSB_INTIFSD_IDLEINT_169_INT169EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,0))) +#define TSB_INTIFSD_IDLEINT_169_INT169PFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,4))) +#define TSB_INTIFSD_IDLEINT_169_INT169NFLG (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,5))) +#define TSB_INTIFSD_IDLEINT_169_INT169PCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,6))) +#define TSB_INTIFSD_IDLEINT_169_INT169NCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_INTIFSD->IDLEINT_169,7))) +#define TSB_INTIFSD_FLAG0_INT16FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,16))) +#define TSB_INTIFSD_FLAG0_INT17FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,17))) +#define TSB_INTIFSD_FLAG0_INT18FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG0,18))) +#define TSB_INTIFSD_FLAG1_INT32FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,0))) +#define TSB_INTIFSD_FLAG1_INT33FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,1))) +#define TSB_INTIFSD_FLAG1_INT34FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,2))) +#define TSB_INTIFSD_FLAG1_INT35FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,3))) +#define TSB_INTIFSD_FLAG1_INT36FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,4))) +#define TSB_INTIFSD_FLAG1_INT37FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,5))) +#define TSB_INTIFSD_FLAG1_INT38FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,6))) +#define TSB_INTIFSD_FLAG1_INT39FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG1,7))) +#define TSB_INTIFSD_FLAG3_INT96FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,0))) +#define TSB_INTIFSD_FLAG3_INT97FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,1))) +#define TSB_INTIFSD_FLAG3_INT98FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,2))) +#define TSB_INTIFSD_FLAG3_INT99FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,3))) +#define TSB_INTIFSD_FLAG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,4))) +#define TSB_INTIFSD_FLAG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,5))) +#define TSB_INTIFSD_FLAG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,6))) +#define TSB_INTIFSD_FLAG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,7))) +#define TSB_INTIFSD_FLAG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,8))) +#define TSB_INTIFSD_FLAG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,9))) +#define TSB_INTIFSD_FLAG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,10))) +#define TSB_INTIFSD_FLAG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,11))) +#define TSB_INTIFSD_FLAG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,12))) +#define TSB_INTIFSD_FLAG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,13))) +#define TSB_INTIFSD_FLAG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,14))) +#define TSB_INTIFSD_FLAG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,15))) +#define TSB_INTIFSD_FLAG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,16))) +#define TSB_INTIFSD_FLAG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,17))) +#define TSB_INTIFSD_FLAG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,18))) +#define TSB_INTIFSD_FLAG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,19))) +#define TSB_INTIFSD_FLAG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,20))) +#define TSB_INTIFSD_FLAG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,21))) +#define TSB_INTIFSD_FLAG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,22))) +#define TSB_INTIFSD_FLAG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,23))) +#define TSB_INTIFSD_FLAG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,24))) +#define TSB_INTIFSD_FLAG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,25))) +#define TSB_INTIFSD_FLAG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,26))) +#define TSB_INTIFSD_FLAG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,27))) +#define TSB_INTIFSD_FLAG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,28))) +#define TSB_INTIFSD_FLAG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,29))) +#define TSB_INTIFSD_FLAG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,30))) +#define TSB_INTIFSD_FLAG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG3,31))) +#define TSB_INTIFSD_FLAG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,0))) +#define TSB_INTIFSD_FLAG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,1))) +#define TSB_INTIFSD_FLAG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,2))) +#define TSB_INTIFSD_FLAG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,3))) +#define TSB_INTIFSD_FLAG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,4))) +#define TSB_INTIFSD_FLAG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,5))) +#define TSB_INTIFSD_FLAG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,6))) +#define TSB_INTIFSD_FLAG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,7))) +#define TSB_INTIFSD_FLAG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,8))) +#define TSB_INTIFSD_FLAG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,9))) +#define TSB_INTIFSD_FLAG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,10))) +#define TSB_INTIFSD_FLAG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,11))) +#define TSB_INTIFSD_FLAG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,12))) +#define TSB_INTIFSD_FLAG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,13))) +#define TSB_INTIFSD_FLAG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,14))) +#define TSB_INTIFSD_FLAG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,15))) +#define TSB_INTIFSD_FLAG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,16))) +#define TSB_INTIFSD_FLAG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,17))) +#define TSB_INTIFSD_FLAG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,18))) +#define TSB_INTIFSD_FLAG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,19))) +#define TSB_INTIFSD_FLAG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,20))) +#define TSB_INTIFSD_FLAG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,21))) +#define TSB_INTIFSD_FLAG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,22))) +#define TSB_INTIFSD_FLAG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,23))) +#define TSB_INTIFSD_FLAG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG4,24))) +#define TSB_INTIFSD_FLAG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,0))) +#define TSB_INTIFSD_FLAG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,1))) +#define TSB_INTIFSD_FLAG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,2))) +#define TSB_INTIFSD_FLAG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,3))) +#define TSB_INTIFSD_FLAG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,4))) +#define TSB_INTIFSD_FLAG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,5))) +#define TSB_INTIFSD_FLAG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,6))) +#define TSB_INTIFSD_FLAG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,7))) +#define TSB_INTIFSD_FLAG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,8))) +#define TSB_INTIFSD_FLAG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_INTIFSD->FLAG5,9))) + + +/* ADC */ +#define TSB_AD_MOD1_I2AD (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,6))) +#define TSB_AD_MOD1_VREFON (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,7))) +#define TSB_AD_MOD3_ADOBSV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD3,0))) +#define TSB_AD_MOD3_ADOBIC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD3,5))) +#define TSB_AD_MOD4_ADHTG (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,4))) +#define TSB_AD_MOD4_ADHS (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,5))) +#define TSB_AD_MOD4_HADHTG (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,6))) +#define TSB_AD_MOD4_HADHS (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD4,7))) +#define TSB_AD_MOD5_ADOBSV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD5,0))) +#define TSB_AD_MOD5_ADOBIC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD5,5))) +#define TSB_AD_MOD6_ADDMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,0))) +#define TSB_AD_MOD6_ADHPDMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,1))) +#define TSB_AD_MOD6_ADM0DMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,2))) +#define TSB_AD_MOD6_ADM1DMA (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD6,3))) + + /** @} *//* End of group Device_Peripheral_registers */ + +#ifdef __cplusplus +} +#endif +#endif /* __TMPM066_H__ */ + +/** @} *//* End of group TMPM066 */ +/** @} *//* End of group TOSHIBA_TX00_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/startup_TMPM066.S b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/startup_TMPM066.S new file mode 100644 index 0000000000..71d7da483e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/startup_TMPM066.S @@ -0,0 +1,190 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM066.S +; * @brief CMSIS Cortex-M0 Core Device Startup File for the +; * TOSHIBA 'TMPM066' Device Series +; * @version V2.0.2.1 (Tentative) +; * @date 2015/08/05 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved +; ******************************************************************************* +; */ + +__initial_sp EQU 0x20004000 ; Top of RAM (16KB) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT0_IRQHandler ; 0: Interrupt Pin0 + DCD INT1_IRQHandler ; 1: Interrupt Pin1 + DCD INT2_IRQHandler ; 2: Interrupt Pin2 + DCD INT3_IRQHandler ; 3: Interrupt Pin3 + DCD INT4_IRQHandler ; 4: Interrupt Pin4 + DCD INT5_IRQHandler ; 5: Interrupt Pin5 + DCD INTRX0_IRQHandler ; 6: Serial reception interrupt(channel0) + DCD INTTX0_IRQHandler ; 7: Serial transmission interrupt(channel0) + DCD INTRX1_IRQHandler ; 8: Serial reception interrupt(channel1) + DCD INTTX1_IRQHandler ; 9: Serial transmission interrupt(channel1) + DCD INTSPIRX_IRQHandler ; 10: SPI serial reception interrupt + DCD INTSPITX_IRQHandler ; 11: SPI serial transmission interrupt + DCD INTSPIERR_IRQHandler ; 12: SPI serial error interrupt + DCD INTI2C0_IRQHandler ; 13: Serial bus interface (channel.0) + DCD INTI2C1_IRQHandler ; 14: Serial bus interface (channel.1) + DCD INTDMA_IRQHandler ; 15: DMAC interrupt + DCD INT16A0_IRQHandler ; 16: 16-bit TMR16A match detection (channel.0) + DCD INT16A1_IRQHandler ; 17: 16-bit TMR16A match detection (channel.1) + DCD INTTB0_IRQHandler ; 18: 16-bit TMRB interrupt(channel.0) + DCD INTTB1_IRQHandler ; 19: 16-bit TMRB interrupt(channel.1) + DCD INTTB2_IRQHandler ; 20: 16-bit TMRB interrupt(channel.2) + DCD INTTB3_IRQHandler ; 21: 16-bit TMRB interrupt(channel.3) + DCD INTTB4_IRQHandler ; 22: 16-bit TMRB interrupt(channel.4) + DCD INTTB5_IRQHandler ; 23: 16-bit TMRB interrupt(channel.5) + DCD INTTB6_IRQHandler ; 24: 16-bit TMRB interrupt(channel.6) + DCD INTTB7_IRQHandler ; 25: 16-bit TMRB interrupt(channel.7) + DCD INTI2CS_IRQHandler ; 26: Serial bus interface for Wakeup(channel.1) + DCD INTTMRD_IRQHandler ; 27: TMRD interrupt + DCD INTUSB_IRQHandler ; 28: USB interrupt + DCD INTUSBWKUP_IRQHandler ; 29: USB wakeup interrupt + DCD INTADHP_IRQHandler ; 30: High Priority A/D conversion interrupt + DCD INTAD_IRQHandler ; 31: Normal A/D conversion completion interrupt + + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT INT0_IRQHandler [WEAK] + EXPORT INT1_IRQHandler [WEAK] + EXPORT INT2_IRQHandler [WEAK] + EXPORT INT3_IRQHandler [WEAK] + EXPORT INT4_IRQHandler [WEAK] + EXPORT INT5_IRQHandler [WEAK] + EXPORT INTRX0_IRQHandler [WEAK] + EXPORT INTTX0_IRQHandler [WEAK] + EXPORT INTRX1_IRQHandler [WEAK] + EXPORT INTTX1_IRQHandler [WEAK] + EXPORT INTSPIRX_IRQHandler [WEAK] + EXPORT INTSPITX_IRQHandler [WEAK] + EXPORT INTSPIERR_IRQHandler [WEAK] + EXPORT INTI2C0_IRQHandler [WEAK] + EXPORT INTI2C1_IRQHandler [WEAK] + EXPORT INTDMA_IRQHandler [WEAK] + EXPORT INT16A0_IRQHandler [WEAK] + EXPORT INT16A1_IRQHandler [WEAK] + EXPORT INTTB0_IRQHandler [WEAK] + EXPORT INTTB1_IRQHandler [WEAK] + EXPORT INTTB2_IRQHandler [WEAK] + EXPORT INTTB3_IRQHandler [WEAK] + EXPORT INTTB4_IRQHandler [WEAK] + EXPORT INTTB5_IRQHandler [WEAK] + EXPORT INTTB6_IRQHandler [WEAK] + EXPORT INTTB7_IRQHandler [WEAK] + EXPORT INTI2CS_IRQHandler [WEAK] + EXPORT INTTMRD_IRQHandler [WEAK] + EXPORT INTUSB_IRQHandler [WEAK] + EXPORT INTUSBWKUP_IRQHandler [WEAK] + EXPORT INTADHP_IRQHandler [WEAK] + EXPORT INTAD_IRQHandler [WEAK] + +INT0_IRQHandler +INT1_IRQHandler +INT2_IRQHandler +INT3_IRQHandler +INT4_IRQHandler +INT5_IRQHandler +INTRX0_IRQHandler +INTTX0_IRQHandler +INTRX1_IRQHandler +INTTX1_IRQHandler +INTSPIRX_IRQHandler +INTSPITX_IRQHandler +INTSPIERR_IRQHandler +INTI2C0_IRQHandler +INTI2C1_IRQHandler +INTDMA_IRQHandler +INT16A0_IRQHandler +INT16A1_IRQHandler +INTTB0_IRQHandler +INTTB1_IRQHandler +INTTB2_IRQHandler +INTTB3_IRQHandler +INTTB4_IRQHandler +INTTB5_IRQHandler +INTTB6_IRQHandler +INTTB7_IRQHandler +INTI2CS_IRQHandler +INTTMRD_IRQHandler +INTUSB_IRQHandler +INTUSBWKUP_IRQHandler +INTADHP_IRQHandler +INTAD_IRQHandler + + B . + + ENDP + + END diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..2f1024ace8 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/tmpm066fwug.sct b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/tmpm066fwug.sct new file mode 100644 index 0000000000..2fbf781aaa --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_ARM_STD/tmpm066fwug.sct @@ -0,0 +1,32 @@ +;; TMPM066FWUG scatter file + +;; Vector table starts at 0 +;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) +;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) +;; Initial PC == &__main (with LSB set to indicate Thumb) +;; These two values are provided by the library +;; Other vectors must be provided by the user +;; Code starts after the last possible vector +;; Data starts at 0x20000000 +;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) +;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) + +;; Compatible with ISSM model + +LR_IROM1 0x00000000 0x20000 +{ + ER_IROM1 0x00000000 0x20000 + { + *.o (RESET, +First) + *(InRoot$$Sections) + *.o (+RO-CODE) + .ANY2 (+RO-DATA) + .ANY (+RO) + } + + /* 8_byte_aligned(32 + 16 vect * 4 bytes) = 8_byte_aligned(0xC0) */ + RW_IRAM1 0x200000C0 (0x4000 - 0xC0) + { + .ANY (+RW, +ZI) + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/startup_TMPM066.S b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/startup_TMPM066.S new file mode 100644 index 0000000000..1709f1f880 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/startup_TMPM066.S @@ -0,0 +1,220 @@ +/** + ******************************************************************************* + * @file startup_TMPM066.S + * @brief CMSIS Cortex-M0 Core Device Startup File for the + * TOSHIBA 'TMPM066' Device Series + * @version V2.0.2.1 (Tentative) + * @date 2015/08/05 + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + ******************************************************************************* + */ + +.syntax unified +.arch armv6-m + +.section .stack +.align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +.section .stack +.align 3 +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.if Heap_Size +.space Heap_Size +.endif +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + +/* Vector Table */ + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long INT0_IRQHandler // 0: Interrupt Pin0 + .long INT1_IRQHandler // 1: Interrupt Pin1 + .long INT2_IRQHandler // 2: Interrupt Pin2 + .long INT3_IRQHandler // 3: Interrupt Pin3 + .long INT4_IRQHandler // 4: Interrupt Pin4 + .long INT5_IRQHandler // 5: Interrupt Pin5 + .long INTRX0_IRQHandler // 6: Serial reception interrupt(channel0) + .long INTTX0_IRQHandler // 7: Serial transmission interrupt(channel0) + .long INTRX1_IRQHandler // 8: Serial reception interrupt(channel1) + .long INTTX1_IRQHandler // 9: Serial transmission interrupt(channel1) + .long INTSPIRX_IRQHandler // 10: SPI serial reception interrupt + .long INTSPITX_IRQHandler // 11: SPI serial transmission interrupt + .long INTSPIERR_IRQHandler // 12: SPI serial error interrupt + .long INTI2C0_IRQHandler // 13: Serial bus interface (channel.0) + .long INTI2C1_IRQHandler // 14: Serial bus interface (channel.1) + .long INTDMA_IRQHandler // 15: DMAC interrupt + .long INT16A0_IRQHandler // 16: 16-bit TMR16A match detection (channel.0) + .long INT16A1_IRQHandler // 17: 16-bit TMR16A match detection (channel.1) + .long INTTB0_IRQHandler // 18: 16-bit TMRB interrupt(channel.0) + .long INTTB1_IRQHandler // 19: 16-bit TMRB interrupt(channel.1) + .long INTTB2_IRQHandler // 20: 16-bit TMRB interrupt(channel.2) + .long INTTB3_IRQHandler // 21: 16-bit TMRB interrupt(channel.3) + .long INTTB4_IRQHandler // 22: 16-bit TMRB interrupt(channel.4) + .long INTTB5_IRQHandler // 23: 16-bit TMRB interrupt(channel.5) + .long INTTB6_IRQHandler // 24: 16-bit TMRB interrupt(channel.6) + .long INTTB7_IRQHandler // 25: 16-bit TMRB interrupt(channel.7) + .long INTI2CS_IRQHandler // 26: Serial bus interface for Wakeup(channel.1) + .long INTTMRD_IRQHandler // 27: TMRD interrupt + .long INTUSB_IRQHandler // 28: USB interrupt + .long INTUSBWKUP_IRQHandler // 29: USB wakeup interrupt + .long INTADHP_IRQHandler // 30: High Priority A/D conversion interrupt + .long INTAD_IRQHandler // 31: Normal A/D conversion completion interrupt + .size __isr_vector, . - __isr_vector + +/* Reset Handler */ + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function + Reset_Handler: + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 + .Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop + .Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text + /* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function + \handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler SVC_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler INT0_IRQHandler + def_irq_default_handler INT1_IRQHandler + def_irq_default_handler INT2_IRQHandler + def_irq_default_handler INT3_IRQHandler + def_irq_default_handler INT4_IRQHandler + def_irq_default_handler INT5_IRQHandler + def_irq_default_handler INTRX0_IRQHandler + def_irq_default_handler INTTX0_IRQHandler + def_irq_default_handler INTRX1_IRQHandler + def_irq_default_handler INTTX1_IRQHandler + def_irq_default_handler INTSPIRX_IRQHandler + def_irq_default_handler INTSPITX_IRQHandler + def_irq_default_handler INTSPIERR_IRQHandler + def_irq_default_handler INTI2C0_IRQHandler + def_irq_default_handler INTI2C1_IRQHandler + def_irq_default_handler INTDMA_IRQHandler + def_irq_default_handler INT16A0_IRQHandler + def_irq_default_handler INT16A1_IRQHandler + def_irq_default_handler INTTB0_IRQHandler + def_irq_default_handler INTTB1_IRQHandler + def_irq_default_handler INTTB2_IRQHandler + def_irq_default_handler INTTB3_IRQHandler + def_irq_default_handler INTTB4_IRQHandler + def_irq_default_handler INTTB5_IRQHandler + def_irq_default_handler INTTB6_IRQHandler + def_irq_default_handler INTTB7_IRQHandler + def_irq_default_handler INTI2CS_IRQHandler + def_irq_default_handler INTTMRD_IRQHandler + def_irq_default_handler INTUSB_IRQHandler + def_irq_default_handler INTUSBWKUP_IRQHandler + def_irq_default_handler INTADHP_IRQHandler + def_irq_default_handler INTAD_IRQHandler + + .end diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld new file mode 100644 index 0000000000..8b0048a290 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_GCC_ARM/tmpm066fwug.ld @@ -0,0 +1,150 @@ +/* Linker script for Toshiba TMPM066 */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + Image$$RW_IRAM1$$Base = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + Image$$RW_IRAM1$$ZI$$Limit = . ; + } > RAM + + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/startup_TMPM066.S b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/startup_TMPM066.S new file mode 100644 index 0000000000..3c8738e3e8 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/startup_TMPM066.S @@ -0,0 +1,281 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM066.S +; * @brief CMSIS Cortex-M0 Core Device Startup File for the +; * TOSHIBA 'TMPM066' Device Series +; * @version V2.0.2.1 (Tentative) +; * @date 2015/08/05 +; * +; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved +; ******************************************************************************* +; */ +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT0_IRQHandler ; 0: Interrupt Pin0 + DCD INT1_IRQHandler ; 1: Interrupt Pin1 + DCD INT2_IRQHandler ; 2: Interrupt Pin2 + DCD INT3_IRQHandler ; 3: Interrupt Pin3 + DCD INT4_IRQHandler ; 4: Interrupt Pin4 + DCD INT5_IRQHandler ; 5: Interrupt Pin5 + DCD INTRX0_IRQHandler ; 6: Serial reception interrupt(channel0) + DCD INTTX0_IRQHandler ; 7: Serial transmission interrupt(channel0) + DCD INTRX1_IRQHandler ; 8: Serial reception interrupt(channel1) + DCD INTTX1_IRQHandler ; 9: Serial transmission interrupt(channel1) + DCD INTSPIRX_IRQHandler ; 10: SPI serial reception interrupt + DCD INTSPITX_IRQHandler ; 11: SPI serial transmission interrupt + DCD INTSPIERR_IRQHandler ; 12: SPI serial error interrupt + DCD INTI2C0_IRQHandler ; 13: Serial bus interface (channel.0) + DCD INTI2C1_IRQHandler ; 14: Serial bus interface (channel.1) + DCD INTDMA_IRQHandler ; 15: DMAC interrupt + DCD INT16A0_IRQHandler ; 16: 16-bit TMR16A match detection (channel.0) + DCD INT16A1_IRQHandler ; 17: 16-bit TMR16A match detection (channel.1) + DCD INTTB0_IRQHandler ; 18: 16-bit TMRB interrupt(channel.0) + DCD INTTB1_IRQHandler ; 19: 16-bit TMRB interrupt(channel.1) + DCD INTTB2_IRQHandler ; 20: 16-bit TMRB interrupt(channel.2) + DCD INTTB3_IRQHandler ; 21: 16-bit TMRB interrupt(channel.3) + DCD INTTB4_IRQHandler ; 22: 16-bit TMRB interrupt(channel.4) + DCD INTTB5_IRQHandler ; 23: 16-bit TMRB interrupt(channel.5) + DCD INTTB6_IRQHandler ; 24: 16-bit TMRB interrupt(channel.6) + DCD INTTB7_IRQHandler ; 25: 16-bit TMRB interrupt(channel.7) + DCD INTI2CS_IRQHandler ; 26: Serial bus interface for Wakeup(channel.1) + DCD INTTMRD_IRQHandler ; 27: TMRD interrupt + DCD INTUSB_IRQHandler ; 28: USB interrupt + DCD INTUSBWKUP_IRQHandler ; 29: USB wakeup interrupt + DCD INTADHP_IRQHandler ; 30: High Priority A/D conversion interrupt + DCD INTAD_IRQHandler ; 31: Normal A/D conversion completion interrupt + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT0_IRQHandler + B INT0_IRQHandler + + PUBWEAK INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT1_IRQHandler + B INT1_IRQHandler + + PUBWEAK INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT2_IRQHandler + B INT2_IRQHandler + + PUBWEAK INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT3_IRQHandler + B INT3_IRQHandler + + PUBWEAK INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT4_IRQHandler + B INT4_IRQHandler + + PUBWEAK INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT5_IRQHandler + B INT5_IRQHandler + + PUBWEAK INTRX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTRX0_IRQHandler + B INTRX0_IRQHandler + + PUBWEAK INTTX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTX0_IRQHandler + B INTTX0_IRQHandler + + PUBWEAK INTRX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTRX1_IRQHandler + B INTRX1_IRQHandler + + PUBWEAK INTTX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTX1_IRQHandler + B INTTX1_IRQHandler + + PUBWEAK INTSPIRX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTSPIRX_IRQHandler + B INTSPIRX_IRQHandler + + PUBWEAK INTSPITX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTSPITX_IRQHandler + B INTSPITX_IRQHandler + + PUBWEAK INTSPIERR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTSPIERR_IRQHandler + B INTSPIERR_IRQHandler + + PUBWEAK INTI2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C0_IRQHandler + B INTI2C0_IRQHandler + + PUBWEAK INTI2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2C1_IRQHandler + B INTI2C1_IRQHandler + + PUBWEAK INTDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTDMA_IRQHandler + B INTDMA_IRQHandler + + PUBWEAK INT16A0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT16A0_IRQHandler + B INT16A0_IRQHandler + + PUBWEAK INT16A1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INT16A1_IRQHandler + B INT16A1_IRQHandler + + PUBWEAK INTTB0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTB0_IRQHandler + B INTTB0_IRQHandler + + PUBWEAK INTTB1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTB1_IRQHandler + B INTTB1_IRQHandler + + PUBWEAK INTTB2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTB2_IRQHandler + B INTTB2_IRQHandler + + PUBWEAK INTTB3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTB3_IRQHandler + B INTTB3_IRQHandler + + PUBWEAK INTTB4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTB4_IRQHandler + B INTTB4_IRQHandler + + PUBWEAK INTTB5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTB5_IRQHandler + B INTTB5_IRQHandler + + PUBWEAK INTTB6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTB6_IRQHandler + B INTTB6_IRQHandler + + PUBWEAK INTTB7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTB7_IRQHandler + B INTTB7_IRQHandler + + PUBWEAK INTI2CS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTI2CS_IRQHandler + B INTI2CS_IRQHandler + + PUBWEAK INTTMRD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTTMRD_IRQHandler + B INTTMRD_IRQHandler + + PUBWEAK INTUSB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUSB_IRQHandler + B INTUSB_IRQHandler + + PUBWEAK INTUSBWKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTUSBWKUP_IRQHandler + B INTUSBWKUP_IRQHandler + + PUBWEAK INTADHP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTADHP_IRQHandler + B INTADHP_IRQHandler + + PUBWEAK INTAD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +INTAD_IRQHandler + B INTAD_IRQHandler + + END diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf new file mode 100644 index 0000000000..0857f4e510 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/TOOLCHAIN_IAR/tmpm066fwug.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x1400; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis.h new file mode 100644 index 0000000000..df61c39c5a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis.h @@ -0,0 +1,12 @@ +/* mbed Microcontroller Library - CMSIS for TMPM066 + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in TMPM066 specifics + */ +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "TMPM066.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.c new file mode 100644 index 0000000000..dabf0d419d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.c @@ -0,0 +1,33 @@ +/* mbed Microcontroller Library - cmsis_nvic for TMPM066 + * Copyright (c) 2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + static int vector_copied = 0; + uint32_t *vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (vector_copied == 0) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS; + for (i = 0; i < NVIC_NUM_VECTORS; i++) { + vectors[i] = old_vectors[i]; + } + vector_copied = 1; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.h new file mode 100644 index 0000000000..77a40de438 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/cmsis_nvic.h @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library - cmsis_nvic for TMPM066 + * Copyright (c) 2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF +// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM +#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + +#ifdef __cplusplus +extern "C" { +#endif + +/** Set the ISR for IRQn + * + * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM + * the first time this function is called + * @param[in] IRQn The Interrupt Request number for which a vector will be registered + * @param[in] vector The ISR vector to register for IRQn + */ +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); + +/** Get the ISR registered for IRQn + * + * Reads the Interrupt Service Routine currently registered for IRQn + * @param[in] IRQn The Interrupt Request number the vector of which will be read + * @return Returns the ISR registered for IRQn + */ +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.c new file mode 100644 index 0000000000..9e9de9004f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.c @@ -0,0 +1,301 @@ +/** + ******************************************************************************* + * @file system_TMPM066.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for the + * TOSHIBA 'TMPM066' Device Series + * @version V2.0.2.1 + * @date 2015/10/22 + * + * (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved + ******************************************************************************* + */ + +#include "TMPM066.h" + +/*-------- <<< Start of configuration section >>> ----------------------------*/ + +/* Watchdog Timer (WD) Configuration */ +#define WD_SETUP (1U) +#define WDMOD_Val (0x00000000UL) +#define WDCR_Val (0x000000B1UL) + +/* Clock Generator (CG) Configuration */ +#define CLOCK_SETUP (1U) +#define SYSCR_Val (0x00000000UL) +#define OSCCR_Val (0x00000102UL) /* OSCCR = 1, OSCCR = 01 */ + +#define STBYCR_Val (0x00000000UL) + +#define CG_8M_MUL_12_FPLL (0x00C60B00UL<<8U) + +#define CG_10M_MUL_8_FPLL (0x00C60700UL<<8U) + +#define CG_12M_MUL_8_FPLL (0x00C60700UL<<8U) + +#define CG_16M_MUL_6_FPLL (0x00C60500UL<<8U) + + +#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001) +#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE) +#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002) +#define CG_PLL0SEL_PLL0ST_MASK ((uint32_t)0x00000004) + +#define CG_OSCCR_IOSCEN_CLEAR ((uint32_t)0xFFFFFFFE) +#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002) +#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100) +#define CG_OSCCR_OSCF_MASK ((uint32_t)0x00000200) + +#define CG_WUON_START_SET ((uint32_t)0x00000001) +#define CG_WUEF_VALUE_MASK ((uint32_t)0x00000002) +#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100) + +#define WD_MOD_WDTE_SET ((uint32_t)0x00000080) + +#define PLLSEL_Ready CG_12M_MUL_8_FPLL + +#define PLLSEL_Val (PLLSEL_Ready|0x00000003UL) +#define PLLSEL_MASK (0xFFFFFF00UL) + +/*-------- <<< End of configuration section >>> ------------------------------*/ + +/*-------- DEFINES -----------------------------------------------------------*/ +/* Define clocks */ +#define OSC_8M ( 8000000UL) +#define OSC_10M (10000000UL) +#define OSC_12M (12000000UL) +#define OSC_16M (16000000UL) +#define EXTALH OSC_12M /* External high-speed oscillator freq */ +#define XTALH OSC_10M /* Internal high-speed oscillator freq */ + +/* Configure Warm-up time */ +#define HZ_1M (1000000UL) +#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ +#define WU_TIME_PLL (100UL) /* warm-up time for PLL is 100us */ +#define WUPHCR_WUPT_MASK (0x000FFFFFUL) +#define WUPHCR_WUPT_EXT ((uint32_t)(((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M / 16UL) << 20U)) /* WUPHCR = warm-up time(us) * EXTALH / 16 */ +#define WUPHCR_WUPT_PLL ((WU_TIME_PLL * EXTALH / HZ_1M /16UL) << 20U) + +#if (CLOCK_SETUP) /* Clock(external) Setup */ +/* Determine core clock frequency according to settings */ +/* System clock is high-speed clock*/ +#if (OSCCR_Val & (1U<<8U)) +#define CORE_TALH (EXTALH) +#else +#define CORE_TALH (XTALH) +#endif + +#if ((PLLSEL_Val & (1U<<1U)) && (PLLSEL_Val & (1U<<0U))) /* If PLL selected and enabled */ +#if (CORE_TALH == OSC_8M) /* If input is 8MHz */ +#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_12_FPLL)) +#define __CORE_CLK ((CORE_TALH * 12U) / 4U) /* output clock is 24MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 8MHz */ +#elif (CORE_TALH == OSC_10M) /* If input is 10MHz */ +#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_8_FPLL)) +#define __CORE_CLK ((CORE_TALH * 8U) / 4U) /* output clock is 20MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 10MHz */ +#elif (CORE_TALH == OSC_12M) /* If input is 12MHz */ +#if ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_8_FPLL) +#define __CORE_CLK ((CORE_TALH * 8U) / 4U) /* output clock is 24MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 12MHz */ +#elif (CORE_TALH == OSC_16M) /* If input is 16MHz */ +#if ((PLLSEL_Val & PLLSEL_MASK) == CG_16M_MUL_6_FPLL) +#define __CORE_CLK ((CORE_TALH * 6U) / 4U) /* output clock is 24MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 16MHz */ +#else /* input clock not known */ +#define __CORE_CLK (0U) +#error "Core Oscillator Frequency invalid!" +#endif /* End switch input clock */ +#else +#define __CORE_CLK (CORE_TALH) +#endif + +#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */ +#define __CORE_SYS (__CORE_CLK) +#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */ +#define __CORE_SYS (__CORE_CLK / 2U) +#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */ +#define __CORE_SYS (__CORE_CLK / 4U) +#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */ +#define __CORE_SYS (__CORE_CLK / 8U) +#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */ +#define __CORE_SYS (__CORE_CLK / 16U) +#else /* Gear -> reserved */ +#define __CORE_SYS (0U) +#endif + +#else +#define __CORE_SYS (XTALH) + +#endif /* clock Setup */ + +/* Clock Variable definitions */ +uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Update SystemCoreClock according register values. + */ +void SystemCoreClockUpdate(void) +{ /* Get Core Clock Frequency */ + uint32_t CoreClock = 0U; + uint32_t CoreClockInput = 0U; + uint32_t regval = 0U; + uint32_t oscsel = 0U; + uint32_t pllsel = 0U; + uint32_t pllon = 0U; + /* Determine clock frequency according to clock register values */ + /* System clock is high-speed clock */ + regval = TSB_CG->OSCCR; + oscsel = regval & CG_OSCCR_OSCSEL_SET; + if (oscsel) { /* If system clock is External high-speed oscillator freq */ + CoreClock = EXTALH; + } else { /* If system clock is Internal high-speed oscillator freq */ + CoreClock = XTALH; + } + regval = TSB_CG->PLL0SEL; + pllsel = regval & CG_PLL0SEL_PLL0SEL_SET; + pllon = regval & CG_PLL0SEL_PLL0ON_SET; + if (pllsel && pllon) { /* If PLL enabled */ + if (CoreClock == OSC_8M) { /* If input is 8MHz */ + if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_8M_MUL_12_FPLL) { + CoreClockInput = (CoreClock * 12U) / 4U; /* output clock is 24MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == OSC_10M) { /* If input is 10MHz */ + if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_10M_MUL_8_FPLL) { + CoreClockInput = (CoreClock * 8U) / 4U; /* output clock is 20MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == OSC_12M) { /* If input is 12MHz */ + if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_12M_MUL_8_FPLL) { + CoreClockInput = (CoreClock * 8U) / 4U; /* output clock is 24MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == OSC_16M) { /* If input is 16MHz */ + if ((TSB_CG->PLL0SEL & PLLSEL_MASK) == CG_16M_MUL_6_FPLL) { + CoreClockInput = (CoreClock * 6U) / 4U; /* output clock is 24MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else { + CoreClockInput = 0U; + } + } else { + CoreClockInput = CoreClock; + } + switch (TSB_CG->SYSCR & 7U) { + case 0U: + SystemCoreClock = CoreClockInput; /* Gear -> fc */ + break; + case 1U: /* Gear -> fc/2 */ + SystemCoreClock = CoreClockInput / 2U; + break; + case 2U: /* Gear -> fc/4 */ + SystemCoreClock = CoreClockInput / 4U; + break; + case 3U: /* Gear -> fc/8 */ + SystemCoreClock = CoreClockInput / 8U; + break; + case 4U: /* Gear -> fc/16 */ + if (CoreClockInput >= OSC_16M) { + SystemCoreClock = CoreClockInput / 16U; + } else { + SystemCoreClock = 0U; + } + break; + default: + SystemCoreClock = 0U; + break; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit(void) +{ + uint32_t regval = 0U; + volatile uint32_t pllst = 0U; + volatile uint32_t wuef = 0U; + volatile uint32_t oscf = 0U; + uint32_t wdte = 0U; + +#if (WD_SETUP) /* Watchdog Setup */ + while (TSB_WD->FLG != 0U) { + } /* When writing to WDMOD or WDCR, confirm "0" of WDFLG. */ + TSB_WD->MOD = WDMOD_Val; + regval = TSB_WD->MOD; + wdte = regval & WD_MOD_WDTE_SET; + if (!wdte) { /* If watchdog is to be disabled */ + TSB_WD->CR = WDCR_Val; + } else { + /*Do nothing*/ + } +#endif + +#if (CLOCK_SETUP) /* Clock(external) Setup */ + TSB_CG->SYSCR = SYSCR_Val; + TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK; + TSB_CG->WUPHCR |= WUPHCR_WUPT_EXT; + TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; + TSB_CG->WUPHCR |= CG_WUPHCR_WUCLK_SET; + TSB_CG->WUPHCR |= CG_WUON_START_SET; + wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; + while (wuef) { + wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; + } /* Warm-up */ + TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; + oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK; + while (oscf != CG_OSCCR_OSCF_MASK) { + oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK; + } /* Confirm CGOSCCR="1" */ + + TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK; + TSB_CG->WUPHCR |= WUPHCR_WUPT_PLL; + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; + TSB_CG->PLL0SEL = PLLSEL_Ready; + TSB_CG->WUPHCR |= CG_WUON_START_SET; + wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; + while (wuef) { + wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; + } /* Warm-up */ + + TSB_CG->WUPHCR &= WUPHCR_WUPT_MASK; + TSB_CG->WUPHCR |= WUPHCR_WUPT_PLL; + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ + TSB_CG->STBYCR = STBYCR_Val; + TSB_CG->WUPHCR |= CG_WUON_START_SET; + wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; + while (wuef) { + wuef = TSB_CG->WUPHCR & CG_WUEF_VALUE_MASK; + } /* Warm-up */ + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; + pllst = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0ST_MASK; + while (pllst != CG_PLL0SEL_PLL0ST_MASK) { + pllst = TSB_CG->PLL0SEL & CG_PLL0SEL_PLL0ST_MASK; + } /*Confirm CGPLLSEL = "1" */ + +#endif +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.h new file mode 100644 index 0000000000..a8b1053e00 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device/system_TMPM066.h @@ -0,0 +1,49 @@ +/** + ***************************************************************************** + * @file system_TMPM066.h + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM066' Device Series + * @version V2.0.2.1 (Tentative) + * @date 2015/8/13 + * + * (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved + ***************************************************************************** + */ + +#include + +#ifndef __SYSTEM_TMPM066_H +#define __SYSTEM_TMPM066_H + +#ifdef __cplusplus +extern "C" { +#endif + + extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ + extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ + extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c new file mode 100644 index 0000000000..c0656e705b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c @@ -0,0 +1,96 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_error.h" + +#define GPIO_DATA PIN_DATA(0, 3) +extern const PinMap PinMap_GPIO_IRQ[]; + +uint32_t gpio_set(PinName pin) +{ + // Check that pin is valid + MBED_ASSERT(pin != (PinName)NC); + + // Checking pin name is not interrupt pins + if (pinmap_find_peripheral(pin, PinMap_GPIO_IRQ) == (uint32_t) NC) { + // Set pin function as GPIO pin + pin_function(pin, GPIO_DATA); + } + + // Return pin mask + return (1 << (pin & 0x07)); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + // Store above pin mask, pin name into GPIO object + obj->pin = pin; + obj->mask = gpio_set(pin); + obj->port = (GPIO_Port) (pin >> 3); + if((PortName)obj->port == PortH) { + CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE); + } + if ((PortName)obj->port == PortJ) { + CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE); + } +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + // Set pin mode + pin_mode(obj->pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + // Set direction + switch (direction) { + case PIN_INPUT: + // Set pin input + GPIO_SetInput(obj->port, obj->mask); + break; + case PIN_OUTPUT: + // Set pin output + GPIO_SetOutput(obj->port, obj->mask); + break; + case PIN_INOUT: + // Set pin both input and output + GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE); + GPIO_SetInputEnableReg(obj->port, obj->mask, ENABLE); + break; + default: + error("Invalid direction\n"); + break; + } +} + +void gpio_write(gpio_t *obj, int value) +{ + // Write gpio object pin data + if ((value == 0) || (value == 1)) { + GPIO_WriteDataBit(obj->port, obj->mask, value); + } else { + error("Invalid value\n"); + } +} + +int gpio_read (gpio_t *obj) +{ + // Read gpio object pin data + return GPIO_ReadDataBit(obj->port, obj->mask); +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c new file mode 100644 index 0000000000..46a3d03abc --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c @@ -0,0 +1,246 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "string.h" +#include "gpio_irq_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" + +#define CHANNEL_NUM 6 + +const PinMap PinMap_GPIO_IRQ[] = { + {PD5, GPIO_IRQ_0, PIN_DATA(0, 0)}, + {PA5, GPIO_IRQ_1, PIN_DATA(0, 0)}, + {PA6, GPIO_IRQ_2, PIN_DATA(0, 0)}, + {PF1, GPIO_IRQ_3, PIN_DATA(0, 0)}, + {PC5, GPIO_IRQ_4, PIN_DATA(0, 0)}, + {PF0, GPIO_IRQ_5, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; + +static void INT_IRQHandler(PinName pin, GPIO_IRQName irq_id, uint32_t index) +{ + uint32_t val; + GPIO_Port port; + uint32_t mask; + INTIFAO_INTActiveState ActiveState; + port = (GPIO_Port)(pin >> 3); + mask = 0x01 << (pin & 0x07); + // Clear interrupt request + INTIFAO_ClearINTReq((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index)); + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)irq_id); + ActiveState = INTIFAO_GetSTBYReleaseINTState((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index)); + INTIFAO_SetSTBYReleaseINTSrc((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index), + ActiveState, DISABLE); + // Get pin value + val = GPIO_ReadDataBit(port, mask); + switch (val) { + // Falling edge detection + case 0: + hal_irq_handler[index](channel_ids[index], IRQ_FALL); + break; + // Rising edge detection + case 1: + hal_irq_handler[index](channel_ids[index], IRQ_RISE); + break; + default: + break; + } + + // Enable interrupt request + INTIFAO_SetSTBYReleaseINTSrc((INTIFAO_INTSrc)(INTIFAO_INT_SRC_0 + index), + ActiveState, ENABLE); +} + +void INT0_IRQHandler(void) +{ + INT_IRQHandler(PD5, GPIO_IRQ_0, 0); +} + +void INT1_IRQHandler(void) +{ + INT_IRQHandler(PA5, GPIO_IRQ_1, 1); +} + +void INT2_IRQHandler(void) +{ + INT_IRQHandler(PA6, GPIO_IRQ_2, 2); +} + +void INT3_IRQHandler(void) +{ + INT_IRQHandler(PF1, GPIO_IRQ_3, 3); +} + +void INT4_IRQHandler(void) +{ + INT_IRQHandler(PC5, GPIO_IRQ_4, 4); +} + +void INT5_IRQHandler(void) +{ + INT_IRQHandler(PF0, GPIO_IRQ_5, 5); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + // Get gpio interrupt ID + obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); + + // Disable interrupt by CPU + __set_PRIMASK(1); + + // Get pin mask + obj->mask = (uint32_t)(1 << (pin & 0x07)); + + // Get GPIO port + obj->port = (GPIO_Port)(pin >> 3); + + // Set pin level as LOW + GPIO_WriteDataBit(obj->port, obj->mask, 0); + + // Enable gpio interrupt function + pinmap_pinout(pin, PinMap_GPIO_IRQ); + + // Get GPIO irq source + switch (obj->irq_id) { + case GPIO_IRQ_0: + obj->irq_src = INTIFAO_INT_SRC_0; + break; + case GPIO_IRQ_1: + obj->irq_src = INTIFAO_INT_SRC_1; + break; + case GPIO_IRQ_2: + obj->irq_src = INTIFAO_INT_SRC_2; + break; + case GPIO_IRQ_3: + obj->irq_src = INTIFAO_INT_SRC_3; + break; + case GPIO_IRQ_4: + obj->irq_src = INTIFAO_INT_SRC_4; + break; + case GPIO_IRQ_5: + obj->irq_src = INTIFAO_INT_SRC_5; + break; + default: + break; + } + + // Save irq handler + hal_irq_handler[obj->irq_src] = handler; + + // Save irq id + channel_ids[obj->irq_src] = id; + + // Initialize interrupt event as both edges detection + obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID; + + // Set interrupt event and enable INTx clear + INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE); + + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + + // Enable gpio interrupt + __set_PRIMASK(0); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + // Clear gpio_irq + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Reset interrupt handler + hal_irq_handler[obj->irq_src] = NULL; + // Reset interrupt id + channel_ids[obj->irq_src] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + //Disable GPIO interrupt on obj + gpio_irq_disable(obj); + if (enable) { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == INTIFAO_INT_ACTIVE_STATE_FALLING) || + (obj->event == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = INTIFAO_INT_ACTIVE_STATE_RISING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == INTIFAO_INT_ACTIVE_STATE_RISING) || + (obj->event == INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = INTIFAO_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = INTIFAO_INT_ACTIVE_STATE_FALLING; + } + } else { + error("Not supported event\n"); + } + } else { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == INTIFAO_INT_ACTIVE_STATE_RISING) || + (obj->event == INTIFAO_INT_ACTIVE_STATE_INVALID)) { + obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID; + } else { + obj->event = INTIFAO_INT_ACTIVE_STATE_FALLING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == INTIFAO_INT_ACTIVE_STATE_FALLING) || + (obj->event == INTIFAO_INT_ACTIVE_STATE_INVALID)) { + obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID; + } else { + obj->event = INTIFAO_INT_ACTIVE_STATE_RISING; + } + } else { + error("Not supported event\n"); + } + } + + if (obj->event != INTIFAO_INT_ACTIVE_STATE_INVALID ) { + // Set interrupt event and enable INTx clear + INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE); + GPIO_SetOutputEnableReg(obj->port, obj->mask, DISABLE); + } else { + GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE); + } + + // Clear interrupt request + INTIFAO_ClearINTReq(obj->irq_src); + // Enable GPIO interrupt on obj + gpio_irq_enable(obj); +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + // Clear and Enable gpio_irq object + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + NVIC_EnableIRQ((IRQn_Type)obj->irq_id); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + // Disable gpio_irq object + NVIC_DisableIRQ((IRQn_Type)obj->irq_id); +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h new file mode 100644 index 0000000000..7852bb602d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + GPIO_Port port; +} gpio_t; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return obj->pin != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c new file mode 100644 index 0000000000..4d3e266ef4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c @@ -0,0 +1,361 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "i2c_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" + +#define I2C_NACK (0) +#define I2C_ACK (1) +#define I2C_TIMEOUT (100000) +#define SELF_ADDR (0xE0) + +static const PinMap PinMap_I2C_SDA[] = { + {PC1, I2C_0, PIN_DATA(1, 2)}, + {PG1, I2C_1, PIN_DATA(1, 2)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {PC0, I2C_0, PIN_DATA(1, 2)}, + {PG0, I2C_1, PIN_DATA(1, 2)}, + {NC, NC, 0} +}; + +void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx); +// Clock setting structure definition +typedef struct { + uint32_t sck; + uint32_t prsck; +} I2C_clock_setting_t; + +static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20, 24, 32, 48, 80, 144, 272, 528}; // SCK Divider value table +static uint32_t start_flag = 0; +I2C_clock_setting_t clk; +I2C_State status; + +static int32_t wait_status(i2c_t *obj) +{ + volatile int32_t timeout = I2C_TIMEOUT; + + while (I2C_GetINTI2CStatus(obj->i2c) == DISABLE) { + if ((timeout--) == 0) { + return (-1); + } + } + return (0); +} + +// Initialize the I2C peripheral. It sets the default parameters for I2C +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + MBED_ASSERT(obj != NULL); + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)i2c_name != NC); + + switch(i2c_name) { + case I2C_0: + CG_SetFcPeriphA(CG_FC_PERIPH_I2C0, ENABLE); + obj->i2c = TSB_I2C0; + obj->IRQn = INTI2C0_IRQn; + break; + case I2C_1: + CG_SetFcPeriphB(CG_FC_PERIPH_I2C1, ENABLE); + obj->i2c = TSB_I2C1; + obj->IRQn = INTI2C1_IRQn; + break; + default: + error("I2C is not available"); + break; + } + + pinmap_pinout(sda, PinMap_I2C_SDA); + pin_mode(sda, OpenDrain); + pin_mode(sda, PullUp); + + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(scl, OpenDrain); + pin_mode(scl, PullUp); + + NVIC_DisableIRQ(obj->IRQn); + + i2c_reset(obj); + i2c_frequency(obj, 100000); +} + +// Configure the I2C frequency +void i2c_frequency(i2c_t *obj, int hz) +{ + uint64_t sck, tmp_sck; + uint64_t prsck, tmp_prsck; + uint64_t fscl, tmp_fscl; + uint64_t fx; + + SystemCoreClockUpdate(); + + if (hz <= 1000000) { + sck = tmp_sck = 0; + prsck = tmp_prsck = 1; + fscl = tmp_fscl = 0; + for (prsck = 1; prsck <= 32; prsck++) { + fx = ((uint64_t)SystemCoreClock / prsck); + if ((fx < 40000000U) && (fx > 6666666U)) { + for (sck = 0; sck <= 7; sck++) { + fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); + if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + tmp_sck = sck; + tmp_prsck = (prsck < 32)? prsck: 0; + } + } + } + } + clk.sck = (uint32_t)tmp_sck; + clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck) : 0; + } + obj->myi2c.I2CSelfAddr = SELF_ADDR; + obj->myi2c.I2CDataLen = I2C_DATA_LEN_8; + obj->myi2c.I2CACKState = ENABLE; + obj->myi2c.I2CClkDiv = clk.sck; + obj->myi2c.PrescalerClkDiv = clk.prsck; + + I2C_Init(obj->i2c, &obj->myi2c); + NVIC_DisableIRQ(obj->IRQn); +} + +int i2c_start(i2c_t *obj) +{ + start_flag = 1; + return 0; +} + +int i2c_stop(i2c_t *obj) +{ + I2C_GenerateStop(obj->i2c); + return 0; +} + +void i2c_reset(i2c_t *obj) +{ + I2C_SWReset(obj->i2c); + return; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int32_t result = 0; + int32_t count = 0; + + if (length > 0) { + start_flag = 1; // Start Condition + if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) { + while (count < length) { + int32_t pdata = i2c_byte_read(obj, ((count < (length - 1))? 0: 1)); + if (pdata < 0) { + break; + } + data[count++] = (uint8_t)pdata; + } + result = count; + } else { + stop = 1; + result = I2C_ERROR_NO_SLAVE; + } + + if (stop) { // Stop Condition + i2c_stop(obj); + } + } + return (result); +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) // Blocking sending data +{ + int32_t result = 0; + int32_t count = 0; + + start_flag = 1; // Start Condition + if (i2c_byte_write(obj, address) == I2C_ACK) { + while (count < length) { + if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { + break; + } + } + result = count; + } else { + stop = 1; + result = I2C_ERROR_NO_SLAVE; + } + + if (stop) { // Stop Condition + i2c_stop(obj); + } + return (result); +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + int32_t result; + + I2C_ClearINTOutput(obj->i2c); + + if (last) { + I2C_SelectACKoutput(obj->i2c, ENABLE); + } else { + I2C_SelectACKoutput(obj->i2c, DISABLE); + } + I2C_SetSendData(obj->i2c, 0x00); + + if (wait_status(obj) < 0) { + result = -1; + } else { + result = (int32_t)I2C_GetReceiveData(obj->i2c); + } + return (result); +} + +void I2C_Start_Condition(i2c_t *p_obj, uint32_t data) +{ + status = I2C_GetState(p_obj->i2c); + if (status.Bit.BusState) { + I2C_SetRepeatStart(p_obj->i2c, ENABLE); + } + I2C_SetSendData(p_obj->i2c, (uint32_t)data); + I2C_GenerateStart(p_obj->i2c); +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int32_t result; + + I2C_ClearINTOutput(obj->i2c); + + if(start_flag == 1) { + I2C_Start_Condition(obj, (uint32_t)data); + start_flag = 0; + } else { + I2C_SetSendData(obj->i2c, (uint32_t)data); + } + + if (wait_status(obj) < 0) { + return (-1); + } + + status = I2C_GetState(obj->i2c); + if (!status.Bit.LastRxBit) { + result = 1; + } else { + result = 0; + } + return (result); +} + + +#if DEVICE_I2CSLAVE + +#define I2C_NO_DATA (0) +#define I2C_READ_ADDRESSED (1) +#define I2C_WRITE_GENERAL (2) +#define I2C_WRITE_ADDRESSED (3) + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + i2c_reset(obj); + + obj->myi2c.I2CDataLen = I2C_DATA_LEN_8; + obj->myi2c.I2CACKState = ENABLE; + obj->myi2c.I2CClkDiv = clk.sck; + obj->myi2c.PrescalerClkDiv = clk.prsck; + + if (enable_slave) { + obj->myi2c.I2CSelfAddr = obj->address; + I2C_SetINTI2CReq(obj->i2c, ENABLE); + } else { + obj->myi2c.I2CSelfAddr = SELF_ADDR; + NVIC_DisableIRQ(obj->IRQn); + I2C_ClearINTOutput(obj->i2c); + } + I2C_Init(obj->i2c, &obj->myi2c); +} + + +int i2c_slave_receive(i2c_t *obj) +{ + int32_t result = I2C_NO_DATA; + + if ((I2C_GetINTI2CStatus(obj->i2c)) && (I2C_GetSlaveAddrMatchState(obj->i2c))) { + status = I2C_GetState(obj->i2c); + if (!status.Bit.TRx) { + result = I2C_WRITE_ADDRESSED; + } else { + result = I2C_READ_ADDRESSED; + } + } + return (result); +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + int32_t count = 0; + + while (count < length) { + int32_t pdata = i2c_byte_read(obj, ((count < (length - 1))? 0: 1)); + status = I2C_GetState(obj->i2c); + if (status.Bit.TRx) { + return (count); + } else { + if (pdata < 0) { + break; + } + data[count++] = (uint8_t)pdata; + } + } + i2c_slave_mode(obj, 1); + return (count); +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + int32_t count = 0; + + while (count < length) { + if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) { + break; + } + } + i2c_slave_mode(obj, 1); + return (count); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + obj->address = address & 0xFE; + i2c_slave_mode(obj, 1); +} + +#endif + +void INTI2C0_IRQHandler(void) +{ + +} + +void INTI2C1_IRQHandler(void) +{ + +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/objects.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/objects.h new file mode 100644 index 0000000000..04328f191b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/objects.h @@ -0,0 +1,80 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "PortNames.h" +#include "PeripheralNames.h" +#include "tmpm066_gpio.h" +#include "tmpm066_uart.h" +#include "tmpm066_cg.h" +#include "tmpm066_intifao.h" +#include "tmpm066_i2c.h" +#include "tmpm066_adc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + uint32_t mask; + GPIO_Port port; + uint32_t irq_id; + INTIFAO_INTActiveState event; + INTIFAO_INTSrc irq_src; +}; + +struct port_s { + PortName port; + uint32_t mask; +}; + +struct pwmout_s { + PinName pin; + TSB_TB_TypeDef *channel; + uint16_t trailing_timing; + uint16_t leading_timing; + uint16_t divisor; + float period; +}; + +struct serial_s { + PinName pin; + uint32_t index; + TSB_SC_TypeDef *UARTx; + UART_InitTypeDef uart_config; +}; + +struct analogin_s { + PinName pin; + ADCName adc; + TSB_AD_TypeDef *obj; +}; + +struct i2c_s { + uint32_t address; + IRQn_Type IRQn; + TSB_I2C_TypeDef *i2c; + I2C_InitTypeDef myi2c; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c new file mode 100644 index 0000000000..cbc499a1e8 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c @@ -0,0 +1,106 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pinmap.h" +#include "tmpm066_gpio.h" + +#define PIN_FUNC_MAX 6 + +void pin_function(PinName pin, int function) +{ + uint32_t port = 0; + uint8_t bit = 0; + uint8_t i = 0; + uint8_t func = 0; + uint8_t dir = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Calculate pin function and pin direction + func = PIN_FUNC(function); + dir = PIN_DIR(function); + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + // Set function if function is in range + if (func <= PIN_FUNC_MAX) { + // Disable other functions + for(i = 0; i < PIN_FUNC_MAX; i++) { + if(i != (func - 1)) { + GPIO_DisableFuncReg((GPIO_Port)port, i, (1 << bit)); + } + } + // Set pin function + if (func) { + GPIO_EnableFuncReg((GPIO_Port)port, (uint8_t)(func - 1), (1 << bit)); + } + } + + // Set direction if direction is in range + switch (dir) { + case PIN_INPUT: + GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE); + GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), DISABLE); + break; + case PIN_OUTPUT: + GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE); + GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), DISABLE); + break; + case PIN_INOUT: + GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE); + GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE); + break; + default: + break; + } +} + +void pin_mode(PinName pin, PinMode mode) +{ + uint32_t port = 0; + uint8_t bit = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Check if function is in range + if (mode > OpenDrain) { + return; + } + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + // Set pin mode + switch (mode) { + case PullNone: + GPIO_SetPullUp((GPIO_Port)port, (1 << bit), DISABLE); + GPIO_SetPullDown((GPIO_Port)port, (1 << bit), DISABLE); + GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), DISABLE); + break; + case PullUp: + GPIO_SetPullUp((GPIO_Port)port, (1 << bit), ENABLE); + break; + case PullDown: + GPIO_SetPullDown((GPIO_Port)port, (1 << bit), ENABLE); + break; + case OpenDrain: + GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), ENABLE); + break; + default: + break; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c new file mode 100644 index 0000000000..83a22e563d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c @@ -0,0 +1,124 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" + +#define PORT_PIN_NUM 8 + +PinName port_pin(PortName port, int pin_n) +{ + PinName pin = NC; + pin = (PinName)((port << 3) | pin_n); + return pin; +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(port <= PortJ); + + // Store port and port mask for future use + obj->port = port; + obj->mask = mask; + + if((PortName)obj->port == PortH) { + CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE); + } + if ((PortName)obj->port == PortJ) { + CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE); + } + + // Set port function and port direction + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_function(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortJ); + + // Set mode for masked pins + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + // Assert that port is valid + MBED_ASSERT(obj->port <= PortJ); + + // Set direction for masked pins + switch (dir) { + case PIN_INPUT: + GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE); + GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE); + break; + case PIN_OUTPUT: + GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE); + GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE); + break; + case PIN_INOUT: + GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE); + GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE); + break; + default: + break; + } +} + +void port_write(port_t *obj, int value) +{ + uint8_t port_data = 0; + uint8_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortJ); + + // Get current data of port + port_data = GPIO_ReadData((GPIO_Port)obj->port); + // Calculate data to write to masked pins + data = (port_data & ~obj->mask) | (value & obj->mask); + // Write data to masked pins of the port + GPIO_WriteData((GPIO_Port)obj->port, data); +} + +int port_read(port_t *obj) +{ + uint8_t port_data = 0; + uint8_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortJ); + + // Get current data of port + port_data = GPIO_ReadData((GPIO_Port)obj->port); + // Calculate data of masked pins + data = port_data & obj->mask; + return data; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/pwmout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/pwmout_api.c new file mode 100644 index 0000000000..6f889d6c42 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/pwmout_api.c @@ -0,0 +1,243 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pwmout_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "tmpm066_tmrb.h" + +#define CLOCK_FREQUENCY SystemCoreClock // input source clock +#define MAX_COUNTER_16B 0xFFFF +#define DEFAULT_CLOCK_DIVISION 32 +#define DEFAULT_PERIOD 0.02f // 20ms + +static const PinMap PinMap_PWM[] = { + {PD1, PWM_0, PIN_DATA(1, 1)}, + {PD2, PWM_1, PIN_DATA(1, 1)}, + {PD3, PWM_2, PIN_DATA(1, 1)}, + {PF4, PWM_3, PIN_DATA(1, 1)}, + {PF5, PWM_4, PIN_DATA(1, 1)}, + {PJ0, PWM_5, PIN_DATA(1, 1)}, + {PJ1, PWM_6, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const uint32_t prescale_tbl[] = { + 2, 8, 32, 64, 128, 256, 512 +}; + +void pwmout_init(pwmout_t *obj, PinName pin) +{ + uint16_t counter = 0; + TMRB_FFOutputTypeDef FFStruct; + TMRB_InitTypeDef m_tmrb; + + // Determine the pwm channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + //Assert input is valid + MBED_ASSERT(pwm != (PWMName)NC); + + // Enable clock supply to TB0 + CG_SetFcPeriphA(CG_FC_PERIPH_TMRB0_3, ENABLE); + CG_SetFcPeriphA(CG_FC_PERIPH_TMRB4_6, ENABLE); + + switch (pwm) { + case PWM_0: + obj->channel = TSB_TB0; + break; + case PWM_1: + obj->channel = TSB_TB1; + break; + case PWM_2: + obj->channel = TSB_TB2; + break; + case PWM_3: + obj->channel = TSB_TB3; + break; + case PWM_4: + obj->channel = TSB_TB4; + break; + case PWM_5: + obj->channel = TSB_TB5; + CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE); + break; + case PWM_6: + obj->channel = TSB_TB6; + CG_SetFcPeriphA(CG_FC_PERIPH_PORTJ, ENABLE); + break; + default: + obj->channel = NULL; + return; + } + // Set pin function as PWM + pinmap_pinout(pin, PinMap_PWM); + obj->pin = pin; + obj->period = DEFAULT_PERIOD; + // Enable channel + TMRB_Enable(obj->channel); + // Stops and clear count operation + TMRB_SetRunState(obj->channel, TMRB_STOP); + // Disables double buffering + TMRB_SetDoubleBuf(obj->channel, DISABLE); + // Set default period = 20ms, duty cycle = 0 + obj->divisor = DEFAULT_CLOCK_DIVISION; + counter = (uint16_t)((DEFAULT_PERIOD * CLOCK_FREQUENCY) / obj->divisor); + + // Init timer variable for using PPG mode + m_tmrb.Mode = TMRB_INTERVAL_TIMER; + m_tmrb.ClkDiv = TMRB_CLK_DIV_32; + m_tmrb.UpCntCtrl = TMRB_AUTO_CLEAR; // clear UC when matching value + m_tmrb.TrailingTiming = counter; // period = 20ms + m_tmrb.LeadingTiming = counter; // duty cycle = 0% + + // Init timer function + TMRB_Init(obj->channel, &m_tmrb); + obj->trailing_timing = counter; + obj->leading_timing = counter; + + // Enable double buffering + TMRB_SetDoubleBuf(obj->channel, ENABLE); + + // Setting to TBxFF0 reverse trigger + FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR; + FFStruct.FlipflopReverseTrg = TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING; + TMRB_SetFlipFlop(obj->channel, &FFStruct); + + // Start count operation + TMRB_SetRunState(obj->channel, TMRB_RUN); +} + +void pwmout_free(pwmout_t *obj) +{ + // Stops and clear count operation + TMRB_SetRunState(obj->channel, TMRB_STOP); + pwmout_write(obj,0); + obj->pin = NC; + obj->channel = NULL; + obj->trailing_timing = 0; + obj->leading_timing = 0; + obj->divisor = 0; +} + +void pwmout_write(pwmout_t *obj, float value) +{ + TMRB_FFOutputTypeDef FFStruct; + + // Stop timer for setting clock again + TMRB_SetRunState(obj->channel, TMRB_STOP); + // values outside this range will be saturated to 0.0f or 1.0f + // Disable flip-flop reverse trigger when leading_timing and trailing_timing are duplicated + if (value <= 0.0f) { + value = 0; + FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR; + FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP; + TMRB_SetFlipFlop(obj->channel, &FFStruct); + } else if (value >= 1.0f) { + value = 1; + FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_SET; + FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP; + TMRB_SetFlipFlop(obj->channel, &FFStruct); + } else { + FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR; + FFStruct.FlipflopReverseTrg = TMRB_FLIPFLOP_MATCH_TRAILINGTIMING | TMRB_FLIPFLOP_MATCH_LEADINGTIMING; + TMRB_SetFlipFlop(obj->channel, &FFStruct); + } + + // Store the new leading_timing value + obj->leading_timing = obj->trailing_timing - (uint16_t)(obj->trailing_timing * value); + + // Setting TBxRG0 register + TMRB_ChangeLeadingTiming(obj->channel, obj->leading_timing); + TMRB_SetRunState(obj->channel, TMRB_RUN); +} + +float pwmout_read(pwmout_t *obj) +{ + float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing; + return duty_cycle; +} + +void pwmout_period(pwmout_t *obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0f)); +} + +void pwmout_period_ms(pwmout_t *obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t *obj, int us) +{ + float seconds = 0; + int cycles = 0; + uint32_t clkdiv = 0; + float duty_cycle = 0; + TMRB_InitTypeDef m_tmrb; + seconds = (float)((us) / 1000000.0f); + obj->period = seconds; + + MBED_ASSERT(obj->channel != NULL); + + // Select highest timer resolution + for (int i = 0; i < 7; ++i) { + cycles = (int)((CLOCK_FREQUENCY / prescale_tbl[i]) * seconds); + if (cycles <= MAX_COUNTER_16B) { + clkdiv = i + 1; // range 1:7 + break; + } + } + // Stop timer for setting clock again + TMRB_SetRunState(obj->channel, TMRB_STOP); + // Restore the duty-cycle + duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing; + obj->trailing_timing = cycles; + obj->leading_timing = (cycles - (uint16_t)(cycles * duty_cycle)); + + // Change the source clock division and period + m_tmrb.Mode = TMRB_INTERVAL_TIMER; + m_tmrb.ClkDiv = clkdiv; + m_tmrb.UpCntCtrl = TMRB_AUTO_CLEAR; + m_tmrb.TrailingTiming = obj->trailing_timing; + m_tmrb.LeadingTiming = obj->leading_timing; + + //Init timer function + TMRB_Init(obj->channel, &m_tmrb); + //Start timer function + TMRB_SetRunState(obj->channel, TMRB_RUN); +} + +void pwmout_pulsewidth(pwmout_t *obj, float seconds) +{ + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + float seconds = 0; + float value = 0; + + MBED_ASSERT(obj->channel != NULL); + + seconds = (float)(us / 1000000.0f); + value = (((seconds / obj->period) * 100.0f) / 100.0f); + pwmout_write(obj, value); +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c new file mode 100644 index 0000000000..a872426fb0 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c @@ -0,0 +1,253 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "serial_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" + +#define UART_NUM 6 + +static const PinMap PinMap_UART_TX[] = { + {PC2, SERIAL_0, PIN_DATA(1, 1)}, + {PE2, SERIAL_1, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {PC3, SERIAL_0, PIN_DATA(1, 0)}, + {PE1, SERIAL_1, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + +static int serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + int is_stdio_uart = 0; + + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart_name != NC); + + obj->index = uart_name; + // Initialize UART instance + switch (uart_name) { + case SERIAL_0: + CG_SetFcPeriphA(CG_FC_PERIPH_SIO0, ENABLE); + obj->UARTx = UART0; + break; + case SERIAL_1: + CG_SetFcPeriphB(CG_FC_PERIPH_SIO1, ENABLE); + obj->UARTx = UART1; + break; + default: + break; + } + + obj->uart_config.BaudRate = 9600; + obj->uart_config.DataBits = UART_DATA_BITS_8; + obj->uart_config.StopBits = UART_STOP_BITS_1; + obj->uart_config.Parity = UART_NO_PARITY; + obj->uart_config.FlowCtrl = UART_NONE_FLOW_CTRL; + + if (tx != NC && rx != NC) { + obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX; + } else { + if (tx != NC) { + obj->uart_config.Mode = UART_ENABLE_TX; + } else { + if (rx != NC) { + obj->uart_config.Mode = UART_ENABLE_RX; + } + } + } + + // Pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + // Initialize UART configure + UART_Enable(obj->UARTx); + UART_SetIdleMode(obj->UARTx, ENABLE); + UART_Init(obj->UARTx, &obj->uart_config); + is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + // Disable UART + UART_Disable(obj->UARTx); + UART_SWReset(obj->UARTx); + // Set information of object to invalid + obj->uart_config.BaudRate = 0; + obj->uart_config.DataBits = 0; + obj->uart_config.StopBits = 0; + obj->uart_config.Parity = 0; + obj->uart_config.Mode = 0; + obj->uart_config.FlowCtrl = 0; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + obj->uart_config.BaudRate = baudrate; + UART_Init(obj->UARTx, &obj->uart_config); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + // 0: 1 stop bits, 1: 2 stop bits + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || + (parity == ParityForced1) || (parity == ParityForced0)); + // 0: 7 data bits ... 2: 9 data bits + MBED_ASSERT((data_bits > 6) && (data_bits < 10)); + + obj->uart_config.DataBits = data_bits; + obj->uart_config.StopBits = stop_bits; + obj->uart_config.Parity = parity; + UART_Init(obj->UARTx, &obj->uart_config); +} + +// INTERRUPTS HANDLING +void INTTX0_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], TxIrq); +} + +void INTRX0_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], RxIrq); +} + +void INTTX1_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], TxIrq); +} + +void INTRX1_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], RxIrq); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + IRQn_Type irq_n = (IRQn_Type)0; + + switch (obj->index) { + case SERIAL_0: + if (irq == RxIrq) { + irq_n = INTRX0_IRQn; + } else { + irq_n = INTTX0_IRQn; + } + break; + case SERIAL_1: + if (irq == RxIrq) { + irq_n = INTRX1_IRQn; + } else { + irq_n = INTTX1_IRQn; + } + break; + default: + break; + } + + if (enable) { + NVIC_EnableIRQ(irq_n); + } else { + NVIC_DisableIRQ(irq_n); + } +} + +int serial_getc(serial_t *obj) +{ + // Wait until Rx buffer is full + while (!serial_readable(obj)) { + // Do nothing + } + + return UART_GetRxData(obj->UARTx); +} + +void serial_putc(serial_t *obj, int c) +{ + // Wait until Tx buffer is empty + while (!serial_writable(obj)) { + // Do nothing + } + + UART_SetTxData(obj->UARTx, (uint32_t)c); +} + +int serial_readable(serial_t *obj) +{ + int ret = 0; + + if (UART_GetBufState(obj->UARTx, UART_RX) == DONE) { + ret = 1; + } + + return ret; +} + +int serial_writable(serial_t *obj) +{ + int ret = 0; + + if (UART_GetBufState(obj->UARTx, UART_TX) == DONE) { + ret = 1; + } + + return ret; +} + +void serial_clear(serial_t *obj) +{ + UART_TxFIFOClear(obj->UARTx); + UART_RxFIFOClear(obj->UARTx); + UART_TxBufferClear(obj->UARTx); +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ +} + +void serial_break_set(serial_t *obj) +{ +} + +void serial_break_clear(serial_t *obj) +{ +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c new file mode 100644 index 0000000000..5d8f0aca0b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c @@ -0,0 +1,66 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" + +// number of warm-up cycle = warm-up time to set / input frequency cycle (s) +// number of 3*10^-6 (s) / (1/12 (MHz) ) = 60000 = 0xea60 +#define CG_WUODR_INT ((uint16_t)0xea60) + +void external_losc_enable(void); + +void hal_sleep(void) +{ + // Set low power consumption mode IDLE + CG_SetSTBYMode(CG_STBY_MODE_IDLE); + // Enter idle mode + __WFI(); +} + +void hal_deepsleep(void) +{ + // Set low power consumption mode STOP1 + CG_SetSTBYMode(CG_STBY_MODE_STOP1); + // Setup warm up time + CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_EXT_HIGH, CG_WUODR_INT); + // Enter stop1 mode + __WFI(); + // Switch over from IHOSC to EHOSC + external_losc_enable(); +} + +void external_losc_enable(void) +{ + // Enable high-speed oscillator + CG_SetFoscSrc(CG_FOSC_OSC_EXT); + // Select internal(fIHOSC) as warm-up clock + CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WUODR_INT); + // Start warm-up + CG_StartWarmUp(); + // Wait until EHOSC become stable + while (CG_GetWarmUpState() != DONE) { + // Do nothing + } + + // Set fosc source + CG_SetFoscSrc(CG_FOSC_OSC_EXT); + // Wait for to become "1" + while (CG_GetFoscSrc() != CG_FOSC_OSC_EXT) { + // Do nothing + } + + // Stop IHOSC + CG_SetFoscSrc(CG_FOSC_OSC_INT); +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c new file mode 100644 index 0000000000..9f3f8d8b61 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c @@ -0,0 +1,103 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "us_ticker_api.h" + +#define TMR16A_100US 0x960 // fsys = fc = 24MHz, Ttmra = 1/24us, 100us*24us = 2400 = 0x960 +#define TMR16A_SYSCK ((uint32_t)0x00000001) +#define TMR16A_RUN ((uint32_t)0x00000001) +#define TMR16A_STOP ((uint32_t)0x00000000) + +static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? +static volatile uint32_t acc_us_ticker = 0; + +// 16Bb high timer counter +static uint32_t us_ticker_16h = 0; + +void INT16A0_IRQHandler(void) +{ + us_ticker_16h++; + if (us_ticker_16h >= 0xFFFF) { + acc_us_ticker++; + us_ticker_16h = 0; + } +} + +void INT16A1_IRQHandler(void) +{ + us_ticker_irq_handler(); +} + +// initialize us_ticker +void us_ticker_init(void) +{ + // Enable clock supply to TA0 + CG_SetFcPeriphA(CG_FC_PERIPH_TMR16A, ENABLE); + if (us_ticker_inited) { + return; + } + us_ticker_inited = 1; + + // Stops and clear count operation + TSB_T16A0->RUN = TMR16A_STOP; + TSB_T16A0->CR = TMR16A_SYSCK; + // Permits INTTA0 interrupt + NVIC_EnableIRQ(INT16A0_IRQn); + // Match counter set to max value + TSB_T16A0->RG = TMR16A_100US; + // TSB_T16A0->CP = 0x00; + TSB_T16A0->RUN = TMR16A_RUN; +} + +uint32_t us_ticker_read() +{ + uint32_t ret_val = 0; + + if (!us_ticker_inited) { + us_ticker_init(); + } + ret_val = (((acc_us_ticker << 16) + us_ticker_16h) * 100); + return ret_val; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + int delta = 0; + // Stops and clear count operation + TSB_T16A1->RUN = TMR16A_STOP; + TSB_T16A1->CR = TMR16A_SYSCK; + // Set the compare register + delta = (int)(timestamp - us_ticker_read()); + TSB_T16A1->RG = delta; + // Set Interrupt + NVIC_EnableIRQ(INT16A1_IRQn); + // Start TMR_TA1 timer + TSB_T16A1->RUN = TMR16A_RUN; +} + +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(INT16A1_IRQn); +} + +void us_ticker_disable_interrupt(void) +{ + NVIC_DisableIRQ(INT16A1_IRQn); +} + +void us_ticker_clear_interrupt(void) +{ + //no flags to clear +} diff --git a/targets/TARGET_TOSHIBA/mbed_rtx.h b/targets/TARGET_TOSHIBA/mbed_rtx.h new file mode 100644 index 0000000000..aeacbcf322 --- /dev/null +++ b/targets/TARGET_TOSHIBA/mbed_rtx.h @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#if defined(TARGET_TMPM066) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20004000UL) +#endif + +#ifdef TOOLCHAIN_GCC_ARM +#define MBED_CONF_APP_MAIN_STACK_SIZE 2048 +#endif + +#endif + +#endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index fd9550f01c..a7e9e578dc 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3348,5 +3348,17 @@ "release_versions": ["5"], "device_name": "M487JIDAE", "bootloader_supported": true + }, + "TMPM066": { + "inherits": ["Target"], + "core": "Cortex-M0", + "is_disk_virtual": true, + "extra_labels": ["TOSHIBA"], + "macros": ["__TMPM066__", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], + "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SLEEP", "I2C", "I2CSLAVE", "STDIO_MESSAGES", "PWMOUT"], + "device_name": "TMPM066FWUG", + "detect_code": ["7011"], + "release_versions": ["5"] } } From 624620b0d256347e4066c9b90c93b214591472de Mon Sep 17 00:00:00 2001 From: Ganesh Ramachandran <30490592+ganesh-ramachandran@users.noreply.github.com> Date: Fri, 4 Aug 2017 17:28:38 +0530 Subject: [PATCH 2/7] SERIAL_FC disabled, critical section API Updation SERIAL_FC disabled, critical section API and Format changes updated --- .../TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h | 20 ++++----- .../TARGET_TMPM066/analogin_api.c | 20 ++++----- .../TARGET_TOSHIBA/TARGET_TMPM066/device.h | 2 +- .../TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c | 6 +-- .../TARGET_TMPM066/gpio_irq_api.c | 20 ++------- .../TARGET_TMPM066/gpio_object.h | 2 +- .../TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c | 42 ++++++------------- .../TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c | 4 +- .../TARGET_TOSHIBA/TARGET_TMPM066/port_api.c | 2 +- .../TARGET_TMPM066/serial_api.c | 14 +------ targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c | 2 +- .../TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c | 5 +-- targets/targets.json | 2 +- 13 files changed, 49 insertions(+), 92 deletions(-) diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h index a791c3f4ea..3a96aa4361 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/PinNames.h @@ -26,7 +26,7 @@ extern "C" { #define PIN_POS(X) ((uint32_t)(X) & 0x7) // Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction -#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0)) +#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0)) #define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) #define PIN_DIR(X) ((X) & 0xffff) @@ -38,15 +38,15 @@ typedef enum { typedef enum { // TMPM066 Pin Names - PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, - PB0 = 1 << 3, PB1, PB2, PB3, - PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, - PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, - PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, - PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, - PG0 = 6 << 3, PG1, - PH0 = 7 << 3, PH1, PH2, PH3, - PJ0 = 8 << 3, PJ1, PJ2, PJ3, + PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PB0 = 1 << 3, PB1, PB2, PB3, + PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, + PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, + PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, + PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PG0 = 6 << 3, PG1, + PH0 = 7 << 3, PH1, PH2, PH3, + PJ0 = 8 << 3, PJ1, PJ2, PJ3, // Other mbed Pin Names LED1 = PB0, diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c index 3c8e19ced4..cc2d737448 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c @@ -21,15 +21,15 @@ #define ADC_10BIT_RANGE 0x3FF static const PinMap PinMap_ADC[] = { - {PA0, ADC_A0, PIN_DATA(0, 0)}, - {PA1, ADC_A1, PIN_DATA(0, 0)}, - {PA2, ADC_A2, PIN_DATA(0, 0)}, - {PA3, ADC_A3, PIN_DATA(0, 0)}, - {PA4, ADC_A4, PIN_DATA(0, 0)}, - {PA5, ADC_A5, PIN_DATA(0, 0)}, - {PA6, ADC_A6, PIN_DATA(0, 0)}, - {PA7, ADC_A7, PIN_DATA(0, 0)}, - {NC, NC, 0} + {PA0, ADC_A0, PIN_DATA(0, 0)}, + {PA1, ADC_A1, PIN_DATA(0, 0)}, + {PA2, ADC_A2, PIN_DATA(0, 0)}, + {PA3, ADC_A3, PIN_DATA(0, 0)}, + {PA4, ADC_A4, PIN_DATA(0, 0)}, + {PA5, ADC_A5, PIN_DATA(0, 0)}, + {PA6, ADC_A6, PIN_DATA(0, 0)}, + {PA7, ADC_A7, PIN_DATA(0, 0)}, + {NC, NC, 0} }; void analogin_init(analogin_t *obj, PinName pin) @@ -72,7 +72,7 @@ uint16_t analogin_read_u16(analogin_t *obj) // Start ADC conversion ADC_Start(); // Wait until AD conversion complete - while(ADC_GetConvertState().Bit.NormalComplete != 1) { + while (ADC_GetConvertState().Bit.NormalComplete != 1) { // Do nothing } // Convert result diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h index ab04cd5c0f..73b9c874f9 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/device.h @@ -19,6 +19,6 @@ #define DEVICE_ID_LENGTH 32 #include "objects.h" -#include "stddef.h" +#include #endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c index c0656e705b..a50b742be0 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_api.c @@ -42,7 +42,7 @@ void gpio_init(gpio_t *obj, PinName pin) obj->pin = pin; obj->mask = gpio_set(pin); obj->port = (GPIO_Port) (pin >> 3); - if((PortName)obj->port == PortH) { + if ((PortName)obj->port == PortH) { CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE); } if ((PortName)obj->port == PortJ) { @@ -68,7 +68,7 @@ void gpio_dir(gpio_t *obj, PinDirection direction) // Set pin output GPIO_SetOutput(obj->port, obj->mask); break; - case PIN_INOUT: + case PIN_INOUT: // Set pin both input and output GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE); GPIO_SetInputEnableReg(obj->port, obj->mask, ENABLE); @@ -89,7 +89,7 @@ void gpio_write(gpio_t *obj, int value) } } -int gpio_read (gpio_t *obj) +int gpio_read(gpio_t *obj) { // Read gpio object pin data return GPIO_ReadDataBit(obj->port, obj->mask); diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c index 46a3d03abc..c463d12405 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_irq_api.c @@ -13,11 +13,11 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include "string.h" #include "gpio_irq_api.h" #include "mbed_error.h" #include "PeripheralNames.h" #include "pinmap.h" +#include "mbed_critical.h" #define CHANNEL_NUM 6 @@ -103,19 +103,13 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 { // Get gpio interrupt ID obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); - - // Disable interrupt by CPU - __set_PRIMASK(1); - + core_util_critical_section_enter(); // Get pin mask obj->mask = (uint32_t)(1 << (pin & 0x07)); - // Get GPIO port obj->port = (GPIO_Port)(pin >> 3); - // Set pin level as LOW GPIO_WriteDataBit(obj->port, obj->mask, 0); - // Enable gpio interrupt function pinmap_pinout(pin, PinMap_GPIO_IRQ); @@ -145,21 +139,15 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 // Save irq handler hal_irq_handler[obj->irq_src] = handler; - // Save irq id channel_ids[obj->irq_src] = id; - // Initialize interrupt event as both edges detection obj->event = INTIFAO_INT_ACTIVE_STATE_INVALID; - // Set interrupt event and enable INTx clear INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE); - // Clear gpio pending interrupt NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); - - // Enable gpio interrupt - __set_PRIMASK(0); + core_util_critical_section_exit();; return 0; } @@ -218,7 +206,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) } } - if (obj->event != INTIFAO_INT_ACTIVE_STATE_INVALID ) { + if (obj->event != INTIFAO_INT_ACTIVE_STATE_INVALID) { // Set interrupt event and enable INTx clear INTIFAO_SetSTBYReleaseINTSrc(obj->irq_src, (INTIFAO_INTActiveState)obj->event, ENABLE); GPIO_SetOutputEnableReg(obj->port, obj->mask, DISABLE); diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h index 7852bb602d..72138a8c86 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/gpio_object.h @@ -30,7 +30,7 @@ typedef struct { static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; + return (obj->pin != (PinName)NC); } #ifdef __cplusplus diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c index 4d3e266ef4..d561e03ec7 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/i2c_api.c @@ -18,10 +18,14 @@ #include "PeripheralNames.h" #include "pinmap.h" -#define I2C_NACK (0) -#define I2C_ACK (1) -#define I2C_TIMEOUT (100000) -#define SELF_ADDR (0xE0) +#define I2C_NACK (0) +#define I2C_ACK (1) +#define I2C_NO_DATA (0) +#define I2C_READ_ADDRESSED (1) +#define I2C_WRITE_GENERAL (2) +#define I2C_WRITE_ADDRESSED (3) +#define SELF_ADDR (0xE0) +#define I2C_TIMEOUT (100000) static const PinMap PinMap_I2C_SDA[] = { {PC1, I2C_0, PIN_DATA(1, 2)}, @@ -42,7 +46,7 @@ typedef struct { uint32_t prsck; } I2C_clock_setting_t; -static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20, 24, 32, 48, 80, 144, 272, 528}; // SCK Divider value table +static const uint32_t I2C_SCK_DIVIDER_TBL[8] = {20, 24, 32, 48, 80, 144, 272, 528}; // SCK Divider value table static uint32_t start_flag = 0; I2C_clock_setting_t clk; I2C_State status; @@ -68,7 +72,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); MBED_ASSERT((int)i2c_name != NC); - switch(i2c_name) { + switch (i2c_name) { case I2C_0: CG_SetFcPeriphA(CG_FC_PERIPH_I2C0, ENABLE); obj->i2c = TSB_I2C0; @@ -153,7 +157,6 @@ int i2c_stop(i2c_t *obj) void i2c_reset(i2c_t *obj) { I2C_SWReset(obj->i2c); - return; } int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) @@ -165,7 +168,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) start_flag = 1; // Start Condition if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) { while (count < length) { - int32_t pdata = i2c_byte_read(obj, ((count < (length - 1))? 0: 1)); + int32_t pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1)); if (pdata < 0) { break; } @@ -245,7 +248,7 @@ int i2c_byte_write(i2c_t *obj, int data) I2C_ClearINTOutput(obj->i2c); - if(start_flag == 1) { + if (start_flag == 1) { I2C_Start_Condition(obj, (uint32_t)data); start_flag = 0; } else { @@ -265,14 +268,6 @@ int i2c_byte_write(i2c_t *obj, int data) return (result); } - -#if DEVICE_I2CSLAVE - -#define I2C_NO_DATA (0) -#define I2C_READ_ADDRESSED (1) -#define I2C_WRITE_GENERAL (2) -#define I2C_WRITE_ADDRESSED (3) - void i2c_slave_mode(i2c_t *obj, int enable_slave) { i2c_reset(obj); @@ -293,7 +288,6 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) I2C_Init(obj->i2c, &obj->myi2c); } - int i2c_slave_receive(i2c_t *obj) { int32_t result = I2C_NO_DATA; @@ -347,15 +341,3 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) obj->address = address & 0xFE; i2c_slave_mode(obj, 1); } - -#endif - -void INTI2C0_IRQHandler(void) -{ - -} - -void INTI2C1_IRQHandler(void) -{ - -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c index cbc499a1e8..78dbec1295 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/pinmap.c @@ -39,8 +39,8 @@ void pin_function(PinName pin, int function) // Set function if function is in range if (func <= PIN_FUNC_MAX) { // Disable other functions - for(i = 0; i < PIN_FUNC_MAX; i++) { - if(i != (func - 1)) { + for (i = 0; i < PIN_FUNC_MAX; i++) { + if (i != (func - 1)) { GPIO_DisableFuncReg((GPIO_Port)port, i, (1 << bit)); } } diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c index 83a22e563d..f8020aec2f 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/port_api.c @@ -36,7 +36,7 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) obj->port = port; obj->mask = mask; - if((PortName)obj->port == PortH) { + if ((PortName)obj->port == PortH) { CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE); } if ((PortName)obj->port == PortJ) { diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c index a872426fb0..f28af1aedb 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c @@ -18,7 +18,7 @@ #include "PeripheralNames.h" #include "pinmap.h" -#define UART_NUM 6 +#define UART_NUM 2 static const PinMap PinMap_UART_TX[] = { {PC2, SERIAL_0, PIN_DATA(1, 1)}, @@ -239,15 +239,3 @@ void serial_pinout_tx(PinName tx) { pinmap_pinout(tx, PinMap_UART_TX); } - -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ -} - -void serial_break_set(serial_t *obj) -{ -} - -void serial_break_clear(serial_t *obj) -{ -} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c index 5d8f0aca0b..79ee066031 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/sleep.c @@ -16,7 +16,7 @@ #include "sleep_api.h" // number of warm-up cycle = warm-up time to set / input frequency cycle (s) -// number of 3*10^-6 (s) / (1/12 (MHz) ) = 60000 = 0xea60 +// number of 3*10^-6 (s) / (1/12 (MHz)) = 60000 = 0xea60 #define CG_WUODR_INT ((uint16_t)0xea60) void external_losc_enable(void); diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c index 9f3f8d8b61..a2924c0f7a 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c @@ -24,7 +24,7 @@ static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? static volatile uint32_t acc_us_ticker = 0; // 16Bb high timer counter -static uint32_t us_ticker_16h = 0; +static volatile uint32_t us_ticker_16h = 0; void INT16A0_IRQHandler(void) { @@ -57,11 +57,10 @@ void us_ticker_init(void) NVIC_EnableIRQ(INT16A0_IRQn); // Match counter set to max value TSB_T16A0->RG = TMR16A_100US; - // TSB_T16A0->CP = 0x00; TSB_T16A0->RUN = TMR16A_RUN; } -uint32_t us_ticker_read() +uint32_t us_ticker_read(void) { uint32_t ret_val = 0; diff --git a/targets/targets.json b/targets/targets.json index a7e9e578dc..09d3b8d7a1 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3356,7 +3356,7 @@ "extra_labels": ["TOSHIBA"], "macros": ["__TMPM066__", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], - "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SLEEP", "I2C", "I2CSLAVE", "STDIO_MESSAGES", "PWMOUT"], + "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "I2C", "I2CSLAVE", "STDIO_MESSAGES", "PWMOUT"], "device_name": "TMPM066FWUG", "detect_code": ["7011"], "release_versions": ["5"] From 0a781c4f04731eb265fa2ef452f6134a94e83da5 Mon Sep 17 00:00:00 2001 From: Ganesh Ramachandran <30490592+ganesh-ramachandran@users.noreply.github.com> Date: Mon, 7 Aug 2017 17:27:51 +0530 Subject: [PATCH 3/7] ADC Reset Conflict Fixed ADC Reset conflict with already configured ADC pins is fixed --- targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c index cc2d737448..75bbdd7c4e 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/analogin_api.c @@ -18,6 +18,7 @@ #include "pinmap.h" #include "mbed_wait_api.h" +static uint8_t adc_reset_init = 0; // Is ADC Reset happened yet? #define ADC_10BIT_RANGE 0x3FF static const PinMap PinMap_ADC[] = { @@ -43,8 +44,11 @@ void analogin_init(analogin_t *obj, PinName pin) CG_SetADCClkSupply(ENABLE); // Set pin function as ADC pinmap_pinout(pin, PinMap_ADC); - // Software reset ADC - ADC_SWReset(); + if (!adc_reset_init) { + // Software reset ADC + ADC_SWReset(); + adc_reset_init = 1; + } // Set sample hold time and pre-scale clock ADC_SetClk(ADC_CONVERSION_81_CLOCK, ADC_FC_DIVIDE_LEVEL_8); // Set input channel From 9dca3fe5dfd534cdc362c4307093201f1baff217 Mon Sep 17 00:00:00 2001 From: Ganesh Ramachandran <30490592+ganesh-ramachandran@users.noreply.github.com> Date: Wed, 9 Aug 2017 19:11:36 +0530 Subject: [PATCH 4/7] Interrupt and Overflow check for us_ticker --- .../TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c | 34 +++++++++++++------ 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c index a2924c0f7a..841d3a25c4 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c @@ -14,24 +14,24 @@ * limitations under the License. */ #include "us_ticker_api.h" +#include "mbed_critical.h" #define TMR16A_100US 0x960 // fsys = fc = 24MHz, Ttmra = 1/24us, 100us*24us = 2400 = 0x960 #define TMR16A_SYSCK ((uint32_t)0x00000001) #define TMR16A_RUN ((uint32_t)0x00000001) #define TMR16A_STOP ((uint32_t)0x00000000) +#define OVERFLOW_32BIT (0xFFFFFFFF / 0x64) -static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? -static volatile uint32_t acc_us_ticker = 0; - -// 16Bb high timer counter -static volatile uint32_t us_ticker_16h = 0; +static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? +static volatile uint32_t ticker_int_counter = 0; // Amount of overflows until user interrupt +static volatile uint32_t us_ticker = 0; // timer counter void INT16A0_IRQHandler(void) { - us_ticker_16h++; - if (us_ticker_16h >= 0xFFFF) { - acc_us_ticker++; - us_ticker_16h = 0; + us_ticker++; + + if (us_ticker > OVERFLOW_32BIT) { + us_ticker = 0; } } @@ -67,18 +67,30 @@ uint32_t us_ticker_read(void) if (!us_ticker_inited) { us_ticker_init(); } - ret_val = (((acc_us_ticker << 16) + us_ticker_16h) * 100); + + uint32_t tickerbefore = 0; + do { + tickerbefore = us_ticker; + ret_val = (us_ticker * 100); + } while (tickerbefore != us_ticker); + return ret_val; } void us_ticker_set_interrupt(timestamp_t timestamp) { int delta = 0; + // Stops and clear count operation TSB_T16A1->RUN = TMR16A_STOP; TSB_T16A1->CR = TMR16A_SYSCK; // Set the compare register delta = (int)(timestamp - us_ticker_read()); + if (delta < 0) { + // Ticker interrupt handle + us_ticker_irq_handler(); + return; + } TSB_T16A1->RG = delta; // Set Interrupt NVIC_EnableIRQ(INT16A1_IRQn); @@ -98,5 +110,5 @@ void us_ticker_disable_interrupt(void) void us_ticker_clear_interrupt(void) { - //no flags to clear + NVIC_ClearPendingIRQ(INT16A1_IRQn); } From 48ee6a0fb69d13b5d84b598e9d4ee4d3930f3d16 Mon Sep 17 00:00:00 2001 From: Ganesh Ramachandran <30490592+ganesh-ramachandran@users.noreply.github.com> Date: Wed, 9 Aug 2017 19:32:59 +0530 Subject: [PATCH 5/7] Clear interrupt and delta check removed --- targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c index 841d3a25c4..4fd8ed13b9 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/us_ticker.c @@ -79,18 +79,13 @@ uint32_t us_ticker_read(void) void us_ticker_set_interrupt(timestamp_t timestamp) { - int delta = 0; + uint32_t delta = 0; // Stops and clear count operation TSB_T16A1->RUN = TMR16A_STOP; TSB_T16A1->CR = TMR16A_SYSCK; // Set the compare register - delta = (int)(timestamp - us_ticker_read()); - if (delta < 0) { - // Ticker interrupt handle - us_ticker_irq_handler(); - return; - } + delta = (timestamp - us_ticker_read()); TSB_T16A1->RG = delta; // Set Interrupt NVIC_EnableIRQ(INT16A1_IRQn); @@ -110,5 +105,5 @@ void us_ticker_disable_interrupt(void) void us_ticker_clear_interrupt(void) { - NVIC_ClearPendingIRQ(INT16A1_IRQn); + //no flags to clear } From 552feccca322d49bd6e7bc111cb370e051437ecf Mon Sep 17 00:00:00 2001 From: Ganesh Ramachandran <30490592+ganesh-ramachandran@users.noreply.github.com> Date: Thu, 10 Aug 2017 11:25:46 +0530 Subject: [PATCH 6/7] Main stack dependant on GCC toolchain removed --- targets/TARGET_TOSHIBA/mbed_rtx.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/targets/TARGET_TOSHIBA/mbed_rtx.h b/targets/TARGET_TOSHIBA/mbed_rtx.h index aeacbcf322..18428f07ff 100644 --- a/targets/TARGET_TOSHIBA/mbed_rtx.h +++ b/targets/TARGET_TOSHIBA/mbed_rtx.h @@ -23,10 +23,6 @@ #define INITIAL_SP (0x20004000UL) #endif -#ifdef TOOLCHAIN_GCC_ARM -#define MBED_CONF_APP_MAIN_STACK_SIZE 2048 -#endif - #endif #endif // MBED_MBED_RTX_H From f79216c8d8cfb8113355cee8fcfd89710e29194f Mon Sep 17 00:00:00 2001 From: Ganesh Ramachandran <30490592+ganesh-ramachandran@users.noreply.github.com> Date: Thu, 17 Aug 2017 11:14:09 +0530 Subject: [PATCH 7/7] Issue with mbed compile for GCC_ARM tool resolved Functions 'serial_break_set' & 'serial_break_clear' wrongly removed during 'SERIAL_FC disabled, critical section API Updation' commit. Due to this 'mbed compile' command for GCC_ARM tool fails to compile. --- targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c index f28af1aedb..46106877fd 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/serial_api.c @@ -239,3 +239,11 @@ void serial_pinout_tx(PinName tx) { pinmap_pinout(tx, PinMap_UART_TX); } + +void serial_break_set(serial_t *obj) +{ +} + +void serial_break_clear(serial_t *obj) +{ +}