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Disabled interrupts on smt32f7 and stm32h7 before calling disable data cache 

Interrupts are disabled before calling disable data cache on Ethernet initialization.
pull/15006/head
Mika Leppänen 2021-08-16 12:27:39 +03:00
parent ca5126e2e4
commit 096ce41094
9 changed files with 27 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c
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@ -29,6 +29,7 @@
#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT #ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
#include "stm32f7xx_hal.h" #include "stm32f7xx_hal.h"
#include "platform/mbed_critical.h"
/** /**
* Override HAL Eth Init function * Override HAL Eth Init function
@ -38,7 +39,9 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) { if (heth->Instance == ETH) {
/* Disable DCache for STM32F7 family */ /* Disable DCache for STM32F7 family */
core_util_critical_section_enter();
SCB_DisableDCache(); SCB_DisableDCache();
core_util_critical_section_exit();
/* Enable GPIOs clocks */ /* Enable GPIOs clocks */
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();

3
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c
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@ -29,6 +29,7 @@
#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT #ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
#include "stm32f7xx_hal.h" #include "stm32f7xx_hal.h"
#include "platform/mbed_critical.h"
/** /**
* Override HAL Eth Init function * Override HAL Eth Init function
@ -38,7 +39,9 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) { if (heth->Instance == ETH) {
/* Disable DCache for STM32F7 family */ /* Disable DCache for STM32F7 family */
core_util_critical_section_enter();
SCB_DisableDCache(); SCB_DisableDCache();
core_util_critical_section_exit();
/* Enable GPIOs clocks */ /* Enable GPIOs clocks */
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();

3
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c
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@ -29,6 +29,7 @@
#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT #ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
#include "stm32f7xx_hal.h" #include "stm32f7xx_hal.h"
#include "platform/mbed_critical.h"
/** /**
* Override HAL Eth Init function * Override HAL Eth Init function
@ -38,7 +39,9 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) { if (heth->Instance == ETH) {
/* Disable DCache for STM32F7 family */ /* Disable DCache for STM32F7 family */
core_util_critical_section_enter();
SCB_DisableDCache(); SCB_DisableDCache();
core_util_critical_section_exit();
/* Enable GPIOs clocks */ /* Enable GPIOs clocks */
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();

3
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c
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@ -29,6 +29,7 @@
#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT #ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
#include "stm32f7xx_hal.h" #include "stm32f7xx_hal.h"
#include "platform/mbed_critical.h"
/** /**
* Override HAL Eth Init function * Override HAL Eth Init function
@ -38,7 +39,9 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) { if (heth->Instance == ETH) {
/* Disable DCache for STM32F7 family */ /* Disable DCache for STM32F7 family */
core_util_critical_section_enter();
SCB_DisableDCache(); SCB_DisableDCache();
core_util_critical_section_exit();
/* Enable GPIOs clocks */ /* Enable GPIOs clocks */
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();

3
connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c
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@ -29,6 +29,7 @@
#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT #ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
#include "stm32f7xx_hal.h" #include "stm32f7xx_hal.h"
#include "platform/mbed_critical.h"
/** /**
* Override HAL Eth Init function * Override HAL Eth Init function
@ -38,7 +39,9 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) { if (heth->Instance == ETH) {
/* Disable DCache for STM32F7 family */ /* Disable DCache for STM32F7 family */
core_util_critical_section_enter();
SCB_DisableDCache(); SCB_DisableDCache();
core_util_critical_section_exit();
/* Enable GPIOs clocks */ /* Enable GPIOs clocks */
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();

3
connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_DISCO_H747I/stm32h7_eth_init.c
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@ -36,6 +36,7 @@
#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT #ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
#include "stm32h7xx_hal.h" #include "stm32h7xx_hal.h"
#include "platform/mbed_critical.h"
#define ETH_TX_EN_Pin GPIO_PIN_11 #define ETH_TX_EN_Pin GPIO_PIN_11
#define ETH_TX_EN_GPIO_Port GPIOG #define ETH_TX_EN_GPIO_Port GPIOG
@ -66,7 +67,9 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
if (heth->Instance == ETH) { if (heth->Instance == ETH) {
#if defined(CORE_CM7) #if defined(CORE_CM7)
/* Disable DCache for STM32H7 family */ /* Disable DCache for STM32H7 family */
core_util_critical_section_enter();
SCB_DisableDCache(); SCB_DisableDCache();
core_util_critical_section_exit();
#endif #endif
/* GPIO Ports Clock Enable */ /* GPIO Ports Clock Enable */

3
connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H743ZI/stm32h7_eth_init.c
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@ -29,6 +29,7 @@
#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT #ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
#include "stm32h7xx_hal.h" #include "stm32h7xx_hal.h"
#include "platform/mbed_critical.h"
#define MCO_Pin GPIO_PIN_0 #define MCO_Pin GPIO_PIN_0
#define MCO_GPIO_Port GPIOH #define MCO_GPIO_Port GPIOH
@ -63,7 +64,9 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
if (heth->Instance == ETH) { if (heth->Instance == ETH) {
/* Disable DCache for STM32H7 family */ /* Disable DCache for STM32H7 family */
core_util_critical_section_enter();
SCB_DisableDCache(); SCB_DisableDCache();
core_util_critical_section_exit();
/* GPIO Ports Clock Enable */ /* GPIO Ports Clock Enable */
__HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE();

3
connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H743ZI2/stm32h7_eth_init.c
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@ -29,6 +29,7 @@
#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT #ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
#include "stm32h7xx_hal.h" #include "stm32h7xx_hal.h"
#include "platform/mbed_critical.h"
#define MCO_Pin GPIO_PIN_0 #define MCO_Pin GPIO_PIN_0
#define MCO_GPIO_Port GPIOH #define MCO_GPIO_Port GPIOH
@ -63,7 +64,9 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
if (heth->Instance == ETH) { if (heth->Instance == ETH) {
/* Disable DCache for STM32H7 family */ /* Disable DCache for STM32H7 family */
core_util_critical_section_enter();
SCB_DisableDCache(); SCB_DisableDCache();
core_util_critical_section_exit();
/* GPIO Ports Clock Enable */ /* GPIO Ports Clock Enable */
__HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE();

3
connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c
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@ -35,6 +35,7 @@
#include "stm32h7xx_hal.h" #include "stm32h7xx_hal.h"
#include "portenta_power.h" #include "portenta_power.h"
#include "platform/mbed_critical.h"
#define ETH_TX_EN_Pin GPIO_PIN_11 #define ETH_TX_EN_Pin GPIO_PIN_11
#define ETH_TX_EN_GPIO_Port GPIOG #define ETH_TX_EN_GPIO_Port GPIOG
@ -66,7 +67,9 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
#if !(defined(DUAL_CORE) && defined(CORE_CM4)) #if !(defined(DUAL_CORE) && defined(CORE_CM4))
/* Disable DCache for STM32H7 family */ /* Disable DCache for STM32H7 family */
core_util_critical_section_enter();
SCB_DisableDCache(); SCB_DisableDCache();
core_util_critical_section_exit();
#endif #endif
/* GPIO Ports Clock Enable */ /* GPIO Ports Clock Enable */