ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

CMSIS/RTX: Pre-processor defines used for assembly 

CMSIS repo does not support pre-processor defines, hence multiple assembly
files are added for secure/non-secure and floating point tools.
Mbed OS tools support assembly file pre-processing, but the build system
does not support multiple assembly files for each target, hence updating
the assembly files.

1. Patch RTX so irq_cm4f.S files work with no FPU targets
2. Patch RTX so irq_armv8mml.S files to work with and without FPU
2. Patch RTX so irq_armv8mml.S and irq_armv8mbl.S files to work with secure and
   non-secure builds
pull/9437/head
Bartek Szatkowski 2017-07-04 15:22:20 +01:00 committed by Deepika
parent bb25e8660d
commit 094662790a
9 changed files with 43 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S
View File

@ -24,9 +24,9 @@
; */ ; */
IF :LNOT::DEF:DOMAIN_NS #ifndef DOMAIN_NS
DOMAIN_NS EQU 0 DOMAIN_NS EQU 0
ENDIF #endif
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset TCB_SM_OFS EQU 48 ; TCB.stack_mem offset

13
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S
View File

@ -24,15 +24,16 @@
; */ ; */
IF :LNOT::DEF:DOMAIN_NS #ifndef DOMAIN_NS
DOMAIN_NS EQU 0 DOMAIN_NS EQU 0
ENDIF #endif
IF ({FPU}="FPv5-SP") || ({FPU}="FPv5_D16") #ifdef __ARM_FP
__FPU_USED EQU 1 __FPU_USED EQU 1
ELSE #else
__FPU_USED EQU 0 __FPU_USED EQU 0
ENDIF #endif
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset TCB_SM_OFS EQU 48 ; TCB.stack_mem offset

7
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S
View File

@ -74,17 +74,22 @@ SVC_Context
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch BNE SVC_ContextSwitch
#ifdef __FPU_PRESENT
LDR R1,=0xE000EF34 ; FPCCR Address LDR R1,=0xE000EF34 ; FPCCR Address
LDR R0,[R1] ; Load FPCCR LDR R0,[R1] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state) BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
STR R0,[R1] ; Store FPCCR STR R0,[R1] ; Store FPCCR
B SVC_ContextSwitch B SVC_ContextSwitch
#endif
SVC_ContextSave SVC_ContextSave
STMDB R12!,{R4-R11} ; Save R4..R11 STMDB R12!,{R4-R11} ; Save R4..R11
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
IT EQ IT EQ
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
#endif
STR R12,[R1,#TCB_SP_OFS] ; Store SP STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
@ -103,9 +108,11 @@ SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
IT EQ IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} ; Restore R4..R11 LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP MSR PSP,R0 ; Set PSP

4
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S
View File

@ -27,9 +27,9 @@
.file "irq_armv8mbl.S" .file "irq_armv8mbl.S"
.syntax unified .syntax unified
.ifndef DOMAIN_NS #ifndef DOMAIN_NS
.equ DOMAIN_NS, 0 .equ DOMAIN_NS, 0
.endif #endif
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
.equ TCB_SM_OFS, 48 // TCB.stack_mem offset .equ TCB_SM_OFS, 48 // TCB.stack_mem offset

10
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S
View File

@ -27,13 +27,15 @@
.file "irq_armv8mml.S" .file "irq_armv8mml.S"
.syntax unified .syntax unified
.ifndef DOMAIN_NS #ifndef DOMAIN_NS
.equ DOMAIN_NS, 0 .equ DOMAIN_NS, 0
.endif #endif
.ifndef __FPU_USED #if defined (__VFP_FP__) && !defined(__SOFTFP__)
.equ __FPU_USED, 1
#else
.equ __FPU_USED, 0 .equ __FPU_USED, 0
.endif #endif
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
.equ TCB_SM_OFS, 48 // TCB.stack_mem offset .equ TCB_SM_OFS, 48 // TCB.stack_mem offset

7
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S
View File

@ -74,17 +74,22 @@ SVC_Context:
CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted
TST LR,#0x10 // Check if extended stack frame TST LR,#0x10 // Check if extended stack frame
BNE SVC_ContextSwitch BNE SVC_ContextSwitch
#ifdef __FPU_PRESENT
LDR R1,=0xE000EF34 // FPCCR Address LDR R1,=0xE000EF34 // FPCCR Address
LDR R0,[R1] // Load FPCCR LDR R0,[R1] // Load FPCCR
BIC R0,R0,#1 // Clear LSPACT (Lazy state) BIC R0,R0,#1 // Clear LSPACT (Lazy state)
STR R0,[R1] // Store FPCCR STR R0,[R1] // Store FPCCR
B SVC_ContextSwitch B SVC_ContextSwitch
#endif
SVC_ContextSave: SVC_ContextSave:
STMDB R12!,{R4-R11} // Save R4..R11 STMDB R12!,{R4-R11} // Save R4..R11
#ifdef __FPU_PRESENT
TST LR,#0x10 // Check if extended stack frame TST LR,#0x10 // Check if extended stack frame
IT EQ IT EQ
VSTMDBEQ R12!,{S16-S31} // Save VFP S16.S31 VSTMDBEQ R12!,{S16-S31} // Save VFP S16.S31
#endif
STR R12,[R1,#TCB_SP_OFS] // Store SP STR R12,[R1,#TCB_SP_OFS] // Store SP
STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information
@ -96,9 +101,11 @@ SVC_ContextRestore:
LDR R0,[R2,#TCB_SP_OFS] // Load SP LDR R0,[R2,#TCB_SP_OFS] // Load SP
ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN
#ifdef __FPU_PRESENT
TST LR,#0x10 // Check if extended stack frame TST LR,#0x10 // Check if extended stack frame
IT EQ IT EQ
VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31 VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} // Restore R4..R11 LDMIA R0!,{R4-R11} // Restore R4..R11
MSR PSP,R0 // Set PSP MSR PSP,R0 // Set PSP

2
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S
View File

@ -297,3 +297,5 @@ Sys_ContextRestore2
Sys_ContextExit Sys_ContextExit
BX LR ; Exit from handler BX LR ; Exit from handler
END

2
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S
View File

@ -270,3 +270,5 @@ Sys_ContextRestore2
Sys_ContextExit Sys_ContextExit
BX LR ; Exit from handler BX LR ; Exit from handler
END

7
rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S
View File

@ -74,17 +74,22 @@ SVC_Context
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch BNE SVC_ContextSwitch
#ifdef __FPU_PRESENT
LDR R1,=0xE000EF34 ; FPCCR Address LDR R1,=0xE000EF34 ; FPCCR Address
LDR R0,[R1] ; Load FPCCR LDR R0,[R1] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state) BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
STR R0,[R1] ; Store FPCCR STR R0,[R1] ; Store FPCCR
B SVC_ContextSwitch B SVC_ContextSwitch
#endif
SVC_ContextSave SVC_ContextSave
STMDB R12!,{R4-R11} ; Save R4..R11 STMDB R12!,{R4-R11} ; Save R4..R11
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
IT EQ IT EQ
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
#endif
STR R12,[R1,#TCB_SP_OFS] ; Store SP STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
@ -96,9 +101,11 @@ SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
#ifdef __FPU_PRESENT
TST LR,#0x10 ; Check if extended stack frame TST LR,#0x10 ; Check if extended stack frame
IT EQ IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} ; Restore R4..R11 LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP MSR PSP,R0 ; Set PSP