From 08b49159d35ec06545422cd4ae7492c6ca0f9407 Mon Sep 17 00:00:00 2001
From: chao_king <37656088+ChazJin@users.noreply.github.com>
Date: Tue, 13 Nov 2018 16:11:02 +0800
Subject: [PATCH] Re add target support for GD32F307VG
1. Mainly change TARGET_Gigadevice --> TARGET_GigaDevice
2. Add license header
---
.../TATGET_GD32F307VG/PinNames.h | 2 +
.../TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.s | 362 ++++++++++++
.../TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.s | 359 ++++++++++++
.../TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.s | 413 ++++++++++++++
.../TOOLCHAIN_IAR/startup_gd32f30x_cl.s | 526 ++++++++++++++++++
5 files changed, 1662 insertions(+)
create mode 100644 targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.s
create mode 100644 targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.s
create mode 100644 targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.s
create mode 100644 targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.s
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/PinNames.h b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/PinNames.h
index 6ce3ace621..1556d25dd4 100644
--- a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/PinNames.h
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/PinNames.h
@@ -177,9 +177,11 @@ typedef enum {
KEY2 = PORTA_0,
KEY3 = PORTB_1,
+ KEY4 = PORTD_2,
BUTTON1 = KEY2,
BUTTON2 = KEY3,
+ BUTTON3 = KEY4,
SERIAL_TX = PORTA_9,
SERIAL_RX = PORTA_10,
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.s b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.s
new file mode 100644
index 0000000000..e0b82158ec
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.s
@@ -0,0 +1,362 @@
+;/*!
+; \file startup_gd32f30x_cl.s
+; \brief start up file
+;
+; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
+;*/
+;
+;/*
+; Copyright (c) 2018, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+;are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this
+; list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+;OF SUCH DAMAGE.
+;*/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20010000 ; Top of RAM
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit EQU (__initial_sp - Stack_Size)
+
+ PRESERVE8
+ THUMB
+
+; /* reset Vector Mapped to at Address 0 */
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+; /* external interrupts handler */
+ DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
+ DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
+ DCD RTC_IRQHandler ; 19:RTC through EXTI Line
+ DCD FMC_IRQHandler ; 20:FMC
+ DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
+ DCD EXTI0_IRQHandler ; 22:EXTI Line 0
+ DCD EXTI1_IRQHandler ; 23:EXTI Line 1
+ DCD EXTI2_IRQHandler ; 24:EXTI Line 2
+ DCD EXTI3_IRQHandler ; 25:EXTI Line 3
+ DCD EXTI4_IRQHandler ; 26:EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
+ DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
+ DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
+ DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
+ DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
+ DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
+ DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
+ DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
+ DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
+ DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
+ DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
+ DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
+ DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
+ DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; 44:TIMER1
+ DCD TIMER2_IRQHandler ; 45:TIMER2
+ DCD TIMER3_IRQHandler ; 46:TIMER3
+ DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
+ DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
+ DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
+ DCD SPI0_IRQHandler ; 51:SPI0
+ DCD SPI1_IRQHandler ; 52:SPI1
+ DCD USART0_IRQHandler ; 53:USART0
+ DCD USART1_IRQHandler ; 54:USART1
+ DCD USART2_IRQHandler ; 55:USART2
+ DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
+ DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
+ DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
+ DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
+ DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
+ DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
+ DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
+ DCD 0 ; Reserved
+ DCD EXMC_IRQHandler ; 64:EXMC
+ DCD 0 ; Reserved
+ DCD TIMER4_IRQHandler ; 66:TIMER4
+ DCD SPI2_IRQHandler ; 67:SPI2
+ DCD UART3_IRQHandler ; 68:UART3
+ DCD UART4_IRQHandler ; 69:UART4
+ DCD TIMER5_IRQHandler ; 70:TIMER5
+ DCD TIMER6_IRQHandler ; 71:TIMER6
+ DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
+ DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
+ DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
+ DCD ENET_IRQHandler ; 77:Ethernet
+ DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
+ DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
+ DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
+ DCD USBFS_IRQHandler ; 83:USBFS
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; /* external interrupts handler */
+ EXPORT WWDGT_IRQHandler [WEAK]
+ EXPORT LVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT RCU_CTC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel0_IRQHandler [WEAK]
+ EXPORT DMA0_Channel1_IRQHandler [WEAK]
+ EXPORT DMA0_Channel2_IRQHandler [WEAK]
+ EXPORT DMA0_Channel3_IRQHandler [WEAK]
+ EXPORT DMA0_Channel4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel5_IRQHandler [WEAK]
+ EXPORT DMA0_Channel6_IRQHandler [WEAK]
+ EXPORT ADC0_1_IRQHandler [WEAK]
+ EXPORT CAN0_TX_IRQHandler [WEAK]
+ EXPORT CAN0_RX0_IRQHandler [WEAK]
+ EXPORT CAN0_RX1_IRQHandler [WEAK]
+ EXPORT CAN0_EWMC_IRQHandler [WEAK]
+ EXPORT EXTI5_9_IRQHandler [WEAK]
+ EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
+ EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
+ EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
+ EXPORT TIMER0_Channel_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT I2C0_EV_IRQHandler [WEAK]
+ EXPORT I2C0_ER_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART0_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT EXTI10_15_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBFS_WKUP_IRQHandler [WEAK]
+ EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
+ EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
+ EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
+ EXPORT TIMER7_Channel_IRQHandler [WEAK]
+ EXPORT EXMC_IRQHandler [WEAK]
+ EXPORT TIMER4_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT TIMER5_IRQHandler [WEAK]
+ EXPORT TIMER6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel0_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT ENET_WKUP_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_EWMC_IRQHandler [WEAK]
+ EXPORT USBFS_IRQHandler [WEAK]
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FMC_IRQHandler
+RCU_CTC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA0_Channel0_IRQHandler
+DMA0_Channel1_IRQHandler
+DMA0_Channel2_IRQHandler
+DMA0_Channel3_IRQHandler
+DMA0_Channel4_IRQHandler
+DMA0_Channel5_IRQHandler
+DMA0_Channel6_IRQHandler
+ADC0_1_IRQHandler
+CAN0_TX_IRQHandler
+CAN0_RX0_IRQHandler
+CAN0_RX1_IRQHandler
+CAN0_EWMC_IRQHandler
+EXTI5_9_IRQHandler
+TIMER0_BRK_TIMER8_IRQHandler
+TIMER0_UP_TIMER9_IRQHandler
+TIMER0_TRG_CMT_TIMER10_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+I2C0_EV_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI10_15_IRQHandler
+RTC_Alarm_IRQHandler
+USBFS_WKUP_IRQHandler
+TIMER7_BRK_TIMER11_IRQHandler
+TIMER7_UP_TIMER12_IRQHandler
+TIMER7_TRG_CMT_TIMER13_IRQHandler
+TIMER7_Channel_IRQHandler
+EXMC_IRQHandler
+TIMER4_IRQHandler
+SPI2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+TIMER5_IRQHandler
+TIMER6_IRQHandler
+DMA1_Channel0_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+ENET_IRQHandler
+ENET_WKUP_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_EWMC_IRQHandler
+USBFS_IRQHandler
+
+ B .
+ ENDP
+
+ ALIGN
+
+ END
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.s b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.s
new file mode 100644
index 0000000000..8d77cf028b
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.s
@@ -0,0 +1,359 @@
+;/*!
+; \file startup_gd32f30x_cl.s
+; \brief start up file
+;
+; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
+;*/
+;
+;/*
+; Copyright (c) 2018, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+;are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this
+; list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+;OF SUCH DAMAGE.
+;*/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20018000
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; /* reset Vector Mapped to at Address 0 */
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+; /* external interrupts handler */
+ DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
+ DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
+ DCD RTC_IRQHandler ; 19:RTC through EXTI Line
+ DCD FMC_IRQHandler ; 20:FMC
+ DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
+ DCD EXTI0_IRQHandler ; 22:EXTI Line 0
+ DCD EXTI1_IRQHandler ; 23:EXTI Line 1
+ DCD EXTI2_IRQHandler ; 24:EXTI Line 2
+ DCD EXTI3_IRQHandler ; 25:EXTI Line 3
+ DCD EXTI4_IRQHandler ; 26:EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
+ DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
+ DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
+ DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
+ DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
+ DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
+ DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
+ DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
+ DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
+ DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
+ DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
+ DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
+ DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
+ DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; 44:TIMER1
+ DCD TIMER2_IRQHandler ; 45:TIMER2
+ DCD TIMER3_IRQHandler ; 46:TIMER3
+ DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
+ DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
+ DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
+ DCD SPI0_IRQHandler ; 51:SPI0
+ DCD SPI1_IRQHandler ; 52:SPI1
+ DCD USART0_IRQHandler ; 53:USART0
+ DCD USART1_IRQHandler ; 54:USART1
+ DCD USART2_IRQHandler ; 55:USART2
+ DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
+ DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
+ DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
+ DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
+ DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
+ DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
+ DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
+ DCD 0 ; Reserved
+ DCD EXMC_IRQHandler ; 64:EXMC
+ DCD 0 ; Reserved
+ DCD TIMER4_IRQHandler ; 66:TIMER4
+ DCD SPI2_IRQHandler ; 67:SPI2
+ DCD UART3_IRQHandler ; 68:UART3
+ DCD UART4_IRQHandler ; 69:UART4
+ DCD TIMER5_IRQHandler ; 70:TIMER5
+ DCD TIMER6_IRQHandler ; 71:TIMER6
+ DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
+ DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
+ DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
+ DCD ENET_IRQHandler ; 77:Ethernet
+ DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
+ DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
+ DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
+ DCD USBFS_IRQHandler ; 83:USBFS
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; /* external interrupts handler */
+ EXPORT WWDGT_IRQHandler [WEAK]
+ EXPORT LVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT RCU_CTC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel0_IRQHandler [WEAK]
+ EXPORT DMA0_Channel1_IRQHandler [WEAK]
+ EXPORT DMA0_Channel2_IRQHandler [WEAK]
+ EXPORT DMA0_Channel3_IRQHandler [WEAK]
+ EXPORT DMA0_Channel4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel5_IRQHandler [WEAK]
+ EXPORT DMA0_Channel6_IRQHandler [WEAK]
+ EXPORT ADC0_1_IRQHandler [WEAK]
+ EXPORT CAN0_TX_IRQHandler [WEAK]
+ EXPORT CAN0_RX0_IRQHandler [WEAK]
+ EXPORT CAN0_RX1_IRQHandler [WEAK]
+ EXPORT CAN0_EWMC_IRQHandler [WEAK]
+ EXPORT EXTI5_9_IRQHandler [WEAK]
+ EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
+ EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
+ EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
+ EXPORT TIMER0_Channel_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT I2C0_EV_IRQHandler [WEAK]
+ EXPORT I2C0_ER_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART0_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT EXTI10_15_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBFS_WKUP_IRQHandler [WEAK]
+ EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
+ EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
+ EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
+ EXPORT TIMER7_Channel_IRQHandler [WEAK]
+ EXPORT EXMC_IRQHandler [WEAK]
+ EXPORT TIMER4_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT TIMER5_IRQHandler [WEAK]
+ EXPORT TIMER6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel0_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT ENET_WKUP_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_EWMC_IRQHandler [WEAK]
+ EXPORT USBFS_IRQHandler [WEAK]
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FMC_IRQHandler
+RCU_CTC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA0_Channel0_IRQHandler
+DMA0_Channel1_IRQHandler
+DMA0_Channel2_IRQHandler
+DMA0_Channel3_IRQHandler
+DMA0_Channel4_IRQHandler
+DMA0_Channel5_IRQHandler
+DMA0_Channel6_IRQHandler
+ADC0_1_IRQHandler
+CAN0_TX_IRQHandler
+CAN0_RX0_IRQHandler
+CAN0_RX1_IRQHandler
+CAN0_EWMC_IRQHandler
+EXTI5_9_IRQHandler
+TIMER0_BRK_TIMER8_IRQHandler
+TIMER0_UP_TIMER9_IRQHandler
+TIMER0_TRG_CMT_TIMER10_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+I2C0_EV_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI10_15_IRQHandler
+RTC_Alarm_IRQHandler
+USBFS_WKUP_IRQHandler
+TIMER7_BRK_TIMER11_IRQHandler
+TIMER7_UP_TIMER12_IRQHandler
+TIMER7_TRG_CMT_TIMER13_IRQHandler
+TIMER7_Channel_IRQHandler
+EXMC_IRQHandler
+TIMER4_IRQHandler
+SPI2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+TIMER5_IRQHandler
+TIMER6_IRQHandler
+DMA1_Channel0_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+ENET_IRQHandler
+ENET_WKUP_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_EWMC_IRQHandler
+USBFS_IRQHandler
+
+ B .
+ ENDP
+
+ ALIGN
+
+ END
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.s b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.s
new file mode 100644
index 0000000000..1f50d990d8
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.s
@@ -0,0 +1,413 @@
+;/*!
+; \file startup_gd32f30x_cl.s
+; \brief start up file
+;
+; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
+;*/
+;
+;/*
+; Copyright (c) 2018, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+;are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this
+; list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+;OF SUCH DAMAGE.
+;*/
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global VecTab
+.global Default_Handler
+
+/* start address of the initialization .data */
+.word _sidata
+/* start address of the .data section */
+.word _sdata
+/* end address of the .data section */
+.word _edata
+
+/* reset Handler */
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* copy the data segment into RAM */
+ movs r1, #0
+ b DataInit
+
+CopyData:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+DataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyData
+
+/* system clock intitialization*/
+ bl SystemInit
+/* static constructors */
+// bl __libc_init_array
+/* jump to application's entry point */
+// bl main
+ bl _start
+/* infinite loop */
+ b .
+
+
+.size Reset_Handler, .-Reset_Handler
+
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+/* infinite loop */
+ b .
+ .size Default_Handler, .-Default_Handler
+
+ .section .isr_vector,"a",%progbits
+ .type VecTab, %object
+ .size VecTab, .-VecTab
+
+
+VecTab:
+
+ .word _estack /* Top of Stack */
+ .word Reset_Handler /* 1,Reset Handler */
+ .word NMI_Handler /* 2,NMI Handler */
+ .word HardFault_Handler /* 3,Hard Fault Handler */
+ .word MemManage_Handler /* 4,MPU Fault Handler */
+ .word BusFault_Handler /* 5,Bus Fault Handler */
+ .word UsageFault_Handler /* 6,Usage Fault Handler */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word SVC_Handler /* 11,SVCall Handler */
+ .word DebugMon_Handler /* 12,Debug Monitor Handler */
+ .word 0 /* Reserved */
+ .word PendSV_Handler /* 14,PendSV Handler */
+ .word SysTick_Handler /* 15,SysTick Handler */
+ /* External Interrupts */
+ .word WWDGT_IRQHandler /* 16,Window Watchdog Timer */
+ .word LVD_IRQHandler /* 17,LVD through EXTI Line detect */
+ .word TAMPER_IRQHandler /* 18,Tamper through EXTI Line detect */
+ .word RTC_IRQHandler /* 19,RTC through EXTI Line */
+ .word FMC_IRQHandler /* 20,FMC */
+ .word RCU_CTC_IRQHandler /* 21,RCU and CTC */
+ .word EXTI0_IRQHandler /* 22,EXTI Line 0 */
+ .word EXTI1_IRQHandler /* 23,EXTI Line 1 */
+ .word EXTI2_IRQHandler /* 24,EXTI Line 2 */
+ .word EXTI3_IRQHandler /* 25,EXTI Line 3 */
+ .word EXTI4_IRQHandler /* 26,EXTI Line 4 */
+ .word DMA0_Channel0_IRQHandler /* 27,DMA0 Channel 0 */
+ .word DMA0_Channel1_IRQHandler /* 28,DMA0 Channel 1 */
+ .word DMA0_Channel2_IRQHandler /* 29,DMA0 Channel 2 */
+ .word DMA0_Channel3_IRQHandler /* 30,DMA0 Channel 3 */
+ .word DMA0_Channel4_IRQHandler /* 31,DMA0 Channel 4 */
+ .word DMA0_Channel5_IRQHandler /* 32,DMA0 Channel 5 */
+ .word DMA0_Channel6_IRQHandler /* 33,DMA0 Channel 6 */
+ .word ADC0_1_IRQHandler /* 34,ADC0 and ADC1 */
+ .word CAN0_TX_IRQHandler /* 35,CAN0 TX */
+ .word CAN0_RX0_IRQHandler /* 36,CAN0 RX0 */
+ .word CAN0_RX1_IRQHandler /* 37,CAN0 RX1 */
+ .word CAN0_EWMC_IRQHandler /* 38,CAN0 EWMC */
+ .word EXTI5_9_IRQHandler /* 39,EXTI5 to EXTI9 */
+ .word TIMER0_BRK_TIMER8_IRQHandler /* 40,TIMER0 Break and TIMER8 */
+ .word TIMER0_UP_TIMER9_IRQHandler /* 41,TIMER0 Update and TIMER9 */
+ .word TIMER0_TRG_CMT_TIMER10_IRQHandler /* 42,TIMER0 Trigger and Commutation and TIMER10 */
+ .word TIMER0_Channel_IRQHandler /* 43,TIMER0 Channel Capture Compare */
+ .word TIMER1_IRQHandler /* 44,TIMER4 */
+ .word TIMER2_IRQHandler /* 45,TIMER2 */
+ .word TIMER3_IRQHandler /* 46,TIMER3 */
+ .word I2C0_EV_IRQHandler /* 47,I2C0 Event */
+ .word I2C0_ER_IRQHandler /* 48,I2C0 Error */
+ .word I2C1_EV_IRQHandler /* 49,I2C1 Event */
+ .word I2C1_ER_IRQHandler /* 50,I2C1 Error */
+ .word SPI0_IRQHandler /* 51,SPI0 */
+ .word SPI1_IRQHandler /* 52,SPI1 */
+ .word USART0_IRQHandler /* 53,USART0 */
+ .word USART1_IRQHandler /* 54,USART1 */
+ .word USART2_IRQHandler /* 55,USART2 */
+ .word EXTI10_15_IRQHandler /* 56,EXTI10 to EXTI15 */
+ .word RTC_Alarm_IRQHandler /* 57,RTC Alarm */
+ .word USBFS_WKUP_IRQHandler /* 58,USBFS Wakeup */
+ .word TIMER7_BRK_TIMER11_IRQHandler /* 59,TIMER7 Break and TIMER11 */
+ .word TIMER7_UP_TIMER12_IRQHandler /* 60:TIMER7 Update and TIMER12 */
+ .word TIMER7_TRG_CMT_TIMER13_IRQHandler /* 61:TIMER7 Trigger and Commutation and TIMER13 */
+ .word TIMER7_Channel_IRQHandler /* 62,TIMER7 Capture Compare */
+ .word 0 /* Reserved */
+ .word EXMC_IRQHandler /* 64,EXMC */
+ .word 0 /* Reserved */
+ .word TIMER4_IRQHandler /* 66,TIMER4 */
+ .word SPI2_IRQHandler /* 67,SPI2 */
+ .word UART3_IRQHandler /* 68,UART3 */
+ .word UART4_IRQHandler /* 69,UART4 */
+ .word TIMER5_IRQHandler /* 70,TIMER5 */
+ .word TIMER6_IRQHandler /* 71,TIMER6 */
+ .word DMA1_Channel0_IRQHandler /* 72,DMA1 Channel0 */
+ .word DMA1_Channel1_IRQHandler /* 73,DMA1 Channel1 */
+ .word DMA1_Channel2_IRQHandler /* 74,DMA1 Channel2 */
+ .word DMA1_Channel3_IRQHandler /* 75,DMA1 Channel3 */
+ .word DMA1_Channel4_IRQHandler /* 76,DMA1 Channel4 */
+ .word ENET_IRQHandler /* 77,Ethernet */
+ .word ENET_WKUP_IRQHandler /* 78,Ethernet Wakeup through EXTI line */
+ .word CAN1_TX_IRQHandler /* 79,CAN1 TX */
+ .word CAN1_RX0_IRQHandler /* 80,CAN1 RX0 */
+ .word CAN1_RX1_IRQHandler /* 81,CAN1 RX1 */
+ .word CAN1_EWMC_IRQHandler /* 82,CAN1 EWMC */
+ .word USBFS_IRQHandler /* 83,USBFS */
+
+/* dummy Exception Handlers */
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDGT_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak LVD_IRQHandler
+ .thumb_set LVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak RCU_CTC_IRQHandler
+ .thumb_set RCU_CTC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel0_IRQHandler
+ .thumb_set DMA0_Channel0_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel1_IRQHandler
+ .thumb_set DMA0_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel2_IRQHandler
+ .thumb_set DMA0_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel3_IRQHandler
+ .thumb_set DMA0_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel4_IRQHandler
+ .thumb_set DMA0_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel5_IRQHandler
+ .thumb_set DMA0_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel6_IRQHandler
+ .thumb_set DMA0_Channel6_IRQHandler,Default_Handler
+
+ .weak ADC0_1_IRQHandler
+ .thumb_set ADC0_1_IRQHandler,Default_Handler
+
+ .weak CAN0_TX_IRQHandler
+ .thumb_set CAN0_TX_IRQHandler,Default_Handler
+
+ .weak CAN0_RX0_IRQHandler
+ .thumb_set CAN0_RX0_IRQHandler,Default_Handler
+
+ .weak CAN0_RX1_IRQHandler
+ .thumb_set CAN0_RX1_IRQHandler,Default_Handler
+
+ .weak CAN0_EWMC_IRQHandler
+ .thumb_set CAN0_EWMC_IRQHandler,Default_Handler
+
+ .weak EXTI5_9_IRQHandler
+ .thumb_set EXTI5_9_IRQHandler,Default_Handler
+
+ .weak TIMER0_BRK_TIMER8_IRQHandler
+ .thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
+
+ .weak TIMER0_UP_TIMER9_IRQHandler
+ .thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
+
+ .weak TIMER0_TRG_CMT_TIMER10_IRQHandler
+ .thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
+
+ .weak TIMER0_Channel_IRQHandler
+ .thumb_set TIMER0_Channel_IRQHandler,Default_Handler
+
+ .weak TIMER1_IRQHandler
+ .thumb_set TIMER1_IRQHandler,Default_Handler
+
+ .weak TIMER2_IRQHandler
+ .thumb_set TIMER2_IRQHandler,Default_Handler
+
+ .weak TIMER3_IRQHandler
+ .thumb_set TIMER3_IRQHandler,Default_Handler
+
+ .weak I2C0_EV_IRQHandler
+ .thumb_set I2C0_EV_IRQHandler,Default_Handler
+
+ .weak I2C0_ER_IRQHandler
+ .thumb_set I2C0_ER_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI0_IRQHandler
+ .thumb_set SPI0_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART0_IRQHandler
+ .thumb_set USART0_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak EXTI10_15_IRQHandler
+ .thumb_set EXTI10_15_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USBFS_WKUP_IRQHandler
+ .thumb_set USBFS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIMER7_BRK_TIMER11_IRQHandler
+ .thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
+
+ .weak TIMER7_UP_TIMER12_IRQHandler
+ .thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
+
+ .weak TIMER7_TRG_CMT_TIMER13_IRQHandler
+ .thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
+
+ .weak TIMER7_Channel_IRQHandler
+ .thumb_set TIMER7_Channel_IRQHandler,Default_Handler
+
+ .weak EXMC_IRQHandler
+ .thumb_set EXMC_IRQHandler,Default_Handler
+
+ .weak TIMER4_IRQHandler
+ .thumb_set TIMER4_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak UART3_IRQHandler
+ .thumb_set UART3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak TIMER5_IRQHandler
+ .thumb_set TIMER5_IRQHandler,Default_Handler
+
+ .weak TIMER6_IRQHandler
+ .thumb_set TIMER6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel0_IRQHandler
+ .thumb_set DMA1_Channel0_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak ENET_IRQHandler
+ .thumb_set ENET_IRQHandler,Default_Handler
+
+ .weak ENET_WKUP_IRQHandler
+ .thumb_set ENET_WKUP_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_EWMC_IRQHandler
+ .thumb_set CAN1_EWMC_IRQHandler,Default_Handler
+
+ .weak USBFS_IRQHandler
+ .thumb_set USBFS_IRQHandler,Default_Handler
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.s b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.s
new file mode 100644
index 0000000000..f04c488aa3
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.s
@@ -0,0 +1,526 @@
+;/*!
+; \file startup_gd32f30x_cl.s
+; \brief start up file
+;
+; \version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
+;*/
+;
+;/*
+; Copyright (c) 2018, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+;are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this
+; list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+;OF SUCH DAMAGE.
+;*/
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; top of stack
+ DCD Reset_Handler ; Vector Number 1,Reset Handler
+
+ DCD NMI_Handler ; Vector Number 2,NMI Handler
+ DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
+ DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
+ DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
+ DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; Vector Number 11,SVCall Handler
+ DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; Vector Number 14,PendSV Handler
+ DCD SysTick_Handler ; Vector Number 15,SysTick Handler
+
+ ; External Interrupts
+ DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
+ DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
+ DCD RTC_IRQHandler ; 19:RTC through EXTI Line
+ DCD FMC_IRQHandler ; 20:FMC
+ DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
+ DCD EXTI0_IRQHandler ; 22:EXTI Line 0
+ DCD EXTI1_IRQHandler ; 23:EXTI Line 1
+ DCD EXTI2_IRQHandler ; 24:EXTI Line 2
+ DCD EXTI3_IRQHandler ; 25:EXTI Line 3
+ DCD EXTI4_IRQHandler ; 26:EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
+ DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
+ DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
+ DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
+ DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
+ DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
+ DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
+ DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
+ DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
+ DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
+ DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
+ DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
+ DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
+ DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; 44:TIMER1
+ DCD TIMER2_IRQHandler ; 45:TIMER2
+ DCD TIMER3_IRQHandler ; 46:TIMER3
+ DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
+ DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
+ DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
+ DCD SPI0_IRQHandler ; 51:SPI0
+ DCD SPI1_IRQHandler ; 52:SPI1
+ DCD USART0_IRQHandler ; 53:USART0
+ DCD USART1_IRQHandler ; 54:USART1
+ DCD USART2_IRQHandler ; 55:USART2
+ DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
+ DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
+ DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
+ DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
+ DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
+ DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
+ DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
+ DCD 0 ; 63:Reserved
+ DCD EXMC_IRQHandler ; 64:EXMC
+ DCD 0 ; 65:Reserved
+ DCD TIMER4_IRQHandler ; 66:TIMER4
+ DCD SPI2_IRQHandler ; 67:SPI2
+ DCD UART3_IRQHandler ; 68:UART3
+ DCD UART4_IRQHandler ; 69:UART4
+ DCD TIMER5_IRQHandler ; 70:TIMER5
+ DCD TIMER6_IRQHandler ; 71:TIMER6
+ DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
+ DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
+ DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
+ DCD ENET_IRQHandler ; 77:Ethernet
+ DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
+ DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
+ DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
+ DCD USBFS_IRQHandler ; 83:USBFS
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDGT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDGT_IRQHandler
+ B WWDGT_IRQHandler
+
+ PUBWEAK LVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_IRQHandler
+ B LVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK RCU_CTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCU_CTC_IRQHandler
+ B RCU_CTC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA0_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel0_IRQHandler
+ B DMA0_Channel0_IRQHandler
+
+ PUBWEAK DMA0_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel1_IRQHandler
+ B DMA0_Channel1_IRQHandler
+
+ PUBWEAK DMA0_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel2_IRQHandler
+ B DMA0_Channel2_IRQHandler
+
+ PUBWEAK DMA0_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel3_IRQHandler
+ B DMA0_Channel3_IRQHandler
+
+ PUBWEAK DMA0_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel4_IRQHandler
+ B DMA0_Channel4_IRQHandler
+
+ PUBWEAK DMA0_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel5_IRQHandler
+ B DMA0_Channel5_IRQHandler
+
+ PUBWEAK DMA0_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel6_IRQHandler
+ B DMA0_Channel6_IRQHandler
+
+ PUBWEAK ADC0_1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC0_1_IRQHandler
+ B ADC0_1_IRQHandler
+
+ PUBWEAK CAN0_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_TX_IRQHandler
+ B CAN0_TX_IRQHandler
+
+ PUBWEAK CAN0_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX0_IRQHandler
+ B CAN0_RX0_IRQHandler
+
+ PUBWEAK CAN0_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX1_IRQHandler
+ B CAN0_RX1_IRQHandler
+
+ PUBWEAK CAN0_EWMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_EWMC_IRQHandler
+ B CAN0_EWMC_IRQHandler
+
+ PUBWEAK EXTI5_9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_9_IRQHandler
+ B EXTI5_9_IRQHandler
+
+ PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_BRK_TIMER8_IRQHandler
+ B TIMER0_BRK_TIMER8_IRQHandler
+
+ PUBWEAK TIMER0_UP_TIMER9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_UP_TIMER9_IRQHandler
+ B TIMER0_UP_TIMER9_IRQHandler
+
+ PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_TRG_CMT_TIMER10_IRQHandler
+ B TIMER0_TRG_CMT_TIMER10_IRQHandler
+
+ PUBWEAK TIMER0_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_Channel_IRQHandler
+ B TIMER0_Channel_IRQHandler
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER1_IRQHandler
+ B TIMER1_IRQHandler
+
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER2_IRQHandler
+ B TIMER2_IRQHandler
+
+ PUBWEAK TIMER3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER3_IRQHandler
+ B TIMER3_IRQHandler
+
+ PUBWEAK I2C0_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_EV_IRQHandler
+ B I2C0_EV_IRQHandler
+
+ PUBWEAK I2C0_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_ER_IRQHandler
+ B I2C0_ER_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_IRQHandler
+ B SPI0_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_IRQHandler
+ B USART0_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK EXTI10_15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_15_IRQHandler
+ B EXTI10_15_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBFS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBFS_WKUP_IRQHandler
+ B USBFS_WKUP_IRQHandler
+
+ PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_BRK_TIMER11_IRQHandler
+ B TIMER7_BRK_TIMER11_IRQHandler
+
+ PUBWEAK TIMER7_UP_TIMER12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_UP_TIMER12_IRQHandler
+ B TIMER7_UP_TIMER12_IRQHandler
+
+ PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_TRG_CMT_TIMER13_IRQHandler
+ B TIMER7_TRG_CMT_TIMER13_IRQHandler
+
+ PUBWEAK TIMER7_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_Channel_IRQHandler
+ B TIMER7_Channel_IRQHandler
+
+ PUBWEAK EXMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXMC_IRQHandler
+ B EXMC_IRQHandler
+
+ PUBWEAK TIMER4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER4_IRQHandler
+ B TIMER4_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK TIMER5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER5_IRQHandler
+ B TIMER5_IRQHandler
+
+ PUBWEAK TIMER6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER6_IRQHandler
+ B TIMER6_IRQHandler
+
+ PUBWEAK DMA1_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel0_IRQHandler
+ B DMA1_Channel0_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK ENET_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ENET_WKUP_IRQHandler
+ B ENET_WKUP_IRQHandler
+
+ PUBWEAK CAN1_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+ B CAN1_TX_IRQHandler
+
+ PUBWEAK CAN1_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+ B CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_EWMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_EWMC_IRQHandler
+ B CAN1_EWMC_IRQHandler
+
+ PUBWEAK USBFS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBFS_IRQHandler
+ B USBFS_IRQHandler
+ END
\ No newline at end of file