From 0864aa86be672188e6f64f70ab2a454c5f4142f9 Mon Sep 17 00:00:00 2001 From: Marcelo Salazar Date: Tue, 28 Apr 2020 08:55:42 +0100 Subject: [PATCH] Remove NCS36510 target --- .../nanostack/mbed-mesh-api/mbed_lib.json | 3 - .../sal-stack-nanostack/mbed_lib.json | 3 - .../NanostackRfPhyNcs36510.cpp | 910 ------------------ .../TARGET_NCS36510/NanostackRfPhyNcs36510.h | 32 - features/netsocket/mbed_lib.json | 3 - targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c | 144 --- .../TARGET_NCS36510/PeripheralNames.h | 72 -- .../TARGET_NCS36510/PeripheralPins.c | 114 --- .../TARGET_NCS36510/PeripheralPins.h | 42 - .../TARGET_ONSEMI/TARGET_NCS36510/PinNames.h | 186 ---- .../TARGET_ONSEMI/TARGET_NCS36510/PortNames.h | 30 - .../TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h | 100 -- .../TARGET_NCS36510/adc_sar_map.h | 79 -- .../TARGET_ONSEMI/TARGET_NCS36510/aes_map.h | 105 -- .../TARGET_NCS36510/analogin_api.c | 205 ---- .../TARGET_NCS36510/architecture.h | 77 -- .../TARGET_NCS36510/assert_onsemi.h | 74 -- .../TARGET_NCS36510/char_driver.h | 85 -- targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h | 134 --- .../TARGET_ONSEMI/TARGET_NCS36510/clock_map.h | 151 --- .../TARGET_ONSEMI/TARGET_NCS36510/crossbar.h | 51 - .../TARGET_NCS36510/crossbar_map.h | 71 -- .../TARGET_ONSEMI/TARGET_NCS36510/device.h | 43 - .../TARGET_NCS36510/device/NCS36510.h | 86 -- .../device/TOOLCHAIN_ARM/NCS36510.sct | 26 - .../device/TOOLCHAIN_ARM/startup_NCS36510.S | 197 ---- .../device/TOOLCHAIN_GCC_ARM/NCS36510.ld | 186 ---- .../TOOLCHAIN_GCC_ARM/startup_NCS36510.S | 209 ---- .../device/TOOLCHAIN_IAR/NCS36510.icf | 85 -- .../device/TOOLCHAIN_IAR/startup_NCS36510.S | 310 ------ .../TARGET_NCS36510/device/cmsis.h | 29 - .../TARGET_NCS36510/device/cmsis_nvic.h | 33 - .../TARGET_NCS36510/device/system_NCS36510.c | 67 -- .../TARGET_NCS36510/device/system_NCS36510.h | 62 -- .../TARGET_ONSEMI/TARGET_NCS36510/dma_map.h | 94 -- targets/TARGET_ONSEMI/TARGET_NCS36510/error.h | 38 - .../TARGET_NCS36510/exceptions.c | 156 --- targets/TARGET_ONSEMI/TARGET_NCS36510/fib.h | 49 - .../TARGET_ONSEMI/TARGET_NCS36510/flash_map.h | 84 -- .../TARGET_NCS36510/fncs36510_sleep.h | 63 -- targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h | 86 -- .../TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c | 201 ---- .../TARGET_NCS36510/gpio_irq_api.c | 246 ----- .../TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h | 65 -- targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h | 163 ---- .../TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c | 201 ---- .../TARGET_NCS36510/i2c_ipc7208_map.h | 87 -- .../TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h | 389 -------- .../TARGET_ONSEMI/TARGET_NCS36510/macros.h | 41 - .../TARGET_NCS36510/memory_map.h | 290 ------ targets/TARGET_ONSEMI/TARGET_NCS36510/mib.h | 140 --- .../TARGET_NCS36510/ncs36510Init.c | 312 ------ .../TARGET_NCS36510/ncs36510Init.h | 54 -- .../TARGET_NCS36510/ncs36510_i2c.c | 231 ----- .../TARGET_NCS36510/ncs36510_lp_ticker_api.c | 82 -- .../TARGET_NCS36510/ncs36510_spi.c | 171 ---- .../TARGET_NCS36510/ncs36510_trng.h | 42 - .../TARGET_NCS36510/ncs36510_trng_api.c | 113 --- .../TARGET_NCS36510/ncs36510_us_ticker_api.c | 210 ---- .../TARGET_ONSEMI/TARGET_NCS36510/objects.h | 204 ---- targets/TARGET_ONSEMI/TARGET_NCS36510/pad.h | 86 -- .../TARGET_ONSEMI/TARGET_NCS36510/pad_map.h | 239 ----- .../TARGET_ONSEMI/TARGET_NCS36510/pinmap.c | 83 -- .../TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h | 95 -- .../TARGET_ONSEMI/TARGET_NCS36510/port_api.c | 162 ---- .../TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h | 63 -- .../TARGET_NCS36510/pwmout_api.c | 214 ---- .../TARGET_NCS36510/random_map.h | 103 -- .../TARGET_ONSEMI/TARGET_NCS36510/reset_map.h | 69 -- targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c | 168 ---- targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h | 69 -- .../TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h | 124 --- targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c | 307 ------ targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h | 156 --- .../TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c | 89 -- .../TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h | 87 -- .../TARGET_NCS36510/serial_api.c | 418 -------- targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c | 120 --- .../TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c | 51 - targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h | 85 -- .../TARGET_ONSEMI/TARGET_NCS36510/spi_api.c | 270 ------ .../TARGET_NCS36510/spi_ipc7207_map.h | 93 -- .../TARGET_ONSEMI/TARGET_NCS36510/swversion.c | 55 -- targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h | 64 -- .../TARGET_NCS36510/target_config.h | 33 - .../TARGET_ONSEMI/TARGET_NCS36510/test_map.h | 125 --- .../TARGET_ONSEMI/TARGET_NCS36510/ticker.h | 85 -- .../TARGET_ONSEMI/TARGET_NCS36510/timer_map.h | 72 -- .../TARGET_NCS36510/timer_ncs36510.h | 122 --- .../TARGET_ONSEMI/TARGET_NCS36510/trim_map.h | 138 --- targets/TARGET_ONSEMI/TARGET_NCS36510/types.h | 51 - targets/TARGET_ONSEMI/TARGET_NCS36510/uart.h | 67 -- .../TARGET_NCS36510/uart_16c550.h | 128 --- .../TARGET_NCS36510/uart_16c550_map.h | 171 ---- .../TARGET_NCS36510/watchdog_api.c | 116 --- .../TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h | 66 -- targets/TARGET_ONSEMI/mbed_rtx.h | 28 - targets/targets.json | 76 -- tools/export/codeblocks/__init__.py | 1 - tools/export/iar/iar_definitions.json | 3 - tools/export/uvision/__init__.py | 1 - tools/targets/NCS.py | 241 ----- tools/targets/__init__.py | 8 - 103 files changed, 12618 deletions(-) delete mode 100644 features/nanostack/targets/TARGET_NCS36510/NanostackRfPhyNcs36510.cpp delete mode 100644 features/nanostack/targets/TARGET_NCS36510/NanostackRfPhyNcs36510.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/PortNames.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/architecture.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/NCS36510.sct delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.S delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.S delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.S delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/error.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/fib.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/fncs36510_sleep.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/macros.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/mib.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_trng.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_trng_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/pad.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/pinmap.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/port_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/random_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/reset_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/target_config.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/test_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/ticker.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/timer_ncs36510.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/types.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/uart.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/watchdog_api.c delete mode 100644 targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h delete mode 100644 targets/TARGET_ONSEMI/mbed_rtx.h delete mode 100644 tools/targets/NCS.py diff --git a/features/nanostack/mbed-mesh-api/mbed_lib.json b/features/nanostack/mbed-mesh-api/mbed_lib.json index 165d57a75f..5a1ca84f10 100644 --- a/features/nanostack/mbed-mesh-api/mbed_lib.json +++ b/features/nanostack/mbed-mesh-api/mbed_lib.json @@ -193,9 +193,6 @@ } }, "target_overrides": { - "NCS36510": { - "mbed-mesh-api.heap-size": 14000 - }, "KW41Z": { "mbed-mesh-api.heap-size": 14000 } diff --git a/features/nanostack/sal-stack-nanostack/mbed_lib.json b/features/nanostack/sal-stack-nanostack/mbed_lib.json index 1ea4926c58..1fddbd2cba 100644 --- a/features/nanostack/sal-stack-nanostack/mbed_lib.json +++ b/features/nanostack/sal-stack-nanostack/mbed_lib.json @@ -9,9 +9,6 @@ }, "macros": ["NS_USE_EXTERNAL_MBED_TLS"], "target_overrides": { - "NCS36510": { - "nanostack.configuration": "lowpan_router" - }, "TB_SENSE_12": { "nanostack.configuration": "lowpan_router" }, diff --git a/features/nanostack/targets/TARGET_NCS36510/NanostackRfPhyNcs36510.cpp b/features/nanostack/targets/TARGET_NCS36510/NanostackRfPhyNcs36510.cpp deleted file mode 100644 index 061f11ba04..0000000000 --- a/features/nanostack/targets/TARGET_NCS36510/NanostackRfPhyNcs36510.cpp +++ /dev/null @@ -1,910 +0,0 @@ -/* -* Copyright (c) 2016-2016 ARM Limited. All rights reserved. -* SPDX-License-Identifier: Apache-2.0 -* Licensed under the Apache License, Version 2.0 (the License); you may -* not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an AS IS BASIS, WITHOUT -* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#include "ns_types.h" -#include -#include "common_functions.h" -#include "randLIB.h" -#include "platform/arm_hal_interrupt.h" -#include "platform/arm_hal_phy.h" -#include "NanostackRfPhyNcs36510.h" - -extern "C" { -#include "TARGET_NCS36510/memory_map.h" -#include "TARGET_NCS36510/clock.h" -#include "TARGET_NCS36510/ticker.h" -#include "TARGET_NCS36510/rfAna.h" -} - -#define RF_THREAD_STACK_SIZE 1024 - -#define SIGNAL_COUNT_RADIO 1 - -#include "Thread.h" -#include "ThisThread.h" -#include "mbed_error.h" -using namespace rtos; -static void rf_thread_loop(); -Thread rf_thread(osPriorityRealtime, RF_THREAD_STACK_SIZE); - -#define PHY_MTU_SIZE 127 -#define CRC_LENGTH 0 -#define PHY_HEADER_LENGTH 0 - -/** - * MAC status code bit definition - */ -#define MAC_STATUS_SUCCESS (0x0) /**< Success */ -#define MAC_STATUS_TIMEOUT (0x1) /**< Time out */ -#define MAC_STATUS_BUSY (0x2) /**< Channel Busy */ -#define MAC_STATUS_CRCFAIL (0x3) /**< CRC Failed */ -#define MAC_STATUS_NOACK (0x5) /**< No ACK */ -#define MAC_STATUS_UNLOCK (0x6) /**< PLL unlocked */ -#define MAC_STATUS_BADSTART (0x7) /**< Bad Start */ -#define MAC_STATUS_RXACK_PENDING (0x8) /**< ACK frame was received with the Pending bit set */ -#define MAC_STATUS_TXACK_PENDING (0x9) /**< ACK frame was transmitted with the Pending bit set */ -#define MAC_STATUS_FAIL_FILTER (0xA) /**< One or more frame filtering tests has failed */ -#define MAC_STATUS_PANID_CONFLICT (0xB) /**< A PANID conflict has been detected */ -#define MAC_STATUS_NOTCOMPLETE (0xF) /**< Not complete */ - -/** - * MAC sequence modes -*/ -#define MAC_SEQUENCE_NOP (0x0) /**< NOP */ -#define MAC_SEQUENCE_RX (0x3) /**< RX */ -#define MAC_SEQUENCE_TX (0x4) /**< TX */ -#define MAC_SEQUENCE_ED (0x5) /**< ED */ -#define MAC_SEQUENCE_CCA (0x6) /**< CCA */ - -/** - * MAC Interrupt enable / disable -*/ -#define MAC_IRQ_NONE (0x0) /**< No IRQ */ -#define MAC_IRQ_COMPLETE (0x1) /**< Event-complete IRQ */ -#define MAC_IRQ_EVENT_STARTED (0x2) /**< Event-started IRQ */ -#define MAC_IRQ_DATA (0x4) /**< Data-arrived IRQ */ -#define MAC_IRQ_FRAME_STARTED (0x8) /**< Frame-started IRQ */ -#define MAC_IRQ_PACKET_FAIL (0x10) /**< Failed-packet IRQ */ -#define MAC_IRQ_FRAME_MATCH (0x20) /**< Frame-match IRQ (indicating matching process is done) */ -#define MAC_IRQ_ALL (0x3F) /**< All IRQs */ - -#define MAC_RSSI_TO_ED 0 -#define MAC_RSSI_TO_LQI 1 - -#define MAC_RF_TRX_OFF 0 -#define MAC_RF_RX_ON 1 -#define MAC_RF_TX_ON 2 -#define MAC_RF_ED_SCAN 3 - -static int8_t rf_radio_driver_id = -1; - -static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel); -static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol); -static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr); -static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr); - -static void rf_mac_hw_init(void); -static void rf_mac_timers_disable_trig_event(void); -static void rf_mac_reset(void); -static void rf_mac_rx_enable(void); -static void rf_mac_ed_state_enable(void); -static uint8_t rf_mac_convert_rssi(uint8_t scale); -static int8_t rf_mac_get_rssi(void); -static void rf_mac_set_rx_on_state(bool enable); -static void rf_mac_write(uint8_t *data_ptr, uint8_t length); - -static void rf_mac_set_pending(uint8_t status); - -static void rf_mac_set_shortAddress(uint8_t* valueAddress); -static void rf_mac_set_panId(uint8_t* valueAddress); -static void rf_mac_set_mac64(const uint8_t* valueAddress); - -static void rf_mac_get_mac64(uint8_t* valueAddress); - -static int8_t set_channel(uint8_t channel); -static void handle_IRQ_events(void); - -static uint8_t MAC64_addr_default[8] = {1, 2, 3, 4, 5, 6, 7, 8}; -static uint8_t MAC64_addr[8]; - -static uint8_t rf_mac_state = MAC_RF_TRX_OFF; -static bool rf_ack_pending_state = false; -static bool rf_mac_ack_requsted = false; -static uint8_t rf_mac_handle; -volatile uint8_t rf_ed_value = 0; - -static NanostackRfPhyNcs36510 *rf = NULL; - -#define MAC_PACKET_SIZE 127 //MAX MAC payload is 127 bytes -static uint8_t PHYPAYLOAD[MAC_PACKET_SIZE]; - -//TODO: verify these values -const phy_rf_channel_configuration_s phy_2_4ghz = {2405000000U, 5000000U, 250000U, 16U, M_OQPSK}; - -const phy_device_channel_page_s phy_channel_pages[] = { - {CHANNEL_PAGE_0, &phy_2_4ghz}, - {CHANNEL_PAGE_0, NULL} -}; - -static phy_device_driver_s device_driver = { - PHY_LINK_15_4_2_4GHZ_TYPE, - PHY_LAYER_PAYLOAD_DATA_FLOW, - MAC64_addr, - PHY_MTU_SIZE, - (char*)"ON Semi ncs36510", - CRC_LENGTH, - PHY_HEADER_LENGTH, - &rf_interface_state_control, - &rf_start_cca, - &rf_address_write, - &rf_extension, - phy_channel_pages, - NULL, - NULL, - NULL, - NULL -}; - -static void rf_thread_loop() -{ - for (;;) { - uint32_t flags = ThisThread::flags_wait_any(0x7FFFFFFF); - - platform_enter_critical(); - if (flags & SIGNAL_COUNT_RADIO) { - handle_IRQ_events(); - } - platform_exit_critical(); - NVIC_ClearPendingIRQ(MacHw_IRQn); - NVIC_EnableIRQ(MacHw_IRQn); - } -} - -static int8_t rf_device_register(void) -{ - if( rf_radio_driver_id < 0 ) { - - rf_mac_hw_init(); - /** - * Read factory stored Mac address to RAM - */ - common_write_32_bit(MACHWREG->LONG_ADDRESS_HIGH, MAC64_addr); - common_write_32_bit(MACHWREG->LONG_ADDRESS_LOW, MAC64_addr + 4); - rf_radio_driver_id = arm_net_phy_register(&device_driver); - } - - return rf_radio_driver_id; -} - -static void rf_device_unregister(void) -{ - arm_net_phy_unregister(rf_radio_driver_id); -} - -void rf_read_mac_address(uint8_t *address_ptr) -{ - platform_enter_critical(); - rf_mac_get_mac64(address_ptr); - platform_exit_critical(); -} - -int8_t rf_read_random(void) -{ - //TODO: Read random from randomizer - return 1; -} - -void rf_set_mac_address(const uint8_t *ptr) -{ - platform_enter_critical(); - rf_mac_set_mac64(ptr); - platform_exit_critical(); -} - -static void rf_mac_set_pending(uint8_t status) { - - if (status) { - MACHWREG->OPTIONS.BITS.TFPO = 0; - MACHWREG->OPTIONS.BITS.TFP = 1; - rf_ack_pending_state = true; - } else { - rf_ack_pending_state = false; - MACHWREG->OPTIONS.BITS.TFPO = 0; - MACHWREG->OPTIONS.BITS.TFP = 0; - } -} - -static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel) -{ - platform_enter_critical(); - switch(new_state){ - case PHY_INTERFACE_RESET: { /**< Reset PHY driver and set to idle. */ - rf_mac_set_rx_on_state(false); - break; - } - case PHY_INTERFACE_DOWN: { /**< Disable PHY interface driver (RF radio disable). */ - rf_mac_set_rx_on_state(false); - break; - } - case PHY_INTERFACE_UP: { /**< Enable PHY interface driver (RF radio receiver ON). */ - set_channel(rf_channel); - rf_mac_set_rx_on_state(true); - - break; - } - case PHY_INTERFACE_RX_ENERGY_STATE: { /**< Enable wirless interface ED scan mode. */ - rf_ed_value = 0; - set_channel(rf_channel); - rf_mac_set_rx_on_state(false); - rf_mac_ed_state_enable(); - break; - } - case PHY_INTERFACE_SNIFFER_STATE: { - set_channel(rf_channel); - rf_mac_set_rx_on_state(true); - break; - } - } - platform_exit_critical(); - return 0; -} - -static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol) -{ - platform_enter_critical(); - (void)data_protocol; - rf_mac_handle = tx_handle; - rf_mac_write(data_ptr, data_length); - platform_exit_critical(); - return 0; -} - -static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr) -{ - int ret_value = 0; - platform_enter_critical(); - switch (address_type) { - case PHY_MAC_64BIT: /**< RF/PLC link layer address. */ - rf_mac_set_mac64(address_ptr); - break; - case PHY_MAC_16BIT: /**< RF interface short address. */ - rf_mac_set_shortAddress(address_ptr); - break; - case PHY_MAC_PANID: /**< RF interface 16-Bit PAN-ID. */ - rf_mac_set_panId(address_ptr); - break; - default: - ret_value = -1; - } - platform_exit_critical(); - - return ret_value; -} - -static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr) -{ - int ret_value = 0; - platform_enter_critical(); - switch (extension_type) { - case PHY_EXTENSION_CTRL_PENDING_BIT: /**< Control MAC pending bit for indirect data. */ - rf_mac_set_pending(*data_ptr); - break; - case PHY_EXTENSION_READ_LAST_ACK_PENDING_STATUS: /**< Read status if the last ACK is still pending. */ - *data_ptr = rf_ack_pending_state; - break; - case PHY_EXTENSION_SET_CHANNEL: /**< Net library channel set. */ - return set_channel(*data_ptr); - - case PHY_EXTENSION_READ_CHANNEL_ENERGY: /**< RF interface ED scan energy read. */ - *data_ptr = rf_ed_value; - break; - - case PHY_EXTENSION_READ_LINK_STATUS: /**< Net library could read link status. */ - case PHY_EXTENSION_CONVERT_SIGNAL_INFO: /**< Convert signal info. */ - default: - ret_value = -1; - } - platform_exit_critical(); - - return ret_value; -} - -static int8_t set_channel(uint8_t channel) -{ - if( channel > 10 && channel < 27 ){ - fRfAnaIoctl(SET_RF_CHANNEL, &channel); - return 0; - } - return -1; -} - - -/** - * SET MAC 16 address to Register - */ -static void rf_mac_set_shortAddress(uint8_t* valueAddress) { - MACHWREG->SHORT_ADDRESS = common_read_16_bit(valueAddress); -} - -/** - * SET PAN-ID to Register - */ -static void rf_mac_set_panId(uint8_t* valueAddress) { - MACHWREG->PANID = common_read_16_bit(valueAddress); -} - -/** - * SET MAC64 address to register - */ -static void rf_mac_set_mac64(const uint8_t* valueAddress) { - MACHWREG->LONG_ADDRESS_HIGH = common_read_32_bit(valueAddress); - valueAddress += 4; - MACHWREG->LONG_ADDRESS_LOW = common_read_32_bit(valueAddress); -} - -static void rf_mac_get_mac64(uint8_t* valueAddress) { - valueAddress = common_write_32_bit(MACHWREG->LONG_ADDRESS_HIGH, valueAddress); - common_write_32_bit(MACHWREG->LONG_ADDRESS_LOW, valueAddress); -} - -static void rf_mac_timers_disable_trig_event(void) { - MACHWREG->TIMER_DISABLE.BITS.START = true; - MACHWREG->TIMER_DISABLE.BITS.STOP = true; - MACHWREG->SEQ_OPTIONS.BITS.NOW = true; -} - -/** - * Call this only One time - */ -static void rf_mac_hw_init(void) { - uint32_t periphClockfrequency; - uint8_t lutIndex; - volatile uint8_t *pMatchReg = MACMATCHREG; - - /** Initialize rf peripheral */ - fRfAnaInit(); - - /** Enable mac clock */ - CLOCK_ENABLE(CLOCK_MACHW); - - /** Disable and clear IRQs */ - MACHWREG->MASK_IRQ.WORD = MAC_IRQ_NONE; - MACHWREG->CLEAR_IRQ.WORD = MAC_IRQ_ALL; - NVIC_ClearPendingIRQ(MacHw_IRQn); - - /** Set sequence options */ - MACHWREG->SEQ_OPTIONS.BITS.MODE = 0x1; - MACHWREG->SEQ_OPTIONS.BITS.NOACK = false; - MACHWREG->SEQ_OPTIONS.BITS.NOW = true; - MACHWREG->SEQ_OPTIONS.BITS.PRM = false; - - MACHWREG->SEQ_OPTIONS.BITS.ACK_ENABLE = false; - MACHWREG->SEQ_OPTIONS.BITS.RES_ENABLE = false; - - /** Set clocks */ - periphClockfrequency = fClockGetPeriphClockfrequency(); - MACHWREG->DIVIDER.BITS.BIT_CLOCK_DIVIDER = (periphClockfrequency / 250000) - 1; - MACHWREG->DIVIDER.BITS.SYSTEM_CLOCK_DIVIDER = (periphClockfrequency / 1000000) - 1; - MACHWREG->DIVIDER.BITS.CHIP_CLOCK_DIVIDER = (periphClockfrequency / 2000000) - 1; - - /** Set miscellaneous */ - - /** This value should be tuned tuned to hit tx sw ack window (192us-204us) */ - MACHWREG->RX_TX_WARMPUPS.BITS.TRANSMIT_WARMPUP = 0x16; - - /** This value is selected to allocate 1 bit margin between tr sw ack and tx sw ack */ - MACHWREG->RX_TX_WARMPUPS.BITS.RECEIVE_WARMPUP = 0x15; - - MACHWREG->TXCCA = 0x30; - MACHWREG->CCA.BITS.CCA_LENGTH = 0x43; - MACHWREG->CCA.BITS.CCA_DELAY = 0x26; - MACHWREG->TX_ACK_DELAY = 0x21; - MACHWREG->ACK_STOP.BITS.RXACK_END = 0xA8; - MACHWREG->SLOT_OFFSET.WORD = 0x00070007; - MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = 0x6; - MACHWREG->TX_FLUSH = 0x00000008; /** Transmit flush duration (8 x 4us = 32 us) */ - - /** Set AGC */ - MACHWREG->AGC_CONTROL.WORD = 0x00000007; // AGC enabled / AGC freeze enabled / Preamble detection mode - - /** It is unclear from design specification if a 16MHz is mandatory for AGC operations or only to build - * settle and measurements delays */ - if (periphClockfrequency == CPU_CLOCK_ROOT_HZ) { - /** AGC time unit = T(PCLK) x 2 = 16MHz period */ - MACHWREG->AGC_SETTINGS.BITS.DIVIDER = 1; - /** settle delay = (value + 1) * AGC time unit = 500ns targeted */ - MACHWREG->AGC_SETTINGS.BITS.SETTLE_DELAY = 7; - /** measurement delay = (value + 1) * AGC time unit = 1500ns targeted */ - MACHWREG->AGC_SETTINGS.BITS.MEASURE_DELAY = 0x17; - } else { - /** AGC time unit is T(PCLK) */ - MACHWREG->AGC_SETTINGS.BITS.DIVIDER = 0; - /** settle delay = (value + 1) * AGC time unit = 500ns targeted */ - MACHWREG->AGC_SETTINGS.BITS.SETTLE_DELAY = (16 / CPU_CLOCK_DIV) - 1; - /** measurement delay = (value + 1) * AGC time unit = 1500ns targeted */ - MACHWREG->AGC_SETTINGS.BITS.MEASURE_DELAY = (48 / CPU_CLOCK_DIV) - 1; - } - - /** AGC high threshold: 3dB below the clipping level */ - MACHWREG->AGC_SETTINGS.BITS.HIGH_THRESHOLD = 1; - /** AGC low threshold: 9dB below the high threshold */ - MACHWREG->AGC_SETTINGS.BITS.LOW_THRESHOLD = 0; - - /** Set Demodulator */ - DMDREG->DMD_CONTROL0.WORD = 0x7FFF0004; - MACHWREG->SHORT_ADDRESS = 0x0000ffff; - MACHWREG->PANID = 0x0000ffff; - - /** Reset macHw peripheral */ - rf_mac_reset(); - - /** Initialise LUT RAM */ - for (lutIndex=0;lutIndex<96;lutIndex++) { - *(pMatchReg + lutIndex) = 0xFF; - } - osStatus status = rf_thread.start(mbed::callback(rf_thread_loop)); - MBED_ASSERT(status == osOK); - - /** Clear and enable MAC IRQ at task level, when scheduler is on. */ - NVIC_ClearPendingIRQ(MacHw_IRQn); - NVIC_EnableIRQ(MacHw_IRQn); -} - -static void rf_mac_set_rx_on_state(bool enable) { - /** Abort ongoing sequence */ - rf_mac_reset(); - /** Start rx if requested */ - if (enable) { - /** Set requested filtering */ - MACHWREG->SEQ_OPTIONS.BITS.BEA_ENABLE = true; - MACHWREG->SEQ_OPTIONS.BITS.DATA_ENABLE = true; - MACHWREG->SEQ_OPTIONS.BITS.CMD_ENABLE = true; - /** Start receiver */ - rf_mac_rx_enable(); - } -} - -static void rf_mac_write(uint8_t *data_ptr, uint8_t length) { - uint8_t i; - volatile uint8_t *txRam = MACTXREG; - - /* This is not make sense but... */ - rf_mac_reset(); - - /* Set tx state */ - rf_mac_state = MAC_RF_TX_ON; - - if (*data_ptr & 0x20) { - MACHWREG->SEQ_OPTIONS.BITS.ACK_ENABLE = true; - } else { - MACHWREG->SEQ_OPTIONS.BITS.ACK_ENABLE = false; - } - rf_mac_ack_requsted = MACHWREG->SEQ_OPTIONS.BITS.ACK_ENABLE; - - /* Set data length */ - MACHWREG->TX_LENGTH.BITS.TXLENGTH = length + 2; - - *txRam++ = *data_ptr++; - *txRam++ = *data_ptr++; - *txRam++ = *data_ptr; - //RR: Retransmission for Data request should have same DSN - MACHWREG->TX_SEQ_NUMBER = *data_ptr++; - for (i = 3; i < length; i++) { - *txRam++ = *data_ptr++; - } - - MACHWREG->SEQ_OPTIONS.BITS.PRM = 0; - - MACHWREG->SEQ_OPTIONS.BITS.NOACK = false; - - rf_mac_state = MAC_RF_TX_ON; - - /* Start CCA immediately */ - rf_mac_timers_disable_trig_event(); - - while (MACHWREG->TIMER != 0x0) MACHWREG->TIMER = 0x0; // HW ISSUE: field is not set immediately - - /* Enable tx irq, reset protocol timer and start tx sequence */ - MACHWREG->MASK_IRQ.WORD = MAC_IRQ_COMPLETE; - MACHWREG->SEQUENCER = MAC_SEQUENCE_TX; - -} - - -static void rf_mac_ed_state_enable(void) { - rf_mac_state = MAC_RF_ED_SCAN; - /** Enable Energy scan state and event complete interrupt */ - MACHWREG->CLEAR_IRQ.WORD = MAC_IRQ_COMPLETE; - MACHWREG->MASK_IRQ.WORD = MAC_IRQ_COMPLETE; - MACHWREG->SEQUENCER = MAC_SEQUENCE_ED; -} - - -static void rf_mac_rx_enable(void) { - rf_mac_state = MAC_RF_RX_ON; - - /** Enable rx irqs, reset protocol timer and start rx sequence */ - MACHWREG->MASK_IRQ.WORD = MAC_IRQ_COMPLETE | MAC_IRQ_FRAME_MATCH | MAC_IRQ_DATA; - while (MACHWREG->TIMER != 0x0) MACHWREG->TIMER = 0x0; // HW ISSUE: field is not set immediately - MACHWREG->SEQUENCER = MAC_SEQUENCE_RX; - return; -} - - -static void rf_mac_reset(void) { - uint32_t macHwDivider; - - /** Recommended abort sequence (with synchronous reset) */ - - /** 1. Set clock divider to minimum (for single clock response) */ - macHwDivider = MACHWREG->DIVIDER.WORD; - /** (to cope with protocol timer and ed REVB silicon issues it is required - * to set protocol timer to 1 and not to 0 as suggested in macHw specification) */ - /* PK !!!MAC_REVD RevB -> RevD change list Item 25: protocol timer */ - MACHWREG->DIVIDER.WORD = 1; - - /** 2. Disable interrupts */ - MACHWREG->MASK_IRQ.WORD = MAC_IRQ_NONE; - - /** 3. Clear interrupts */ - MACHWREG->CLEAR_IRQ.WORD = MAC_IRQ_ALL; - - NVIC_ClearPendingIRQ(MacHw_IRQn); - - /** 4. Clear previous sequence type (write no-op sequence) */ - MACHWREG->SEQUENCER = MAC_SEQUENCE_NOP; - - /** 5. Move all MAC state machines to idle state (on, with synchronous reset) */ - MACHWREG->CONTROL.WORD = 0x00000003; - - /** 6. Release reset */ - MACHWREG->CONTROL.WORD = 0x00000002; - - /** 7. Disable start, stop timers */ - rf_mac_timers_disable_trig_event(); - - /** 8. Return clock dividers to original value */ - MACHWREG->DIVIDER.WORD = macHwDivider; - - MACHWREG->SEQ_OPTIONS.BITS.BEA_ENABLE = False; - MACHWREG->SEQ_OPTIONS.BITS.DATA_ENABLE = False; - MACHWREG->SEQ_OPTIONS.BITS.CMD_ENABLE = False; - - /** Set MAC_HW state */ - rf_mac_state = MAC_RF_TRX_OFF; -} - -static uint8_t rf_mac_convert_rssi(uint8_t scale) { - /* RSSI Value: The value is captured at the end of packet reception or at the end of ED/CCA - * measurements and is interpreted in dBm as follows: - * 1xxxxxxx: not used - * 01111111: 0 dBm (or above) - * 01111110: -1 dBm - * 01111101: -2 dBm - * - - * 00000010: -125 dBm - * 00000001: -126 dBm - * 00000000: -127 dBm (or below) - */ - - /* check rssi is well in spec range */ - //ASSERT ((DMDREG->DMD_STATUS.BITS.RSSI_VALUE & 0x80) != 0x80); - if (DMDREG->DMD_STATUS.BITS.RSSI_VALUE & 0x80) { - return 0; - } - - /* convert rssi in sign char: translate 01111111 into 0 and following alike, make negative */ - signed char rssi_value = -1 * (DMDREG->DMD_STATUS.BITS.RSSI_VALUE ^ 0x7F); - - if (scale == MAC_RSSI_TO_ED ) { - /** - * For ED (IEEE 6.9.7) "The ED result shall be reported to the MLME as an 8 bit integer - * ranging from 0x00 to 0xff. The minimum ED value (zero) shall indicate received power less than 10 dB - * above the specified receiver sensitivity (see 6.5.3.3 and 6.6.3.4), and the range of received power spanned by - * the ED values shall be at least 40 dB. Within this range, the mapping from the received power in decibels to - * ED value shall be linear with an accuracy of � 6 dB." - * (-85dBm receiver sensitivity will be targeted => zero ED value is associated to -75dBm) - * (span will have 51dBm range from 0x0=-75dBm to 0xff=-24dBm) - */ - - /* Clip maximal and minimal rssi value reported by ED */ - if (rssi_value < -75) rssi_value = -75; - if (rssi_value > -24) rssi_value = -24; - - /* scale the span -75dBm --> -24dBm to 0x00 --> 0xFF - * Attention: This scaling implies that granularity of the result is changing from 1dBm per unit to 1/5 dBm per unit - * 0xFF: -24 dBm (or above) - * 0xFE - 0xFB: (impossible code) - * 0xFA: -25 dBm - * 0xF9 - 0xF6: (impossible code) - * 0xF5: -26 dBm - * ... - * 0x05: -74 dBm - * 0x01 - 0x04: (impossible code) - * 0x00: -75 dBm (or below) - */ - return (rssi_value + 75) * 5; - } else { - - /** - * For LQI: (IEEE 6.9.7) "The LQI measurement shall be performed for each received packet, and the result shall be reported to the - * MAC sublayer using PD-DATA.indication (see 6.2.1.3) as an integer ranging from 0x00 to 0xff. The - * minimum and maximum LQI values (0x00 and 0xff) should be associated with the lowest and highest - * quality compliant signals detectable by the receiver, and LQI values in between should be uniformly - * distributed between these two limits. At least eight unique values of LQI shall be used." - * (-85dBm sensitivity will be targeted => zero LQI value will be associated to -85dBm) - * (span will have 64dBm range from 0x0=-85dBm to 0xff=-21dBm) - */ - - /* Clip maximal and minimal rssi value reported by LQI */ - if (rssi_value < -85) rssi_value = -85; - if (rssi_value > -21) rssi_value = -21; - - /* scale the span -85dBm --> -21,25dBm to 0x00 --> 0xFF - * Attention: This scaling implies that granularity of the result is changing from 1dBm per unit to 1/4 dBm per unit - * 0xFF: -21,25 dBm (or above) - * 0xFE: (impossible code) - * 0xFD: (impossible code) - * 0xFC: -22 dBm - * 0xFB: (impossible code) - * 0xFA: (impossible code) - * 0xF9: (impossible code) - * 0xF8: -23 dBm - * ... - * 0x05: (impossible code) - * 0x04: - 84dBm - * 0x03: (impossible code) - * 0x02: (impossible code) - * 0x01: (impossible code) - * 0x00: - 85dBm - */ - if (rssi_value == -21) - return ((rssi_value + 85) * 4) - 1; - else - return (rssi_value + 85) * 4; - } -} - -static int8_t rf_mac_get_rssi(void) { - int8_t rssi_value = -1 * (DMDREG->DMD_STATUS.BITS.RSSI_VALUE ^ 0x7F); - return rssi_value; -} - -static void rf_rx_ed_scan_interrupt() { - MACHWREG->CLEAR_IRQ.WORD = MAC_IRQ_COMPLETE; - if (MACHWREG->STATUS.BITS.CODE == MAC_STATUS_SUCCESS) { - uint8_t ed = rf_mac_convert_rssi(MAC_RSSI_TO_ED); - if (ed) { - if (ed > rf_ed_value) { - rf_ed_value = ed; - } - } - } - - MACHWREG->MASK_IRQ.WORD = MAC_IRQ_COMPLETE; - MACHWREG->SEQUENCER = MAC_SEQUENCE_ED; -} - -static void rf_rx_interrupt() { - // Frame match is used for association and data frames - uint8_t seqSts = MACHWREG->STATUS.BITS.CODE; - - if (MACHWREG->IRQ_STATUS.BITS.FM) { - if (!rf_ack_pending_state) { - MACHWREG->OPTIONS.BITS.TFP = 0; - MACHWREG->OPTIONS.BITS.TFPO = 1; - } else { - MACHWREG->OPTIONS.BITS.TFP = 1; - MACHWREG->OPTIONS.BITS.TFPO = 1; - } - - MACHWREG->CLEAR_IRQ.WORD = MAC_IRQ_FRAME_MATCH; - return; - } - - /** RR: Process the event complete IRQ */ - if (MACHWREG->IRQ_STATUS.BITS.EC || MACHWREG->IRQ_STATUS.BITS.DATA) { - /** Clear the event */ - if (MACHWREG->IRQ_STATUS.BITS.EC) { - MACHWREG->CLEAR_IRQ.WORD = MAC_IRQ_COMPLETE; - } - - if (MACHWREG->IRQ_STATUS.BITS.DATA) { - MACHWREG->CLEAR_IRQ.WORD = MAC_IRQ_DATA; - } - - /** Build frame (containing received frame or timeout) */ - - volatile uint8_t *rxRam = MACRXREG; - uint8_t length; - int8_t rssi; - uint8_t lqi; - - /** Return directly in case of timeout */ - if (seqSts == MAC_STATUS_TIMEOUT) { - /* Initialize frame status */ - return; - } - - length = *rxRam++; - if (length < 5){ - rf_mac_rx_enable(); - return; - } - length -= 2; //Cut CRC OUT - - /* Initialize frame status */ - for (uint8_t i=0; i < length; i++) { - PHYPAYLOAD[i] = *rxRam++; - } - - lqi = rf_mac_convert_rssi(MAC_RSSI_TO_LQI); - rssi = rf_mac_get_rssi(); - rf_mac_rx_enable(); - //Call ARM API - if( device_driver.phy_rx_cb ){ - device_driver.phy_rx_cb(PHYPAYLOAD, length, lqi, rssi, rf_radio_driver_id); - } - } -} - -static void rf_mac_tx_interrupt(void) -{ - phy_link_tx_status_e status; - /** Clear the event complete IRQ */ - MACHWREG->CLEAR_IRQ.WORD = MAC_IRQ_COMPLETE; - /* This IRQ means that Data Request is complete; check the status */ - uint8_t sharedSeqSts = MACHWREG->STATUS.BITS.CODE; - - rf_mac_set_rx_on_state(true); - - switch (sharedSeqSts) { - case MAC_STATUS_SUCCESS: /* Positive */ - //SET Success - if (rf_mac_ack_requsted) { - status = PHY_LINK_TX_DONE; - } else { - status = PHY_LINK_TX_SUCCESS; - } - break; - - case MAC_STATUS_RXACK_PENDING: /* Positive for broadcast */ - status = PHY_LINK_TX_DONE_PENDING; - break; - - - case MAC_STATUS_BUSY: - status = PHY_LINK_CCA_FAIL; - break; - - default: - status = PHY_LINK_TX_FAIL; - break; - } - rf_mac_ack_requsted = false; - //Call RX TX complete - if( device_driver.phy_tx_done_cb ) { - device_driver.phy_tx_done_cb(rf_radio_driver_id, rf_mac_handle, status, 1, 1); - } -} - -/** -* RF MAC Interrupt handler -*/ -extern "C" void fIrqMacHwHandler(void) -{ - NVIC_DisableIRQ(MacHw_IRQn); - rf_thread.flags_set(SIGNAL_COUNT_RADIO); -} - -static void handle_IRQ_events(void) -{ - /** Set MAC timers to initial state */ - MACHWREG->TIMER_ENABLE.BITS.START = false; - MACHWREG->TIMER_ENABLE.BITS.STOP = false; - MACHWREG->TIMER_DISABLE.BITS.START = false; - MACHWREG->TIMER_DISABLE.BITS.STOP = false; - - /** Disarm start/stop timers, disable and clear irq (event_complete) */ - rf_mac_timers_disable_trig_event(); - /** REVD changes to sequence tracking register. Sequence register can be used instead of rf_mac_state */ - - if (rf_mac_state == MAC_RF_RX_ON) { - rf_rx_interrupt(); - } else if(rf_mac_state == MAC_RF_TX_ON) { - rf_mac_tx_interrupt(); - } else if (rf_mac_state == MAC_RF_ED_SCAN){ - rf_rx_ed_scan_interrupt(); - } else { - /** Clear the event complete IRQ */ - MACHWREG->CLEAR_IRQ.WORD = MAC_IRQ_COMPLETE; - uint8_t sharedSeqSts = MACHWREG->STATUS.BITS.CODE; - } -} - -NanostackRfPhyNcs36510::NanostackRfPhyNcs36510() -{ - memcpy(MAC64_addr, MAC64_addr_default, sizeof(MAC64_addr)); -} - -NanostackRfPhyNcs36510::~NanostackRfPhyNcs36510() -{ - // Do nothing -} - -int8_t NanostackRfPhyNcs36510::rf_register() -{ - platform_enter_critical(); - - if (rf != NULL) { - platform_exit_critical(); - error("Multiple registrations of NanostackRfPhyNcs36510 not supported"); - return -1; - } - - rf = this; - int8_t radio_id = rf_device_register(); - if (radio_id < 0) { - rf = NULL; - } - - platform_exit_critical(); - return radio_id; -} - -void NanostackRfPhyNcs36510::rf_unregister() -{ - platform_enter_critical(); - - if (rf != this) { - platform_exit_critical(); - return; - } - - rf_device_unregister(); - rf = NULL; - - platform_exit_critical(); -} - -void NanostackRfPhyNcs36510::get_mac_address(uint8_t *mac) -{ - platform_enter_critical(); - - memcpy((void*)mac, (void*)MAC64_addr, sizeof(MAC64_addr)); - - platform_exit_critical(); -} - -void NanostackRfPhyNcs36510::set_mac_address(uint8_t *mac) -{ - platform_enter_critical(); - - if (NULL != rf) { - error("NanostackRfPhyNcs36510 cannot change mac address when running"); - platform_exit_critical(); - return; - } - memcpy((void*)MAC64_addr, (void*)mac, sizeof(MAC64_addr)); - - platform_exit_critical(); -} - -NanostackRfPhy &NanostackRfPhy::get_default_instance() -{ - static NanostackRfPhyNcs36510 rf_phy; - return rf_phy; -} diff --git a/features/nanostack/targets/TARGET_NCS36510/NanostackRfPhyNcs36510.h b/features/nanostack/targets/TARGET_NCS36510/NanostackRfPhyNcs36510.h deleted file mode 100644 index 32caedf741..0000000000 --- a/features/nanostack/targets/TARGET_NCS36510/NanostackRfPhyNcs36510.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2014-2015 ARM Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef NANOSTACK_PHY_NCS36510_H_ -#define NANOSTACK_PHY_NCS36510_H_ - -#include "NanostackRfPhy.h" - -class NanostackRfPhyNcs36510 : public NanostackRfPhy { -public: - NanostackRfPhyNcs36510(); - ~NanostackRfPhyNcs36510(); - int8_t rf_register(); - void rf_unregister(); - void get_mac_address(uint8_t *mac); - void set_mac_address(uint8_t *mac); -}; - -#endif /* NANOSTACK_PHY_NCS36510_H_ */ diff --git a/features/netsocket/mbed_lib.json b/features/netsocket/mbed_lib.json index ca24434b7c..5d1eccb4a5 100644 --- a/features/netsocket/mbed_lib.json +++ b/features/netsocket/mbed_lib.json @@ -76,9 +76,6 @@ } }, "target_overrides": { - "NCS36510": { - "nsapi.default-mesh-type": "LOWPAN" - }, "TB_SENSE_12": { "nsapi.default-mesh-type": "LOWPAN" } diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c deleted file mode 100644 index 142101fbd3..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c +++ /dev/null @@ -1,144 +0,0 @@ -/** -****************************************************************************** -* @file pad.c -* @brief PAD management support code -* @internal -* @author ON Semiconductor -* $Rev: 2848 $ -* $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup pad -* -* @details -*/ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "memory_map.h" -#include "pad_map.h" -#include "clock.h" - -/************************************************************************************************* -* * -* Symbolic Constants * -* * -*************************************************************************************************/ -#define PAD_CTRL_OP_DRIVE_STRENGTH_MASK (uint32_t)0x1C -#define PAD_NUM_OF_IO 17 -#define PAD_OP_DRIVE_STRGTH_MAX 7 -#define PAD_OP_DRIVE_TYPE_MAX 1 -#define PAD_OP_PULL_TYPE_MAX 3 - -#define PAD_REG_ADRS_BYTE_SIZE 4 - -#define PAD_OP_DRIVE_STRGTH_BIT_POS 2 -#define PAD_OP_DRIVE_TYPE_BIT_POS 5 -#define PAD_OP_PULL_TYPE_BIT_POS 0 - -/************************************************************************************************* -* * -* Global variables * -* * -*************************************************************************************************/ - -/* Peripheral PAD register mutex */ -/* sem_pt GlobMutexPadReg; */ - -/************************************************************************************************* -* * -* Functions * -* * -*************************************************************************************************/ - -/** Find description at pad.h */ -void fPadInit() -{ - /** - Enable the clock for PAD peripheral device */ - CLOCK_ENABLE(CLOCK_PAD); - - /** - Set pad parameters, output drive strength, pull piece control, output drive type */ - PADREG->PADIO0.WORD = PAD_OUTPUT_PN_L1_OD; /* UART1 TXD */ - PADREG->PADIO1.WORD = PAD_INPUT_PD_L1_PP; /* UART1 RXD */ - PADREG->PADIO2.WORD = PAD_INPUT_PD_L1_PP; /* UART1 CTS */ - PADREG->PADIO3.WORD = PAD_OUTPUT_PN_L1_OD; /* UART1 RTS */ - PADREG->PADIO4.WORD = PAD_UNUSED_PD_L1_PP; - PADREG->PADIO5.WORD = PAD_UNUSED_PD_L1_PP; - PADREG->PADIO6.WORD = PAD_UNUSED_PD_L1_PP; - PADREG->PADIO7.WORD = PAD_UNUSED_PD_L1_PP; - PADREG->PADIO8.WORD = PAD_OUTPUT_PN_L1_OD; /* UART2 TXD */ - PADREG->PADIO9.WORD = PAD_INPUT_PD_L1_PP; /* UART2 RXD */ - PADREG->PADIO10.WORD = PAD_UNUSED_PD_L1_PP; - PADREG->PADIO11.WORD = PAD_INPUT_PD_L1_PP; /* SWO */ - PADREG->PADIO12.WORD = PAD_INPUT_PD_L1_PP; /* SWCLK */ - PADREG->PADIO13.WORD = PAD_INPUT_PD_L1_PP; /* SWDIO */ - PADREG->PADIO14.WORD = PAD_INPUT_PD_L1_PP; - PADREG->PADIO15.WORD = PAD_UNUSED_PD_L1_PP; - PADREG->PADIO16.WORD = PAD_UNUSED_PD_L1_PP; - PADREG->PADIO17.WORD = PAD_UNUSED_PD_L1_PP; - - /** - Disable the clock for PAD peripheral device */ - CLOCK_DISABLE(CLOCK_PAD); - -} - -/** Find description at pad.h */ -boolean fPadIOCtrl(uint8_t PadNum, uint8_t OutputDriveStrength, uint8_t OutputDriveType, uint8_t PullType) -{ - PadReg_t *PadRegOffset; - /** \verbatim - Table: O/p drive strength - - Drive strength 3.3V (min/typ/max) 1V (min/typ/max) - 000 1/1.4/2.1 mA 0.043/0.07/0.11 mA - 001 2/2.7/4.1 mA 0.086/0.15/0.215 mA - 010 4.1/5.3/7.8 mA 0.188/0.3/0.4 mA - 011 8.1/10.4/15 8 mA 0.4/0.6/0.81 mA - 100 20.8/26/37 mA* 1/1.6/2.2 mA - 101 40.5/50/70 mA* 2/3/4.3 mA - 11x 57/73/102 mA* 3/4.6/6.2 mA - - *Values are only accessible when CDBGPWRUPREQ is high. This limits the maximum output current in functional mode. \endverbatim */ - - - if((PadNum <= PAD_NUM_OF_IO) && - (OutputDriveStrength <= PAD_OP_DRIVE_STRGTH_MAX) && - (OutputDriveType <= PAD_OP_DRIVE_TYPE_MAX) && (PullType <= PAD_OP_PULL_TYPE_MAX)) { - /** - Get PAD IO register address for the PAD number */ - PadRegOffset = (PadReg_t*)(PADREG_BASE + (PadNum * PAD_REG_ADRS_BYTE_SIZE)); - - /** - Enable the clock for PAD peripheral device */ - CLOCK_ENABLE(CLOCK_PAD); - - /** - Set drive type, pulltype & drive strength */ - PadRegOffset->PADIO0.WORD = (uint32_t)((PullType << PAD_OP_PULL_TYPE_BIT_POS) | - (OutputDriveStrength << PAD_OP_DRIVE_STRGTH_BIT_POS) | - (OutputDriveType << PAD_OP_DRIVE_TYPE_BIT_POS)); - - /** - Disable the clock for PAD peripheral device */ - CLOCK_DISABLE(CLOCK_PAD); - return True; - } - /* Invalid parameter/s */ - return False; -} \ No newline at end of file diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h deleted file mode 100644 index 7306fa2e0b..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralNames.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - ****************************************************************************** - * @file peripheralnames.h - * @brief Implements an assertion. - * @internal - * @author ON Semiconductor - * $Rev: 0.1 $ - * $Date: 2015-11-07 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup debug - */ - -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#include "memory_map.h" /* This is needed because enums use base adresses */ -#include "PinNames.h" -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_0 = (int)ADCREG_BASE -} ADCName; - -typedef enum { - UART_0 = (int)UART1REG_BASE, - UART_1 = (int)UART2REG_BASE, -} UARTName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -typedef enum { - SPI_0 = (int)SPI1REG_BASE, - SPI_1 = (int)SPI2REG_BASE -} SPIName; - -typedef enum { - I2C_0 = (int)I2C1REG_BASE, - I2C_1 = (int)I2C2REG_BASE -} I2CName; - -typedef enum { - PWM_0 = (int)PWMREG_BASE, -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c deleted file mode 100644 index fa03866705..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c +++ /dev/null @@ -1,114 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*todo: determine how function argument is used */ - -#include "PeripheralPins.h" - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {A0, ADC_0, 0}, - {A1, ADC_0, 0}, - {A2, ADC_0, 0}, - {A3, ADC_0, 0}, - {NC , NC , 0} -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {GPIO3, I2C_0, 5}, - {GPIO4, I2C_0, 5}, - {GPIO10, I2C_0, 5}, - {GPIO12, I2C_0, 5}, - {GPIO15, I2C_1, 5}, - {GPIO16, I2C_1, 5}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {GPIO2, I2C_0, 5}, - {GPIO5, I2C_0, 5}, - {GPIO11, I2C_0, 5}, - {GPIO13, I2C_0, 5}, - {GPIO14, I2C_1, 5}, - {GPIO17, I2C_1, 5}, - {NC , NC , 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {GPIO0, UART_0, 7}, - {GPIO8, UART_1, 7}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {GPIO1, UART_0, 7}, - {GPIO9, UART_1, 7}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - /*todo: other pins are possible, need to add */ - {SPI1_SCLK_2, SPI_0, 6}, - {SPI1_SCLK_3, SPI_0, 6}, - {SPI2_SCLK, SPI_1, 6}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - /*todo: other pins are possible, need to add */ - {SPI1_SDATAO_2, SPI_0, 6}, - {SPI1_SDATAO_3, SPI_0, 6}, - {SPI2_SDATAO, SPI_1, 6}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - /*todo: other pins are possible, need to add */ - {SPI1_SDATAI_2, SPI_0, 6}, - {SPI1_SDATAI_3, SPI_0, 6}, - {SPI2_SDATAI, SPI_1, 6}, - {NC, NC, 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - /*todo: other pins are possible, need to add */ - /* TODO what about SSNO */ - {SPI1_SSNO0_1, SPI_0, 6}, - {SPI1_SSNO1_1, SPI_0, 6}, - {SPI1_SSNO2_1, SPI_0, 6}, - {SPI1_SSNO3_1, SPI_0, 6}, - {SPI1_SSNI_2, SPI_0, 6}, - {SPI1_SSNO0_2, SPI_0, 6}, - {SPI1_SSNO1_2, SPI_0, 6}, - {SPI1_SSNO2_2, SPI_0, 6}, - {SPI2_SSNI, SPI_1, 6}, - {SPI2_SSNO0, SPI_1, 6}, - {NC, NC, 0} -}; - - -const PinMap PinMap_PWM[] = { - - {GPIO6 , PWM_0 , 4}, - {GPIO7 , PWM_0 , 4}, - {GPIO9 , PWM_0 , 4}, - {GPIO12 , PWM_0 , 4}, - {GPIO13 , PWM_0 , 4}, - {NC , NC , 0} -}; diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.h deleted file mode 100644 index e815b3e574..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.h +++ /dev/null @@ -1,42 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -/************I2C***************/ -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -/************UART***************/ -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -/************SPI***************/ -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SSEL[]; - -extern const PinMap PinMap_PWM[]; - -#endif diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h deleted file mode 100644 index f49368c096..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h +++ /dev/null @@ -1,186 +0,0 @@ -/** - ****************************************************************************** - * @file PinNames.h - * @brief Implements common PIN names for peripherals. - * @internal - * @author ON Semiconductor - * $Rev: 0.1 $ - * $Date: 2015-11-06 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup debug - */ - - -#ifndef PINNAME_H_ -#define PINNAME_H_ - -#include "types.h" -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - NC = (int)0xFFFFFFFF, - GPIO0 = 0, - GPIO1, - GPIO2, - GPIO3, - GPIO4, - GPIO5, - GPIO6, - GPIO7, - GPIO8, - GPIO9, - GPIO10, - GPIO11, - GPIO12, - GPIO13, - GPIO14, - GPIO15, - GPIO16, - GPIO17, - A0, - A1, - A2, - A3, - A4 = NC, - A5 = NC, - UART1_TX = GPIO0, - UART1_RX = GPIO1, - UART2_TX = GPIO8, - UART2_RX = GPIO9, - - I2C1_SCLK_1 = GPIO2, - I2C1_SDATA_1 = GPIO3, - I2C1_SCLK_2 = GPIO5, - I2C1_SDATA_2 = GPIO4, - I2C1_SCLK = I2C1_SCLK_1, /*Default*/ - I2C1_SDATA = I2C1_SDATA_1, /*Default*/ - - I2C2_SCLK_1 = GPIO14, - I2C2_SDATA_1 = GPIO15, - I2C2_SCLK_2 = GPIO17, - I2C2_SDATA_2 = GPIO16, - I2C2_SCLK = I2C2_SCLK_2, /*Default*/ - I2C2_SDATA = I2C2_SDATA_2, /*Default*/ - I2C_SCL = I2C1_SCLK_1, /*Default*/ - I2C_SDA = I2C1_SDATA_1, /*Default*/ - - /* SPI 1 with 1st set of CROSS BAR */ - SPI1_SSNO0_1 = GPIO0, - SPI1_SSNO1_1 = GPIO1, - SPI1_SSNO2_1 = GPIO2, - SPI1_SSNO3_1 = GPIO3, - - /* SPI 1 with 2st set of CROSS BAR */ - SPI1_SCLK_2 = GPIO4, - SPI1_SDATAO_2 = GPIO5, - SPI1_SDATAI_2 = GPIO6, - SPI1_SSNI_2 = GPIO7, - SPI1_SSNO0_2 = GPIO8, - SPI1_SSNO1_2 = GPIO9, - SPI1_SSNO2_2 = GPIO10, - - SPI1_SCLK = SPI1_SCLK_2, /*Default*/ - SPI1_SDATAO = SPI1_SDATAO_2, /*Default*/ - SPI1_SDATAI = SPI1_SDATAI_2, /*Default*/ - SPI1_SSNI = SPI1_SSNI_2, /*Default*/ - SPI1_SSNO0 = SPI1_SSNO0_2, /*Default*/ - SPI1_SSNO1 = SPI1_SSNO1_2, /*Default*/ - SPI1_SSNO2 = SPI1_SSNO2_2, /*Default*/ - - /* SPI 1 with 3rd set of CROSS BAR */ - SPI1_SCLK_3 = GPIO8, - SPI1_SDATAO_3 = GPIO9, - SPI1_SDATAI_3 = GPIO10, - - /* SPI 2 */ - SPI2_SCLK = GPIO14, - SPI2_SDATAO = GPIO15, - SPI2_SDATAI = GPIO16, - SPI2_SSNI = GPIO17, - SPI2_SSNO0 = GPIO17, - - // Generic signals namings - LED1 = GPIO4, - LED2 = GPIO6, - LED3 = GPIO5, - LED4 = (int)0xFFFFFFFF, - LED5 = (int)0xFFFFFFFF, - LED_GREEN = GPIO4, - LED_YELLOW = GPIO6, - LED_BLUE = GPIO5, - USER_BUTTON = GPIO7, /*NEW connection on NCS36510-RF Rev 1.1 - Alias of SW1 */ - - SW1 = GPIO7, /*NEW connection on NCS36510-RF Rev 1.1 */ - SW2 = GPIO10, /*NEW connection on NCS36510-RF Rev 1.1 */ - - // Standardized button names - BUTTON1 = SW1, - BUTTON2 = SW2, - - SERIAL_TX = GPIO0, - SERIAL_RX = GPIO1, - USBTX = GPIO0, - USBRX = GPIO1, - D0 = GPIO9, - D1 = GPIO8, - D2 = GPIO4, - D3 = GPIO6, - D4 = GPIO5, - D5 = GPIO7, - D6 = GPIO10, - D7 = (int)0xFFFFFFFF, - D8 = (int)0xFFFFFFFF, - D9 = (int)0xFFFFFFFF, - D10 = GPIO17, - D11 = GPIO15, - D12 = GPIO16, - D13 = GPIO14, - D14 = GPIO3, - D15 = GPIO2 -} PinName; - -typedef enum { - PIN_INPUT, - PIN_OUTPUT, - -} PinDirection; - -typedef enum { - PushPullPullDown = 0, - PushPullNoPull = 1, - PushPullPullUp = 2, - OpenDrainPullDown = 3, - OpenDrainNoPull = 4, - OpenDrainPullUp = 5, - PullNone = PushPullNoPull, - PullUp = PushPullPullUp, - PullDown = PushPullPullDown, - OpenDrain = OpenDrainPullUp, - PullDefault = PullNone - -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif //PINNAME_H_ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/PortNames.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/PortNames.h deleted file mode 100644 index b2674b1f16..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/PortNames.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0 //GPIO pins 0-17 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h deleted file mode 100644 index 98279357ef..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - ****************************************************************************** - * @file adc_sar.h - * @internal - * @author ON Semiconductor - * $Rev: 3426 $ - * $Date: 2015-06-15 16:46:35 +0530 (Mon, 15 Jun 2015) $ - * @brief Definitions and API for the SAR ADC driver. - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup adc_sar - * - * @details - *

- *

- */ - -#ifndef ADC_DRIVER_H_ -#define ADC_DRIVER_H_ - -#include "adc_sar_map.h" - -#if DEVICE_ANALOGIN - -#ifdef __cplusplus -extern "C" { -#endif - -/* ADC register bits */ -#define ADC_CONTROL_MODE_BIT_POS 0 -#define ADC_CONTROL_MEASTYPE_BIT_POS 3 -#define ADC_CONTROL_INPUTSCALE_BIT_POS 4 -#define ADC_CONTROL_MEAS_CH_BIT_POS 8 -#define ADC_CONTROL_REF_CH_BIT_POS 12 -#define ADC_PRESCALE_VAL_BIT_POS 0 -#define ADC_PRESCALE_EN_BIT_POS 8 -#define ADC_DELAY_SAMPLE_RATE_BIT_POS 0 -#define ADC_DELAY_WARMUP_BIT_POS 16 -#define ADC_DELAY_SAMPLE_TIME_BIT_POS 24 - -typedef enum { - ADC_CHANNEL0 = 0, - ADC_CHANNEL1, - ADC_CHANNEL2, - ADC_CHANNEL3, - ADC_TEMPSENSR = 6, - ADC_BATTERY -} Type_RefCh_ConvCh; - -typedef enum { - ADC_RELATIVE_MEAS = 0, - ADC_ABSOLUTE_MEAS -} Type_Meastype; - -typedef enum { - ADC_SINGLE_SAMPLE = 0, - ADC_CONTINUOUS_SAMPLE -} Type_Mode; - -typedef enum { - ADC_INT_DISABLE = 0, - ADC_INT_ENABLE -} Type_Intrpt; - -typedef enum { - ADC_IP_SCALE_1_0 = 0, - ADC_IP_SCALE_0_6923, - ADC_IP_SCALE_0_5294, - ADC_IP_SCALE_0_4286, - ADC_IP_SCALE_0_3600, - ADC_IP_SCALE_0_3103, - ADC_IP_SCALE_0_2728, - ADC_IP_SCALE_0_2432 -} Ip_Scale_Type; - -void fAdcHandler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* DEVICE_ANALOGIN */ - -#endif /* ADC_DRIVER_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h deleted file mode 100644 index cb5793d483..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h +++ /dev/null @@ -1,79 +0,0 @@ -/** - ****************************************************************************** - * @file adc_sar_map.h - * @brief ADC HW register map - * @internal - * @author ON Semiconductor - * $Rev: 3422 $ - * $Date: 2015-06-09 11:01:43 +0530 (Tue, 09 Jun 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup adc_sar - * - * @details - *

- * ADC HW register map description - *

- * - */ - -#ifndef ADC_MAP_H_ -#define ADC_MAP_H_ - - -#include "architecture.h" - -/* ADC Control HW Structure Overlay */ -typedef struct { - union { - struct { - __IO uint32_t MODE :1; /** 1= Continuous Conversion 0= Single Shot */ - __IO uint32_t START_CONV :1; /** 1= Start Conversion 0= No effect*/ - __IO uint32_t ABORT :1; /** 1= Aborts the Continuous Conversion mode 0=No effect */ - __IO uint32_t MEASUREMENT_TYPE :1; /** 1= Absolute 0= Differential */ - __IO uint32_t INPUT_SCALE :3; /** 000 – 1.0 001 – 0.6923 010 – 0.5294 011 – 0.4286 100 – 0.3600 101 – 0.3103 110 – 0.2728 111 – 0.2432 */ - __I uint32_t BIT7:1; /** NA Always read backs 0*/ - __IO uint32_t CONV_CH :3; /** Selects 1 or 8 channels to do a conversion on. 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor 111 – Battery */ - __I uint32_t NA :1; /** NA */ - __IO uint32_t REF_CH :3; /** Selects 1 to 8 channels for reference channel 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor 111 – Battery */ - } BITS; - __IO uint32_t WORD; - } CONTROL; - union { - struct { - __IO uint32_t SAMPLE_RATE :16; /** Sets the sample rate in units of PCLKperiod * (Prescale + 1). */ - __IO uint32_t WARMUP_TIME :8; /** Sets the warm-up time in units of PCLKperiod * (Prescale + 1) */ - __IO uint32_t SAMPLE_TIME :8; /** Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/ - } BITS; - __IO uint32_t WORD; - } DELAY; - __I uint32_t DATA; - __IO uint32_t IR; - union { - struct { - __IO uint32_t PRESC_VAL :8; /**Set the pre-scalar value. The SAR ADC nominally runs at 4MHz, so this value should be programmed to 32 Mhz/4mhz -1=7 */ - __IO uint32_t PRESC_EN :1; /** 1= enables PreScalar 0= Disable Prescalar */ -// __IO uint32_t PHASE_CTRL :1; /** 1 = Phase 2 is delayed two 32MHz clock from phase 1. 0= Phase 2 is delayed one 32MHz clock from phase 1. */ - } BITS; - __IO uint32_t WORD; - } PRESCALE; - __I uint32_t STATUS; -} ADCReg_t,*AdcReg_pt; - -#endif /* ADC_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h deleted file mode 100644 index ec649307e7..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - ****************************************************************************** - * @file aes_map.h - * @brief AES HW register map - * @internal - * @author ON Semiconductor. - * $Rev: 2110 $ - * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup aes - * - * @details - *

- * AES HW register map description - *

- */ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -#ifndef AES_MAP_H_ -#define AES_MAP_H_ - -#include "architecture.h" - -/** AES Encryption HW Structure Overlay */ -typedef struct { - __IO uint32_t KEY0; /**< Bits[31:00] of the 128-bit key */ - __IO uint32_t KEY1; /**< Bits[63:32] of the 128-bit key */ - __IO uint32_t KEY2; /**< Bits[95:64] of the 128-bit key */ - __IO uint32_t KEY3; /**< Bits[127:96] of the 128-bit key */ - __IO uint32_t KEY4; /**< Bits[159:128] of the 256-bit key */ - __IO uint32_t KEY5; /**< Bits[191:160] of the 256-bit key */ - __IO uint32_t KEY6; /**< Bits[223:192] of the 256-bit key */ - __IO uint32_t KEY7; /**< Bits[255:224] of the 256-bit key */ - - __IO uint32_t CNTi0; /**< Bits[31:00] of the 128-bit counter value used in counter mode */ - __IO uint32_t CNTi1; /**< Bits[63:32] of the 128-bit counter value used in counter mode */ - __IO uint32_t CNTi2; /**< Bits[95:64] of the 128-bit counter value used in counter mode */ - __IO uint32_t CNTi3; /**< Bits[127:96] of the 128-bit counter value used in counter mode */ - __I uint32_t CNTo0; /**< Bits[31:00] of the 128-bit counter result */ - __I uint32_t CNTo1; /**< Bits[63:32] of the 128-bit counter result */ - __I uint32_t CNTo2; /**< Bits[95:64] of the 128-bit counter result */ - __I uint32_t CNTo3; /**< Bits[127:96] of the 128-bit counter result */ - - __I uint32_t CBCo0; /**< Bits[31:00] of the 128-bit CBC result */ - __I uint32_t CBCo1; /**< Bits[63:32] of the 128-bit CBC result */ - __I uint32_t CBCo2; /**< Bits[95:64] of the 128-bit CBC result */ - __I uint32_t CBCo3; /**< Bits[127:96] of the 128-bit CBC result */ - union { - struct { - __IO uint32_t START:1; /**< start the encryption : 0 = no-effect , 1 = enable */ - __IO uint32_t ACC_CLR:1; /**< Clear the CBC accumulator : 0 = no-effect 1 = clears the CBC accumulator */ - __IO uint32_t INT_CLEAR:1; /**< interrupt clear : 0 = no-effect 1 = clear the interrupt */ - } BITS; - __IO uint32_t WORD; - } CTL; - union { - struct { - __IO uint32_t CBC_MODE:1; /**< counter mode : 0 = counter mode , 1 = CBC mode */ - __IO uint32_t BYPASS:1; /**< encryption : 0 = Normal Mode , 1 = Bypasss any encryption */ - __IO uint32_t INT_EN:1; /**< interrupt mask : 0 = disabled 1 = enabled */ - __IO uint32_t KEY_LENGTH:1; /**< Key Length: 0 = 128 Bit Encryption 1 = 256 Bit Encryption */ - - } BITS; - __IO uint32_t WORD; - } MODE; - union { - struct { - __I uint32_t COMPLETE:1;/**< status : 0 = not complete , 1 = complete */ - } BITS; - __IO uint32_t WORD; - } STAT; - - __O uint32_t MAC_INIT0; /**< Bits[31:00] of the CBC Initialization Vector */ - __O uint32_t MAC_INIT1; /**< Bits[63:32] of the CBC Initialization Vector */ - __O uint32_t MAC_INIT2; /**< Bits[95:64] of the CBC Initialization Vector */ - __O uint32_t MAC_INIT3; /**< Bits[127:96] of the CBC Initialization Vector */ - - __IO uint32_t RESERVED; - __O uint32_t DATA0; /**< Bits[31:00] of the 128-bit data to encrypt */ - __O uint32_t DATA1; /**< Bits[63:32] of the 128-bit data to encrypt */ - __O uint32_t DATA2; /**< Bits[95:64] of the 128-bit data to encrypt */ - __O uint32_t DATA3; /**< Bits[127:96] of the 128-bit data to encrypt */ -} AesReg_t, *AesReg_pt; - -#endif /* AES_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c deleted file mode 100644 index b93318c01f..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/analogin_api.c +++ /dev/null @@ -1,205 +0,0 @@ -/** - ****************************************************************************** - * @file adc_sar.c - * @brief Implementation of a SAR ADC driver - * @internal - * @author ON Semiconductor - * $Rev: - * $Date: - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup adc_sar - * - * @details - *

- *

- * - */ - -#include "device.h" -#include "analogin_api.h" -#include "PeripheralPins.h" -#include "mbed_assert.h" -#include "clock.h" -#include "adc_sar.h" - -#if DEVICE_ANALOGIN - -/** - * \defgroup hal_analogin Analogin hal functions - * @{ - */ - -/** Initialize the analogin peripheral - * - * Configures the pin used by analogin. - * @param obj The analogin object to initialize - * @param pin The analogin pin name - */ -void analogin_init(analogin_t *obj, PinName pin) -{ - CLOCK_ENABLE(CLOCK_ADC); - ADCName adc; - uint8_t adc_pin = 0; - - adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(adc != (ADCName)NC); - - obj->adcReg = (AdcReg_pt)adc; - obj->pin = pin; - obj->pinFlag = 1; - obj->ADC_Offset_Value = TRIMREG->ADC_OFFSET_TRIM; - - switch (pin) { - case A0: - adc_pin=0; - break; - case A1: - adc_pin = 1; - break; - case A2: - adc_pin = 2; - break; - case A3: - adc_pin = 3; - break; - default: - break; - } - - /* If no config parameters are passed on; assume default value */ - if (obj->adcConf == Null) { - /* Single sample, absolute conversion, scale = 1 */ - obj->adcReg->CONTROL.WORD = ((0 << ADC_CONTROL_MODE_BIT_POS) | - (1 << ADC_CONTROL_MEASTYPE_BIT_POS) | - (6 << ADC_CONTROL_INPUTSCALE_BIT_POS) | - (((uint8_t)adc_pin) << ADC_CONTROL_MEAS_CH_BIT_POS)); - - /* Prescaler enabled; set to 7 */ - obj->adcReg->PRESCALE.WORD = ((True << ADC_PRESCALE_EN_BIT_POS) | - (7 << ADC_PRESCALE_VAL_BIT_POS)); /* ADC clock = 32MHz/(Prescale + 1) */ - - obj->adcReg->DELAY.WORD = ((0x34 << ADC_DELAY_SAMPLE_RATE_BIT_POS) | /** 25 uS Sets the sample rate in units of PCLKperiod * (Prescale + 1). */ - (0x05 << ADC_DELAY_WARMUP_BIT_POS) | /** 12.5 uS Sets the measure time in units of PCLKperiod * (Prescale + 1). */ - (0x1A << ADC_DELAY_SAMPLE_TIME_BIT_POS)); /** 2.5 uS Sets the warm-up time in units of PCLKperiod * (Prescale + 1). */ - - obj->adcReg->IR = 0; /** No interrupt generated */ - } else { - obj->adcConf->convCh = adc_pin; - - /* ADC register settings */ - if((obj->adcConf->measurementType) == ADC_RELATIVE_MEAS) { - obj->adcReg->CONTROL.WORD = ((obj->adcConf->mode << ADC_CONTROL_MODE_BIT_POS) | - (obj->adcConf->measurementType << ADC_CONTROL_MEASTYPE_BIT_POS) | - (obj->adcConf->inputScale << ADC_CONTROL_INPUTSCALE_BIT_POS) | - (obj->adcConf->convCh << ADC_CONTROL_MEAS_CH_BIT_POS) | - (obj->adcConf->referenceCh << ADC_CONTROL_REF_CH_BIT_POS)); - } else { - obj->adcReg->CONTROL.WORD = ((obj->adcConf->mode << ADC_CONTROL_MODE_BIT_POS) | - (obj->adcConf->measurementType << ADC_CONTROL_MEASTYPE_BIT_POS) | - (obj->adcConf->inputScale << ADC_CONTROL_INPUTSCALE_BIT_POS) | - (obj->adcConf->convCh << ADC_CONTROL_MEAS_CH_BIT_POS)); - } - - obj->adcReg->PRESCALE.WORD = ((True << ADC_PRESCALE_EN_BIT_POS) | - (obj->adcConf->PrescaleVal << ADC_PRESCALE_VAL_BIT_POS)); /* ADC clock = 32MHz/(Prescale + 1) */ - - obj->adcReg->DELAY.WORD = ((obj->adcConf->samplingRate << ADC_DELAY_SAMPLE_RATE_BIT_POS) | /** 25 uS Sets the sample rate in units of PCLKperiod * (Prescale + 1). */ - (obj->adcConf->WarmUpTime << ADC_DELAY_WARMUP_BIT_POS) | /** 12.5 uS Sets the measure time in units of PCLKperiod * (Prescale + 1). */ - (obj->adcConf->samplingTime << ADC_DELAY_SAMPLE_TIME_BIT_POS)); /** 2.5 uS Sets the warm-up time in units of PCLKperiod * (Prescale + 1). */ - - obj->adcReg->IR = obj->adcConf->interruptConfig; /** Interrupt setting */ - } - - /* Enable interrupt */ - NVIC_ClearPendingIRQ(Adc_IRQn); - NVIC_EnableIRQ(Adc_IRQn); -} - -/** Read the input voltage, represented as a float in the range [0.0, 1.0] - * - * @param obj The analogin object - * @return A floating value representing the current input voltage - */ -float analogin_read(analogin_t *obj) -{ - float retVal = 0.0; - uint16_t value = analogin_read_u16(obj); - retVal = (float)value * (1.0f / (float)0x03FF); - return(retVal); -} - -/** Read the value from analogin pin, represented as an unsigned 16bit value - * - * @param obj The analogin object - * @return An unsigned 16bit value representing the current input voltage - */ -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t adcData = 0; - uint8_t adc_pin = 0; - - CLOCK_ENABLE(CLOCK_ADC); - - if (obj->pinFlag) { - switch (obj->pin) { - case A0: - adc_pin=0; - break; - case A1: - adc_pin = 1; - break; - case A2: - adc_pin = 2; - break; - case A3: - adc_pin = 3; - break; - default: - break; - } - - /* Re initialize the pin configured for ADC read */ - obj->adcReg->CONTROL.BITS.CONV_CH = adc_pin; - } - - obj->adcReg->CONTROL.BITS.START_CONV=1; /* Start The Conversion */ - - while((uint32_t)(obj->adcReg->STATUS)!=(uint32_t)1) { - } - adcData =(uint16_t)(obj->adcReg->DATA); - - /* Offset the ADC data with trim value */ - if (obj->ADC_Offset_Value != 0xFFFFFFFF) { - - if(adcData >= obj->ADC_Offset_Value) { - adcData -= obj->ADC_Offset_Value; - } - } - - return(adcData); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} - -#endif // DEVICE_ANALOGIN - diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/architecture.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/architecture.h deleted file mode 100644 index 69652af0ee..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/architecture.h +++ /dev/null @@ -1,77 +0,0 @@ -/** -****************************************************************************** -* @file architecture.h -* @brief CM3 architecture specific inclusions and defines. -* @internal -* @author ON Semiconductor -* $Rev: $ -* $Date: $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup bsp -*/ - -#ifndef ARCHITECTURE_H_ -#define ARCHITECTURE_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -//#include -//#include -//#include - -#include "NCS36510.h" -#include "system_NCS36510.h" -#include "core_cm3.h" -#include "cmsis.h" - - -/************************************************************************************************* -* * -* Symbolic Constants * -* * -*************************************************************************************************/ - -/* Interrupt Control and State Register (0xE000ED04) - * 31 NMIPENDSET R/W 0 NMI pended - * 28 PENDSVSET R/W 0 Write 1 to pend system call; Read value - * indicates pending status - * 27 PENDSVCLR W 0 Write 1 to clear PendSV pending status - * 26 PENDSTSET R/W 0 Write 1 to pend Systick exception; Read - * value indicates pending status - * 25 PENDSTCLR W 0 Write 1 to clear Systick pending status - * 23 ISRPREEMPT R 0 Indicate that a pending interrupt is going - * to be active in next step (for debug) - * 22 ISRPENDING R 0 External interrupt pending (excluding - * system exceptions such as NMI for - * fault) - * 21:12 VECTPENDING R 0 Pending ISR number - * 11 RETTOBASE R 0 Set to 1 when the processor is running - * an exception handler and will return to - * thread level if interrupt return and no - * other exceptions pending - * 9:0 VECTACTIVE R 0 Current running interrupt service routine - */ -#define RUNNING_IN_ISR (((SCB->ICSR & 0x3FF) > 0 ) ? 1 : 0) - -#endif /* ARCHITECTURE_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h deleted file mode 100644 index b78089330e..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - ****************************************************************************** - * @file assert.h - * @brief Defines an assertion for debugging purposes. - * @internal - * @author ON Semiconductor - * $Rev: 3823 $ - * $Date: 2015-10-23 16:21:37 +0530 (Fri, 23 Oct 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @details - * While debugging, the ASSERT macro can be used to verify the expected behaviour - * of the source code. If the condition that is passed as a parameter to the ASSERT - * macro evaluates to False, execution stops. - * - * The user has the possibility to hook into the assertion through the assertCallback - * callback function. Note though that the callback function must not use any - * functionality of the RTOS, or rely on interrupts being called. Once the function - * returns, it's done. - * - * @ingroup debug - */ - -#ifndef ASSERT_H_ -#define ASSERT_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef DEBUG - -/** Executes when an assertion condition evaluates to false. - * @param filename The name of the current file (normally the __FILE__ macro). - * @param line The current line number (normally the __LINE__ macro). - */ -void fOnAssert(const char *filename, unsigned int line); - -/** Can be assigned to hook into the assertion. */ -extern void (*assertCallback)(const char *filename, unsigned int line); - -#define ASSERT(test) ((test) ? (void)0 : fOnAssert(__FILE__, __LINE__)) - -#define VERIFY(test) ASSERT(test) - -#else - -#define ASSERT(test) ((test) ? (void)0 : 1) - -#define VERIFY(test) ((void)(test)) - -#endif // DEBUG - -#ifdef __cplusplus -} -#endif - -#endif /* ASSERT_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h deleted file mode 100644 index 0f6ab4489d..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - ****************************************************************************** - * @file char_driver.h - * @brief Defines a character driver data type. - * @internal - * @author ON Semiconductor - * $Rev: 2607 $ - * $Date: 2013-12-06 18:02:43 +0530 (Fri, 06 Dec 2013) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @details - * The character driver is intended for devices that allow read and write - * operations with "streams" of data, such as UART devices, SPI or I2c, etc. - * - * The character driver derives from the generic driver template (see driver.h). - * It does so by including an element of the generic driver_t type. - * - * The driver defines blocking and non-blocking read and write operations. It is - * up to the driver implementation to decide which of these to actually implement. - * - * @ingroup char_drivers - */ - -#ifndef CHAR_DRIVER_H_ -#define CHAR_DRIVER_H_ - -#include "driver.h" - -#define DRV_NO_ERROR (True) -#define DRV_ERROR (False) - -/** A character driver structure. */ -typedef struct char_driver { - /** The parent generic driver. */ - driver_t driver; - - /** Blocking read into a buffer. - * @param device The device to read from. - * @param buf The buffer to read into. - * @param len The number of bytes to read. - */ - uint8_t (*read_b)(device_pt device, uint8_t *const buf, uint32_t len); - - /** Non-blocking read into a buffer. - * @param device The device to read from. - * @param buf The buffer to read into. - * @param len The maximum number of bytes to read; typically the size of the buffer. - * @return The number of bytes actually read. - */ - uint32_t (*read_nb)(device_pt device, uint8_t *const buf, uint32_t len); - - /** Blocking write from a buffer. - * @param device The device to write to. - * @param buf The buffer to read from. - * @param len The number of bytes to write; typically the size of the buffer. - * @return success or error message - */ - uint8_t (*write_b)(device_pt device, const uint8_t *buf, uint32_t len); - - /** Non-blocking write from a buffer. - * @param device The device to write to. - * @param buf The buffer to read from. - * @param len The number of bytes to write; typically the size of the buffer. - * @return success or error message - */ - uint8_t (*write_nb)(device_pt device, const uint8_t *buf, uint32_t len); -} char_driver_t, *char_driver_pt; - -#endif /* CHAR_DRIVER_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h deleted file mode 100644 index 000b31362c..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/clock.h +++ /dev/null @@ -1,134 +0,0 @@ -/** -****************************************************************************** -* @file clock.h -* @brief Header of clock hw module functions -* @internal -* @author ON Semiconductor -* $Rev: 3414 $ -* $Date: 2015-06-05 13:27:04 +0530 (Fri, 05 Jun 2015) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup clock -*/ - -#ifndef CLOCK_H_ -#define CLOCK_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "types.h" - -/************************************************************************************************* -* * -* Symbolic Constants * -* * -*************************************************************************************************/ - -/** Peripherals clock disable defines / - * @details - */ -#define CLOCK_TIMER0 (0x0) /**< Timer 0 clock enable offset */ -#define CLOCK_TIMER1 (0x1) /**< Timer 1 clock enable offset : */ -#define CLOCK_TIMER2 (0x2) /**< Timer 2 clock enable offset : */ -#define CLOCK_PAD0_0 (0x3) /**< Unused offset */ -#define CLOCK_PAD0_1 (0x4) /**< Unused offset */ -#define CLOCK_UART1 (0x5) /**< UART 1 clock enable offset */ -#define CLOCK_SPI (0x6) /**< SPI clock enable offset */ -#define CLOCK_I2C (0x7) /**< I2C clock enable offset */ -#define CLOCK_UART2 (0x8) /**< UART 2 clock enable offset */ -#define CLOCK_SPI2 (0x9) /**< Unused offset : */ -#define CLOCK_WDOG (0xA) /**< Watchdog clock enable offset */ -#define CLOCK_PWM (0xB) /**< PWM clock enable offset */ -#define CLOCK_GPIO (0xC) /**< GPIO clock enable offset */ -#define CLOCK_I2C2 (0xD) /**< Unused offset */ -#define CLOCK_PAD2_1 (0xE) /**< Unused offset */ -#define CLOCK_RTC (0xF) /**< RTC clock enable offset */ -#define CLOCK_CROSSB (0x10) /**< Crossbar clock enable offset */ -#define CLOCK_RAND (0x11) /**< Randomizer clock enable offset */ -#define CLOCK_PAD3_0 (0x12) /**< Unused offset */ -#define CLOCK_PAD3_1 (0x13) /**< Unused offset */ -#define CLOCK_MACHW (0x14) /**< macHw clock enable offset */ -#define CLOCK_ADC (0x15) /**< ADC clock enable offset */ -#define CLOCK_AES (0x16) /**< AES clock enable offset */ -#define CLOCK_FLASH (0x17) /**< Flash controller clock enable offset */ -#define CLOCK_PAD4_0 (0x18) /**< Unused offset */ -#define CLOCK_RFANA (0x19) /**< rfAna clock enable offset */ -#define CLOCK_IO (0x1A) /**< IO clock enable offset */ -#define CLOCK_PAD5_0 (0x1B) /**< Unused offset */ -#define CLOCK_PAD (0x1C) /**< Pad clock enable offset */ -#define CLOCK_PMU (0x1D) /**< Pmu clock enable offset */ -#define CLOCK_DMA (0x1E) /**< DMA clock enable offset */ -#define CLOCK_TEST (0x1F) /**< Test controller clock enable offset */ - -#define CLOCK_ENABLE(a) CLOCKREG->PDIS.WORD &= ~(1 << a) -#define CLOCK_DISABLE(a) CLOCKREG->PDIS.WORD |= (uint32_t)(1 << a) -#define CLOCK_IS_ENABLED(a) (((CLOCKREG->PDIS.WORD >> a) & 1)?0:1) - -/************************************************************************************************* -* * -* Functions * -* * -*************************************************************************************************/ - -/** Function to initialize clocks - * @details - * The function initializes clocks. - * This initialization includes: - * - Enable of external 32mHz oscillator - * - Disable of all peripheral clocks (to be turned on selectively when used later in the application) - * - Setting core frequency - */ -void fClockInit(void); - -/** Function to get peripheral clock frequency - * @details - * The function checks and returns peripheral clock frequency - * @return Peripheral clock frequency - */ -uint32_t fClockGetPeriphClockfrequency(); - -/** Function to get peripheral clock frequency - * @details - * The function checks which input clock is sourcing 32kHz clock domain. - * This domain can be either sourced by: - * - Internal 32kHz oscillator - * - External 32.768kHz oscillator - * @return 32kHz clock domain frequency - */ -uint16_t fClockGet32kClockfrequency(); - -/** Function to enable peripheral clock - * @details - * The function enables clock of peripheral indicated by parameter - * @param deviceId Peripheral ID whose clock must be enabled. - */ -void fClockEnablePeriph(uint8_t deviceId); - -/** Function to disable peripheral clock - * @details - * The function disables clock of peripheral indicated by parameter - * @param deviceId ID Peripheral whose clock must be disabled. - */ -void fClockDisablePeriph(uint8_t deviceId); - -#endif /* CLOCK_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h deleted file mode 100644 index caf8777b0b..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h +++ /dev/null @@ -1,151 +0,0 @@ -/** -****************************************************************************** -* @file clock_map.h -* @brief CLOCK hw module register map -* @internal -* @author ON Semiconductor -* $Rev: 2848 $ -* $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup clock -* -* @details -*/ - -#ifndef CLOCK_MAP_H_ -#define CLOCK_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "architecture.h" - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -/** Clock control HW structure overlay */ -typedef struct { - union { - struct { - __IO uint32_t OSC_SEL:1; - __IO uint32_t PAD0:1; - __IO uint32_t CAL32K:1; - __IO uint32_t CAL32M:1; - __IO uint32_t RTCEN:1; - } BITS; - __IO uint32_t WORD; - } CCR; /**< 0x4001B000 Clock control register */ - union { - struct { - __I uint32_t XTAL32M:1; - __I uint32_t XTAL32K:1; - __I uint32_t CAL32K:1; - __I uint32_t DONE32K:1; - __I uint32_t CAL32MFAIL:1; - __I uint32_t CAL32MDONE:1; - } BITS; - __I uint32_t WORD; - } CSR; /**< 0x4001B004 Clock status register */ - union { - struct { - __IO uint32_t IE32K:1; - __IO uint32_t IE32M:1; - } BITS; - __IO uint32_t WORD; - } IER; /**< 0x4001B008 Interrup enable register */ - __IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */ - union { - struct { - __IO uint32_t TIMER0:1; - __IO uint32_t TIMER1:1; - __IO uint32_t TIMER2:1; - __IO uint32_t PAD0:2; - __IO uint32_t UART1:1; - __IO uint32_t SPI:1; - __IO uint32_t I2C:1; - __IO uint32_t UART2:1; - __IO uint32_t PAD1:1; - __IO uint32_t WDOG:1; - __IO uint32_t PWM:1; - __IO uint32_t GPIO:1; - __IO uint32_t PAD2:2; - __IO uint32_t RTC:1; - __IO uint32_t XBAR:1; - __IO uint32_t RAND:1; - __IO uint32_t PAD3:2; - __IO uint32_t MACHW:1; - __IO uint32_t ADC:1; - __IO uint32_t AES:1; - __IO uint32_t FLASH:1; - __IO uint32_t PAD4:1; - __IO uint32_t RFANA:1; - __IO uint32_t IO:1; - __IO uint32_t PAD5:1; - __IO uint32_t PAD:1; - __IO uint32_t PMU:1; - __IO uint32_t PAD6:1; - __IO uint32_t TEST:1; - } BITS; - __IO uint32_t WORD; - } PDIS; /**< 0x4001B010 Periphery disable */ - __IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */ - __IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */ - __IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */ - __IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */ - __IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */ - union { - struct { - __IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */ - __IO uint32_t BOOST :2; /* Boost done signal tap control */ - __IO uint32_t READY :2; /* Ready signal tap control */ - __IO uint32_t GAIN_MODE :2; /* Gain Mode */ - __IO uint32_t PAD :20; /* Unused bits */ - } BITS; - __IO uint32_t WORD; - } TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */ - - union { - struct { - __IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */ - __IO uint32_t BOOST :2; /* Boost done signal tap control */ - __IO uint32_t READY :2; /* Ready signal tap control */ - __IO uint32_t GAIN_MODE :2; /* Gain Mode */ - __IO uint32_t PAD :20; /* Unused bits */ - } BITS; - __IO uint32_t WORD; - } TRIM_32K_EXT; - union { - struct { - __IO uint32_t OV32M; - __IO uint32_t EN32M; - __IO uint32_t OV32K; - __IO uint32_t EN32K; - } BITS; - __IO uint32_t WORD; - } CER; /**< 0x4001B038 clock enable register*/ -} ClockReg_t, *ClockReg_pt; - -#endif /* CLOCK_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h deleted file mode 100644 index 127944dd99..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar.h +++ /dev/null @@ -1,51 +0,0 @@ -/** -****************************************************************************** -* @file crossbar.h -* @brief CROSSBAR hw module register map -* @internal -* @author ON Semiconductor -* $Rev: 2033 $ -* $Date: 2013-06-28 17:12:31 +0200 (Fri, 28 Jun 2013) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup crossbar -* -* @details -* Defines magic numbers for the different peripheral devices. -*/ - -#ifndef _CROSSBAR_H_ -#define _CROSSBAR_H_ - -/************************************************************************************************* -* * -* Symbolic Constants * -* * -*************************************************************************************************/ - -#define CONFIGURE_AS_GPIO (uint8_t)0x00 -#define CONFIGURE_AS_RESERVED_0 (uint8_t)0x01 -#define CONFIGURE_AS_RESERVED_1 (uint8_t)0x02 -#define CONFIGURE_AS_RESERVED_2 (uint8_t)0x03 -#define CONFIGURE_AS_PWM (uint8_t)0x04 -#define CONFIGURE_AS_I2C (uint8_t)0x05 -#define CONFIGURE_AS_SPI (uint8_t)0x06 -#define CONFIGURE_AS_UART (uint8_t)0x07 - -#endif //_CROSSBAR_H_ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h deleted file mode 100644 index 4f1f89c60a..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h +++ /dev/null @@ -1,71 +0,0 @@ -/** -****************************************************************************** -* @file crossbar_map.h -* @brief CROSSBAR hw module register map -* @internal -* @author ON Semiconductor -* $Rev: 3318 $ -* $Date: 2015-03-27 16:29:34 +0530 (Fri, 27 Mar 2015) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup crossbar -* -* @details -*/ - -#ifndef CROSSB_MAP_H_ -#define CROSSB_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "architecture.h" - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -/* Crossbar Control HW Structure Overlay */ -typedef struct { - __IO uint32_t DIOCTRL0; /**< Switch IO0 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL1; /**< Switch IO1 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL2; /**< Switch IO2 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL3; /**< Switch IO3 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL4; /**< Switch IO4 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL5; /**< Switch IO5 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL6; /**< Switch IO6 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL7; /**< Switch IO7 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL8; /**< Switch IO8 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL9; /**< Switch IO9 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL10; /**< Switch IO10 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL11; /**< Switch IO11 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL12; /**< Switch IO12 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL13; /**< Switch IO13 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL14; /**< Switch IO14 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL15; /**< Switch IO15 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL16; /**< Switch IO16 to GPIO(default) or peripheral device */ - __IO uint32_t DIOCTRL17; /**< Switch IO17 to GPIO(default) or peripheral device */ -} CrossbReg_t, *CrossbReg_pt; - -#endif /* CROSSB_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/device.h deleted file mode 100644 index 1dd9b649de..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - ****************************************************************************** - * @file Device.h - * @brief Implements an assertion. - * @internal - * @author ON Semiconductor - * $Rev: 0.1 $ - * $Date: 2015-11-06 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup debug - */ -#ifndef DEVICE_H_ -#define DEVICE_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "objects.h" - -#ifdef __cplusplus -} -#endif - - -#endif /* DEVICE_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h deleted file mode 100644 index 9ae2a1cbfa..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************/ -/** - * @file NCS36510.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * for CM3 Device Series - * @version V1.05 - * @date 26. July 2011 - * - * @note - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef ARMCM3_H -#define ARMCM3_H - -/** - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ -typedef enum IRQn { - /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - - /****** ARMCM3 specific Interrupt Numbers ********************************************************/ - Tim0_IRQn = 0, - Tim1_IRQn = 1, - Tim2_IRQn = 2, - Uart1_IRQn = 3, - Spi_IRQn = 4, - I2C_IRQn = 5, - Gpio_IRQn = 6, - Rtc_IRQn = 7, - Flash_IRQn = 8, - MacHw_IRQn = 9, - Aes_IRQn = 10, - Adc_IRQn = 11, - ClockCal_IRQn = 12, - Uart2_IRQn = 13, - Uvi_IRQn = 14, - Dma_IRQn = 15, - DbgPwrUp_IRQn = 16, - Spi2_IRQn = 17, - I2C2_IRQn = 18, - FVDDHComp_IRQn = 19 -} IRQn_Type; - -/** - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/** Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __CM3_REV 0x0201 /*!< Core Revision r2p1 */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -//#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER) - -#include /* Cortex-M3 processor and core peripherals */ -#include "system_NCS36510.h" /* System Header */ - -#endif /* ARMCM3_H */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/NCS36510.sct b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/NCS36510.sct deleted file mode 100644 index fe6c48028f..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/NCS36510.sct +++ /dev/null @@ -1,26 +0,0 @@ -#! armcc -E - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x00003000 0x0004F000 { ; load region size_region - ER_IROM1 0x00003000 0x0004F000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (*) - } - - - RW_IRAM1 0x3FFF4000 + 0x90 { ; 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 - .ANY(+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 8) ALIGN 8 EMPTY (0x3FFF4000 + 0xC000 - AlignExpr(ImageLimit(RW_IRAM1),8) - Stack_Size) { - } - - ARM_LIB_STACK 0x3FFF4000 + 0xC000 EMPTY -Stack_Size { ; stack - } -} diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.S b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.S deleted file mode 100644 index 4d9a529050..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.S +++ /dev/null @@ -1,197 +0,0 @@ -;/* File: startup_ncs36510.s -; * Purpose: startup file for Cortex-M3 devices. Should use with -; * ARMGCC for ARM Embedded Processors -; * Version: V2.00 -; * Date: 25 Feb 2016 -; * -; */ -;/* Copyright (c) 2011 - 2014 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0x3000 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of RAM - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD fIrqTim0Handler - DCD fIrqTim1Handler - DCD fIrqTim2Handler - DCD fIrqUart1Handler - DCD fIrqSpiHandler - DCD fIrqI2CHandler - DCD fIrqGpioHandler - DCD fIrqRtcHandler - DCD fIrqFlashHandler - DCD fIrqMacHwHandler - DCD fIrqAesHandler - DCD fIrqAdcHandler - DCD fIrqClockCalHandler - DCD fIrqUart2Handler - DCD fIrqUviHandler - DCD fIrqDmaHandler - DCD fIrqDbgPwrUpHandler - DCD fIrqSpi2Handler - DCD fIrqI2C2Handler - DCD fIrqFVDDHCompHandler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT fIrqTim0Handler [WEAK] - EXPORT fIrqTim1Handler [WEAK] - EXPORT fIrqTim2Handler [WEAK] - EXPORT fIrqUart1Handler [WEAK] - EXPORT fIrqSpiHandler [WEAK] - EXPORT fIrqI2CHandler [WEAK] - EXPORT fIrqGpioHandler [WEAK] - EXPORT fIrqRtcHandler [WEAK] - EXPORT fIrqFlashHandler [WEAK] - EXPORT fIrqMacHwHandler [WEAK] - EXPORT fIrqAesHandler [WEAK] - EXPORT fIrqAdcHandler [WEAK] - EXPORT fIrqClockCalHandler [WEAK] - EXPORT fIrqUart2Handler [WEAK] - EXPORT fIrqUviHandler [WEAK] - EXPORT fIrqDmaHandler [WEAK] - EXPORT fIrqDbgPwrUpHandler [WEAK] - EXPORT fIrqSpi2Handler [WEAK] - EXPORT fIrqI2C2Handler [WEAK] - EXPORT fIrqFVDDHCompHandler [WEAK] - -fIrqTim0Handler -fIrqTim1Handler -fIrqTim2Handler -fIrqUart1Handler -fIrqSpiHandler -fIrqI2CHandler -fIrqGpioHandler -fIrqRtcHandler -fIrqFlashHandler -fIrqMacHwHandler -fIrqAesHandler -fIrqAdcHandler -fIrqClockCalHandler -fIrqUart2Handler -fIrqUviHandler -fIrqDmaHandler -fIrqDbgPwrUpHandler -fIrqSpi2Handler -fIrqI2C2Handler -fIrqFVDDHCompHandler -DefaultISR - - B . - - ENDP - - END diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld deleted file mode 100644 index 273226105e..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld +++ /dev/null @@ -1,186 +0,0 @@ -/* - * NCS36510 ARM GCC linker script file - */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -MEMORY { - FIB (rx) : ORIGIN = 0x00002000, LENGTH = 0x00000800 - TRIM (rx) : ORIGIN = 0x00002800, LENGTH = 0x00000800 - VECTORS (rx) : ORIGIN = 0x00003000, LENGTH = 0x00000090 - FLASH (rx) : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90 - RAM (rwx) : ORIGIN = 0x3FFF4090, LENGTH = 48K - 0x90 /* 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 */ -} - - /* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * _reset_init : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ - ENTRY(Reset_Handler) - - SECTIONS { - .fib : - { - KEEP(*(.fib)) - } > FIB - - .trim : - { - KEEP(*(.trim)) - } > TRIM - - .isr_vector : - { - __vector_table = .; - KEEP(*(.vector_table)) - . = ALIGN(8); - } > VECTORS - - -.text : - { - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - -.ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - -.ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > FLASH - -.data : - { - PROVIDE( __etext = LOADADDR(.data) ); - - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - /* All data end */ - . = ALIGN(32); - __data_end__ = .; - - } >RAM AT>FLASH - - - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss (NOLOAD): - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - *(.heap*); - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - PROVIDE(__heap_size = SIZEOF(.heap)); - PROVIDE(__mbed_sbrk_start = ADDR(.heap)); - PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap)); - - /* .stack section doesn't contains any symbols. It is only - * used for linker to reserve space for the main stack section - * WARNING: .stack should come immediately after the last secure memory - * section. This provides stack overflow detection. */ - .stack (NOLOAD): - { - __StackLimit = .; - *(.stack*); - . += STACK_SIZE - (. - __StackLimit); - } > RAM - - /* Set stack top to end of RAM */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - -} diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.S b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.S deleted file mode 100644 index 45771e7dfb..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.S +++ /dev/null @@ -1,209 +0,0 @@ -/* File: startup_ncs36510.S - * Purpose: startup file for Cortex-M3 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V2.00 - * Date: 15 Jan 2016 - * - */ -/* Copyright (c) 2011 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -.syntax unified -.arch armv7-m - -.section .stack -.align 3 -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x400 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -.section .heap -.align 3 -#ifdef __HEAP_SIZE -.equ Heap_Size, __HEAP_SIZE -#else -.equ Heap_Size, 0x400 -#endif -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.space Heap_Size -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - -.section .vector_table,"a",%progbits -.align 2 -.globl __Vectors -__Vectors: -.long __StackTop /* Top of Stack */ -.long Reset_Handler /* Reset Handler */ -.long NMI_Handler /* NMI Handler */ -.long HardFault_Handler /* Hard Fault Handler */ -.long MemManage_Handler /* MPU Fault Handler */ -.long BusFault_Handler /* Bus Fault Handler */ -.long UsageFault_Handler /* Usage Fault Handler */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long SVC_Handler /* SVCall Handler */ -.long DebugMon_Handler /* Debug Monitor Handler */ -.long 0 /* Reserved */ -.long PendSV_Handler /* PendSV Handler */ -.long SysTick_Handler /* SysTick Handler */ - -/* External Interrupts */ -.long fIrqTim0Handler -.long fIrqTim1Handler -.long fIrqTim2Handler -.long fIrqUart1Handler -.long fIrqSpiHandler -.long fIrqI2CHandler -.long fIrqGpioHandler -.long fIrqRtcHandler -.long fIrqFlashHandler -.long fIrqMacHwHandler -.long fIrqAesHandler -.long fIrqAdcHandler -.long fIrqClockCalHandler -.long fIrqUart2Handler -.long fIrqUviHandler -.long fIrqDmaHandler -.long fIrqDbgPwrUpHandler -.long fIrqSpi2Handler -.long fIrqI2C2Handler -.long fIrqFVDDHCompHandler - -.size __Vectors, . - __Vectors - -.section .text.Reset_Handler -.thumb -.thumb_func -.align 2 -.globl Reset_Handler -.type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges -* of copy from/to are specified by following symbols evaluated in -* linker script. -* __etext: End of code section, i.e., begin of data sections to copy from. -* __data_start__/__data_end__: RAM address range that data should be -* copied to. Both must be aligned to 4 bytes boundary. */ - -disable_watchdog: -/*MPL - Need to implement?! */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler -* will be weak symbol and just dead loops. They can be -* overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - -/* Exception Handlers */ - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - -/* IRQ Handlers */ - def_irq_default_handler fIrqTim0Handler - def_irq_default_handler fIrqTim1Handler - def_irq_default_handler fIrqTim2Handler - def_irq_default_handler fIrqUart1Handler - def_irq_default_handler fIrqSpiHandler - def_irq_default_handler fIrqI2CHandler - def_irq_default_handler fIrqGpioHandler - def_irq_default_handler fIrqRtcHandler - def_irq_default_handler fIrqFlashHandler - def_irq_default_handler fIrqMacHwHandler - def_irq_default_handler fIrqAesHandler - def_irq_default_handler fIrqAdcHandler - def_irq_default_handler fIrqClockCalHandler - def_irq_default_handler fIrqUart2Handler - def_irq_default_handler fIrqUviHandler - def_irq_default_handler fIrqDmaHandler - def_irq_default_handler fIrqDbgPwrUpHandler - def_irq_default_handler fIrqSpi2Handler - def_irq_default_handler fIrqI2C2Handler - def_irq_default_handler fIrqFVDDHCompHandler - def_irq_default_handler DefaultISR - - .end diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf deleted file mode 100644 index 4a4275752a..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf +++ /dev/null @@ -1,85 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_1.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00003000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_IROM1_start__ = 0x00003000; /* FLASHA program start*/ -define symbol __ICFEDIT_region_IROM1_end__ = 0x00051FFF; /* 316K = 320K - 4K(FIB table), FLASHA end */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x00102000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x00151FFF; /* 320K */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x0; -define symbol __ICFEDIT_region_EROM1_end__ = 0x0; -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - -define symbol __ICFEDIT_region_IRAM1_start__ = 0x3FFFC000; /* RAMA start */ -define symbol __ICFEDIT_region_IRAM1_end__ = 0x3FFFFFFF; /* RAMA end */ -define symbol __ICFEDIT_region_IRAM2_start__ = 0x3FFF8000; /* RAMB start */ -define symbol __ICFEDIT_region_IRAM2_end__ = 0x3FFFBFFF; /* RAMB end */ -define symbol __ICFEDIT_region_IRAM3_start__ = 0x3FFF4000; /* RAMC start */ -define symbol __ICFEDIT_region_IRAM3_end__ = 0x3FFF7FFF; /* RAMC end */ -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; - -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x4000; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region FLASH_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] - | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; - -define region RAM_VECTOR_region = mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_start__ + 0x90 - 1]; - -define region RAM_region = mem:[from __ICFEDIT_region_IRAM3_start__ + 0x90 to __ICFEDIT_region_IRAM3_end__] - | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__] - | mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__ - __ICFEDIT_size_cstack__ ]; - -define region CSTACK_region = mem:[from __ICFEDIT_region_IRAM1_end__ - __ICFEDIT_size_cstack__ + 1 to __ICFEDIT_region_IRAM1_end__]; - - -/* Define overlays for MIB's, ths allows view of one MIB from a application level while - * MAC and PHY only know about their own MIB */ -define overlay MIBOVERLAY { section MIBSTARTSECTION }; -define overlay MIBOVERLAY { section MIBSECTION }; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block RAM_VECTORS with alignment = 8, size = 0x90 { }; - -initialize by copy { readwrite }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - // Required in a multi-threaded application - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -/* Initialize the code in RAM, copied over from FLASH */ -initialize by copy with packing = none { readonly code section EXECINRAM }; - -/*initialize by copy { readwrite };*/ -do not initialize { section .noinit }; - - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec, readonly section SWVERSION, readonly section FIBTABLE }; - -place in FLASH_region { readonly section .cstartup, readonly }; - -place at start of RAM_VECTOR_region {block RAM_VECTORS}; - -place in RAM_region { readwrite, block HEAP, section XHEAP, readonly code section EXECINRAM, overlay MIBOVERLAY, readwrite section MIBENDSECTION}; - -place at end of CSTACK_region { block CSTACK }; diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.S b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.S deleted file mode 100644 index e3a7ab075c..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.S +++ /dev/null @@ -1,310 +0,0 @@ -;/****************************************************************************** -; * @file startup_ARMCM3.s -; * @brief CMSIS Cortex-M4 Core Device Startup File -; * for CM3 Device Series -; * @version V1.05 -; * @date 25. July 2011 -; * -; * @note -; * Copyright (C) 2010-2011 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN fInitSource - EXTERN HardFault_Handler - EXTERN SVC_Handler - EXTERN PendSV_Handler - EXTERN SysTick_Handler - EXTERN fIrqTim0Handler - EXTERN fIrqTim1Handler - EXTERN fIrqTim2Handler - EXTERN fIrqGpioHandler - EXTERN fIrqSpiHandler - EXTERN fIrqUart1Handler - EXTERN fIrqUart2Handler - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler -#ifndef RAM_VECTOR_TABLE - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -#endif -__vector_table_0x1c -#ifndef RAM_VECTOR_TABLE - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD fIrqTim0Handler - DCD fIrqTim1Handler - DCD fIrqTim2Handler - DCD fIrqUart1Handler - DCD fIrqSpiHandler - DCD fIrqI2CHandler - DCD fIrqGpioHandler - DCD fIrqRtcHandler - DCD fIrqFlashHandler - DCD fIrqMacHwHandler - DCD fIrqAesHandler - DCD fIrqAdcHandler - DCD fIrqClockCalHandler - DCD fIrqUart2Handler - DCD fIrqUviHandler - DCD fIrqDmaHandler - DCD fIrqDbgPwrUpHandler - /* REV C/D interrupts */ - DCD fIrqSpi2Handler - DCD fIrqI2c2Handler - DCD FIrqFVDDHCompHandler /* FVDDH Supply Comparator Trip */ -#endif -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -opt: DC32 0x2082353F /* Full featured device */ -opt_reg: DC32 0x4001E000 -enable: DC32 0x00000000 -per_en: DC32 0x4001B010 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - -;; Taken from article http://netstorage.iar.com/SuppDB/Public/UPDINFO/007040/arm/doc/infocenter/ilinkarm.ENU.html -;; If this line is removed, veneers for functions copied into RAM are flasely also placed in RAM, but are NOT -;; copied into it by __iar_copy_init3 -__iar_init$$done - - PUBLIC Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0,= enable ;; load R0 with address of enable - LDR R0,[R0] ;; load R0 with what address R0 points to - LDR R1,= per_en ;; load R1 with address of per_en - LDR R1,[R1] ;; load R1 with what address R1 points to - STR R0,[R1] ;; store R0 into address pointed to by R1 /* Disable all peripherals */ - - LDR R0,= opt ;; load R0 with address of opt - LDR R0,[R0] ;; load R0 with what address R0 points to - LDR R1,= opt_reg ;; load R1 with address of opt_reg - LDR R1,[R1] ;; load R1 with what address R1 points to - STR R0, [R1] ;; store R0 into address pointed to by R1 /* Device option: Full featured device */ - - LDR R0,= sfe(CSTACK) - MOV SP,R0 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - -; PUBWEAK HardFault_Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;HardFault_Handler -; B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - -; PUBWEAK vPortSVCHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;vPortSVCHandler -; B vPortSVCHandler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - -; PUBWEAK xPortPendSVHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;xPortPendSVHandler -; B xPortPendSVHandler - -; PUBWEAK SysTick_Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;SysTick_Handler -; B SysTick_Handler - - -; PUBWEAK fIrqTim0Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqTim0Handler -; B fIrqTim0Handler - -; PUBWEAK fIrqTim1Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqTim1Handler -; B fIrqTim1Handler - -; PUBWEAK fIrqTim2Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqTim2Handler -; B fIrqTim2Handler - -; PUBWEAK fIrqUart1Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqUart1Handler -; B fIrqUart1Handler - -; PUBWEAK fIrqSpiHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqSpiHandler -; B fIrqSpiHandler - - PUBWEAK fIrqI2CHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqI2CHandler - B fIrqI2CHandler - -; PUBWEAK fIrqGpioHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqGpioHandler -; B fIrqGpioHandler - - PUBWEAK fIrqRtcHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqRtcHandler - B fIrqRtcHandler - - PUBWEAK fIrqFlashHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqFlashHandler - B fIrqFlashHandler - - PUBWEAK fIrqMacHwHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqMacHwHandler - B fIrqMacHwHandler - - PUBWEAK fIrqAesHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqAesHandler - B fIrqAesHandler - - PUBWEAK fIrqAdcHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqAdcHandler - B fIrqAdcHandler - - PUBWEAK fIrqClockCalHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqClockCalHandler - B fIrqClockCalHandler - -; PUBWEAK fIrqUart2Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqUart2Handler -; B fIrqUart2Handler - - PUBWEAK fIrqDbgPwrUpHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqDbgPwrUpHandler - B fIrqDbgPwrUpHandler - - PUBWEAK fIrqDmaHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqDmaHandler - B fIrqDmaHandler - - PUBWEAK fIrqUviHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqUviHandler - B fIrqUviHandler - - PUBWEAK fIrqSpi2Handler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqSpi2Handler - B fIrqSpi2Handler - - PUBWEAK fIrqI2c2Handler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqI2c2Handler - B fIrqI2c2Handler - - PUBWEAK FIrqFVDDHCompHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FIrqFVDDHCompHandler - B FIrqFVDDHCompHandler - - PUBWEAK DEF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DEF_IRQHandler - B DEF_IRQHandler - - END diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis.h deleted file mode 100644 index 8b388a2b4f..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * PackageLicenseDeclared: Apache-2.0 - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* mbed Microcontroller Library - CMSIS - * - * A generic CMSIS include header, pulling in K64F specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "NCS36510.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.h deleted file mode 100644 index 665638b571..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.h +++ /dev/null @@ -1,33 +0,0 @@ -/** -****************************************************************************** -* @file cmsis_nvic.h -* @brief Contains relocatable exception table. -* @internal -* @author ON Semiconductor. -* $Rev: 0.1 $ -* $Date: 2015-11-06 $ -****************************************************************************** -* Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductorâ€). -* All rights reserved. This software and/or documentation is licensed by ON Semiconductor -* under limited terms and conditions. The terms and conditions pertaining to the software -* and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf -* (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Softwareâ€) and -* if applicable the software license agreement. Do not use this software and/or -* documentation unless you have carefully read and you agree to the limited terms and -* conditions. By using this software and/or documentation, you agree to the limited -* terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup -* -* @details -*/ - -#define NVIC_NUM_VECTORS (16 + 20) -#define NVIC_RAM_VECTOR_ADDRESS 0x3FFF4000 // Vectors positioned at start of RAM diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.c deleted file mode 100644 index f12bfb6210..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.c +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************//** - * @file system_NCS36510.c - * @brief CMSIS Cortex-M3 Device System Source File - * for CM3 Device Series - * @version V1.05 - * @date 26. July 2011 - * - * @note - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include -#include "ncs36510Init.h" -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __HSI ( 8000000UL) -#define __XTAL (32769000UL) /* Oscillator frequency */ - -/** Value initialized here*/ -#define __SYSTEM_CLOCK (32000000) - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - /*Function not implimented */ - SystemCoreClock = __SYSTEM_CLOCK; -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ - - SystemCoreClock = __SYSTEM_CLOCK; - - fNcs36510Init(); -} diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.h deleted file mode 100644 index f5dd20864d..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/system_NCS36510.h +++ /dev/null @@ -1,62 +0,0 @@ -/**************************************************************************//** - * @file system_NCS36510.h - * @brief CMSIS Cortex-M3 Device System Header File - * for CM3 Device Series - * @version V1.05 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef SYSTEM_ARMCM3_H -#define SYSTEM_ARMCM3_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_ARMCM3_H */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h deleted file mode 100644 index db396a7df3..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h +++ /dev/null @@ -1,94 +0,0 @@ -/** -****************************************************************************** -* @file dma_map.h -* @brief DMA hw module register map -* @internal -* @author ON Semiconductor -* $Rev: 3415 $ -* $Date: 2015-06-05 13:29:52 +0530 (Fri, 05 Jun 2015) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup dma -* -* @details -*/ - -#ifndef DMA_MAP_H_ -#define DMA_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "architecture.h" - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -/** DMA control HW registers structure overlay */ -typedef struct { - union { - struct { - __IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */ - __IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */ - } BITS; - __IO uint32_t WORD; - } CONTROL; /**< Control register */ - __IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */ - __IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */ - __IO uint32_t SIZE; /**< Lenght of the entire transfer */ - union { - struct { - __I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */ - __I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */ - __I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */ - } BITS; - __I uint32_t WORD; - } STATUS; /**< Status register */ - union { - struct { - __IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */ - __IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */ - __IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */ - } BITS; - __IO uint32_t WORD; - } INT_ENABLE; /**< Interrupt enable */ - union { - struct { - __IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */ - __IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */ - __IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */ - } BITS; - __IO uint32_t WORD; - } INT_CLEAR; /**< Interrupt clear */ - union { - struct { - __I uint32_t COMPLETED:1; /**< Transfer complete interrupt */ - __I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */ - __I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */ - } BITS; - __I uint32_t WORD; - } INT_STATUS; /**< Interrupt status */ -} DmaReg_t, *DmaReg_pt; -#endif /* DMA_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/error.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/error.h deleted file mode 100644 index 1c33cc3ea4..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/error.h +++ /dev/null @@ -1,38 +0,0 @@ -/** - ****************************************************************************** - * @file error.h - * @brief Defines an error data type, which can be used for error codes or return values. - * @internal - * @author ON Semiconductor - * $Rev: 2074 $ - * $Date: 2013-07-10 18:06:15 +0530 (Wed, 10 Jul 2013) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup util - */ - -#ifndef ERROR_H_ -#define ERROR_H_ - -#include - -typedef uint8_t error; -#define NO_ERROR (0xFF) - -#endif /* ERROR_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c deleted file mode 100644 index cf33119d9b..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c +++ /dev/null @@ -1,156 +0,0 @@ -/** -****************************************************************************** -* @file exceptions.c -* @brief Contains relocatable exception table. -* @internal -* @author ON Semiconductor -* $Rev: 2074 $ -* $Date: 2013-07-10 14:36:15 +0200 (Wed, 10 Jul 2013) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup app -* -* @details -*/ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -/* BSP inclusions */ -#include "device.h" -#include "uart_16c550.h" - -#include "memory_map.h" -#include "timer_ncs36510.h" - -/* Other inclusions */ -#include "types.h" - - -#include "rtc.h" -#include "gpio.h" -#include "uart_16c550.h" - -/************************************************************************************************* -* * -* Externally declarewd functions * -* * -*************************************************************************************************/ -extern void fSysTickHandler(void); -/************************************************************************************************* -* * -* Functions * -* * -*************************************************************************************************/ - -/** Not implemented exception, exception handler */ -void NotImplemented_Handler(void) -{ - while (1) {}; -} - -/************************************************************************************************* -* * -* Functions * -* * -*************************************************************************************************/ -/** MacHw IRQ handler implemented in the RF driver stack */ - -/** Call the Timer0 IRQ handler */ -void fIrqTim0Handler() -{ - us_timer_isr(); -} - -/** Call the Timer1 IRQ handler */ -void fIrqTim1Handler() -{ - us_ticker_isr(); -} - -/** Call the Timer2 IRQ handler */ -void fIrqTim2Handler() -{ - NotImplemented_Handler(); -} - -/** Call the Gpio IRQ handler */ -void fIrqGpioHandler() -{ - fGpioHandler(); -} - -/** Call the Spi IRQ handler */ -void fIrqSpiHandler() -{ - NotImplemented_Handler(); -} - -/** Call the Uart 1 IRQ handler */ -void fIrqUart1Handler(void) -{ - Uart1_Irq(); -} - -/** Call the Uart 2 IRQ handler */ -void fIrqUart2Handler(void) -{ - Uart2_Irq(); -} - -#if DEVICE_RTC -/** Call the RTC IRQ handler */ -void fIrqRtcHandler(void) -{ - fRtcHandler(); -} -#endif - -/** Call the I2C IRQ handler */ -void fIrqI2CHandler(void) -{ - NotImplemented_Handler(); -} - -/** Call the I2c2 IRQ handler */ -void fIrqI2C2Handler(void) -{ - NotImplemented_Handler(); -} - -/** Call the Spi2 IRQ handler */ -void fIrqSpi2Handler(void) -{ - NotImplemented_Handler(); -} - -/** Call the UVI IRQ handler */ -void fIrqUviHandler(void) -{ - NotImplemented_Handler(); -} - -/** Call the ADC handler */ -void fIrqAdcHandler(void) -{ - NotImplemented_Handler(); -} diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/fib.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/fib.h deleted file mode 100644 index fb7a400fdf..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/fib.h +++ /dev/null @@ -1,49 +0,0 @@ -/** -****************************************************************************** -* @file sys.h -* @brief Defines a FIB (Firmware Information Base) -* @internal -* @author ON Semiconductor -* $Rev: 2074 $ -* $Date: 2013-07-10 14:36:15 +0200 (Wed, 10 Jul 2013) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup sys -* -* @details -* -*/ - -#ifndef FIB_H_ -#define FIB_H_ - -#include "mib.h" -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -typedef struct { - unsigned int fwbase_address; - mib_systemRevision_t fw_version; -} fibtable_t; - - -#endif \ No newline at end of file diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h deleted file mode 100644 index 35df77ffb8..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/flash_map.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - ****************************************************************************** - * @file flash_map.h - * @brief Flash controller HW register map - * @internal - * @author ON Semiconductor - * $Rev: 2686 $ - * $Date: 2014-01-23 13:31:54 +0530 (Thu, 23 Jan 2014) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup flash - * - * @details - *

- * Flash controller HW register map description - *

- * - */ -#ifndef FLASH_MAP_H_ -#define FLASH_MAP_H_ - -#include "architecture.h" - -/** Flash Control HW Structure Overlay */ -typedef struct { - union { - struct { - __I uint32_t FLASH_A_BUSY:1; /**< Busy A */ - __I uint32_t FLASH_B_BUSY:1; /**< Busy B */ - __I uint32_t FLASH_A_UNLOCK:1; /**< Unlock A */ - __I uint32_t FLASH_B_UNLOCK:1; /**< Unlock B */ - __I uint32_t FLASH_ERROR:3; /**< 000 – No Error, 111 – Attempt to access an array while it is busy powering up, 001 – Attempt to erase bootloader in the field, 010 – Attempt to access array during erase, 100 – Attempt to access array during write */ - } BITS; - __I uint32_t WORD; - } STATUS; - union { - struct { - __IO uint32_t FLASHB_PD:1; - __IO uint32_t FLASHA_PD:1; - __IO uint32_t REMAP:1; - __IO uint32_t WR_INT_EN:1; - __IO uint32_t ERASE_INT_EN:1; - __IO uint32_t ERROR_INT_EN:1; - __IO uint32_t WRITE_BLOCK:1; - } BITS; - __IO uint32_t WORD; - } CONTROL; - union { - struct { - __IO uint32_t PAGEERASE:1; /**< Erase a single page */ - __IO uint32_t MASSERASE:1; /**< MASS Erase */ - } BITS; - __IO uint32_t WORD; - } COMMAND; - __IO uint32_t ADDR; - __IO uint32_t UNLOCK1; - __IO uint32_t UNLOCKA; - __IO uint32_t UNLOCKB; - union { - struct { - __I uint32_t INT_PEND:1; // Interrupt pending - __I uint32_t INT_TYPE:3; // Interrupt type - } BITS; - __I uint32_t WORD; - } INT_STATUS; -} FlashReg_t, *FlashReg_pt; - -#endif /* FLASH_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/fncs36510_sleep.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/fncs36510_sleep.h deleted file mode 100644 index 44c2019927..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/fncs36510_sleep.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - ******************************************************************************* - * @file sleep.c - * @brief Implementation of a sleep functionality - * @internal - * @author ON Semiconductor - * $Rev: $ - * $Date: $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup sleep - * - * @details - * Sleep implementation TBD - Dummy function is fine for first release - * - */ - -#ifndef SLEEP_H_ -#define SLEEP_H_ - -/* Orion specific includes */ -#include "types.h" -#include "memory_map.h" -#include "gpio_map.h" -#include "pad_map.h" -#include "crossbar.h" -#include "clock.h" - -#define SLEEP_TYPE_NONE 0 -#define SLEEP_TYPE_SLEEP 1 -#define SLEEP_TYPE_DEEPSLEEP 2 -#define SLEEP_TYPE_COMA 3 - -#define SLEEP_TYPE_DEFAULT SLEEP_TYPE_DEEPSLEEP - -#define SLEEP_DURATION_SLEEP_MIN 10 /* msec */ -#define SLEEP_DURATION_SLEEP_MAX 200 /* msec */ -#define SLEEP_DURATION_DEEPSLEEP_MAX 500 /* msec */ -#define SLEEP_DURATION_COMA_MAX 1000000000 /* TODO 1000 sec */ - -void fncs36510_sleep(void); - -void fncs36510_deepsleep(void); - -void fncs36510_coma(void); - -#endif // SLEEP_H_ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h deleted file mode 100644 index e10facf61b..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - ****************************************************************************** - * @file gpio.h - * @brief (API) Public header of GPIO driver - * @internal - * @author ON Semiconductor - * $Rev: 3724 $ - * $Date: 2015-09-14 14:35:42 +0530 (Mon, 14 Sep 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup gpio - * - * @details - * - *

General description

- *

- * The APB GPIO is a configurable module allowing the use of 14 I/O lines. - * Each line can be configured independently. - * The GPIO module supports a wide variety of features concerning interrupts, - * which can be triggered by a low level, high level, positive or negative edge, - * or both edges. - *

- * - */ - -#ifndef GPIO_H_ -#define GPIO_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "memory_map.h" -#include "gpio_map.h" -#include "pad_map.h" -#include "crossbar.h" -#include "clock.h" -#include "pad.h" - - -/** output configuration push/pull */ -#define PAD_OUTCFG_PUSHPULL (uint8_t)0x00 - -/** output configuration open drain */ -#define PAD_OOUTCFG_OPENDRAIN (uint8_t)0x01 - -/** no pull up nor pull down */ -#define PAD_PULL_NONE (uint8_t)0x01 - -/** pull down */ -#define PAD_PULL_DOWN (uint8_t)0x00 - -/** pull up */ -#define PAD_PULL_UP (uint8_t)0x03 - -/* Number of DIO lines supported by NCS36510 */ -#define NUMBER_OF_GPIO ((uint8_t)0x12) - -/* All DIO lines set to 1 */ -#define IO_ALL ((uint32_t)0x3FFFF) -#define IO_NONE ((uint32_t)0x00000) - -/* Gpio handler */ -void fGpioHandler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* GPIO_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c deleted file mode 100644 index 45d759e166..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/** - ****************************************************************************** - * @file gpio_api.c - * @brief Implementation of a GPIO driver - * @internal - * @author ON Semiconductor - * $Rev: - * $Date: 2015-11-04 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup gpio - * - * @details - * - * @internal - *

Reference document(s)

- *

- * Reference document: IPC7203 APB GPIO Design Specification v1.2 - *

- * @endinternal - * - *

Functional description (internal)

- *

- * Each GPIO line can be independently programmed as an input or an output. Separate Set - * and Clear registers are provided since it is likely that different software tasks may be - * servicing different I/O signals. Inputs are synchronized to the system clock - * through a pair of flip-flops. Each input can be programmed - * to cause an interrupt to be generated. The interrupt can be programmed to be level-sensitive - * or edge-sensitive and the level (high or low) or edge (rising, falling or either) that causes - * the interrupt can be selected. Interrupts can be individually enabled or disabled. - * Level-sensitive interrupts stay asserted until the interrupting condition is cleared. - * Edge-triggered interrupts are cleared by writing to the GPIO interrupt clear register. - *

- * - *

Use of GPIO driver in SW

- *

- * The user of the GPIO driver should set the pin as GPIO, using crossbar. - * Init the GPIO and configure the mode and direction.This will return a device pointer. One device controls all GPIO's. It is not - * needed nor supported to create a device per GPIO. - * Next, the user should call the fGpioOpen function with the device and options as paramter. - *

- *

- * Use the device driver fGpioIoctl function to change the behavior of the GPIO's and to register an - * interrupt handler for each IO that has an interrupt enabled. There is one interrupt for all GPIO's. - * The GPIO driver will look up what IO caused the interrupt and call the respective interrupt handler. - *

- */ - -#include "gpio.h" - -/* Include from the mbed-hal layer */ -#include "gpio_api.h" -#include "pinmap.h" - - -/** Set the given pin as GPIO - * - * @param pin The pin to be set as GPIO - * @return The GPIO port mask for this pin - **/ -uint32_t gpio_set(PinName pin) -{ - if (pin != NC) { - /* Configure to GPIO using pin function API*/ - pin_function(pin, CONFIGURE_AS_GPIO); - - return ((uint32_t) 0x1 << pin); - - } - - return(0x00000000); - -} - -/** Initialize the GPIO pin - * - * @param obj The GPIO object to initialize - * @param pin The GPIO pin to initialize - */ -void gpio_init(gpio_t *obj, PinName pin) -{ - /* Initialize the GPIO membase */ - obj->GPIOMEMBASE = GPIOREG; - - /* Initialize the pin to be GPIO */ - obj->gpioPin = pin; - obj->gpioMask = gpio_set(pin); - - /* Enable the GPIO clock */ - CLOCK_ENABLE(CLOCK_GPIO); - - /* Set the drive strength of the pin to 1 by default */ - /** - Get PAD IO register address for the PAD number */ - PadReg_t *PadRegOffset = (PadReg_t*)(PADREG_BASE + (pin * PAD_REG_ADRS_BYTE_SIZE)); - - /** - Enable the clock for PAD peripheral device */ - CLOCK_ENABLE(CLOCK_PAD); - - /** - Set drive type, pulltype & drive strength */ - PadRegOffset->PADIO0.BITS.POWER = 1; - - /** - Disable the clock for PAD peripheral device */ - CLOCK_DISABLE(CLOCK_PAD); -} - -/** Set the input pin mode - * - * @param obj The GPIO object - * @param mode The pin mode to be set - */ -void gpio_mode(gpio_t *obj, PinMode mode) -{ - uint32_t pin = obj->gpioPin; - - /* Set the mode for the pin */ - pin_mode((PinName)pin, mode); -} - -/** Set the pin direction - * - * @param obj The GPIO object - * @param direction The pin direction to be set - */ -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - /* Enable the GPIO clock which may have been switched off by other drivers */ - CLOCK_ENABLE(CLOCK_GPIO); - - if (direction == PIN_INPUT) { - obj->GPIOMEMBASE->W_IN = obj->gpioMask; - } else if (direction == PIN_OUTPUT) { - obj->GPIOMEMBASE->W_OUT = obj->gpioMask; - } - -} - -/** Set the output value - * - * @param obj The GPIO object - * @param value The value to be set - */ -void gpio_write(gpio_t *obj, int value) -{ - - /* Enable the GPIO clock which may have been switched off by other drivers */ - CLOCK_ENABLE(CLOCK_GPIO); - - /* Set the GPIO based on value */ - if (value) { - obj->GPIOMEMBASE->R_STATE_W_SET = obj->gpioMask; - } else { - obj->GPIOMEMBASE->R_IRQ_W_CLEAR = obj->gpioMask; - } - -} - -/** Read the input value - * - * @param obj The GPIO object - * @return An integer value 1 or 0 - */ -int gpio_read(gpio_t *obj) -{ - int ret; - - /* Enable the GPIO clock which may have been switched off by other drivers */ - CLOCK_ENABLE(CLOCK_GPIO); - - ret = (obj->GPIOMEMBASE->R_STATE_W_SET & obj->gpioMask) ? 1: 0; - - return ret; -} - -/* Checks if gpio object is connected (pin was not initialized with NC) - * @param pin The pin to be set as GPIO - * @return 0 if port is initialized with NC - **/ -int gpio_is_connected(const gpio_t *obj) -{ - if(obj->gpioPin != (PinName)NC) { - return 1; - } else { - return 0; - } -} diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c deleted file mode 100644 index 657586a9f2..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c +++ /dev/null @@ -1,246 +0,0 @@ -/** - ****************************************************************************** - * @file gpio_irq_api.c - * @brief Implementation of a GPIO irq handlers - * @internal - * @author ON Semiconductor - * $Rev: - * $Date: 2015-11-04 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup gpio - * - * @details - * - * @internal - *

Reference document(s)

- *

- * Reference document: IPC7203 APB GPIO Design Specification v1.2 - *

- * @endinternal - * - *

Functional description (internal)

- *

- * Each GPIO line can be independently programmed as an input or an output. Separate Set - * and Clear registers are provided since it is likely that different software tasks may be - * servicing different I/O signals. Inputs are synchronized to the system clock - * through a pair of flip-flops. Each input can be programmed - * to cause an interrupt to be generated. The interrupt can be programmed to be level-sensitive - * or edge-sensitive and the level (high or low) or edge (rising, falling or either) that causes - * the interrupt can be selected. Interrupts can be individually enabled or disabled. - * Level-sensitive interrupts stay asserted until the interrupting condition is cleared. - * Edge-triggered interrupts are cleared by writing to the GPIO interrupt clear register. - *

- * - *

Use of GPIO driver in SW

- *

- * The user of the GPIO driver should set the pin as GPIO, using crossbar. - * Init the GPIO and configure the mode and direction.This will return a device pointer. One device controls all GPIO's. It is not - * needed nor supported to create a device per GPIO. - * Next, the user should call the fGpioOpen function with the device and options as paramter. - *

- *

- * Use the device driver fGpioIoctl function to change the behavior of the GPIO's and to register an - * interrupt handler for each IO that has an interrupt enabled. There is one interrupt for all GPIO's. - * The GPIO driver will look up what IO caused the interrupt and call the respective interrupt handler. - *

- */ - - - -#include "gpio.h" - -/* Include files from the mbed-hal layer */ -#include "gpio_irq_api.h" - -#include "device.h" - -#if DEVICE_INTERRUPTIN - -/* Handler for the GPIO pin */ -static gpio_irq_handler irq_handler; -static uint32_t gpioIds[NUMBER_OF_GPIO] = {0}; - -/** Main GPIO IRQ handler called from vector table handler - * - * @param gpioBase The GPIO register base address - * @return void - */ -void fGpioHandler(void) -{ - uint8_t index; - uint32_t active_interrupts = 0; - gpio_irq_event event = IRQ_NONE; - GpioReg_pt gpioBase; - - /* Enable the GPIO clock which may have been switched off by other drivers */ - CLOCK_ENABLE(CLOCK_GPIO); - - gpioBase = GPIOREG; - - /** - Store all active interrupts */ - active_interrupts = gpioBase->R_IRQ_W_CLEAR; - - for (index=0; index < NUMBER_OF_GPIO; index++) { - - /* Check the pin for which IRQ is raised */ - if ((active_interrupts >> index) & 0x01) { - /* Check if it is edge triggered and clear the interrupt */ - if ((gpioBase->IRQ_EDGE >> index) & 0x01) { - if ((gpioBase->IRQ_POLARITY_SET >> index) &0x01) { - /* Edge triggered high */ - event = IRQ_RISE; - } else { - /* Edge triggered low */ - event = IRQ_FALL; - } - } - gpioBase->IRQ_CLEAR = (0x1 << index); - - /* Call the handler registered to the pin */ - irq_handler(gpioIds[index], event); - } - - } -} - -/** Initialize the GPIO IRQ pin - * - * @param obj The GPIO object to initialize - * @param pin The GPIO pin name - * @param handler The handler to be attached to GPIO IRQ - * @param id The object ID - * @return -1 if pin is NC, 0 otherwise - */ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - /* If Pin is not connected; then return -1 */ - if (pin == NC) { - return(-1); - } - - /* Store the pin for which handler is registered */ - obj->pin = pin; - obj->pinMask = (0x1 << pin); - - /* Store the ID, this is required by registered handler function */ - gpioIds[pin] = id; - - /* Enable the GPIO clock which may have been switched off by other drivers */ - CLOCK_ENABLE(CLOCK_GPIO); - - /* Initialize the GPIO membase */ - obj->GPIOMEMBASE = GPIOREG; - - /* Set default values for the pin interrupt */ - obj->GPIOMEMBASE->W_IN = obj->pinMask; - obj->GPIOMEMBASE->IRQ_EDGE = obj->pinMask; - obj->GPIOMEMBASE->IRQ_POLARITY_SET = obj->pinMask; - - /* Register the handler for this pin */ - irq_handler = handler; - - /* Enable interruption associated with the gpio */ - NVIC_ClearPendingIRQ(Gpio_IRQn); - NVIC_EnableIRQ(Gpio_IRQn); - - return(0); -} - -/** Release the GPIO IRQ PIN - * - * @param obj The gpio object - */ -void gpio_irq_free(gpio_irq_t *obj) -{ - /* Enable the GPIO clock which may have been switched off by other drivers */ - CLOCK_ENABLE(CLOCK_GPIO); - - /* Disable IRQs to indicate that it is now free */ - obj->GPIOMEMBASE->IRQ_ENABLE_CLEAR = obj->pinMask; - gpioIds[obj->pin] = 0; -} - -/** Enable/disable pin IRQ event - * - * @param obj The GPIO object - * @param event The GPIO IRQ event - * @param enable The enable flag - */ -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - /* Enable the GPIO clock which may have been switched off by other drivers */ - CLOCK_ENABLE(CLOCK_GPIO); - obj->GPIOMEMBASE->IRQ_EDGE = obj->pinMask; - - switch(event) { - case IRQ_RISE: - - /* Enable rising edge */ - obj->GPIOMEMBASE->IRQ_POLARITY_SET = obj->pinMask; - break; - - case IRQ_FALL: - - /* Enable falling edge */ - obj->GPIOMEMBASE->IRQ_POLARITY_CLEAR = obj->pinMask; - break; - - default: - /* No event is set */ - break; - } - /* Enable the IRQ based on enable parameter */ - if (enable) { - - obj->GPIOMEMBASE->IRQ_ENABLE_SET = obj->pinMask; - } else { - - obj->GPIOMEMBASE->IRQ_ENABLE_CLEAR = obj->pinMask; - } -} - -/** Enable GPIO IRQ - * - * This is target dependent, as it might enable the entire port or just a pin - * @param obj The GPIO object - */ -void gpio_irq_enable(gpio_irq_t *obj) -{ - /* Enable the GPIO clock which may have been switched off by other drivers */ - CLOCK_ENABLE(CLOCK_GPIO); - - obj->GPIOMEMBASE->IRQ_ENABLE_SET = obj->pinMask; -} - -/** Disable GPIO IRQ - * - * This is target dependent, as it might disable the entire port or just a pin - * @param obj The GPIO object - */ -void gpio_irq_disable(gpio_irq_t *obj) -{ - - /* Enable the GPIO clock which may have been switched off by other drivers */ - CLOCK_ENABLE(CLOCK_GPIO); - - obj->GPIOMEMBASE->IRQ_ENABLE_CLEAR = obj->pinMask; -} - -#endif //DEVICE_INTERRUPTIN diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h deleted file mode 100644 index 831d73e4e5..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/gpio_map.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - ****************************************************************************** - * @file gpio_map.h - * @brief GPIO HW register map - * @internal - * @author ON Semiconductor - * $Rev: 2115 $ - * $Date: 2013-07-17 18:08:17 +0530 (Wed, 17 Jul 2013) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup gpio - * - * @details - *

- * GPIO HW register map description - *

- * - *

Reference document(s)

- *

- * - * Reference document: IPC7203 APB GPIO Design Specification v1.2 - *

- */ - -#ifndef GPIO_MAP_H_ -#define GPIO_MAP_H_ - -#include "architecture.h" - -/** Structure overlay for GPIO control registers, see memory_map.h - * For most registers, bit lockations match GPIO numbers.*/ -typedef struct { - __IO uint32_t R_STATE_W_SET; /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/ - __IO uint32_t R_IRQ_W_CLEAR; /**< Read state of irq / Write ones to bits to clear corresponging output IO's */ - __IO uint32_t W_OUT; /**< Write ones to set direction to output */ - __IO uint32_t W_IN; /**< Write ones to set direction to input */ - __IO uint32_t IRQ_ENABLE_SET; /**< Read active high irq enable / Write ones to enable irq */ - __IO uint32_t IRQ_ENABLE_CLEAR; /**< Read active high irq enable / Write ones to disable irq */ - __IO uint32_t IRQ_EDGE; /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */ - __IO uint32_t IRQ_LEVEL; /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */ - __IO uint32_t IRQ_POLARITY_SET; /**< Read irq polarity / Write ones to set irq to active high or rising edge */ - __IO uint32_t IRQ_POLARITY_CLEAR; /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */ - __IO uint32_t ANYEDGE_SET; /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */ - __IO uint32_t ANYEDGE_CLEAR; /**< Read irq anyedge configuration / Write ones to clear edge selection override */ - __IO uint32_t IRQ_CLEAR; /**< Write ones to clear edge-sensitive irq */ - __IO uint32_t CONTROL; /**< Controls loopback/normal mode selection */ -} GpioReg_t, *GpioReg_pt; - -#endif /* GPIO_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h deleted file mode 100644 index 2b5f323343..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - ****************************************************************************** - * @file i2c.h - * @brief (API) Public header of i2c driver - * @internal - * @author ON Semiconductor - * $Rev: $ - * $Date: 2016-04-20 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup i2c - */ - -#include "mbed_assert.h" -#include "i2c_api.h" -#include "clock.h" -#include "i2c_ipc7208_map.h" -#include "memory_map.h" -#include "PeripheralPins.h" - -#ifndef I2C_H_ -#define I2C_H_ - -/* Miscellaneous I/O and control operations codes */ -#define I2C_IPC7208_IOCTL_NOT_ACK 0x03 -#define I2C_IPC7208_IOCTL_NULL_CMD 0x04 -#define I2C_IPC7208_IOCTL_ACK 0x05 - -/* Definitions for the clock speed. */ -#define I2C_SPEED_100K_AT_8MHZ (uint8_t)0x12 -#define I2C_SPEED_100K_AT_16MHZ (uint8_t)0x26 -#define I2C_SPEED_400K_AT_8MHZ (uint8_t)0x03 -#define I2C_SPEED_400K_AT_16MHZ (uint8_t)0x08 - -/* I2C commands */ -#define I2C_CMD_NULL 0x00 -#define I2C_CMD_WDAT0 0x10 -#define I2C_CMD_WDAT1 0x11 -#define I2C_CMD_WDAT8 0x12 -#define I2C_CMD_RDAT8 0x13 -#define I2C_CMD_STOP 0x14 -#define I2C_CMD_START 0x15 -#define I2C_CMD_VRFY_ACK 0x16 -#define I2C_CMD_VRFY_VACK 0x17 - -/* Status register bits */ -#define I2C_STATUS_CMD_FIFO_MPTY_BIT 0x01 -#define I2C_STATUS_RD_DATA_RDY_BIT 0x02 -#define I2C_STATUS_BUS_ERR_BIT 0x04 -#define I2C_STATUS_RD_DATA_UFL_BIT 0x08 -#define I2C_STATUS_CMD_FIFO_OFL_BIT 0x10 -#define I2C_STATUS_CMD_FIFO_FULL_BIT 0x20 - -/* I2C return status */ -#define I2C_STATUS_INVALID 0xFF -#define I2C_STATUS_SUCCESS 0x00 -#define I2C_STATUS_FAIL 0x01 -#define I2C_STATUS_BUS_ERROR 0x02 -#define I2C_STATUS_RD_DATA_UFL 0x03 -#define I2C_STATUS_CMD_FIFO_OFL 0x04 -#define I2C_STATUS_INTERRUPT_ERROR 0x05 -#define I2C_STATUS_CMD_FIFO_EMPTY 0x06 - -/* I2C clock divider position */ -#define I2C_CLOCKDIVEDER_VAL_MASK 0x1F -#define I2C_APB_CLK_DIVIDER_VAL_MASK 0x1FE0 - -/* Error check */ -#define I2C_UFL_CHECK (obj->membase->STATUS.WORD & 0x80) -#define I2C_FIFO_FULL (obj->membase->STATUS.WORD & 0x20) -#define FIFO_OFL_CHECK (obj->membase->STATUS.WORD & 0x10) -#define I2C_BUS_ERR_CHECK (obj->membase->STATUS.WORD & 0x04) -#define RD_DATA_READY (obj->membase->STATUS.WORD & 0x02) -#define I2C_FIFO_EMPTY (obj->membase->STATUS.WORD & 0x01) - -#define I2C_API_STATUS_SUCCESS 0 -#define PAD_REG_ADRS_BYTE_SIZE 4 - -// The wait_us(0) command is needed so the I2C state machines have enough -// time for data to settle across all clock domain crossings in their -// synchronizers, both directions. -#define SEND_COMMAND(cmd) wait_us(0); obj->membase->CMD_REG = cmd; wait_us(0); - -/** Init I2C device. - * @details - * Sets the necessary registers. The baud rate is set default to 100K - * - * @param obj A I2C device instance. - * @param sda GPIO number for SDA line - * @param scl GPIO number for SCL line - * @return None - */ -extern void fI2cInit(i2c_t *obj,PinName sda,PinName scl); - -/** Set baud rate or frequency - * @details - * Sets user baudrate - * - * @param obj A I2C device instance. - * @param hz User desired baud rate/frequency - * @return None - */ -extern void fI2cFrequency(i2c_t *obj, uint32_t hz); - -/** Sends start bit - * @details - * Sends start bit on i2c pins - * - * @param obj A I2C device instance. - * @return status - */ -extern int32_t fI2cStart(i2c_t *obj); - -/** Sends stop bit - * @details - * Sends stop bit on i2c pins - * - * @param obj A I2C device instance. - * @return status - */ -extern int32_t fI2cStop(i2c_t *obj); - -/** Reads data from a I2C device in blocking fashion. - * @details - * The data is read from the receive queue into the buffer. The receive queue is - * filled by the interrupt handler. If not enough data is available, - * - * @param d The device to read from. - * @param buf The buffer to read into (only the contents of the buffer may be modified, not the buffer itself). - * @param len The maximum number of bytes to read, typically the buffer length. - * @return On Success: The actual number of bytes read. On Failure: Failure code. - */ -extern int32_t fI2cReadB(i2c_t *d, char *buf, int len); - -/** Write data to an I2C device. - * @details - * The commands(I2C instructions) and data arrive at the I2C Engine via the Command FIFO. - * The command to write the data & data to be written is sent to command FIFO by writing it into command register. - * - * @param d The device to write to. - * @param buf The buffer to write from (the contents of the buffer may not be modified). - * @param len The number of bytes to write. - * @return On success: The actual number of bytes written. On Failure: Failure code - */ -extern int32_t fI2cWriteB(i2c_t *d, const char *buf, int len); - -#endif /* I2C_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c deleted file mode 100644 index a45dd333ae..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/** - ******************************************************************************* - * @file i2c.c - * @brief Implementation of an i2c api - * @internal - * @author ON Semiconductor - * $Rev: 3525 $ - * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup i2c - * - */ -#if DEVICE_I2C - -#include "i2c.h" -#include "i2c_api.h" -#include "mbed_wait_api.h" - -#define I2C_READ_WRITE_BIT_MASK 0xFE - -/* See i2c_api.h for details */ -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - fI2cInit(obj, sda, scl); -} - -/* See i2c_api.h for details */ -void i2c_frequency(i2c_t *obj, int hz) -{ - fI2cFrequency(obj, hz); -} - -/* See i2c_api.h for details */ -int i2c_start(i2c_t *obj) -{ - return(fI2cStart(obj)); -} - -/* See i2c_api.h for details */ -int i2c_stop(i2c_t *obj) -{ - return(fI2cStop(obj)); -} - -/* See i2c_api.h for details */ -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - /* TODO address parameter not usable */ - int Count, status; - const char WriteData = (address | (~I2C_READ_WRITE_BIT_MASK)) & 0xFF; - - /* Send start bit */ - status = fI2cStart(obj); - if(status) { - /* Error sending start bit */ - return status; - } - - /* Send address | read */ - Count = fI2cWriteB(obj, &WriteData, 1); - if(Count != 1) { - /* Error sending address */ - return Count; - } - - /* Send command/s */ - Count = fI2cReadB(obj, data, length); - if(Count != length) { - /* Error sending coomand/s */ - return Count; - } - if(stop) { /* Send stop bit if requested */ - status = fI2cStop(obj); - if(status) { - /* Error sending stop bit */ - return status; - } - } - return Count; -} - -/* See i2c_api.h for details */ -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - int Count, status; - const char WriteData = (address & I2C_READ_WRITE_BIT_MASK) & 0xFF; - - /* Send start bit */ - status = fI2cStart(obj); - if(status) { - /* Error sending start bit */ - return status; - } - - /* Send address | write */ - Count = fI2cWriteB(obj, &WriteData, 1); - if(Count != 1) { - /* Error sending address */ - return Count; - } - - /* Sens command, [data] */ - Count = fI2cWriteB(obj, data, length); - if(Count != length) { - /* Error sending address */ - return Count; - } - - if(stop) { /* If stop requested */ - /* Send stop bit */ - status = fI2cStop(obj); - if(status) { - /* Error sending stop bit */ - return status; - } - } - return Count; -} - -/* See i2c_api.h for details */ -void i2c_reset(i2c_t *obj) -{ - (void)fI2cStop(obj); -} - -/* See i2c_api.h for details */ -int i2c_byte_read(i2c_t *obj, int last) /* TODO return size can be uint8_t */ -{ - int Count; - char data; - Count = fI2cReadB(obj, &data, 1); - if(Count != 1) { - /* Error */ - return Count; - } - if(last) { - /* ACK */ - SEND_COMMAND(I2C_CMD_WDAT0); - } else { - /* No ACK */ - SEND_COMMAND(I2C_CMD_WDAT1); - } - return data; -} - -/* See i2c_api.h for details */ -int i2c_byte_write(i2c_t *obj, int data) -{ - int Count; - Count = fI2cWriteB(obj, (const char *)&data, 1); - if(Count != 1) { - return Count; - } - - if(I2C_BUS_ERR_CHECK) { - /* Bus error means NAK received */ - return 0; - } else { - /* ACK received */ - return 1; - } -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_SDA; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_SCL; -} - -#endif /* DEVICE_I2C */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h deleted file mode 100644 index c7bf1940a4..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - ****************************************************************************** - * @file i2c_ipc7208_map.h - * @brief I2C IPC 7208 HW register map - * @internal - * @author ON Semiconductor - * $Rev: 3324 $ - * $Date: 2015-03-27 17:00:28 +0530 (Fri, 27 Mar 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup i2c_ipc7208 - * - * @details - *

- * I2C IPC 7208 HW register map description - *

- * - *

Reference document(s)

- *

- * - * IPC7208 APB I2C Master Design Specification v1.3 - *

- */ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -#ifndef I2C_IPC7208_MAP_H_ -#define I2C_IPC7208_MAP_H_ - -#include "architecture.h" - -/** I2C HW Structure Overlay */ -typedef struct { - union { - struct { - __IO uint32_t CMD_FIFO_EMPTY :1; /**< 1 = Command FIFO is empty , 0 = Command FIFO is empty */ - __IO uint32_t RD_FIFO_NOT_EMPTY :1; /**< 0 = Read data is not ready , 1 = Read data is ready */ - __IO uint32_t I2C_BUS_ERR :1; /**< 0 = No buss error occurred , 1 = buss error */ - __IO uint32_t RD_FIFO_UFL :1; /**< 0 = Read data FIFO is not underflowed , 1 = Read data FIFO is underflowed */ - __IO uint32_t CMD_FIFO_OFL :1;/**< 0 = Command FIFO is not overflowed 1 = Command FIFO is overflowed */ - __IO uint32_t CMD_FIFO_FULL :1; /**< 0 = Command FIFO not full , 1 = Command FIFO full */ - __IO uint32_t PAD :2; /**< Reserved . Always reads back 0. */ - } BITS; - __IO uint32_t WORD; - } STATUS; - __IO uint32_t RD_FIFO_REG;/**< Data from the I2C Slave to be read by the processor. */ - __IO uint32_t CMD_REG; /**< I2C Command Programming interface */ - union { - struct { - __IO uint32_t CMD_FIFO_INT :1; /**< Command FIFO empty interrupt : 0 = disable , 1 = enable */ - __IO uint32_t RD_FIFO_INT :1; /**< Read Data FIFO Not Empty Interrupt : 0 = disable , 1 = enable */ - __IO uint32_t I2C_ERR_INT :1; /**< I2C Error Interrupt : 0 = disable , 1 = enable */ - // __IO uint32_t PAD :4; /**< Reserved. Writes have no effect; Read as 0x00. */ - } BITS; - __IO uint32_t WORD; - } IER; - union { - struct { - __IO uint32_t CD_VAL :5; /**< I2C APB Clock Divider Value (low 5 bits). */ - __IO uint32_t I2C_APB_CD_EN :1; /**< 0 = I2C clock divider disable 1 = I2C clock divider enable */ - __IO uint32_t I2C_CLK_SRC :1; /**< I2C clock source : 0 = external clock , 1 = APB clock */ - __IO uint32_t I2C_MODULE_EN :1; /**< 0 = I2C disable , 1 = I2C enable */ - } BITS; - __IO uint32_t WORD; - } CR; - __IO uint32_t PRE_SCALE_REG; /* I2C APB Clock Divider Value (upper 8 bits). */ -} I2cIpc7208Reg_t, *I2cIpc7208Reg_pt; - -#endif /* I2C_IPC7208_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h deleted file mode 100644 index f92241a467..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/macHw_map.h +++ /dev/null @@ -1,389 +0,0 @@ -/** -****************************************************************************** -* @file macHw_map.h -* @brief MACHW hw module register map -* @internal -* @author ON Semiconductor -* $Rev: 3390 $ -* $Date: 2015-05-13 17:21:05 +0530 (Wed, 13 May 2015) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup macHw -* -* @details -*/ - -#ifndef MACHW_MAP_H_ -#define MACHW_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "architecture.h" - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -/** macHw register map (phy, mac and agc parts) */ -typedef struct { - __O uint32_t SEQUENCER; /**< 0x40014000 */ - union { - struct { - __IO uint32_t MODE:2; - __IO uint32_t NOACK:1; - __IO uint32_t FT:1; - __IO uint32_t PAD0:3; - __IO uint32_t AUTO:1; - __IO uint32_t PAD1:1; - __IO uint32_t NOW:1; - __IO uint32_t PAD2:1; - __IO uint32_t PRM:1; - __IO uint32_t NFCS:1; - __IO uint32_t PAN:1; - __IO uint32_t RSTT:1; - __IO uint32_t RSTR:1; - __IO uint32_t ACK_ENABLE:1; - __IO uint32_t BEA_ENABLE:1; - __IO uint32_t CMD_ENABLE:1; - __IO uint32_t DATA_ENABLE:1; - __IO uint32_t RES_ENABLE:1; - } BITS; - __IO uint32_t WORD; - } SEQ_OPTIONS; /**< 0x40014004 */ - union { - struct { - __IO uint32_t SRST:1; - __IO uint32_t ON:1; - __IO uint32_t CLKDIV:1; - } BITS; - __IO uint32_t WORD; - } CONTROL; /**< 0x40014008 */ - __O uint32_t PAD0; /**< 0x4001400C */ - union { - struct { - __I uint32_t CODE:4; - __I uint32_t PAD0:8; - __I uint32_t MSO:1; - __I uint32_t CB:1; - __I uint32_t PAD1:1; - __I uint32_t MST:1; - } BITS; - __I uint32_t WORD; - } STATUS; /**< 0x40014010 */ - union { - struct { - __IO uint32_t TFP:1; - __IO uint32_t SDC:1; - __IO uint32_t IC:1; - __IO uint32_t SDB:1; - __IO uint32_t SSP:1; - __IO uint32_t TFPO:1; - } BITS; - __IO uint32_t WORD; - } OPTIONS; /**< 0x40014014 */ - __IO uint32_t PANID; /**< 0x40014018 */ - __IO uint32_t SHORT_ADDRESS; /**< 0x4001401C */ - __IO uint32_t LONG_ADDRESS_HIGH; /**< 0x40014020 */ - __IO uint32_t LONG_ADDRESS_LOW; /**< 0x40014024 */ - union { - struct { - __IO uint32_t BIT_CLOCK_DIVIDER:8; - __IO uint32_t SYSTEM_CLOCK_DIVIDER:8; - __IO uint32_t CHIP_CLOCK_DIVIDER:8; - } BITS; - __IO uint32_t WORD; - } DIVIDER; /**< 0x40014028 */ - union { - struct { - __IO uint32_t RECEIVE_WARMPUP:12; - __IO uint32_t PAD0:4; - __IO uint32_t TRANSMIT_WARMPUP:12; - } BITS; - __IO uint32_t WORD; - } RX_TX_WARMPUPS; /**< 0x4001402c */ - union { - struct { - __O uint32_t EC:1; - __O uint32_t ES:1; - __O uint32_t DATA:1; - __O uint32_t FS:1; - __O uint32_t FP:1; - __O uint32_t FMD:1; - __I uint32_t PC:1; - } BITS; - __O uint32_t WORD; - } CLEAR_IRQ; /**< 0x40014030 */ - union { - struct { - __IO uint32_t EC:1; - __IO uint32_t ES:1; - __IO uint32_t DATA:1; - __IO uint32_t FS:1; - __IO uint32_t FP:1; - __IO uint32_t FM:1; - __I uint32_t PC:1; - } BITS; - __IO uint32_t WORD; - } MASK_IRQ; /**< 0x40014034 */ - union { - struct { - __I uint32_t EC:1; - __I uint32_t ES:1; - __I uint32_t DATA:1; - __I uint32_t FS:1; - __I uint32_t FP:1; - __I uint32_t FM:1; - __I uint32_t PC:1; - } BITS; - __I uint32_t WORD; - } IRQ_STATUS; /**< 0x40014038 */ - __O uint32_t PAD1; /**< 0x4001403C */ - union { - struct { - __IO uint32_t START:1; - __IO uint32_t STOP:1; - } BITS; - __IO uint32_t WORD; - } TIMER_ENABLE; /**< 0x40014040 */ - union { - struct { - __IO uint32_t START:1; - __IO uint32_t STOP:1; - } BITS; - __IO uint32_t WORD; - } TIMER_DISABLE; /**< 0x40014044 */ - __IO uint32_t TIMER; /**< 0x40014048 */ - __IO uint32_t START_TIME; /**< 0x4001404C */ - __IO uint32_t STOP_TIME; /**< 0x40014050 */ - union { - struct { - __I uint32_t START:1; - __I uint32_t STOP:1; - } BITS; - __I uint32_t WORD; - } TIMER_STATUS; /**< 0x40014054 */ - __I uint32_t PROTOCOL_TIMER; /**< 0x40014058 */ - __O uint32_t PAD4; /**< 0x4001405C */ - __I uint32_t FINISH_TIME; /**< 0x40014060 */ - union { - struct { - __IO uint32_t TX_SLOT_OFFSET:12; - __IO uint32_t PAD0:4; - __IO uint32_t RX_SLOT_OFFSET:12; - } BITS; - __IO uint32_t WORD; - } SLOT_OFFSET; /**< 0x40014064 */ - __I uint32_t TIME_STAMP; /**< 0x40014068 */ - union { - struct { - __IO uint32_t CRD_SHORT_ADDRESS:16; - __IO uint32_t PAD0:13; - __IO uint32_t ASSOC_PAN_COORD:1; - __IO uint32_t PAN_COORD_ADDR_L:1; - __IO uint32_t PAN_COORD_ADDR_S:1; - } BITS; - __IO uint32_t WORD; -} CRD_SHORT_ADDR; /**< 0x4001406C */ -__IO uint32_t CRD_LONG_ADDR_HI; /**< 0x40014070 */ -__IO uint32_t CRD_LONG_ADDR_LO; /**< 0x40014074 */ -__O uint32_t PAD5; /**< 0x40014078 */ -__O uint32_t PAD9; /**< 0x4001407C */ -__O uint32_t PAD10; /**< 0x40014080 */ -__O uint32_t PAD11; /**< 0x40014084 */ -__IO uint32_t RX_LENGTH; /**< 0x40014088 */ -union { - struct { - __IO uint32_t TXLENGTH:7; - __O uint32_t PAD0:1; - __IO uint32_t TX_PRE_CHIPS:4; - } BITS; - __IO uint32_t WORD; -} TX_LENGTH; /**< 0x4001408C */ -__IO uint32_t TX_SEQ_NUMBER; /**< 0x40014090 */ -__IO uint32_t TX_ACK_DELAY; /**< 0x40014094 */ -union { - struct { - __IO uint32_t RXACKDELAY:12; - __IO uint32_t PAD0:4; - __IO uint32_t RXAUTODELAY:12; - } BITS; - __IO uint32_t WORD; -} RX_ACK_DELAY; /**< 0x40014098 */ -__IO uint32_t TX_FLUSH; /**< 0x4001409C */ -union { - struct { - __IO uint32_t CCA_DELAY:12; - __IO uint32_t PAD0:4; - __IO uint32_t CCA_LENGTH:12; - } BITS; - __IO uint32_t WORD; -} CCA; /**< 0x400140A0 */ -union { - struct { - __IO uint32_t RXACK_END:12; - __IO uint32_t PAD0:4; - __IO uint32_t RXSLOTTED_END:12; - } BITS; - __IO uint32_t WORD; -} ACK_STOP; /**< 0x400140A4 */ -__IO uint32_t TXCCA; /**< 0x400140A8 */ -__IO uint32_t ADDR_L_LOC; /**< 0x400140AC */ -__IO uint32_t ADDR_S_LOC; /**< 0x400140B0 */ -__IO uint32_t FRAME_MATCH_RESULT; /**< 0x400140B4 */ -__IO uint32_t FRAME_MATCH_ADDR_L; /**< 0x400140B8 */ -__IO uint32_t FRAME_MATCH_ADDR_S; /**< 0x400140BC */ -union { - struct { - __IO uint32_t AA:1; - __IO uint32_t AFA:1; - __IO uint32_t PRE:1; - __IO uint32_t PAD0:25; - __IO uint32_t GAIN_START:4; - } BITS; - __IO uint32_t WORD; -} AGC_CONTROL; /**< 0x400140C0 */ -union { - struct { - __IO uint32_t SETTLE_DELAY:8; - __IO uint32_t MEASURE_DELAY:8; - __IO uint32_t DIVIDER:8; - __IO uint32_t HIGH_THRESHOLD:4; - __IO uint32_t LOW_THRESHOLD:4; - } BITS; - __IO uint32_t WORD; -} AGC_SETTINGS; /**< 0x400140C4 */ -union { - struct { - __IO uint32_t GC1:3; - __IO uint32_t GC2:3; - __IO uint32_t GC3:1; - __IO uint32_t PAD:1; - __IO uint32_t AGC_STATE:4; - } BITS; - __IO uint32_t WORD; -} AGC_STATUS; /**< 0x400140C8 */ -union { - struct { - __IO uint32_t GAIN3:7; - __IO uint32_t PAD0:1; - __IO uint32_t GAIN2:7; - __IO uint32_t PAD1:1; - __IO uint32_t GAIN1:7; - __IO uint32_t PAD2:1; - __IO uint32_t GAIN0:7; - __IO uint32_t PAD3:1; - } BITS; - __IO uint32_t WORD; -} AGC_GAIN_TABLE0; /**< 0x400140CC */ -union { - struct { - __IO uint32_t GAIN7:7; - __IO uint32_t PAD0:1; - __IO uint32_t GAIN6:7; - __IO uint32_t PAD1:1; - __IO uint32_t GAIN5:7; - __IO uint32_t PAD2:1; - __IO uint32_t GAIN4:7; - __IO uint32_t PAD3:1; - } BITS; - __IO uint32_t WORD; -} AGC_GAIN_TABLE1; /**< 0x400140D0 */ -union { - struct { - __IO uint32_t GAIN11:7; - __IO uint32_t PAD0:1; - __IO uint32_t GAIN10:7; - __IO uint32_t PAD1:1; - __IO uint32_t GAIN9:7; - __IO uint32_t PAD2:1; - __IO uint32_t GAIN8:7; - __IO uint32_t PAD3:1; - } BITS; - __IO uint32_t WORD; -} AGC_GAIN_TABLE2; /**< 0x400140D4 */ -union { - struct { - __IO uint32_t GAIN15:7; - __IO uint32_t PAD0:1; - __IO uint32_t GAIN14:7; - __IO uint32_t PAD1:1; - __IO uint32_t GAIN13:7; - __IO uint32_t PAD2:1; - __IO uint32_t GAIN12:7; - __IO uint32_t PAD3:1; - } BITS; - __IO uint32_t WORD; -} AGC_GAIN_TABLE3; /**< 0x400140D8 */ -} MacHwReg_t, *MacHwReg_pt; - -/** macHw register map (demodulator part) */ -typedef struct { - union { - struct { - __IO uint32_t DRC:1; /**< Reserved */ - __IO uint32_t SWIQ:1; /**< Compensation for quadrature polarity. (set to 1 for RevB) */ - __IO uint32_t LIF:1; /**< Allows the receiver to use a low-IF frequency of +1.23 MHz (0) or -1.23 MHz (1). */ - __IO uint32_t PM:1; /**< Preamble Mode: Mode 0 (high sensitivity) – Preamble detection is based on observation of a regular pattern of correlation peaks over a span of 5 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If 4 out of 5 symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode improves preamble detection rate by tolerating one corrupt correlation result in the span of 5 symbols. However, the relaxed detection rule allows a higher rate of false preamble detection when no signal is present. Mode 1 (low false detection) – Preamble detection is based on a span of 4 consecutive symbol periods. Each symbol period produces a time index and frequency index corresponding to the largest correlation peak. If all four symbol periods produce time/frequency index values that meet a set of similarity criteria, then preamble detection is declared. This mode enforces a more strict detection rule and therefore offers lower rate of false preamble detection at the expense of higher missed detection. */ - __IO uint32_t ASM:1; /**< This bit determines whether antenna selection is automatic (1) or manual (0). For applications that do not use antenna diversity, this bit should be set to 0. */ - __IO uint32_t AS:1; /**< If automatic antenna selection mode is used, this bit determines the initial antenna selection. If manual antenna selection mode is used, this bit determines the antenna selection, 0 or 1. */ - __IO uint32_t DTC:1; /**< Sets the decay time constant used in the RSSI calculation and Digital Gain Control functions. 0: Time constant set to 1 symbol period. This produces a slower response time but more stable RSSI values. Not recommended for use with antenna diversity. 1: Time constant set to 1/4th of a symbol period. This produces a faster response with slightly more variance in the RSSI calculation. Recommended for most cases. */ - __IO uint32_t PAD1:9; - __IO uint32_t DFR:16; /** threshold. Default 0xFF */ - __IO uint32_t RSSI_OFFSET:6; /**< Calibration constant added to the RSSI calculation. The 6-bit field is treated as a signed value in two’s complement format with values from -32 to +31 dB. */ - } BITS; - __IO uint32_t WORD; - } DMD_CONTROL2; /**< 0x40014108 */ - union { - struct { - __I uint32_t RSSI_VALUE:8; /**< The value is captured at the end of packet reception or at the end of ED/CCA measurements and is interpreted in dBm as follows: 00000000 -> 0127dBm (or below) ... 01111111 -> 0dBm (or above) */ - __I uint32_t FREQUENCY_OFFSET:4; /**< Frequency correction applied to the received packet. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */ - __I uint32_t ANT:1; /**< Antenna used for reception. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */ - __I uint32_t PAD0:3; - __I uint32_t RSSI_COMPONENT:4; /**< Magnitude of the baseband digital signal (units are dB relative to A/D saturation). The value is updated until AGC is frozen. The value is captured at the end of packet reception or at the end of ED/CCA measurements. */ - } BITS; - __I uint32_t WORD; - } DMD_STATUS; /**< 0x4001410C */ -} DmdReg_t, *DmdReg_pt; - -#endif /* MACHW_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/macros.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/macros.h deleted file mode 100644 index fff801ec85..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/macros.h +++ /dev/null @@ -1,41 +0,0 @@ -/** - ****************************************************************************** - * @file macros.h - * @brief Implements some handy macros - * @internal - * @author : ON Semiconductor. - * $Rev: 2076 $ - * $Date: 2013-07-10 18:26:10 +0530 (Wed, 10 Jul 2013) $ - ******************************************************************************* - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @details - * - * @ingroup UTILITY - */ - -#ifndef MACROS_H_ -#define MACROS_H_ - -#define BM(n) (1 << (n)) -#define BF(x,b,s) (((x) & (b)) >> (s)) -#define MIN(n,m) (((n) < (m)) ? (n) : (m)) -#define MAX(n,m) (((n) < (m)) ? (m) : (n)) -#define ABS(n) ((n < 0) ? -(n) : (n)) - -#endif /* MACROS_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h deleted file mode 100644 index 4be0010e6e..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h +++ /dev/null @@ -1,290 +0,0 @@ -/** -****************************************************************************** -* @file memory_map.h -* @brief Defines the silicon memory map. All peripheral devices shall be mapped in structures. -* @internal -* @author ON Semiconductor -* $Rev: 3525 $ -* $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup bsp -@verbatim - +-----------------+ - | | ,_________________________ - | Private Per. | |PMUREG 0x4001D000| -0xE0000000 +-----------------+ |PADREG 0x4001C000| - | |_____________|CLOCKREG 0x4001B000| - | PERIPHERALS | |RFANAREG 0x40019000| - +-----------------+ |RESETREG 0x40018000| - | | |FLASHREG 0x40017000| -0x3FFF8000 |SRAM A 32K | |AESREG 0x40016000| - +-----------------+ |ADCREG 0x40015000| - | | |MACHWREG 0x40014000| - |SRAM B 16K | |RANDREG 0x40011000| -0x3FFF4000 +-----------------+ |CROSSBREG 0x40010000| - | | |RTCREG 0x4000F000| -0x24000100 |SRAM DMA 7B | |GPIOREG 0x4000C000| - +-----------------+ |PWMREG 0x4000B000| -0x24000000 |SRAM MAC 256B | |WDTREG 0x4000A000| - +-----------------+ |UARTREG 0x40008000| - | 320K | |I2CREG 0x40007000| -0x00102000 |FLASHB | |SPIREG 0x40006000| -0x00100000 |FLASHB Inf Block | |UARTREG 0x40005000| - +-----------------+ |TIM2REG 0x40002000| - | 320K | |TIM1REG 0x40001000| -0x00002000 |FLASHA | |TIM0REG 0x40000000| -0x00000000 |FLASHA Inf Block | '`'''''''''''''''''''''''' - '`''''''''''''''''' - -@endverbatim -*/ - -#ifndef _MEMORY_MAP_H_ -#define _MEMORY_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include - -#include "architecture.h" - -// Register maps of HW modules controlled with device drivers -#include "adc_sar_map.h" -#include "aes_map.h" -#include "flash_map.h" -#include "gpio_map.h" -#include "i2c_ipc7208_map.h" -#include "pwm_map.h" -#include "rtc_map.h" -#include "spi_ipc7207_map.h" -#include "timer_map.h" -#include "uart_16c550_map.h" -#include "wdt_map.h" - -// Register maps of HW modules controlled with specific functions -#include "clock_map.h" -#include "crossbar_map.h" -#include "dma_map.h" -#include "macHw_map.h" -#include "pad_map.h" -#include "pmu_map.h" -#include "random_map.h" -#include "reset_map.h" -#include "rfAna_map.h" -#include "test_map.h" - -// Trim structure map -#include "trim_map.h" - -/************************************************************************************************* -* * -* Symbolic Constants * -* * -*************************************************************************************************/ - -/** Trim structure mapping - * - */ -#define TRIMREG_BASE ((uint32_t)0x1FA0) -#define TRIMREG ((TrimReg_t *)TRIMREG_BASE) - -/** User trim structure mapping - * - */ -#define USRETRIMREG_BASE ((uint32_t)0x2800) -#define USERTRIMREG ((UserTrimReg_t *)USRETRIMREG_BASE) - -/** DMA HW Registers Offset */ -#define DMAREG_BASE ((uint32_t)0x24000400) -/** DMA HW Structure Overlay */ -#define DMAREG ((DmaReg_pt)DMAREG_BASE) - -/** MAC MATCH HW Registers Offset */ -#define MACMATCHREG_BASE ((uint32_t)0x24000100) -/** MAC MATCH HW Structure Overlay */ -#define MACMATCHREG ((volatile uint8_t *)MACMATCHREG_BASE) - -/** MAC RX HW Registers Offset */ -#define MACRXREG_BASE ((uint32_t)0x24000080) -/** MAC RX HW Structure Overlay */ -#define MACRXREG ((volatile uint8_t *)MACRXREG_BASE) - -/** MAC TX HW Registers Offset */ -#define MACTXREG_BASE ((uint32_t)0x24000000) -/** MAC TX HW Structure Overlay */ -#define MACTXREG ((volatile uint8_t *)MACTXREG_BASE) - -/** TEST Interface for flash HW Registers Offset */ -#define TESTNVMREG_BASE ((uint32_t)0x4001F140) -/** TEST Interface for flash HW Structure Overlay */ -#define TESTNVMREG ((TestNvmReg_pt)TESTNVMREG_BASE) - -/** Test Interface for digital HW Registers Offset */ -#define TESTDIGREG_BASE ((uint32_t)0x4001F100) -/** Test Interface for digital HW Structure Overlay */ -#define TESTDIGREG ((TestDigReg_pt)TESTDIGREG_BASE) - -/** Test Interface HW Registers Offset */ -#define TESTREG_BASE ((uint32_t)0x4001F000) -/** Test Interface HW Structure Overlay */ -#define TESTREG ((TestReg_pt)TESTREG_BASE) - -/** Device option HW Registers Offset */ -#define DEVOPTREG_BASE ((uint32_t)0x4001E000) -/** MAC TX HW Structure Overlay */ -#define DEVOPTREG ((volatile uint32_t *)DEVOPTREG_BASE) - -/** PMU HW Registers Offset */ -#define PMUREG_BASE ((uint32_t)0x4001D000) -/** PMU HW Structure Overlay */ -#define PMUREG ((PmuReg_pt)PMUREG_BASE) - -/** PAD Control HW Registers Offset */ -#define PADREG_BASE ((uint32_t)0x4001C000) -/** PAD Control HW Structure Overlay */ -#define PADREG ((PadReg_pt)PADREG_BASE) - -/** Clock Control HW Registers Offset */ -#define CLOCKREG_BASE ((uint32_t)0x4001B000) -/** Clock Control HW Structure Overlay */ -#define CLOCKREG ((ClockReg_pt)CLOCKREG_BASE) - -/** Analogue Trim HW Registers Offset */ -#define RFANATRIMREG_BASE ((uint32_t)0x40019080) -/** Analogue Trim HW Structure Overlay */ -#define RFANATRIMREG ((RfAnaTrimReg_pt)RFANATRIMREG_BASE) - -/** Analogue RF HW Registers Offset */ -#define RFANAREG_BASE ((uint32_t)0x40019000) -/** Analogue RF HW Structure Overlay */ -#define RFANAREG ((RfAnaReg_pt)RFANAREG_BASE) - -/** Reset Cause HW Registers Offset */ -#define RESETREG_BASE ((uint32_t)0x40018000) -/** Reset Cause HW Structure Overlay */ -#define RESETREG ((ResetReg_pt)RESETREG_BASE) - -/** FLASH Control HW Registers Offset */ -#define FLASHREG_BASE ((uint32_t)0x40017000) -/** FLASH Control HW Structure Overlay */ -#define FLASHREG ((FlashReg_pt)FLASHREG_BASE) - -/** AES Encryption HW Registers Offset */ -#define AESREG_BASE ((uint32_t)0x40016000) -/** AES Encryption HW Structure Overlay */ -#define AESREG ((AesReg_pt)AESREG_BASE) - -/** SAR ADC HW Registers Offset */ -#define ADCREG_BASE ((uint32_t)0x40015000) -/** SAR ADC HW Structure Overlay */ -#define ADCREG ((AdcReg_pt)ADCREG_BASE) - -/** Demodulator HW Registers Offset */ -#define DMDREG_BASE ((uint32_t)0x40014100) -/** Demodulator HW Structure Overlay */ -#define DMDREG ((DmdReg_pt)DMDREG_BASE) - -/** MAC Control HW Registers Offset */ -#define MACHWREG_BASE ((uint32_t)0x40014000) -/** MAC Control HW Structure Overlay */ -#define MACHWREG ((MacHwReg_pt)MACHWREG_BASE) - -/** Random Generator HW Registers Offset */ -#define RANDREG_BASE ((uint32_t)0x40011000) -/** Random Generator HW Structure Overlay */ -#define RANDREG ((RandReg_pt)RANDREG_BASE) - -/** Cross Bar HW Registers Offset */ -#define CROSSBREG_BASE ((uint32_t)0x40010000) -/** Cross Bar HW Structure Overlay */ -#define CROSSBREG ((CrossbReg_pt)CROSSBREG_BASE) - -/** Real Time Clock HW Registers Offset */ -#define RTCREG_BASE ((uint32_t)0x4000F000) -/** Real Time Clock HW Structure Overlay */ -#define RTCREG ((RtcReg_pt)RTCREG_BASE) - -/** GPIO HW Registers Offset */ -#define GPIOREG_BASE ((uint32_t)0x4000C000) -/** GPIO HW Structure Overlay */ -#define GPIOREG ((GpioReg_pt)GPIOREG_BASE) - -/** PWM HW Registers Offset */ -#define PWMREG_BASE ((uint32_t)0x4000B000) -/** PWM HW Structure Overlay */ -#define PWMREG ((PwmReg_pt)PWMREG_BASE) - -/** Watchdog Timer HW Registers Offset */ -#define WDTREG_BASE ((uint32_t)0x4000A000) -/** Watchdog Timer HW Structure Overlay */ -#define WDTREG ((WdtReg_pt)WDTREG_BASE) - -/** UART 2 HW Registers Offset */ -#define UART2REG_BASE ((uint32_t)0x40008000) -/** UART 2 HW Structure Overlay */ -#define UART2REG ((Uart16C550Reg_pt)UART2REG_BASE) - -/** I2C HW Registers Offset */ -#define I2C1REG_BASE ((uint32_t)0x40007000) -/** I2C HW Structure Overlay */ -#define I2C1REG ((I2cIpc7208Reg_pt)I2C1REG_BASE) - -/** SPI HW Registers Offset */ -#define SPI1REG_BASE ((uint32_t)0x40006000) -/** SPI HW Structure Overlay */ -#define SPI1REG ((SpiIpc7207Reg_pt)SPI1REG_BASE) - -/** UART1 HW Registers Offset */ -#define UART1REG_BASE ((uint32_t)0x40005000) -/** UART1 HW Structure Overlay */ -#define UART1REG ((Uart16C550Reg_pt)UART1REG_BASE) - -#define UARTREG_BASES { UART1REG_BASE, UART2REG_BASE} - -/** Timer 2 HW Registers Offset */ -#define TIM2REG_BASE ((uint32_t)0x40002000) -/** Timer 2 HW Structure Overlay */ -#define TIM2REG ((TimerReg_pt)TIM2REG_BASE) - -/** Timer 1 HW Registers Offset */ -#define TIM1REG_BASE ((uint32_t)0x40001000) -/** Timer 1 HW Structure Overlay */ -#define TIM1REG ((TimerReg_pt)TIM1REG_BASE) - -/** Timer 0 HW Registers Offset */ -#define TIM0REG_BASE ((uint32_t)0x40000000) -/** Timer 0 HW Structure Overlay */ -#define TIM0REG ((TimerReg_pt)TIM0REG_BASE) - -/** I2C2 HW Registers Offset */ -#define I2C2REG_BASE ((uint32_t)0x4000D000) -/** I2C2 HW Structure Overlay */ -#define I2C2REG ((I2cIpc7208Reg_pt)I2C2REG_BASE) - -/** SPI2 HW Registers Offset */ -#define SPI2REG_BASE ((uint32_t)0x40009000) -/** SPI2 HW Structure Overlay */ -#define SPI2REG ((SpiIpc7207Reg_pt)SPI2REG_BASE) - -#endif /*_MEMORY_MAP_H_*/ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/mib.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/mib.h deleted file mode 100644 index bb63e92852..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/mib.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - ****************************************************************************** - * @file mib.h - * @brief Defines the structure of a Management Information Base (MIB) - * @internal - * @author ON Semiconductor - * $Rev: 2284 $ - * $Date: 2013-09-12 15:08:22 +0530 (Thu, 12 Sep 2013) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @details - * This file defines the structure, as seen from the outside, of any Management - * Information Base (MIB) implementation. It does not define the contents of the - * MIB. - * - * A MIB is implemented as a map of parameters, each identified by a unique Object ID. - * The contents of the map have to be filled in by the actual MIB implementation, by - * assigning to the GlobMibMap variable. The mib_param_t data type defines the format - * of each parameter in the map. *NOTE:* The length of the last entry in the map must - * be 0. - * - * One parameter must always be present in the MIB map: the system revision. It has - * to be set by assigning a value to the systemRevision variable. - * - * Parameters can be of any data type, and read / write or read only. To resemble - * the hierarchical structure of an SNMP MIB, each Object ID consists of four nibbles - * (uint16_t) where the more significant nibbles correspond to a higher level in the - * hierarchy. - * - * The contents of the map can be accessed with the fMibSetBytes() and fMibGetBytes() - * functions. The implementation of the MIB may also make its parameters accessible - * in a more "direct" way; that is left to the implementation. The fMibSetBytes() and - * fMibGetBytes() functions are made available to the user interface (see ui.h). In - * order to do so, fMibUiInit() must be called during device initialization. - * - * Additionally, for parameters that have an array as their value, the individual - * elements of the array can be accessed using the fMibIndexedSetBytes() and - * fMibIndexedGetBytes() functions. The functions are similar to their non-indexed - * variants (fMibSetBytes() and fMibGetBytes()), except that they expect the index of - * the element as an argument. - * - * fMibGetBytes() and fMibSetBytes() will normally copy bytes from the MIB parameter - * into a given place in memory, or from memory to the MIB parameter. This behaviour - * can be overruled by assigning a function to the setAction and / or getAction - * fields of the MIB parameter. - * - * For parameters that have an array as their value, the length field has a slightly - * different meaning: the most significant 16 bits contain the length of the array; - * the least significant 16 bits contain the width of the array (i.e. the size in - * bytes of the array's elements). This implies that the normal fMibGetBytes() and - * fMibSetBytes() cannot be used on these parameters; instead, a get and set action - * needs to be provided to interpret the length field in case of a non-indexed get - * or set. - * - * To access the MIB fields over the user interface, the module ID must be equal to - * MIB_MODULE_ID or 0x01. The data in the packet must have the following structure: - * - * - * - * - * - * - * - * - * - * - * - *
Get (0x00) / Set (0x01) codeObject IDValue (only for set)
1 Byte2 BytesX bytes
- * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Indexed Get (0x02) / Set (0x03) codeObject IDIndexValue (only for set)
1 Byte2 Bytes2 BytesX bytes
- * - * The reply to this request will have the same structure, with the value always - * being present (in case of a Set as well as a Get request). - * - * In case an error occurs during a Set or Get request, an error is returned by - * fMibGetBytes(), fMibSetBytes() or the UI. See the UI Module's documentation for - * the format of an error reply. The applicable error codes are: - * - * - * - * - * - *
0x01Trying to set a read-only parameter.
0x02Requested value out of range.
0x03Object ID is unknown.
0x04Provided index is incorrect.
- * - * @ingroup mib - */ - -#ifndef MIB_H_ -#define MIB_H_ - - -#include - -#include "types.h" -#include "error.h" - -/** A structure defining the format of the system revision parameter. */ -typedef struct mib_systemRevision { - uint8_t hardwareRevision; - uint8_t patchLevel; - uint8_t bugFix; - uint8_t featureSet; - uint8_t generation; - uint8_t release; -} mib_systemRevision_t, *mib_systemRevision_pt; - -/** The system revision. */ -extern const mib_systemRevision_t systemRevision; - - -#endif /* MIB_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c deleted file mode 100644 index 8976efe973..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c +++ /dev/null @@ -1,312 +0,0 @@ -/** -*************************************************************************** -* @file ncs36510_init.c -* @brief Initialization of Orion SoC -* @internal -* @author ON Semiconductor -* $Rev: -* $Date: $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup main -* -* @details -*/ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ -#include "ncs36510Init.h" - -void fPmuInit(void); - -/** - * @brief - * Hardware trimming function - * This function copies trim codes from specific flash location - * where they are stored to proper hw registers. - */ -boolean fTrim() -{ - boolean status = False; - - /**- Check if trim values are present */ - /**- If Trim data is present. Only trim if valid trim values are present. */ - /**- Copy trims in registers */ - if (TRIMREG->REVISION_CODE != 0xFFFFFFFF) { - - if ( TRIMREG->MAC_ADDR_LOW != 0xFFFFFFFF ) { - MACHWREG->LONG_ADDRESS_LOW = TRIMREG->MAC_ADDR_LOW; - } - - if ( TRIMREG->MAC_ADDR_HIGH != 0xFFFFFFFF ) { - MACHWREG->LONG_ADDRESS_HIGH = TRIMREG->MAC_ADDR_HIGH; - } - - /**- board specific clock trims may only be done when present, writing all 1's is not good */ - if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) { - CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT; - } - - if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) { - CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT; - } - - MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = TRIMREG->TX_PRE_CHIPS; - - if ((TRIMREG->TX_TRIM & 0xFFFF0000) != 0xFFFF0000) { - RFANATRIMREG->TX_TRIM.WORD = TRIMREG->TX_TRIM; - } - RFANATRIMREG->PLL_VCO_TAP_LOCATION = TRIMREG->PLL_VCO_TAP_LOCATION; - RFANATRIMREG->PLL_TRIM.WORD = TRIMREG->PLL_TRIM; - - /**- board specific RSSI trims may only be done when present, writing all 1's is not good */ - if ((TRIMREG->RSSI_OFFSET & 0xFFFF0000) != 0xFFFF0000) { - DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = TRIMREG->RSSI_OFFSET; - } - - RFANATRIMREG->RX_CHAIN_TRIM = TRIMREG->RX_CHAIN_TRIM; - RFANATRIMREG->PMU_TRIM = TRIMREG->PMU_TRIM; - RANDREG->WR_SEED_RD_RAND = TRIMREG->WR_SEED_RD_RAND; - - /* High side injection settings */ - RFANATRIMREG->RX_VCO_TRIM_LUT1 = TRIMREG->RX_VCO_LUT1.WORD;; - RFANATRIMREG->RX_VCO_TRIM_LUT2 = TRIMREG->RX_VCO_LUT2.WORD;; - - RFANATRIMREG->TX_VCO_TRIM_LUT1 = TRIMREG->TX_VCO_LUT1.WORD;; - RFANATRIMREG->TX_VCO_TRIM_LUT2 = TRIMREG->TX_VCO_LUT2.WORD;; - - status = True; - - } else { - - return(False); - } - - /** Read in user trim values programmed in the flash memory - The user trim values take precedence over factory trim for MAC address - */ - if (( USERTRIMREG->MAC_ADDRESS_LOW != 0xFFFFFFFF ) && - (USERTRIMREG->MAC_ADDRESS_HIGH != 0xFFFFFFFF)) { - - MACHWREG->LONG_ADDRESS_LOW = USERTRIMREG->MAC_ADDRESS_LOW; - MACHWREG->LONG_ADDRESS_HIGH = USERTRIMREG->MAC_ADDRESS_HIGH; - } - - if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) { - CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF); - } - - if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) { - CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF); - } - - if (USERTRIMREG->RSSI_OFFSET != 0xFFFFFFFF) { - DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = (USERTRIMREG->RSSI_OFFSET & 0x0000003F); - } - - if (USERTRIMREG->TX_TRIM != 0xFFFFFFFF) { - RFANATRIMREG->TX_TRIM.BITS.TX_TUNE = (USERTRIMREG->TX_TRIM & 0x0000000F); - } - return(status); -} - -/* See clock.h for documentation. */ -void fClockInit() -{ - - /** Enable external 32MHz oscillator */ - CLOCKREG->CCR.BITS.OSC_SEL = 1; - - /** - Wait external 32MHz oscillator to be ready */ - while(CLOCKREG->CSR.BITS.XTAL32M != 1) {} /* If you get stuck here, something is wrong with board or trim values */ - - /** Internal 32MHz calibration \n *//** - Enable internal 32MHz clock */ - PMUREG->CONTROL.BITS.INT32M = 0; - - /** - Wait 5 uSec for clock to stabilize */ - volatile uint8_t Timer; - for(Timer = 0; Timer < 10; Timer++); - - /** - Enable calibration */ - CLOCKREG->CCR.BITS.CAL32M = True; - - /** - Wait calibration to be completed */ - while(CLOCKREG->CSR.BITS.CAL32MDONE == False); /* If you stuck here, issue with internal 32M calibration */ - - /** - Check calibration status */ - while(CLOCKREG->CSR.BITS.CAL32MFAIL == True); /* If you stuck here, issue with internal 32M calibration */ - - /** - Power down internal 32MHz osc */ - PMUREG->CONTROL.BITS.INT32M = 1; - - /** Internal 32KHz calibration \n */ /** - Enable internal 32KHz clock */ - PMUREG->CONTROL.BITS.INT32K = 0; - - /** - Wait 5 uSec for clock to stabilize */ - for(Timer = 0; Timer < 10; Timer++); - - /** - Enable calibration */ - CLOCKREG->CCR.BITS.CAL32K = True; - - /** - Wait calibration to be completed */ - while(CLOCKREG->CSR.BITS.DONE32K == False); /* If you stuck here, issue with internal 32K calibration */ - - /** - Check calibration status */ - while(CLOCKREG->CSR.BITS.CAL32K == True); /* If you stuck here, issue with internal 32M calibration */ - - /** - Power down external 32KHz osc */ - PMUREG->CONTROL.BITS.EXT32K = 1; - - /** Disable all peripheral clocks by default */ - CLOCKREG->PDIS.WORD = 0xFFFFFFFF; - - /** Set core frequency */ - CLOCKREG->FDIV = CPU_CLOCK_DIV - 1; -} - -/* Initializes PMU module */ -void fPmuInit() -{ - /** Enable the clock for PMU peripheral device */ - CLOCK_ENABLE(CLOCK_PMU); - - /** Unset wakeup on pending (only enabled irq can wakeup) */ - SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk; - - /** Unset auto sleep when returning from wakeup irq */ - SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; - - /** Set regulator timings */ - PMUREG->FVDD_TSETTLE = 160; - PMUREG->FVDD_TSTARTUP = 400; - - - /** Keep SRAMA & SRAMB powered in coma mode */ - PMUREG->CONTROL.BITS.SRAMA = False; - PMUREG->CONTROL.BITS.SRAMB = False; - - PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */ - PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */ - - /** Disable the clock for PMU peripheral device, all settings are done */ - CLOCK_DISABLE(CLOCK_PMU); -} - -/* See clock.h for documentation. */ -uint32_t fClockGetPeriphClockfrequency() -{ - return (CPU_CLOCK_ROOT_HZ / CPU_CLOCK_DIV); -} - - -/** -* @brief -* Hardware initialization function -* This function initializes hardware at application start up prior -* to other initializations or OS operations. -*/ -static void fHwInit(void) -{ - - /* Trim register settings */ - fTrim(); - - /* Clock setting */ - /** - Initialize clock */ - fClockInit(); - - /** - Initialize pmu */ - fPmuInit(); - - /** Orion has 4 interrupt bits in interrupt priority register - * The lowest 4 bits are not used. - * - @verbatim - +-----+-----+-----+-----+-----+-----+-----+-----+ - |bit 7|bit 6|bit 5|bit 4|bit 3|bit 2|bit 1|bit 0| - | | | | | 0 | 0 | 0 | 0 | - +-----+-----+-----+-----+-----+-----+-----+-----+ - | - INTERRUPT PRIORITY | NOT IMPLEMENTED, - | read as 0 - Valid priorities are 0x00, 0x10, 0x20, 0x30 - 0x40, 0x50, 0x60, 0x70 - 0x80, 0x90, 0xA0, 0xB0 - 0xC0, 0xD0, 0xE0, 0xF0 - @endverbatim - * Lowest number is highest priority - * - * - * This range is defined by - * configKERNEL_INTERRUPT_PRIORITY (lowest) - * and configMAX_SYSCALL_INTERRUPT_PRIORITY (highest). All interrupt - * priorities need to fall in that range. - * - * To be future safe, the LSbits of the priority are set to 0xF. - * This wil lmake sure that if more interrupt bits are used, the - * priority is maintained. - */ - - /** - Set IRQs priorities */ - NVIC_SetPriority(Tim0_IRQn, 14); - NVIC_SetPriority(Tim1_IRQn, 14); - NVIC_SetPriority(Tim2_IRQn, 14); - NVIC_SetPriority(Uart1_IRQn,14); - NVIC_SetPriority(Spi_IRQn, 14); - NVIC_SetPriority(I2C_IRQn, 14); - NVIC_SetPriority(Gpio_IRQn, 14); - NVIC_SetPriority(Rtc_IRQn, 14); - NVIC_SetPriority(MacHw_IRQn, 13); - NVIC_SetPriority(Aes_IRQn, 13); - NVIC_SetPriority(Adc_IRQn, 14); - NVIC_SetPriority(ClockCal_IRQn, 14); - NVIC_SetPriority(Uart2_IRQn, 14); - NVIC_SetPriority(Dma_IRQn, 14); - NVIC_SetPriority(Uvi_IRQn, 14); - NVIC_SetPriority(DbgPwrUp_IRQn, 14); - NVIC_SetPriority(Spi2_IRQn, 14); - NVIC_SetPriority(I2C2_IRQn, 14); -} - -extern void __Vectors; - -void fNcs36510Init(void) -{ - /** Setting this register is helping to debug imprecise bus access faults - * making them precise bus access faults. It has an impact on application - * performance. */ - // SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk; - - /** This main function implements: */ - /**- Disable all interrupts */ - NVIC->ICER[0] = 0x1F; - - /**- Clear all Pending interrupts */ - NVIC->ICPR[0] = 0x1F; - - /**- Clear all pending SV and systick */ - SCB->ICSR = (uint32_t)0x0A000000; - SCB->VTOR = (uint32_t) (&__Vectors); - - /**- Initialize hardware */ - fHwInit(); -} diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h deleted file mode 100644 index 953512aa16..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.h +++ /dev/null @@ -1,54 +0,0 @@ -/** -*************************************************************************** -* @file ncs36510_init.h -* @brief Initialization of Orion SoC -* @internal -* @author ON Semiconductor. -* $Rev: -* $Date: $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup main -* -* @details -*/ -#ifndef NCS36510_H_ -#define NCS36510_H_ - -/* BSP inclusions */ -#include "architecture.h" -#include "memory_map.h" -#include "ticker.h" -#include "gpio.h" -#include "gpio_api.h" - -/* Other inclusions */ -#include "types.h" - -boolean fTrim(void); - -void fClockInit(void) ; - -uint32_t fClockGetPeriphClockfrequency(void); - -void fNcs36510Init(void); - -#endif //NCS36510_H_ - - diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c deleted file mode 100644 index 8ae4a9b935..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c +++ /dev/null @@ -1,231 +0,0 @@ -/** - ****************************************************************************** - * @file i2c.c - * @brief I2C driver - * @internal - * @author ON Semiconductor - * $Rev: $ - * $Date: 2016-04-12 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup i2c - * - * @details - * - *

Reference document(s)

- *

- * IPC7208 APB I2C Master Design Specification v1.3 - *

- * The I2C bus is an industry-standard two-wire (clock and data) serial communication bus between master(initiator) and slave device. - * Within the procedure of the I2C-bus, unique situations arise which are defined as START and STOP conditions .A HIGH to LOW transition on - * the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition.A LOW to HIGH transition on the - * SDA line while SCL is HIGH defines a STOP condition.START and STOP conditions are always generated by the master. The bus is considered - * to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. - * A master may start a transfer only if the bus is free. Two or more masters may generate a START condition. - * Every byte put on the SDA line must be 8-bits long.Each byte has to be followed by an acknowledge bit. - * This APB(Advanced peripheral bus) I2C Master is an APB Slave peripheral that can also serves as an I2C bus Master. The Command register - * is the programming interface to the I2C Engine. The commands arrive at the I2C Engine via the Command FIFO,so the first valid command - * that is written to the Command register is the first I2C instruction implemented on the I2C bus.Because the command interface provides - * the basic building blocks for any I2C transaction, access to a wide range of I2C slave devices is supported. - * I2C can be enabled by setting bit 7 of the control register . - * There is a generated clock (a divided version of the APB clock) in this module that may be used as the I2C System Clock. - * There are two FIFO in the I2C; Command FIFO and Read data FIFO - * The commands(I2C instructions) and data arrive at the I2C Engine via the Command FIFO. - * if the command FIFO is empty , up to 32 commands can be written to the command interface , it is programmer's responsibility to keep - * the track of command FIFO's status either by interrupt or by polling method by reading status register, which represents Operational - * Status of the I2C Module and its sub-modules.The action from the processor may be necessary after reading the status register.Reading - * the Status register clears the blkInt Interrupt signal.Read data FIFO is where data read by the processor from I2C slave is placed . - * - * - *

Functional description (internal)

- *

- * - *

- */ -#if DEVICE_I2C -#include "i2c.h" -#include "mbed_wait_api.h" - -/* See i2c.h for details */ -void fI2cInit(i2c_t *obj,PinName sda,PinName scl) -{ - /* determine the I2C to use */ - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - obj->membase = (I2cIpc7208Reg_pt)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT((int)obj->membase != NC); - - /* By default disbale interrupts */ - obj->membase->IER.WORD = False; - - /* enable interrupt associated with the device */ - if(obj->membase == I2C1REG) { - CLOCK_ENABLE(CLOCK_I2C); /* enable i2c peripheral */ - NVIC_ClearPendingIRQ(I2C_IRQn); - NVIC_EnableIRQ(I2C_IRQn); - } else { - CLOCK_ENABLE(CLOCK_I2C2); /* enable i2c peripheral */ - NVIC_ClearPendingIRQ(I2C2_IRQn); - NVIC_EnableIRQ(I2C2_IRQn); - } - - /*select I2C clock source */ - obj->membase->CR.BITS.I2C_CLK_SRC = True; - - /* enable I2C clock divider */ - obj->membase->CR.BITS.I2C_APB_CD_EN = True; - - /* set default baud rate at 100k */ - fI2cFrequency(obj, 100000); - - /* Cross bar setting */ - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - - /*Enable open drain & pull up for sda & scl pin */ - pin_mode(sda, OpenDrainPullUp); - pin_mode(scl, OpenDrainPullUp); - - /* PAD drive strength */ - PadReg_t *padRegSda = (PadReg_t*)(PADREG_BASE + (sda * PAD_REG_ADRS_BYTE_SIZE)); - PadReg_t *padRegScl = (PadReg_t*)(PADREG_BASE + (scl * PAD_REG_ADRS_BYTE_SIZE)); - - CLOCK_ENABLE(CLOCK_PAD); - padRegSda->PADIO0.BITS.POWER = 3; /* sda: Drive strength */ - padRegScl->PADIO0.BITS.POWER = 3; /* scl: Drive strength */ - CLOCK_DISABLE(CLOCK_PAD); - - CLOCK_ENABLE(CLOCK_GPIO); - GPIOREG->W_OUT |= ((True << sda) | (True << scl)); - CLOCK_DISABLE(CLOCK_GPIO); - - /* Enable i2c module */ - obj->membase->CR.BITS.I2C_MODULE_EN = True; -} - -/* See i2c.h for details */ -void fI2cFrequency(i2c_t *obj, uint32_t hz) -{ - /* Set user baud rate */ - uint32_t clockDivisor; - clockDivisor = ((fClockGetPeriphClockfrequency() / hz) >> 2) - 2; - obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK); - obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */ -} - -/* See i2c.h for details */ -int32_t fI2cStart(i2c_t *obj) -{ - /* Send start bit */ - SEND_COMMAND(I2C_CMD_START); - return I2C_API_STATUS_SUCCESS; -} - -/* See i2c.h for details */ -int32_t fI2cStop(i2c_t *obj) -{ - /* Send stop bit */ - SEND_COMMAND(I2C_CMD_STOP); - if (obj->membase->STATUS.WORD & (I2C_STATUS_CMD_FIFO_FULL_BIT | - I2C_STATUS_CMD_FIFO_OFL_BIT | - I2C_STATUS_BUS_ERR_BIT)) { - /* I2c error occured */ - return I2C_ERROR_BUS_BUSY; - } - return I2C_API_STATUS_SUCCESS; -} - -/* See i2c.h for details */ -int32_t fI2cReadB(i2c_t *obj, char *buf, int len) -{ - int32_t read = 0; - - while (read < len) { - - while(FIFO_OFL_CHECK); /* Wait till command overflow ends */ - - /* Send read command */ - SEND_COMMAND(I2C_CMD_RDAT8); - while(!RD_DATA_READY) { - if (I2C_BUS_ERR_CHECK) { - /* Bus error occured */ - return I2C_ERROR_BUS_BUSY; - } - } - buf[read++] = obj->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */ - - if(!(read>=len)) { - SEND_COMMAND(I2C_CMD_WDAT0); - } else { - /* No ack */ - SEND_COMMAND(I2C_CMD_WDAT1); - } - - /* check for FIFO underflow */ - if(I2C_UFL_CHECK) { - return I2C_EVENT_ERROR; - } - if(I2C_BUS_ERR_CHECK) { - /* Bus error */ - return I2C_ERROR_BUS_BUSY; - } - } - - return read; -} - -/* See i2c.h for details */ -int32_t fI2cWriteB(i2c_t *obj, const char *buf, int len) -{ - int32_t write = 0; - - while (write < len) { - - while(FIFO_OFL_CHECK); /* Wait till command overflow ends */ - - if(buf[write] == I2C_CMD_RDAT8) { - /* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13) - then as the command is read out (i.e. the FIFO goes empty), the WDAT8 command will be misinterpreted as a - RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */ - /* Send 0x13 bit wise */ - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT1); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT1); - SEND_COMMAND(I2C_CMD_WDAT1); - write++; - } else { - /* Send data */ - SEND_COMMAND(I2C_CMD_WDAT8); - SEND_COMMAND(buf[write++]); - } - SEND_COMMAND(I2C_CMD_VRFY_ACK); - - if (I2C_BUS_ERR_CHECK) { - /* Bus error */ - return I2C_ERROR_BUS_BUSY; - } - } - return write; -} - -#endif /* DEVICE_I2C */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c deleted file mode 100644 index 2e80f07f5d..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_lp_ticker_api.c +++ /dev/null @@ -1,82 +0,0 @@ -/** - ******************************************************************************* - * @file lpticker.c - * @brief Implementation of a Low Power Ticker functionality based on RTC - * @internal - * @author ON Semiconductor - * $Rev: $ - * $Date: $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a �ON Semiconductor�). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (�ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software�) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup lpticker - * - * @details - * This is Low Power ticker derived from RTC - * - */ - -#include "device.h" -#if DEVICE_LPTICKER - -#include "cmsis_nvic.h" -#include "lp_ticker_api.h" -#include "rtc.h" -#include "rtc_map.h" - -/* Initialize the RTC for low power ticker */ -void lp_ticker_init() -{ - fRtcInit(); -} - -/* Return the current RTC counter value in us */ -uint32_t lp_ticker_read() -{ - return (uint32_t)(fRtcRead() & 0xFFFFFFFF); /* TODO Truncating 64 bit value to 32 bit */ -} - -/* Set interrupt for specified time */ -void lp_ticker_set_interrupt(timestamp_t timestamp) -{ - /* The RTC Match register needs to be Set to the RTC alarm value */ - fRtcSetInterrupt(timestamp); -} - -void lp_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(Rtc_IRQn); -} - -/** Disable low power ticker interrupt - * - */ -void lp_ticker_disable_interrupt(void) -{ - fRtcDisableInterrupt(); -} - -/** Clear the low power ticker interrupt - * - */ -void lp_ticker_clear_interrupt(void) -{ - fRtcClearInterrupt(); -} - -#endif /* DEVICE_LPTICKER */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c deleted file mode 100644 index 42441d5d8f..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c +++ /dev/null @@ -1,171 +0,0 @@ -/** - ****************************************************************************** - * @file spi.c - * @brief Implementation of a IPC 7207 SPI master driver - * @internal - * @author ON Semiconductor - * @version $Rev: $ - * @date $Date: 2016-02-05 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup spi - * - * @details - * - */ -#if DEVICE_SPI - -#include "spi.h" -#include "clock.h" -#include "objects.h" -#include "spi_api.h" -#include "PeripheralPins.h" -#include "spi_ipc7207_map.h" -#include "crossbar.h" -#include "pad.h" -#include "mbed_assert.h" - -/** Initializes a spi device. - * @details - * - * @param obj A spi device instance. - * @param mosi pin to used as SPI MOSI - * @param miso pin to used as SPI MISO - * @param sclk pin to used as SPI SCLK - * @return None - */ -void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - uint32_t clockDivisor; - - /* determine the SPI to use */ - SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); - SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); - SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); - SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); - - SPIName spi_data_1 = (SPIName)pinmap_merge(spi_mosi, spi_miso); - SPIName spi_data_2 = (SPIName)pinmap_merge(spi_sclk, spi_ssel); - - obj->membase = (SpiIpc7207Reg_pt)pinmap_merge(spi_data_1, spi_data_2); - MBED_ASSERT((int)obj->membase != NC); - - /* Check device to be activated */ - if(obj->membase == SPI1REG) { - /* SPI 1 selected */ - CLOCK_ENABLE(CLOCK_SPI); /* Enable clock */ - } else { - /* SPI 2 selected */ - CLOCK_ENABLE(CLOCK_SPI2); /* Enable clock */ - } - - CLOCK_ENABLE(CLOCK_CROSSB); - /* Cross bar setting: Map GPIOs to SPI */ - pinmap_pinout(sclk, PinMap_SPI_SCLK); - pinmap_pinout(mosi, PinMap_SPI_MOSI); - - /* Configure GPIO Direction */ - CLOCK_ENABLE(CLOCK_GPIO); - GPIOREG->W_OUT |= ((True << sclk) | (True << mosi) | (True << ssel)); /* Set pins as output */ - GPIOREG->W_IN |= (True << miso); /* Set pin as input */ - - /* Pad settings */ - CLOCK_ENABLE(CLOCK_PAD); - pin_mode(sclk, PushPullPullDown); - pin_mode(mosi, PushPullPullDown); - - /* PAD drive strength */ - PadReg_t *padRegOffset = (PadReg_t*)(PADREG_BASE + (sclk * PAD_REG_ADRS_BYTE_SIZE)); - padRegOffset->PADIO0.BITS.POWER = True; /* sclk: Drive strength */ - padRegOffset->PADIO1.BITS.POWER = True; /* mosi: Drive strength */ - if(miso != NC) { - pinmap_pinout(miso, PinMap_SPI_MISO); /* Cross bar settings */ - pin_mode(miso, OpenDrainNoPull); /* Pad setting */ - padRegOffset->PADIO2.BITS.POWER = True; /* miso: Drive strength */ - } - if(ssel != NC) { - pinmap_pinout(ssel, PinMap_SPI_SSEL); /* Cross bar settings */ - pin_mode(ssel, PushPullPullUp); /* Pad setting */ - padRegOffset->PADIO3.BITS.POWER = True; /* ssel: Drive strength */ - SPI1REG->SLAVE_SELECT.BITS.SS_ENABLE = SPI_SLAVE_SELECT_NORM_BEHAVE; /* Slave select: Normal behavior */ - } - CLOCK_DISABLE(CLOCK_PAD); - CLOCK_DISABLE(CLOCK_GPIO); - CLOCK_DISABLE(CLOCK_CROSSB); - - /* disable/reset the spi port: Clear control register*/ - obj->membase->CONTROL.WORD = False; - - /* set default baud rate to 1MHz */ - clockDivisor = ((fClockGetPeriphClockfrequency() / SPI_DEFAULT_SPEED) >> True) - True; - obj->membase->FDIV = clockDivisor; - - /* set tx/rx fifos watermarks */ /* TODO water mark level 1 byte ?*/ - obj->membase->TX_WATERMARK = True; - obj->membase->RX_WATERMARK = True; - - /* DIsable and clear IRQs */ /* TODO sync api, do not need irq ?*/ - obj->membase->IRQ_ENABLE = False; - obj->membase->IRQ_CLEAR = SPI_BYTE_MASK; /* Clear all */ - - /* configure slave select */ - obj->membase->SLAVE_SELECT.WORD = SPI_SLAVE_SELECT_DEFAULT; - obj->membase->SLAVE_SELECT_POLARITY = False; - - /* Configure control register parameters: 8 bits, master, CPOL = 0, Idle low. CPHA = 0, First transmit occurs before first edge of SCLK. MSB first. Sample incoming data on opposite edge of SCLK from when outgoing data is driven. enable the spi port */ - obj->membase->CONTROL.WORD = SPI_DEFAULT_CONFIG; -} - -/** Close a spi device. - * @details - * - * @param obj The spi device to close. - * @return None - */ -void fSpiClose(spi_t *obj) -{ - /* disable the spi port */ - obj->membase->CONTROL.BITS.ENABLE = False; - - /* disable interruption associated with spi */ - NVIC_DisableIRQ(obj->irq); -} - -/** - * Write data to an SPI device. - * The data is written from the buffer into the transmit register. - * This function blocks untill write and read happens. - * - * @param obj The device to write to. - * @param buf The buffer to write from (the contents of the buffer may not be modified). - * @return the value received during send - */ -int fSpiWriteB(spi_t *obj, uint32_t const buf) -{ - int byte; - - while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */ - obj->membase->TX_DATA = buf; - - while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */ - byte = obj->membase->RX_DATA; - return byte; -} - -#endif /* DEVICE_SPI */ \ No newline at end of file diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_trng.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_trng.h deleted file mode 100644 index 75439d8a52..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_trng.h +++ /dev/null @@ -1,42 +0,0 @@ -/** - ****************************************************************************** - * @file ncs36510_trng.h - * @brief Header file for ncs36510_trng_api.c. - * @internal - * @author ON Semiconductor. - * $Rev: $ - * $Date: $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup TRNG header - * - */ - -#ifndef RANDOM_H_ -#define RANDOM_H_ - -#define TRNG_SLOW_MODE 0 -#define TRNG_FAST_MODE 1 - -#define TRNG_DISABLE 0 -#define TRNG_ENABLE 1 - -#define TRNG_ON_READ_EVENT 1 - -#endif /* RANDOM_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_trng_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_trng_api.c deleted file mode 100644 index c9842e3842..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_trng_api.c +++ /dev/null @@ -1,113 +0,0 @@ -/** - ****************************************************************************** - * @file trng_api.c - * @brief Implementation of TRNG functionality. - * @internal - * @author ON Semiconductor. - * $Rev: $ - * $Date: $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup TRNG - * - */ -#if DEVICE_TRNG - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ -#include "trng_api.h" -#include "memory_map.h" -#include "ncs36510_trng.h" -#include "clock.h" -#include "mbed_wait_api.h" - -/************************************************************************************************* -* * -* Functions * -* * -*************************************************************************************************/ - - -void trng_init(trng_t *obj) -{ - /* Enable TRNG */ - CLOCK_ENABLE(CLOCK_RAND); - - /* Initialize TRNG */ - RANDREG->CONTROL.WORD = False; - - return; -} -void trng_free(trng_t *obj) -{ - /* Stop TRNG */ - RANDREG->CONTROL.WORD = False; - - /* Disable TRNG */ - CLOCK_DISABLE(CLOCK_RAND); - - return; -} - -int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) -{ - uint32_t MSLRandom = 0, Index, TempLen, *TempPtr = (uint32_t*)output; - - RANDREG->CONTROL.BITS.METASTABLE_LATCH_EN = TRNG_ENABLE; /* ENable MSL TRNG */ - RANDREG->CONTROL.BITS.MEATSTABLE_SPEED = TRNG_FAST_MODE; /* Meta-stable Latch TRNG Speed Control */ - RANDREG->CONTROL.BITS.MODE = TRNG_ON_READ_EVENT; /* TRNG is only updated on a read event of the TRNG register */ - - wait_us(1); /* Wait till MSL generates random number after enable for the first time */ - - TempLen = length / 4; - - for(Index = 0; Index < TempLen; Index++) - { - MSLRandom = RANDREG->METASTABLE_LATCH_VAL; - *TempPtr++ = MSLRandom ; - } - - TempLen = length % 4; - Index *= 4; - - if(TempLen-- > 0) - { - MSLRandom = RANDREG->METASTABLE_LATCH_VAL; - *(output + Index++) = (MSLRandom >> 0) & 0xFF; - if(TempLen-- > 0) - { - *(output + Index++) = (MSLRandom >> 8) & 0xFF; - if(TempLen-- > 0) - { - *(output + Index++) = (MSLRandom >> 16) & 0xFF; - } - } - } - - RANDREG->CONTROL.BITS.METASTABLE_LATCH_EN = TRNG_DISABLE; /* Disable MSL */ - - *output_length = Index; - - return 0; /* Success */ -} - -#endif /* DEVICE_TRNG */ \ No newline at end of file diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c deleted file mode 100644 index 8ae3b1a341..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file us_ticker_api.h - * @brief Implementation of a Timer driver - * @internal - * @author ON Semiconductor - * $Rev: $ - * $Date: 2015-11-15 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup timer -*/ - -#include -#include "timer_ncs36510.h" - -#define US_TIMER TIMER0 -#define US_TICKER TIMER1 - -static int us_ticker_inited = 0; - -static void us_timer_init(void); - -static uint32_t us_ticker_target = 0; -static volatile uint16_t msb_counter = 0; - -void us_ticker_init(void) -{ - if (!us_ticker_inited) { - us_timer_init(); - } -} - -/******************************************************************************* - * Timer for us timing reference - * - * Uptime counter for scheduling reference. It uses TIMER0. - * The NCS36510 does not have a 32 bit timer nor the option to chain timers, - * which is why a software timer is required to get 32-bit word length. - ******************************************************************************/ -/* TODO - Need some sort of load value/prescale calculation for non-32MHz clock */ -/* TODO - How is overflow handled? */ - -/* Timer 0 for free running time */ -extern void us_timer_isr(void) -{ - TIM0REG->CLEAR = 0; - msb_counter++; -} - -/* Initializing TIMER 0(TImer) and TIMER 1(Ticker) */ -static void us_timer_init(void) -{ - /* Enable the timer0 periphery clock */ - CLOCK_ENABLE(CLOCK_TIMER0); - /* Enable the timer0 periphery clock */ - CLOCK_ENABLE(CLOCK_TIMER1); - - /* Timer init */ - /* load timer value */ - TIM0REG->LOAD = 0xFFFF; - - /* set timer prescale 32 (1 us), mode & enable */ - TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) | - (TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS) | - (TIMER_ENABLE_BIT << TIMER_ENABLE_BIT_POS)); - - /* Ticker init */ - /* load timer value */ - TIM1REG->LOAD = 0xFFFF; - - /* set timer prescale 32 (1 us), mode & enable */ - TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) | - (TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS)); - - /* Register & enable interrupt associated with the timer */ - NVIC_SetVector(Tim0_IRQn,(uint32_t)us_timer_isr); - NVIC_SetVector(Tim1_IRQn,(uint32_t)us_ticker_isr); - - /* Clear pending irqs */ - NVIC_ClearPendingIRQ(Tim0_IRQn); - NVIC_ClearPendingIRQ(Tim1_IRQn); - - /* Setup NVIC for timer */ - NVIC_EnableIRQ(Tim0_IRQn); - NVIC_EnableIRQ(Tim1_IRQn); - - us_ticker_inited = 1; -} - -/* Reads 32 bit timer's current value (16 bit s/w timer | 16 bit h/w timer) */ -uint32_t us_ticker_read() -{ - - if (!us_ticker_inited) { - us_timer_init(); - } - - NVIC_DisableIRQ(Tim0_IRQn); - uint32_t retval, tim0cval; - /* Get the current tick from the hw and sw timers */ - tim0cval = TIM0REG->VALUE; /* read current time */ - retval = (0xFFFF - tim0cval); /* subtract down count */ - - if (TIM0REG->CONTROL.BITS.INT) { - us_timer_isr(); /* handle ISR again */ - NVIC_ClearPendingIRQ(Tim0_IRQn); - retval = (0xFFFF - TIM0REG->VALUE); - } - retval |= msb_counter << 16; /* add software bits */ - NVIC_EnableIRQ(Tim0_IRQn); - return retval; -} - -void us_ticker_fire_interrupt(void) -{ - us_ticker_target = 0; - NVIC_SetPendingIRQ(Tim1_IRQn); -} - -/******************************************************************************* - * Event Timer - * - * Schedules interrupts at given (32bit)us interval of time. It uses TIMER1. - * The NCS36510 does not have a 32 bit timer nor the option to chain timers, - * which is why a software timer is required to get 32-bit word length. - *******************************************************************************/ -/* TODO - Need some sort of load value/prescale calculation for non-32MHz clock */ - -/* TImer 1 disbale interrupt */ -void us_ticker_disable_interrupt(void) -{ - /* Disable the TIMER1 interrupt */ - TIM1REG->CONTROL.BITS.ENABLE = 0x0; -} - -/* TImer 1 clear interrupt */ -void us_ticker_clear_interrupt(void) -{ - /* Clear the Ticker (TIMER1) interrupt */ - TIM1REG->CLEAR = 0; -} - -/* Setting TImer 1 (ticker) */ -inline static void ticker_set(uint32_t count) -{ - /* Disable TIMER1, load the new value, and re-enable */ - TIM1REG->CONTROL.BITS.ENABLE = 0; - TIM1REG->LOAD = count; - TIM1REG->CONTROL.BITS.ENABLE = 1; -} - -/* TImer 1 - ticker ISR */ -extern void us_ticker_isr(void) -{ - /* Clear IRQ flag */ - TIM1REG->CLEAR = 0; - - if (us_ticker_target > 0) { - --us_ticker_target; - ticker_set(0xFFFF); - } else { - us_ticker_irq_handler(); - } -} - -/* Set timer 1 ticker interrupt */ -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - int32_t delta = timestamp - us_ticker_read(); - // we got 16 bit timer, use upper 16bit as a simple counter how many times - // we need to schedule full range ticker count - us_ticker_target = (uint32_t)delta >> 16; - - if (delta <= 0) { - /* This event was in the past */ - //us_ticker_irq_handler(); - // This event was in the past. - // Set the interrupt as pending, but don't process it here. - // This prevents a recurive loop under heavy load - // which can lead to a stack overflow. - NVIC_SetPendingIRQ(Tim1_IRQn); - - return; - } - - // we set the full reminder of 16 bit, the next ISR will do the upper part - ticker_set(delta & 0xFFFF); -} - -void us_ticker_free(void) -{ - -} diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h deleted file mode 100644 index de6146728e..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h +++ /dev/null @@ -1,204 +0,0 @@ -/** - ****************************************************************************** - * @file Objects.h - * @brief Implements an assertion. - * @internal - * @author ON Semiconductor - * $Rev: 0.1 $ - * $Date: 2015-11-06 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup debug - */ -#ifndef OBJECTS_H_ -#define OBJECTS_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#include "gpio_map.h" -#include "uart_16c550_map.h" -#include "PinNames.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "target_config.h" - -typedef enum { - FlowControlNone_1, - FlowControlRTS_1, - FlowControlCTS_1, - FlowControlRTSCTS_1 -} FlowControl_1; - -struct serial_s { - Uart16C550Reg_pt UARTREG; - FlowControl_1 FlowCtrl; - IRQn_Type IRQType; - int index; -}; - -typedef struct _gpio_t { - GpioReg_pt GPIOMEMBASE; - PinName gpioPin; - uint32_t gpioMask; - -} gpio_t; - - -/* TODO: This is currently a dummy structure; implementation will be done along - * with the sleep API implementation - */ -typedef struct sleep_s { - uint32_t timeToSleep; /* 0: Use sleep type variable to select low power mode; Noz-zero: Selects sleep type based on timeToSleep duration using table 1. sleep below */ - uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */ -} sleep_t; - -/* Table 1. Sleep - ___________________________________________________________________________________ - | Sleep duration | Sleep Type | - |-------------------------------------------------------------------|---------------| - | > Zero AND <= SLEEP_DURATION_SLEEP_MAX | sleep | - | > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX | deepsleep | - | > SLEEP_DURATION_DEEPSLEEP_MAX | coma | - |___________________________________________________________________|_______________| - -*/ - -struct gpio_irq_s { - uint32_t pin; - uint32_t pinMask; - GpioReg_pt GPIOMEMBASE; -}; - -typedef struct { - - /* options to configure the ADC */ - uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */ - uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */ - uint8_t measurementType; /**< 1= Absolute 0= Differential */ - uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */ - uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */ - uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/ - uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */ - uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/ - uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */ - uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */ - -} analog_config_s; - -struct analogin_s { - - analog_config_s *adcConf; - AdcReg_pt adcReg; - PinName pin; - uint8_t pinFlag; - uint32_t ADC_Offset_Value; -}; - -struct pwmout_s { - - PwmReg_pt pwmReg; -}; - -struct port_s { - GpioReg_pt GPIOMEMBASE; - PortName port; - uint32_t mask; -}; - -typedef enum { - littleEndian = 0, - bigEndian -} spi_ipc7207_endian_t, *spi_ipc7207_endian_pt; - -/** Type for the clock polarity. */ -typedef enum { - activeLow = 0, - activeHigh -} spi_clockPolarity_t, *spi_clockPolarity_pt; - -/** Type for the clock phase. */ -typedef enum { - risingEdge = 0, - fallingEdge -} spi_clockPhase_t, *spi_clockPhase_pt; - -struct spi_s { - SpiIpc7207Reg_pt membase; /* Register address */ - IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */ - uint8_t irqEnable; /* IRQ enables for 8 IRQ sources: - * - bit 7 = Receive FIFO Full - * - bit 6 = Receive FIFO 'Half' Full (watermark level) - * - bit 5 = Receive FIFO Not Empty - * - bit 4 = Transmit FIFO Not Full - * - bit 3 = Transmit FIFO 'Half' Empty (watermark level) - * - bit 2 = Transmit FIFO Empty - * - bit 1 = Transfer Error - * - bit 0 = ssIn (conditionally inverted and synchronized to PCLK) - * (unused option in current implementation / irq 6 and 7 used) */ - uint8_t slaveSelectEnable; /* Slave Select enables (x4): - * - 0 (x4) = Slave select enable - * - 1 (x4) = Slave select disable */ - uint8_t slaveSelectBurst; /* Slave Select burst mode: - * - NO_BURST_MODE = Burst mode disable - * - BURST_MODE = Burst mode enable */ - uint8_t slaveSelectPolarity; /* Slave Select polarity (x4) for up to 4 slaves: - * - 0 (x4) = Slave select is active low - * - 1 (x4) = Slave select is active high */ - uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag - * - Value between 1 and 15 - * (unused option in current implementation / not txWatermark irq used) */ - uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag: - * - Value between 1 and 15 - * * (unused option in current implementation / rxWatermark fixed to 1) */ - spi_ipc7207_endian_t endian; /* Bits endianness: - * - LITTLE_ENDIAN = LSB first - * - BIG_ENDIAN = MSB first */ - uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge): - * - 0 = opposite to SDO sampling edge - * - 1 = same as SDO sampling edge */ - uint32_t baudrate; /* The expected baud rate. */ - spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */ - spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */ - uint8_t wordSize; /* The size word size in number of bits. */ - uint8_t Mode; - uint32_t event; -}; - -struct i2c_s { - uint32_t baudrate; /**< The expected baud rate. */ - uint32_t I2cStatusFromInt; - uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */ - uint8_t irqEnable; /**< IRQs to be enabled */ - I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */ - IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */ - //queue_pt rxQueue; /**< The receive queue for the device instance. */ -}; - -struct trng_s { - RandReg_pt membase; /**< The memory base for the device's registers. */ -}; - -#ifdef __cplusplus -} -#endif - -#endif //OBJECTS_H_ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/pad.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/pad.h deleted file mode 100644 index 9aa7c39045..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/pad.h +++ /dev/null @@ -1,86 +0,0 @@ -/** -****************************************************************************** -* @file pad.h -* @brief PAD Power management support code -* @internal -* @author ON Semiconductor -* $Rev: 2848 $ -* $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup pad -* -* @details -*/ - -#ifndef _PAD_H_ -#define _PAD_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "types.h" -#include "memory_map.h" -#include "gpio_map.h" -#include "pad_map.h" -#include "crossbar.h" -#include "clock.h" - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - - - -#define CROSS_REG_ADRS_BYTE_SIZE 4 - -#define PAD_REG_ADRS_BYTE_SIZE 4 - - -/************************************************************************************************* -* * -* Functions * -* * -*************************************************************************************************/ - -/** -* @brief -* Configures the PAD IO for desired behavior -*/ -extern void fPadInit(); - -/** -* @brief -* Set ouptput drive strength, output drive type & pull type for PAD IO -* -* @param PadNum Pad number -* @param OutputDriveStrength Ouput drive strength. Ref Table: O/p drive strength -* @param OutputDriveType Push/pull: 0; opern dran: 1 -* @param PullType Pull down active: 0; no pull active:1 or 2; pull up active: 3 -* -* @return true for success; false for invalid parameters -*/ -extern boolean fPadIOCtrl(uint8_t, uint8_t, uint8_t, uint8_t); - -#endif //_PAD_H_ \ No newline at end of file diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h deleted file mode 100644 index 63a99a45d5..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/pad_map.h +++ /dev/null @@ -1,239 +0,0 @@ -/** -****************************************************************************** -* @file pad_map.h -* @brief PAD hw module register map -* @internal -* @author ON Semiconductor -* $Rev: 3166 $ -* $Date: 2015-01-19 11:28:08 +0530 (Mon, 19 Jan 2015) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup pad -* -* @details -*/ - -#ifndef PAD_MAP_H_ -#define PAD_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "architecture.h" - -/************************************************************************************************* -* * -* Symbolic Constants * -* * -*************************************************************************************************/ - -/** no pull up nor pull down */ -#define PAD_PULL_NONE (uint8_t)0x01 -/** pull down */ -#define PAD_PULL_DOWN (uint8_t)0x00 -/** pull up */ -#define PAD_PULL_UP (uint8_t)0x03 - -/** Drive strength */ -#define PAD_DRIVE_L0 (uint8_t)0x00 -#define PAD_DRIVE_L1 (uint8_t)0x01 -#define PAD_DRIVE_L2 (uint8_t)0x02 -#define PAD_DRIVE_L3 (uint8_t)0x03 -#define PAD_DRIVE_L4 (uint8_t)0x04 -#define PAD_DRIVE_L5 (uint8_t)0x05 -#define PAD_DRIVE_L6 (uint8_t)0x06 - -/** output configuration push/pull */ -#define PAD_OUTCFG_PUSHPULL (uint8_t)0x00 -/** output configuration open drain */ -#define PAD_OOUTCFG_OPENDRAIN (uint8_t)0x01 - -/** lowest power PAD configuration, shall be the default */ -#define PAD_LOW_POWER (PAD_PULL_NONE | (PAD_DRIVE_L0<<2) | (PAD_OOUTCFG_OPENDRAIN<<5)) - -/** custom Power PAD configuration */ -#define PAD_OUTPUT_PN_L1_OD (PAD_PULL_NONE | (PAD_DRIVE_L1<<2) | (PAD_OOUTCFG_OPENDRAIN<<5)) -#define PAD_INPUT_PD_L1_PP (PAD_PULL_DOWN | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5)) -#define PAD_UNUSED_PD_L1_PP (PAD_PULL_DOWN | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5)) - -#define PAD_UART_TX (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OUTCFG_PUSHPULL<<5)) -#define PAD_UART_RX (PAD_PULL_UP | (PAD_DRIVE_L1<<2) | (PAD_OOUTCFG_OPENDRAIN<<5)) - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -/** Pad control - * The pad control peripheral is used to setup any necessary pad parameters - * not controlled directly via the cross-bar: output drive strength, - * push/pull control and output drive type. - */ -typedef struct { - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO0; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO1; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO2; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO3; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO4; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO5; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO6; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO7; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO8; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO9; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO10; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO11; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO12; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO13; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO14; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO15; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO16; - union { - struct { - __IO uint32_t PULL :2; /**< 00 – Pull-down active, 01 – No pull active, 10 – No pull active, 11 – Pull-up active*/ - __IO uint32_t POWER :3; /**< Output Drive Strength*/ - __IO uint32_t TYPE :1; /**< Output Type: 0 – Push/Pull, 1 – Open Drain*/ - } BITS; - __IO uint32_t WORD; - } PADIO17; -} PadReg_t, *PadReg_pt; - -#endif /* PAD_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/pinmap.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/pinmap.c deleted file mode 100644 index 55effa2cfa..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/pinmap.c +++ /dev/null @@ -1,83 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* Orion specific header files */ - -#include "pad.h" - -/* MBED header files */ -#include "pinmap.h" - -void pin_function(PinName pin, int function) -{ - /** - Enable the clock for PAD peripheral device */ - CLOCK_ENABLE(CLOCK_CROSSB); - - /* Note: GPIO 0,1,2,3 are used for UART 1, GPIO 8,9 are used for UART 2 */ - CrossbReg_pt crossBar = (CrossbReg_t *)(CROSSBREG_BASE + (pin * CROSS_REG_ADRS_BYTE_SIZE)); - crossBar->DIOCTRL0 = function; - - /** - Disable the clock for PAD peripheral device */ - CLOCK_DISABLE(CLOCK_CROSSB); -} - -void pin_mode(PinName pin, PinMode mode) -{ - /** - Get PAD IO register address for the PAD number */ - PadReg_t *padRegOffset = (PadReg_t*)(PADREG_BASE + (pin * PAD_REG_ADRS_BYTE_SIZE)); - - /** - Enable the clock for PAD peripheral device */ - CLOCK_ENABLE(CLOCK_PAD); - - switch (mode) { - case PushPullPullDown: - padRegOffset->PADIO0.BITS.TYPE = PAD_OUTCFG_PUSHPULL; - padRegOffset->PADIO0.BITS.PULL = PAD_PULL_DOWN; - break; - - case PushPullNoPull: - padRegOffset->PADIO0.BITS.TYPE = PAD_OUTCFG_PUSHPULL; - padRegOffset->PADIO0.BITS.PULL = PAD_PULL_NONE; - break; - - case PushPullPullUp: - padRegOffset->PADIO0.BITS.TYPE = PAD_OUTCFG_PUSHPULL; - padRegOffset->PADIO0.BITS.PULL = PAD_PULL_UP; - break; - - case OpenDrainPullDown: - padRegOffset->PADIO0.BITS.TYPE = PAD_OOUTCFG_OPENDRAIN; - padRegOffset->PADIO0.BITS.PULL = PAD_PULL_DOWN; - break; - - case OpenDrainNoPull: - padRegOffset->PADIO0.BITS.TYPE = PAD_OOUTCFG_OPENDRAIN; - padRegOffset->PADIO0.BITS.PULL = PAD_PULL_NONE; - break; - - case OpenDrainPullUp: - padRegOffset->PADIO0.BITS.TYPE = PAD_OOUTCFG_OPENDRAIN; - padRegOffset->PADIO0.BITS.PULL = PAD_PULL_UP; - break; - - default: - break; - } - - /** - Disable the clock for PAD peripheral device */ - CLOCK_DISABLE(CLOCK_PAD); - -} diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h deleted file mode 100644 index d452fda648..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h +++ /dev/null @@ -1,95 +0,0 @@ -/** -****************************************************************************** -* @file pmu_map.h -* @brief PMU hw module register map -* @internal -* @author ON Semiconductor -* $Rev: 3372 $ -* $Date: 2015-04-22 12:18:18 +0530 (Wed, 22 Apr 2015) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup pmu -* -* @details -*/ - -#ifndef PMU_MAP_H_ -#define PMU_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "architecture.h" - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -/** PMU control - * The Power Management Unit (PMU) is used to control the differing power modes. - */ -typedef struct { - union { - struct { - __IO uint32_t ENCOMA :1; /**< 0- Sleep or SleepDeep depending on System Control Register (see WFI and WFE instructions), 1 – Coma */ - __IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */ - __IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */ - __IO uint32_t EXT32K :1; /**< External 32.768kHz Enable: 0 – Disabled (off), 1 – Enabled (on), Hardware guarantees that this oscillator cannot be powered if the internal 32kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */ - __IO uint32_t INT32K :1; /**< Internal 32kHz Enable: 0 – Enabled (on), 1 – Disabled (Off), Hardware guarantees that this oscillator cannot be powered down if the external 32.768kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */ - __IO uint32_t INT32M :1; /**< Internal 32MHz Enable: 0 – Enabled (on), 1 – Disabled (off), This bit will automatically get cleared when exiting Coma, or SleepDeep modes of operation. This bit should be set by software after switching over to the external 32MHz oscillator using the Oscillator Select bit in the Clock Control register */ - __IO uint32_t C1V1:1; /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */ - __IO uint32_t N1V1:1; /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */ - __IO uint32_t DBGPOW :1; /**< Debugger Power Behavior: 0 – Normal power behavior when the debugger is present, 1 – When debugger is present the ASIC can only enter SleepDeep mode and FVDDH and FVDDL always remain powered. The 32MHz oscillators can never be powered down in this mode either. */ - __IO uint32_t UVIC:1; /**< Under voltage indicator control: 0 - disabled, 1 - enabled */ - __IO uint32_t UVII:1; /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */ - __IO uint32_t UVIR:1; /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */ - } BITS; - __IO uint32_t WORD; - } CONTROL; /* 0x4001D000 */ - union { - struct { - __I uint32_t BATTDET:1; /**< Detected battery: 0 - 1V, 1 - 3V */ - __I uint32_t UVIC:1; /**< Under voltage status: 0 - normal, 1 - low */ - - } BITS; - __IO uint32_t WORD; - } STATUS; /* 0x4001D004 */ - - __IO uint32_t PLACEHOLDER; /* 0x4001D008 */ - __IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */ /* 0x4001D00C */ - __IO uint32_t PLACEHOLDER1; /* 0x4001D010 */ - __IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */ /* 0x4001D014 */ - union { - struct { - __IO uint32_t TH:6; /**< Threshold */ - __I uint32_t PAD:2; - __I uint32_t UVIVAL:6; /**< UVI value */ - } BITS; - __IO uint32_t WORD; - } UVI_TBASE; /* 0x4001D018 */ - __IO uint32_t SRAM_TRIM; /* 0x4001D01C */ - -} PmuReg_t, *PmuReg_pt; - -#endif /* PMU_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/port_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/port_api.c deleted file mode 100644 index 4975a3697c..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/port_api.c +++ /dev/null @@ -1,162 +0,0 @@ -/** - ****************************************************************************** - * @file port_api.c - * @brief Implementation of a port API - * @internal - * @author ON Semiconductor - * $Rev: - * $Date: - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - */ -#include "gpio.h" -#include "gpio_api.h" -#include "port_api.h" -#include "pinmap.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -/** Get the pin name from the port's pin number - * - * @param port The port name - * @param pin_n The pin number within the specified port - * @return The pin name for the port's pin number - */ -PinName port_pin(PortName port, int pin_n) -{ - return((PinName)(pin_n)); -} - -/** Initilize the port - * - * @param obj The port object to initialize - * @param port The port name - * @param mask The bitmask to identify which bits in the port should be included (0 - ignore) - * @param dir The port direction - */ -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - uint8_t i; - PinName pin; - - /* Store the port mask in obj */ - obj->mask = mask; - - /* Store the port name in obj */ - obj->port = port; - - /* Store GPIO base address */ - obj->GPIOMEMBASE = GPIOREG; - - for (i=0; imask & (1<port, i); - - /* Set the pin as GPIO */ - gpio_set(pin); - } - } - - /* Call function to set pin direction */ - port_dir(obj, dir); -} - -/** Set the input port mode - * - * @param obj The port object - * @param mode THe port mode to be set - */ -void port_mode(port_t *obj, PinMode mode) -{ - uint8_t i = 0; - PinName pin; - - /* For each pin in the mask, set the mode to that defined in "mode" parameter */ - for (i=0; i < NUMBER_OF_GPIO; i++) { - /* check for valid pin */ - if (obj->mask & (1<port, i); - - /* Set the mode for the pin */ - pin_mode(pin, mode); - } - } -} - -/** Set port direction (in/out) - * - * @param obj The port object - * @param dir The port direction to be set - */ -void port_dir(port_t *obj, PinDirection dir) -{ - /* Enable the GPIO clock */ - CLOCK_ENABLE(CLOCK_GPIO); - - if (dir == PIN_INPUT) { - obj->GPIOMEMBASE->W_IN = obj->mask; - } else if (dir == PIN_OUTPUT) { - obj->GPIOMEMBASE->W_OUT = obj->mask; - } - - /* Disable the GPIO clock */ - CLOCK_DISABLE(CLOCK_GPIO); -} - -/** Write value to the port - * - * @param obj The port object - * @param value The value to be set - */ -void port_write(port_t *obj, int value) -{ - /* Enable the GPIO clock */ - CLOCK_ENABLE(CLOCK_GPIO); - - obj->GPIOMEMBASE->R_STATE_W_SET = value;//(obj->mask & value); - obj->GPIOMEMBASE->R_IRQ_W_CLEAR = ~value;//(obj->mask ^ value); - - /* Disable the GPIO clock */ - CLOCK_DISABLE(CLOCK_GPIO); -} - -/** Read the current value on the port - * - * @param obj The port object - * @return An integer with each bit corresponding to an associated port pin setting - */ -int port_read(port_t *obj) -{ - int gpio_level = 0; - - /* Enable the GPIO clock */ - CLOCK_ENABLE(CLOCK_GPIO); - - gpio_level = obj->GPIOMEMBASE->R_STATE_W_SET; - - /* Disable the GPIO clock */ - CLOCK_DISABLE(CLOCK_GPIO); - - return(gpio_level); -} - -#endif diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h deleted file mode 100644 index b815a0d0d3..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/pwm_map.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - ****************************************************************************** - * @file pwm_map.h - * @brief PWM HW register map - * @internal - * @author ON Semiconductor - * $Rev: 3378 $ - * $Date: 2015-04-28 13:38:36 +0530 (Tue, 28 Apr 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup pwm - * - * @details - *

- * PWM HW register map description - *

- * - *

Reference document(s)

- *

- * - * IPC7205 APB PWM Design Specification v1.1 - *

- */ - -#ifndef PWM_MAP_H_ -#define PWM_MAP_H_ - -#include "architecture.h" - -/** Power management Control HW Structure Overlay */ -typedef struct { - __O uint32_t DUTYCYCLE; - __O uint32_t PWM_ENABLE; - __O uint32_t PWM_DISABLE; - __O uint32_t PRESCALE_ENABLE; - __O uint32_t PRESCALE_DISABLE; - union { - struct { - __I uint32_t CUR_DUTY_CYCLE_VALUE : 8; /** Curent value of duty Cycle */ - __I uint32_t CUR_PRE_SCALER_STATE : 1; /** Current state of the prescaler. ‘1’ the prescaler is enabled. ‘0’ the prescaler is disabled. */ - __I uint32_t CUR_PWM_ENABLE_STATE : 1; /** Current state of the PWM. ‘1’ the PWM is enabled. ‘0’ the PWM is disabled. */ - __I uint32_t CUR_PWM_OUTPUT_STATE : 1; /** Current state of PWM output */ - } BITS; - __I uint32_t WORD; - } READ_CONFIG_STATUS; -} PwmReg_t, *PwmReg_pt; -#endif /* PWM_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c deleted file mode 100644 index 255c41e2f8..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/pwmout_api.c +++ /dev/null @@ -1,214 +0,0 @@ -/** - ****************************************************************************** - * @file pwmout_api.c - * @brief Implementation of a PWM driver - * @internal - * @author ON Semiconductor - * $Rev: - * $Date: - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal -*/ -#include "pwmout_api.h" -#include "PeripheralPins.h" -#include "mbed_assert.h" -#include "clock.h" - -#if DEVICE_PWMOUT - -/** - * \defgroup hal_pwmout Pwmout hal functions - * @{ - */ - -/** Initialize the pwm out peripheral and configure the pin - * - * @param obj The pwmout object to initialize - * @param pin The pwmout pin to initialize - */ -void pwmout_init(pwmout_t *obj, PinName pin) -{ - /* Get the base address of the PWM register using the pinmap functions ; pwmout_s struct contains base address only */ - PWMName pwm; - - pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(pwm != (PWMName)NC); - - pinmap_pinout(pin, PinMap_PWM); - - obj->pwmReg = (PwmReg_pt)pwm; - MBED_ASSERT(obj->pwmReg != 0x00000000); - - CLOCK_ENABLE(CLOCK_PWM); - - /* Configuration parameters of duty cycle 0x4000B000, and prescaler 0x4000B00C, shall be set to default values */ - /* Duty cycle shall be 50% and prescaler shall be disabled by default */ - obj->pwmReg->DUTYCYCLE = 0x80; - - /* Write the PWM output enable register 0x4000B004, to 1 */ - obj->pwmReg->PWM_ENABLE = 0x1; - - obj->pwmReg->PRESCALE_DISABLE = 0x1; - -} - -/** Deinitialize the pwmout object - * - * @param obj The pwmout object - */ -void pwmout_free(pwmout_t *obj) -{ - /* Write the PWM output disable register 0x4000B008, to 1 */ - obj->pwmReg->PWM_DISABLE = 0x1; -} - -/** Set the output duty-cycle in range <0.0f, 1.0f> - * - * Value 0.0f represents 0 percentage, 1.0f represents 100 percent. - * @param obj The pwmout object - * @param percent The floating-point percentage number - */ -void pwmout_write(pwmout_t *obj, float percent) -{ - if (percent == 0.0) { - obj->pwmReg->DUTYCYCLE = 0x00; - } else if (percent == 1.0) { - obj->pwmReg->DUTYCYCLE = 0xFF; - } else { - /* Write the duty cycle config register 0x4000B000, with the value passed on */ - /* ((percent * 255) + 1) is the duty cycle. Plus 1 is for accounting for round off errors; like a ceil function */ - obj->pwmReg->DUTYCYCLE = (uint8_t)((percent * 255) + 1); - } -} - -/** Read the current float-point output duty-cycle - * - * @param obj The pwmout object - * @return A floating-point output duty-cycle - */ -float pwmout_read(pwmout_t *obj) -{ - float retVal = 0.0; - float dc = 0.0; - - /* Read out the value of duty cycle register 0x4000B000 and return as a percent */ - /* Read value / 255 is the percent returned */ - dc = obj->pwmReg->DUTYCYCLE; - retVal = dc/ (float)255; - - return(retVal); -} - -/** Set the PWM period specified in seconds, keeping the duty cycle the same - * - * Periods smaller than microseconds (the lowest resolution) are set to zero. - * @param obj The pwmout object - * @param seconds The floating-point seconds period - */ -void pwmout_period(pwmout_t *obj, float seconds) -{ - /* Cannot be configured, prescaler is either 256 or 4096 */ - return; -} - -/** Set the PWM period specified in miliseconds, keeping the duty cycle the same - * - * @param obj The pwmout object - * @param ms The milisecond period - */ -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - /* Cannot be configured, prescaler is either 256 or 4096 */ - return; -} - -/** Set the PWM period specified in microseconds, keeping the duty cycle the same - * - * @param obj The pwmout object - * @param us The microsecond period - */ -void pwmout_period_us(pwmout_t *obj, int us) -{ - /* Cannot be configured, prescaler is either 256 or 4096 */ - return; -} - -/** Set the PWM pulsewidth specified in seconds, keeping the period the same. - * - * @param obj The pwmout object - * @param seconds The floating-point pulsewidth in seconds - */ -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - /* Pulse width can never be in seconds since the period - * itself is limited to either 8uSec or 128uSec - */ - return; -} - -/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same. - * - * @param obj The pwmout object - * @param ms The floating-point pulsewidth in miliseconds - */ -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - - /* Pulse width can never be in seconds since the period - * itself is limited to either 8uSec or 128uSec - */ - return; -} - -/** Set the PWM pulsewidth specified in microseconds, keeping the period the same. - * - * @param obj The pwmout object - * @param us The floating-point pulsewidth in microseconds - */ -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - int pulseWidth = 0; - - /* Check if the uSec value is greater than 128uSec, if so reject */ - if (us > 128) { - return; - } - /* If pulsewidth is less than 128uSec, set the prescaler to 4096 - * by enabling prescale register 0x4000B00C to 1 */ - obj->pwmReg->PRESCALE_ENABLE = 0x1; - - /* Calculate the duty cycle based on the width of the pulse */ - /* ((255 * us) / 128) + 1 = duty cycle */ - pulseWidth = (int)((float)(255 * us)/(float)128) + 1; - if (us == 0) { - obj->pwmReg->DUTYCYCLE = 0x0; - } else if (us == 128) { - obj->pwmReg->DUTYCYCLE = 0xFF; - } else { - obj->pwmReg->DUTYCYCLE = (uint8_t)pulseWidth; - } -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} - -/**@}*/ - -#endif // DEVICE_PWMOUT diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/random_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/random_map.h deleted file mode 100644 index 7e25f21f89..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/random_map.h +++ /dev/null @@ -1,103 +0,0 @@ -/** -****************************************************************************** -* @file random_map.h -* @brief Randomizer hw module register map -* @internal -* @author ON Semiconductor -* $Rev: 3283 $ -* $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup random -* -* @details -*/ - -#ifndef RANDOM_MAP_H_ -#define RANDOM_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "architecture.h" - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -/** Random Number Generator Control HW Structure Overlay */ -typedef struct { - __IO uint32_t WR_SEED_RD_RAND; /* Seed set & random read reg - 0x40011000 */ - union { - struct { - __IO uint32_t MODE :1; /** Reference document(s) -*/ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "memory_map.h" -#include "rfAna.h" -#include "clock.h" - -/************************************************************************************************* -* * -* Global variables * -* * -*************************************************************************************************/ - -/** Rf channel and tx power lookup tables (constant) - * @details - * - * The rf channel table is used to program internal hardware register for different 15.4 rf channels. - * It has 16 entries corresponding to 16 15.4 channels. - * Entry 1 <-> Channel 11 - * ... - * Entry 16 <-> Channel 26 - * - * Each entry is compound of 4 items. - * Item 0: Rx Frequency integer divide portion - * Item 1: Rx Frequency fractional divide portion - * Item 2: Tx Frequency integer divide portion - * Item 3: Tx Frequency fractional divide portion - * - * The tx power table is used to program internal hardware register for different 15.4 tx power levels. - * It has 43 entries corresponding to tx power levels from -32dBm to +10dBm. - * Entry 1 <-> -32dB - * Entry 2 <-> -31dB - * ... - * Entry 2 <-> 9dB - * Entry 43 <-> +10dB - * - * Each entry is compound of 1 byte. - */ - -// RR: Making high side injection changes to RevD - -/** This rf LUT is built for high side injection, using low side injection - * would requiere to change this LUT. */ -const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000}, - {0x50,0x017F52,0x4B,0x014001}, - {0x51,0xFE29FB,0x4B,0x01E001}, - {0x51,0xFED4A6,0x4C,0xFE7FFF}, - {0x51,0xFF7F51,0x4C,0xFF1FFF}, - {0x51,0x0029FC,0x4C,0xFFC000}, - {0x51,0x00D4A7,0x4C,0x006000}, - {0x51,0x017F52,0x4C,0x010001}, - {0x52,0xFE29FB,0x4C,0x01A001}, - {0x52,0xFED4A6,0x4D,0xFE3FFF}, - {0x52,0xFF7F51,0x4D,0xFEDFFF}, - {0x52,0x0029FC,0x4D,0xFF8000}, - {0x52,0x00D4A7,0x4D,0x002000}, - {0x52,0x017F52,0x4D,0x00C001}, - {0x53,0xFE29FB,0x4D,0x016001}, - {0x53,0xFED4A6,0x4E,0xFDFFFE} -}; - -const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm - 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm - 0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm - 3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm - 13,14,15,16,17,18,19,20,20,20 - }; // +1dBm to +10 dBm - -/************************************************************************************************* -* * -* Functions * -* * -*************************************************************************************************/ - -void fRfAnaInit() -{ - // Enable rfana clock - CLOCK_ENABLE(CLOCK_RFANA); - - // Set PLL timing - RFANAREG->PLL_TIMING.BITS.PLL_RESET_TIME = 0x1E; // 30us - RFANAREG->PLL_TIMING.BITS.PLL_LOCK_TIME = 0x2F; // 47us - - // Set other parameters - RFANAREG->RX_CONTROL.BITS.LNA_GAIN_MODE = 0x1; // High Gain mode - RFANAREG->RX_CONTROL.BITS.ADC_DITHER_MODE = 0x0; // Dither mode disabled -} - -boolean fRfAnaIoctl (uint32_t request, void *argument) -{ - uint8_t channel, txPower; - - // Enable rfana clock (in case fRfAnaIoctl is used before call of fRfAnaInit) - CLOCK_ENABLE(CLOCK_RFANA); - - switch(request) { - case SET_RF_CHANNEL: - channel = *(uint8_t*)argument; - - // Set tx/rx integer/fractional divide portions - RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3]; - RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2]; - RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1]; - RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0]; - - // Set tx/rx vco trims - /** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done - * from trims stored in dedicated registers available in digital.*/ - if (channel < 19) { - RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4); - RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4); - } else { - RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4); - RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4); - } - break; - case SET_TX_POWER: - txPower = *(uint8_t*)argument; - - // Set tx power register - if ((txPower & 0x20) == 0) { - RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF); - } else { - RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF); - } - - break; - default: - return False; - } - return True; -} diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h deleted file mode 100644 index a2d5513d2d..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.h +++ /dev/null @@ -1,69 +0,0 @@ -/** -****************************************************************************** -* @file rfAna.h -* @brief Header of rfAna hw module functions -* @internal -* @author ON Semiconductor -* $Rev: 2848 $ -* $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup rfAna -*/ - -#ifndef RFANA_H_ -#define RFANA_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "types.h" - -/************************************************************************************************* -* * -* Symbolic Constants * -* * -*************************************************************************************************/ - -/** Miscellaneous I/O codes / - * @details - */ -#define SET_RF_CHANNEL (0x0) /**< Ioctl request code: Set Rf channel frequency */ -#define SET_TX_POWER (0x1) /**< Ioctl request code: Set Tx output power */ - -/************************************************************************************************* -* * -* Functions * -* * -*************************************************************************************************/ - -/** Function to initialize rfAna - * @details - */ -void fRfAnaInit(void); - -/** Function for miscellaneous I/O and control operations on rfAna - * @details - */ -boolean fRfAnaIoctl (uint32_t request, void *argument); - -#endif /* RFANA_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h deleted file mode 100644 index 65b2102ea2..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h +++ /dev/null @@ -1,124 +0,0 @@ -/** -****************************************************************************** -* @file rfAna_map.h -* @brief rfAna hw module register map -* @internal -* @author ON Semiconductor -* $Rev: 2953 $ -* $Date: 2014-09-15 18:13:01 +0530 (Mon, 15 Sep 2014) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup rfAna -* -* @details -*

-* Rf and Analog control and trimming hw module register map -*

-*/ - -#ifndef RFANA_MAP_H_ -#define RFANA_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "architecture.h" - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -/** rfAna register map (control part) */ -typedef struct { - union { - struct { - __IO uint32_t FRACT_WORD:24; - __IO uint32_t INT_WORD:8; - } BITS; - __IO uint32_t WORD; - } TX_LO_CONTROL; - union { - struct { - __IO uint32_t FRACT_WORD:24; - __IO uint32_t INT_WORD:8; - } BITS; - __IO uint32_t WORD; - } RX_LO_CONTROL; - union { - struct { - __IO uint32_t PLL_RESET_TIME:10; - __I uint32_t RESERVED:6; - __IO uint32_t PLL_LOCK_TIME:10; - } BITS; - __IO uint32_t WORD; - } PLL_TIMING; - union { - struct { - __IO uint32_t LNA_GAIN_MODE:1; - __IO uint32_t ADC_DITHER_MODE:1; - } BITS; - __IO uint32_t WORD; - } RX_CONTROL; - __IO uint32_t TX_POWER; - __I uint32_t RECEIVER_GAIN; -} RfAnaReg_t, *RfAnaReg_pt; - -/** rfAna register map (trimming part) */ -typedef struct { - __IO uint32_t PMU_TRIM; - __IO uint32_t RESERVED; - __IO uint32_t RX_CHAIN_TRIM; - union { - struct { - __I uint32_t BIAS_VCO_TRIM:4; - __I uint32_t MODULATION_TRIM:4; - __IO uint32_t TX_VCO_TRIM:4; - __IO uint32_t RX_VCO_TRIM:4; - __I uint32_t DIV_TRIM:3; - __I uint32_t REG_TRIM:2; - __I uint32_t LFR_TRIM:3; - __I uint32_t PAD0:4; - __I uint32_t CHARGE_PUMP_RANGE:4; - } BITS; - __IO uint32_t WORD; - } PLL_TRIM; - __IO uint32_t PLL_VCO_TAP_LOCATION; - union { - struct { - __IO uint32_t TX_TUNE:4; - __IO uint32_t PA_REGULATOR_TRIM:4; - __IO uint32_t REGULATOR_TRIM:2; - __IO uint32_t RESERVED:2; - } BITS; - __IO uint32_t WORD; - } TX_TRIM; - - __IO uint32_t RX_VCO_TRIM_LUT2; /** 0x40019098 */ - __IO uint32_t RX_VCO_TRIM_LUT1; /** 0x4001909C */ - __IO uint32_t TX_VCO_TRIM_LUT2; /** 0x400190A0 */ - __IO uint32_t TX_VCO_TRIM_LUT1; /** 0x400190A4 */ - __IO uint32_t ADC_OFFSET_BUF; /** 0x400190A8 */ -} RfAnaTrimReg_t, *RfAnaTrimReg_pt; - -#endif /* RFANA_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c deleted file mode 100644 index 5401693035..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c +++ /dev/null @@ -1,307 +0,0 @@ -/** - ******************************************************************************* - * @file rtc.c - * @brief Implementation of a Rtc driver - * @internal - * @author ON Semiconductor - * $Rev: 3525 $ - * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a �ON Semiconductor�). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (�ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software�) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup rtc - * - * @details - * A real-time clock (RTC) is a computer clock ,that keeps track of the current time. The heart of the RTC is a series of - * freely running counters one for each time unit, The series of counters is linked as follows: a roll over event of - * the seconds counter produces a minutes enable pulse; a roll over event of the minutes counter produces an hours - * enable pulse, etc.Note that all Counter registers are in an undefined state on power-up. - * Use the Reset bit in the Control Register to reset the counters to their default values. - * DIVISOR is the register containing the value to divide the clock frequency to produce 1Hz strobe ; 1Hz strobe is used - * internally to time the incrementing of the Seconds Counter. - * There is a set of register to set the values in the counter for each time unit.from where time is start to increment. - * There is another set of register to set the ALARM ...Each of the Alarm Registers can be programmed with a value that - * is used to compare to a Counter Register in order to produce an alarm (an interrupt) when the values match. - * There is a programmable bit in each Alarm Register that determines if the alarm occurs upon a value match, or - * if the alarm occurs upon a Counter increment condition. - * - */ - -#if DEVICE_RTC - -#include "rtc.h" -#include "mbed_assert.h" -#include "lp_ticker_api.h" - -static volatile uint64_t last_time_read; - -/** - * Convert sub seconds ticks to micro seconds. - * The clock running at 32kHz, a tick is 1/32768 of a second. - */ -static inline uint32_t ticks_to_us(uint16_t ticks) { - return (((uint64_t)ticks * RTC_SEC_TO_US) / RTC_CLOCK_HZ); -} - -/** - * Convert us into sub seconds ticks. - * @note result might be troncated to be in the range [0 - RTC_SUB_SEC_MASK]. - */ -static inline uint16_t us_to_ticks(uint32_t us) { - return (((uint64_t) us * RTC_CLOCK_HZ) / RTC_SEC_TO_US) & RTC_SUB_SEC_MASK; -} - -#define RTC_TICK_THRESHOLD 5 - -/* See rtc.h for details */ -void fRtcInit(void) -{ - CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */ - CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */ - - /* Reset RTC control register */ - RTCREG->CONTROL.WORD = 0; - - /* Initialize all counters */ - RTCREG->SECOND_COUNTER = 0; - RTCREG->SUB_SECOND_COUNTER = 0; - RTCREG->SECOND_ALARM = 0; - RTCREG->SUB_SECOND_ALARM = 0; - last_time_read = 0; - - /* Reset RTC Status register */ - RTCREG->STATUS.WORD = 0; - - /* Clear interrupt status */ - RTCREG->INT_CLEAR.WORD = ( - (1 << RTC_INT_CLR_SUB_SEC_BIT_POS) | - (1 << RTC_INT_CLR_SEC_BIT_POS) - ); - - /* Wait previous write to complete */ - while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); - /* Start sec & sub_sec counter */ - RTCREG->CONTROL.WORD |= ( - (True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) | - (True << RTC_CONTROL_SEC_CNT_START_BIT_POS) - ); - - /* enable interruption associated with the rtc at NVIC level */ - NVIC_SetVector(Rtc_IRQn,(uint32_t) fRtcHandler); /* TODO define lp_ticker_isr */ - NVIC_ClearPendingIRQ(Rtc_IRQn); - NVIC_EnableIRQ(Rtc_IRQn); - - /* Wait for RTC to finish writing register */ - while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); -} - -/* See rtc.h for details */ -void fRtcFree(void) -{ - /* Disable interrupts and counter */ - RTCREG->CONTROL.WORD = 0; - - /* disable interruption associated with the rtc */ - NVIC_DisableIRQ(Rtc_IRQn); - - /* Wait for RTC to finish writing register */ - while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); -} - -/* See rtc.h for details */ -void fRtcSetInterrupt(uint32_t timestamp) -{ - uint64_t current_time = fRtcRead(); - - uint64_t full_timestamp = (current_time & ~UINT32_MAX) | timestamp; - if ( (uint32_t)current_time > timestamp) { - full_timestamp += ((uint64_t) UINT32_MAX) + 1; - } - - uint32_t target_seconds = full_timestamp / RTC_SEC_TO_US; - uint16_t target_ticks = us_to_ticks(full_timestamp); - - /* - * If the interrupt is in more than one second from now then use the - * second alarm, otherwise use the subsecond alarm. - * In case of the second alarm is used, there is no need to preserve the - * remaining subsecond because the irq handler should manage spurious - * interrupts (like when the timestamp is in the past). In such case, irq - * handler will schedule a new interrupt with the remaining us. - */ - NVIC_DisableIRQ(Rtc_IRQn); - if (target_seconds != RTCREG->SECOND_COUNTER) { - RTCREG->SECOND_ALARM = target_seconds; - - uint32_t rtc_control = RTCREG->CONTROL.WORD; - rtc_control |= (1 << RTC_CONTROL_SEC_CNT_INT_BIT_POS); // enable seconds interrupt - rtc_control &= ~(1 << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); // disable sub sec interrupt - RTCREG->CONTROL.WORD = rtc_control; - } else { - uint16_t current_ticks = RTCREG->SUB_SECOND_COUNTER; - if (current_ticks == target_ticks || - ((target_ticks > current_ticks) && ((target_ticks - current_ticks) < RTC_TICK_THRESHOLD)) || - ((target_ticks < current_ticks) && ((RTC_SUB_SEC_MASK - (current_ticks - target_ticks)) < RTC_TICK_THRESHOLD))) { - // target ticks too close; schedule the interrupt immediately - NVIC_SetPendingIRQ(Rtc_IRQn); - } else { - RTCREG->SUB_SECOND_ALARM = target_ticks; - - uint32_t rtc_control = RTCREG->CONTROL.WORD; - rtc_control &= ~(1 << RTC_CONTROL_SEC_CNT_INT_BIT_POS); // disable seconds interrupt - rtc_control |= (1 << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS); // enable sub sec interrupt - RTCREG->CONTROL.WORD = rtc_control; - } - } - NVIC_EnableIRQ(Rtc_IRQn); - - /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/ - while(RTCREG->STATUS.WORD & - ( - (True << RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS) | - (True << RTC_STATUS_SEC_ALARM_WRT_BIT_POS) | - (True << RTC_STATUS_CONTROL_WRT_BIT_POS) - ) - ); -} - -/* See rtc.h for details */ -void fRtcDisableInterrupt(void) -{ - NVIC_DisableIRQ(Rtc_IRQn); -} - -/* See rtc.h for details */ -void fRtcEnableInterrupt(void) -{ - NVIC_EnableIRQ(Rtc_IRQn); -} - -/* See rtc.h for details */ -void fRtcClearInterrupt(void) -{ - /* Disable subsec/sec interrupt */ - /* Clear sec & sub_sec interrupts */ - RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) | - (True << RTC_INT_CLR_SEC_BIT_POS)); - - while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) | - (True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS)))); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/ -} - -/* See rtc.h for details */ -uint64_t fRtcRead(void) -{ - /* Hardware Bug fix: The rollover of the sub-second counter initiates the increment of the second counter. - * That means there is one cycle where the sub-second has rolled back to zero and the second counter has not incremented - * and a read during that cycle will be incorrect. That will occur for one RTC cycle and that is about 31us of exposure. - * If you read a zero in the sub-second counter then increment the second counter by 1. - * Alternatively, subtract 1 from the Sub-seconds counter to align the Second and Sub-Second rollover. - */ - uint32_t seconds = RTCREG->SECOND_COUNTER; - uint16_t ticks = (RTCREG->SUB_SECOND_COUNTER - 1) & SUB_SEC_MASK; - - /* - * If seconds has changed while reading ticks, read them both again. - */ - while (seconds != RTCREG->SECOND_COUNTER) { - seconds = RTCREG->SECOND_COUNTER; - ticks = (RTCREG->SUB_SECOND_COUNTER - 1) & SUB_SEC_MASK; - } - - uint64_t current_time = ((uint64_t) seconds * RTC_SEC_TO_US) + ticks_to_us(ticks); - - /*check that the time did not go backwards */ - MBED_ASSERT(current_time >= last_time_read); - last_time_read = current_time; - - return current_time; -} - -/* See rtc.h for details */ -void fRtcWrite(uint64_t RtcTimeus) -{ - uint32_t Second = False; - uint16_t SubSecond = False; - /* Stop RTC */ - RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) | - (True << RTC_CONTROL_SEC_CNT_START_BIT_POS)); - - if(RtcTimeus > RTC_SEC_TO_US) { - /* TimeStamp is big enough to set second counter */ - Second = ((RtcTimeus / RTC_SEC_TO_US) & RTC_SEC_MASK); - } - RTCREG->SECOND_COUNTER = Second; - RtcTimeus = RtcTimeus - (Second * RTC_SEC_TO_US); - if(RtcTimeus > False) { - /* Convert TimeStamp to sub_seconds */ - SubSecond = (uint16_t)((float)(RtcTimeus * RTC_CLOCK_HZ / RTC_SEC_TO_US)) & RTC_SUB_SEC_MASK; - } - /* Set SUB_SEC_ALARM */ - RTCREG->SUB_SECOND_COUNTER = SubSecond; - - while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/ - /* Start RTC */ - RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) | - (True << RTC_CONTROL_SEC_CNT_START_BIT_POS)); - - while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/ -} - -/* See rtc.h for details */ -void fRtcHandler(void) -{ - /* Disable RTC interrupt */ - NVIC_DisableIRQ(Rtc_IRQn); - - /* Clear sec & sub_sec interrupts */ - RTCREG->INT_CLEAR.WORD = ( - (True << RTC_INT_CLR_SUB_SEC_BIT_POS) | - (True << RTC_INT_CLR_SEC_BIT_POS) - ); - - /* Disable sub seconds and seconds interrupts */ - RTCREG->CONTROL.WORD &= ~( - (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) | - (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS) - ); - - NVIC_EnableIRQ(Rtc_IRQn); - - /* Wait for RTC to finish writing registers */ - while(RTCREG->STATUS.WORD & - ( - (True << RTC_STATUS_CONTROL_WRT_BIT_POS) | - (True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) | - (True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS) - ) - ); - - lp_ticker_irq_handler(); -} - -boolean fIsRtcEnabled(void) -{ - if(RTCREG->CONTROL.BITS.SUB_SEC_COUNTER_EN | RTCREG->CONTROL.BITS.SEC_COUNTER_EN) { - return True; - } else { - return False; - } -} - -#endif diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h deleted file mode 100644 index d9a4dc4b2e..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - ****************************************************************************** - * @file rtc.h - * @brief (API) Public header of RTC driver - * @internal - * @author ON Semiconductor - * $Rev: 3485 $ - * $Date: 2015-07-14 15:20:11 +0530 (Tue, 14 Jul 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup rtc - */ - -#ifndef RTC_H_ -#define RTC_H_ - -#include "rtc_map.h" -#include "clock.h" -#include "memory_map.h" - -#define RTC_CLOCK_HZ 32768 -#define RTC_SEC_TO_US 1000000 -#define RTC_SUB_SEC_MASK 0x7FFF -#define RTC_SEC_MASK 0xFFFFFFFF -#define RTC_SEC_INT_STATUS_MASK 0x2 - -#define RTC_SUBSEC_INTERRUPT_BIT_VAL 0x1 -#define RTC_SEC_INTERRUPT_BIT_VAL 0x2 -#define RTC_ALL_INTERRUPT_BIT_VAL 0x3 - -#define RTC_INT_CLR_SUB_SEC_BIT_POS 0 -#define RTC_INT_CLR_SEC_BIT_POS 1 - -#define RTC_CONTROL_SUBSEC_CNT_START_BIT_POS 0 -#define RTC_CONTROL_SEC_CNT_START_BIT_POS 1 -#define RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS 2 -#define RTC_CONTROL_SEC_CNT_INT_BIT_POS 3 - -#define RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS 6 -#define RTC_STATUS_SEC_ALARM_WRT_BIT_POS 7 -#define RTC_STATUS_CONTROL_WRT_BIT_POS 8 -#define RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS 9 -#define RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS 10 - -#define SUB_SEC_MASK 0x7FFF - - -/* FUnction pointer for call back */ -typedef void (* fRtcCallBack)(void); - -/** - * @details - * Initializes RTC, enable RTC & register call back function - * - * @param RtcCallBack Function pointer for RTC call back funtion - * @return None - */ -void fRtcInit(void); - -/** - * @details - * Disable RTC - * - * @param None - * @return None - */ -void fRtcFree(void); - -/** - * @details - * Set up alram for RTC interrupt in micro second - * Pre-requisite: Both second & sub second interrupts should be cleared. - * @param TimeStamp in micro seconds - * @return None - */ -void fRtcSetInterrupt(uint32_t timestamp); - -/** - * @details - * Disable interrupt - * - * @param None - * @return None - */ -void fRtcDisableInterrupt(void); - -/** - * @details - * Enable interrupt - * - * @param None - * @return None - */ -void fRtcEnableInterrupt(void); - -/** - * @details - * Clear interrupt - * - * @param None - * @return None - */ -void fRtcClearInterrupt(void); - -/** - * @details - * Returns RTC time in micro seconds - * - * @param None - * @return RTC Time in micro second - */ -uint64_t fRtcRead(void); - -/** - * @details - * Set RTC time in micro seconds - * - * @param RtcTime in micro Seconds - * @return None - */ -void fRtcWrite(uint64_t RtcTimeus); - -/** - * @details - * RTC interrupt handler - * - * @param None - * @return None - */ -void fRtcHandler(void); - -/** - * @details - * Is RTC enabled? - * - * @param None - * @return RTC status - */ -boolean fIsRtcEnabled(void); -#endif /* RTC_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c deleted file mode 100644 index a7e66bbc99..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_api.c +++ /dev/null @@ -1,89 +0,0 @@ -/** -****************************************************************************** -* @file rtc_api.c -* @brief Implementation of a RTC driver -* @internal -* @author ON Semiconductor -* $Rev: 0.1 $ -* $Date: 2016-01-20 12:09:00 +0530 (Wed, 20 Jan 2016) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup rtc -* -*/ -#include "rtc_api.h" -#if DEVICE_RTC -#include "device.h" - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" -#include "mbed_assert.h" -#include -#include "rtc.h" -#include "cmsis_nvic.h" - -#define US_PER_SEC 1000000 - -static time_t m_time_base; - -static uint32_t rtc_seconds_get() -{ - return (uint32_t)((fRtcRead() / US_PER_SEC) & 0xFFFFFFFF); -} - -/* See rtc_apc.h for description */ - -void rtc_init(void) -{ - fRtcInit(); -} - -/* See rtc_apc.h for description */ -void rtc_free(void) -{ - fRtcFree(); -} - -/* See rtc_apc.h for description */ -int rtc_isenabled(void) -{ - return(fIsRtcEnabled()); -} - -/* See rtc_apc.h for description */ -time_t rtc_read(void) -{ - return m_time_base + rtc_seconds_get(); -} - -/* See rtc_apc.h for description */ -void rtc_write(time_t t) -{ - uint32_t seconds; - do { - seconds = rtc_seconds_get(); - m_time_base = t - seconds; - /* If the number of seconds indicated by the counter changed during the - update of the time base, just repeat the update, now using the new - number of seconds. */ - } while (seconds != rtc_seconds_get()); -} - -#endif /* DEVICE_RTC */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h deleted file mode 100644 index 18ab0a4d77..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - ****************************************************************************** - * @file rtc_map.h - * @brief Real Time Clock HW register map - * @internal - * @author ON Semiconductor. - * $Rev: 3008 $ - * $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup rtc - * - * @details - *

- * Teal Time Clock HW register map description - *

- * - *

Reference document(s)

- *

- * - * IPC7206 APB RTC Design Specification v1.0 - *

- */ - -#ifndef RTC_MAP_H_ -#define RTC_MAP_H_ - -#include "architecture.h" - -/** Real Time Clock Control HW Structure Overlay */ -typedef struct { - __IO uint32_t SUB_SECOND_COUNTER; /** -#include "uart_16c550.h" -#include "cmsis_nvic.h" - -static IRQn_Type Irq; - -uint32_t stdio_uart_inited = 0; -serial_t stdio_uart; - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; -static inline void uart_irq(uint8_t status, uint32_t index); - - -/** Opens UART device. - * @details - * Sets the necessary registers. Set to default Baud rate 115200, 8 bit, parity None and stop bit 1. - * The UART interrupt is enabled. - * - * @note The UART transmit interrupt is not enabled, because sending is controlled - * by the task. - * - * @param UartNum A UART device instance. - * @param options The options parameter containing the baud rate. - * @return True if opening was successful. - */ - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - uint16_t clockDivisor; - - CrossbReg_t *CbRegOffSet; - PadReg_t *PadRegOffset; - - //find which peripheral is associated with the rx and tx pins - uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); - uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); - //check if the peripherals for each pin are the same or not - //returns the enum associated with the peripheral - //in the case of this target, the enum is the base address of the peripheral - obj->UARTREG = (Uart16C550Reg_pt) pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT(obj->UARTREG != (Uart16C550Reg_pt) NC); - - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - /*TODO: Mac Lobdell - we should recommend using the instance method and not using base addresses as index */ - - if (obj->UARTREG == (Uart16C550Reg_pt)STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } - /*TODO: determine if pullups are needed/recommended */ - /* if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - */ - /* Configure IOs to UART using cross bar, pad and GPIO settings */ - - if(obj->UARTREG == UART2REG) { - /* UART 2 */ - CLOCK_ENABLE(CLOCK_UART2); - Irq = Uart2_IRQn; - } else if(obj->UARTREG == UART1REG) { - /* UART 1 */ - CLOCK_ENABLE(CLOCK_UART1); - - Irq = Uart1_IRQn; - } else { - MBED_ASSERT(False); - } - - CLOCK_ENABLE(CLOCK_GPIO); - CLOCK_ENABLE(CLOCK_CROSSB); - CLOCK_ENABLE(CLOCK_PAD); - - /*TODO: determine if tx and rx are used correctly in this case - this depends on the pin enum matching the position in the crossbar*/ - - /* Configure tx pin as UART */ - CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (tx * CROSS_REG_ADRS_BYTE_SIZE)); - CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* tx pin as UART */ - - /* Configure rx pin as UART */ - CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (rx * CROSS_REG_ADRS_BYTE_SIZE)); - CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* rx pin as UART */ - - /** - Set pad parameters, output drive strength, pull piece control, output drive type */ - PadRegOffset = (PadReg_t*)(PADREG_BASE + (tx * PAD_REG_ADRS_BYTE_SIZE)); - PadRegOffset->PADIO0.WORD = PAD_UART_TX; /* Pad setting for UART Tx */ - - PadRegOffset = (PadReg_t*)(PADREG_BASE + (rx * PAD_REG_ADRS_BYTE_SIZE)); - PadRegOffset->PADIO0.WORD = PAD_UART_RX; /* Pad settings for UART Rx */ - - GPIOREG->W_OUT = (0x1 << tx); /* tx as OUT direction */ - GPIOREG->W_IN = (0x1 << rx); /* rx as IN directon */ - - CLOCK_DISABLE(CLOCK_PAD); - CLOCK_DISABLE(CLOCK_CROSSB); - CLOCK_DISABLE(CLOCK_GPIO); - - /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers. - * The right-shift of 4 is a division of 16, representing the oversampling rate. */ - clockDivisor = (fClockGetPeriphClockfrequency() / UART_DEFAULT_BAUD) >> 4; - obj->UARTREG->LCR.WORD = 0x80; - obj->UARTREG->DLL = clockDivisor & 0xFF; - obj->UARTREG->DLM = clockDivisor >> 8; - - /* Set the character width to 8 data bits, no parity, 1 stop bit. Write the entire line control register, - * effectively disabling the divisor latch. */ - obj->UARTREG->LCR.WORD = 0x03; - - /* Enable the FIFOs, reset the Tx and Rx FIFOs, set the Rx FIFO trigger level to 8 bytes, and set DMA Mode - to 1. */ - obj->UARTREG->FCR.WORD = (FCR_RXFIFOTRIGGERLEVEL_8 | FCR_DMA_MODE_1 | - FCR_TXFIFO_RESET | FCR_RXFIFO_RESET | FCR_FIFO_ENABLE); - - /* Make a copy of the current MSR to the SCR register. This is used from task space to determine the - * flow control state. */ - obj->UARTREG->SCR = obj->UARTREG->MSR.WORD; - - if((int)obj->UARTREG == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } - - NVIC_ClearPendingIRQ(Irq); - - return; -} - -/** Closes a UART device. - * @details - * Disables the UART interrupt. - * - * @param device The UART device to close. - */ -void serial_free(serial_t *obj) -{ - NVIC_DisableIRQ(obj->IRQType); -} - -void serial_baud(serial_t *obj, int baudrate) -{ - /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers. - * The right-shift of 4 is a division of 16, representing the oversampling rate. */ - uint16_t clockDivisor = (fClockGetPeriphClockfrequency() / baudrate) >> 4; - - obj->UARTREG->LCR.BITS.DLAB = True; - obj->UARTREG->DLL = clockDivisor & 0xFF; - obj->UARTREG->DLM = clockDivisor >> 8; - obj->UARTREG->LCR.BITS.DLAB = False; -} - -/* -Parity XX0 – Parity disabled; 001 – Odd Parity; 011 – Even Parity; 101 – Stick Parity, checked as 1; 111 – Stick Parity, checked as 0. -StopBit 0 – 1 stop bit; 1 – 2 stop bits. -DataLen 00 – 5 bits; 01 – 6 bits; 10 – 7 bits; 11 – 8 bits -*/ -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - if(data_bits >= 5 && data_bits <= 8 && parity <= 7 && stop_bits >= 1 && stop_bits <= 2) { - if(parity == (SerialParity)0) { - parity = (SerialParity)0; - } else { - parity = (SerialParity)(parity + parity - 1) ; - } - - obj->UARTREG->LCR.WORD |= ((((data_bits - 5) << UART_LCR_DATALEN_BIT_POS) | - (parity << UART_LCR_PARITY_BIT_POS) | - ((stop_bits - 1) << UART_LCR_STPBIT_BIT_POS)) & 0x3F); - } else { - MBED_ASSERT(False); - } -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -/****************************************************** -************* Internal IRQ functions ****************** -*******************************************************/ -void Uart1_Irq() -{ - uint8_t active_irq = (uint8_t)(UART1REG->LSR.WORD) & 0xFF; - uint8_t irq_mask = 0; - - if(UART1REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/ - irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK; - } - - if(UART1REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/ - irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK; - } - - //uart_irq((uint8_t)(UART1REG->LSR.WORD & 0xFF), 0); - uart_irq(active_irq & irq_mask, 0); -} - -void Uart2_Irq() -{ - uint8_t active_irq = (uint8_t)(UART2REG->LSR.WORD) & 0xFF; - uint8_t irq_mask = 0; - - if(UART2REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/ - irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK; - } - - if(UART2REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/ - irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK; - } - - //uart_irq((uint8_t)(UART2REG->LSR.WORD & 0xFF), 1); - uart_irq(active_irq & irq_mask, 1); - -} - -static inline void uart_irq(uint8_t status, uint32_t index) -{ - if (serial_irq_ids[index] != 0) { - if (status & UART_LSR_TX_EMPTY_MASK) { - irq_handler(serial_irq_ids[index], TxIrq); - } - if (status & UART_LSR_RX_DATA_READY_MASK) { - irq_handler(serial_irq_ids[index], RxIrq); - } - } -} -/******************************************************/ - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t Vector = 0; - - /* Check UART number & assign irq handler */ - if(obj->UARTREG == UART1REG) { - /* UART 2 */ - Vector = (uint32_t)&Uart1_Irq; - irq_n = Uart1_IRQn; - } else if(obj->UARTREG == UART2REG) { - /* UART 1 */ - Vector = (uint32_t)&Uart2_Irq; - irq_n = Uart2_IRQn; - } else { - MBED_ASSERT(False); - } - - /* Check IRQ type & enable/disable accordingly */ - if(enable) { - /* Enable */ - if(irq == RxIrq) { - /* Rx IRQ */ - obj->UARTREG->FCR.BITS.RX_FIFO_TRIG = 0x0; - obj->UARTREG->IER.BITS.RX_DATA_INT = True; - } else if(irq == TxIrq) { - /* Tx IRQ */ - obj->UARTREG->IER.BITS.TX_HOLD_INT = True; - } else { - MBED_ASSERT(False); - } - NVIC_SetVector(irq_n, Vector); - NVIC_EnableIRQ(irq_n); - } else { - /* Disable */ - NVIC_DisableIRQ(irq_n); - if(irq == RxIrq) { - /* Rx IRQ */ - obj->UARTREG->IER.BITS.RX_DATA_INT = False; - } else if(irq == TxIrq) { - /* Tx IRQ */ - - obj->UARTREG->IER.BITS.TX_HOLD_INT = False; - } else { - MBED_ASSERT(False); - } - } -} - -int serial_getc(serial_t *obj) -{ - uint8_t c; - - while(!obj->UARTREG->LSR.BITS.READY); /* Wait for received data is ready */ - c = obj->UARTREG->RBR & 0xFF; /* Get received character */ - return c; -} - -void serial_putc(serial_t *obj, int c) -{ - - while(!obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY);/* Wait till THR is empty */ - obj->UARTREG->THR = c; /* Transmit byte */ - -} - -int serial_readable(serial_t *obj) -{ - return obj->UARTREG->LSR.BITS.READY; -} - -int serial_writable(serial_t *obj) -{ - return obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY; -} - -void serial_clear(serial_t *obj) -{ - /* Reset TX & RX FIFO */ - obj->UARTREG->FCR.WORD |= ((True << UART_FCS_TX_FIFO_RST_BIT_POS) | - (True << UART_FCS_RX_FIFO_RST_BIT_POS)); -} - -void serial_break_set(serial_t *obj) -{ - obj->UARTREG->LCR.BITS.BREAK = True; -} - -void serial_break_clear(serial_t *obj) -{ - obj->UARTREG->LCR.BITS.BREAK = False; -} - -void serial_pinout_tx(PinName tx) -{ - /* COnfigure PinNo to drive strength of 1, Push pull and pull none */ - fPadIOCtrl(tx, 1, 0, 1); -} - -/** Configure the serial for the flow control. It sets flow control in the hardware - * if a serial peripheral supports it, otherwise software emulation is used. - * - * @param obj The serial object - * @param type The type of the flow control. Look at the available FlowControl types. - * @param rxflow The TX pin name - * @param txflow The RX pin name - */ -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - /* TODO: This is an empty implementation for now.*/ -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} - -#endif /* DEVICE_SERIAL */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c deleted file mode 100644 index 41be2fea41..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c +++ /dev/null @@ -1,120 +0,0 @@ -/** - ******************************************************************************* - * @file sleep.c - * @brief Implementation of an sleep functionality - * @internal - * @author ON Semiconductor - * $Rev: 0.1 $ - * $Date: 01-21-2016 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup sleep - * - * @details - * Sleep implementation - * - */ -#if DEVICE_SLEEP -#include "mbed_power_mgmt.h" -#include "sleep_api.h" -#include "cmsis_nvic.h" - -#define ENABLE (uint8_t)0x01 -#define DISABLE (uint8_t)0x00 -#define MAC_LUT_SIZE (uint8_t)96 - -#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) ) -#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) -#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) -#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) - -void fncs36510_sleep(void) -{ - /** Unset SLEEPDEEP (SCR) and COMA to select sleep mode */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - PMUREG->CONTROL.BITS.ENCOMA = DISABLE; - - /* Enter into sleep mode */ - __ISB(); - __WFI(); -} - -void fncs36510_deepsleep(void) -{ - /** Set SLEEPDEEP (SCR) and unset COMA to select deep sleep mode */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - PMUREG->CONTROL.BITS.ENCOMA = DISABLE; - - /** Enter into deep sleep mode */ - __ISB(); - __WFI(); - __NOP(); - __NOP(); - - /** Wait for the external 32MHz to be power-ed up & running - * Re-power down the 32MHz internal osc - */ - while (!CLOCKREG->CSR.BITS.XTAL32M); - PMUREG->CONTROL.BITS.INT32M = 1; -} - -void fncs36510_coma(void) -{ - /** Set SLEEPDEEP (SCR) and set COMA to select coma mode */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - PMUREG->CONTROL.BITS.ENCOMA = ENABLE; - - /* TODO Wait till MAC is idle */ - // while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA)); - - /* TODO Back up MAC_LUT * - uint8_t MAC_LUT_BackUp[MAC_LUT_SIZE]; - fMacBackupFrameStoreLUT(MAC_LUT_BackUp); */ - - /* Disable UART 1 & 2 FIFO during coma*/ - UART1REG->FCR.WORD &= ~(FCR_FIFO_ENABLE); - UART2REG->FCR.WORD &= ~(FCR_FIFO_ENABLE); - - /** Enter into coma mode */ - __ISB(); - __WFI(); - - /** Wait for the external 32MHz to be power-ed up & running - * Re-power down the 32MHz internal osc - */ - while (!CLOCKREG->CSR.BITS.XTAL32M); - PMUREG->CONTROL.BITS.INT32M = 1; - - /** Trim the oscillators */ - if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) { - CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT; - } - if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) { - CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT; - } - - /* Enable UART 1 & 2 FIFO */ - UART1REG->FCR.WORD |= FCR_FIFO_ENABLE; - UART2REG->FCR.WORD |= FCR_FIFO_ENABLE; - - /* TODO Restore MAC_LUT * - fMacRestoreFrameStoreLUT(MAC_LUT_BackUp); */ -} - -#endif /* DEVICE_SLEEP */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c deleted file mode 100644 index 1ed5e18292..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep_api.c +++ /dev/null @@ -1,51 +0,0 @@ -/** - ******************************************************************************* - * @file sleep_api.c - * @brief Implementation of a sleep functionality - * @internal - * @author ON Semiconductor - * $Rev: $ - * $Date: $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup sleep - * - * @details - * Sleep implementation TBD - Dummy function is fine for first release - * - */ - -#if DEVICE_SLEEP - -#include "fncs36510_sleep.h" -#include "sleep_api.h" -#include "cmsis_nvic.h" - -void hal_sleep() -{ - fncs36510_sleep(); -} - -void hal_deepsleep() -{ - fncs36510_deepsleep(); -} - -#endif /* DEVICE_SLEEP */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h deleted file mode 100644 index 91c3b33366..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - ****************************************************************************** - * @file spi.h - * @brief Inlcude file of a SPI master driver - * @internal - * @author ON Semiconductor - * @version $Rev: $ - * @date $Date: 2016-02-05 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup spi_h - * - * @details - * - */ -#ifndef SPI_H_ -#define SPI_H_ - -#include "device.h" -#include "spi_api.h" - -#if DEVICE_SPI - -#ifdef __cplusplus -extern "C" { -#endif - -/* Miscellaneous I/O and control operations codes */ -#define SPI_IPC7207_IOCTL_GET_SLAVE_SELECT (0x1) /**< Ioctl request code: Reading slaveSelect register */ -#define SPI_IPC7207_IOCTL_SET_SLAVE_SELECT (0x2) /**< Ioctl request code: Setting slaveSelect register */ -#define SPI_IPC7207_IOCTL_FLUSH (0x3) /**< Ioctl request code: Flushin FIFOs and serial shift registers */ - -/* Control register bit positions */ -#define SPI_WORD_WIDTH_BIT_POS 6 -#define SPI_SLAVE_MASTER_BIT_POS 5 -#define SPI_CPOL_BIT_POS 4 -#define SPI_CPHA_BIT_POS 3 -#define SPI_ENDIAN_BIT_POS 2 -#define SPI_SAMPLE_EDGE_BIT_POS 1 -#define SPI_PORT_ENABLE_BIT_POS 0 - -/* COntrol register bits */ -#define SPI_ENDIAN_MSB_FIRST 1 -#define SPI_CPOL_IDLE_LOW 0 -#define SPI_CPHA_BEFORE_1ST_EDGE 0 -#define SPI_MASTER_MODE 1 -#define SPI_WORD_WIDTH_8_BITS 0 -#define SPI_SAMPLE_OPP_CLK_EDGE_DATA 0 -#define SPI_SLAVE_SELECT_NORM_BEHAVE 0 -#define SPI_PORT_ENABLE 1 - -#define SPI_SLAVE_SELECT_DEFAULT 0x10 - -#define SPI_DEFAULT_CONFIG 0x25 - -#define SPI_DEFAULT_SPEED 1000000 -#define SPI_BYTE_MASK 0xFF - -extern void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel); -extern void fSpiClose(spi_t *obj); -extern int fSpiWriteB(spi_t *obj, uint32_t const buf); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* DEVICE_SPI */ - -#endif /* SPI_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c deleted file mode 100644 index f36062577a..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c +++ /dev/null @@ -1,270 +0,0 @@ -/** - ******************************************************************************* - * @file spi_api.c - * @brief Implementation of a sleep functionality - * @internal - * @author ON Semiconductor - * $Rev: 0.1 $ - * $Date: 02-05-2016 $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup spi_api - * - * @details - * SPI implementation - * - */ -#if DEVICE_SPI -#include "spi.h" -#include "PeripheralPins.h" -#include "objects.h" -#include "spi_api.h" -#include "mbed_assert.h" -#include "memory_map.h" -#include "spi_ipc7207_map.h" -#include "crossbar.h" -#include "clock.h" -#include "cmsis_nvic.h" - - -#define SPI_FREQ_MAX 4000000 - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - fSpiInit(obj, mosi, miso, sclk, ssel); -} -void spi_free(spi_t *obj) -{ - fSpiClose(obj); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - /* Clear word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */ - obj->membase->CONTROL.WORD &= ~(uint32_t)((True << SPI_WORD_WIDTH_BIT_POS) | - (True << SPI_SLAVE_MASTER_BIT_POS) | - (True << SPI_CPOL_BIT_POS) | - (True << SPI_CPHA_BIT_POS)); - - /* Configure word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */ - obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) << SPI_WORD_WIDTH_BIT_POS) | - (!slave << SPI_SLAVE_MASTER_BIT_POS) | - ((mode >> 0x1) << SPI_CPOL_BIT_POS) | - ((mode & 0x1) << SPI_CPHA_BIT_POS)); -} - -void spi_frequency(spi_t *obj, int hz) -{ - /* If the frequency is outside the allowable range, set it to the max */ - if(hz > SPI_FREQ_MAX) { - hz = SPI_FREQ_MAX; - } - obj->membase->FDIV = ((fClockGetPeriphClockfrequency() / hz) >> 1) - 1; -} - -int spi_master_write(spi_t *obj, int value) -{ - return(fSpiWriteB(obj, value)); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_busy(spi_t *obj) -{ - return(obj->membase->STATUS.BITS.XFER_IP); -} - -uint8_t spi_get_module(spi_t *obj) -{ - if(obj->membase == SPI1REG) { - return 0; /* UART #1 */ - } else if(obj->membase == SPI2REG) { - return 1; /* UART #2 */ - } else { - return 2; /* Invalid address */ - } -} - -int spi_slave_receive(spi_t *obj) -{ - if(obj->membase->STATUS.BITS.RX_EMPTY != True){ /* if receive status is not empty */ - return True; /* Byte available to read */ - } - return False; /* Byte not available to read */ -} - -int spi_slave_read(spi_t *obj) -{ - int byte; - - while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */ - byte = obj->membase->RX_DATA; - return byte; -} - -void spi_slave_write(spi_t *obj, int value) -{ - while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */ - obj->membase->TX_DATA = value; -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_MOSI; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_MISO; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_SCLK; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_SSEL; -} - -#if DEVICE_SPI_ASYNCH /* TODO Not yet implemented */ - -void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t handler, uint32_t event, DMAUsage hint) -{ - - uint32_t i; - int ndata = 0; - uint16_t *tx_ptr = (uint16_t *) tx; - - if(obj->spi->CONTROL.BITS.WORD_WIDTH == 0) { - /* Word size 8 bits */ - WORD_WIDTH_MASK = 0xFF; - } else if(obj->spi->CONTROL.BITS.WORD_WIDTH == 1) { - /* Word size 16 bits */ - WORD_WIDTH_MASK = 0xFFFF; - } else { - /* Word size 32 bits */ - WORD_WIDTH_MASK = 0xFFFFFFFF; - } - - //frame size - if(tx_length == 0) { - tx_length = rx_length; - tx = (void*) 0; - } - //set tx rx buffer - obj->tx_buff.buffer = (void *)tx; - obj->rx_buff.buffer = rx; - obj->tx_buff.length = tx_length; - obj->rx_buff.length = rx_length; - obj->tx_buff.pos = 0; - obj->rx_buff.pos = 0; - obj->tx_buff.width = bit_width; - obj->rx_buff.width = bit_width; - - - if((obj->spi.bits == 9) && (tx != 0)) { - // Make sure we don't have inadvertent non-zero bits outside 9-bit frames which could trigger unwanted operation - for(i = 0; i < (tx_length / 2); i++) { - tx_ptr[i] &= 0x1FF; - } - } - - - // enable events - - obj->spi.event |= event; - - - // set sleep_level - enable irq - - //write async - - if ( && ) { - - } - while ((obj->tx_buff.pos < obj->tx_buff.length) && - (obj->spi->STATUS.BITS.TX_FULL == False) && - (obj->spi->STATUS.BITS.RX_FULL == False)) { - // spi_buffer_tx_write(obj); - - if (obj->tx_buff.buffer == (void *)0) { - data = SPI_FILL_WORD; - } else { - uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer); - data = tx[obj->tx_buff.pos] & 0xFF; - } - obj->spi->TX_DATA = data; - } - - ndata++; -} -return ndata; - -} - -uint32_t spi_irq_handler_asynch(spi_t *obj) -{ -} - -uint8_t spi_active(spi_t *obj) -{ -} - -void spi_abort_asynch(spi_t *obj) -{ -} - -#endif /* DEVICE_SPI_ASYNCH */ -#endif /* DEVICE_SPI */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h deleted file mode 100644 index 507c104235..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - ****************************************************************************** - * @file spi_ipc7207_map.h - * @brief SPI IPC 7207 HW register map - * @internal - * @author ON Semiconductor - * $Rev: 2110 $ - * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup spi_ipc7207 - * - * @details - *

- * SPI HW register map description - *

- * - *

Reference document(s)

- *

- * - * IPC7207 APB SPI Design Specification v1.2 - *

- */ - -#ifndef SPI_IPC7207_MAP_H_ -#define SPI_IPC7207_MAP_H_ - -#include "architecture.h" - -/** SPI HW Structure Overlay */ -typedef struct { - __O uint32_t TX_DATA; - __I uint32_t RX_DATA; - __IO uint32_t FDIV; - union { - struct { - __IO uint32_t ENABLE :1; /**< SPI port enable: 0 = disable , 1 = enable */ - __IO uint32_t SAMPLING_EDGE :1; /**< SDI sampling edge: 0 = opposite to SDO edge / 1 = same as SDO edge */ - __IO uint32_t ENDIAN :1; /**< Bits endianness: 0 = LSB first (little-endian) / 1 = MSB first (big-endian) */ - __IO uint32_t CPHA :1; /**< Clock phase: 0 = SDO set before first SCLK edge / 1 = SDO set after first SCLK edge */ - __IO uint32_t CPOL :1; /**< Clock polarity: 0 = active high / 1 = active low */ - __IO uint32_t MODE :1; /**< Device mode: 0 = slave mode / 1 = master mode */ - __IO uint32_t WORD_WIDTH :2; /**< Word width: 0 = 8b / 1 = 16b / 2 = 32b / 3 = reserved */ - } BITS; - __IO uint32_t WORD; - } CONTROL; - union { - struct { - __I uint32_t XFER_IP :1; /**< Transfer in progress: 0 = No transfer in progress / 1 = transfer in progress */ - __I uint32_t XFER_ERROR :1;/**< Transfer error: 0 = no error / 1 = SPI Overflow or Underflow */ - __I uint32_t TX_EMPTY :1; /**< Transmit FIFO/buffer empty flag: 0 = not empty / 1 = empty */ - __I uint32_t TX_HALF :1; /**< Transmit FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */ - __I uint32_t TX_FULL :1; /**< Transmit FIFO/buffer full flag: 0 = not full / 1 = full */ - __I uint32_t RX_EMPTY :1; /**< Receive FIFO/buffer empty flag: 0 = not empty / 1 = empty */ - __I uint32_t RX_HALF :1; /**< Receive FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */ - __I uint32_t RX_FULL :1; /**< Receive FIFO/buffer full flag: 0 = not full / 1 = full */ - } BITS; - __I uint32_t WORD; - } STATUS; - union { - struct { - __IO uint32_t SS_ENABLE :4; /**< Slave Select (x4): 0 = disable / 1 = enable */ - __IO uint32_t SS_BURST :1; /**< Slave Select burst mode (maintain SS active if TXFIFO not empty) */ - } BITS; - __IO uint32_t WORD; - } SLAVE_SELECT; - __IO uint32_t SLAVE_SELECT_POLARITY; /**< Slave Select polarity for up to 4 slaves:0 = active low / 1 = active high */ - __IO uint32_t IRQ_ENABLE; /**< IRQ (x8) enable: 0 = disable / 1 = enable */ - __I uint32_t IRQ_STATUS; /**< IRQ (x8) status: 0 = no IRQ occurred / 1 = IRQ occurred */ - __O uint32_t IRQ_CLEAR; /**< IRQ (x8) clearing: write 1 to clear IRQ */ - __IO uint32_t TX_WATERMARK; /**< Transmit FIFO Watermark: Defines level of RX Half Full Flag */ - __IO uint32_t RX_WATERMARK; /**< Receive FIFO Watermark: Defines level of TX Half Full Flag */ - __I uint32_t TX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of TX FIFO. */ - __I uint32_t RX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of RX FIFO. */ -} SpiIpc7207Reg_t, *SpiIpc7207Reg_pt; - -#endif /* SPI_IPC7207_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c deleted file mode 100644 index f392085d4d..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/swversion.c +++ /dev/null @@ -1,55 +0,0 @@ -/** -****************************************************************************** -* @file swversion.c -* @brief Defines the system revision for the current application. -* @internal -* @author ON Semiconductor -* $Rev: 2199 $ -* $Date: 2013-08-07 12:17:27 +0200 (Wed, 07 Aug 2013) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a "ON Semiconductor"). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * ("ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software") and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup common_mib -*/ - -/* Other inclusions */ -#include -#include "fib.h" - -/************************************************************************************************* -* * -* Global variables * -* * -*************************************************************************************************/ - -#ifdef __ICCARM__ -/** Define a fib table constant region, to be located at fixed offset in the binary - * such that flash loader knows where to find it and gets the build dependent data - * it needs for programming the new fib. - */ -__root const fibtable_t fib_table @ "FIBTABLE" = {LOAD_ADDRESS,{0x0,0x00,0x00,0x00}}; -#endif /* __ICCARM__ */ - -const mib_systemRevision_t systemRevision = { - 0x82, /**< hardware revision */ - 0x00, /**< patch level */ - 0x01, /**< Build number */ - 0x00, /**< feature set, Minor version */ - 0x01, /**< generation, Major version */ - 'E' /**< release */ -}; diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h deleted file mode 100644 index 979b80ce26..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/sys.h +++ /dev/null @@ -1,64 +0,0 @@ -/** -****************************************************************************** -* @file sys.h -* @brief Defines the System module -* @internal -* @author ON Semiconductor -* $Rev: 2074 $ -* $Date: 2013-07-10 14:36:15 +0200 (Wed, 10 Jul 2013) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup sys -* -* @details -* -*/ - -#ifndef SYS_H_ -#define SYS_H_ - -/************************************************************************************************* -* * -* Symbolic Constants * -* * -*************************************************************************************************/ - -#define SYS_MODULE_ID 0x04 - -#define SYS_RESET_CODE 0x00 -#define SYS_SLEEP_CODE 0x10 -#define SYS_DEEPSLEEP_CODE 0x11 -#define SYS_COMA_CODE 0x12 - -#define SYS_RESET_WATCHDOG 0x00 -#define SYS_RESET_CORTEX 0x01 - -#define PWM_ACCESS_CODE 0x30 -#define PWM_IOCTLS_CODE 0x31 - -/************************************************************************************************* -* * -* Functions * -* * -*************************************************************************************************/ - -/** Initializes the system module. */ -void fSysUiInit(void); - -#endif /* SYS_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/target_config.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/target_config.h deleted file mode 100644 index 11904d9c54..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/target_config.h +++ /dev/null @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_TARGET_CONFIG_H -#define MBED_TARGET_CONFIG_H - -// Number of modules for a peripheral - -//#define MODULES_SIZE_ANALOGIN 1 -//#define MODULES_SIZE_ANALOGOUT 1 -#define MODULES_SIZE_GPIO 1 -//#define MODULES_SIZE_SPI 3 -//#define MODULES_SIZE_I2C 3 -//#define MODULES_SIZE_PWMOUT 4 -#define MODULES_SIZE_SERIAL 2 - -// Transaction queue size for each peripheral - -//#define TRANSACTION_QUEUE_SIZE_SPI 16 - -#endif diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/test_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/test_map.h deleted file mode 100644 index 122a2434ed..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/test_map.h +++ /dev/null @@ -1,125 +0,0 @@ -/** -****************************************************************************** -* @file test_map.h -* @brief Test hw module register map -* @internal -* @author ON Semiconductor -* $Rev: 2848 $ -* $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup test -* -* @details -*/ - -#ifndef TEST_MAP_H_ -#define TEST_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "architecture.h" - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -/** General test registers - * - */ -typedef struct { - __IO uint32_t UNLOCK; - __IO uint32_t ANA_TEST_MUX; - __IO uint32_t OVD_ENA_MODE; - __IO uint32_t OVD_VAL; - __IO uint32_t ANA_TEST_MODE; - __IO uint32_t CLK_TEST_MODE; - union { - struct { - __IO uint32_t PAD0:1; - __IO uint32_t PAD1:1; - __IO uint32_t FORCE_SOURCE:1; - __IO uint32_t FORCE_SINK:1; - __IO uint32_t PD_CONTROL:3; - __IO uint32_t PAD3:1; - __IO uint32_t BYPASS_PLL_REG:1; - __IO uint32_t PAD4:4; - __IO uint32_t DITHER_MODE:1; - __IO uint32_t PLL_MODE:1; - __IO uint32_t FORCE_LOCK:1; - } BITS; - __IO uint32_t WORD; - } PLL_TEST_MODE; - __IO uint32_t RX_TEST_MODE; - __IO uint32_t PMU_TEST_MODE; -} TestReg_t, *TestReg_pt; - -/** Digital test registers - * - */ -typedef struct { - union { - struct { - __IO uint32_t PAD0 :4; /**< */ - __IO uint32_t DIO4 :4; /**< DIO4 Test Mux Control */ - __IO uint32_t DIO5 :4; /**< DIO5 Test Mux Control */ - __IO uint32_t DIO6 :4; /**< DIO6 Test Mux Control */ - __IO uint32_t DIO7 :4; /**< DIO7 Test Mux Control */ - __IO uint32_t DIO8 :4; /**< DIO8 Test Mux Control */ - __IO uint32_t DIO9 :4; /**< DIO9 Test Mux Control */ - __IO uint32_t DIO10 :4; /**< DIO10 Test Mux Control */ - } BITS; - __IO uint32_t WORD; - } DIG_TEST_MUX; - __IO uint32_t DIG_TEST_MODE; - union { - struct { - __IO uint32_t PAD0 :12; /**< */ - __IO uint32_t DIO5 :3; /**< DIO5 Input Test Mux Control */ - __IO uint32_t DIO6 :3; /**< DIO6 Input Test Mux Control */ - __IO uint32_t DIO7 :3; /**< DIO7 Input Test Mux Control */ - __IO uint32_t DIO8 :3; /**< DIO8 Input Test Mux Control */ - __IO uint32_t DIO9 :3; /**< DIO9 Input Test Mux Control */ - __IO uint32_t DIO10 :3; /**< DIO10 Input Test Mux Control */ - } BITS; - __IO uint32_t WORD; - } DIG_IN_TEST_MUX; - __IO uint32_t SCAN_MODE; - __IO uint32_t BIST_TEST_MUX; - __IO uint32_t RAM_DIAG_ADDR; - __IO uint32_t RAM_DIAG_DATA; - __IO uint32_t SRAMA_DIAG_COMP; - __IO uint32_t SRAMB_DIAG_COMP; - __IO uint32_t RAM_BUF_TEST_MODE; -} TestDigReg_t, *TestDigReg_pt; - -/** NVM test registers - * - */ -typedef struct { - __O uint32_t PAD; -} TestNvmReg_t, *TestNvmReg_pt; - -#endif /* TEST_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ticker.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/ticker.h deleted file mode 100644 index f7be3c94fc..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ticker.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - ****************************************************************************** - * @file ticker.h - * @brief Microcontroller uSec ticker - * @internal - * @author ON Semiconductor. - * $Rev: - * $Date: - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * - */ - -#ifndef TICKER_H_ -#define TICKER_H_ - -#include "types.h" - -/** Core frequency definitions. / - * - * These definitions should be adjusted to setup Orion core frequencies. - */ -#define CPU_CLOCK_ROOT_HZ ( ( unsigned long ) 32000000) /**< Orion 32MHz root frequency */ -#define CPU_CLOCK_DIV_32M ( 1 ) /**< Divider to set up core frequency at 32MHz */ -#define CPU_CLOCK_DIV_16M ( 2 ) /**< Divider to set up core frequency at 16MHz */ -#define CPU_CLOCK_DIV_8M ( 4 ) /**< Divider to set up core frequency at 8MHz */ -#define CPU_CLOCK_DIV_4M ( 8 ) /**< Divider to set up core frequency at 4MHz */ - -#define CPU_CLOCK_DIV CPU_CLOCK_DIV_32M /**< Selected divider to be used by application code */ - -#define configCPU_CLOCK_HZ ( ( unsigned long ) (CPU_CLOCK_ROOT_HZ/CPU_CLOCK_DIV) ) -#define configTICK_RATE_HZ ( ( unsigned long ) 1000000 ) // 1uSec ticker rate - - -/* Lowest priority */ - -#define configKERNEL_INTERRUPT_PRIORITY ( 0xFF ) -#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 0x8F ) - -#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ - -/* Constants required to manipulate the core. Registers first... */ -#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) ) -#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) ) -#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) ) -#define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) ) -#define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) ) - -/* ...then bits in the registers. */ -#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) -#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) -#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) -#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) - -/* Orion has 4 interrupt priority bits - */ -#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) - -/* API definitions */ -void fSysTickInit(void); - -void fSysTickHandler(void); - -uint32_t fSysTickRead(void); - -void fSysTickEnableInterrupt (void); - -void fSysTickDisableInterrupt (void); -#endif // TICKER_H_ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h deleted file mode 100644 index 86fc51af46..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_map.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - ****************************************************************************** - * @file timer_map.h - * @brief Timer HW register map - * @internal - * @author ON Semiconductor - * $Rev: 3423 $ - * $Date: 2015-06-09 11:16:49 +0530 (Tue, 09 Jun 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup timer - * - * @details - *

- * Timer HW register map description - *

- * - *

Reference document(s)

- *

- * - * IPC7200 APB Timer Design Specification v1.2 - *

- */ - -#ifndef TIMER_MAP_H_ -#define TIMER_MAP_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "architecture.h" - -/** Timer HW Structure Overlay */ -typedef struct { - __IO uint32_t LOAD; /**< 16bit counter (re-)load value */ - __I uint32_t VALUE; /**< 16bit current counter value */ - union { - struct { - __IO uint32_t PAD0 :2; /**< Always reads 0 */ - __IO uint32_t PRESCALE :3; /**< 0:no division, 1..7: divide by 16, 256, 2, 8, 32, 128, 1024*/ - __IO uint32_t PAD1 :1; /**< Always reads 0 */ - __IO uint32_t MODE :1; /**< 0:free-run, 1:periodic */ - __IO uint32_t ENABLE :1; /**< 0: disable, 1:enable */ - __I uint32_t INT :1; /**< interrupt status */ - } BITS; - __IO uint32_t WORD; - } CONTROL; - __O uint32_t CLEAR; /**< Write any value to clear the interrupt */ -} TimerReg_t, *TimerReg_pt; - -#ifdef __cplusplus -} -#endif - -#endif /* TIMER_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_ncs36510.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_ncs36510.h deleted file mode 100644 index 58affbc145..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/timer_ncs36510.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - ****************************************************************************** - * @file timer.h - * @brief (API) Public header of Timer driver - * @internal - * @author ON Semiconductor - * $Rev: 3725 $ - * $Date: 2015-09-14 14:36:27 +0530 (Mon, 14 Sep 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup timer - * - * @details - * - *

General description

- *

- * The APB Timer module is a 16-bit down counter with a selectable prescaler. - * Prescaler values can be selected from 1 to 1024. - * (prescaler extends the range of the timer at the expense of precision) - * The Timer provides two modes of operation being free running and periodic. - * In free running mode, when the counter reaches zero it is decremented to 0xFFFF - * and no interrupt is generated. - * In periodic, when the counter reaches zero it is decremented to load value - * and an interruption is generated. - *

- * - */ - -#ifndef TIMER_H_ -#define TIMER_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -//#include "driver.h" -#include "us_ticker_api.h" -#include "clock.h" -#include "timer_map.h" -#include "types.h" -#include "cmsis_nvic.h" - -/* Miscellaneous I/O and control operations codes */ -#define TIMER_IOCTL_GET_LOAD 1 /**< Ioctl request code: Getting load value. */ -#define TIMER_IOCTL_SET_LOAD 2 /**< Ioctl request code: Seting load value. */ -#define TIMER_IOCTL_GET_VALUE 3 /**< Ioctl request code: Getting current timer value. */ - -/* Timer control bits */ -#define TIMER_ENABLE_BIT 0x1 -#define TIMER_PRESCALE_BIT_POS 0x2 -#define TIMER_MODE_BIT_POS 0x6 -#define TIMER_ENABLE_BIT_POS 0x7 - -/* Options defines */ -// TODO (MIV): put this in an enumerated value -typedef enum { - CLK_DIVIDER_1 = 0, - CLK_DIVIDER_2 = 3, - CLK_DIVIDER_8 = 4, - CLK_DIVIDER_16 = 1, - CLK_DIVIDER_32 = 5, - CLK_DIVIDER_128 = 6, - CLK_DIVIDER_256 = 2, - CLK_DIVIDER_1024 = 7 -} ClockDivider; - -#define TIME_MODE_FREE_RUNNING 0x0 -#define TIME_MODE_PERIODIC 0x1 - -typedef void (*timer_irq_handlers_t)(void) ; - -/** Options to be passed when opening a timer device instance.*/ -typedef struct timer_options { - TimerReg_pt membase; /**< Memory base for the device's registers. */ - uint8_t irq; /**< IRQ number of the IRQ associated to the device. */ - boolean mode; /**< Timer mode: - * - 0 = Free Run mode (no interrupt generation) - * # timer duration = (65535 + 1) * prescaler * peripheral clock (PCLK) period - * - 1 = Periodic mode (interrupt generation) - * # timer duration = (load + 1) * prescaler * peripheral clock (PCLK) period */ - uint8_t prescale; /**< Timer prescaler: from 1 to 1024. - * - CLK_DIVIDER_1 = clock not divided - * - CLK_DIVIDER_2 = clock is divided by 2 - * - CLK_DIVIDER_8 = clock is divided by 8 - * - CLK_DIVIDER_16 = clock is divided by 16 - * - CLK_DIVIDER_32 = clock is divided by 32 - * - CLK_DIVIDER_128 = clock is divided by 128 - * - CLK_DIVIDER_256 = clock is divided by 256 - * - CLK_DIVIDER_1024 = clock is divided by 1024 */ - uint16_t load; /**< Timer load: from 0 to 65535. */ - timer_irq_handlers_t handler; /**< Timer handler or call-back */ -} timer_options_t, *timer_options_pt; - -/** Interrupt handler for timer devices; to be called from an actual ISR. - * @param membase Memory base for the device's registers - */ -void fTimerHandler(TimerReg_pt membase); - -extern void us_timer_isr(void); -extern void us_ticker_isr(void); - -#ifdef __cplusplus -} -#endif - -#endif /* TIMER_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h deleted file mode 100644 index e518b88e95..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h +++ /dev/null @@ -1,138 +0,0 @@ -/** -****************************************************************************** -* @file trim_map.h -* @brief trim register map -* @internal -* @author ON Semiconductor -* $Rev: 3727 $ -* $Date: 2015-09-14 14:38:34 +0530 (Mon, 14 Sep 2015) $ -****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. -* -* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* @endinternal -* -* @ingroup trim -* -* @details -*

-* Rf and Analog control hw module register map -*

-*/ - -#ifndef TRIM_MAP_H_ -#define TRIM_MAP_H_ - -/************************************************************************************************* -* * -* Header files * -* * -*************************************************************************************************/ - -#include "architecture.h" - -/************************************************************************************************** -* * -* Type definitions * -* * -**************************************************************************************************/ - -/** trim register map */ -typedef struct { - __I uint32_t PAD0; /**< 0x1FA0 */ - __I uint32_t MAC_ADDR_LOW; /**< 0x1FA4 */ - __I uint32_t MAC_ADDR_HIGH; /**< 0x1FA8 */ - __I uint32_t TRIM_32K_EXT; /**< 0x1FAC */ - __I uint32_t TRIM_32M_EXT; /**< 0x1FB0 */ - __I uint32_t FVVDH_COMP_TH; /**< 0x1FB4 */ - union { - struct { - __I uint32_t CHANNEL11:4; - __I uint32_t CHANNEL12:4; - __I uint32_t CHANNEL13:4; - __I uint32_t CHANNEL14:4; - __I uint32_t CHANNEL15:4; - __I uint32_t CHANNEL16:4; - __I uint32_t CHANNEL17:4; - __I uint32_t CHANNEL18:4; - } BITS; - __I uint32_t WORD; - } TX_VCO_LUT1; /**< 0x1FB8 */ - union { - struct { - __I uint32_t CHANNEL19:4; - __I uint32_t CHANNEL20:4; - __I uint32_t CHANNEL21:4; - __I uint32_t CHANNEL22:4; - __I uint32_t CHANNEL23:4; - __I uint32_t CHANNEL24:4; - __I uint32_t CHANNEL25:4; - __I uint32_t CHANNEL26:4; - } BITS; - __I uint32_t WORD; - } TX_VCO_LUT2; /**< 0x1FBC */ - union { - struct { - __I uint32_t CHANNEL11:4; - __I uint32_t CHANNEL12:4; - __I uint32_t CHANNEL13:4; - __I uint32_t CHANNEL14:4; - __I uint32_t CHANNEL15:4; - __I uint32_t CHANNEL16:4; - __I uint32_t CHANNEL17:4; - __I uint32_t CHANNEL18:4; - } BITS; - __I uint32_t WORD; - } RX_VCO_LUT1; /**< 0x1FC0 */ - union { - struct { - __I uint32_t CHANNEL19:4; - __I uint32_t CHANNEL20:4; - __I uint32_t CHANNEL21:4; - __I uint32_t CHANNEL22:4; - __I uint32_t CHANNEL23:4; - __I uint32_t CHANNEL24:4; - __I uint32_t CHANNEL25:4; - __I uint32_t CHANNEL26:4; - } BITS; - __I uint32_t WORD; - } RX_VCO_LUT2; /**< 0x1FC4 */ - __I uint32_t ON_RESERVED0; /**< 0x1FC8 */ - __I uint32_t ON_RESERVED1; /**< 0x1FCC */ - __I uint32_t ADC_OFFSET_TRIM; /**< 0x1FD0 */ - __I uint32_t TX_PRE_CHIPS; /**< 0x1FD4 */ - __I uint32_t TX_TRIM; /**< 0x1FD8 */ - __I uint32_t PLL_VCO_TAP_LOCATION; /**< 0x1FDC */ - __I uint32_t PLL_TRIM; /**< 0x1FE0 */ - __I uint32_t RSSI_OFFSET; /**< 0x1FE4 */ - __I uint32_t RX_CHAIN_TRIM; /**< 0x1FE8 */ - __I uint32_t PMU_TRIM; /**< 0x1FEC */ - __I uint32_t WR_SEED_RD_RAND; /**< 0x1FF0 */ - __I uint32_t WAFER_LOCATION; /**< 0x1FF4 */ - __I uint32_t LOT_NUMBER; /**< 0x1FF8 */ - __I uint32_t REVISION_CODE; /**< 0x1FFC */ -} TrimReg_t, *TrimReg_pt; - - -/** User defined trim register map */ -typedef struct { - __IO uint32_t MAC_ADDRESS_LOW; /**< 0x2800 */ - __IO uint32_t MAC_ADDRESS_HIGH; /**< 0x2804 */ - __IO uint32_t TRIM_32K_EXT; /**< 0x2808 */ - __IO uint32_t TRIM_32M_EXT; /**< 0x280C */ - __IO uint32_t RSSI_OFFSET; /**< 0x2810 */ - __IO uint32_t TX_TRIM; /**< 0x2814 */ -} UserTrimReg_t, *UserTrimReg_pt; -#endif /* TRIM_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/types.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/types.h deleted file mode 100644 index d0e7757d9a..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/types.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - ****************************************************************************** - * @file types.h - * @brief Defines a number of general purpose data types. - * @internal - * @author ON Semiconductor - * $Rev: 2074 $ - * $Date: 2013-07-10 18:06:15 +0530 (Wed, 10 Jul 2013) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup util - */ - -#ifndef _UTIL_TYPES_H_ -#define _UTIL_TYPES_H_ - -#include "architecture.h" - -#include -#include - -typedef unsigned char BYTE; -typedef unsigned short WORD; -typedef unsigned long DWORD; -typedef unsigned long long QWORD; - - -typedef unsigned char boolean; - -#define True (1) -#define False (0) - -#define Null NULL - -#endif /* _UTIL_TYPES_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/uart.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/uart.h deleted file mode 100644 index cdb92bc79d..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/uart.h +++ /dev/null @@ -1,67 +0,0 @@ -/** - ****************************************************************************** - * @file uart.h - * @brief Defines common properties of any UART driver. - * @internal - * @author ON Semiconductor - * $Rev: 2074 $ - * $Date: 2013-07-10 18:06:15 +0530 (Wed, 10 Jul 2013) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @details - * A UART driver must comply to the generic driver template (see driver.h), and - * more specifically to the character driver template (see char_driver.h). All - * UART drivers share some properties; defining these is the purpose of this file. - * - * The options passed when opening a UART device should at least include the - * flow control type and the baud rate. These are included in the uart_options_t - * data type. The type can be extended by a UART driver implementation. - * - * The UART driver implementation must make its driver publicly available with - * an external global variable. - * - * @ingroup uart - */ - -#ifndef UART_H_ -#define UART_H_ - -//#include "char_driver.h" - -/** Type listing the supported kinds of flow control. */ -typedef enum { - /** No flow control */ - none, - /** use hardware CTS (External CPU indicates it is ok for the modem to transmit) - * and RTS (modem requests to sent to external CPU) flow control. - */ - rtscts, - /** use hardware CTS/RTS flow control, but CTS is no response to RTS, - * RTS and CTS are used to indicate intent to transmit. - */ - rtscts_e -} flow_control_t; - -/** A set of options to be passed when creating a uart device instance. */ -typedef struct uart_options { - uint32_t baudrate; /**< The expected baud rate. */ - flow_control_t control;/**< Defines type of flow control, none or rtscts */ -} uart_options_t, *uart_options_pt; - -#endif /* UART_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h deleted file mode 100644 index 6329156cce..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - ****************************************************************************** - * @file uart_16c550.h - * @brief Definitions and API for the 16c550 driver. - * @internal - * @author ON Semiconductor - * $Rev: 2607 $ - * $Date: 2013-12-06 18:02:43 +0530 (Fri, 06 Dec 2013) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup uart_16c550 - * - * @details - * The driver for the 16c550 UART is a character driver (see char_driver.h). - * The driver can be accessed via the uart_16c550_driver variable. - * - * This file defines the options structure to be passed to the driver when - * opening a device. The structure depends on the generic uart_options_t - * options structure for any UART implementation (see uart.h). - * - * Any application that uses this driver must define an interrupt handler - * for the 16C550 interrupt and call the fUart16C550Handler() function from - * that ISR. - */ - -#ifndef UART_16C550_H_ -#define UART_16C550_H_ - -#include "architecture.h" -#include "uart.h" -#include "uart_16c550_map.h" -#include "memory_map.h" -#include "crossbar.h" -#include "types.h" -#include "clock.h" -#include "pad.h" -#include "serial_api.h" - -/** A set of options to be passed when opening a 16C550 UART device. */ -typedef struct uart_16c550_options { - uart_options_t uartOptions; /**< The generic UART options. */ - Uart16C550Reg_pt membase; /**< The memory base for the device's registers. */ - uint8_t irq; /**< The IRQ number of the IRQ associated to the device. */ -} uart_16c550_options_t, *uart_16c550_options_pt; - -#define UART_NUM 2 - -#define CTS_ASSERT 1 -#define CTS_UNASSERT 0 -#define RTS_ASSERT 1 -#define RTS_UNASSERT 0 - -#define UART_ERROR_INSUFFICIENT_SPACE ((uint8_t)0xF0) -#define UART_ERROR_TOO_BIG ((uint8_t)0xF1) - -/** The depth of the hardware FIFOs. */ -#define UART_HW_FIFO_DEPTH 16 - -/** The length of the receive buffer in software. */ -#define UART_RX_BUFFER_LENGTH (1<<8) -#define UART_TX_BUFFER_LENGTH (1<<8) - -#define STATUS_INVALID_PARAMETER 0x1 -#define STATUS_SUCCESS 0x1 - -#define UART_LCR_DATALEN_BIT_POS 0 -#define UART_LCR_STPBIT_BIT_POS 2 -#define UART_LCR_PARITY_BIT_POS 3 - -#define UART_FCS_RX_FIFO_RST_BIT_POS 1 -#define UART_FCS_TX_FIFO_RST_BIT_POS 2 - -#define UART_RX_IRQ 0x0 -#define UART_TX_IRQ 0x1 - -#define UART_RX_BUFFER_LEN_MAX 16 - -#define UART_LSR_TX_EMPTY_MASK 0x40 -#define UART_LSR_RX_DATA_READY_MASK 0x01 - -#define UART_IER_TX_EMPTY_MASK 0x02 -#define UART_IER_RX_DATA_READY_MASK 0x01 - -#define UART_DEFAULT_BAUD 9600 - -/** Interrupt handler for 16C550 UART devices; to be called from an actual ISR. - * @param membase The memory base for the device that corresponds to the IRQ. - */ -void fUart16C550Handler(Uart16C550Reg_pt membase); - -/** An externally accessible instance of the UART driver implementation. */ -//extern char_driver_t uart_16c550_driver; -typedef void (*fUartCallBack)(void); -//void serial_init(serial_t *obj, PinName tx, PinName rx); -//extern void fSerialInit(Uart16C550Reg_pt UartRegBase, flow_control_t FlowControl); -extern void fSerialFree(void); -extern void fSerialBaud(Uart16C550Reg_pt UartRegBase, uint32_t BaudRate); -extern void fSerialFormat(Uart16C550Reg_pt UartRegBase, uint8_t DataLen, uint8_t Parity, uint8_t StopBit); -extern void fSerialIrqSet(Uart16C550Reg_pt UartRegBase, fUartCallBack PtrUartCallBack, uint8_t IrqType, boolean Enable); -extern uint8_t fSerialGetc(Uart16C550Reg_pt UartRegBase); -extern void fSerialPutc(Uart16C550Reg_pt UartRegBase, uint8_t c); -extern boolean fSerialReadable(Uart16C550Reg_pt UartRegBase); -extern boolean fSerialWritable(Uart16C550Reg_pt UartRegBase); -extern void fSerialClear(Uart16C550Reg_pt UartRegBase); -extern void fSerialBreakSet(Uart16C550Reg_pt UartRegBase); -extern void fSerialBreakClear(Uart16C550Reg_pt UartRegBase); -extern void fSerialPinoutTx(uint8_t PinNo); - -extern void Uart1_Irq(void); -extern void Uart2_Irq(void); - -#endif /* UART_16C550_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h deleted file mode 100644 index b33ca489fd..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h +++ /dev/null @@ -1,171 +0,0 @@ -/** - ****************************************************************************** - * @file uart_16c550_map.h - * @brief UART module hardware register map. - * @internal - * @author ON Semiconductor. - * $Rev: 2615 $ - * $Date: 2013-12-13 13:17:21 +0530 (Fri, 13 Dec 2013) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup uart_16c550 - * - * @details - *

Reference document(s)

- *

- * - * IPC7202 APB UART Design Specification v1.4 - *

- */ - -#ifndef UART_16C550_MAP_H_ -#define UART_16C550_MAP_H_ - -#include "architecture.h" - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -#define DCTS (uint8_t)0x01 -#define DDSR (uint8_t)0x02 -#define TERI (uint8_t)0x04 -#define DDCD (uint8_t)0x08 -//#define CTS (uint8_t)0x10 -#define DSR (uint8_t)0x20 -#define RI (uint8_t)0x40 -#define DCD (uint8_t)0x80 -#define IER_PWRDNENACTIVE ((uint8_t)(1<<5)) -#define IER_MSI ((uint8_t)(1<<3)) -#define IER_RLSI ((uint8_t)(1<<2)) -#define IER_THRI ((uint8_t)(1<<1)) -#define IER_RDAI ((uint8_t)(1<<0)) -#define FCR_RXFIFOTRIGGERLEVEL_1 ((uint8_t)(0x00)) -#define FCR_RXFIFOTRIGGERLEVEL_4 ((uint8_t)(0x40)) -#define FCR_RXFIFOTRIGGERLEVEL_8 ((uint8_t)(0x80)) -#define FCR_RXFIFOTRIGGERLEVEL_14 ((uint8_t)(0xC0)) -#define FCR_DMA_MODE_0 ((uint8_t)(0<<3)) -#define FCR_DMA_MODE_1 ((uint8_t)(1<<3)) -#define FCR_TXFIFO_RESET ((uint8_t)(1<<2)) -#define FCR_RXFIFO_RESET ((uint8_t)(1<<1)) -#define FCR_FIFO_ENABLE ((uint8_t)(1<<0)) - -/** UART HW Structure Overlay */ -typedef struct { - /** Base address + 0x0: Receive, transmit and divisor_LSB offset */ - union { - __I uint32_t RBR; /**< Received data (8 bits wide) / read only */ - __O uint32_t THR; /**< Data to be transmitted (8 bits wide) / write only */ - __IO uint32_t DLL; /**< If DLAB = 1. LS byte for input to baud rate generator */ - }; - /** Base address + 0x4: Interrupt enable and divisor_MSB offset */ - union { - union { - struct { - __IO uint32_t RX_DATA_INT :1; /**< Enables the received data interrupt, write 1 to enable */ - __IO uint32_t TX_HOLD_INT :1; /**< Enables the transmitter holding interrupt, write 1 to enable */ - __IO uint32_t RX_STATUS_INT :1; /**< Enables the receiver line status interrupt, write 1 to enable */ - __IO uint32_t MODEM_STATUS_INT :1; /**< Enables the modem status interrupt, write 1 to enable */ - __IO uint32_t PAD0 :1; - __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in MCR is set also */ - __IO uint32_t PAD1 :2; - } BITS; - __IO uint32_t WORD; - } IER; /** Interrupt enable offset 0x04 */ - __IO uint32_t DLM; /**< If DLAB = 1. MS byte for input to baud rate generator */ - }; - /** Base address + 0x8: Interrupt status and fifo control offset*/ - union { - union { - struct { - __I uint32_t INT_PEND :1; /**< Interrupt is pending if 1 */ - __I uint32_t INT_ID :3; /**< Interrupt identification: 011-RX Line, 010-Rx Data, 110-char TO, 001-TX empty, 000-Modem status*/ - __I uint32_t PAD0 :2; - __I uint32_t FIFO_EN :2; /**< Fifos enabled: 00-disabled, 01/10-undefined, 11-enabled */ - } BITS; - __I uint32_t WORD; - } IIR; /** Interrupt status and fifo status offset 0x08 */ - union { - struct { - __O uint32_t FIFO_EN :1; /**< FIFO enable, write 1 to enable */ - __O uint32_t RX_FIFO_RST :1; /**< RX FIFO reset, write 1 to reset */ - __O uint32_t TX_FIFO_RST :1; /**< TX FIFO reset, write 1 to reset */ - __O uint32_t DMA_SEL :1; /**< DMA mode select */ - __O uint32_t PAD0 :2; - __O uint32_t RX_FIFO_TRIG :2; /**< Receiver FIFO trigger level:00-1byte, 01-4bytes, 10-8bytes, 11-14bytes */ - } BITS; - __O uint32_t WORD; - } FCR; /** Fifo control offset 0x08 */ - }; - /** Base address + 0xC: Line control offset */ - union { - struct { - __IO uint32_t CHAR_LEN :2; /**< Number of bits per character: 00-5bits, 01-6bits, 10:7bits, 11:8bits */ - __IO uint32_t NUM_STOP :1; /**< Number of stop bits: 0-1bit, 1-2bits */ - __IO uint32_t PARITY :3; /**< Parity: xx0-disable, 001-odd, 011-even, 101-stick generated/checked as 1, 111-stick generated/checked as 0 */ - __IO uint32_t BREAK :1; /**< Set to 1 to force output to 0, set to 0 to return to normal operation */ - __IO uint32_t DLAB :1; /**< Set to 1 to enable the DLL, DLM registers at 0x00 and 0x04 */ - } BITS; - __IO uint32_t WORD; - } LCR; /** Line control offset 0x0C */ - /** Base address + 0x10: Modem control offset */ - union { - struct { - __IO uint32_t DTR :1; /**< Data terminal ready. Write 1 to set DTR high (de-asserted), or read DTR */ - __IO uint32_t RTS :1; /**< Request to send. Write 1 to set RTS high (de-asserted), or read RTS */ - __IO uint32_t OUTN_CTRL :2; /**< Direct control of out2N and out1N */ - __IO uint32_t LOOPBACK :1; /**< Write 1 to enable loop back */ - __IO uint32_t PAD0 :3; - __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in IER is set also */ - } BITS; - __IO uint32_t WORD; - } MCR; /**< Modem control offset 0x10 */ - /** Base address + 0x14: Line status offset */ - union { - struct { - __O uint32_t READY :1; /**< Rx data available */ - __O uint32_t OVERRUN_ERR :1; /**< Overrun error */ - __O uint32_t PARITY_ERR :1; /**< Parity error */ - __O uint32_t FRAME_ERR :1; /**< Framing error */ - __O uint32_t BREAK_INT :1; /**< Break interrupt is set when output is kept to 0 for more than 1 bit time */ - __O uint32_t TX_HOLD_EMPTY :1; /**< Transmit holding register empty */ - __O uint32_t TX_EMPTY :1; /**< Transmitter empty */ - __O uint32_t FIFO_ERR :1; /**< Receive fifo error */ - } BITS; - __O uint32_t WORD; - } LSR; /**< Line status offset 0x14 */ - /** Base address + 0x18: Modem status offset */ - union { - struct { - __O uint32_t CHG_CTSN :1; /**< CTS change since last MSR read */ - __O uint32_t CHG_DSRN :1; /**< DSR change since last MSR read */ - __O uint32_t CHG_RIN :1; /**< RI change since last MSR read */ - __O uint32_t CHG_DCDN :1; /**< DCD change since last MSR read */ - __O uint32_t CURR_CTSN :1; /**< CTS current state, 0 = asserted, 1 = de-asserted */ - __O uint32_t CURR_DSRN :1; /**< DSR current state */ - __O uint32_t CURR_RIN :1; /**< RI current state */ - __O uint32_t CURR_DCDN :1; /**< DCD current state */ - } BITS; - __O uint32_t WORD; - } MSR; /**< Modem status offset 0x18 */ - /** Base address + 0x1C: Scratch offset*/ - __IO uint32_t SCR; /**< Scratch pad register */ -} Uart16C550Reg_t, *Uart16C550Reg_pt; - -#endif /* UART_16C550_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/watchdog_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/watchdog_api.c deleted file mode 100644 index 6f899496b4..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/watchdog_api.c +++ /dev/null @@ -1,116 +0,0 @@ -/** - ******************************************************************************* - * @file watchdog_api.c - * @brief Implementation of watchdog_api - * @internal - * @author ON Semiconductor - ****************************************************************************** - * Copyright 2018 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - */ -#include "watchdog_api.h" -#if DEVICE_WATCHDOG - -#include "clock.h" // Peripheral clock control definitions. -#include "wdt_map.h" // Watchdog hardware register definitions. -#include "memory_map.h" // Pointer to watchdog peripheral in memory. - - -// watchdog_api feature definitions -#define WDT_MAX_TIMEOUT_MS ((uint32_t)8000) -#define WDT_CAN_UPDATE ((boolean)True) -#define WDT_CAN_STOP ((boolean)True) - -// WDT LOAD register definitions -#define WDT_MAX_LOAD_VAL ((uint32_t)0x3FFFF) -#define WDT_TICKS_PER_MS (WDT_MAX_LOAD_VAL / WDT_MAX_TIMEOUT_MS) - -// WDT KICK register definitions -#define WDT_KICK_VAL ((uint32_t)1) - -// WDT LOCK register definitions -#define WDT_LOCK_DISABLE ((uint32_t)0x1ACCE551) -#define WDT_LOCK_ENABLE ((uint32_t)0x00000000) - - -watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) -{ - if (!config || config->timeout_ms > WDT_MAX_TIMEOUT_MS || config->timeout_ms == 0) { - return WATCHDOG_STATUS_INVALID_ARGUMENT; - } - - if (!CLOCK_IS_ENABLED(CLOCK_WDOG)) { - CLOCK_ENABLE(CLOCK_WDOG); - } - - // Disable write lock in case WDT is being reconfigured. - WDTREG->LOCK = WDT_LOCK_DISABLE; - - while (WDTREG->STATUS.BITS.WRITE_BUSY_ANY); - WDTREG->LOAD = config->timeout_ms * WDT_TICKS_PER_MS; - - while (WDTREG->STATUS.BITS.WRITE_BUSY_LOAD); - WDTREG->CONTROL.BITS.WDT_EN = True; - - while (WDTREG->STATUS.BITS.WRITE_BUSY_CONTROL); - WDTREG->LOCK = WDT_LOCK_ENABLE; - - return WATCHDOG_STATUS_OK; -} - -void hal_watchdog_kick(void) -{ - // Write any value to kick watchdog. - WDTREG->KICK = WDT_KICK_VAL; -} - -watchdog_status_t hal_watchdog_stop(void) -{ - WDTREG->LOCK = WDT_LOCK_DISABLE; - - while (WDTREG->STATUS.BITS.WRITE_BUSY_ANY); - WDTREG->CONTROL.BITS.WDT_EN = False; - - while (WDTREG->STATUS.BITS.WRITE_BUSY_ANY); - CLOCK_DISABLE(CLOCK_WDOG); - - return WATCHDOG_STATUS_OK; -} - -uint32_t hal_watchdog_get_reload_value(void) -{ - while (WDTREG->STATUS.BITS.WRITE_BUSY_LOAD); - return WDTREG->LOAD / WDT_TICKS_PER_MS; -} - -watchdog_features_t hal_watchdog_get_platform_features(void) -{ - const watchdog_features_t features = { - .max_timeout = WDT_MAX_TIMEOUT_MS, - .update_config = WDT_CAN_UPDATE, - .disable_watchdog = WDT_CAN_STOP, - .clock_typical_frequency = 36000, - .clock_max_frequency = 47000 - }; - - return features; -} - - -#endif // DEVICE_WATCHDOG - diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h deleted file mode 100644 index a4ac0bcd55..0000000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - ****************************************************************************** - * @file wdt_map.h - * @brief WDT HW register map - * @internal - * @author ON Semiconductor - * $Rev: 3283 $ - * $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $ - ****************************************************************************** - * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”). - * All rights reserved. This software and/or documentation is licensed by ON Semiconductor - * under limited terms and conditions. The terms and conditions pertaining to the software - * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf - * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and - * if applicable the software license agreement. Do not use this software and/or - * documentation unless you have carefully read and you agree to the limited terms and - * conditions. By using this software and/or documentation, you agree to the limited - * terms and conditions. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, - * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * @endinternal - * - * @ingroup wdt - * - * @details - *

- * Watchdog Timer HW register map description - *

- * - */ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -#ifndef WDT_MAP_H_ -#define WDT_MAP_H_ - -#include "architecture.h" - -typedef struct { - __IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */ - __I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */ - union { - struct { - __IO uint32_t WDT_EN :1; /**< Watchdog enable, 0 – Watchdog disabled, 1 – Watchdog enabled */ - } BITS; - __IO uint32_t WORD; - } CONTROL; /* 0x4000A008 */ - __O uint32_t KICK; /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */ - __O uint32_t LOCK; /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write access. A read from this register only returns the bottom bit…, 0 – Write access is enabled, 1 – Write access is disabled */ - union { - struct { - __I uint32_t WRITE_BUSY_ANY :1; /**< Busy writing any register */ - __I uint32_t WRITE_BUSY_LOAD :1; /**< Busy writing the load register */ - __I uint32_t WRITE_BUSY_CONTROL :1; /**< Busy writing the control enable register */ - __IO uint32_t WRITE_ERROR :1; /**< Error bit. Set when write occurs before previous write completes (busy) */ - } BITS; - __IO uint32_t WORD; - } STATUS; /* 0x4000A014 */ -} WdtReg_t, *WdtReg_pt; -#endif /* WDT_MAP_H_ */ diff --git a/targets/TARGET_ONSEMI/mbed_rtx.h b/targets/TARGET_ONSEMI/mbed_rtx.h deleted file mode 100644 index 58677a495e..0000000000 --- a/targets/TARGET_ONSEMI/mbed_rtx.h +++ /dev/null @@ -1,28 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_MBED_RTX_H -#define MBED_MBED_RTX_H - -#if defined(TARGET_NCS36510) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x40000000UL) -#endif - -#endif - -#endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index 5946a064dd..01607f930f 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -7517,82 +7517,6 @@ "1302" ] }, - "NCS36510": { - "inherits": [ - "Target" - ], - "core": "Cortex-M3", - "extra_labels": [ - "ONSEMI" - ], - "config": { - "mac-addr-low": { - "help": "Lower 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.", - "value": "0xFFFFFFFF" - }, - "mac-addr-high": { - "help": "Higher 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.", - "value": "0xFFFFFFFF" - }, - "32KHz-clk-trim": { - "help": "32KHz clock trim", - "value": "0x39" - }, - "32MHz-clk-trim": { - "help": "32MHz clock trim", - "value": "0x17" - }, - "rssi-trim": { - "help": "RSSI trim", - "value": "0x3D" - }, - "txtune-trim": { - "help": "TX tune trim", - "value": "0xFFFFFFFF" - } - }, - "OUTPUT_EXT": "hex", - "post_binary_hook": { - "function": "NCS36510TargetCode.ncs36510_addfib" - }, - "macros": [ - "CM3", - "CPU_NCS36510", - "TARGET_NCS36510", - "LOAD_ADDRESS=0x3000" - ], - "supported_toolchains": [ - "GCC_ARM", - "ARM", - "IAR" - ], - "device_has": [ - "ANALOGIN", - "SERIAL", - "I2C", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "TRNG", - "SPISLAVE", - "WATCHDOG", - "802_15_4_PHY", - "MPU", - "USTICKER" - ], - "release_versions": [ - "2", - "5" - ], - "detect_code": [ - "1200" - ] - }, "NUMAKER_PFM_M453": { "core": "Cortex-M4F", "default_toolchain": "ARM", diff --git a/tools/export/codeblocks/__init__.py b/tools/export/codeblocks/__init__.py index 92cf57565c..527994a4f6 100644 --- a/tools/export/codeblocks/__init__.py +++ b/tools/export/codeblocks/__init__.py @@ -35,7 +35,6 @@ class CodeBlocks(GccArm): PREPROCESS_ASM = False POST_BINARY_WHITELIST = set([ - "NCS36510TargetCode.ncs36510_addfib", "PSOC6Code.complete" ]) diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index 66485b7874..8c281ef385 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -246,9 +246,6 @@ "CExtraOptions": "--drv_vector_table_base=0x0", "CMSISDAPJtagSpeedList": 10 }, - "NCS36510":{ - "OGChipSelectEditMenu": "NCS36510\tONSemiconductor NCS36510" - }, "NANO130KE3BN": { "OGChipSelectEditMenu": "Nano100BN series\tNuvoton Nano100BN series (Nano100BN,Nano110BN,Nano120BN,Nano130BN)", "IlinkOverrideProgramEntryLabel": 1, diff --git a/tools/export/uvision/__init__.py b/tools/export/uvision/__init__.py index 02b330f64d..467b70263a 100644 --- a/tools/export/uvision/__init__.py +++ b/tools/export/uvision/__init__.py @@ -135,7 +135,6 @@ class Uvision(Exporter): "MCU_NRF51Code.binary_hook", "LPCTargetCode.lpc_patch", "MTSCode.combine_bins_mts_dragonfly", - "NCS36510TargetCode.ncs36510_addfib", "LPC55S69Code.binary_hook", "M2351Code.merge_secure" ]) diff --git a/tools/targets/NCS.py b/tools/targets/NCS.py deleted file mode 100644 index 710e48c466..0000000000 --- a/tools/targets/NCS.py +++ /dev/null @@ -1,241 +0,0 @@ -""" -@copyright (c) 2012 ON Semiconductor. All rights reserved. -ON Semiconductor is supplying this software for use with ON Semiconductor -processor based microcontrollers only. -THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, -INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -""" - -from __future__ import absolute_import -from __future__ import print_function - -import itertools -import binascii -import intelhex -from tools.config import Config - -FIB_BASE = 0x2000 -TRIM_BASE = 0x2800 -FLASH_BASE = 0x3000 -FLASHA_SIZE = 0x52000 -FLASHB_BASE = 0x00102000 -FLASHB_SIZE = 0x52000 -FW_REV = 0x01000100 - -def ranges(i): - for _, b in itertools.groupby(enumerate(i), lambda x_y: x_y[1] - x_y[0]): - b = list(b) - yield b[0][1], b[-1][1] - - -def add_fib_at_start(arginput): - input_file = arginput + ".hex" - file_name_hex = arginput + ".hex" - file_name_bin = arginput + ".bin" - - # Read in hex file - input_hex_file = intelhex.IntelHex() - input_hex_file.loadhex(input_file) - #set padding value to be returned when reading from unspecified address - input_hex_file.padding = 0xFF - # Create new hex file - output_hex_file = intelhex.IntelHex() - - # Get the starting and ending address - addresses = input_hex_file.addresses() - addresses.sort() - start_end_pairs = list(ranges(addresses)) - regions = len(start_end_pairs) - - if regions == 1: - #single range indicating fits within first flash block (<320K) - start, end = start_end_pairs[0] - print("Memory start 0x%08X, end 0x%08X" % (start, end)) - # Compute checksum over the range (don't include data at location of crc) - size = end - start + 1 - data = input_hex_file.tobinarray(start=start, size=size) - crc32 = binascii.crc32(data) & 0xFFFFFFFF - else: - #multiple ranges indicating requires both flash blocks (>320K) - start, end = start_end_pairs[0] - start2, end2 = start_end_pairs[1] - print("Region 1: memory start 0x%08X, end 0x%08X" % (start, end)) - print("Region 2: memory start 0x%08X, end 0x%08X" % (start2, end2)) - # Compute checksum over the range (don't include data at location of crc) - # replace end with end of flash block A - end = FLASHA_SIZE - 1 - size = end - start + 1 - data = input_hex_file.tobinarray(start=start, size=size) - - # replace start2 with base of flash block B - start2 = FLASHB_BASE - size2 = end2 - start2 + 1 - data2 = input_hex_file.tobinarray(start=start2, size=size2) - - #concatenate data and data2 arrays together - data.extend(data2) - crc32 = binascii.crc32(data) & 0xFFFFFFFF - - #replace size with sum of two memory region sizes - size = size + size2 - - assert start >= FLASH_BASE, ("Error - start 0x%x less than begining of user\ - flash area" %start) - - assert regions <= 2, ("Error - more than 2 memory regions found") - - fw_rev = FW_REV - - checksum = (start + size + crc32 + fw_rev) & 0xFFFFFFFF - - print("Writing FIB: base 0x%08X, size 0x%08X, crc32 0x%08X, fw rev 0x%08X,\ - checksum 0x%08X" % (start, size, crc32, fw_rev, checksum)) - -#expected initial values used by daplink to validate that it is a valid bin -#file added as dummy values in this file because the fib area preceeds the -#application area the bootloader will ignore these dummy values -# 00 is stack pointer (RAM address) -# 04 is Reset vector (FLASH address) -# 08 NMI_Handler (FLASH address) -# 0C HardFault_Handler(FLASH address) -# 10 dummy - dummy_sp = 0x3FFFFC00 - dummy_reset_vector = 0x00003625 - dummy_nmi_handler = 0x00003761 - dummy_hardfault_handler = 0x00003691 - dummy_blank = 0x00000000 - -#expected fib structure -#typedef struct fib{ - #uint32_t base; /**< Base offset of firmware, indicating what flash the - # firmware is in. (will never be 0x11111111) */ - #uint32_t size; /**< Size of the firmware */ - #uint32_t crc; /**< CRC32 for firmware correctness check */ - #uint32_t rev; /**< Revision number */ - #uint32_t checksum; /**< Check-sum of information block */ -#}fib_t, *fib_pt; - - fib_start = FIB_BASE - dummy_fib_size = 20 - fib_size = 20 - trim_size = 24 - user_code_start = FLASH_BASE - trim_area_start = TRIM_BASE - - # Write FIB to the file in little endian - output_hex_file[fib_start + 0] = (dummy_sp >> 0) & 0xFF - output_hex_file[fib_start + 1] = (dummy_sp >> 8) & 0xFF - output_hex_file[fib_start + 2] = (dummy_sp >> 16) & 0xFF - output_hex_file[fib_start + 3] = (dummy_sp >> 24) & 0xFF - - output_hex_file[fib_start + 4] = (dummy_reset_vector >> 0) & 0xFF - output_hex_file[fib_start + 5] = (dummy_reset_vector >> 8) & 0xFF - output_hex_file[fib_start + 6] = (dummy_reset_vector >> 16) & 0xFF - output_hex_file[fib_start + 7] = (dummy_reset_vector >> 24) & 0xFF - - output_hex_file[fib_start + 8] = (dummy_nmi_handler >> 0) & 0xFF - output_hex_file[fib_start + 9] = (dummy_nmi_handler >> 8) & 0xFF - output_hex_file[fib_start + 10] = (dummy_nmi_handler >> 16) & 0xFF - output_hex_file[fib_start + 11] = (dummy_nmi_handler >> 24) & 0xFF - - output_hex_file[fib_start + 12] = (dummy_hardfault_handler >> 0) & 0xFF - output_hex_file[fib_start + 13] = (dummy_hardfault_handler >> 8) & 0xFF - output_hex_file[fib_start + 14] = (dummy_hardfault_handler >> 16) & 0xFF - output_hex_file[fib_start + 15] = (dummy_hardfault_handler >> 24) & 0xFF - - output_hex_file[fib_start + 16] = (dummy_blank >> 0) & 0xFF - output_hex_file[fib_start + 17] = (dummy_blank >> 8) & 0xFF - output_hex_file[fib_start + 18] = (dummy_blank >> 16) & 0xFF - output_hex_file[fib_start + 19] = (dummy_blank >> 24) & 0xFF - - # Write FIB to the file in little endian - output_hex_file[fib_start + 20] = (start >> 0) & 0xFF - output_hex_file[fib_start + 21] = (start >> 8) & 0xFF - output_hex_file[fib_start + 22] = (start >> 16) & 0xFF - output_hex_file[fib_start + 23] = (start >> 24) & 0xFF - - output_hex_file[fib_start + 24] = (size >> 0) & 0xFF - output_hex_file[fib_start + 25] = (size >> 8) & 0xFF - output_hex_file[fib_start + 26] = (size >> 16) & 0xFF - output_hex_file[fib_start + 27] = (size >> 24) & 0xFF - - output_hex_file[fib_start + 28] = (crc32 >> 0) & 0xFF - output_hex_file[fib_start + 29] = (crc32 >> 8) & 0xFF - output_hex_file[fib_start + 30] = (crc32 >> 16) & 0xFF - output_hex_file[fib_start + 31] = (crc32 >> 24) & 0xFF - - output_hex_file[fib_start + 32] = (fw_rev >> 0) & 0xFF - output_hex_file[fib_start + 33] = (fw_rev >> 8) & 0xFF - output_hex_file[fib_start + 34] = (fw_rev >> 16) & 0xFF - output_hex_file[fib_start + 35] = (fw_rev >> 24) & 0xFF - - output_hex_file[fib_start + 36] = (checksum >> 0) & 0xFF - output_hex_file[fib_start + 37] = (checksum >> 8) & 0xFF - output_hex_file[fib_start + 38] = (checksum >> 16) & 0xFF - output_hex_file[fib_start + 39] = (checksum >> 24) & 0xFF - - #pad the rest of the file - for i in range(fib_start + dummy_fib_size + fib_size, trim_area_start): - output_hex_file[i] = 0xFF - - # Read in configuration data from the config parameter in targets.json - configData = Config('NCS36510') - paramData = configData.get_target_config_data() - for v in paramData.values(): - if (v.name == "target.mac-addr-high"): - mac_addr_high = int(v.value, 16) - elif (v.name == "target.mac-addr-low"): - mac_addr_low = int(v.value,16) - elif (v.name == "target.32KHz-clk-trim"): - clk_32k_trim = int(v.value,16) - elif (v.name == "target.32MHz-clk-trim"): - clk_32m_trim = int(v.value,16) - elif (v.name == "target.rssi-trim"): - rssi = int(v.value,16) - elif (v.name == "target.txtune-trim"): - txtune = int(v.value,16) - else: - print("Not a valid param") - - output_hex_file[trim_area_start + 0] = mac_addr_low & 0xFF - output_hex_file[trim_area_start + 1] = (mac_addr_low >> 8) & 0xFF - output_hex_file[trim_area_start + 2] = (mac_addr_low >> 16) & 0xFF - output_hex_file[trim_area_start + 3] = (mac_addr_low >> 24) & 0xFF - - output_hex_file[trim_area_start + 4] = mac_addr_high & 0xFF - output_hex_file[trim_area_start + 5] = (mac_addr_high >> 8) & 0xFF - output_hex_file[trim_area_start + 6] = (mac_addr_high >> 16) & 0xFF - output_hex_file[trim_area_start + 7] = (mac_addr_high >> 24) & 0xFF - - output_hex_file[trim_area_start + 8] = clk_32k_trim & 0xFF - output_hex_file[trim_area_start + 9] = (clk_32k_trim >> 8) & 0xFF - output_hex_file[trim_area_start + 10] = (clk_32k_trim >> 16) & 0xFF - output_hex_file[trim_area_start + 11] = (clk_32k_trim >> 24) & 0xFF - - output_hex_file[trim_area_start + 12] = clk_32m_trim & 0xFF - output_hex_file[trim_area_start + 13] = (clk_32m_trim >> 8) & 0xFF - output_hex_file[trim_area_start + 14] = (clk_32m_trim >> 16) & 0xFF - output_hex_file[trim_area_start + 15] = (clk_32m_trim >> 24) & 0xFF - - output_hex_file[trim_area_start + 16] = rssi & 0xFF - output_hex_file[trim_area_start + 17] = (rssi >> 8) & 0xFF - output_hex_file[trim_area_start + 18] = (rssi >> 16) & 0xFF - output_hex_file[trim_area_start + 19] = (rssi >> 24) & 0xFF - - output_hex_file[trim_area_start + 20] = txtune & 0xFF - output_hex_file[trim_area_start + 21] = (txtune >> 8) & 0xFF - output_hex_file[trim_area_start + 22] = (txtune >> 16) & 0xFF - output_hex_file[trim_area_start + 23] = (txtune >> 24) & 0xFF - - # pad the rest of the area with 0xFF - for i in range(trim_area_start + trim_size, user_code_start): - output_hex_file[i] = 0xFF - - #merge two hex files - output_hex_file.merge(input_hex_file, overlap='error') - - # Write out file(s) - output_hex_file.tofile(file_name_hex, 'hex') diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index 30a88fa18f..72ce4e9b24 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -573,14 +573,6 @@ class MCU_NRF51Code(object): binh.write_hex_file(fileout, write_start_addr=False) -class NCS36510TargetCode(object): - @staticmethod - def ncs36510_addfib(t_self, resources, elf, binf): - from tools.targets.NCS import add_fib_at_start - print("binf ", binf) - add_fib_at_start(binf[:-4]) - - class RTL8195ACode(object): """RTL8195A Hooks""" @staticmethod