From 071cffafc5e77f68ef3efca43084e84bf7b2fe36 Mon Sep 17 00:00:00 2001 From: Jerome Coutant Date: Tue, 15 Feb 2022 11:19:17 +0100 Subject: [PATCH] STM32G4 : STM32G471xx CMSIS file --- .../STM32Cube_FW/CMSIS/stm32g471xx.h | 228 ++++++++++-------- 1 file changed, 130 insertions(+), 98 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h index 00b93f5839..89dac423a7 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -45,11 +44,11 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ /** * @} @@ -125,7 +124,6 @@ typedef enum TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ @@ -141,6 +139,10 @@ typedef enum COMP4_IRQn = 65, /*!< COMP4 */ CRS_IRQn = 75, /*!< CRS global interrupt */ SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */ I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */ @@ -967,6 +969,10 @@ typedef struct } UCPD_TypeDef; +/** + * @} + */ + /** @addtogroup Peripheral_memory_map * @{ */ @@ -1002,7 +1008,6 @@ typedef struct #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) #define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) @@ -1052,6 +1057,7 @@ typedef struct #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) #define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) @@ -1144,7 +1150,6 @@ typedef struct #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) @@ -1192,6 +1197,7 @@ typedef struct #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) @@ -1277,6 +1283,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2928,9 +2943,6 @@ typedef struct #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U) #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */ #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk -#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) -#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */ -#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U) #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */ #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk @@ -2980,6 +2992,9 @@ typedef struct #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U) #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk +#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U) +#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */ +#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk /******************************************************************************/ /* */ @@ -8101,9 +8116,6 @@ typedef struct #define RCC_APB1RSTR1_TIM4RST_Pos (2U) #define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */ #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk -#define RCC_APB1RSTR1_TIM5RST_Pos (3U) -#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */ -#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk #define RCC_APB1RSTR1_TIM6RST_Pos (4U) #define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */ #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk @@ -8192,6 +8204,9 @@ typedef struct #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_TIM20RST_Pos (20U) +#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */ +#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk #define RCC_APB2RSTR_SAI1RST_Pos (21U) #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */ #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk @@ -8272,9 +8287,6 @@ typedef struct #define RCC_APB1ENR1_TIM4EN_Pos (2U) #define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */ #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk -#define RCC_APB1ENR1_TIM5EN_Pos (3U) -#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */ -#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk #define RCC_APB1ENR1_TIM6EN_Pos (4U) #define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */ #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk @@ -8369,6 +8381,9 @@ typedef struct #define RCC_APB2ENR_TIM17EN_Pos (18U) #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */ #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_TIM20EN_Pos (20U) +#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */ +#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk #define RCC_APB2ENR_SAI1EN_Pos (21U) #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */ #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk @@ -8458,9 +8473,6 @@ typedef struct #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U) #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */ #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk -#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U) -#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */ -#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U) #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */ #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk @@ -8555,6 +8567,9 @@ typedef struct #define RCC_APB2SMENR_TIM17SMEN_Pos (18U) #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */ #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk +#define RCC_APB2SMENR_TIM20SMEN_Pos (20U) +#define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */ +#define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk #define RCC_APB2SMENR_SAI1SMEN_Pos (21U) #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */ #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk @@ -13396,122 +13411,127 @@ typedef struct ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting 32 bits counter ****************/ -#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM5)) +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /************** TIM Instances : supporting Break source selection *************/ #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting 2 break inputs *****************/ #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /************* TIM Instances : at least 1 capture/compare channel *************/ #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /************ TIM Instances : at least 2 capture/compare channels *************/ #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20)) /************ TIM Instances : at least 3 capture/compare channels *************/ #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /************ TIM Instances : at least 4 capture/compare channels *************/ #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : at least 5 capture/compare channels *******/ #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : at least 6 capture/compare channels *******/ #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /******************** TIM Instances : DMA burst feature ***********************/ #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /******************* TIM Instances : output(s) available **********************/ #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ @@ -13541,12 +13561,6 @@ typedef struct ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ - (((INSTANCE) == TIM5) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4))) \ - || \ (((INSTANCE) == TIM8) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ @@ -13563,7 +13577,15 @@ typedef struct (((CHANNEL) == TIM_CHANNEL_1))) \ || \ (((INSTANCE) == TIM17) && \ - (((CHANNEL) == TIM_CHANNEL_1)))) + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM20) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6)))) /****************** TIM Instances : supporting complementary output(s) ********/ #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ @@ -13586,135 +13608,143 @@ typedef struct ((CHANNEL) == TIM_CHANNEL_1)) \ || \ (((INSTANCE) == TIM17) && \ - ((CHANNEL) == TIM_CHANNEL_1))) + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM20) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4)))) /****************** TIM Instances : supporting clock division *****************/ #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15)|| \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15)|| \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting commutation event generation ***/ #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting counting mode selection ********/ #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting encoder interface **************/ #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting Hall sensor interface **********/ #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20)) /**************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /************* TIM Instances : supporting ETR source selection ***************/ #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20)) /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ @@ -13723,51 +13753,54 @@ typedef struct ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting repetition counter *************/ #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /******************* TIM Instances : Timer input XOR function *****************/ #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20)) /******************* TIM Instances : Timer input selection ********************/ #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : Advanced timer instances *******************/ #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) - + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting HSE/32 request instances *******************/ #define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \ @@ -13907,4 +13940,3 @@ typedef struct * @} */ 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