mirror of https://github.com/ARMmbed/mbed-os.git
Martin Kojtal
GitHub
commit
06da49984f
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@ -69,44 +69,44 @@ static int aes_set_key(mbedtls_aes_context *ctx,
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const unsigned char *key,
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const unsigned char *key,
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unsigned int keybits)
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unsigned int keybits)
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{
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{
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/* Deinitializes the CRYP peripheral */
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/* Deinitializes the CRYP peripheral */
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if (HAL_CRYP_DeInit(&ctx->hcryp_aes) == HAL_ERROR) {
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if (HAL_CRYP_DeInit(&ctx->hcryp_aes) == HAL_ERROR) {
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return (HAL_ERROR);
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return (HAL_ERROR);
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}
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}
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switch (keybits) {
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switch (keybits) {
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case 128:
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case 128:
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ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_128B;;
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ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_128B;;
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SWAP_B8_TO_B32(ctx->aes_key[0],key,0);
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SWAP_B8_TO_B32(ctx->aes_key[0], key, 0);
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SWAP_B8_TO_B32(ctx->aes_key[1],key,4);
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SWAP_B8_TO_B32(ctx->aes_key[1], key, 4);
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SWAP_B8_TO_B32(ctx->aes_key[2],key,8);
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SWAP_B8_TO_B32(ctx->aes_key[2], key, 8);
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SWAP_B8_TO_B32(ctx->aes_key[3],key,12);
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SWAP_B8_TO_B32(ctx->aes_key[3], key, 12);
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break;
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break;
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case 192:
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case 192:
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ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_192B;
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ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_192B;
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SWAP_B8_TO_B32(ctx->aes_key[0],key,0);
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SWAP_B8_TO_B32(ctx->aes_key[0], key, 0);
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SWAP_B8_TO_B32(ctx->aes_key[1],key,4);
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SWAP_B8_TO_B32(ctx->aes_key[1], key, 4);
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SWAP_B8_TO_B32(ctx->aes_key[2],key,8);
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SWAP_B8_TO_B32(ctx->aes_key[2], key, 8);
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SWAP_B8_TO_B32(ctx->aes_key[3],key,12);
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SWAP_B8_TO_B32(ctx->aes_key[3], key, 12);
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SWAP_B8_TO_B32(ctx->aes_key[4],key,16);
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SWAP_B8_TO_B32(ctx->aes_key[4], key, 16);
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SWAP_B8_TO_B32(ctx->aes_key[5],key,20);
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SWAP_B8_TO_B32(ctx->aes_key[5], key, 20);
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break;
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break;
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case 256:
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case 256:
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ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_256B;
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ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_256B;
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SWAP_B8_TO_B32(ctx->aes_key[0],key,0);
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SWAP_B8_TO_B32(ctx->aes_key[0], key, 0);
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SWAP_B8_TO_B32(ctx->aes_key[1],key,4);
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SWAP_B8_TO_B32(ctx->aes_key[1], key, 4);
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SWAP_B8_TO_B32(ctx->aes_key[2],key,8);
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SWAP_B8_TO_B32(ctx->aes_key[2], key, 8);
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SWAP_B8_TO_B32(ctx->aes_key[3],key,12);
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SWAP_B8_TO_B32(ctx->aes_key[3], key, 12);
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SWAP_B8_TO_B32(ctx->aes_key[4],key,16);
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SWAP_B8_TO_B32(ctx->aes_key[4], key, 16);
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SWAP_B8_TO_B32(ctx->aes_key[5],key,20);
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SWAP_B8_TO_B32(ctx->aes_key[5], key, 20);
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SWAP_B8_TO_B32(ctx->aes_key[6],key,24);
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SWAP_B8_TO_B32(ctx->aes_key[6], key, 24);
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SWAP_B8_TO_B32(ctx->aes_key[7],key,28);
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SWAP_B8_TO_B32(ctx->aes_key[7], key, 28);
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break;
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break;
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default :
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default :
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@ -141,9 +141,9 @@ static void mbedtls_zeroize(void *v, size_t n)
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void mbedtls_aes_init(mbedtls_aes_context *ctx)
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void mbedtls_aes_init(mbedtls_aes_context *ctx)
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{
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{
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AES_VALIDATE( ctx != NULL );
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AES_VALIDATE(ctx != NULL);
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memset(ctx, 0, sizeof(mbedtls_aes_context));
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memset(ctx, 0, sizeof(mbedtls_aes_context));
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}
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}
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@ -163,21 +163,22 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx)
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}
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}
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#if defined(MBEDTLS_CIPHER_MODE_XTS)
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#if defined(MBEDTLS_CIPHER_MODE_XTS)
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void mbedtls_aes_xts_init( mbedtls_aes_xts_context *ctx )
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void mbedtls_aes_xts_init(mbedtls_aes_xts_context *ctx)
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{
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{
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AES_VALIDATE( ctx != NULL );
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AES_VALIDATE(ctx != NULL);
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mbedtls_aes_init( &ctx->crypt );
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mbedtls_aes_init(&ctx->crypt);
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mbedtls_aes_init( &ctx->tweak );
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mbedtls_aes_init(&ctx->tweak);
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}
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}
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void mbedtls_aes_xts_free( mbedtls_aes_xts_context *ctx )
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void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx)
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{
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{
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if( ctx == NULL )
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if (ctx == NULL) {
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return;
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return;
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}
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mbedtls_aes_free( &ctx->crypt );
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mbedtls_aes_free(&ctx->crypt);
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mbedtls_aes_free( &ctx->tweak );
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mbedtls_aes_free(&ctx->tweak);
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}
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}
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#endif /* MBEDTLS_CIPHER_MODE_XTS */
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#endif /* MBEDTLS_CIPHER_MODE_XTS */
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@ -189,8 +190,8 @@ int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key,
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{
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{
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int ret_val = 0;
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int ret_val = 0;
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AES_VALIDATE_RET( ctx != NULL );
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AES_VALIDATE_RET(ctx != NULL);
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AES_VALIDATE_RET( key != NULL );
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AES_VALIDATE_RET(key != NULL);
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ret_val = aes_set_key(ctx, key, keybits);
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ret_val = aes_set_key(ctx, key, keybits);
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return (ret_val);
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return (ret_val);
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@ -204,29 +205,31 @@ int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key,
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{
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{
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int ret_val = 0;
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int ret_val = 0;
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AES_VALIDATE_RET( ctx != NULL );
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AES_VALIDATE_RET(ctx != NULL);
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AES_VALIDATE_RET( key != NULL );
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AES_VALIDATE_RET(key != NULL);
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ret_val = aes_set_key(ctx, key, keybits);
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ret_val = aes_set_key(ctx, key, keybits);
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return (ret_val);
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return (ret_val);
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}
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}
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#if defined(MBEDTLS_CIPHER_MODE_XTS)
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#if defined(MBEDTLS_CIPHER_MODE_XTS)
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static int mbedtls_aes_xts_decode_keys( const unsigned char *key,
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static int mbedtls_aes_xts_decode_keys(const unsigned char *key,
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unsigned int keybits,
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unsigned int keybits,
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const unsigned char **key1,
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const unsigned char **key1,
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unsigned int *key1bits,
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unsigned int *key1bits,
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const unsigned char **key2,
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const unsigned char **key2,
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unsigned int *key2bits )
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unsigned int *key2bits)
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{
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{
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const unsigned int half_keybits = keybits / 2;
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const unsigned int half_keybits = keybits / 2;
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const unsigned int half_keybytes = half_keybits / 8;
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const unsigned int half_keybytes = half_keybits / 8;
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switch( keybits )
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switch (keybits) {
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{
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case 256:
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case 256: break;
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break;
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case 512: break;
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case 512:
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default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
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break;
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default :
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return (MBEDTLS_ERR_AES_INVALID_KEY_LENGTH);
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}
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}
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*key1bits = half_keybits;
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*key1bits = half_keybits;
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@ -237,54 +240,58 @@ static int mbedtls_aes_xts_decode_keys( const unsigned char *key,
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return 0;
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return 0;
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}
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}
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int mbedtls_aes_xts_setkey_enc( mbedtls_aes_xts_context *ctx,
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int mbedtls_aes_xts_setkey_enc(mbedtls_aes_xts_context *ctx,
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const unsigned char *key,
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const unsigned char *key,
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unsigned int keybits)
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unsigned int keybits)
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{
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{
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int ret;
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int ret;
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const unsigned char *key1, *key2;
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const unsigned char *key1, *key2;
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unsigned int key1bits, key2bits;
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unsigned int key1bits, key2bits;
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AES_VALIDATE_RET( ctx != NULL );
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AES_VALIDATE_RET(ctx != NULL);
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AES_VALIDATE_RET( key != NULL );
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AES_VALIDATE_RET(key != NULL);
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ret = mbedtls_aes_xts_decode_keys( key, keybits, &key1, &key1bits,
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ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits,
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&key2, &key2bits );
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&key2, &key2bits);
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if( ret != 0 )
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if (ret != 0) {
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return( ret );
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return (ret);
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}
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/* Set the tweak key. Always set tweak key for the encryption mode. */
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/* Set the tweak key. Always set tweak key for the encryption mode. */
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ret = mbedtls_aes_setkey_enc( &ctx->tweak, key2, key2bits );
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ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits);
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if( ret != 0 )
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if (ret != 0) {
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return( ret );
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return (ret);
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}
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/* Set crypt key for encryption. */
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/* Set crypt key for encryption. */
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return mbedtls_aes_setkey_enc( &ctx->crypt, key1, key1bits );
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return mbedtls_aes_setkey_enc(&ctx->crypt, key1, key1bits);
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}
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}
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int mbedtls_aes_xts_setkey_dec( mbedtls_aes_xts_context *ctx,
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int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx,
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const unsigned char *key,
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const unsigned char *key,
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unsigned int keybits)
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unsigned int keybits)
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{
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{
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int ret;
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int ret;
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const unsigned char *key1, *key2;
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const unsigned char *key1, *key2;
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unsigned int key1bits, key2bits;
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unsigned int key1bits, key2bits;
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AES_VALIDATE_RET( ctx != NULL );
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AES_VALIDATE_RET(ctx != NULL);
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AES_VALIDATE_RET( key != NULL );
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AES_VALIDATE_RET(key != NULL);
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ret = mbedtls_aes_xts_decode_keys( key, keybits, &key1, &key1bits,
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ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits,
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&key2, &key2bits );
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&key2, &key2bits);
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if( ret != 0 )
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if (ret != 0) {
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return( ret );
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return (ret);
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}
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/* Set the tweak key. Always set tweak key for encryption. */
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/* Set the tweak key. Always set tweak key for encryption. */
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ret = mbedtls_aes_setkey_enc( &ctx->tweak, key2, key2bits );
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ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits);
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if( ret != 0 )
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if (ret != 0) {
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return( ret );
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return (ret);
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}
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/* Set crypt key for decryption. */
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/* Set crypt key for decryption. */
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return mbedtls_aes_setkey_dec( &ctx->crypt, key1, key1bits );
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return mbedtls_aes_setkey_dec(&ctx->crypt, key1, key1bits);
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}
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}
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#endif /* MBEDTLS_CIPHER_MODE_XTS */
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#endif /* MBEDTLS_CIPHER_MODE_XTS */
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@ -296,13 +303,13 @@ int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx,
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const unsigned char input[16],
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const unsigned char input[16],
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unsigned char output[16])
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unsigned char output[16])
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{
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{
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int ret;
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int ret;
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AES_VALIDATE_RET( ctx != NULL );
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AES_VALIDATE_RET(ctx != NULL);
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AES_VALIDATE_RET( input != NULL );
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AES_VALIDATE_RET(input != NULL);
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AES_VALIDATE_RET( output != NULL );
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AES_VALIDATE_RET(output != NULL);
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AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT ||
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AES_VALIDATE_RET(mode == MBEDTLS_AES_ENCRYPT ||
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mode == MBEDTLS_AES_DECRYPT );
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mode == MBEDTLS_AES_DECRYPT);
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/* allow multi-instance of CRYP use: restore context for CRYP hw module */
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/* allow multi-instance of CRYP use: restore context for CRYP hw module */
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ctx->hcryp_aes.Instance->CR = ctx->ctx_save_cr;
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ctx->hcryp_aes.Instance->CR = ctx->ctx_save_cr;
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@ -311,8 +318,7 @@ int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx,
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ctx->hcryp_aes.Init.pKey = ctx->aes_key;
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ctx->hcryp_aes.Init.pKey = ctx->aes_key;
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/* Set the Algo if not configured till now */
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/* Set the Algo if not configured till now */
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if (CRYP_AES_ECB != ctx->hcryp_aes.Init.Algorithm)
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if (CRYP_AES_ECB != ctx->hcryp_aes.Init.Algorithm) {
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{
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ctx->hcryp_aes.Init.Algorithm = CRYP_AES_ECB;
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ctx->hcryp_aes.Init.Algorithm = CRYP_AES_ECB;
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/* Configure the CRYP */
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/* Configure the CRYP */
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@ -365,14 +371,14 @@ int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx,
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uint32_t tickstart;
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uint32_t tickstart;
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uint32_t *iv_ptr = (uint32_t *)&iv[0];
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uint32_t *iv_ptr = (uint32_t *)&iv[0];
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ALIGN_32BYTES (static uint32_t iv_32B[4]);
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ALIGN_32BYTES(static uint32_t iv_32B[4]);
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AES_VALIDATE_RET( ctx != NULL );
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AES_VALIDATE_RET(ctx != NULL);
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AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT ||
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AES_VALIDATE_RET(mode == MBEDTLS_AES_ENCRYPT ||
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mode == MBEDTLS_AES_DECRYPT );
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mode == MBEDTLS_AES_DECRYPT);
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AES_VALIDATE_RET( iv != NULL );
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AES_VALIDATE_RET(iv != NULL);
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AES_VALIDATE_RET( input != NULL );
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AES_VALIDATE_RET(input != NULL);
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AES_VALIDATE_RET( output != NULL );
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AES_VALIDATE_RET(output != NULL);
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if (length % 16) {
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if (length % 16) {
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return (MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH);
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return (MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH);
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@ -383,8 +389,7 @@ int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx,
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}
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}
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/* Set the Algo if not configured till now */
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/* Set the Algo if not configured till now */
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if (CRYP_AES_CBC != ctx->hcryp_aes.Init.Algorithm)
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if (CRYP_AES_CBC != ctx->hcryp_aes.Init.Algorithm) {
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{
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ctx->hcryp_aes.Init.Algorithm = CRYP_AES_CBC;
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ctx->hcryp_aes.Init.Algorithm = CRYP_AES_CBC;
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}
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}
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@ -394,7 +399,7 @@ int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx,
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/* reconfigure the CRYP */
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/* reconfigure the CRYP */
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HAL_CRYP_SetConfig(&ctx->hcryp_aes, &ctx->hcryp_aes.Init);
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HAL_CRYP_SetConfig(&ctx->hcryp_aes, &ctx->hcryp_aes.Init);
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if (HAL_CRYP_Decrypt(&ctx->hcryp_aes, (uint32_t *)input, length/4, (uint32_t *)output, TIMEOUT_VALUE) != HAL_OK) {
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if (HAL_CRYP_Decrypt(&ctx->hcryp_aes, (uint32_t *)input, length / 4, (uint32_t *)output, TIMEOUT_VALUE) != HAL_OK) {
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return ST_ERR_AES_BUSY;
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return ST_ERR_AES_BUSY;
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}
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}
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@ -415,14 +420,14 @@ int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx,
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ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
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ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
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ctx->hcryp_aes.Init.DataWidthUnit = CRYP_DATAWIDTHUNIT_BYTE;
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ctx->hcryp_aes.Init.DataWidthUnit = CRYP_DATAWIDTHUNIT_BYTE;
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SWAP_B8_TO_B32(iv_32B[0],iv,0);
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SWAP_B8_TO_B32(iv_32B[0], iv, 0);
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SWAP_B8_TO_B32(iv_32B[1],iv,4);
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SWAP_B8_TO_B32(iv_32B[1], iv, 4);
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SWAP_B8_TO_B32(iv_32B[2],iv,8);
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SWAP_B8_TO_B32(iv_32B[2], iv, 8);
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SWAP_B8_TO_B32(iv_32B[3],iv,12);
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SWAP_B8_TO_B32(iv_32B[3], iv, 12);
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ctx->hcryp_aes.Init.pInitVect = iv_32B;
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ctx->hcryp_aes.Init.pInitVect = iv_32B;
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/* reconfigure the CRYP */
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/* reconfigure the CRYP */
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HAL_CRYP_SetConfig(&ctx->hcryp_aes, &ctx->hcryp_aes.Init);
|
HAL_CRYP_SetConfig(&ctx->hcryp_aes, &ctx->hcryp_aes.Init);
|
||||||
|
|
||||||
if (HAL_CRYP_Encrypt(&ctx->hcryp_aes, (uint32_t *)input, length, (uint32_t *)output, TIMEOUT_VALUE) != HAL_OK) {
|
if (HAL_CRYP_Encrypt(&ctx->hcryp_aes, (uint32_t *)input, length, (uint32_t *)output, TIMEOUT_VALUE) != HAL_OK) {
|
||||||
|
|
@ -476,30 +481,30 @@ int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx,
|
||||||
* for machine endianess and hence works correctly on both big and little
|
* for machine endianess and hence works correctly on both big and little
|
||||||
* endian machines.
|
* endian machines.
|
||||||
*/
|
*/
|
||||||
static void mbedtls_gf128mul_x_ble( unsigned char r[16],
|
static void mbedtls_gf128mul_x_ble(unsigned char r[16],
|
||||||
const unsigned char x[16] )
|
const unsigned char x[16])
|
||||||
{
|
{
|
||||||
uint64_t a, b, ra, rb;
|
uint64_t a, b, ra, rb;
|
||||||
|
|
||||||
GET_UINT64_LE( a, x, 0 );
|
GET_UINT64_LE(a, x, 0);
|
||||||
GET_UINT64_LE( b, x, 8 );
|
GET_UINT64_LE(b, x, 8);
|
||||||
|
|
||||||
ra = ( a << 1 ) ^ 0x0087 >> ( 8 - ( ( b >> 63 ) << 3 ) );
|
ra = (a << 1) ^ 0x0087 >> (8 - ((b >> 63) << 3));
|
||||||
rb = ( a >> 63 ) | ( b << 1 );
|
rb = (a >> 63) | (b << 1);
|
||||||
|
|
||||||
PUT_UINT64_LE( ra, r, 0 );
|
PUT_UINT64_LE(ra, r, 0);
|
||||||
PUT_UINT64_LE( rb, r, 8 );
|
PUT_UINT64_LE(rb, r, 8);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* AES-XTS buffer encryption/decryption
|
* AES-XTS buffer encryption/decryption
|
||||||
*/
|
*/
|
||||||
int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx,
|
int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx,
|
||||||
int mode,
|
int mode,
|
||||||
size_t length,
|
size_t length,
|
||||||
const unsigned char data_unit[16],
|
const unsigned char data_unit[16],
|
||||||
const unsigned char *input,
|
const unsigned char *input,
|
||||||
unsigned char *output )
|
unsigned char *output)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
size_t blocks = length / 16;
|
size_t blocks = length / 16;
|
||||||
|
|
@ -508,61 +513,64 @@ int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx,
|
||||||
unsigned char prev_tweak[16];
|
unsigned char prev_tweak[16];
|
||||||
unsigned char tmp[16];
|
unsigned char tmp[16];
|
||||||
|
|
||||||
AES_VALIDATE_RET( ctx != NULL );
|
AES_VALIDATE_RET(ctx != NULL);
|
||||||
AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT ||
|
AES_VALIDATE_RET(mode == MBEDTLS_AES_ENCRYPT ||
|
||||||
mode == MBEDTLS_AES_DECRYPT );
|
mode == MBEDTLS_AES_DECRYPT);
|
||||||
AES_VALIDATE_RET( data_unit != NULL );
|
AES_VALIDATE_RET(data_unit != NULL);
|
||||||
AES_VALIDATE_RET( input != NULL );
|
AES_VALIDATE_RET(input != NULL);
|
||||||
AES_VALIDATE_RET( output != NULL );
|
AES_VALIDATE_RET(output != NULL);
|
||||||
|
|
||||||
/* Data units must be at least 16 bytes long. */
|
/* Data units must be at least 16 bytes long. */
|
||||||
if( length < 16 )
|
if (length < 16) {
|
||||||
return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH;
|
return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH;
|
||||||
|
}
|
||||||
|
|
||||||
/* NIST SP 800-38E disallows data units larger than 2**20 blocks. */
|
/* NIST SP 800-38E disallows data units larger than 2**20 blocks. */
|
||||||
if( length > ( 1 << 20 ) * 16 )
|
if (length > (1 << 20) * 16) {
|
||||||
return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH;
|
return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH;
|
||||||
|
}
|
||||||
|
|
||||||
/* Compute the tweak. */
|
/* Compute the tweak. */
|
||||||
ret = mbedtls_aes_crypt_ecb( &ctx->tweak, MBEDTLS_AES_ENCRYPT,
|
ret = mbedtls_aes_crypt_ecb(&ctx->tweak, MBEDTLS_AES_ENCRYPT,
|
||||||
data_unit, tweak );
|
data_unit, tweak);
|
||||||
if( ret != 0 )
|
if (ret != 0) {
|
||||||
return( ret );
|
return (ret);
|
||||||
|
}
|
||||||
|
|
||||||
while( blocks-- )
|
while (blocks--) {
|
||||||
{
|
|
||||||
size_t i;
|
size_t i;
|
||||||
|
|
||||||
if( leftover && ( mode == MBEDTLS_AES_DECRYPT ) && blocks == 0 )
|
if (leftover && (mode == MBEDTLS_AES_DECRYPT) && blocks == 0) {
|
||||||
{
|
|
||||||
/* We are on the last block in a decrypt operation that has
|
/* We are on the last block in a decrypt operation that has
|
||||||
* leftover bytes, so we need to use the next tweak for this block,
|
* leftover bytes, so we need to use the next tweak for this block,
|
||||||
* and this tweak for the lefover bytes. Save the current tweak for
|
* and this tweak for the lefover bytes. Save the current tweak for
|
||||||
* the leftovers and then update the current tweak for use on this,
|
* the leftovers and then update the current tweak for use on this,
|
||||||
* the last full block. */
|
* the last full block. */
|
||||||
memcpy( prev_tweak, tweak, sizeof( tweak ) );
|
memcpy(prev_tweak, tweak, sizeof(tweak));
|
||||||
mbedtls_gf128mul_x_ble( tweak, tweak );
|
mbedtls_gf128mul_x_ble(tweak, tweak);
|
||||||
}
|
}
|
||||||
|
|
||||||
for( i = 0; i < 16; i++ )
|
for (i = 0; i < 16; i++) {
|
||||||
tmp[i] = input[i] ^ tweak[i];
|
tmp[i] = input[i] ^ tweak[i];
|
||||||
|
}
|
||||||
|
|
||||||
ret = mbedtls_aes_crypt_ecb( &ctx->crypt, mode, tmp, tmp );
|
ret = mbedtls_aes_crypt_ecb(&ctx->crypt, mode, tmp, tmp);
|
||||||
if( ret != 0 )
|
if (ret != 0) {
|
||||||
return( ret );
|
return (ret);
|
||||||
|
}
|
||||||
|
|
||||||
for( i = 0; i < 16; i++ )
|
for (i = 0; i < 16; i++) {
|
||||||
output[i] = tmp[i] ^ tweak[i];
|
output[i] = tmp[i] ^ tweak[i];
|
||||||
|
}
|
||||||
|
|
||||||
/* Update the tweak for the next block. */
|
/* Update the tweak for the next block. */
|
||||||
mbedtls_gf128mul_x_ble( tweak, tweak );
|
mbedtls_gf128mul_x_ble(tweak, tweak);
|
||||||
|
|
||||||
output += 16;
|
output += 16;
|
||||||
input += 16;
|
input += 16;
|
||||||
}
|
}
|
||||||
|
|
||||||
if( leftover )
|
if (leftover) {
|
||||||
{
|
|
||||||
/* If we are on the leftover bytes in a decrypt operation, we need to
|
/* If we are on the leftover bytes in a decrypt operation, we need to
|
||||||
* use the previous tweak for these bytes (as saved in prev_tweak). */
|
* use the previous tweak for these bytes (as saved in prev_tweak). */
|
||||||
unsigned char *t = mode == MBEDTLS_AES_DECRYPT ? prev_tweak : tweak;
|
unsigned char *t = mode == MBEDTLS_AES_DECRYPT ? prev_tweak : tweak;
|
||||||
|
|
@ -576,28 +584,30 @@ int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx,
|
||||||
* byte of cyphertext we won't steal. At the same time, copy the
|
* byte of cyphertext we won't steal. At the same time, copy the
|
||||||
* remainder of the input for this final round (since the loop bounds
|
* remainder of the input for this final round (since the loop bounds
|
||||||
* are the same). */
|
* are the same). */
|
||||||
for( i = 0; i < leftover; i++ )
|
for (i = 0; i < leftover; i++) {
|
||||||
{
|
|
||||||
output[i] = prev_output[i];
|
output[i] = prev_output[i];
|
||||||
tmp[i] = input[i] ^ t[i];
|
tmp[i] = input[i] ^ t[i];
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Copy ciphertext bytes from the previous block for input in this
|
/* Copy ciphertext bytes from the previous block for input in this
|
||||||
* round. */
|
* round. */
|
||||||
for( ; i < 16; i++ )
|
for (; i < 16; i++) {
|
||||||
tmp[i] = prev_output[i] ^ t[i];
|
tmp[i] = prev_output[i] ^ t[i];
|
||||||
|
}
|
||||||
|
|
||||||
ret = mbedtls_aes_crypt_ecb( &ctx->crypt, mode, tmp, tmp );
|
ret = mbedtls_aes_crypt_ecb(&ctx->crypt, mode, tmp, tmp);
|
||||||
if( ret != 0 )
|
if (ret != 0) {
|
||||||
return ret;
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
/* Write the result back to the previous block, overriding the previous
|
/* Write the result back to the previous block, overriding the previous
|
||||||
* output we copied. */
|
* output we copied. */
|
||||||
for( i = 0; i < 16; i++ )
|
for (i = 0; i < 16; i++) {
|
||||||
prev_output[i] = tmp[i] ^ t[i];
|
prev_output[i] = tmp[i] ^ t[i];
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return( 0 );
|
return (0);
|
||||||
}
|
}
|
||||||
#endif /* MBEDTLS_CIPHER_MODE_XTS */
|
#endif /* MBEDTLS_CIPHER_MODE_XTS */
|
||||||
|
|
||||||
|
|
@ -616,13 +626,13 @@ int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx,
|
||||||
int c;
|
int c;
|
||||||
size_t n;
|
size_t n;
|
||||||
|
|
||||||
AES_VALIDATE_RET( ctx != NULL );
|
AES_VALIDATE_RET(ctx != NULL);
|
||||||
AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT ||
|
AES_VALIDATE_RET(mode == MBEDTLS_AES_ENCRYPT ||
|
||||||
mode == MBEDTLS_AES_DECRYPT );
|
mode == MBEDTLS_AES_DECRYPT);
|
||||||
AES_VALIDATE_RET( iv_off != NULL );
|
AES_VALIDATE_RET(iv_off != NULL);
|
||||||
AES_VALIDATE_RET( iv != NULL );
|
AES_VALIDATE_RET(iv != NULL);
|
||||||
AES_VALIDATE_RET( input != NULL );
|
AES_VALIDATE_RET(input != NULL);
|
||||||
AES_VALIDATE_RET( output != NULL );
|
AES_VALIDATE_RET(output != NULL);
|
||||||
|
|
||||||
n = *iv_off;
|
n = *iv_off;
|
||||||
|
|
||||||
|
|
@ -670,12 +680,12 @@ int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx,
|
||||||
unsigned char c;
|
unsigned char c;
|
||||||
unsigned char ov[17];
|
unsigned char ov[17];
|
||||||
|
|
||||||
AES_VALIDATE_RET( ctx != NULL );
|
AES_VALIDATE_RET(ctx != NULL);
|
||||||
AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT ||
|
AES_VALIDATE_RET(mode == MBEDTLS_AES_ENCRYPT ||
|
||||||
mode == MBEDTLS_AES_DECRYPT );
|
mode == MBEDTLS_AES_DECRYPT);
|
||||||
AES_VALIDATE_RET( iv != NULL );
|
AES_VALIDATE_RET(iv != NULL);
|
||||||
AES_VALIDATE_RET( input != NULL );
|
AES_VALIDATE_RET(input != NULL);
|
||||||
AES_VALIDATE_RET( output != NULL );
|
AES_VALIDATE_RET(output != NULL);
|
||||||
|
|
||||||
while (length--) {
|
while (length--) {
|
||||||
memcpy(ov, iv, 16);
|
memcpy(ov, iv, 16);
|
||||||
|
|
@ -705,44 +715,44 @@ int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx,
|
||||||
/*
|
/*
|
||||||
* AES-OFB (Output Feedback Mode) buffer encryption/decryption
|
* AES-OFB (Output Feedback Mode) buffer encryption/decryption
|
||||||
*/
|
*/
|
||||||
int mbedtls_aes_crypt_ofb( mbedtls_aes_context *ctx,
|
int mbedtls_aes_crypt_ofb(mbedtls_aes_context *ctx,
|
||||||
size_t length,
|
size_t length,
|
||||||
size_t *iv_off,
|
size_t *iv_off,
|
||||||
unsigned char iv[16],
|
unsigned char iv[16],
|
||||||
const unsigned char *input,
|
const unsigned char *input,
|
||||||
unsigned char *output )
|
unsigned char *output)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
size_t n;
|
size_t n;
|
||||||
|
|
||||||
AES_VALIDATE_RET( ctx != NULL );
|
AES_VALIDATE_RET(ctx != NULL);
|
||||||
AES_VALIDATE_RET( iv_off != NULL );
|
AES_VALIDATE_RET(iv_off != NULL);
|
||||||
AES_VALIDATE_RET( iv != NULL );
|
AES_VALIDATE_RET(iv != NULL);
|
||||||
AES_VALIDATE_RET( input != NULL );
|
AES_VALIDATE_RET(input != NULL);
|
||||||
AES_VALIDATE_RET( output != NULL );
|
AES_VALIDATE_RET(output != NULL);
|
||||||
|
|
||||||
n = *iv_off;
|
n = *iv_off;
|
||||||
|
|
||||||
if( n > 15 )
|
if (n > 15) {
|
||||||
return( MBEDTLS_ERR_AES_BAD_INPUT_DATA );
|
return (MBEDTLS_ERR_AES_BAD_INPUT_DATA);
|
||||||
|
}
|
||||||
|
|
||||||
while( length-- )
|
while (length--) {
|
||||||
{
|
if (n == 0) {
|
||||||
if( n == 0 )
|
ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv);
|
||||||
{
|
if (ret != 0) {
|
||||||
ret = mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
|
|
||||||
if( ret != 0 )
|
|
||||||
goto exit;
|
goto exit;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
*output++ = *input++ ^ iv[n];
|
*output++ = *input++ ^ iv[n];
|
||||||
|
|
||||||
n = ( n + 1 ) & 0x0F;
|
n = (n + 1) & 0x0F;
|
||||||
}
|
}
|
||||||
|
|
||||||
*iv_off = n;
|
*iv_off = n;
|
||||||
|
|
||||||
exit:
|
exit:
|
||||||
return( ret );
|
return (ret);
|
||||||
}
|
}
|
||||||
#endif /* MBEDTLS_CIPHER_MODE_OFB */
|
#endif /* MBEDTLS_CIPHER_MODE_OFB */
|
||||||
|
|
||||||
|
|
@ -761,12 +771,12 @@ int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx,
|
||||||
int c, i;
|
int c, i;
|
||||||
size_t n;
|
size_t n;
|
||||||
|
|
||||||
AES_VALIDATE_RET( ctx != NULL );
|
AES_VALIDATE_RET(ctx != NULL);
|
||||||
AES_VALIDATE_RET( nc_off != NULL );
|
AES_VALIDATE_RET(nc_off != NULL);
|
||||||
AES_VALIDATE_RET( nonce_counter != NULL );
|
AES_VALIDATE_RET(nonce_counter != NULL);
|
||||||
AES_VALIDATE_RET( stream_block != NULL );
|
AES_VALIDATE_RET(stream_block != NULL);
|
||||||
AES_VALIDATE_RET( input != NULL );
|
AES_VALIDATE_RET(input != NULL);
|
||||||
AES_VALIDATE_RET( output != NULL );
|
AES_VALIDATE_RET(output != NULL);
|
||||||
|
|
||||||
n = *nc_off;
|
n = *nc_off;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -73,8 +73,7 @@ mbedtls_aes_context;
|
||||||
/**
|
/**
|
||||||
* \brief The AES XTS context-type definition.
|
* \brief The AES XTS context-type definition.
|
||||||
*/
|
*/
|
||||||
typedef struct mbedtls_aes_xts_context
|
typedef struct mbedtls_aes_xts_context {
|
||||||
{
|
|
||||||
mbedtls_aes_context crypt; /*!< The AES context to use for AES block
|
mbedtls_aes_context crypt; /*!< The AES context to use for AES block
|
||||||
encryption or decryption. */
|
encryption or decryption. */
|
||||||
mbedtls_aes_context tweak; /*!< The AES context used for tweak
|
mbedtls_aes_context tweak; /*!< The AES context used for tweak
|
||||||
|
|
@ -105,7 +104,7 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx);
|
||||||
*
|
*
|
||||||
* \param ctx The AES XTS context to initialize. This must not be \c NULL.
|
* \param ctx The AES XTS context to initialize. This must not be \c NULL.
|
||||||
*/
|
*/
|
||||||
void mbedtls_aes_xts_init( mbedtls_aes_xts_context *ctx );
|
void mbedtls_aes_xts_init(mbedtls_aes_xts_context *ctx);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* \brief This function releases and clears the specified AES XTS context.
|
* \brief This function releases and clears the specified AES XTS context.
|
||||||
|
|
@ -114,7 +113,7 @@ void mbedtls_aes_xts_init( mbedtls_aes_xts_context *ctx );
|
||||||
* If this is \c NULL, this function does nothing.
|
* If this is \c NULL, this function does nothing.
|
||||||
* Otherwise, the context must have been at least initialized.
|
* Otherwise, the context must have been at least initialized.
|
||||||
*/
|
*/
|
||||||
void mbedtls_aes_xts_free( mbedtls_aes_xts_context *ctx );
|
void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx);
|
||||||
#endif /* MBEDTLS_CIPHER_MODE_XTS */
|
#endif /* MBEDTLS_CIPHER_MODE_XTS */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -158,9 +157,9 @@ int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key,
|
||||||
* \return \c 0 on success.
|
* \return \c 0 on success.
|
||||||
* \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
|
* \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
|
||||||
*/
|
*/
|
||||||
int mbedtls_aes_xts_setkey_enc( mbedtls_aes_xts_context *ctx,
|
int mbedtls_aes_xts_setkey_enc(mbedtls_aes_xts_context *ctx,
|
||||||
const unsigned char *key,
|
const unsigned char *key,
|
||||||
unsigned int keybits );
|
unsigned int keybits);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* \brief This function prepares an XTS context for decryption and
|
* \brief This function prepares an XTS context for decryption and
|
||||||
|
|
@ -178,9 +177,9 @@ int mbedtls_aes_xts_setkey_enc( mbedtls_aes_xts_context *ctx,
|
||||||
* \return \c 0 on success.
|
* \return \c 0 on success.
|
||||||
* \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
|
* \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
|
||||||
*/
|
*/
|
||||||
int mbedtls_aes_xts_setkey_dec( mbedtls_aes_xts_context *ctx,
|
int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx,
|
||||||
const unsigned char *key,
|
const unsigned char *key,
|
||||||
unsigned int keybits );
|
unsigned int keybits);
|
||||||
#endif /* MBEDTLS_CIPHER_MODE_XTS */
|
#endif /* MBEDTLS_CIPHER_MODE_XTS */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -265,12 +264,12 @@ int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx,
|
||||||
* smaller than an AES block in size (16 Bytes) or if \p
|
* smaller than an AES block in size (16 Bytes) or if \p
|
||||||
* length is larger than 2^20 blocks (16 MiB).
|
* length is larger than 2^20 blocks (16 MiB).
|
||||||
*/
|
*/
|
||||||
int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx,
|
int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx,
|
||||||
int mode,
|
int mode,
|
||||||
size_t length,
|
size_t length,
|
||||||
const unsigned char data_unit[16],
|
const unsigned char data_unit[16],
|
||||||
const unsigned char *input,
|
const unsigned char *input,
|
||||||
unsigned char *output );
|
unsigned char *output);
|
||||||
#endif /* MBEDTLS_CIPHER_MODE_XTS */
|
#endif /* MBEDTLS_CIPHER_MODE_XTS */
|
||||||
|
|
||||||
#if defined(MBEDTLS_CIPHER_MODE_CFB)
|
#if defined(MBEDTLS_CIPHER_MODE_CFB)
|
||||||
|
|
@ -385,12 +384,12 @@ int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx,
|
||||||
*
|
*
|
||||||
* \return \c 0 on success.
|
* \return \c 0 on success.
|
||||||
*/
|
*/
|
||||||
int mbedtls_aes_crypt_ofb( mbedtls_aes_context *ctx,
|
int mbedtls_aes_crypt_ofb(mbedtls_aes_context *ctx,
|
||||||
size_t length,
|
size_t length,
|
||||||
size_t *iv_off,
|
size_t *iv_off,
|
||||||
unsigned char iv[16],
|
unsigned char iv[16],
|
||||||
const unsigned char *input,
|
const unsigned char *input,
|
||||||
unsigned char *output );
|
unsigned char *output);
|
||||||
|
|
||||||
#endif /* MBEDTLS_CIPHER_MODE_OFB */
|
#endif /* MBEDTLS_CIPHER_MODE_OFB */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -63,8 +63,7 @@
|
||||||
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
{
|
{
|
||||||
GPIO_InitTypeDef GPIO_InitStruct;
|
GPIO_InitTypeDef GPIO_InitStruct;
|
||||||
if(heth->Instance == ETH)
|
if (heth->Instance == ETH) {
|
||||||
{
|
|
||||||
/* Disable DCache for STM32H7 family */
|
/* Disable DCache for STM32H7 family */
|
||||||
SCB_DisableDCache();
|
SCB_DisableDCache();
|
||||||
|
|
||||||
|
|
@ -80,37 +79,37 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
__HAL_RCC_ETH1TX_CLK_ENABLE();
|
__HAL_RCC_ETH1TX_CLK_ENABLE();
|
||||||
__HAL_RCC_ETH1RX_CLK_ENABLE();
|
__HAL_RCC_ETH1RX_CLK_ENABLE();
|
||||||
|
|
||||||
/**ETH GPIO Configuration
|
/**ETH GPIO Configuration
|
||||||
PG11 ------> ETH_TX_EN
|
PG11 ------> ETH_TX_EN
|
||||||
PG12 ------> ETH_TXD1
|
PG12 ------> ETH_TXD1
|
||||||
PG13 ------> ETH_TXD0
|
PG13 ------> ETH_TXD0
|
||||||
PC1 ------> ETH_MDC
|
PC1 ------> ETH_MDC
|
||||||
PA2 ------> ETH_MDIO
|
PA2 ------> ETH_MDIO
|
||||||
PA1 ------> ETH_REF_CLK
|
PA1 ------> ETH_REF_CLK
|
||||||
PA7 ------> ETH_CRS_DV
|
PA7 ------> ETH_CRS_DV
|
||||||
PC4 ------> ETH_RXD0
|
PC4 ------> ETH_RXD0
|
||||||
PC5 ------> ETH_RXD1
|
PC5 ------> ETH_RXD1
|
||||||
*/
|
*/
|
||||||
GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin;
|
GPIO_InitStruct.Pin = ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin;
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||||
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
||||||
|
|
||||||
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin;
|
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin;
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
||||||
|
|
||||||
GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin;
|
GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin;
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||||
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -120,29 +119,28 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
*/
|
*/
|
||||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
|
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
|
||||||
{
|
{
|
||||||
if(heth->Instance == ETH)
|
if (heth->Instance == ETH) {
|
||||||
{
|
/* Peripheral clock disable */
|
||||||
/* Peripheral clock disable */
|
__HAL_RCC_ETH1MAC_CLK_DISABLE();
|
||||||
__HAL_RCC_ETH1MAC_CLK_DISABLE();
|
__HAL_RCC_ETH1TX_CLK_DISABLE();
|
||||||
__HAL_RCC_ETH1TX_CLK_DISABLE();
|
__HAL_RCC_ETH1RX_CLK_DISABLE();
|
||||||
__HAL_RCC_ETH1RX_CLK_DISABLE();
|
|
||||||
|
|
||||||
/**ETH GPIO Configuration
|
|
||||||
PG11 ------> ETH_TX_EN
|
|
||||||
PG12 ------> ETH_TXD1
|
|
||||||
PG13 ------> ETH_TXD0
|
|
||||||
PC1 ------> ETH_MDC
|
|
||||||
PA2 ------> ETH_MDIO
|
|
||||||
PA1 ------> ETH_REF_CLK
|
|
||||||
PA7 ------> ETH_CRS_DV
|
|
||||||
PC4 ------> ETH_RXD0
|
|
||||||
PC5 ------> ETH_RXD1
|
|
||||||
*/
|
|
||||||
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin);
|
|
||||||
|
|
||||||
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin);
|
/**ETH GPIO Configuration
|
||||||
|
PG11 ------> ETH_TX_EN
|
||||||
|
PG12 ------> ETH_TXD1
|
||||||
|
PG13 ------> ETH_TXD0
|
||||||
|
PC1 ------> ETH_MDC
|
||||||
|
PA2 ------> ETH_MDIO
|
||||||
|
PA1 ------> ETH_REF_CLK
|
||||||
|
PA7 ------> ETH_CRS_DV
|
||||||
|
PC4 ------> ETH_RXD0
|
||||||
|
PC5 ------> ETH_RXD1
|
||||||
|
*/
|
||||||
|
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin);
|
||||||
|
|
||||||
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin);
|
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin);
|
||||||
|
|
||||||
|
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -61,8 +61,7 @@
|
||||||
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
{
|
{
|
||||||
GPIO_InitTypeDef GPIO_InitStruct;
|
GPIO_InitTypeDef GPIO_InitStruct;
|
||||||
if(heth->Instance == ETH)
|
if (heth->Instance == ETH) {
|
||||||
{
|
|
||||||
/* Disable DCache for STM32H7 family */
|
/* Disable DCache for STM32H7 family */
|
||||||
SCB_DisableDCache();
|
SCB_DisableDCache();
|
||||||
|
|
||||||
|
|
@ -96,14 +95,14 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||||
HAL_GPIO_Init(RMII_MDC_GPIO_Port, &GPIO_InitStruct);
|
HAL_GPIO_Init(RMII_MDC_GPIO_Port, &GPIO_InitStruct);
|
||||||
|
|
||||||
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
|
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin;
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||||
|
|
||||||
GPIO_InitStruct.Pin = RMII_RXD0_Pin|RMII_RXD1_Pin;
|
GPIO_InitStruct.Pin = RMII_RXD0_Pin | RMII_RXD1_Pin;
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||||
|
|
@ -117,7 +116,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||||
HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
|
HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
|
||||||
|
|
||||||
GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
|
GPIO_InitStruct.Pin = RMII_TX_EN_Pin | RMII_TXD0_Pin;
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||||
|
|
@ -131,8 +130,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
*/
|
*/
|
||||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
|
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
|
||||||
{
|
{
|
||||||
if(heth->Instance == ETH)
|
if (heth->Instance == ETH) {
|
||||||
{
|
|
||||||
/* Disable Peripheral clock */
|
/* Disable Peripheral clock */
|
||||||
__HAL_RCC_ETH1MAC_CLK_DISABLE();
|
__HAL_RCC_ETH1MAC_CLK_DISABLE();
|
||||||
__HAL_RCC_ETH1TX_CLK_DISABLE();
|
__HAL_RCC_ETH1TX_CLK_DISABLE();
|
||||||
|
|
@ -149,13 +147,13 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
|
||||||
PG11 ------> ETH_TX_EN
|
PG11 ------> ETH_TX_EN
|
||||||
PG13 ------> ETH_TXD0
|
PG13 ------> ETH_TXD0
|
||||||
*/
|
*/
|
||||||
HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin);
|
HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin | RMII_RXD0_Pin | RMII_RXD1_Pin);
|
||||||
|
|
||||||
HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin);
|
HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin);
|
||||||
|
|
||||||
HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
|
HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
|
||||||
|
|
||||||
HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin|RMII_TXD0_Pin);
|
HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin | RMII_TXD0_Pin);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -61,8 +61,7 @@
|
||||||
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
{
|
{
|
||||||
GPIO_InitTypeDef GPIO_InitStruct;
|
GPIO_InitTypeDef GPIO_InitStruct;
|
||||||
if(heth->Instance == ETH)
|
if (heth->Instance == ETH) {
|
||||||
{
|
|
||||||
/* Disable DCache for STM32H7 family */
|
/* Disable DCache for STM32H7 family */
|
||||||
SCB_DisableDCache();
|
SCB_DisableDCache();
|
||||||
|
|
||||||
|
|
@ -96,14 +95,14 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||||
HAL_GPIO_Init(RMII_MDC_GPIO_Port, &GPIO_InitStruct);
|
HAL_GPIO_Init(RMII_MDC_GPIO_Port, &GPIO_InitStruct);
|
||||||
|
|
||||||
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
|
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin;
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||||
|
|
||||||
GPIO_InitStruct.Pin = RMII_RXD0_Pin|RMII_RXD1_Pin;
|
GPIO_InitStruct.Pin = RMII_RXD0_Pin | RMII_RXD1_Pin;
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||||
|
|
@ -117,7 +116,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
||||||
HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
|
HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
|
||||||
|
|
||||||
GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
|
GPIO_InitStruct.Pin = RMII_TX_EN_Pin | RMII_TXD0_Pin;
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||||
|
|
@ -131,8 +130,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||||
*/
|
*/
|
||||||
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
|
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
|
||||||
{
|
{
|
||||||
if(heth->Instance == ETH)
|
if (heth->Instance == ETH) {
|
||||||
{
|
|
||||||
/* Disable Peripheral clock */
|
/* Disable Peripheral clock */
|
||||||
__HAL_RCC_ETH1MAC_CLK_DISABLE();
|
__HAL_RCC_ETH1MAC_CLK_DISABLE();
|
||||||
__HAL_RCC_ETH1TX_CLK_DISABLE();
|
__HAL_RCC_ETH1TX_CLK_DISABLE();
|
||||||
|
|
@ -149,13 +147,13 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
|
||||||
PG11 ------> ETH_TX_EN
|
PG11 ------> ETH_TX_EN
|
||||||
PG13 ------> ETH_TXD0
|
PG13 ------> ETH_TXD0
|
||||||
*/
|
*/
|
||||||
HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin);
|
HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin | RMII_RXD0_Pin | RMII_RXD1_Pin);
|
||||||
|
|
||||||
HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin);
|
HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin);
|
||||||
|
|
||||||
HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
|
HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
|
||||||
|
|
||||||
HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin|RMII_TXD0_Pin);
|
HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin | RMII_TXD0_Pin);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
/**
|
/**
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file lan8742.c
|
* @file lan8742.c
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
|
|
@ -34,7 +34,7 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "lan8742.h"
|
#include "lan8742.h"
|
||||||
|
|
@ -45,12 +45,12 @@
|
||||||
|
|
||||||
/** @addtogroup Component
|
/** @addtogroup Component
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup LAN8742 LAN8742
|
/** @defgroup LAN8742 LAN8742
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
/* Private define ------------------------------------------------------------*/
|
/* Private define ------------------------------------------------------------*/
|
||||||
/** @defgroup LAN8742_Private_Defines LAN8742 Private Defines
|
/** @defgroup LAN8742_Private_Defines LAN8742 Private Defines
|
||||||
|
|
@ -62,7 +62,7 @@
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
/* Private macro -------------------------------------------------------------*/
|
||||||
/* Private variables ---------------------------------------------------------*/
|
/* Private variables ---------------------------------------------------------*/
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
@ -70,467 +70,388 @@
|
||||||
/** @defgroup LAN8742_Private_Functions LAN8742 Private Functions
|
/** @defgroup LAN8742_Private_Functions LAN8742 Private Functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Register IO functions to component object
|
* @brief Register IO functions to component object
|
||||||
* @param pObj: device object of LAN8742_Object_t.
|
* @param pObj: device object of LAN8742_Object_t.
|
||||||
* @param ioctx: holds device IO functions.
|
* @param ioctx: holds device IO functions.
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
* LAN8742_STATUS_ERROR if missing mandatory function
|
* LAN8742_STATUS_ERROR if missing mandatory function
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx)
|
int32_t LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx)
|
||||||
{
|
{
|
||||||
if(!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick)
|
if (!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick) {
|
||||||
{
|
return LAN8742_STATUS_ERROR;
|
||||||
return LAN8742_STATUS_ERROR;
|
}
|
||||||
}
|
|
||||||
|
pObj->IO.Init = ioctx->Init;
|
||||||
pObj->IO.Init = ioctx->Init;
|
pObj->IO.DeInit = ioctx->DeInit;
|
||||||
pObj->IO.DeInit = ioctx->DeInit;
|
pObj->IO.ReadReg = ioctx->ReadReg;
|
||||||
pObj->IO.ReadReg = ioctx->ReadReg;
|
pObj->IO.WriteReg = ioctx->WriteReg;
|
||||||
pObj->IO.WriteReg = ioctx->WriteReg;
|
pObj->IO.GetTick = ioctx->GetTick;
|
||||||
pObj->IO.GetTick = ioctx->GetTick;
|
|
||||||
|
return LAN8742_STATUS_OK;
|
||||||
return LAN8742_STATUS_OK;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Initialize the lan8742 and configure the needed hardware resources
|
* @brief Initialize the lan8742 and configure the needed hardware resources
|
||||||
* @param pObj: device object LAN8742_Object_t.
|
* @param pObj: device object LAN8742_Object_t.
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
* LAN8742_STATUS_ADDRESS_ERROR if cannot find device address
|
* LAN8742_STATUS_ADDRESS_ERROR if cannot find device address
|
||||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||||
* LAN8742_STATUS_RESET_TIMEOUT if cannot perform a software reset
|
* LAN8742_STATUS_RESET_TIMEOUT if cannot perform a software reset
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_Init(lan8742_Object_t *pObj)
|
int32_t LAN8742_Init(lan8742_Object_t *pObj)
|
||||||
{
|
{
|
||||||
uint32_t tickstart = 0, regvalue = 0, addr = 0;
|
uint32_t tickstart = 0, regvalue = 0, addr = 0;
|
||||||
int32_t status = LAN8742_STATUS_OK;
|
int32_t status = LAN8742_STATUS_OK;
|
||||||
|
|
||||||
if(pObj->Is_Initialized == 0)
|
if (pObj->Is_Initialized == 0) {
|
||||||
{
|
if (pObj->IO.Init != 0) {
|
||||||
if(pObj->IO.Init != 0)
|
/* GPIO and Clocks initialization */
|
||||||
{
|
pObj->IO.Init();
|
||||||
/* GPIO and Clocks initialization */
|
}
|
||||||
pObj->IO.Init();
|
|
||||||
}
|
/* for later check */
|
||||||
|
pObj->DevAddr = LAN8742_MAX_DEV_ADDR + 1;
|
||||||
/* for later check */
|
|
||||||
pObj->DevAddr = LAN8742_MAX_DEV_ADDR + 1;
|
/* Get the device address from special mode register */
|
||||||
|
for (addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++) {
|
||||||
/* Get the device address from special mode register */
|
if (pObj->IO.ReadReg(addr, LAN8742_SMR, ®value) < 0) {
|
||||||
for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++)
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
{
|
/* Can't read from this device address
|
||||||
if(pObj->IO.ReadReg(addr, LAN8742_SMR, ®value) < 0)
|
continue with next address */
|
||||||
{
|
continue;
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
}
|
||||||
/* Can't read from this device address
|
|
||||||
continue with next address */
|
if ((regvalue & LAN8742_SMR_PHY_ADDR) == addr) {
|
||||||
continue;
|
pObj->DevAddr = addr;
|
||||||
}
|
status = LAN8742_STATUS_OK;
|
||||||
|
break;
|
||||||
if((regvalue & LAN8742_SMR_PHY_ADDR) == addr)
|
}
|
||||||
{
|
}
|
||||||
pObj->DevAddr = addr;
|
|
||||||
status = LAN8742_STATUS_OK;
|
if (pObj->DevAddr > LAN8742_MAX_DEV_ADDR) {
|
||||||
break;
|
status = LAN8742_STATUS_ADDRESS_ERROR;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
|
/* if device address is matched */
|
||||||
if(pObj->DevAddr > LAN8742_MAX_DEV_ADDR)
|
if (status == LAN8742_STATUS_OK) {
|
||||||
{
|
/* set a software reset */
|
||||||
status = LAN8742_STATUS_ADDRESS_ERROR;
|
if (pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, LAN8742_BCR_SOFT_RESET) >= 0) {
|
||||||
}
|
/* get software reset status */
|
||||||
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) >= 0) {
|
||||||
/* if device address is matched */
|
tickstart = pObj->IO.GetTick();
|
||||||
if(status == LAN8742_STATUS_OK)
|
|
||||||
{
|
/* wait until software reset is done or timeout occured */
|
||||||
/* set a software reset */
|
while (regvalue & LAN8742_BCR_SOFT_RESET) {
|
||||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, LAN8742_BCR_SOFT_RESET) >= 0)
|
if ((pObj->IO.GetTick() - tickstart) <= LAN8742_SW_RESET_TO) {
|
||||||
{
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) < 0) {
|
||||||
/* get software reset status */
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) >= 0)
|
break;
|
||||||
{
|
}
|
||||||
tickstart = pObj->IO.GetTick();
|
} else {
|
||||||
|
status = LAN8742_STATUS_RESET_TIMEOUT;
|
||||||
/* wait until software reset is done or timeout occured */
|
}
|
||||||
while(regvalue & LAN8742_BCR_SOFT_RESET)
|
}
|
||||||
{
|
} else {
|
||||||
if((pObj->IO.GetTick() - tickstart) <= LAN8742_SW_RESET_TO)
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
{
|
}
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) < 0)
|
} else {
|
||||||
{
|
status = LAN8742_STATUS_WRITE_ERROR;
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
}
|
||||||
break;
|
}
|
||||||
}
|
}
|
||||||
}
|
|
||||||
else
|
if (status == LAN8742_STATUS_OK) {
|
||||||
{
|
tickstart = pObj->IO.GetTick();
|
||||||
status = LAN8742_STATUS_RESET_TIMEOUT;
|
|
||||||
}
|
/* Wait for 2s to perform initialization */
|
||||||
}
|
while ((pObj->IO.GetTick() - tickstart) <= LAN8742_INIT_TO) {
|
||||||
}
|
}
|
||||||
else
|
pObj->Is_Initialized = 1;
|
||||||
{
|
}
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
return status;
|
||||||
}
|
}
|
||||||
else
|
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_WRITE_ERROR;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if(status == LAN8742_STATUS_OK)
|
|
||||||
{
|
|
||||||
tickstart = pObj->IO.GetTick();
|
|
||||||
|
|
||||||
/* Wait for 2s to perform initialization */
|
|
||||||
while((pObj->IO.GetTick() - tickstart) <= LAN8742_INIT_TO)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
pObj->Is_Initialized = 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief De-Initialize the lan8742 and it's hardware resources
|
* @brief De-Initialize the lan8742 and it's hardware resources
|
||||||
* @param pObj: device object LAN8742_Object_t.
|
* @param pObj: device object LAN8742_Object_t.
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_DeInit(lan8742_Object_t *pObj)
|
int32_t LAN8742_DeInit(lan8742_Object_t *pObj)
|
||||||
{
|
{
|
||||||
if(pObj->Is_Initialized)
|
if (pObj->Is_Initialized) {
|
||||||
{
|
if (pObj->IO.DeInit != 0) {
|
||||||
if(pObj->IO.DeInit != 0)
|
if (pObj->IO.DeInit() < 0) {
|
||||||
{
|
return LAN8742_STATUS_ERROR;
|
||||||
if(pObj->IO.DeInit() < 0)
|
}
|
||||||
{
|
}
|
||||||
return LAN8742_STATUS_ERROR;
|
|
||||||
}
|
pObj->Is_Initialized = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
pObj->Is_Initialized = 0;
|
return LAN8742_STATUS_OK;
|
||||||
}
|
|
||||||
|
|
||||||
return LAN8742_STATUS_OK;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Disable the LAN8742 power down mode.
|
* @brief Disable the LAN8742 power down mode.
|
||||||
* @param pObj: device object LAN8742_Object_t.
|
* @param pObj: device object LAN8742_Object_t.
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_DisablePowerDownMode(lan8742_Object_t *pObj)
|
int32_t LAN8742_DisablePowerDownMode(lan8742_Object_t *pObj)
|
||||||
{
|
{
|
||||||
uint32_t readval = 0;
|
uint32_t readval = 0;
|
||||||
int32_t status = LAN8742_STATUS_OK;
|
int32_t status = LAN8742_STATUS_OK;
|
||||||
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0) {
|
||||||
{
|
readval &= ~LAN8742_BCR_POWER_DOWN;
|
||||||
readval &= ~LAN8742_BCR_POWER_DOWN;
|
|
||||||
|
/* Apply configuration */
|
||||||
/* Apply configuration */
|
if (pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0) {
|
||||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0)
|
status = LAN8742_STATUS_WRITE_ERROR;
|
||||||
{
|
}
|
||||||
status = LAN8742_STATUS_WRITE_ERROR;
|
} else {
|
||||||
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
else
|
return status;
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Enable the LAN8742 power down mode.
|
* @brief Enable the LAN8742 power down mode.
|
||||||
* @param pObj: device object LAN8742_Object_t.
|
* @param pObj: device object LAN8742_Object_t.
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_EnablePowerDownMode(lan8742_Object_t *pObj)
|
int32_t LAN8742_EnablePowerDownMode(lan8742_Object_t *pObj)
|
||||||
{
|
{
|
||||||
uint32_t readval = 0;
|
uint32_t readval = 0;
|
||||||
int32_t status = LAN8742_STATUS_OK;
|
int32_t status = LAN8742_STATUS_OK;
|
||||||
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0) {
|
||||||
{
|
readval |= LAN8742_BCR_POWER_DOWN;
|
||||||
readval |= LAN8742_BCR_POWER_DOWN;
|
|
||||||
|
/* Apply configuration */
|
||||||
/* Apply configuration */
|
if (pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0) {
|
||||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0)
|
status = LAN8742_STATUS_WRITE_ERROR;
|
||||||
{
|
}
|
||||||
status = LAN8742_STATUS_WRITE_ERROR;
|
} else {
|
||||||
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
else
|
return status;
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Start the auto negotiation process.
|
* @brief Start the auto negotiation process.
|
||||||
* @param pObj: device object LAN8742_Object_t.
|
* @param pObj: device object LAN8742_Object_t.
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_StartAutoNego(lan8742_Object_t *pObj)
|
int32_t LAN8742_StartAutoNego(lan8742_Object_t *pObj)
|
||||||
{
|
{
|
||||||
uint32_t readval = 0;
|
uint32_t readval = 0;
|
||||||
int32_t status = LAN8742_STATUS_OK;
|
int32_t status = LAN8742_STATUS_OK;
|
||||||
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0) {
|
||||||
{
|
readval |= LAN8742_BCR_AUTONEGO_EN;
|
||||||
readval |= LAN8742_BCR_AUTONEGO_EN;
|
|
||||||
|
/* Apply configuration */
|
||||||
/* Apply configuration */
|
if (pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0) {
|
||||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0)
|
status = LAN8742_STATUS_WRITE_ERROR;
|
||||||
{
|
}
|
||||||
status = LAN8742_STATUS_WRITE_ERROR;
|
} else {
|
||||||
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
else
|
return status;
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Get the link state of LAN8742 device.
|
* @brief Get the link state of LAN8742 device.
|
||||||
* @param pObj: Pointer to device object.
|
* @param pObj: Pointer to device object.
|
||||||
* @param pLinkState: Pointer to link state
|
* @param pLinkState: Pointer to link state
|
||||||
* @retval LAN8742_STATUS_LINK_DOWN if link is down
|
* @retval LAN8742_STATUS_LINK_DOWN if link is down
|
||||||
* LAN8742_STATUS_AUTONEGO_NOTDONE if Auto nego not completed
|
* LAN8742_STATUS_AUTONEGO_NOTDONE if Auto nego not completed
|
||||||
* LAN8742_STATUS_100MBITS_FULLDUPLEX if 100Mb/s FD
|
* LAN8742_STATUS_100MBITS_FULLDUPLEX if 100Mb/s FD
|
||||||
* LAN8742_STATUS_100MBITS_HALFDUPLEX if 100Mb/s HD
|
* LAN8742_STATUS_100MBITS_HALFDUPLEX if 100Mb/s HD
|
||||||
* LAN8742_STATUS_10MBITS_FULLDUPLEX if 10Mb/s FD
|
* LAN8742_STATUS_10MBITS_FULLDUPLEX if 10Mb/s FD
|
||||||
* LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD
|
* LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD
|
||||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj)
|
int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj)
|
||||||
{
|
{
|
||||||
uint32_t readval = 0;
|
uint32_t readval = 0;
|
||||||
|
|
||||||
/* Read Status register */
|
/* Read Status register */
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0) {
|
||||||
{
|
return LAN8742_STATUS_READ_ERROR;
|
||||||
return LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Read Status register again */
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0)
|
|
||||||
{
|
|
||||||
return LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
if((readval & LAN8742_BSR_LINK_STATUS) == 0)
|
|
||||||
{
|
|
||||||
/* Return Link Down status */
|
|
||||||
return LAN8742_STATUS_LINK_DOWN;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check Auto negotiaition */
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) < 0)
|
|
||||||
{
|
|
||||||
return LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
if((readval & LAN8742_BCR_AUTONEGO_EN) != LAN8742_BCR_AUTONEGO_EN)
|
|
||||||
{
|
|
||||||
if(((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) && ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE))
|
|
||||||
{
|
|
||||||
return LAN8742_STATUS_100MBITS_FULLDUPLEX;
|
|
||||||
}
|
}
|
||||||
else if ((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT)
|
|
||||||
{
|
/* Read Status register again */
|
||||||
return LAN8742_STATUS_100MBITS_HALFDUPLEX;
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0) {
|
||||||
}
|
return LAN8742_STATUS_READ_ERROR;
|
||||||
else if ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)
|
|
||||||
{
|
|
||||||
return LAN8742_STATUS_10MBITS_FULLDUPLEX;
|
|
||||||
}
|
}
|
||||||
else
|
|
||||||
{
|
if ((readval & LAN8742_BSR_LINK_STATUS) == 0) {
|
||||||
return LAN8742_STATUS_10MBITS_HALFDUPLEX;
|
/* Return Link Down status */
|
||||||
}
|
return LAN8742_STATUS_LINK_DOWN;
|
||||||
}
|
|
||||||
else /* Auto Nego enabled */
|
|
||||||
{
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_PHYSCSR, &readval) < 0)
|
|
||||||
{
|
|
||||||
return LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Check if auto nego not done */
|
/* Check Auto negotiaition */
|
||||||
if((readval & LAN8742_PHYSCSR_AUTONEGO_DONE) == 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) < 0) {
|
||||||
{
|
return LAN8742_STATUS_READ_ERROR;
|
||||||
return LAN8742_STATUS_AUTONEGO_NOTDONE;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_FD)
|
if ((readval & LAN8742_BCR_AUTONEGO_EN) != LAN8742_BCR_AUTONEGO_EN) {
|
||||||
{
|
if (((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) && ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)) {
|
||||||
return LAN8742_STATUS_100MBITS_FULLDUPLEX;
|
return LAN8742_STATUS_100MBITS_FULLDUPLEX;
|
||||||
|
} else if ((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) {
|
||||||
|
return LAN8742_STATUS_100MBITS_HALFDUPLEX;
|
||||||
|
} else if ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE) {
|
||||||
|
return LAN8742_STATUS_10MBITS_FULLDUPLEX;
|
||||||
|
} else {
|
||||||
|
return LAN8742_STATUS_10MBITS_HALFDUPLEX;
|
||||||
|
}
|
||||||
|
} else { /* Auto Nego enabled */
|
||||||
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_PHYSCSR, &readval) < 0) {
|
||||||
|
return LAN8742_STATUS_READ_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check if auto nego not done */
|
||||||
|
if ((readval & LAN8742_PHYSCSR_AUTONEGO_DONE) == 0) {
|
||||||
|
return LAN8742_STATUS_AUTONEGO_NOTDONE;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_FD) {
|
||||||
|
return LAN8742_STATUS_100MBITS_FULLDUPLEX;
|
||||||
|
} else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_HD) {
|
||||||
|
return LAN8742_STATUS_100MBITS_HALFDUPLEX;
|
||||||
|
} else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_10BT_FD) {
|
||||||
|
return LAN8742_STATUS_10MBITS_FULLDUPLEX;
|
||||||
|
} else {
|
||||||
|
return LAN8742_STATUS_10MBITS_HALFDUPLEX;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_HD)
|
|
||||||
{
|
|
||||||
return LAN8742_STATUS_100MBITS_HALFDUPLEX;
|
|
||||||
}
|
|
||||||
else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_10BT_FD)
|
|
||||||
{
|
|
||||||
return LAN8742_STATUS_10MBITS_FULLDUPLEX;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
return LAN8742_STATUS_10MBITS_HALFDUPLEX;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Set the link state of LAN8742 device.
|
* @brief Set the link state of LAN8742 device.
|
||||||
* @param pObj: Pointer to device object.
|
* @param pObj: Pointer to device object.
|
||||||
* @param pLinkState: link state can be one of the following
|
* @param pLinkState: link state can be one of the following
|
||||||
* LAN8742_STATUS_100MBITS_FULLDUPLEX if 100Mb/s FD
|
* LAN8742_STATUS_100MBITS_FULLDUPLEX if 100Mb/s FD
|
||||||
* LAN8742_STATUS_100MBITS_HALFDUPLEX if 100Mb/s HD
|
* LAN8742_STATUS_100MBITS_HALFDUPLEX if 100Mb/s HD
|
||||||
* LAN8742_STATUS_10MBITS_FULLDUPLEX if 10Mb/s FD
|
* LAN8742_STATUS_10MBITS_FULLDUPLEX if 10Mb/s FD
|
||||||
* LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD
|
* LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
* LAN8742_STATUS_ERROR if parameter error
|
* LAN8742_STATUS_ERROR if parameter error
|
||||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_SetLinkState(lan8742_Object_t *pObj, uint32_t LinkState)
|
int32_t LAN8742_SetLinkState(lan8742_Object_t *pObj, uint32_t LinkState)
|
||||||
{
|
{
|
||||||
uint32_t bcrvalue = 0;
|
uint32_t bcrvalue = 0;
|
||||||
int32_t status = LAN8742_STATUS_OK;
|
int32_t status = LAN8742_STATUS_OK;
|
||||||
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &bcrvalue) >= 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &bcrvalue) >= 0) {
|
||||||
{
|
/* Disable link config (Auto nego, speed and duplex) */
|
||||||
/* Disable link config (Auto nego, speed and duplex) */
|
bcrvalue &= ~(LAN8742_BCR_AUTONEGO_EN | LAN8742_BCR_SPEED_SELECT | LAN8742_BCR_DUPLEX_MODE);
|
||||||
bcrvalue &= ~(LAN8742_BCR_AUTONEGO_EN | LAN8742_BCR_SPEED_SELECT | LAN8742_BCR_DUPLEX_MODE);
|
|
||||||
|
if (LinkState == LAN8742_STATUS_100MBITS_FULLDUPLEX) {
|
||||||
if(LinkState == LAN8742_STATUS_100MBITS_FULLDUPLEX)
|
bcrvalue |= (LAN8742_BCR_SPEED_SELECT | LAN8742_BCR_DUPLEX_MODE);
|
||||||
{
|
} else if (LinkState == LAN8742_STATUS_100MBITS_HALFDUPLEX) {
|
||||||
bcrvalue |= (LAN8742_BCR_SPEED_SELECT | LAN8742_BCR_DUPLEX_MODE);
|
bcrvalue |= LAN8742_BCR_SPEED_SELECT;
|
||||||
|
} else if (LinkState == LAN8742_STATUS_10MBITS_FULLDUPLEX) {
|
||||||
|
bcrvalue |= LAN8742_BCR_DUPLEX_MODE;
|
||||||
|
} else {
|
||||||
|
/* Wrong link status parameter */
|
||||||
|
status = LAN8742_STATUS_ERROR;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
}
|
}
|
||||||
else if (LinkState == LAN8742_STATUS_100MBITS_HALFDUPLEX)
|
|
||||||
{
|
if (status == LAN8742_STATUS_OK) {
|
||||||
bcrvalue |= LAN8742_BCR_SPEED_SELECT;
|
/* Apply configuration */
|
||||||
|
if (pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, bcrvalue) < 0) {
|
||||||
|
status = LAN8742_STATUS_WRITE_ERROR;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
else if (LinkState == LAN8742_STATUS_10MBITS_FULLDUPLEX)
|
|
||||||
{
|
return status;
|
||||||
bcrvalue |= LAN8742_BCR_DUPLEX_MODE;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* Wrong link status parameter */
|
|
||||||
status = LAN8742_STATUS_ERROR;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
if(status == LAN8742_STATUS_OK)
|
|
||||||
{
|
|
||||||
/* Apply configuration */
|
|
||||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, bcrvalue) < 0)
|
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_WRITE_ERROR;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Enable loopback mode.
|
* @brief Enable loopback mode.
|
||||||
* @param pObj: Pointer to device object.
|
* @param pObj: Pointer to device object.
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_EnableLoopbackMode(lan8742_Object_t *pObj)
|
int32_t LAN8742_EnableLoopbackMode(lan8742_Object_t *pObj)
|
||||||
{
|
{
|
||||||
uint32_t readval = 0;
|
uint32_t readval = 0;
|
||||||
int32_t status = LAN8742_STATUS_OK;
|
int32_t status = LAN8742_STATUS_OK;
|
||||||
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0) {
|
||||||
{
|
readval |= LAN8742_BCR_LOOPBACK;
|
||||||
readval |= LAN8742_BCR_LOOPBACK;
|
|
||||||
|
/* Apply configuration */
|
||||||
/* Apply configuration */
|
if (pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0) {
|
||||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0)
|
status = LAN8742_STATUS_WRITE_ERROR;
|
||||||
{
|
}
|
||||||
status = LAN8742_STATUS_WRITE_ERROR;
|
} else {
|
||||||
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
else
|
return status;
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Disable loopback mode.
|
* @brief Disable loopback mode.
|
||||||
* @param pObj: Pointer to device object.
|
* @param pObj: Pointer to device object.
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||||
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
* LAN8742_STATUS_WRITE_ERROR if connot write to register
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_DisableLoopbackMode(lan8742_Object_t *pObj)
|
int32_t LAN8742_DisableLoopbackMode(lan8742_Object_t *pObj)
|
||||||
{
|
{
|
||||||
uint32_t readval = 0;
|
uint32_t readval = 0;
|
||||||
int32_t status = LAN8742_STATUS_OK;
|
int32_t status = LAN8742_STATUS_OK;
|
||||||
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0) {
|
||||||
{
|
readval &= ~LAN8742_BCR_LOOPBACK;
|
||||||
readval &= ~LAN8742_BCR_LOOPBACK;
|
|
||||||
|
/* Apply configuration */
|
||||||
/* Apply configuration */
|
if (pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0) {
|
||||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0)
|
status = LAN8742_STATUS_WRITE_ERROR;
|
||||||
{
|
}
|
||||||
status = LAN8742_STATUS_WRITE_ERROR;
|
} else {
|
||||||
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
else
|
return status;
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Enable IT source.
|
* @brief Enable IT source.
|
||||||
* @param pObj: Pointer to device object.
|
* @param pObj: Pointer to device object.
|
||||||
* @param Interrupt: IT source to be enabled
|
* @param Interrupt: IT source to be enabled
|
||||||
* should be a value or a combination of the following:
|
* should be a value or a combination of the following:
|
||||||
* LAN8742_WOL_IT
|
* LAN8742_WOL_IT
|
||||||
* LAN8742_ENERGYON_IT
|
* LAN8742_ENERGYON_IT
|
||||||
* LAN8742_AUTONEGO_COMPLETE_IT
|
* LAN8742_AUTONEGO_COMPLETE_IT
|
||||||
* LAN8742_REMOTE_FAULT_IT
|
* LAN8742_REMOTE_FAULT_IT
|
||||||
* LAN8742_LINK_DOWN_IT
|
* LAN8742_LINK_DOWN_IT
|
||||||
* LAN8742_AUTONEGO_LP_ACK_IT
|
* LAN8742_AUTONEGO_LP_ACK_IT
|
||||||
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
||||||
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
|
|
@ -539,38 +460,34 @@ int32_t LAN8742_DisableLoopbackMode(lan8742_Object_t *pObj)
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_EnableIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
int32_t LAN8742_EnableIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
||||||
{
|
{
|
||||||
uint32_t readval = 0;
|
uint32_t readval = 0;
|
||||||
int32_t status = LAN8742_STATUS_OK;
|
int32_t status = LAN8742_STATUS_OK;
|
||||||
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_IMR, &readval) >= 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_IMR, &readval) >= 0) {
|
||||||
{
|
readval |= Interrupt;
|
||||||
readval |= Interrupt;
|
|
||||||
|
/* Apply configuration */
|
||||||
/* Apply configuration */
|
if (pObj->IO.WriteReg(pObj->DevAddr, LAN8742_IMR, readval) < 0) {
|
||||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_IMR, readval) < 0)
|
status = LAN8742_STATUS_WRITE_ERROR;
|
||||||
{
|
}
|
||||||
status = LAN8742_STATUS_WRITE_ERROR;
|
} else {
|
||||||
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
else
|
return status;
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Disable IT source.
|
* @brief Disable IT source.
|
||||||
* @param pObj: Pointer to device object.
|
* @param pObj: Pointer to device object.
|
||||||
* @param Interrupt: IT source to be disabled
|
* @param Interrupt: IT source to be disabled
|
||||||
* should be a value or a combination of the following:
|
* should be a value or a combination of the following:
|
||||||
* LAN8742_WOL_IT
|
* LAN8742_WOL_IT
|
||||||
* LAN8742_ENERGYON_IT
|
* LAN8742_ENERGYON_IT
|
||||||
* LAN8742_AUTONEGO_COMPLETE_IT
|
* LAN8742_AUTONEGO_COMPLETE_IT
|
||||||
* LAN8742_REMOTE_FAULT_IT
|
* LAN8742_REMOTE_FAULT_IT
|
||||||
* LAN8742_LINK_DOWN_IT
|
* LAN8742_LINK_DOWN_IT
|
||||||
* LAN8742_AUTONEGO_LP_ACK_IT
|
* LAN8742_AUTONEGO_LP_ACK_IT
|
||||||
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
||||||
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
|
|
@ -579,38 +496,34 @@ int32_t LAN8742_EnableIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_DisableIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
int32_t LAN8742_DisableIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
||||||
{
|
{
|
||||||
uint32_t readval = 0;
|
uint32_t readval = 0;
|
||||||
int32_t status = LAN8742_STATUS_OK;
|
int32_t status = LAN8742_STATUS_OK;
|
||||||
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_IMR, &readval) >= 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_IMR, &readval) >= 0) {
|
||||||
{
|
readval &= ~Interrupt;
|
||||||
readval &= ~Interrupt;
|
|
||||||
|
/* Apply configuration */
|
||||||
/* Apply configuration */
|
if (pObj->IO.WriteReg(pObj->DevAddr, LAN8742_IMR, readval) < 0) {
|
||||||
if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_IMR, readval) < 0)
|
status = LAN8742_STATUS_WRITE_ERROR;
|
||||||
{
|
}
|
||||||
status = LAN8742_STATUS_WRITE_ERROR;
|
} else {
|
||||||
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
else
|
return status;
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Clear IT flag.
|
* @brief Clear IT flag.
|
||||||
* @param pObj: Pointer to device object.
|
* @param pObj: Pointer to device object.
|
||||||
* @param Interrupt: IT flag to be cleared
|
* @param Interrupt: IT flag to be cleared
|
||||||
* should be a value or a combination of the following:
|
* should be a value or a combination of the following:
|
||||||
* LAN8742_WOL_IT
|
* LAN8742_WOL_IT
|
||||||
* LAN8742_ENERGYON_IT
|
* LAN8742_ENERGYON_IT
|
||||||
* LAN8742_AUTONEGO_COMPLETE_IT
|
* LAN8742_AUTONEGO_COMPLETE_IT
|
||||||
* LAN8742_REMOTE_FAULT_IT
|
* LAN8742_REMOTE_FAULT_IT
|
||||||
* LAN8742_LINK_DOWN_IT
|
* LAN8742_LINK_DOWN_IT
|
||||||
* LAN8742_AUTONEGO_LP_ACK_IT
|
* LAN8742_AUTONEGO_LP_ACK_IT
|
||||||
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
||||||
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
||||||
* @retval LAN8742_STATUS_OK if OK
|
* @retval LAN8742_STATUS_OK if OK
|
||||||
|
|
@ -618,64 +531,60 @@ int32_t LAN8742_DisableIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_ClearIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
int32_t LAN8742_ClearIT(lan8742_Object_t *pObj, uint32_t Interrupt)
|
||||||
{
|
{
|
||||||
uint32_t readval = 0;
|
uint32_t readval = 0;
|
||||||
int32_t status = LAN8742_STATUS_OK;
|
int32_t status = LAN8742_STATUS_OK;
|
||||||
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_ISFR, &readval) < 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_ISFR, &readval) < 0) {
|
||||||
{
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
}
|
||||||
}
|
|
||||||
|
return status;
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Get IT Flag status.
|
* @brief Get IT Flag status.
|
||||||
* @param pObj: Pointer to device object.
|
* @param pObj: Pointer to device object.
|
||||||
* @param Interrupt: IT Flag to be checked,
|
* @param Interrupt: IT Flag to be checked,
|
||||||
* should be a value or a combination of the following:
|
* should be a value or a combination of the following:
|
||||||
* LAN8742_WOL_IT
|
* LAN8742_WOL_IT
|
||||||
* LAN8742_ENERGYON_IT
|
* LAN8742_ENERGYON_IT
|
||||||
* LAN8742_AUTONEGO_COMPLETE_IT
|
* LAN8742_AUTONEGO_COMPLETE_IT
|
||||||
* LAN8742_REMOTE_FAULT_IT
|
* LAN8742_REMOTE_FAULT_IT
|
||||||
* LAN8742_LINK_DOWN_IT
|
* LAN8742_LINK_DOWN_IT
|
||||||
* LAN8742_AUTONEGO_LP_ACK_IT
|
* LAN8742_AUTONEGO_LP_ACK_IT
|
||||||
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
* LAN8742_PARALLEL_DETECTION_FAULT_IT
|
||||||
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
* LAN8742_AUTONEGO_PAGE_RECEIVED_IT
|
||||||
* @retval 1 IT flag is SET
|
* @retval 1 IT flag is SET
|
||||||
* 0 IT flag is RESET
|
* 0 IT flag is RESET
|
||||||
* LAN8742_STATUS_READ_ERROR if connot read register
|
* LAN8742_STATUS_READ_ERROR if connot read register
|
||||||
*/
|
*/
|
||||||
int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt)
|
int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt)
|
||||||
{
|
{
|
||||||
uint32_t readval = 0;
|
uint32_t readval = 0;
|
||||||
int32_t status = 0;
|
int32_t status = 0;
|
||||||
|
|
||||||
if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_ISFR, &readval) >= 0)
|
if (pObj->IO.ReadReg(pObj->DevAddr, LAN8742_ISFR, &readval) >= 0) {
|
||||||
{
|
status = ((readval & Interrupt) == Interrupt);
|
||||||
status = ((readval & Interrupt) == Interrupt);
|
} else {
|
||||||
}
|
status = LAN8742_STATUS_READ_ERROR;
|
||||||
else
|
}
|
||||||
{
|
|
||||||
status = LAN8742_STATUS_READ_ERROR;
|
return status;
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
||||||
|
|
@ -34,38 +34,38 @@
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __LAN8742_H
|
#ifndef __LAN8742_H
|
||||||
#define __LAN8742_H
|
#define __LAN8742_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
/** @addtogroup BSP
|
/** @addtogroup BSP
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup Component
|
/** @addtogroup Component
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup LAN8742
|
/** @defgroup LAN8742
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* Exported constants --------------------------------------------------------*/
|
/* Exported constants --------------------------------------------------------*/
|
||||||
/** @defgroup LAN8742_Exported_Constants LAN8742 Exported Constants
|
/** @defgroup LAN8742_Exported_Constants LAN8742 Exported Constants
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup LAN8742_Registers_Mapping LAN8742 Registers Mapping
|
/** @defgroup LAN8742_Registers_Mapping LAN8742 Registers Mapping
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LAN8742_BCR ((uint16_t)0x0000U)
|
#define LAN8742_BCR ((uint16_t)0x0000U)
|
||||||
#define LAN8742_BSR ((uint16_t)0x0001U)
|
#define LAN8742_BSR ((uint16_t)0x0001U)
|
||||||
#define LAN8742_PHYI1R ((uint16_t)0x0002U)
|
#define LAN8742_PHYI1R ((uint16_t)0x0002U)
|
||||||
|
|
@ -94,7 +94,7 @@
|
||||||
|
|
||||||
/** @defgroup LAN8742_BCR_Bit_Definition LAN8742 BCR Bit Definition
|
/** @defgroup LAN8742_BCR_Bit_Definition LAN8742 BCR Bit Definition
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LAN8742_BCR_SOFT_RESET ((uint16_t)0x8000U)
|
#define LAN8742_BCR_SOFT_RESET ((uint16_t)0x8000U)
|
||||||
#define LAN8742_BCR_LOOPBACK ((uint16_t)0x4000U)
|
#define LAN8742_BCR_LOOPBACK ((uint16_t)0x4000U)
|
||||||
#define LAN8742_BCR_SPEED_SELECT ((uint16_t)0x2000U)
|
#define LAN8742_BCR_SPEED_SELECT ((uint16_t)0x2000U)
|
||||||
|
|
@ -102,14 +102,14 @@
|
||||||
#define LAN8742_BCR_POWER_DOWN ((uint16_t)0x0800U)
|
#define LAN8742_BCR_POWER_DOWN ((uint16_t)0x0800U)
|
||||||
#define LAN8742_BCR_ISOLATE ((uint16_t)0x0400U)
|
#define LAN8742_BCR_ISOLATE ((uint16_t)0x0400U)
|
||||||
#define LAN8742_BCR_RESTART_AUTONEGO ((uint16_t)0x0200U)
|
#define LAN8742_BCR_RESTART_AUTONEGO ((uint16_t)0x0200U)
|
||||||
#define LAN8742_BCR_DUPLEX_MODE ((uint16_t)0x0100U)
|
#define LAN8742_BCR_DUPLEX_MODE ((uint16_t)0x0100U)
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup LAN8742_BSR_Bit_Definition LAN8742 BSR Bit Definition
|
/** @defgroup LAN8742_BSR_Bit_Definition LAN8742 BSR Bit Definition
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LAN8742_BSR_100BASE_T4 ((uint16_t)0x8000U)
|
#define LAN8742_BSR_100BASE_T4 ((uint16_t)0x8000U)
|
||||||
#define LAN8742_BSR_100BASE_TX_FD ((uint16_t)0x4000U)
|
#define LAN8742_BSR_100BASE_TX_FD ((uint16_t)0x4000U)
|
||||||
#define LAN8742_BSR_100BASE_TX_HD ((uint16_t)0x2000U)
|
#define LAN8742_BSR_100BASE_TX_HD ((uint16_t)0x2000U)
|
||||||
|
|
@ -226,7 +226,7 @@
|
||||||
/** @defgroup LAN8742_MMDACR_Bit_Definition LAN8742 MMDACR Bit Definition
|
/** @defgroup LAN8742_MMDACR_Bit_Definition LAN8742 MMDACR Bit Definition
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LAN8742_MMDACR_MMD_FUNCTION ((uint16_t)0xC000U)
|
#define LAN8742_MMDACR_MMD_FUNCTION ((uint16_t)0xC000U)
|
||||||
#define LAN8742_MMDACR_MMD_FUNCTION_ADDR ((uint16_t)0x0000U)
|
#define LAN8742_MMDACR_MMD_FUNCTION_ADDR ((uint16_t)0x0000U)
|
||||||
#define LAN8742_MMDACR_MMD_FUNCTION_DATA ((uint16_t)0x4000U)
|
#define LAN8742_MMDACR_MMD_FUNCTION_DATA ((uint16_t)0x4000U)
|
||||||
#define LAN8742_MMDACR_MMD_DEV_ADDR ((uint16_t)0x001FU)
|
#define LAN8742_MMDACR_MMD_DEV_ADDR ((uint16_t)0x001FU)
|
||||||
|
|
@ -344,14 +344,14 @@
|
||||||
#define LAN8742_PHYSCSR_10BT_HD ((uint16_t)0x0004U)
|
#define LAN8742_PHYSCSR_10BT_HD ((uint16_t)0x0004U)
|
||||||
#define LAN8742_PHYSCSR_10BT_FD ((uint16_t)0x0014U)
|
#define LAN8742_PHYSCSR_10BT_FD ((uint16_t)0x0014U)
|
||||||
#define LAN8742_PHYSCSR_100BTX_HD ((uint16_t)0x0008U)
|
#define LAN8742_PHYSCSR_100BTX_HD ((uint16_t)0x0008U)
|
||||||
#define LAN8742_PHYSCSR_100BTX_FD ((uint16_t)0x0018U)
|
#define LAN8742_PHYSCSR_100BTX_FD ((uint16_t)0x0018U)
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup LAN8742_Status LAN8742 Status
|
/** @defgroup LAN8742_Status LAN8742 Status
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define LAN8742_STATUS_READ_ERROR ((int32_t)-5)
|
#define LAN8742_STATUS_READ_ERROR ((int32_t)-5)
|
||||||
#define LAN8742_STATUS_WRITE_ERROR ((int32_t)-4)
|
#define LAN8742_STATUS_WRITE_ERROR ((int32_t)-4)
|
||||||
|
|
@ -371,7 +371,7 @@
|
||||||
|
|
||||||
/** @defgroup LAN8742_IT_Flags LAN8742 IT Flags
|
/** @defgroup LAN8742_IT_Flags LAN8742 IT Flags
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LAN8742_WOL_IT LAN8742_INT_8
|
#define LAN8742_WOL_IT LAN8742_INT_8
|
||||||
#define LAN8742_ENERGYON_IT LAN8742_INT_7
|
#define LAN8742_ENERGYON_IT LAN8742_INT_7
|
||||||
#define LAN8742_AUTONEGO_COMPLETE_IT LAN8742_INT_6
|
#define LAN8742_AUTONEGO_COMPLETE_IT LAN8742_INT_6
|
||||||
|
|
@ -388,36 +388,34 @@
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
/* Exported types ------------------------------------------------------------*/
|
||||||
/** @defgroup LAN8742_Exported_Types LAN8742 Exported Types
|
/** @defgroup LAN8742_Exported_Types LAN8742 Exported Types
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
typedef int32_t (*lan8742_Init_Func) (void);
|
typedef int32_t (*lan8742_Init_Func)(void);
|
||||||
typedef int32_t (*lan8742_DeInit_Func) (void);
|
typedef int32_t (*lan8742_DeInit_Func)(void);
|
||||||
typedef int32_t (*lan8742_ReadReg_Func) (uint32_t, uint32_t, uint32_t *);
|
typedef int32_t (*lan8742_ReadReg_Func)(uint32_t, uint32_t, uint32_t *);
|
||||||
typedef int32_t (*lan8742_WriteReg_Func) (uint32_t, uint32_t, uint32_t);
|
typedef int32_t (*lan8742_WriteReg_Func)(uint32_t, uint32_t, uint32_t);
|
||||||
typedef int32_t (*lan8742_GetTick_Func) (void);
|
typedef int32_t (*lan8742_GetTick_Func)(void);
|
||||||
|
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
lan8742_Init_Func Init;
|
||||||
lan8742_Init_Func Init;
|
lan8742_DeInit_Func DeInit;
|
||||||
lan8742_DeInit_Func DeInit;
|
lan8742_WriteReg_Func WriteReg;
|
||||||
lan8742_WriteReg_Func WriteReg;
|
lan8742_ReadReg_Func ReadReg;
|
||||||
lan8742_ReadReg_Func ReadReg;
|
lan8742_GetTick_Func GetTick;
|
||||||
lan8742_GetTick_Func GetTick;
|
} lan8742_IOCtx_t;
|
||||||
} lan8742_IOCtx_t;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
uint32_t DevAddr;
|
||||||
uint32_t DevAddr;
|
uint32_t Is_Initialized;
|
||||||
uint32_t Is_Initialized;
|
lan8742_IOCtx_t IO;
|
||||||
lan8742_IOCtx_t IO;
|
void *pData;
|
||||||
void *pData;
|
} lan8742_Object_t;
|
||||||
}lan8742_Object_t;
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
/* Exported functions --------------------------------------------------------*/
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
@ -440,7 +438,7 @@ int32_t LAN8742_ClearIT(lan8742_Object_t *pObj, uint32_t Interrupt);
|
||||||
int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt);
|
int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
|
@ -450,7 +448,7 @@ int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
|
@ -458,9 +456,9 @@ int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
||||||
|
|
@ -104,8 +104,7 @@ static int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *
|
||||||
static int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal);
|
static int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal);
|
||||||
static int32_t ETH_PHY_IO_GetTick(void);
|
static int32_t ETH_PHY_IO_GetTick(void);
|
||||||
|
|
||||||
static lan8742_IOCtx_t LAN8742_IOCtx =
|
static lan8742_IOCtx_t LAN8742_IOCtx = {
|
||||||
{
|
|
||||||
ETH_PHY_IO_Init,
|
ETH_PHY_IO_Init,
|
||||||
ETH_PHY_IO_DeInit,
|
ETH_PHY_IO_DeInit,
|
||||||
ETH_PHY_IO_WriteReg,
|
ETH_PHY_IO_WriteReg,
|
||||||
|
|
@ -149,26 +148,25 @@ int32_t _phy_get_state()
|
||||||
|
|
||||||
bool _phy_get_duplex_and_speed(int32_t phy_state, uint32_t *duplex, uint32_t *speed)
|
bool _phy_get_duplex_and_speed(int32_t phy_state, uint32_t *duplex, uint32_t *speed)
|
||||||
{
|
{
|
||||||
switch (phy_state)
|
switch (phy_state) {
|
||||||
{
|
case LAN8742_STATUS_100MBITS_FULLDUPLEX:
|
||||||
case LAN8742_STATUS_100MBITS_FULLDUPLEX:
|
*duplex = ETH_FULLDUPLEX_MODE;
|
||||||
*duplex = ETH_FULLDUPLEX_MODE;
|
*speed = ETH_SPEED_100M;
|
||||||
*speed = ETH_SPEED_100M;
|
break;
|
||||||
break;
|
case LAN8742_STATUS_100MBITS_HALFDUPLEX:
|
||||||
case LAN8742_STATUS_100MBITS_HALFDUPLEX:
|
*duplex = ETH_HALFDUPLEX_MODE;
|
||||||
*duplex = ETH_HALFDUPLEX_MODE;
|
*speed = ETH_SPEED_100M;
|
||||||
*speed = ETH_SPEED_100M;
|
break;
|
||||||
break;
|
case LAN8742_STATUS_10MBITS_FULLDUPLEX:
|
||||||
case LAN8742_STATUS_10MBITS_FULLDUPLEX:
|
*duplex = ETH_FULLDUPLEX_MODE;
|
||||||
*duplex = ETH_FULLDUPLEX_MODE;
|
*speed = ETH_SPEED_10M;
|
||||||
*speed = ETH_SPEED_10M;
|
break;
|
||||||
break;
|
case LAN8742_STATUS_10MBITS_HALFDUPLEX:
|
||||||
case LAN8742_STATUS_10MBITS_HALFDUPLEX:
|
*duplex = ETH_HALFDUPLEX_MODE;
|
||||||
*duplex = ETH_HALFDUPLEX_MODE;
|
*speed = ETH_SPEED_10M;
|
||||||
*speed = ETH_SPEED_10M;
|
break;
|
||||||
break;
|
default:
|
||||||
default:
|
return false;
|
||||||
return false;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
|
|
@ -181,45 +179,45 @@ bool _phy_is_up(int32_t phy_state)
|
||||||
|
|
||||||
static void MPU_Config(void)
|
static void MPU_Config(void)
|
||||||
{
|
{
|
||||||
MPU_Region_InitTypeDef MPU_InitStruct;
|
MPU_Region_InitTypeDef MPU_InitStruct;
|
||||||
|
|
||||||
/* Disable the MPU */
|
|
||||||
HAL_MPU_Disable();
|
|
||||||
|
|
||||||
/* Configure the MPU attributes as Device not cacheable
|
/* Disable the MPU */
|
||||||
for ETH DMA descriptors */
|
HAL_MPU_Disable();
|
||||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
|
||||||
MPU_InitStruct.BaseAddress = 0x30040000;
|
|
||||||
MPU_InitStruct.Size = MPU_REGION_SIZE_1KB;
|
|
||||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
|
||||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
|
|
||||||
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
|
|
||||||
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
|
|
||||||
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
|
|
||||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
|
||||||
MPU_InitStruct.SubRegionDisable = 0x00;
|
|
||||||
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
|
|
||||||
|
|
||||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
/* Configure the MPU attributes as Device not cacheable
|
||||||
|
for ETH DMA descriptors */
|
||||||
/* Configure the MPU attributes as Cacheable write through
|
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||||
for LwIP RAM heap which contains the Tx buffers */
|
MPU_InitStruct.BaseAddress = 0x30040000;
|
||||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
MPU_InitStruct.Size = MPU_REGION_SIZE_1KB;
|
||||||
MPU_InitStruct.BaseAddress = 0x30044000;
|
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||||
MPU_InitStruct.Size = MPU_REGION_SIZE_16KB;
|
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
|
||||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
|
||||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
|
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
|
||||||
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
|
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
|
||||||
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
|
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
||||||
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
|
MPU_InitStruct.SubRegionDisable = 0x00;
|
||||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
|
||||||
MPU_InitStruct.SubRegionDisable = 0x00;
|
|
||||||
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
|
|
||||||
|
|
||||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||||
|
|
||||||
/* Enable the MPU */
|
/* Configure the MPU attributes as Cacheable write through
|
||||||
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
|
for LwIP RAM heap which contains the Tx buffers */
|
||||||
|
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||||
|
MPU_InitStruct.BaseAddress = 0x30044000;
|
||||||
|
MPU_InitStruct.Size = MPU_REGION_SIZE_16KB;
|
||||||
|
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||||
|
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
|
||||||
|
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
|
||||||
|
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
|
||||||
|
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
|
||||||
|
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
||||||
|
MPU_InitStruct.SubRegionDisable = 0x00;
|
||||||
|
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
|
||||||
|
|
||||||
|
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||||
|
|
||||||
|
/* Enable the MPU */
|
||||||
|
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -254,7 +252,7 @@ void ETH_IRQHandler(void)
|
||||||
|
|
||||||
STM32_EMAC::STM32_EMAC()
|
STM32_EMAC::STM32_EMAC()
|
||||||
: thread(0)
|
: thread(0)
|
||||||
#ifdef ETH_IP_VERSION_V2
|
#ifdef ETH_IP_VERSION_V2
|
||||||
, phy_status(0)
|
, phy_status(0)
|
||||||
#endif
|
#endif
|
||||||
{
|
{
|
||||||
|
|
@ -340,8 +338,7 @@ bool STM32_EMAC::low_level_init_successful()
|
||||||
EthHandle.Init.TxDesc = DMATxDscrTab;
|
EthHandle.Init.TxDesc = DMATxDscrTab;
|
||||||
EthHandle.Init.RxBuffLen = 1524;
|
EthHandle.Init.RxBuffLen = 1524;
|
||||||
|
|
||||||
if (HAL_ETH_Init(&EthHandle) != HAL_OK)
|
if (HAL_ETH_Init(&EthHandle) != HAL_OK) {
|
||||||
{
|
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -350,8 +347,7 @@ bool STM32_EMAC::low_level_init_successful()
|
||||||
TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
|
TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
|
||||||
TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
|
TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
|
||||||
|
|
||||||
for(idx = 0; idx < ETH_RX_DESC_CNT; idx++)
|
for (idx = 0; idx < ETH_RX_DESC_CNT; idx++) {
|
||||||
{
|
|
||||||
HAL_ETH_DescAssignMemory(&EthHandle, idx, Rx_Buff[idx], NULL);
|
HAL_ETH_DescAssignMemory(&EthHandle, idx, Rx_Buff[idx], NULL);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -464,7 +460,7 @@ error:
|
||||||
/* Get exclusive access */
|
/* Get exclusive access */
|
||||||
TXLockMutex.lock();
|
TXLockMutex.lock();
|
||||||
|
|
||||||
memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef));
|
memset(Txbuffer, 0, ETH_TX_DESC_CNT * sizeof(ETH_BufferTypeDef));
|
||||||
|
|
||||||
/* copy frame from pbufs to driver buffers */
|
/* copy frame from pbufs to driver buffers */
|
||||||
for (q = p; q != NULL; q = q->next) {
|
for (q = p; q != NULL; q = q->next) {
|
||||||
|
|
@ -477,13 +473,11 @@ error:
|
||||||
Txbuffer[i].len = q->len;
|
Txbuffer[i].len = q->len;
|
||||||
frameLength += q->len;
|
frameLength += q->len;
|
||||||
|
|
||||||
if (i > 0)
|
if (i > 0) {
|
||||||
{
|
|
||||||
Txbuffer[i - 1].next = &Txbuffer[i];
|
Txbuffer[i - 1].next = &Txbuffer[i];
|
||||||
}
|
}
|
||||||
|
|
||||||
if (q->next == NULL)
|
if (q->next == NULL) {
|
||||||
{
|
|
||||||
Txbuffer[i].next = NULL;
|
Txbuffer[i].next = NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -494,7 +488,7 @@ error:
|
||||||
TxConfig.TxBuffer = Txbuffer;
|
TxConfig.TxBuffer = Txbuffer;
|
||||||
|
|
||||||
status = HAL_ETH_Transmit(&EthHandle, &TxConfig, 50);
|
status = HAL_ETH_Transmit(&EthHandle, &TxConfig, 50);
|
||||||
if(status == HAL_OK){
|
if (status == HAL_OK) {
|
||||||
success = 1;
|
success = 1;
|
||||||
} else {
|
} else {
|
||||||
printf("Error returned by HAL_ETH_Transmit (%d)\n", status);
|
printf("Error returned by HAL_ETH_Transmit (%d)\n", status);
|
||||||
|
|
@ -504,7 +498,7 @@ error:
|
||||||
error:
|
error:
|
||||||
|
|
||||||
if (p->ref > 1) {
|
if (p->ref > 1) {
|
||||||
pbuf_free(p);
|
pbuf_free(p);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Restore access */
|
/* Restore access */
|
||||||
|
|
@ -603,10 +597,8 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf)
|
||||||
ETH_BufferTypeDef RxBuff;
|
ETH_BufferTypeDef RxBuff;
|
||||||
uint32_t frameLength = 0;
|
uint32_t frameLength = 0;
|
||||||
|
|
||||||
if (HAL_ETH_GetRxDataBuffer(&EthHandle, &RxBuff) == HAL_OK)
|
if (HAL_ETH_GetRxDataBuffer(&EthHandle, &RxBuff) == HAL_OK) {
|
||||||
{
|
if (HAL_ETH_GetRxDataLength(&EthHandle, &frameLength) != HAL_OK) {
|
||||||
if (HAL_ETH_GetRxDataLength(&EthHandle, &frameLength) != HAL_OK)
|
|
||||||
{
|
|
||||||
printf("Error: returned by HAL_ETH_GetRxDataLength\n");
|
printf("Error: returned by HAL_ETH_GetRxDataLength\n");
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
@ -618,13 +610,10 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf)
|
||||||
SCB_InvalidateDCache_by_Addr((uint32_t *)RxBuff.buffer, frameLength);
|
SCB_InvalidateDCache_by_Addr((uint32_t *)RxBuff.buffer, frameLength);
|
||||||
|
|
||||||
*buf = pbuf_alloc(PBUF_RAW, frameLength, PBUF_POOL);
|
*buf = pbuf_alloc(PBUF_RAW, frameLength, PBUF_POOL);
|
||||||
if (*buf)
|
if (*buf) {
|
||||||
{
|
|
||||||
pbuf_take((struct pbuf *)*buf, RxBuff.buffer, frameLength);
|
pbuf_take((struct pbuf *)*buf, RxBuff.buffer, frameLength);
|
||||||
}
|
}
|
||||||
}
|
} else {
|
||||||
else
|
|
||||||
{
|
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -698,27 +687,23 @@ void STM32_EMAC::phy_task()
|
||||||
const bool is_up = _phy_is_up(status);
|
const bool is_up = _phy_is_up(status);
|
||||||
const bool was_up = _phy_is_up(old_status);
|
const bool was_up = _phy_is_up(old_status);
|
||||||
|
|
||||||
if (is_up && !was_up)
|
if (is_up && !was_up) {
|
||||||
{
|
|
||||||
uint32_t duplex, speed;
|
uint32_t duplex, speed;
|
||||||
ETH_MACConfigTypeDef MACConf;
|
ETH_MACConfigTypeDef MACConf;
|
||||||
|
|
||||||
if (!_phy_get_duplex_and_speed(status, &speed, &duplex))
|
if (!_phy_get_duplex_and_speed(status, &speed, &duplex)) {
|
||||||
{
|
|
||||||
// Default
|
// Default
|
||||||
duplex = ETH_FULLDUPLEX_MODE;
|
duplex = ETH_FULLDUPLEX_MODE;
|
||||||
speed = ETH_SPEED_10M;
|
speed = ETH_SPEED_10M;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Get MAC Config MAC */
|
/* Get MAC Config MAC */
|
||||||
HAL_ETH_GetMACConfig(&EthHandle, &MACConf);
|
HAL_ETH_GetMACConfig(&EthHandle, &MACConf);
|
||||||
MACConf.DuplexMode = duplex;
|
MACConf.DuplexMode = duplex;
|
||||||
MACConf.Speed = speed;
|
MACConf.Speed = speed;
|
||||||
HAL_ETH_SetMACConfig(&EthHandle, &MACConf);
|
HAL_ETH_SetMACConfig(&EthHandle, &MACConf);
|
||||||
HAL_ETH_Start_IT(&EthHandle);
|
HAL_ETH_Start_IT(&EthHandle);
|
||||||
}
|
} else if (was_up && !is_up) {
|
||||||
else if (was_up && !is_up)
|
|
||||||
{
|
|
||||||
// Stop ETH
|
// Stop ETH
|
||||||
disable_interrupts();
|
disable_interrupts();
|
||||||
HAL_ETH_Stop(&EthHandle);
|
HAL_ETH_Stop(&EthHandle);
|
||||||
|
|
@ -951,9 +936,9 @@ MBED_WEAK EMAC &EMAC::get_default_instance()
|
||||||
* @retval 0 if OK, -1 if ERROR
|
* @retval 0 if OK, -1 if ERROR
|
||||||
*/
|
*/
|
||||||
static int32_t ETH_PHY_IO_Init(void)
|
static int32_t ETH_PHY_IO_Init(void)
|
||||||
{
|
{
|
||||||
/* We assume that MDIO GPIO configuration is already done
|
/* We assume that MDIO GPIO configuration is already done
|
||||||
in the ETH_MspInit() else it should be done here
|
in the ETH_MspInit() else it should be done here
|
||||||
*/
|
*/
|
||||||
STM32_EMAC &emac = STM32_EMAC::get_instance();
|
STM32_EMAC &emac = STM32_EMAC::get_instance();
|
||||||
|
|
||||||
|
|
@ -968,23 +953,22 @@ static int32_t ETH_PHY_IO_Init(void)
|
||||||
* @param None
|
* @param None
|
||||||
* @retval 0 if OK, -1 if ERROR
|
* @retval 0 if OK, -1 if ERROR
|
||||||
*/
|
*/
|
||||||
static int32_t ETH_PHY_IO_DeInit (void)
|
static int32_t ETH_PHY_IO_DeInit(void)
|
||||||
{
|
{
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Read a PHY register through the MDIO interface.
|
* @brief Read a PHY register through the MDIO interface.
|
||||||
* @param DevAddr: PHY port address
|
* @param DevAddr: PHY port address
|
||||||
* @param RegAddr: PHY register address
|
* @param RegAddr: PHY register address
|
||||||
* @param pRegVal: pointer to hold the register value
|
* @param pRegVal: pointer to hold the register value
|
||||||
* @retval 0 if OK -1 if Error
|
* @retval 0 if OK -1 if Error
|
||||||
*/
|
*/
|
||||||
static int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal)
|
static int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal)
|
||||||
{
|
{
|
||||||
STM32_EMAC &emac = STM32_EMAC::get_instance();
|
STM32_EMAC &emac = STM32_EMAC::get_instance();
|
||||||
if(HAL_ETH_ReadPHYRegister(&emac.EthHandle, DevAddr, RegAddr, pRegVal) != HAL_OK)
|
if (HAL_ETH_ReadPHYRegister(&emac.EthHandle, DevAddr, RegAddr, pRegVal) != HAL_OK) {
|
||||||
{
|
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -995,14 +979,13 @@ static int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *
|
||||||
* @brief Write a value to a PHY register through the MDIO interface.
|
* @brief Write a value to a PHY register through the MDIO interface.
|
||||||
* @param DevAddr: PHY port address
|
* @param DevAddr: PHY port address
|
||||||
* @param RegAddr: PHY register address
|
* @param RegAddr: PHY register address
|
||||||
* @param RegVal: Value to be written
|
* @param RegVal: Value to be written
|
||||||
* @retval 0 if OK -1 if Error
|
* @retval 0 if OK -1 if Error
|
||||||
*/
|
*/
|
||||||
static int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal)
|
static int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal)
|
||||||
{
|
{
|
||||||
STM32_EMAC &emac = STM32_EMAC::get_instance();
|
STM32_EMAC &emac = STM32_EMAC::get_instance();
|
||||||
if(HAL_ETH_WritePHYRegister(&emac.EthHandle, DevAddr, RegAddr, RegVal) != HAL_OK)
|
if (HAL_ETH_WritePHYRegister(&emac.EthHandle, DevAddr, RegAddr, RegVal) != HAL_OK) {
|
||||||
{
|
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -1015,7 +998,7 @@ static int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t
|
||||||
*/
|
*/
|
||||||
static int32_t ETH_PHY_IO_GetTick(void)
|
static int32_t ETH_PHY_IO_GetTick(void)
|
||||||
{
|
{
|
||||||
return HAL_GetTick();
|
return HAL_GetTick();
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -1023,7 +1006,7 @@ static int32_t ETH_PHY_IO_GetTick(void)
|
||||||
*/
|
*/
|
||||||
void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
|
void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
|
||||||
{
|
{
|
||||||
MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_ETHERNET, EIO), \
|
MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_ETHERNET, EIO), \
|
||||||
"Error from ethernet HAL (HAL_ETH_DMAErrorCallback)\n");
|
"Error from ethernet HAL (HAL_ETH_DMAErrorCallback)\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -1032,7 +1015,7 @@ void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
|
||||||
*/
|
*/
|
||||||
void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
|
void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
|
||||||
{
|
{
|
||||||
MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_ETHERNET, EIO), \
|
MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_ETHERNET, EIO), \
|
||||||
"Error from ethernet HAL (HAL_ETH_MACErrorCallback)\n");
|
"Error from ethernet HAL (HAL_ETH_MACErrorCallback)\n");
|
||||||
}
|
}
|
||||||
#endif // ETH_IP_VERSION_V2
|
#endif // ETH_IP_VERSION_V2
|
||||||
|
|
|
||||||
|
|
@ -254,7 +254,7 @@ void serial_clear(serial_t *obj)
|
||||||
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
|
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
|
||||||
|
|
||||||
/* Clear RXNE and error flags */
|
/* Clear RXNE and error flags */
|
||||||
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR;
|
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR;
|
||||||
HAL_UART_ErrorCallback(huart);
|
HAL_UART_ErrorCallback(huart);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -4,7 +4,7 @@
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* modification, are permitted provided that the following conditions are met:
|
* modification, are permitted provided that the following conditions are met:
|
||||||
*
|
*
|
||||||
|
|
|
||||||
|
|
@ -4,7 +4,7 @@
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* modification, are permitted provided that the following conditions are met:
|
* modification, are permitted provided that the following conditions are met:
|
||||||
*
|
*
|
||||||
|
|
|
||||||
|
|
@ -4,7 +4,7 @@
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* modification, are permitted provided that the following conditions are met:
|
* modification, are permitted provided that the following conditions are met:
|
||||||
*
|
*
|
||||||
|
|
|
||||||
|
|
@ -4,7 +4,7 @@
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* modification, are permitted provided that the following conditions are met:
|
* modification, are permitted provided that the following conditions are met:
|
||||||
*
|
*
|
||||||
|
|
|
||||||
|
|
@ -57,5 +57,5 @@ extern const pwm_apb_map_t pwm_apb_map_table[];
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -311,13 +311,13 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = {
|
||||||
{PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#1- USART2_CTS_NSS
|
{PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#1- USART2_CTS_NSS
|
||||||
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_MDIO
|
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_MDIO
|
||||||
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX
|
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX
|
||||||
{PA_9_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_TX
|
{PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_TX
|
||||||
{PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to SPI2_SCK
|
{PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to SPI2_SCK
|
||||||
{PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)},
|
{PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)},
|
||||||
{PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)},
|
{PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)},
|
||||||
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to HDMI_CEC
|
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to HDMI_CEC
|
||||||
{PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to HDMI_CEC
|
{PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to HDMI_CEC
|
||||||
{PB_6_ALT1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, // Connected to HDMI_CEC
|
{PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, // Connected to HDMI_CEC
|
||||||
{PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#19_DFSDM-DATA7
|
{PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#19_DFSDM-DATA7
|
||||||
{PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D3
|
{PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D3
|
||||||
{PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D6
|
{PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D6
|
||||||
|
|
@ -343,12 +343,12 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = {
|
||||||
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ULPI_D0
|
{PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ULPI_D0
|
||||||
{PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, // Connected to CEC_CK/MCO1
|
{PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, // Connected to CEC_CK/MCO1
|
||||||
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX
|
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX
|
||||||
{PA_10_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_RX
|
{PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_RX
|
||||||
{PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to PMOD\#1
|
{PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to PMOD\#1
|
||||||
{PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)},
|
{PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)},
|
||||||
{PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D7
|
{PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D7
|
||||||
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||||
{PB_7_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)},
|
{PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)},
|
||||||
{PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#20_DFSDM-CK7
|
{PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#20_DFSDM-CK7
|
||||||
{PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D4
|
{PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D4
|
||||||
{PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D5
|
{PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D5
|
||||||
|
|
@ -373,7 +373,7 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = {
|
||||||
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
|
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
|
||||||
{PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_REF_CLK
|
{PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_REF_CLK
|
||||||
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SPI2_SCK
|
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SPI2_SCK
|
||||||
{PA_12_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to SPI2_SCK
|
{PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to SPI2_SCK
|
||||||
{PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
{PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||||
{PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PMOD\#9
|
{PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PMOD\#9
|
||||||
{PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#9
|
{PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#9
|
||||||
|
|
@ -391,7 +391,7 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = {
|
||||||
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
|
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
|
||||||
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD\#1- USART2_CTS_NSS
|
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD\#1- USART2_CTS_NSS
|
||||||
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to PMOD\#1
|
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to PMOD\#1
|
||||||
{PA_11_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to PMOD\#1
|
{PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to PMOD\#1
|
||||||
{PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ULPI_D1
|
{PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ULPI_D1
|
||||||
{PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D6
|
{PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D6
|
||||||
{PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#8
|
{PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#8
|
||||||
|
|
|
||||||
|
|
@ -57,11 +57,11 @@
|
||||||
#endif /* HSE_VALUE */
|
#endif /* HSE_VALUE */
|
||||||
|
|
||||||
#if !defined (CSI_VALUE)
|
#if !defined (CSI_VALUE)
|
||||||
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
|
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
|
||||||
#endif /* CSI_VALUE */
|
#endif /* CSI_VALUE */
|
||||||
|
|
||||||
#if !defined (HSI_VALUE)
|
#if !defined (HSI_VALUE)
|
||||||
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
|
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
|
||||||
#endif /* HSI_VALUE */
|
#endif /* HSI_VALUE */
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -104,14 +104,14 @@
|
||||||
/** @addtogroup STM32H7xx_System_Private_Variables
|
/** @addtogroup STM32H7xx_System_Private_Variables
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* This variable is updated in three ways:
|
/* This variable is updated in three ways:
|
||||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||||
Note: If you use this function to configure the system clock; then there
|
Note: If you use this function to configure the system clock; then there
|
||||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||||
variable is updated automatically.
|
variable is updated automatically.
|
||||||
*/
|
*/
|
||||||
#if defined(CORE_CM7)
|
#if defined(CORE_CM7)
|
||||||
#define SystemCoreClock SystemD1Clock
|
#define SystemCoreClock SystemD1Clock
|
||||||
#elif defined(CORE_CM4)
|
#elif defined(CORE_CM4)
|
||||||
|
|
@ -119,9 +119,9 @@
|
||||||
#else
|
#else
|
||||||
#error "Wrong core selection"
|
#error "Wrong core selection"
|
||||||
#endif
|
#endif
|
||||||
uint32_t SystemD1Clock = 64000000;
|
uint32_t SystemD1Clock = 64000000;
|
||||||
uint32_t SystemD2Clock = 64000000;
|
uint32_t SystemD2Clock = 64000000;
|
||||||
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
|
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
|
@ -146,95 +146,94 @@
|
||||||
* @param None
|
* @param None
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
void SystemInit (void)
|
void SystemInit(void)
|
||||||
{
|
{
|
||||||
/* FPU settings ------------------------------------------------------------*/
|
/* FPU settings ------------------------------------------------------------*/
|
||||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
|
SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is
|
/*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is
|
||||||
detectable by the CPU after a WFI/WFE instruction.*/
|
detectable by the CPU after a WFI/WFE instruction.*/
|
||||||
SCB->SCR |= SCB_SCR_SEVONPEND_Pos;
|
SCB->SCR |= SCB_SCR_SEVONPEND_Pos;
|
||||||
|
|
||||||
#ifdef CORE_CM7
|
#ifdef CORE_CM7
|
||||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||||
/* Set HSION bit */
|
/* Set HSION bit */
|
||||||
RCC->CR |= RCC_CR_HSION;
|
RCC->CR |= RCC_CR_HSION;
|
||||||
|
|
||||||
/* Reset CFGR register */
|
/* Reset CFGR register */
|
||||||
RCC->CFGR = 0x00000000;
|
RCC->CFGR = 0x00000000;
|
||||||
|
|
||||||
/* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
|
/* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
|
||||||
RCC->CR &= 0xEAF6ED7FU;
|
RCC->CR &= 0xEAF6ED7FU;
|
||||||
|
|
||||||
/* Reset D1CFGR register */
|
/* Reset D1CFGR register */
|
||||||
RCC->D1CFGR = 0x00000000;
|
RCC->D1CFGR = 0x00000000;
|
||||||
|
|
||||||
/* Reset D2CFGR register */
|
/* Reset D2CFGR register */
|
||||||
RCC->D2CFGR = 0x00000000;
|
RCC->D2CFGR = 0x00000000;
|
||||||
|
|
||||||
/* Reset D3CFGR register */
|
/* Reset D3CFGR register */
|
||||||
RCC->D3CFGR = 0x00000000;
|
RCC->D3CFGR = 0x00000000;
|
||||||
|
|
||||||
/* Reset PLLCKSELR register */
|
/* Reset PLLCKSELR register */
|
||||||
RCC->PLLCKSELR = 0x00000000;
|
RCC->PLLCKSELR = 0x00000000;
|
||||||
|
|
||||||
/* Reset PLLCFGR register */
|
/* Reset PLLCFGR register */
|
||||||
RCC->PLLCFGR = 0x00000000;
|
RCC->PLLCFGR = 0x00000000;
|
||||||
/* Reset PLL1DIVR register */
|
/* Reset PLL1DIVR register */
|
||||||
RCC->PLL1DIVR = 0x00000000;
|
RCC->PLL1DIVR = 0x00000000;
|
||||||
/* Reset PLL1FRACR register */
|
/* Reset PLL1FRACR register */
|
||||||
RCC->PLL1FRACR = 0x00000000;
|
RCC->PLL1FRACR = 0x00000000;
|
||||||
|
|
||||||
/* Reset PLL2DIVR register */
|
/* Reset PLL2DIVR register */
|
||||||
RCC->PLL2DIVR = 0x00000000;
|
RCC->PLL2DIVR = 0x00000000;
|
||||||
|
|
||||||
/* Reset PLL2FRACR register */
|
/* Reset PLL2FRACR register */
|
||||||
|
|
||||||
RCC->PLL2FRACR = 0x00000000;
|
RCC->PLL2FRACR = 0x00000000;
|
||||||
/* Reset PLL3DIVR register */
|
/* Reset PLL3DIVR register */
|
||||||
RCC->PLL3DIVR = 0x00000000;
|
RCC->PLL3DIVR = 0x00000000;
|
||||||
|
|
||||||
/* Reset PLL3FRACR register */
|
/* Reset PLL3FRACR register */
|
||||||
RCC->PLL3FRACR = 0x00000000;
|
RCC->PLL3FRACR = 0x00000000;
|
||||||
|
|
||||||
/* Reset HSEBYP bit */
|
/* Reset HSEBYP bit */
|
||||||
RCC->CR &= 0xFFFBFFFFU;
|
RCC->CR &= 0xFFFBFFFFU;
|
||||||
|
|
||||||
/* Disable all interrupts */
|
/* Disable all interrupts */
|
||||||
RCC->CIER = 0x00000000;
|
RCC->CIER = 0x00000000;
|
||||||
|
|
||||||
/* Enable CortexM7 HSEM EXTI line (line 78)*/
|
/* Enable CortexM7 HSEM EXTI line (line 78)*/
|
||||||
EXTI_D2->EMR3 |= 0x4000UL;
|
EXTI_D2->EMR3 |= 0x4000UL;
|
||||||
|
|
||||||
|
|
||||||
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
|
if ((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) {
|
||||||
{
|
/* if stm32h7 revY*/
|
||||||
/* if stm32h7 revY*/
|
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
|
||||||
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
|
*((__IO uint32_t *)0x51008108) = 0x000000001U;
|
||||||
*((__IO uint32_t*)0x51008108) = 0x000000001U;
|
}
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CORE_CM7*/
|
#endif /* CORE_CM7*/
|
||||||
|
|
||||||
#ifdef CORE_CM4
|
#ifdef CORE_CM4
|
||||||
|
|
||||||
/* Configure the Vector Table location add offset address ------------------*/
|
/* Configure the Vector Table location add offset address ------------------*/
|
||||||
#ifdef VECT_TAB_SRAM
|
#ifdef VECT_TAB_SRAM
|
||||||
SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||||
#else
|
#else
|
||||||
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader
|
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#else
|
#else
|
||||||
#ifdef CORE_CM7
|
#ifdef CORE_CM7
|
||||||
|
|
||||||
/* Configure the Vector Table location add offset address ------------------*/
|
/* Configure the Vector Table location add offset address ------------------*/
|
||||||
#ifdef VECT_TAB_SRAM
|
#ifdef VECT_TAB_SRAM
|
||||||
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */
|
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */
|
||||||
#else
|
#else
|
||||||
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader
|
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#else
|
#else
|
||||||
|
|
@ -281,83 +280,78 @@ void SystemInit (void)
|
||||||
* @param None
|
* @param None
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
void SystemCoreClockUpdate (void)
|
void SystemCoreClockUpdate(void)
|
||||||
{
|
{
|
||||||
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
|
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
|
||||||
float_t fracn1, pllvco;
|
float_t fracn1, pllvco;
|
||||||
|
|
||||||
/* Get SYSCLK source -------------------------------------------------------*/
|
/* Get SYSCLK source -------------------------------------------------------*/
|
||||||
|
|
||||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
switch (RCC->CFGR & RCC_CFGR_SWS) {
|
||||||
{
|
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
||||||
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
SystemD1Clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
|
||||||
SystemD1Clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
|
|
||||||
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
|
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
|
||||||
SystemD1Clock = CSI_VALUE;
|
SystemD1Clock = CSI_VALUE;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
||||||
SystemD1Clock = HSE_VALUE;
|
SystemD1Clock = HSE_VALUE;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
|
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
|
||||||
|
|
||||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
||||||
SYSCLK = PLL_VCO / PLLR
|
SYSCLK = PLL_VCO / PLLR
|
||||||
*/
|
*/
|
||||||
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
|
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
|
||||||
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
|
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
|
||||||
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
|
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
|
||||||
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
|
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
|
||||||
|
|
||||||
if (pllm != 0U)
|
if (pllm != 0U) {
|
||||||
{
|
switch (pllsource) {
|
||||||
switch (pllsource)
|
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
|
||||||
{
|
|
||||||
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
|
|
||||||
|
|
||||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)) ;
|
||||||
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
|
||||||
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
|
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
|
||||||
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
|
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
|
||||||
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
|
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
|
||||||
SystemD1Clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
|
SystemD1Clock = (uint32_t)(float_t)(pllvco / (float_t)pllp);
|
||||||
|
} else {
|
||||||
|
SystemD1Clock = 0U;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
SystemD1Clock = CSI_VALUE;
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
else
|
|
||||||
{
|
|
||||||
SystemD1Clock = 0U;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
/* Compute SystemClock frequency --------------------------------------------------*/
|
||||||
SystemD1Clock = CSI_VALUE;
|
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos];
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Compute SystemClock frequency --------------------------------------------------*/
|
/* SystemD1Clock frequency : CM7 CPU frequency */
|
||||||
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
|
SystemD1Clock >>= tmp;
|
||||||
|
|
||||||
/* SystemD1Clock frequency : CM7 CPU frequency */
|
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
|
||||||
SystemD1Clock >>= tmp;
|
SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
|
||||||
|
|
||||||
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
|
|
||||||
SystemD2Clock = (SystemD1Clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -234,15 +234,15 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = {
|
||||||
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTGFS_VBUS
|
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTGFS_VBUS
|
||||||
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to I2C1_SCL
|
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to I2C1_SCL
|
||||||
{PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to USART3_TX
|
{PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to USART3_TX
|
||||||
{PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USART3_RX
|
{PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USART3_RX
|
||||||
{PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_D1
|
{PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_D1
|
||||||
{PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_A1
|
{PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_A1
|
||||||
{PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_D2
|
{PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_D2
|
||||||
{PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to uSD_D2
|
{PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to uSD_D2
|
||||||
{PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to uSD_CLK
|
{PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to uSD_CLK
|
||||||
// {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PSRAM_WE // Connected to the same UART as STDIO_UART_TX
|
// {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PSRAM_WE // Connected to the same UART as STDIO_UART_TX
|
||||||
{PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D13
|
{PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D13
|
||||||
{PG_7, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_15
|
{PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_15
|
||||||
{PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OCTOSPIM_P2_IO6
|
{PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OCTOSPIM_P2_IO6
|
||||||
{NC, NC, 0}
|
{NC, NC, 0}
|
||||||
};
|
};
|
||||||
|
|
@ -273,15 +273,15 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = {
|
||||||
{PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
{PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
{PA_15_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
{PA_15_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
|
||||||
{PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
{PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
|
||||||
{PB_1_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
|
{PB_1_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
|
||||||
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||||
{PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
|
{PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
|
||||||
{PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to DFDATIN1
|
{PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to DFDATIN1
|
||||||
{PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SPI2_MISO
|
{PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SPI2_MISO
|
||||||
{PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_CMD
|
{PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_CMD
|
||||||
{PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PSRAM_OE
|
{PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PSRAM_OE
|
||||||
{PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PSRAM_A17
|
{PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PSRAM_A17
|
||||||
{PG_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
|
{PG_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
|
||||||
{PG_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OCTOSPIM_P2_CS
|
{PG_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OCTOSPIM_P2_CS
|
||||||
{NC, NC, 0}
|
{NC, NC, 0}
|
||||||
};
|
};
|
||||||
|
|
@ -289,16 +289,16 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = {
|
||||||
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
|
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
|
||||||
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_A4
|
{PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_A4
|
||||||
{PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SPI2_CS
|
{PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SPI2_CS
|
||||||
{PA_6_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SPI2_CS
|
{PA_6_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SPI2_CS
|
||||||
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTGFS_DM
|
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTGFS_DM
|
||||||
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||||
{PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SAI1_SDB
|
{PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SAI1_SDB
|
||||||
{PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PSRAM_ADV
|
{PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PSRAM_ADV
|
||||||
{PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SPI2_CLK
|
{PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SPI2_CLK
|
||||||
{PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SPI2_CLK
|
{PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SPI2_CLK
|
||||||
{PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PSRAM_CLK
|
{PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PSRAM_CLK
|
||||||
{PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PSRAM_A16
|
{PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PSRAM_A16
|
||||||
{PG_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to PSRAM_A15
|
{PG_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to PSRAM_A15
|
||||||
{PG_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
{PG_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
|
||||||
{NC, NC, 0}
|
{NC, NC, 0}
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -102,10 +102,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||||
|
|
||||||
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
|
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) {
|
||||||
{
|
|
||||||
return 0; // FAIL
|
return 0; // FAIL
|
||||||
}
|
}
|
||||||
|
|
||||||
// Enable HSE oscillator and activate PLL with HSE as source
|
// Enable HSE oscillator and activate PLL with HSE as source
|
||||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
|
||||||
|
|
|
||||||
|
|
@ -28,7 +28,7 @@ reset_reason_t hal_reset_reason_get(void)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef RCC_FLAG_LPWR1RST
|
#ifdef RCC_FLAG_LPWR1RST
|
||||||
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_LPWR1RST))||(__HAL_RCC_GET_FLAG(RCC_FLAG_LPWR2RST))) {
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_LPWR1RST)) || (__HAL_RCC_GET_FLAG(RCC_FLAG_LPWR2RST))) {
|
||||||
return RESET_REASON_WAKE_LOW_POWER;
|
return RESET_REASON_WAKE_LOW_POWER;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -34,12 +34,12 @@
|
||||||
// and Watchdog_counter_reload_value bits (RL) of Reload_register (IWDG_RLR)
|
// and Watchdog_counter_reload_value bits (RL) of Reload_register (IWDG_RLR)
|
||||||
// to a timeout value [ms].
|
// to a timeout value [ms].
|
||||||
#define PR_RL2UINT64_TIMEOUT_MS(PR_BITS, RL_BITS) \
|
#define PR_RL2UINT64_TIMEOUT_MS(PR_BITS, RL_BITS) \
|
||||||
((PR2PRESCALER_DIV(PR_BITS)) * (RL_BITS) * 1000ULL / (LSI_VALUE))
|
((PR2PRESCALER_DIV(PR_BITS)) * (RL_BITS) * 1000ULL / (LSI_VALUE))
|
||||||
|
|
||||||
// Convert Prescaler_divider bits (PR) of Prescaler_register (IWDG_PR) and a timeout value [ms]
|
// Convert Prescaler_divider bits (PR) of Prescaler_register (IWDG_PR) and a timeout value [ms]
|
||||||
// to Watchdog_counter_reload_value bits (RL) of Reload_register (IWDG_RLR)
|
// to Watchdog_counter_reload_value bits (RL) of Reload_register (IWDG_RLR)
|
||||||
#define PR_TIMEOUT_MS2RL(PR_BITS, TIMEOUT_MS) \
|
#define PR_TIMEOUT_MS2RL(PR_BITS, TIMEOUT_MS) \
|
||||||
(((TIMEOUT_MS) * (LSI_VALUE) / (PR2PRESCALER_DIV(PR_BITS)) + 999UL) / 1000UL)
|
(((TIMEOUT_MS) * (LSI_VALUE) / (PR2PRESCALER_DIV(PR_BITS)) + 999UL) / 1000UL)
|
||||||
|
|
||||||
#define MAX_TIMEOUT_MS_UINT64 PR_RL2UINT64_TIMEOUT_MS(MAX_IWDG_PR, MAX_IWDG_RL)
|
#define MAX_TIMEOUT_MS_UINT64 PR_RL2UINT64_TIMEOUT_MS(MAX_IWDG_PR, MAX_IWDG_RL)
|
||||||
#if (MAX_TIMEOUT_MS_UINT64 > UINT32_MAX)
|
#if (MAX_TIMEOUT_MS_UINT64 > UINT32_MAX)
|
||||||
|
|
@ -51,7 +51,8 @@
|
||||||
#define INVALID_IWDG_PR ((MAX_IWDG_PR) + 1) // Arbitrary value used to mark an invalid PR bits value.
|
#define INVALID_IWDG_PR ((MAX_IWDG_PR) + 1) // Arbitrary value used to mark an invalid PR bits value.
|
||||||
|
|
||||||
// Pick a minimal Prescaler_divider bits (PR) value suitable for given timeout.
|
// Pick a minimal Prescaler_divider bits (PR) value suitable for given timeout.
|
||||||
static uint8_t pick_min_iwdg_pr(const uint32_t timeout_ms) {
|
static uint8_t pick_min_iwdg_pr(const uint32_t timeout_ms)
|
||||||
|
{
|
||||||
for (uint8_t pr = 0; pr <= MAX_IWDG_PR; pr++) {
|
for (uint8_t pr = 0; pr <= MAX_IWDG_PR; pr++) {
|
||||||
// Check that max timeout for given pr is greater than
|
// Check that max timeout for given pr is greater than
|
||||||
// or equal to timeout_ms.
|
// or equal to timeout_ms.
|
||||||
|
|
@ -72,16 +73,15 @@ watchdog_status_t hal_watchdog_init(const watchdog_config_t *config)
|
||||||
}
|
}
|
||||||
const uint32_t rl = PR_TIMEOUT_MS2RL(pr, config->timeout_ms);
|
const uint32_t rl = PR_TIMEOUT_MS2RL(pr, config->timeout_ms);
|
||||||
|
|
||||||
IwdgHandle.Instance = IWDG;
|
IwdgHandle.Instance = IWDG;
|
||||||
|
|
||||||
IwdgHandle.Init.Prescaler = pr;
|
IwdgHandle.Init.Prescaler = pr;
|
||||||
IwdgHandle.Init.Reload = rl;
|
IwdgHandle.Init.Reload = rl;
|
||||||
#if defined IWDG_WINR_WIN
|
#if defined IWDG_WINR_WIN
|
||||||
IwdgHandle.Init.Window = IWDG_WINDOW_DISABLE;
|
IwdgHandle.Init.Window = IWDG_WINDOW_DISABLE;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
if (HAL_IWDG_Init(&IwdgHandle) != HAL_OK)
|
if (HAL_IWDG_Init(&IwdgHandle) != HAL_OK) {
|
||||||
{
|
|
||||||
error("HAL_IWDG_Init error\n");
|
error("HAL_IWDG_Init error\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -123,7 +123,7 @@ watchdog_features_t hal_watchdog_get_platform_features(void)
|
||||||
features.max_timeout = MAX_TIMEOUT_MS;
|
features.max_timeout = MAX_TIMEOUT_MS;
|
||||||
features.update_config = true;
|
features.update_config = true;
|
||||||
features.disable_watchdog = false;
|
features.disable_watchdog = false;
|
||||||
|
|
||||||
/* STM32 IWDG (Independent Watchdog) is clocked by its own dedicated low-speed clock (LSI) */
|
/* STM32 IWDG (Independent Watchdog) is clocked by its own dedicated low-speed clock (LSI) */
|
||||||
features.clock_typical_frequency = LSI_VALUE;
|
features.clock_typical_frequency = LSI_VALUE;
|
||||||
|
|
||||||
|
|
@ -139,7 +139,7 @@ watchdog_features_t hal_watchdog_get_platform_features(void)
|
||||||
#elif defined(STM32H7) || defined(STM32L4) || defined(STM32WB)
|
#elif defined(STM32H7) || defined(STM32L4) || defined(STM32WB)
|
||||||
features.clock_max_frequency = 33600;
|
features.clock_max_frequency = 33600;
|
||||||
#else
|
#else
|
||||||
#error "unsupported target"
|
#error "unsupported target"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
return features;
|
return features;
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue