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PSOC6: update BSP generated sources with latest configurator 

Use ModusToolbox Device Configurator 1.1.0.284 to generate the
BSP low-level initialization code. Compatible version of Device
Configurator to be released with ModusToolbox 1.1.

Notable changes:
* rename cycfg_connectivity -> cycfg_routing
* switch LF_CLK clock source from ILO to WCO on
  CY8CPROTO-062-4343W and CYW943012P6EVB-01
pull/9762/head
Volodymyr Medvid 2019-02-15 19:48:29 +02:00
parent cefc7452c9
commit 06354bf48e
37 changed files with 98 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.c
View File

@ -30,5 +30,5 @@ void init_cycfg_all(void)
init_cycfg_peripherals(); init_cycfg_peripherals();
init_cycfg_pins(); init_cycfg_pins();
init_cycfg_platform(); init_cycfg_platform();
init_cycfg_connectivity(); init_cycfg_routing();
} }

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg.h
View File

@ -34,7 +34,7 @@ extern "C" {
#include "cycfg_peripherals.h" #include "cycfg_peripherals.h"
#include "cycfg_pins.h" #include "cycfg_pins.h"
#include "cycfg_platform.h" #include "cycfg_platform.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
void init_cycfg_all(void); void init_cycfg_all(void);

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_peripherals.h
View File

@ -35,7 +35,7 @@
#include "cy_mcwdt.h" #include "cy_mcwdt.h"
#include "cy_rtc.h" #include "cy_rtc.h"
#include "cy_tcpwm_pwm.h" #include "cy_tcpwm_pwm.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#include "cy_usbfs_dev_drv.h" #include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus) #if defined(__cplusplus)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_pins.h
View File

@ -27,7 +27,7 @@
#include "cycfg_notices.h" #include "cycfg_notices.h"
#include "cy_gpio.h" #include "cy_gpio.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_routing.c
View File

@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* File Name: cycfg_connectivity.c * File Name: cycfg_routing.c
* *
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
@ -22,11 +22,11 @@
* limitations under the License. * limitations under the License.
********************************************************************************/ ********************************************************************************/
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#include "cy_device_headers.h" #include "cy_device_headers.h"
void init_cycfg_connectivity(void) void init_cycfg_routing(void)
{ {
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_connectivity.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/GeneratedSource/cycfg_routing.h
View File

@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* File Name: cycfg_connectivity.h * File Name: cycfg_routing.h
* *
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
@ -22,16 +22,16 @@
* limitations under the License. * limitations under the License.
********************************************************************************/ ********************************************************************************/
#if !defined(CYCFG_CONNECTIVITY_H) #if !defined(CYCFG_ROUTING_H)
#define CYCFG_CONNECTIVITY_H #define CYCFG_ROUTING_H
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {
#endif #endif
#include "cycfg_notices.h" #include "cycfg_notices.h"
void init_cycfg_connectivity(void); void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1 #define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 #define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 #define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
@ -73,4 +73,4 @@ void init_cycfg_connectivity(void);
#endif #endif
#endif /* CYCFG_CONNECTIVITY_H */ #endif /* CYCFG_ROUTING_H */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c
View File

@ -30,5 +30,5 @@ void init_cycfg_all(void)
init_cycfg_peripherals(); init_cycfg_peripherals();
init_cycfg_pins(); init_cycfg_pins();
init_cycfg_platform(); init_cycfg_platform();
init_cycfg_connectivity(); init_cycfg_routing();
} }

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h
View File

@ -34,7 +34,7 @@ extern "C" {
#include "cycfg_peripherals.h" #include "cycfg_peripherals.h"
#include "cycfg_pins.h" #include "cycfg_pins.h"
#include "cycfg_platform.h" #include "cycfg_platform.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
void init_cycfg_all(void); void init_cycfg_all(void);

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h
View File

@ -27,7 +27,7 @@
#include "cycfg_notices.h" #include "cycfg_notices.h"
#include "cy_gpio.h" #include "cy_gpio.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c
View File

@ -119,7 +119,7 @@ __STATIC_INLINE void Cy_SysClk_IloInit()
__STATIC_INLINE void Cy_SysClk_ClkLfInit() __STATIC_INLINE void Cy_SysClk_ClkLfInit()
{ {
/* The WDT is unlocked in the default startup code */ /* The WDT is unlocked in the default startup code */
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
} }
__STATIC_INLINE void Cy_SysClk_ClkPath0Init() __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
{ {

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h
View File

@ -35,7 +35,7 @@
extern "C" { extern "C" {
#endif #endif
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_PWR_VDDA_MV 3300 #define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300 #define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300 #define CY_CFG_PWR_VBACKUP_MV 3300

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.c
View File

@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* File Name: cycfg_connectivity.c * File Name: cycfg_routing.c
* *
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
@ -22,11 +22,11 @@
* limitations under the License. * limitations under the License.
********************************************************************************/ ********************************************************************************/
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#include "cy_device_headers.h" #include "cy_device_headers.h"
void init_cycfg_connectivity(void) void init_cycfg_routing(void)
{ {
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |

34
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_connectivity.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h
View File

@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* File Name: cycfg_connectivity.h * File Name: cycfg_routing.h
* *
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
@ -22,43 +22,43 @@
* limitations under the License. * limitations under the License.
********************************************************************************/ ********************************************************************************/
#if !defined(CYCFG_CONNECTIVITY_H) #if !defined(CYCFG_ROUTING_H)
#define CYCFG_CONNECTIVITY_H #define CYCFG_ROUTING_H
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {
#endif #endif
#include "cycfg_notices.h" #include "cycfg_notices.h"
void init_cycfg_connectivity(void); void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 #define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 #define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 #define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 #define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 #define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX #define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#if defined(__cplusplus) #if defined(__cplusplus)
} }
#endif #endif
#endif /* CYCFG_CONNECTIVITY_H */ #endif /* CYCFG_ROUTING_H */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c
View File

@ -30,5 +30,5 @@ void init_cycfg_all(void)
init_cycfg_peripherals(); init_cycfg_peripherals();
init_cycfg_pins(); init_cycfg_pins();
init_cycfg_platform(); init_cycfg_platform();
init_cycfg_connectivity(); init_cycfg_routing();
} }

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h
View File

@ -35,7 +35,7 @@ extern "C" {
#include "cycfg_peripherals.h" #include "cycfg_peripherals.h"
#include "cycfg_pins.h" #include "cycfg_pins.h"
#include "cycfg_platform.h" #include "cycfg_platform.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
void init_cycfg_all(void); void init_cycfg_all(void);

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h
View File

@ -34,7 +34,7 @@
#include "cy_mcwdt.h" #include "cy_mcwdt.h"
#include "cy_rtc.h" #include "cy_rtc.h"
#include "cy_tcpwm_pwm.h" #include "cy_tcpwm_pwm.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#include "cy_usbfs_dev_drv.h" #include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus) #if defined(__cplusplus)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h
View File

@ -27,7 +27,7 @@
#include "cycfg_notices.h" #include "cycfg_notices.h"
#include "cy_gpio.h" #include "cy_gpio.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c
View File

@ -152,7 +152,7 @@ __STATIC_INLINE void Cy_SysClk_IloInit()
__STATIC_INLINE void Cy_SysClk_ClkLfInit() __STATIC_INLINE void Cy_SysClk_ClkLfInit()
{ {
/* The WDT is unlocked in the default startup code */ /* The WDT is unlocked in the default startup code */
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
} }
__STATIC_INLINE void Cy_SysClk_ClkPath0Init() __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
{ {

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h
View File

@ -35,7 +35,7 @@
extern "C" { extern "C" {
#endif #endif
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_PWR_VDDA_MV 3300 #define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300 #define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300 #define CY_CFG_PWR_VBACKUP_MV 3300

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c
View File

@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* File Name: cycfg_connectivity.c * File Name: cycfg_routing.c
* *
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
@ -22,7 +22,7 @@
* limitations under the License. * limitations under the License.
********************************************************************************/ ********************************************************************************/
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#include "cy_trigmux.h" #include "cy_trigmux.h"
@ -30,16 +30,16 @@
#include "cy_device_headers.h" #include "cy_device_headers.h"
void init_cycfg_connectivity(void) void init_cycfg_routing(void)
{ {
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT47, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT43, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT49, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT4, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT6, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT1, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |

20
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_connectivity.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h
View File

@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* File Name: cycfg_connectivity.h * File Name: cycfg_routing.h
* *
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
@ -22,16 +22,16 @@
* limitations under the License. * limitations under the License.
********************************************************************************/ ********************************************************************************/
#if !defined(CYCFG_CONNECTIVITY_H) #if !defined(CYCFG_ROUTING_H)
#define CYCFG_CONNECTIVITY_H #define CYCFG_ROUTING_H
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {
#endif #endif
#include "cycfg_notices.h" #include "cycfg_notices.h"
void init_cycfg_connectivity(void); void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1 #define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 #define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 #define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
@ -73,17 +73,17 @@ void init_cycfg_connectivity(void);
#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1 #define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3 #define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
#define udb_0_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0 #define udb_0_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
#define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT4 #define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT1
#define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3 #define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT4
#define udb_0_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1 #define udb_0_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
#define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT0 #define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
#define udb_0_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3 #define udb_0_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
#define udb_0_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7 #define udb_0_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
#define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT6 #define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
#if defined(__cplusplus) #if defined(__cplusplus)
} }
#endif #endif
#endif /* CYCFG_CONNECTIVITY_H */ #endif /* CYCFG_ROUTING_H */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c
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@ -30,5 +30,5 @@ void init_cycfg_all(void)
init_cycfg_peripherals(); init_cycfg_peripherals();
init_cycfg_pins(); init_cycfg_pins();
init_cycfg_platform(); init_cycfg_platform();
init_cycfg_connectivity(); init_cycfg_routing();
} }

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h
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@ -34,7 +34,7 @@ extern "C" {
#include "cycfg_peripherals.h" #include "cycfg_peripherals.h"
#include "cycfg_pins.h" #include "cycfg_pins.h"
#include "cycfg_platform.h" #include "cycfg_platform.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
void init_cycfg_all(void); void init_cycfg_all(void);

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h
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@ -35,7 +35,7 @@
#include "cy_mcwdt.h" #include "cy_mcwdt.h"
#include "cy_rtc.h" #include "cy_rtc.h"
#include "cy_tcpwm_pwm.h" #include "cy_tcpwm_pwm.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h
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@ -27,7 +27,7 @@
#include "cycfg_notices.h" #include "cycfg_notices.h"
#include "cy_gpio.h" #include "cy_gpio.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {

14
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c
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@ -86,7 +86,7 @@ __WEAK void cycfg_ClockStartupError(uint32_t error)
} }
__STATIC_INLINE void Cy_SysClk_ClkBakInit() __STATIC_INLINE void Cy_SysClk_ClkBakInit()
{ {
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
} }
__STATIC_INLINE void Cy_SysClk_ClkFastInit() __STATIC_INLINE void Cy_SysClk_ClkFastInit()
{ {
@ -129,7 +129,7 @@ __STATIC_INLINE void Cy_SysClk_IloInit()
__STATIC_INLINE void Cy_SysClk_ClkLfInit() __STATIC_INLINE void Cy_SysClk_ClkLfInit()
{ {
/* The WDT is unlocked in the default startup code */ /* The WDT is unlocked in the default startup code */
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
} }
__STATIC_INLINE void Cy_SysClk_ClkPath0Init() __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
{ {
@ -175,12 +175,7 @@ void init_cycfg_platform(void)
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL); Cy_SysLib_SetWaitStates(false, 150UL);
#if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD) #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */){ Cy_SysLib_ResetBackupDomain(); }
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#endif #endif
#ifdef CY_CFG_PWR_ENABLED #ifdef CY_CFG_PWR_ENABLED
/* Configure power mode */ /* Configure power mode */
@ -215,9 +210,6 @@ void init_cycfg_platform(void)
Cy_SysClk_FllDisable(); Cy_SysClk_FllDisable();
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
#ifdef CY_IP_MXBLESS
(void)Cy_BLE_EcoReset();
#endif
#ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE
(void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2); (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h
View File

@ -34,7 +34,7 @@
extern "C" { extern "C" {
#endif #endif
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_PWR_VDDA_MV 3300 #define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300 #define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300 #define CY_CFG_PWR_VBACKUP_MV 3300

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.c
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@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* File Name: cycfg_connectivity.c * File Name: cycfg_routing.c
* *
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
@ -22,11 +22,11 @@
* limitations under the License. * limitations under the License.
********************************************************************************/ ********************************************************************************/
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#include "cy_device_headers.h" #include "cy_device_headers.h"
void init_cycfg_connectivity(void) void init_cycfg_routing(void)
{ {
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_connectivity.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h
View File

@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* File Name: cycfg_connectivity.h * File Name: cycfg_routing.h
* *
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
@ -22,16 +22,16 @@
* limitations under the License. * limitations under the License.
********************************************************************************/ ********************************************************************************/
#if !defined(CYCFG_CONNECTIVITY_H) #if !defined(CYCFG_ROUTING_H)
#define CYCFG_CONNECTIVITY_H #define CYCFG_ROUTING_H
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {
#endif #endif
#include "cycfg_notices.h" #include "cycfg_notices.h"
void init_cycfg_connectivity(void); void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM0_LINE_COMPL1 #define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM0_LINE_COMPL1
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 #define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 #define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
@ -72,4 +72,4 @@ void init_cycfg_connectivity(void);
#endif #endif
#endif /* CYCFG_CONNECTIVITY_H */ #endif /* CYCFG_ROUTING_H */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c
View File

@ -30,5 +30,5 @@ void init_cycfg_all(void)
init_cycfg_peripherals(); init_cycfg_peripherals();
init_cycfg_pins(); init_cycfg_pins();
init_cycfg_platform(); init_cycfg_platform();
init_cycfg_connectivity(); init_cycfg_routing();
} }

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h
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@ -35,7 +35,7 @@ extern "C" {
#include "cycfg_peripherals.h" #include "cycfg_peripherals.h"
#include "cycfg_pins.h" #include "cycfg_pins.h"
#include "cycfg_platform.h" #include "cycfg_platform.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
void init_cycfg_all(void); void init_cycfg_all(void);

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h
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@ -34,7 +34,7 @@
#include "cy_mcwdt.h" #include "cy_mcwdt.h"
#include "cy_rtc.h" #include "cy_rtc.h"
#include "cy_tcpwm_pwm.h" #include "cy_tcpwm_pwm.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#include "cy_usbfs_dev_drv.h" #include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus) #if defined(__cplusplus)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h
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@ -27,7 +27,7 @@
#include "cycfg_notices.h" #include "cycfg_notices.h"
#include "cy_gpio.h" #include "cy_gpio.h"
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c
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@ -104,7 +104,7 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
} }
__STATIC_INLINE void Cy_SysClk_ClkBakInit() __STATIC_INLINE void Cy_SysClk_ClkBakInit()
{ {
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
} }
__STATIC_INLINE void Cy_SysClk_EcoInit() __STATIC_INLINE void Cy_SysClk_EcoInit()
{ {
@ -166,7 +166,7 @@ __STATIC_INLINE void Cy_SysClk_IloInit()
__STATIC_INLINE void Cy_SysClk_ClkLfInit() __STATIC_INLINE void Cy_SysClk_ClkLfInit()
{ {
/* The WDT is unlocked in the default startup code */ /* The WDT is unlocked in the default startup code */
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
} }
__STATIC_INLINE void Cy_SysClk_ClkPath0Init() __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
{ {

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h
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@ -35,7 +35,7 @@
extern "C" { extern "C" {
#endif #endif
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_PWR_VDDA_MV 3300 #define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300 #define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300 #define CY_CFG_PWR_VBACKUP_MV 3300

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.c → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c
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@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* File Name: cycfg_connectivity.c * File Name: cycfg_routing.c
* *
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
@ -22,7 +22,7 @@
* limitations under the License. * limitations under the License.
********************************************************************************/ ********************************************************************************/
#include "cycfg_connectivity.h" #include "cycfg_routing.h"
#include "cy_trigmux.h" #include "cy_trigmux.h"
@ -30,7 +30,7 @@
#include "cy_device_headers.h" #include "cy_device_headers.h"
void init_cycfg_connectivity(void) void init_cycfg_routing(void)
{ {
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT5, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT5, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_connectivity.h → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h
View File

@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* File Name: cycfg_connectivity.h * File Name: cycfg_routing.h
* *
* Description: * Description:
* Establishes all necessary connections between hardware elements. * Establishes all necessary connections between hardware elements.
@ -22,16 +22,16 @@
* limitations under the License. * limitations under the License.
********************************************************************************/ ********************************************************************************/
#if !defined(CYCFG_CONNECTIVITY_H) #if !defined(CYCFG_ROUTING_H)
#define CYCFG_CONNECTIVITY_H #define CYCFG_ROUTING_H
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {
#endif #endif
#include "cycfg_notices.h" #include "cycfg_notices.h"
void init_cycfg_connectivity(void); void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 #define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 #define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 #define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
@ -90,4 +90,4 @@ void init_cycfg_connectivity(void);
#endif #endif
#endif /* CYCFG_CONNECTIVITY_H */ #endif /* CYCFG_ROUTING_H */